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2020-10-27drm/amd/pm: correct Polaris DIDT configurationsEvan Quan2-2/+34
Correct Polaris DIDT enablement. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: correct Polaris powertune table setupEvan Quan3-1/+85
Correct powertune table setup for Polaris. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: correct the checks for sclk/mclk SS supportEvan Quan4-1/+26
Correct sclk/mclk SS support checks. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: correct VR shared rail infoEvan Quan5-2/+34
Add VR shared rail info. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: add mc register table initializationEvan Quan4-0/+58
Add mc register table initialization. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: add edc leakage controller settingEvan Quan6-0/+252
Enable edc controller table setting. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: setup zero rpm parameters for polaris10Evan Quan3-0/+29
Only if the ZeroRPM feature is supported. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: correct polaris10 clock stretcher data table settingEvan Quan1-31/+11
By using the saved copy of ro_range_maximum and ro_range_minimum. Correct the setting for "LdoRefSel". Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: correct the settings for ro range minimum and maximumEvan Quan2-0/+65
Make the settings more precise. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: drop redundant efuse mask calculationsEvan Quan4-6/+10
By moving that in atomfw_read_efuse(). Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: optimize AC timing programmingEvan Quan1-1/+1
Programming AC Timing Parameters is only dependent on MCLK. No need to nest loop for each SCLK DPM level. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/powerplay: separate Polaris fan table setup from TongaEvan Quan2-1/+87
Instead of sharing the fan table setup with Tonga, Polaris has its own fan table setup. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: add PWR_CKS_CNTL settingEvan Quan1-4/+11
This is for some special Polaris10 ASICs. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amdgpu: correct CG_ACLK_CNTL settingEvan Quan1-3/+11
Correct polaris CG_ACLK_CNTL setting. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: drop arb table first byte workaroundEvan Quan1-31/+0
As this is not needed for polaris. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: add pptable VRHotLevel settingEvan Quan1-0/+3
Add missing VRHotLevel setting. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: correct the BootLinkLevel setupEvan Quan1-1/+1
Set the BootLinkLevel as the max level. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: correct the ACPI table setup V2Evan Quan1-1/+2
Correct the setting for "ActivityLevel". V2: rich the comment Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: correct mclk table setupEvan Quan1-12/+8
Correct the settings for "StutterEnable" and "EnabledForActivity". Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: correct sclk table setupEvan Quan1-2/+21
Correct Polaris10 sclk table setup. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: correct vddci table setupEvan Quan1-2/+2
Make sure the settings are applied only when voltage controlled by gpio. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: populate smc samu tableEvan Quan1-0/+53
Add missing smc samu table setup. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: populate smc vddc tableEvan Quan1-0/+26
Add missing vddc table setup. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-27drm/amd/pm: correct the checks for polaris kickersEvan Quan3-49/+48
By defining new Macros. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amd/display: Clean up debug macrosTakashi Iwai2-21/+13
This patch simplifies the ASSERT*() and BREAK_TO_DEBUGGER() macros: - Move the dependency check of CONFIG_KGDB into Kconfig - Unify the kgdb_breakpoint() call - Drop the non-existing CONFIG_HAVE_KGDB Also align the behavior of ASSERT() macro in both cases with and without CONFIG_DEBUG_KERNEL_DC. Acked-by: Alex Deucher <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Takashi Iwai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amd/display: Don't invoke kgdb_breakpoint() unconditionallyTakashi Iwai1-1/+1
ASSERT_CRITICAL() invokes kgdb_breakpoint() whenever either CONFIG_KGDB or CONFIG_HAVE_KGDB is set. This, however, may lead to a kernel panic when no kdb stuff is attached, since the kgdb_breakpoint() call issues INT3. It's nothing but a surprise for normal end-users. For avoiding the pitfall, make the kgdb_breakpoint() call only when CONFIG_DEBUG_KERNEL_DC is set. https://bugzilla.opensuse.org/show_bug.cgi?id=1177973 Cc: <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Takashi Iwai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amd/display: Fix kernel panic by dal_gpio_open() errorTakashi Iwai1-2/+2
Currently both error code paths handled in dal_gpio_open_ex() issues ASSERT_CRITICAL(), and this leads to a kernel panic unnecessarily if CONFIG_KGDB is enabled. Since basically both are non-critical errors and can be recovered, drop those assert calls and use a safer one, BREAK_TO_DEBUGGER(), for allowing the debugging, instead. BugLink: https://bugzilla.opensuse.org/show_bug.cgi?id=1177973 Cc: <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Takashi Iwai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amdgpu: use true and false for bool initialisationsSumera Priyadarsini1-1/+1
Bool initialisation should use 'true' and 'false' values instead of 0 and 1. Modify amdgpu_amdkfd_gpuvm.c to initialise variable is_imported to false instead of 0. Issue found with Coccinelle. Signed-off-by: Sumera Priyadarsini <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amdgpu: Discard unnecessary breaksZhang Qilong3-17/+0
The 'break' is unnecessary because of previous 'return', discard it. Signed-off-by: Zhang Qilong <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amdgpu/display: use kvzalloc again in dc_create_stateAlex Deucher1-2/+2
It looks this was accidently lost in a follow up patch. dc context is large and we don't need contiguous pages. Fixes: e4863f118a7d ("drm/amd/display: Multi display cause system lag on mode change") Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: Aric Cyr <[email protected]> Cc: Alex Xu <[email protected]> Reported-by: Alex Xu (Hello71) <[email protected]> Tested-by: Alex Xu (Hello71) <[email protected]>
2020-10-26drm/amd/display: combined user regamma and OS GAMMA_CS_TFM_1DDerek Lai2-4/+14
[Why] For user regamma we're missing this function call to combine user regamma + OS for GAMMA_CS_TFM_1D type. [How] Applied 1D LUT in the mod_color_build_user_regamma. And Set the regamma dirty as updateGamma. Signed-off-by: Derek Lai <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amd/display: Using udelay for specific dongle while edid return deferjinlong zhang3-1/+12
[why] Some platform has a limitation of 2ms for udelay [how] Add 1ms udelay for specific dongle. Signed-off-by: jinlong zhang <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amd/display: Removed unreferenced variables.George Shen2-3/+1
Signed-off-by: George Shen <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amd/display: prevent null pointer accessDmytro Laktyushkin1-5/+7
Prevent null pointer access when checking odm tree. Signed-off-by: Dmytro Laktyushkin <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: <[email protected]>
2020-10-26drm/amd/display: Add tracepoint for capturing clocks stateRodrigo Siqueira3-1/+131
The clock state update is the source of many problems, and capturing this sort of information helps debug. This commit introduces tracepoints for capturing clock values and also add traces in DCE, DCN1, DCN2x, and DCN3. Signed-off-by: Rodrigo Siqueira <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amd/display: Add pipe_state tracepointRodrigo Siqueira4-3/+151
This commit introduces a trace mechanism for struct pipe_ctx by adding a middle layer struct in the amdgpu_dm_trace.h for capturing the most important data from struct pipe_ctx and showing its data via tracepoint. This tracepoint was added to dc.c and dcn10_hw_sequencer, however, it can be added to other DCN architecture. Signed-off-by: Rodrigo Siqueira <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amd/display: Add tracepoint for amdgpu_dmRodrigo Siqueira2-0/+304
Debug amdgpu_dm could be a complicated task, therefore, this commit adds tracepoints in some convenient functions such as plane and connector check inside amdgpu_dm. Signed-off-by: Rodrigo Siqueira <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amd/display: Rework registers tracepointRodrigo Siqueira1-31/+24
amdgpu_dc_rreg and amdgpu_dc_wreg are very similar, for this reason, this commits abstract these two events by using DECLARE_EVENT_CLASS and create an instance of it for each one of these events. Signed-off-by: Rodrigo Siqueira <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amd/display: Decouple amdgpu_dm_trace from serviceRodrigo Siqueira5-65/+61
Our DC currently uses some of the tracepoint function inside a DC header, which means that many other files implicitly include part of the trace function. This situation limits how we can expand this feature for other parts of the driver by generating multiple compilation errors when we try to reuse some of the existing structures. This commit decouples part of the amdgpu_dm_trace from DC core to simplify the trace enlargement in future changes. Signed-off-by: Rodrigo Siqueira <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amd/display: 3.2.108Aric Cyr1-1/+1
Signed-off-by: Aric Cyr <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amd/display: [FW Promotion] Release 0.0.38Anthony Koo1-3/+24
| [Header Changes] | - Add new SCRATCH15 boot option and fw_state member to skip | phy access | - Add new SCRATCH15 boot option and fw_state member to disable | clk gating | - Add defines for AUX return status | - Add defines for HPD events Signed-off-by: Anthony Koo <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amd/display: adding ddc_gpio_vga_reg_list to ddc reg def'nsMartin Leung1-0/+12
why: oem-related ddc read/write fails without these regs how: copy from hw_factory_dcn20.c Signed-off-by: Martin Leung <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amd/display: Fix max brightness pixel accuracyFelipe Clark1-21/+89
[WHY] It was detected in some Freesync HDR tests that displays were not reaching their maximum nominal brightness. [HOW] The Multi-plane combiner (MPC) Output Gamma (OGAM) block builds a discrete Lookup Table (LUT). When the display's maximum brightness falls in between two values, having to be linearly interpolated by the hardware, rounding issues might occur that will cause the display to never reach its maximum brightness. The fix involves doing the calculations backwards, ensuring that the interpolation in the maximum brightness values translates to an output of 1.0. Signed-off-by: Felipe Clark <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amd/display: Don't trigger flip twice when ODM combine in useAric Cyr1-3/+2
[Why] When ODM combine is in use we trigger multiple update events causing issues with variable refresh rate. [How] Only trigger on a single ODM instance. Signed-off-by: Aric Cyr <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amd/display: Update GSL state if leaving immediate flipAlvin Lee9-135/+1
[Why] We should leave GSL if we're not doing immediate flip no matter if we're doing pipe split or not [How] Check for updating GSL state whenever we're not doing immediate flip v2: Squash in build fix (Alex) Signed-off-by: Aric Cyr <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amd/display: disable seamless boot for VSC_SDPYu-Ting Shen1-0/+4
[WHY] VBIOS will not enable VSC_SDP during pre-OS to lead MISC1[6] wasn't matched with driver. [HOW] disabled seamless boot if sink supports VSC_SDP Signed-off-by: Yu-Ting Shen <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amd/display: Reduce height of visual confirm on right side.Yongqiang Sun1-1/+1
[Why] right side visual confirm is too thick due to it is 4 times of left side (16 lines). [How] Change factor from 4 to 2. Signed-off-by: Yongqiang Sun <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amd/display: Revert check for flip pending before locking pipesIsabel Zhang4-88/+83
[Why] Causes underflow regression [How] This reverts commit 99d1437aa0ac1f598e9aabca8bf0e8a40c38f8a1 Signed-off-by: Isabel Zhang <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amd/display: skip avmute actionBrandon Syu2-2/+4
[Why] For some monitors, they can't display under BIOS with avmute enabled. [How] Add monitor patch for skip avmute action. Signed-off-by: Brandon Syu <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amd/display: Refactor ABM_MASK_SH_LIST_DCN301 namingRoman Li4-8/+8
[Why] All DCN3x resources share ABM_MASK_SH_LIST_DCN301 definition. The naming is misleading since it looks like DCN30 code depends on next version DCN301, which in fact is vice-versa. [How] Refactor the naming to ABM_MASK_SH_LIST_DCN30. v2: squash in build fixes (Alex) Signed-off-by: Roman Li <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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