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2018-07-13drm/amd/display: add additional info for cursor position programmingDmytro Laktyushkin5-12/+15
Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-13drm/amd/display: drop unused register definesDmytro Laktyushkin1-6/+2
Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-13drm/amd/display: remove dentist_vco_freq from resource_poolDmytro Laktyushkin1-1/+0
Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-13drm/amd/display: hook dp test pattern through debugfsHersen Wu1-11/+211
set PHY layer or Link layer test pattern PHY test pattern is used for PHY SI check. Link layer test will not affect PHY SI. - normal video mode 0 = DP_TEST_PATTERN_VIDEO_MODE - PHY test pattern supported 1 = DP_TEST_PATTERN_D102 2 = DP_TEST_PATTERN_SYMBOL_ERROR 3 = DP_TEST_PATTERN_PRBS7 4 = DP_TEST_PATTERN_80BIT_CUSTOM 5 = DP_TEST_PATTERN_CP2520_1 6 = DP_TEST_PATTERN_CP2520_2 = DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE 7 = DP_TEST_PATTERN_CP2520_3 - DP PHY Link Training Patterns 8 = DP_TEST_PATTERN_TRAINING_PATTERN1 9 = DP_TEST_PATTERN_TRAINING_PATTERN2 0xa = DP_TEST_PATTERN_TRAINING_PATTERN3 0xb = DP_TEST_PATTERN_TRAINING_PATTERN4 - DP Link Layer Test pattern 0xc = DP_TEST_PATTERN_COLOR_SQUARES 0xd = DP_TEST_PATTERN_COLOR_SQUARES_CEA 0xe = DP_TEST_PATTERN_VERTICAL_BARS 0xf = DP_TEST_PATTERN_HORIZONTAL_BARS 0x10= DP_TEST_PATTERN_COLOR_RAMP debugfs phy_test_pattern is located at /syskernel/debug/dri/0/DP-x --- set test pattern echo <test pattern #> > test_pattern - custom test pattern If test pattern # is not supported, NO HW programming will be done for DP_TEST_PATTERN_80BIT_CUSTOM, it needs extra 10 bytes of data for the user pattern. input 10 bytes data are separated by space echo 0x4 0x11 0x22 0x33 0x44 0x55 0x66 0x77 0x88 0x99 0xaa > test_pattern --- reset test pattern echo 0 > test_pattern --- HPD detection is disabled when set PHY test pattern when PHY test pattern (pattern # within [1,7]) is set, HPD pin of HW ASIC is disable. User could unplug DP display from DP connected and plug scope to check test pattern PHY SI. If there is need unplug scope and plug DP display back, do steps below: echo 0 > phy_test_pattern unplug scope plug DP display. "echo 0 > phy_test_pattern" will re-enable HPD pin again so that video sw driver could detect "unplug scope" and "plug DP display" Signed-off-by: Hersen Wu <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-13drm/amd/display: dcc always on for bw calculations on ravenDmytro Laktyushkin1-1/+18
Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-13drm/amd/display: read DP sink and DP branch hardware and firmware revision ↵Alvin lee3-0/+33
from DPCD - define new dpcd address in drm - implement new members in dpcd_caps to store values read from new dpcd address Signed-off-by: Alvin lee <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-13drm/amd/display: Convert remaining loggers off dc_loggerNicholas Kazlauskas14-713/+99
- Removed dal/dm/dc loggers from linux, switched to kernel prints - Modified functions that used these directly to use macros - dc_logger support is completely dropped from Linux Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-13drm/amd/display: Return aux replies directly to DRMHarry Wentland3-114/+117
Currently we still go through DC code that does error checking, retries, etc. There's no need for that since DRM already does that for us. This simplifies the code a bit and makes it easier to debug. This also ensures we correctly tell DRM how many bytes have actually been read, as we should. This allows DRM to correctly read the EDID on the Chamelium DP port. Signed-off-by: Harry Wentland <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-13drm/amd/display: Break out function to simply read aux replyHarry Wentland2-49/+76
DRM's DP helpers take care of dealing with the error code for us. In order not to step on each other's toes we'll need to be able to simply read auch channel replies without further logic based on return values. Signed-off-by: Harry Wentland <[email protected]> Reviewed-by: Sun peng Li <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-13drm/amd/display: Serialize is_dp_sink_presentHarry Wentland4-2/+23
Access to GPIO needs to be serialized. Aux transactions are already serialized in DRM but we also need to serialize access to the GPIO pin for purposes of DP dongle detection. Call is_dp_sink_present through DM so we can lock correctly. This follows the same pattern used for DPCD transactions. Signed-off-by: Harry Wentland <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-13drm/amd/display: Expose configure_encoder for link_encoderTony Cheng2-2/+5
Signed-off-by: Tony Cheng <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-13drm/amd/display: Define couple extra DCN registersCharlene Liu2-2/+8
Signed-off-by: Charlene Liu <[email protected]> Reviewed-by: Dmytro Laktyushkin <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-13drm/amd/display: Add Azalia registers to HW sequencerEric Bernstein1-1/+4
Signed-off-by: Eric Bernstein <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-13drm/amd/display: Correct calculation of duration time.Hugo Hu1-2/+2
Signed-off-by: Hugo Hu <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-13drm/amd/display: dal 3.1.53Tony Cheng1-1/+1
Signed-off-by: Tony Cheng <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-13drm/amd/display: set-read link rate and lane count through debugfsHersen Wu1-31/+196
function description get/ set DP configuration: lane_count, link_rate, spread_spectrum valid lane count value: 1, 2, 4 valid link rate value: 06h = 1.62Gbps per lane 0Ah = 2.7Gbps per lane 0Ch = 3.24Gbps per lane 14h = 5.4Gbps per lane 1Eh = 8.1Gbps per lane debugfs is located at /sys/kernel/debug/dri/0/DP-x/link_settings --- to get dp configuration xxd -l 300 phy_settings It will list current, verified, reported, preferred dp configuration. current -- for current video mode verified --- maximum configuration which pass link training reported --- DP rx report caps (DPCD register offset 0, 1 2) preferred --- user force settings --- set (or force) dp configuration echo <lane_count> <link_rate> for example, to force to 2 lane, 2.7GHz, echo 4 0xa > link_settings spread_spectrum could not be changed dynamically. in case invalid lane count, link rate are force, no hw programming will be done. please check link settings after force operation to see if HW get programming. xxd -l 300 link_settings check current and preferred settings. Signed-off-by: Hersen Wu <[email protected]> Reviewed-by: Hersen Wu <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-13drm/amd/display: fix incorrect check for atom table sizeTony Cheng1-1/+1
in case we have very few pins in the table, check fails and we can't boot Signed-off-by: Tony Cheng <[email protected]> Reviewed-by: Yongqiang Sun <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-13drm/amd/display: generic indirect register accessTony Cheng2-0/+97
add generic indirect register access following our register access pattern this will make it easier to review code and programming sequence, with all the complexity hidden in macro Signed-off-by: Tony Cheng <[email protected]> Reviewed-by: Yongqiang Sun <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-13drm/amd/display: fix bug where we are creating bogus i2c auxTony Cheng6-2/+9
[WHY] we were using 6 instances based on i2caux_dce110.c [HOW] pass in how many instances to ctor Signed-off-by: Tony Cheng <[email protected]> Reviewed-by: Yongqiang Sun <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-13drm/amd/display: Move common GPIO registers into a common defineCharlene Liu1-2/+5
Signed-off-by: Charlene Liu <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-13drm/amd/display: Linux Set/Read link rate and lane count through debugfsHersen Wu2-0/+82
expose dc function to be called by linux dm Signed-off-by: Hersen Wu <[email protected]> Reviewed-by: Sun peng Li <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-13drm/amd/display: Implement cursor multiplierKrunoslav Kovac3-4/+24
DCN allows cursor multiplier when blending FP16 surface. Signed-off-by: Krunoslav Kovac <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-13drm/amd/display: support access ddc for mst branchEric Yang1-0/+4
[Why] Megachip dockings accesses ddc line through display driver when installing FW. Previously, we would fail every transaction because link attached to mst branch did not have their ddc transaction type set. [How] Set ddc transaction type when mst branch is connected. Signed-off-by: Eric Yang <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-13drm/amd/display: Add avoid_vbios_exec_table debug bitTony Cheng1-0/+1
Signed-off-by: Tony Cheng <[email protected]> Reviewed-by: Yongqiang Sun <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-13drm/amd/display: Separate HUBP surface size and rotation/mirror programmingEric Bernstein2-13/+23
Separate HUBP surface size and rotation/mirror programming so that HUBP revision without mirror/rotation do not access those register fields. Signed-off-by: Eric Bernstein <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-13Revert "drm/amd/display: make dm_dp_aux_transfer return payload bytes ↵Harry Wentland5-13/+21
instead of size" This reverts commit cc195141133ac3e767d930bedd8294ceebf1f10b. This commit was problematic on other OSes. The real solution is to leave all the error checking to DRM and don't do it in DC, which is addressed by "Return aux replies directly to DRM" later in this patchset. v2: Add reason for revert. Signed-off-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-13Revert "drm/amd/display: Don't return ddc result and read_bytes in same ↵Harry Wentland3-22/+13
return value" This reverts commit 8a61bc085ffab3071c59efcbeff4044c034e7490. Need to revert "make dm_dp_aux_transfer return payload bytes instead of size", which this commit is based on. That commit was problematic on other OSes. The real solution is to leave all the error checking to DRM and don't do it in DC, which is addressed by "Return aux replies directly to DRM" later in this patchset. v2: Add reason for revert. Signed-off-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-13drm/amdgpu: Warn and update pin_size values when destroying a pinned BOMichel Dänzer1-7/+25
This shouldn't happen, but if it does, we'll get a backtrace of the caller, and update the pin_size values as needed. v2: * Check bo->pin_count instead of placement flags (Christian König) Reviewed-by: Christian König <[email protected]> Signed-off-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-13drm/amdgpu: Make pin_size values atomicMichel Dänzer4-21/+23
Concurrent execution of the non-atomic arithmetic could result in completely bogus values. v2: * Rebased on v2 of the previous patch Cc: [email protected] Bugzilla: https://bugs.freedesktop.org/106872 Reviewed-by: Christian König <[email protected]> Signed-off-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-13drm/amdgpu: Keep track of amount of pinned CPU visible VRAMMichel Dänzer5-19/+14
Instead of CPU invisible VRAM. Preparation for the following, no functional change intended. v2: * Also change amdgpu_vram_mgr_bo_invisible_size to amdgpu_vram_mgr_bo_visible_size, allowing further simplification (Christian König) Cc: [email protected] Reviewed-by: Christian König <[email protected]> Signed-off-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-13drm/scheduler: modify args of drm_sched_entity_initNayan Deshmukh11-33/+33
replace run queue by a list of run queues and remove the sched arg as that is part of run queue itself Signed-off-by: Nayan Deshmukh <[email protected]> Reviewed-by: Christian König <[email protected]> Acked-by: Eric Anholt <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-13drm/scheduler: add a pointer to scheduler in the rqNayan Deshmukh2-2/+6
This patch is in preparation for a better load balancing in scheduler. It allows us to associate entities with the run queues instead of binding them to a scheduler. Signed-off-by: Nayan Deshmukh <[email protected]> Reviewed-by: Christian König <[email protected]> Acked-by: Eric Anholt <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-13drm/amdgpu: fix TTM move entity init orderChristian König1-16/+21
We are initializing the entity before the scheduler is actually initialized. This can lead to all kind of problem, but especially NULL pointer deref because of Nayan's scheduler work. Signed-off-by: Christian König <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-13drm/amd: Use newly added interrupt source defs for SOC15.Andrey Grodzovsky7-15/+29
Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-13drm/amd: Add interrupt source definitions for SOC15 v3.Andrey Grodzovsky9-0/+359
Stop using 'magic numbers' when registering interrupt sources. v2: Switch to kernel style comments. v3: Rebase. Signed-off-by: Andrey Grodzovsky <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-13drm/amd: Use newly added interrupt source defs for VI v3.Andrey Grodzovsky12-26/+46
v2: Rebase v3: Use defines for CP_SQ and CP_ECC_ERROR interrupts. Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-13drm/amd: Add interrupt source definitions for VI v3.Andrey Grodzovsky1-0/+98
Stop using 'magic numbers' when registering interrupt sources. v2: Clean redundant comments. Switch to kernel style comments. v3: Add CP_ECC_ERROR define Signed-off-by: Andrey Grodzovsky <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-13drm/amd/powerplay: convert the sclk/mclk into Mhz for comparationEvan Quan1-2/+2
Convert the clocks into right Mhz unit. Otherwise, it will miss the equal situation. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-13drm/amd/powerplay: no need to mask workable gfxoff feature for vega12Evan Quan1-1/+1
Gfxoff feature for vega12 is workable. So, there is no need to mask it any more. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-13drm/amd/powerplay: add vega12 SMU gfxoff support v3Evan Quan3-0/+46
Export apis for enabling/disabling SMU gfxoff support. v2: fit the latest gfxoff support framework v3: add feature_mask control Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Huang Rui <ray.huang at amd.com> Signed-off-by: Alex Deucher <[email protected]>
2018-07-13drm/amdgpu: reduce the idle period that RLC has to wait before request CGCGEvan Quan1-4/+7
Gfxoff feature may depends on the CGCG(on vega12, that's the case). This change will help to enable gfxoff feature more frequently. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-13drm/amdgpu: no touch for the reserved bit of RLC_CGTT_MGCG_OVERRIDEEvan Quan1-4/+11
On vega12, the bit0 of RLC_CGTT_MGCG_OVERRIDE is reserved. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-13drm/amdgpu: drop mmRLC_PG_CNTL clear v2Evan Quan1-3/+0
SMU owns this register so the driver should not set it to avoid breaking gfxoff. v2: update description Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <alexander.deucher at amd.com> Reviewed-by: Huang Rui <ray.huang at amd.com> Signed-off-by: Alex Deucher <[email protected]>
2018-07-13drm/amdgpu: correct rlc save restore list initialization for v2_1Evan Quan1-6/+12
The save restore list initialization does not have to be pg guarded. And for some asic(e.g. Vega12), it does not have cntl/gpm/srm lists. Signed-off-by: Evan Quan <[email protected]> Acked-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-13drm/amdgpu: init CSIB regardless of rlc version and pg statusEvan Quan1-1/+2
CSIB init has no relation with rlc version and pg status. It should be needed regardless of them. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-13drm/amdgpu: pin the csb buffer on hw init v2Evan Quan1-0/+40
Without this pin, the csb buffer will be filled with inconsistent data after S3 resume. And that will causes gfx hang on gfxoff exit since this csb will be executed then. v2: fit amdgpu_bo_pin change(take one less argument) Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-10drm/amd/pp: fix semicolon.cocci warningskbuild test robot1-1/+1
drivers/gpu/drm/amd/amdgpu/../powerplay/amd_powerplay.c:1209:17-18: Unneeded semicolon Remove unneeded semicolon. Generated by: scripts/coccinelle/misc/semicolon.cocci Fixes: ea870e44415a ("drm/amd/pp: Export notify_smu_enable_pwe to display") CC: Rex Zhu <[email protected]> Signed-off-by: kbuild test robot <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-10drm/amdgpu: get VCN start to process in the dpm disabled caseLeo Liu1-1/+1
Fixes: 22cc6c5e19 (drm/amdgpu: Add runtime VCN PG support) Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-10drm/amdgpu: move cache window setup after power and clock resumeLeo Liu1-2/+2
To make register read/write reliable Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-10drm/amdgpu: Take VCN jpeg ring into account in idle work handlerLeo Liu1-0/+2
VCN won't get power off when only jpeg active Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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