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2024-06-14drm/amdgpu: refine gfx7 firmware loadingYang Wang1-14/+13
refine gfx7 firmware loading Signed-off-by: Yang Wang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: added NULL check at start of dc_validate_streamwinstang1-0/+3
[Why] prevent invalid memory access [How] check if dc and stream are NULL Co-authored-by: winstang <[email protected]> Reviewed-by: Alvin Lee <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: winstang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amdkfd: Extend gfx12 trap handler fix to gfx10/11Jay Cornwall2-16/+38
In commit fda812ebe3d9 ("drm/amdkfd: gfx12 context save/restore trap handler fixes") the following fix was introduced but incorrectly restricted to gfx12. The same issue and a corresponding fix apply to gfx10 and gfx11. Do not overwrite TRAPSTS.{SAVECTX,HOST_TRAP} when restoring this register. Both of these fields can assert while the wavefront is running the trap handler. Signed-off-by: Jay Cornwall <[email protected]> Reviewed-by: Lancelot Six <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: [FW Promotion] Release 0.0.220.0Anthony Koo1-12/+14
- Change ordering of structs to put enums together - Add new define DMUB_TRACE_ENTRY_DEFINED to guard the trace code enum Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Anthony Koo <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Add sequential ONO sequencing for DCN35Nicholas Kazlauskas3-15/+75
[Why] Adds support for performing the sequential ONO changes from DCN351 into DCN35 ASIC based on revision. [How] Check the revision and run the DCN351 sequences on applicable revisions. Reviewed-by: Sung joon Kim <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Ignore phantom DTBCLK requirementAlvin Lee1-1/+9
[Description] Phantom DTBCLK can be calculated different from main because phantom has no DSC and thus will have a different output BPP. Ignore phantom DTBCLK requirement and only consider non-phantom DTBCLK requirements. Reviewed-by: Dillon Varone <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Add fallback defaults for invalid LTTPR DPCD capsMichael Strauss1-3/+16
[WHY] Some sinks are observed to return invalid LTTPR revision and/or invalid LTTPR link rate capabilities. [HOW] Assume any LTTPR which reports invalid max link rate supports HBR3. Don't validate LTTPR DPCD revision in dp_is_lttpr_present check. Reviewed-by: George Shen <[email protected]> Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Michael Strauss <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Update FIXED_VS retimer training pattern delayMichael Strauss1-3/+3
[WHY] Needed for PHY patterns as well to perform electrical compliance. Also need to increase wait time from 30ms to 50ms to resolve very intermittent UHBR20 link training failures. Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Michael Strauss <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: reduce ODM slice count to initial new dc state only when neededWenjing Liu2-41/+71
[why] We need to decrease ODM slice when adding or removing planes because MPO support takes precedence over dynamic ODM combine. However there is a case where we remove ODM combine even for ODM combine required timing in the initial new dc state. This is normally okay because ODM will be added back after we pass DML bandwidth validation. However since we remove ODM combine in the initial new state, the previous ODM pipe allocation is lost. This may cause the new plane to take away the original secondary OPP head pipe that is still required in the new state. For a timing that requires ODM 2:1 but optimized with ODM 4:1, if we add an MPO plane, we will not have enough pipe to preserve ODM 4:1. In this case we should reduce ODM slice count then try to add the MPO plane again. By reducing, we are gradually remove 1 ODM slice from right most side one at a time until we have enough free pipes for the new plane. If we remove ODM combine entirely, we could use the pipe at ODM slice index 1 as a DPP pipe for the new plane. But ODM slice 1 is still needed as the timing requires ODM 2:1. This transition is not seamless and user will see corruption on the screen. [how] Remove single ODM slice one at time until we have enough pipes for a new plane. Remove previous logic to always remove ODM combine entirely. Reviewed-by: Dillon Varone <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Fix multiple cursors when using 4 displays on a contiguous ↵Nevenko Stupar1-25/+0
large surface [Why & How] Remove some cursor offset calculations for rotated cursor for fixing a bug where multiple cursors are seen. Reviewed-by: Alvin Lee <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Nevenko Stupar <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Return after InitDaniel Sa1-0/+1
why: DML21 being overwritten after init. how: After initializing, early return. Reviewed-by: Dillon Varone <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Daniel Sa <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Change AVI Info Frame version to 4 for OVTChris Park1-1/+1
[Why] Official Release CTA specification reverted the change and no longer uses version 5 to indicate OVT timing. [How] Change the version used for AVI info Frame for OVT to 4. Reviewed-by: Leo Ma <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Chris Park <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Remove NULL assignment for stream_statusAlvin Lee1-2/+0
[Description] No need to assign stream_status NULL because it is always re-assigned before usage. This change is to fix coverity errors. Reviewed-by: Nicholas Choi <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Remove dcn32_smu13 duplicate headerZaeem Mohamed3-110/+2
[WHY] Duplicate headers requiring unecessary maintenance of both headers [HOW] Removal of smu13_driver_if header and all referneces to it changed to dcn32_smu13_driver Signed-off-by: Zaeem Mohamed <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Remove redundant ternary operationIvan Lipski1-1/+1
[WHY] Coverity analysis flagged this ternary operation as DEADCODE. Since 'total_y_free_entry' is initialized as 0x200 and 'total_c_free_entry' is initialized as 0x140, and they never change values before the ternary operator, so 'total_y_free_entry' is always greater 'total_c_free_entry', 'so small_free_entry' is always set to 'total_c_free_entry'. [HOW] Replace the ternary operator with the variable declaration. Signed-off-by: Ivan Lipski <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Remove unreachable checkIvan Lipski2-5/+0
[WHY] Coverity analysis flagged this code as DEADCODE since the condition and return in the outer loop are never reached. All operations with the 'dwb_pipe' variable happen in the inner loop, that already contains the same check with the 'MAX_DWB_PIPES'. The later check condition cannot occur before the check condition in the inner loop, thus the later condition is unreacable. [HOW] Remove the unreachable condition. Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Ivan Lipski <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Remove redundant if conditionsIvan Lipski2-10/+0
[WHY] Coverity analysis flagged the two if conditions in dcn30_dpp.c and dcn401_dpp.c as DEADCODE since they are never true, since the variable 'program_prealpha_dealpha' is initialized at 0 and never chagnes. [HOW] Removed the variable 'program_prealpha_dealpha' and the if conditions. Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Ivan Lipski <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: add odm_slice_rect parameter in spl_inWenjing Liu3-15/+28
[why] OPP input rect aka odm slice rect is a hardware dependent parameter that can't be determined by SPL software logic. Therefore we need to explicitly pass odm slice rect in. So ODM slice rect calculation is moved out of SPL. [how] add odm_slice_rect parameter in spl_in Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: use even ODM slice width for two pixels per containerWenjing Liu2-0/+4
[why] When optc uses two pixel per container, each ODM slice width must be an even number. [how] If ODM slice width is odd number increase it by 1. Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Fix Replay Desync Error TestDennis Chan1-0/+12
When PHY power off, the DP_SEC_CNTL cannot be configured and cause disable Adaptive sync SDP failed. Regarding the issue, the driver will disabled AS-SDP in replay state machine. Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Dennis Chan <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Replay + IPS + ABM in Full Screen VPBChunTao Tso1-0/+12
[Why] Because ABM will wait VStart to start getting histogram data, it will cause we can't enter IPS while full screnn video playing. [How] Modify the panel refresh rate to the maximun multiple of current refresh rate Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: ChunTao Tso <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Expand supported Replay residency modeLeon Huang2-9/+25
[Why] Dmub provides several Replay residency calculation methods, but current interface only supports either ALPM or PHY mode [How] Modify the interface for supporting different types of Replay residency calculation. Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Leon Huang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Replay low hzChunTao Tso3-16/+30
[Why] The original coasting vtotal is 2 bytes, and it need to be amended to 4 bytes because low hz case. [How] Amend coasting vtotal from 2 bytes to 4 bytes. Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: ChunTao Tso <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Use TPS3 for ALPM on Specific Panelpochchan1-2/+5
For some specific panel, it need to use TPS3 rather than use TP2 in ALPM when DSC is enabled. Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: pochchan <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Wake DMCUB before sending a command for replay featureNicholas Kazlauskas1-3/+3
[Why] We can hang in place trying to send commands when the DMCUB isn't powered on. [How] For functions that execute within a DC context or DC lock we can wrap the direct calls to dm_execute_dmub_cmd/list with code that exits idle power optimizations and reallows once we're done with the command submission on success. For DM direct submissions the DM will need to manage the enter/exit sequencing manually. We cannot invoke a DMCUB command directly within the DM execution helper or we can deadlock. Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Don't use fsleep for PSR exit waits on dmub replayNicholas Kazlauskas1-1/+2
[Why] These functions can be called from high IRQ levels and the OS will hang if it tries to use a usleep_highres or a msleep. [How] Replace the flseep with a udelay for dmub_replay_enable. Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amdgpu: revert "take runtime pm reference when we attach a buffer" v2Christian König3-51/+0
This reverts commit b8c415e3bf98 ("drm/amdgpu: take runtime pm reference when we attach a buffer") and commit 425285d39afd ("drm/amdgpu: add amdgpu runpm usage trace for separate funcs"). Taking a runtime pm reference for DMA-buf is actually completely unnecessary and even dangerous. The problem is that calling pm_runtime_get_sync() from the DMA-buf callbacks is illegal because we have the reservation locked here which is also taken during resume. So this would deadlock. When the buffer is in GTT it is still accessible even when the GPU is powered down and when it is in VRAM the buffer gets migrated to GTT before powering down. The only use case which would make it mandatory to keep the runtime pm reference would be if we pin the buffer into VRAM, and that's not something we currently do. v2: improve the commit message Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]> CC: [email protected]
2024-06-14drm/amd/display: Use dc wake for get the replay stateRodrigo Siqueira1-9/+3
Use dc_wake_and_execute_gpint with DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY to get the replay state. Signed-off-by: Rodrigo Siqueira <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amdgpu: refine imu firmware loadingYang Wang2-12/+8
refine imu firmware loading Signed-off-by: Yang Wang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amdgpu: refine pmfw/smu firmware loadingYang Wang5-25/+7
refine pmfw/smu firmware loading Signed-off-by: Yang Wang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amdgpu: refine gmc firmware loadingYang Wang3-19/+8
refine gmc firmware loading Signed-off-by: Yang Wang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amdgpu: refine vpe firmware loadingYang Wang1-4/+2
refine vpe firmware loading Signed-off-by: Yang Wang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amdgpu: refine vcn firmware loadingYang Wang1-9/+5
refine vcn firmware loading Signed-off-by: Yang Wang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amdgpu: move aca/mca init functions into ras_init() stageYang Wang4-37/+69
adjust the function position to better match aca/mca fini code in ras_fini(). Signed-off-by: Yang Wang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amdgpu: fix overflowed constant warning in mmhub_set_clockgating()Bob Zhou4-4/+4
To fix potential overflowed constant warning, modify the variables to u32 for getting the return value of RREG32_SOC15(). Signed-off-by: Bob Zhou <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amdgpu: Indicate CU havest info to CPHarish Kasiviswanathan1-2/+13
To achieve full occupancy CP hardware needs to know if CUs in SE are symmetrically or asymmetrically harvested v2: Reset is_symmetric_cus for each loop Signed-off-by: Harish Kasiviswanathan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amdgpu: Skip coredump during resets for debugLijo Lazar1-0/+1
Skip scheduling coredump when gpu reset is intentionally triggered through debugfs. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Asad Kamal <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amdgpu: refine sdma firmware loadingYang Wang4-19/+22
refine sdma firmware loading Signed-off-by: Yang Wang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amdgpu: refine psp firmware loadingYang Wang1-19/+7
refine psp firmware loading Signed-off-by: Yang Wang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amdgpu: add lock in kfd_process_dequeue_from_deviceYunxiang Li1-2/+7
We need to take the reset domain lock before talking to MES. While in this case we can take the lock inside the mes helper. We can't do so for most other mes helpers since they are used during reset. So for consistency sake we add the lock here. Signed-off-by: Yunxiang Li <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amdgpu: refine mes firmware loadingYang Wang1-4/+2
v1: refine mes firmware loading v2: use dev_info instead of DRM_INFO Signed-off-by: Yang Wang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amdgpu: Add missing locking for MES API callsMukul Joshi1-0/+12
Add missing locking at a few places when calling MES APIs to ensure exclusive access to MES queue. Signed-off-by: Mukul Joshi <[email protected]> Reviewed-by: Kent Russell <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Set default brightness according to ACPIMario Limonciello4-1/+24
Currently, amdgpu will always set up the brightness at 100% when it loads. However this is jarring when the BIOS has it previously programmed to a much lower value. The ACPI ATIF method includes two members for "ac_level" and "dc_level". These represent the default values that should be used if the system is brought up in AC and DC respectively. Use these values to set up the default brightness when the backlight device is registered. v2: squash in ACPI fix Reviewed-by: Leo Li <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Mario Limonciello <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amdgpu: drop some kernel messages in VCN codeDavid (Ming Qiang) Wu14-104/+17
Similar to commit 813e7d4cd05e where some kernel log messages are dropped. With this commit, more log messages in older version of VCN/JPEG code are dropped. Acked-by: Leo Liu <[email protected]> Signed-off-by: David (Ming Qiang) Wu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14Revert "drm/amd/display: Add NULL check for 'afb' before dereferencing in ↵Ivan Lipski1-12/+4
amdgpu_dm_plane_handle_cursor_update" [WHY] This patch is a dupplicate implementation of 14bcf29b, which we are reverting due to a regression with kms_plane_cursor IGT tests. This reverts commit 38e6f715b02b572f74677eb2f29d3b4bc6f1ddff. Reviewed-by: Srinivasan Shanmugam <[email protected]> Tested-by: George Zhang <[email protected]> Signed-off-by: Ivan Lipski <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14Revert "drm/amd/display: Add null check for 'afb' in amdgpu_dm_update_cursor"Ivan Lipski1-12/+4
[WHY] This commit introduced a regression with kms_plane_cursor IGT tests, causing AMD Asics to fail these tests. This reverts commit ce66ffd9813c8bd73e21b96d6476e5fb32b727c7. Reviewed-by: Srinivasan Shanmugam <[email protected]> Tested-by: George Zhang <[email protected]> Signed-off-by: Ivan Lipski <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amdgpu: refine gpu_info firmware loadingYang Wang1-5/+4
refine gpu_info firmware loading Signed-off-by: Yang Wang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: prevent register access while in IPSHamza Mahfooz1-0/+10
We can't read/write to DCN registers while in IPS. Since, that can cause the system to hang. So, before proceeding with the access in that scenario, force the system out of IPS. Cc: [email protected] # 6.6+ Reviewed-by: Roman Li <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amdgpu: enhance amdgpu_ucode_request() function flexibilityYang Wang2-9/+24
v1: Adding formatting string feature to improve function flexibility. v2: modify macro name to ADMGPU_UCODE_MAX_NAME. Signed-off-by: Yang Wang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amdgpu: fix the overflowed constant warning for RREG32_SOC15()Bob Zhou1-3/+4
To fix potential overflowed constant warning reported by Coverity, modify the variables to uint32_t. Signed-off-by: Bob Zhou <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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