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2012-10-01MIPS: Kconfig: Avoid build errors by hiding USE_OF from the user.Jonas Gorski1-3/+1
b01da9f1 ("MIPS: Prune some target specific code out of prom.c") removed the generic implementation of device_tree_init, breaking the kernel build when manually selecting USE_OF. Hide the config symbol so it can't be selected acidentially anymore. Signed-off-by: Jonas Gorski <[email protected]> Cc: [email protected] Cc: David Daney <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/4346/ Signed-off-by: Ralf Baechle <[email protected]>
2012-09-28Merge branch 'ralf-3.7' of ↵Ralf Baechle44-116/+2874
git://git.linux-mips.org/pub/scm/sjhill/linux-sjhill into mips-for-linux-next
2012-09-28Merge branch 'rixi-3.7' of ↵Ralf Baechle11-29/+35
git://git.linux-mips.org/pub/scm/sjhill/linux-sjhill into mips-for-linux-next
2012-09-27Merge branch 'broadcom' of git://dev.phrozen.org/mips-next into ↵Ralf Baechle10-39/+401
mips-for-linux-next
2012-09-27Merge branch 'ath79' of git://dev.phrozen.org/mips-next into mips-for-linux-nextRalf Baechle99-555/+671
2012-09-27Merge branch 'lantiq' of git://dev.phrozen.org/mips-next into ↵Ralf Baechle22-221/+2272
mips-for-linux-next
2012-09-27Merge branch 'cn6xxx-mgmt' of ↵Ralf Baechle4-139/+512
git://git.linux-mips.org/pub/scm/daney/upstream-daney into mips-for-linux-next
2012-09-27Merge branch 'cn68xx-ciu2' of ↵Ralf Baechle114-1618/+44371
git://git.linux-mips.org/pub/scm/daney/upstream-daney into mips-for-linux-next
2012-09-26MIPS: Replace `-' in defconfig filename wth `_' for consistency.Ralf Baechle5-0/+0
Signed-off-by: Ralf Baechle <[email protected]>
2012-09-26MIPS: Wire kcmp syscall.Ralf Baechle5-6/+13
Signed-off-by: Ralf Baechle <[email protected]>
2012-09-25MIPS: MIPSsim: Remove the MIPSsim platform.Steven J. Hill15-845/+0
The MIPSsim platform is no longer supported or used. [[email protected]: Also remove mipssim from arch/mips/Kbuild.platforms and delete arch/mips/include/asm/mach-mipssim/*.] Signed-off-by: Steven J. Hill <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/4350/ Signed-off-by: Ralf Baechle <[email protected]>
2012-09-22MIPS: NOTIFY_RESUME is not needed in TIF masksAl Viro1-2/+1
If it's set, SIGPENDING is also set. And SIGPENDING is present in the masks... Signed-off-by: Al Viro <[email protected]> Signed-off-by: Ralf Baechle <[email protected]>
2012-09-22MIPS: Merge the identical "return from syscall" per-ABI codeAl Viro5-51/+13
No need to keep 4 copies of that stuff; merged and taken to entry.S, unused public symbols there killed off. Signed-off-by: Al Viro <[email protected]> Signed-off-by: Ralf Baechle <[email protected]>
2012-09-22MIPS: Unobfuscate _TIF..._MASKAl Viro1-3/+4
Signed-off-by: Al Viro <[email protected]> Signed-off-by: Ralf Baechle <[email protected]>
2012-09-22MIPS: Prevent hitting do_notify_resume() with !user_mode(regs).Al Viro2-8/+3
Too late to do anything there... Signed-off-by: Al Viro <[email protected]> Signed-off-by: Ralf Baechle <[email protected]>
2012-09-17MIPS: Malta: Don't crash on spurious interrupt.Ralf Baechle1-3/+6
48d480b0bde794781fcae9501fb043c1bac0e523 [[MIPS] Malta: Fix off by one bug in interrupt handler.] did not take in account that irq_ffs() will also return 0 if for some reason the set of pending interrupts happens to be empty. This is trivial to trigger with a RM5261 CPU module running a 64-bit kernel and results in something like the following: CPU 0 Unable to handle kernel paging request at virtual address 0000000000000000, epc == ffffffff801772d0, ra == ffffffff8017ad24 Oops[#1]: Cpu 0 $ 0 : 0000000000000000 ffffffff9000a4e0 ffffffff9000a4e0 ffffffff9000a4e0 $ 4 : ffffffff80592be0 0000000000000000 00000000000000d6 ffffffff80322ed0 $ 8 : ffffffff805fe538 0000000000000000 ffffffff9000a4e0 ffffffff80590000 $12 : 00000000000000d6 0000000000000000 ffffffff80600000 ffffffff805fe538 $16 : 0000000000000000 0000000000000010 ffffffff80592be0 0000000000000010 $20 : 0000000000000000 0000000000500001 0000000000000000 ffffffff8051e078 $24 : 0000000000000028 ffffffff803226e8 $28 : 9800000003828000 980000000382b900 ffffffff8051e060 ffffffff8017ad24 Hi : 0000000000000000 Lo : 0000006388974000 epc : ffffffff801772d0 handle_irq_event_percpu+0x70/0x2f0 Not tainted ra : ffffffff8017ad24 handle_percpu_irq+0x54/0x88 Status: 9000a4e2 KX SX UX KERNEL EXL Cause : 00808008 BadVA : 0000000000000000 PrId : 000028a0 (Nevada) Modules linked in: Process init (pid: 1, threadinfo=9800000003828000, task=9800000003827968, tls=0000000077087490) Stack : ffffffff80592be0 ffffffff8058d248 0000000000000040 0000000000000000 ffffffff80613340 0000000000500001 ffffffff805a0000 0000000000000882 9800000003b89000 ffffffff8017ad24 00000000000000d5 0000000000000010 ffffffff9000a4e1 ffffffff801769f4 ffffffff9000a4e0 ffffffff801037f8 0000000000000000 ffffffff80101c44 0000000000000000 ffffffff9000a4e0 0000000000000000 9000000018000000 90000000180003f9 0000000000000001 0000000000000000 00000000000000ff 0000000000000018 0000000000000001 0000000000000001 00000000003fffff 0000000000000020 ffffffff802cf7ac ffffffff80208918 000000007fdadf08 ffffffff80612d88 ffffffff9000a4e1 0000000000000040 0000000000000000 ffffffff80613340 0000000000500001 ... Call Trace: [<ffffffff801772d0>] handle_irq_event_percpu+0x70/0x2f0 [<ffffffff8017ad24>] handle_percpu_irq+0x54/0x88 [<ffffffff801769f4>] generic_handle_irq+0x44/0x60 [<ffffffff801037f8>] do_IRQ+0x48/0x70 [<ffffffff80101c44>] ret_from_irq+0x0/0x4 [<ffffffff80326170>] serial8250_startup+0x310/0x870 [<ffffffff8032175c>] uart_startup.part.7+0x9c/0x330 [<ffffffff80321b4c>] uart_open+0x15c/0x1b0 [<ffffffff80302034>] tty_open+0x1fc/0x720 [<ffffffff801bffac>] chrdev_open+0x7c/0x180 [<ffffffff801b9ab8>] do_dentry_open.isra.14+0x288/0x390 [<ffffffff801bac5c>] nameidata_to_filp+0x5c/0xc0 [<ffffffff801ca700>] do_last.isra.33+0x330/0x8f0 [<ffffffff801caf3c>] path_openat+0xbc/0x440 [<ffffffff801cb3c8>] do_filp_open+0x38/0xa8 [<ffffffff801bade4>] do_sys_open+0x124/0x218 [<ffffffff80110538>] handle_sys+0x118/0x13c Code: 02d5a825 12800012 02a0b02d <de820000> de850008 0040f809 0220202d 0040a82d 40026000 ---[ end trace 5d8e7b9a86badd2d ]--- Kernel panic - not syncing: Fatal exception in interrupt Signed-off-by: Ralf Baechle <[email protected]>
2012-09-14MIPS: Malta: Remove RTC Data Mode bootstrap breakageMaciej W. Rozycki1-5/+0
YAMON requires and enforces the RTC Data Mode (Register B, DM bit) to binary, that is the bit is set every time the board goes through the firmware bootstrap sequence. Likewise its calendar manipulation commands interpret or set the RTC registers unconditionally as binary, never actually checking what the value of the DM bit is, under the (correct) assumption that it has been previously set, to indicate the binary mode. A change to Linux a while ago however introduced a platform-specific tweak that clears that bit and therefore forces the data mode to BCD. This causes clock corruption and misinterpretation that has to be fixed up by user-mode tools in system startup scripts as the initial clock is often incorrect according to the BCD interpretation forced. This change removes the hack; a comment included refers to alarm code, but even if it was broken at one point by requiring the BCD mode, it should have been trivially corrected and even if not, given how rarely the alarm feature is used, that was not really a reasonable justification to break the system clock that is indeed used by virtually everything. And either way the alarm code has been since fixed anyway. Signed-off-by: Maciej W. Rozycki <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/4336/ Signed-off-by: Ralf Baechle <[email protected]>
2012-09-13MIPS: Replace 'kernel_uses_smartmips_rixi' with 'cpu_has_rixi'.Steven J. Hill8-29/+26
Remove usage of the 'kernel_uses_smartmips_rixi' macro from all files and use new 'cpu_has_rixi' instead. Signed-off-by: Steven J. Hill <[email protected]> Acked-by: David Daney <[email protected]>
2012-09-13MIPS: Add base architecture support for RI and XI.Steven J. Hill4-1/+10
Originally both Read Inhibit (RI) and Execute Inhibit (XI) were supported by the TLB only for a SmartMIPS core. The MIPSr3(TM) Architecture now defines an optional feature to implement these TLB bits separately. Support for one or both features can be checked by looking at the Config3.RXI bit. Signed-off-by: Steven J. Hill <[email protected]> Acked-by: David Daney <[email protected]>
2012-09-13MIPS: Optimise TLB handlers for MIPS32/64 R2 cores.Steven J. Hill1-0/+16
The EXT and INS instructions can be used to decrease code size and thus speed up TLB handlers on MIPS32R2 and MIPS64R2 cores. Signed-off-by: Steven J. Hill <[email protected]>
2012-09-13MIPS: uasm: Add INS and EXT instructions.Steven J. Hill2-5/+20
These are MIPS32R2 instructions for merging and extracting bit fields from one GPR into another. Signed-off-by: Steven J. Hill <[email protected]>
2012-09-13MIPS: Avoid pipeline stalls on some MIPS32R2 cores.Steven J. Hill1-1/+13
The architecture specification says that an EHB instruction is needed to avoid a hazard when writing TLB entries. However, some cores do not have this hazard, and thus the EHB instruction causes a costly pipeline stall. Detect these cores and do not use the EHB instruction. Signed-off-by: Steven J. Hill <[email protected]>
2012-09-13MIPS: Make VPE count to be one-based.Steven J. Hill1-0/+1
When dealing with multiple VPEs, the count needs to be one-based for correct initialization of the GIC. Signed-off-by: Steven J. Hill <[email protected]>
2012-09-13MIPS: Add new end of interrupt functionality for GIC.Steven J. Hill1-1/+1
Each platform should define its own 'gic_finish_irq' function. Signed-off-by: Steven J. Hill <[email protected]>
2012-09-13MIPS: Add EIC support for GIC.Steven J. Hill2-8/+95
Add support to use an external interrupt controller with the GIC. Signed-off-by: Steven J. Hill <[email protected]>
2012-09-13MIPS: Code clean-ups for the GIC.Steven J. Hill2-34/+26
Fix whitespace, beautify the code and remove debug statements. Signed-off-by: Steven J. Hill <[email protected]>
2012-09-13MIPS: Make GIC code platform independent.Steven J. Hill4-72/+81
The GIC interrupt code is used by multiple platforms and the current code was half Malta dependent code. These changes abstract away the platform specific differences. Signed-off-by: Steven J. Hill <[email protected]>
2012-09-13MIPS: Changes to configuration files for SEAD-3 platform.Steven J. Hill3-2/+155
Change MIPS configuration files to add the SEAD-3. Also add new default configuration file for a SEAD-3 kernel. Signed-off-by: Steven J. Hill <[email protected]>
2012-09-13MIPS: Add core files for MIPS SEAD-3 development platform.Steven J. Hill29-0/+2445
More information about the SEAD-3 platform can be found at <http://www.mips.com/products/development-kits/mips-sead-3/> on MTI's site. Currently, the M14K family of cores is what the SEAD-3 is utilised with. Signed-off-by: Douglas Leung <[email protected]> Signed-off-by: Chris Dearman <[email protected]> Signed-off-by: Steven J. Hill <[email protected]>
2012-09-13MIPS: Add support for the 1074K core.Steven J. Hill4-0/+28
Signed-off-by: Steven J. Hill <[email protected]>
2012-09-13GPIO: MIPS: lantiq: fix overflow inside stp-xway driverJohn Crispin1-1/+1
The driver was using a 16 bit field for storing the shadow value of the shift register cascade. This resulted in only the first 2 shift registeres receiving the correct data. The third shift register would always receive 0x00. Fix this by using a 32bit field for the shadow value. Signed-off-by: John Crispin <[email protected]> Cc: [email protected]
2012-09-13MIPS: lantiq: make use of __gpio_to_irqJohn Crispin1-4/+1
The gpio_chip struct allows us to set a .to_irq callback. Once this is set we can rely on the generic __gpio_to_irq() function to map gpio->irq allowing more than one gpio_chip to register an interrupt Signed-off-by: John Crispin <[email protected]>
2012-09-13Document: devicetree: add OF documents for lantiq falcon pinctrlJohn Crispin1-0/+83
Signed-off-by: John Crispin <[email protected]> Signed-off-by: Thomas Langer <[email protected]> Acked-by: Linus Walleij <[email protected]> Cc: [email protected] Cc: [email protected]
2012-09-13Document: devicetree: add OF documents for lantiq xway pinctrlJohn Crispin1-0/+97
Signed-off-by: John Crispin <[email protected]> Acked-by: Linus Walleij <[email protected]> Cc: [email protected] Cc: [email protected]
2012-09-13OF: pinctrl: MIPS: lantiq: adds support for FALCON SoCJohn Crispin5-0/+479
Implement support for pinctrl on lantiq/falcon socs. The FALCON has 5 banks of up to 32 pins. Signed-off-by: John Crispin <[email protected]> Signed-off-by: Thomas Langer <[email protected]> Acked-by: Linus Walleij <[email protected]> Cc: [email protected] Cc: [email protected]
2012-09-13OF: pinctrl: MIPS: lantiq: implement lantiq/xway pinctrl supportJohn Crispin9-184/+1334
Implement support for pinctrl on lantiq/xway socs. The IO core found on these socs has the registers for pinctrl, pinconf and gpio mixed up in the same register range. As the gpio_chip handling is only a few lines, the driver also implements the gpio functionality. This obseletes the old gpio driver that was located in the arch/ folder. Signed-off-by: John Crispin <[email protected]> Acked-by: Linus Walleij <[email protected]> Cc: [email protected] Cc: [email protected]
2012-08-31netdev: octeon_mgmt: Make multi-line comment style consistent.David Daney1-18/+9
No code changes. Recent patches have used the netdev style multi-line comment formatting, making the style inconsistent within octeon_mgmt.c Update the remaining comment blocks to achieve style harmony. Signed-off-by: David Daney <[email protected]> Acked-by: David S. Miller <[email protected]>
2012-08-31netdev: octeon_mgmt: Remove some useless 'inline'David Daney1-4/+4
Signed-off-by: David Daney <[email protected]> Acked-by: David S. Miller <[email protected]>
2012-08-31netdev: octeon_mgmt: Cleanup and modernize MAC address handling.David Daney1-7/+9
Use eth_mac_addr(), and generate a random address if none is otherwise assigned. Signed-off-by: David Daney <[email protected]> Acked-by: David S. Miller <[email protected]>
2012-08-31netdev: octeon_mgmt: Set the parent device.David Daney1-0/+2
This establishes useful links in sysfs. Signed-off-by: David Daney <[email protected]> Acked-by: David S. Miller <[email protected]>
2012-08-31netdev: octeon_mgmt: Improve ethtool_ops.David Daney1-4/+18
Correctly show no link when the interface is down, and return -EOPNOTSUPP for things that don't work. This quiets the ethtool program when run on down interfaces. Signed-off-by: David Daney <[email protected]> Acked-by: David S. Miller <[email protected]>
2012-08-31netdev: octeon_mgmt: Add hardware timestamp support.Chad Reese1-5/+152
Octeon cn6XXX models have timestamp support on the mgmt ports, so hook it up. Signed-off-by: Chad Reese <[email protected]> Signed-off-by: David Daney <[email protected]> Acked-by: David S. Miller <[email protected]>
2012-08-31netdev: octeon_mgmt: Add support for 1Gig ports.David Daney1-73/+255
The original hardware only supported 10M and 100M. Later versions added 1G support. Here we update the driver to make use of this. Also minor logic clean-ups for testing PHY registration error codes and TX complete high water marks. Signed-off-by: David Daney <[email protected]> Acked-by: David S. Miller <[email protected]>
2012-08-31MIPS: Octeon: Add octeon_io_clk_delay() function.David Daney3-31/+66
Also cleanup and fix octeon_init_cvmcount() Signed-off-by: David Daney <[email protected]> Acked-by: David S. Miller <[email protected]>
2012-08-31MIPS: OCTEON: Register ciu/ciu2 as the default irq_domain.David Daney1-0/+2
This makes it possible to call irq_create_mapping(NULL, ??) Signed-off-by: David Daney <[email protected]>
2012-08-31MIPS: Octeon: Make interrupt controller work with threaded handlers.David Daney1-143/+137
For CIUv1 controllers, we were relying on all calls to the irq_chip functions to be done from the CPU that received the irq, and that they would all be done from interrupt contest. These assumptions do not hold for threaded handlers. We make all the masking actually mask the irq source, and use real raw_spin_locks instead of manually twiddling the Status[IE] bit. Signed-off-by: David Daney <[email protected]>
2012-08-31MIPS: OCTEON: Add support for cn68XX interrupt controller.David Daney2-24/+547
The cn68XX has a new interrupt controller named CIU2, add support for this, and use it if cn68XX detected at runtime. Signed-off-by: David Daney <[email protected]>
2012-08-31MIPS: OCTEON: Add OCTEON_IRQ_* definitions for cn68XX chips.David Daney1-3/+4
There are 64 workqueue, 32 watchdog, and 4 mbox. Signed-off-by: David Daney <[email protected]>
2012-08-31MIPS: OCTEON: Update register definitions.David Daney38-1160/+42982
Add support for cn68xx, cn61xx, cn63xx, cn66xx and cnf71XX. Add little-endian register layouts. Patch cvmx-interrupt-rsl.c for changed definition. Signed-off-by: David Daney <[email protected]>
2012-08-31MIPS: OCTEON: Add detection of cnf71xx parts.David Daney1-0/+18
Also add cvmx_get_octeon_family(). Both of these are needed by the upcoming register definition refresh patch. Signed-off-by: David Daney <[email protected]>
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