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2021-05-19drm/amd/amdgpu: update golden_setting_10_3_5 for beige_gobyChengming Gui1-0/+2
add mmCGTT_SPI_{RA0/RA1}_CLK_CTRL setting Signed-off-by: Chengming Gui <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: Enable VCN for Beige GobyVeerabadhran Gopalakrishnan3-45/+68
Enabled VCN support for Beige Goby chip Signed-off-by: Veerabadhran Gopalakrishnan <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: add gc_10_3_5 golden setting for beige_gobyHawking Zhang1-0/+38
execute gc_10_3_5 golden registers one-time initialization Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Jiansong Chen <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: add mmhub client support for beige gobyAlex Deucher1-0/+27
For decoding GPUVM page faults. Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/amdgpu: add psp support for beige_gobyChengming Gui4-2/+16
add general PSP support for beige_goby Signed-off-by: Chengming Gui <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/amdgpu: add smu support for beige_gobyChengming Gui4-2/+15
Use soft-pptable for beige_goby v2: fix format Signed-off-by: Chengming Gui <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdkfd: add kfd2kgd funcs for beige_goby kfd supportChengming Gui1-0/+1
Add the function pointer. Signed-off-by: Chengming Gui <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdkfd: support beige_goby KFDChengming Gui6-0/+84
Add KFD support for beige_goby v2: fix asic name typo v3: squash in updates (Alex) v4: squash in needs_atomics fix (Alex) Signed-off-by: Chengming Gui <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/amdgpu: Use IP discovery table for beige gobyChengming Gui1-0/+1
Rather than gpu info firmware. Signed-off-by: Chengming Gui <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/amdgpu: support cp_fw_write_wait for beige_gobyChengming Gui1-0/+1
Same as dimgrey_cavefish to support WAIT_REG_MEM packet. Signed-off-by: Chengming Gui <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/amdgpu: add virtual display support for beige_gobyChengming Gui1-0/+2
Add virtual ip block for beige_goby Signed-off-by: Chengming Gui <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/amdgpu: configure beige_goby gfx according to gfx 10.3's definitionChengming Gui1-0/+9
The gfx version of beige_goby is 10.3, identical to sienna_cichlid, follow the way of sienna_cichlid Signed-off-by: Chengming Gui <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/amdgpu: add sdma ip block for beige_gobyChengming Gui2-0/+8
Enable sdma block for beige_goby, same as sienna_cichlid v2: share the same setting of sdma instance num with vangogh Signed-off-by: Chengming Gui <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Suggested-by: Alexander Deucher <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/amdgpu: add gfx ip block for beige_gobyChengming Gui2-0/+6
Enable gfx block for beige_goby, same as dimgrey_cavefish Signed-off-by: Chengming Gui <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/amdgpu: add ih ip block for beige_gobyChengming Gui2-0/+2
Enable ih block for beige_goby, same as dimgrey_cavefish Signed-off-by: Chengming Gui <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/amdgpu: add gmc ip block for beige_gobyChengming Gui2-0/+2
Enable gmc block for beige_goby, same as sienna_cichlid Signed-off-by: Chengming Gui <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/amdgpu: add common ip block for beige_gobyChengming Gui1-0/+3
Same as dimgrey_cavefish v2: fix comments typo Signed-off-by: Chengming Gui <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/amdgpu: add mmhub support for beige_gobyChengming Gui1-0/+6
Same as dimgrey_cavefish Signed-off-by: Chengming Gui <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/amdgpu: initialize IP offset for beige_gobyChengming Gui5-1/+1334
Add ip offset definition for beige_goby and initialize it v2: squash in fixes (Alex) V3: fix permissions on file (Alex) Signed-off-by: Chengming Gui <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/amdgpu: add common support for beige_gobyChengming Gui1-0/+6
Add external id and set clock gating for beige_goby Signed-off-by: Chengming Gui <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/amdgpu: add gmc support for beige_gobyChengming Gui1-0/+3
Same as dimgrey_cavefish Signed-off-by: Chengming Gui <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/amdgpu: add support for beige_goby firmwareChengming Gui1-0/+10
Add support for beige_goby cp/rlc firmware Signed-off-by: Chengming Gui <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/amdgpu: set asic family and ip blocks for beige_gobyChengming Gui1-0/+1
Same as navi series Signed-off-by: Chengming Gui <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/amdgpu: set fw load type for beige_gobyChengming Gui1-0/+2
Use direct load for beige_goby Signed-off-by: Chengming Gui <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/amdgpu: add beige_goby asic typeChengming Gui2-0/+2
Add chip type for beige_goby v2: fix enum count (Alex) Signed-off-by: Chengming Gui <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/display: 3.2.136Aric Cyr1-1/+1
Signed-off-by: Aric Cyr <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/display: [FW Promotion] Release 0.0.66Anthony Koo1-2/+2
Signed-off-by: Anthony Koo <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/display: Refactor and add visual confirm for HW Flip QueueWyatt Wood14-25/+68
[Why] Visual confirm will indicate if driver is programming the surface address. Refactor is required because much of the visual confirm logic is buried deep in the mpcc files. In addition, visual confirm is not updated during fast updates. [How] In order to have visual confirm for driver flips, visual confirm needs to be updated on every frame, including fast updates. Add a new hw sequencer interface update_visual_confirm_color, and a new mpc function pointer set_bg_color. v2: drop unused variable (Alex) Signed-off-by: Wyatt Wood <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/display: Use the correct max downscaling value for DCN3.x familyNikola Cornij3-9/+12
[why] As per spec, DCN3.x can do 6:1 downscaling and DCN2.x can do 4:1. The max downscaling limit value for DCN2.x is 250, which means it's calculated as 1000 / 4 = 250. For DCN3.x this then gives 1000 / 6 = 167. [how] Set maximum downscaling limit to 167 for DCN3.x Signed-off-by: Nikola Cornij <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/display: Avoid get/put vblank when stream disabledWayne Lin2-3/+4
[Why] amdgpu_dm_crtc_set_crc_source() will call amdgpu_dm_crtc_configure_crc_source() to enable/disable CRC generation. However, configuration will be deferred to stream enabled. If stream is not enabled, current flow will still try to get/put vblank refcount. [How] Return EINVAL to skip actions on vblank refcount when stream is not enabled. Signed-off-by: Wayne Lin <[email protected]> Reviewed-by: Chao-kai Wang <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/display: Correct DPCD revision for eDP v1.4Zhan Liu1-2/+10
[Why] eDP version and DPCD revision are different. Per VESA spec, "The DPCD revision for eDP v1.4 is 13h". SUPPORTED_LINK_RATES is valid since eDP v1.4 (DPCD_REV_13). [How] Correct DPCD_REV for eDP v1.4. Signed-off-by: Zhan Liu <[email protected]> Reviewed-by: Nikola Cornij <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/display: Add Overflow check to skip MALLBhawanpreet Lakha1-0/+9
[Why] In some small modes (<200pixels) the stutter period is really big and will cause overflow. In these cases we shouldnt try to enable MALL as it will exceeds range of hysteresis timer (this can be seen in some IGT tests where the plane size is small) [How] Compare the stutter_period with the frame time and if we will overflow there is no point in trying to enable MALL (and see the ASSERT) so we early exist in this case Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/display: Refactor suspend/resume of Secure displayWayne Lin3-77/+15
[Why] Once set ROI and do suspend/resume, current flow will not enable OTG_CRC_CTL again due to we'll defer crc configuration when stream is enabled. [How] Remove current suspend/resume function and have logic implemented into amdgpu_dm_atomic_commit_tail() Signed-off-by: Wayne Lin <[email protected]> Reviewed-by: Chao-kai Wang <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/display: consider channel coding in configure lttpr modeWenjing Liu2-18/+30
[why] Some lttpr configuration steps are exclusive to 8b/10b channel coding mode. We need to take channel conding into account. Signed-off-by: Wenjing Liu <[email protected]> Reviewed-by: George Shen <[email protected]> Acked-by: Stylon Wang <[email protected]> Acked-by: Wesley Chalmers <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/display: rename perform_link_training_int functionWenjing Liu1-2/+2
[why] The function's name doesn't represent what it actaully does. The function implements necessary steps for our hardware to transition from link training mode back to video idle mode. Therefore, rename the function as dp_transition_to_video_idle so everyone can understand it. Signed-off-by: Wenjing Liu <[email protected]> Reviewed-by: George Shen <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/display: decide link training settings based on channel codingWenjing Liu1-4/+15
[how] Rename initialize_training_settings to decide_training_settings. Call get link encoding format and decide training settings based on current channel coding. Signed-off-by: Wenjing Liu <[email protected]> Reviewed-by: George Shen <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/display: determine dp link encoding format from link settingsWenjing Liu3-0/+13
[how] Implement a function that determines link encoding format based on the link settings passed in. Signed-off-by: Wenjing Liu <[email protected]> Reviewed-by: George Shen <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/display: Disconnect non-DP with no EDIDChris Park1-0/+18
[Why] Active DP dongles return no EDID when dongle is connected, but VGA display is taken out. Current driver behavior does not remove the active display when this happens, and this is a gap between dongle DTP and dongle behavior. [How] For active DP dongles and non-DP scenario, disconnect sink on detection when no EDID is read due to timeout. Signed-off-by: Chris Park <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/display: Minor refactor of DP PHY test automationGeorge Shen1-7/+10
[Why] Improve readability and maintainability of code. [How] Refactor test pattern size calculation out of function call parameter and store value in variable. Signed-off-by: George Shen <[email protected]> Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/display: Document set RECOUT operationRodrigo Siqueira2-16/+39
During the investigation on how to add visual confirmation on top of the planes used by DCN, it becomes evident that the lack of information in the code makes this work unnecessarily complicated. This commit introduces a set of documentation related to the RECOUT operation in order to make it easy for developers to navigate this set of functions. Signed-off-by: Rodrigo Siqueira <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/display: Add kernel-doc to some hubp functionsRodrigo Siqueira1-0/+13
Signed-off-by: Rodrigo Siqueira <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/display: Remove legacy commentsRodrigo Siqueira1-160/+0
To improve the code readability, this commit removes a set of commented and not used functions for a long time. Notice that now we have the amdgpu_dm_dtn_log, which prints all the relevant information that we need. Signed-off-by: Rodrigo Siqueira <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/display: Add documentation for power gate planeRodrigo Siqueira1-2/+36
This commit introduces kernel documentation to some essential functions related to power gate control over planes. It also adds a macro to make one part of the code easy to understand. Signed-off-by: Rodrigo Siqueira <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/display: Add get_current_time interface to dmub_srvWyatt Wood5-2/+13
[Why] Need to get current DMUB time. [How] Add get_current_time interface to dmub_srv. v2: drop whitespace changes (Alex) Signed-off-by: Wyatt Wood <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/display: treat memory as a single-channel for asymmetric memory V3Hugo Hu2-2/+48
Previous patch caused crash and had been reverted. This patch addresses the issue without regression. [Why] 1. Driver use umachannelnumber to calculate watermarks for stutter. In asymmetric memory config, the actual bandwidth is less than dual-channel. The bandwidth should be the same as single-channel. 2. We found single rank dimm need additional delay time for stutter. [How] Get information from each DIMM. Treat memory config as a single-channel for asymmetric memory in bandwidth calculating. Add additional delay time for single rank dimm. Signed-off-by: Hugo Hu <[email protected]> Reviewed-by: Sung Lee <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/pm: Reset max GFX clock after disabling determinismLijo Lazar1-3/+8
When determinism mode is disabled on aldebaran, max GFX clock will be reset to default max frequency value. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/pm: Fix showing incorrect frequencies on aldebaranLijo Lazar2-25/+55
v1: Use the current and custom pstate frequencies to track the current and user-set min/max values in manual and determinism mode. Previously, only actual_* value was used to track the currrent and user requested value. The value will get reassigned whenever user requests a new value with pp_od_clk_voltage node. Hence it will show incorrect values when user requests an invalid value or tries a partial request without committing the values. Separating out to custom and current variable fixes such issues. v2: Remove redundant if-else check Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/pm: Add custom/current freq to pstatesLijo Lazar1-0/+8
Add custom member for user requested custom frequency, level mask or min/max frequencies. Add curr member to keep track of the current active values. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: Conditionally reset RAS counters on bootJohn Clements4-14/+14
Only clear RAS error counters if perestent EDC harvesting is not supported Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: disable 3DCGCG on picasso/raven1 to avoid compute hangChangfeng2-5/+7
There is problem with 3DCGCG firmware and it will cause compute test hang on picasso/raven1. It needs to disable 3DCGCG in driver to avoid compute hang. Signed-off-by: Changfeng <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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