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2021-05-19drm/amdgpu: Refine the error report when flush tlb.Peng Ju Zhou1-1/+1
there are 2 hubs to flush in the gmc, to make it easier to debug when hub flush failed, refine the logs. Signed-off-by: Peng Ju Zhou <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: Skip the program of GRBM_CAM* in SRIOVPeng Ju Zhou1-0/+3
KMD should not the program these registers, so skip them in the SRIOV environment. Signed-off-by: Peng Ju Zhou <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: Fix GPU TLB update error when PAGE_SIZE > AMDGPU_PAGE_SIZEYi Li1-1/+1
When PAGE_SIZE is larger than AMDGPU_PAGE_SIZE, the number of GPU TLB entries which need to update in amdgpu_map_buffer() should be multiplied by AMDGPU_GPU_PAGES_IN_CPU_PAGE (PAGE_SIZE / AMDGPU_PAGE_SIZE). Reviewed-by: Christian König <[email protected]> Signed-off-by: Yi Li <[email protected]> Signed-off-by: Huacai Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdkfd: heavy-weight flush TLB after unmapPhilip Yang4-6/+13
Need do a heavy-weight TLB flush to make sure we have no more dirty data in the cache for the unmapped pages. Define enum TLB_FLUSH_TYPE, add flush_type parameter to amdgpu_amdkfd_flush_gpu_tlb_pasid. Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19Revert "drm/amdkfd: flush TLB after updating GPU page table"Philip Yang1-3/+0
This reverts commit 1704ac8e439e3dcf97431e268bd64fde1874d807. After "drm/amdgpu: flush TLB if valid PDE turns into PTE" is checked in, this workaround is not needed. Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: Fill adev->unique_id with data from PF2VF msgJiawei Gu2-1/+4
Initialize unique_id from PF2VF under virtualization. V2: skip smu_get_unique_id() under virtualization Signed-off-by: Jiawei Gu <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: flush TLB if valid PDE turns into PTEPhilip Yang3-7/+27
Mapping huge page, 2MB aligned address with 2MB size, uses PDE0 as PTE. If previously valid PDE0, PDE0.V=1 and PDE0.P=0 turns into PTE, this requires TLB flush, otherwise page table walker will not read updated PDE0. Change page table update mapping to return table_freed flag to indicate the previously valid PDE may have turned into a PTE if page table is freed. Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/radeon: use the dummy page for GART if neededChristian König1-1/+2
Imported BOs don't have a pagelist any more. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Fixes: 0575ff3d33cd ("drm/radeon: stop using pages with drm_prime_sg_to_page_addr_arrays v2")
2021-05-19drm/amdgpu: move struct amdgpu_vram_reservation into vram mgrChristian König2-5/+5
Not used outside of that file. Signed-off-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Tested-by: Nirmoy Das <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: check contiguous flags instead of mm_nodeChristian König1-7/+4
Drop the last user of drm_mm_node. Signed-off-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Tested-by: Nirmoy Das <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: set the contiguous flag if possibleChristian König1-2/+3
This avoids reallocating scanout BOs on first pin in a lot of cases. Signed-off-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Tested-by: Nirmoy Das <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: use cursor functions in amdgpu_bo_in_cpu_visible_vramChristian König1-6/+9
One of the last remaining uses of drm_mm_node. Signed-off-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Tested-by: Nirmoy Das <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: re-apply "use the new cursor in the VM code" v2Christian König3-40/+20
Now that we found the underlying problem we can re-apply this patch. This reverts commit 6b44b667e24cf89603ebdaa31b939c034d425162. v2: rebase on KFD changes Signed-off-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Tested-by: Nirmoy Das <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: query boot config cap before issue psp cmdHawking Zhang1-4/+6
Only send boot_config cmd to ASICs that support dynamic boot config. Otherwise, the boot_config cmd will fail. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: add helper function to query dynamic boot config capHawking Zhang3-0/+18
Check firmware flags to determine whether dynmaic boot config is supported or not. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: switch to cached fw flags for mem training capHawking Zhang3-62/+11
Check cached firmware_flags to determin whether two stage mem training is supported or not. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: switch to cached fw flags for sram ecc capHawking Zhang1-21/+7
Check cached firmware_flags to determine whether sram ecc is supported or not. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: switch to cached fw flags for gpu virt capHawking Zhang3-16/+13
Check cached firmware_flags to determine if gpu virtualization is supported in vbios Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: add atomfirmware helper function to query fw capHawking Zhang4-12/+44
Fimware capability was changed from 16 bits to 32 bits for atomfirmware. add helper funciton to query firmware capability and cache the value at early stage. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: Complete multimedia bandwidth interfaceBokun Zhang4-7/+225
- Update SRIOV PF2VF header with latest revision - Extend existing function in amdgpu_virt.c to read MM bandwidth config from PF2VF message - Add SRIOV Sienna Cichlid codec array and update the bandwidth with PF2VF message v2: squash in removal of unused variable (Alex) Signed-off-by: Bokun Zhang <[email protected]> Reviewed-by: Monk liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: Albebaran: MTYPE_NC for coarse-grain remote memoryFelix Kuehling2-2/+4
MTYPE UC was used for a specific use case that ended up not being implemented. Use NC for better performance for coarse-grained memory where cache coherence during shader execution is not required. Signed-off-by: Felix Kuehling <[email protected]> Reviewed-by: Oak Zeng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: Arcturus: MTYPE_NC for coarse-grain remote memoryFelix Kuehling2-2/+4
MTYPE UC was used for a specific use case that ended up not being implemented. Use NC for better performance for coarse-grained memory where cache coherence during shader execution is not required. Signed-off-by: Felix Kuehling <[email protected]> Reviewed-by: Oak Zeng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: Add compile flag for securedisplayJinzhou Su1-0/+4
Add compile flag CONFIG_DEBUG_FS to clear the warning: unused variable 'amdgpu_securedisplay_debugfs_ops' Signed-off-by: Jinzhou Su <[email protected]> Acked-by: Alex Deucher <[email protected]> Acked-by: Huang Rui <[email protected]> Reported-by: kernel test robot <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdkfd: refine the poison data consumption handlingDennis Li3-1/+42
The user applications maybe register the KFD_EVENT_TYPE_HW_EXCEPTION and KFD_EVENT_TYPE_MEMORY events, driver could notify them when poison data consumed. Beside that, some applications maybe register SIGBUS signal hander. These applications will handle poison data by themselves, exit or re-create context to re-dispatch works. Signed-off-by: Dennis Li <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/radeon/dpm: Disable sclk switching on Oland when two 4K 60Hz monitors ↵Kai-Heng Feng3-0/+12
are connected Screen flickers rapidly when two 4K 60Hz monitors are in use. This issue doesn't happen when one monitor is 4K 60Hz (pixelclock 594MHz) and another one is 4K 30Hz (pixelclock 297MHz). The issue is gone after setting "power_dpm_force_performance_level" to "high". Following the indication, we found that the issue occurs when sclk is too low. So resolve the issue by disabling sclk switching when there are two monitors requires high pixelclock (> 297MHz). v2: - Only apply the fix to Oland. Signed-off-by: Kai-Heng Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdkfd: new range accessible by all GPUsPhilip Yang1-4/+8
If xnack is on, new range is created to recover retry vm fault or created by SVM API calls, set all GPUs have access to the range. Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/pm: Update aldebaran pmfw interfaceLijo Lazar2-3/+6
Update aldebaran driver-PMFW interface to version 0x07 Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/amdgpu: Cancel the hrtimer in sw_finiRoy Sun1-7/+5
Move the process of cancelling hrtimer to sw_fini Signed-off-by: Roy Sun <[email protected]> Reviewed-by: Emily Deng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/pm: enable ASPM by defaultKenneth Feng4-4/+4
Since ASPM function has been stable, we don't need to add the modprobe parameter and we can enable ASPM by default. Signed-off-by: Kenneth Feng <[email protected]> Reviewed-by: Jiansong Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: update the method for harvest IP for specific SKULikun Gao1-14/+16
Update the method of disabling VCN IP for specific SKU for navi1x ASIC, it will judge whether should add the related IP at the function of amdgpu_device_ip_block_add(). Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: add judgement when add ip blocks (v2)Likun GAO6-2/+57
Judgement whether to add an sw ip according to the harvest info. v2: fix indentation (Alex) Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: add synchronization among waves in the same threadgroupDennis Li1-134/+142
It is possible that the previous waves have exited before others are created, so the other waves maybe reuse pyhsical resouces left by previous ones. Therefore add barrier instruction to synchronize waves within the same threadgroup. Signed-off-by: Dennis Li <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu/display: fix dal_allocation documentationAlex Deucher1-0/+4
Add missing structure elements. Fixes: 0dd79532340568 ("drm/amdgpu/display: Implement functions to let DC allocate GPU memory") Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-11drm/amdgpu/display: fix build when CONFIG_DRM_AMD_DC_DCN is not definedAlex Deucher1-0/+2
Fixes: drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c: In function ‘amdgpu_dm_initialize_drm_device’: drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:3726:7: error: implicit declaration of function ‘register_outbox_irq_handlers’; did you mean ‘register_hpd_handlers’? [-Werror=implicit-function-declaration] 3726 | if (register_outbox_irq_handlers(dm->adev)) { | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ | register_hpd_handlers Fixes: 81927e2808be ("drm/amd/display: Support for DMUB AUX") Reviewed-by: Jude Shih <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: Jude Shish <[email protected]>
2021-05-11drm/amdgpu/display: fix warning when CONFIG_DRM_AMD_DC_DCN is not definedAlex Deucher1-1/+1
Fixes: At top level: drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:633:13: warning: ‘dm_dmub_outbox1_low_irq’ defined but not used [-Wunused-function] 633 | static void dm_dmub_outbox1_low_irq(void *interrupt_params) | ^~~~~~~~~~~~~~~~~~~~~~~ Fixes: 81927e2808be ("drm/amd/display: Support for DMUB AUX") Reviewed-by: Jude Shih <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: Jude Shih <[email protected]>
2021-05-11drm/amdgpu/display: remove an old DCN3 guardAlex Deucher1-2/+0
The DCN3 guards were dropped a while ago, this one must have snuck in in a merge or something. Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-11drm/amdgpu: Delete two unneeded bool conversionsZhen Lei1-2/+2
The result of an expression consisting of a single relational operator is already of the bool type and does not need to be evaluated explicitly. No functional change. Signed-off-by: Zhen Lei <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-11drm/amd/display: Delete several unneeded bool conversionsZhen Lei2-3/+3
The result of an expression consisting of a single relational operator is already of the bool type and does not need to be evaluated explicitly. No functional change. Signed-off-by: Zhen Lei <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-11drm/amd/display: Initialize attribute for hdcp_srm sysfs fileDavid Ward1-0/+1
It is stored in dynamically allocated memory, so sysfs_bin_attr_init() must be called to initialize it. (Note: "initialization" only sets the .attr.key member in this struct; it does not change the value of any other members.) Otherwise, when CONFIG_DEBUG_LOCK_ALLOC=y this message appears during boot: BUG: key ffff9248900cd148 has not been registered! Fixes: 9037246bb2da ("drm/amd/display: Add sysfs interface for set/get srm") Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1586 Reported-by: Mikhail Gavrilov <[email protected]> Signed-off-by: David Ward <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-10drm/amd/pm: Fix out-of-bounds bugGustavo A. R. Silva2-99/+109
Create new structure SISLANDS_SMC_SWSTATE_SINGLE, as initialState.levels and ACPIState.levels are never actually used as flexible arrays. Those arrays can be used as simple objects of type SISLANDS_SMC_HW_PERFORMANCE_LEVEL, instead. Currently, the code fails because flexible array _levels_ in struct SISLANDS_SMC_SWSTATE doesn't allow for code that accesses the first element of initialState.levels and ACPIState.levels arrays: drivers/gpu/drm/amd/pm/powerplay/si_dpm.c: 4820: table->initialState.levels[0].mclk.vDLL_CNTL = 4821: cpu_to_be32(si_pi->clock_registers.dll_cntl); ... 5021: table->ACPIState.levels[0].mclk.vDLL_CNTL = 5022: cpu_to_be32(dll_cntl); because such element cannot be accessed without previously allocating enough dynamic memory for it to exist (which never actually happens). So, there is an out-of-bounds bug in this case. That's why struct SISLANDS_SMC_SWSTATE should only be used as type for object driverState and new struct SISLANDS_SMC_SWSTATE_SINGLE is created as type for objects initialState, ACPIState and ULVState. Also, with the change from one-element array to flexible-array member in commit 0e1aa13ca3ff ("drm/amd/pm: Replace one-element array with flexible-array in struct SISLANDS_SMC_SWSTATE"), the size of dpmLevels in struct SISLANDS_SMC_STATETABLE should be fixed to be SISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE instead of SISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1. Fixes: 0e1aa13ca3ff ("drm/amd/pm: Replace one-element array with flexible-array in struct SISLANDS_SMC_SWSTATE") Cc: [email protected] Signed-off-by: Gustavo A. R. Silva <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-10drm/radeon/si_dpm: Fix SMU power state loadGustavo A. R. Silva2-99/+109
Create new structure SISLANDS_SMC_SWSTATE_SINGLE, as initialState.levels and ACPIState.levels are never actually used as flexible arrays. Those arrays can be used as simple objects of type SISLANDS_SMC_HW_PERFORMANCE_LEVEL, instead. Currently, the code fails because flexible array _levels_ in struct SISLANDS_SMC_SWSTATE doesn't allow for code that access the first element of initialState.levels and ACPIState.levels arrays: 4353 table->initialState.levels[0].mclk.vDLL_CNTL = 4354 cpu_to_be32(si_pi->clock_registers.dll_cntl); ... 4555 table->ACPIState.levels[0].mclk.vDLL_CNTL = 4556 cpu_to_be32(dll_cntl); because such element cannot exist without previously allocating any dynamic memory for it (which never actually happens). That's why struct SISLANDS_SMC_SWSTATE should only be used as type for object driverState and new struct SISLANDS_SMC_SWSTATE_SINGLE is created as type for objects initialState, ACPIState and ULVState. Also, with the change from one-element array to flexible-array member in commit 96e27e8d919e ("drm/radeon/si_dpm: Replace one-element array with flexible-array in struct SISLANDS_SMC_SWSTATE"), the size of dpmLevels in struct SISLANDS_SMC_STATETABLE should be fixed to be SISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE instead of SISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1583 Fixes: 96e27e8d919e ("drm/radeon/si_dpm: Replace one-element array with flexible-array in struct SISLANDS_SMC_SWSTATE") Cc: [email protected] Reported-by: Kai-Heng Feng <[email protected]> Tested-by: Kai-Heng Feng <[email protected]> Signed-off-by: Gustavo A. R. Silva <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-10drm/radeon/ni_dpm: Fix booting bugGustavo A. R. Silva2-84/+94
Create new structure NISLANDS_SMC_SWSTATE_SINGLE, as initialState.levels and ACPIState.levels are never actually used as flexible arrays. Those arrays can be used as simple objects of type NISLANDS_SMC_HW_PERFORMANCE_LEVEL, instead. Currently, the code fails because flexible array _levels_ in struct NISLANDS_SMC_SWSTATE doesn't allow for code that access the first element of initialState.levels and ACPIState.levels arrays: drivers/gpu/drm/radeon/ni_dpm.c: 1690 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = 1691 cpu_to_be32(ni_pi->clock_registers.mpll_ad_func_cntl); ... 1903: table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); 1904: table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2); because such element cannot exist without previously allocating any dynamic memory for it (which never actually happens). That's why struct NISLANDS_SMC_SWSTATE should only be used as type for object driverState and new struct SISLANDS_SMC_SWSTATE_SINGLE is created as type for objects initialState, ACPIState and ULVState. Also, with the change from one-element array to flexible-array member in commit 434fb1e7444a ("drm/radeon/nislands_smc.h: Replace one-element array with flexible-array member in struct NISLANDS_SMC_SWSTATE"), the size of dpmLevels in struct NISLANDS_SMC_STATETABLE should be fixed to be NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE instead of NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1. Bug: https://lore.kernel.org/dri-devel/[email protected]/ Fixes: 434fb1e7444a ("drm/radeon/nislands_smc.h: Replace one-element array with flexible-array member in struct NISLANDS_SMC_SWSTATE") Cc: [email protected] Reported-by: Christian Zigotzky <[email protected]> Tested-by: Christian Zigotzky <[email protected]> Link: https://lore.kernel.org/dri-devel/[email protected]/ Signed-off-by: Gustavo A. R. Silva <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-10drm/amd/amdgpu: Fix errors in function documentationDwaipayan Ray1-0/+3
Fix a couple of syntax errors and removed one excess parameter in the function documentations which lead to kernel docs build warning. Reviewed-by: Christian König <[email protected]> Signed-off-by: Dwaipayan Ray <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-10drm/amd/display: remove unused function dc_link_perform_link_trainingRouven Czerwinski2-16/+0
This function is not used anywhere, remove it. It was added in 40dd6bd376a4 ("drm/amd/display: Linux Set/Read link rate and lane count through debugfs") and moved in fe798de53a7a ("drm/amd/display: Move link functions from dc to dc_link"), but a user is missing. Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Rouven Czerwinski <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-10drm/amdgpu: add function to clear MMEA error status for aldebaranDennis Li3-0/+24
For aldebaran, hardware will not clear error status automatically when reading error status register, insteadly driver should set clear bit of the error status register explicitly to clear error status. Signed-off-by: Dennis Li <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-10drm/amdgpu: correct the funtion to clear GCEA error statusDennis Li1-1/+4
The bit 11 of GCEA_ERR_STATUS register is used to clear GCEA error status. Signed-off-by: Dennis Li <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-10drm/amd/display: 3.2.135.1Aric Cyr1-1/+1
- adding missed FW promotion Signed-off-by: Aric Cyr <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-10drm/amd/display: [FW Promotion] Release 0.0.65Anthony Koo1-7/+116
- Implement INBOX0 messaging for HW lock Signed-off-by: Anthony Koo <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-10drm/amd/display: 3.2.135Aric Cyr1-1/+1
Signed-off-by: Aric Cyr <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-10drm/amd/display: fix use_max_lb flag for 420 pixel formatsDmytro Laktyushkin1-3/+6
Right now the flag simply selects memory config 0 when flag is true however 420 modes benefit more from memory config 3. Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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