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2021-04-09drm/amdgpu: split umc callbacks to ras and non-ras onesHawking Zhang12-32/+51
umc ras is not managed by gpu driver when gpu is connected to cpu through xgmi. split umc callbacks into ras and non-ras ones so gpu driver only initializes umc ras callbacks when it manages umc ras. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amdgpu: move xgmi ras functions to xgmi_ras_funcsHawking Zhang6-17/+42
xgmi ras is not managed by gpu driver when gpu is connected to cpu through xgmi. move all xgmi ras functions to xgmi_ras_funcs so gpu driver only initializes xgmi ras functions when it manages xgmi ras. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amdgpu: split nbio callbacks into ras and non-ras onesHawking Zhang6-30/+63
nbio ras is not managed by gpu driver when gpu is connected to cpu through xgmi. split nbio callbacks into ras and non-ras ones so gpu driver only initializes nbio ras callbacks when it manages nbio ras. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amdgpu: implement query_ras_error_address callbackHawking Zhang1-0/+90
query_ras_error_address will be invoked to query bad page address when there is poison data in HBM consumed by GPU engines. Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amdgpu: implement umc query error count callbackHawking Zhang2-0/+92
umc query_ras_error_count will be invoked to query umc correctable and uncorrectable error. It will reset the umc ras error counter after the query. Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amdgpu: add helper funtion to query umc ras errorHawking Zhang2-0/+77
Add helper functions to query correctable and uncorrectable umc ras error. Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amdgpu: create umc_v6_7_funcs for aldebaranHawking Zhang3-1/+58
umc_v6_7_funcs are callbacks to support umc ras functionalities in aldebaran Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amdgpu: initialze ras caps per paltform configHawking Zhang1-12/+23
Driver only manages GFX/SDMA/MMHUB RAS in platforms that gpu node is connected to cpu through XGMI, other than that, it queries VBIOS for RAS capabilities. Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amdkfd: Avoid null pointer in SMI eventAmber Lin1-1/+1
Power Management IP is initialized/enabled before KFD init. When a thermal throttling happens before kfd_smi_init is done, calling the KFD SMI update function causes a stack dump by referring a NULL pointer ( smi_clients list). Check if kfd_init is completed before calling the function. Signed-off-by: Amber Lin <[email protected]> Reviewed-by: Mukul Joshi <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09amd: display: modules: Remove repeated struct declarationWan Jiabing1-2/+0
struct mod_hdcp is declared twice. One is declared at 33rd line. The blew one is not needed. Remove the duplicate. Signed-off-by: Wan Jiabing <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amdgpu: drop some unused atombios functionsAlex Deucher2-163/+0
These were leftover from the old CI dpm code which was retired a while ago. Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amd: cleanup coding style a bitBernard Zhao1-4/+3
Fix patch check warning: WARNING: suspect code indent for conditional statements (8, 17) + if (obj && obj->use < 0) { + DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", obj->head.name); WARNING: braces {} are not necessary for single statement blocks + if (obj && obj->use < 0) { + DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", obj->head.name); + } Signed-off-by: Bernard Zhao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amd: use kmalloc_array over kmalloc with multiplyBernard Zhao1-1/+1
Fix patch check warning: WARNING: Prefer kmalloc_array over kmalloc with multiply + buf = kmalloc(MAX_KFIFO_SIZE * sizeof(*buf), GFP_KERNEL); Signed-off-by: Bernard Zhao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amdgpu: support sdma error injectionStanley.Yang1-0/+1
Signed-off-by: Stanley.Yang <[email protected]> Reivewed-by: Dennis Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amdgpu: reserve fence slot to update page tablePhilip Yang1-2/+8
Forgot to reserve a fence slot to use sdma to update page table, cause below kernel BUG backtrace to handle vm retry fault while application is exiting. [ 133.048143] kernel BUG at /home/yangp/git/compute_staging/kernel/drivers/dma-buf/dma-resv.c:281! [ 133.048487] Workqueue: events amdgpu_irq_handle_ih1 [amdgpu] [ 133.048506] RIP: 0010:dma_resv_add_shared_fence+0x204/0x280 [ 133.048672] amdgpu_vm_sdma_commit+0x134/0x220 [amdgpu] [ 133.048788] amdgpu_vm_bo_update_range+0x220/0x250 [amdgpu] [ 133.048905] amdgpu_vm_handle_fault+0x202/0x370 [amdgpu] [ 133.049031] gmc_v9_0_process_interrupt+0x1ab/0x310 [amdgpu] [ 133.049165] ? kgd2kfd_interrupt+0x9a/0x180 [amdgpu] [ 133.049289] ? amdgpu_irq_dispatch+0xb6/0x240 [amdgpu] [ 133.049408] amdgpu_irq_dispatch+0xb6/0x240 [amdgpu] [ 133.049534] amdgpu_ih_process+0x9b/0x1c0 [amdgpu] [ 133.049657] amdgpu_irq_handle_ih1+0x21/0x60 [amdgpu] [ 133.049669] process_one_work+0x29f/0x640 [ 133.049678] worker_thread+0x39/0x3f0 [ 133.049685] ? process_one_work+0x640/0x640 Signed-off-by: Philip Yang <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amdgpu: indirect register access for nv12 sriovPeng Ju Zhou5-63/+164
1. expand rlcg interface for gc & mmhub indirect access 2. add rlcg interface for no kiq v2: squash in fix for gfx9 (Changfeng) Signed-off-by: Peng Ju Zhou <[email protected]> Reviewed-by: Emily.Deng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amdgpu: indirect register access for nv12 sriovPeng Ju Zhou2-0/+19
using the control bits got from host to control registers access. Signed-off-by: Peng Ju Zhou <[email protected]> Reviewed-by: Emily.Deng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amdgpu: indirect register access for nv12 sriovPeng Ju Zhou2-0/+13
get pf2vf msg info at it's earliest time so that guest driver can use these info to decide whether register indirect access enabled. Signed-off-by: Peng Ju Zhou <[email protected]> Reviewed-by: Emily.Deng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amdgpu: indirect register access for nv12 sriovPeng Ju Zhou1-3/+3
unify host driver and guest driver indirect access control bits names Signed-off-by: Peng Ju Zhou <[email protected]> Reviewed-by: Emily.Deng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amdgpu/display: fix warning on 32 bit in dmubAlex Deucher1-1/+1
Use uintptr_t rather than uint64_t. Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: Dave Airlie <[email protected]> Cc: Harry Wentland <[email protected]>
2021-04-09drm/amdgpu: check alignment on CPU page for bo mapXℹ Ruoyao1-4/+4
The page table of AMDGPU requires an alignment to CPU page so we should check ioctl parameters for it. Return -EINVAL if some parameter is unaligned to CPU page, instead of corrupt the page table sliently. Reviewed-by: Christian König <[email protected]> Signed-off-by: Xi Ruoyao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amdgpu: Set a suitable dev_info.gart_page_sizeHuacai Chen1-2/+2
In Mesa, dev_info.gart_page_size is used for alignment and it was set to AMDGPU_GPU_PAGE_SIZE(4KB). However, the page table of AMDGPU driver requires an alignment on CPU pages. So, for non-4KB page system, gart_page_size should be max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE). Signed-off-by: Rui Wang <[email protected]> Signed-off-by: Huacai Chen <[email protected]> Link: https://github.com/loongson-community/linux-stable/commit/caa9c0a1 [Xi: rebased for drm-next, use max_t for checkpatch, and reworded commit message.] Signed-off-by: Xi Ruoyao <[email protected]> BugLink: https://gitlab.freedesktop.org/drm/amd/-/issues/1549 Tested-by: Dan Horák <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/radeon: avoid potential null pointer accessGuchun Chen1-1/+1
Leverage the same logic from amdgpu_ttm_tt_unpin_userptr. Signed-off-by: Guchun Chen <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amdgpu: fix compiler warning(v2)Guchun Chen1-3/+1
warning: ISO C90 forbids mixed declarations and code [-Wdeclaration-after-statement] int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); v2: put short variable declaration last Signed-off-by: Guchun Chen <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amdgpu: fix NULL pointer dereferenceGuchun Chen1-1/+1
ttm->sg needs to be checked before accessing its child member. Call Trace: amdgpu_ttm_backend_destroy+0x12/0x70 [amdgpu] ttm_bo_cleanup_memtype_use+0x3a/0x60 [ttm] ttm_bo_release+0x17d/0x300 [ttm] amdgpu_bo_unref+0x1a/0x30 [amdgpu] amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu+0x78b/0x8b0 [amdgpu] kfd_ioctl_alloc_memory_of_gpu+0x118/0x220 [amdgpu] kfd_ioctl+0x222/0x400 [amdgpu] ? kfd_dev_is_large_bar+0x90/0x90 [amdgpu] __x64_sys_ioctl+0x8e/0xd0 ? __context_tracking_exit+0x52/0x90 do_syscall_64+0x33/0x80 entry_SYSCALL_64_after_hwframe+0x44/0xa9 RIP: 0033:0x7f97f264d317 Code: b3 66 90 48 8b 05 71 4b 2d 00 64 c7 00 26 00 00 00 48 c7 c0 ff ff ff ff c3 66 2e 0f 1f 84 00 00 00 00 00 b8 10 00 00 00 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 41 4b 2d 00 f7 d8 64 89 01 48 RSP: 002b:00007ffdb402c338 EFLAGS: 00000246 ORIG_RAX: 0000000000000010 RAX: ffffffffffffffda RBX: 00007f97f3cc63a0 RCX: 00007f97f264d317 RDX: 00007ffdb402c380 RSI: 00000000c0284b16 RDI: 0000000000000003 RBP: 00007ffdb402c380 R08: 00007ffdb402c428 R09: 00000000c4000004 R10: 00000000c4000004 R11: 0000000000000246 R12: 00000000c0284b16 R13: 0000000000000003 R14: 00007f97f3cc63a0 R15: 00007f8836200000 Signed-off-by: Guchun Chen <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amd/display: Use pr_debug in DM to prevent dmesg floodingVictor Lu2-10/+13
[why] Our CI enables drm.debug=0x4 logs and the dmesg is flooded with cursor updates. We probably want to avoid spamming the log with DRM_DEBUG_KMS. [how] Define and use pr_debug macros instead of a few spammy DRM_DEBUG_*'s. Signed-off-by: Victor Lu <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amd/display: add DMCUB trace irq support for DCN302Guchun Chen1-0/+30
Otherwise, below errors will be found on DIMGREY_CAVEFISH with DCN302. Error log observed in driver load: [drm:amdgpu_dm_irq_register_interrupt [amdgpu]] *ERROR* DM_IRQ: invalid irq_source: 0! Error observed in mode1_rest sequence: [ 27.265920] #PF: supervisor read access in kernel mode [ 27.265941] #PF: error_code(0x0000) - not-present page [ 27.265956] PGD 0 P4D 0 [ 27.265967] Oops: 0000 [#1] SMP NOPTI [ 27.265979] CPU: 0 PID: 1360 Comm: cat Tainted: G W 5.11.0-99b3786c1770 #20210323 [ 27.266005] Hardware name: System manufacturer System Product Name/PRIME Z390-A, BIOS 1401 11/26/2019 [ 27.266033] RIP: 0010:dal_irq_service_ack+0x25/0x60 [amdgpu] [ 27.266203] Code: 5d 5d c3 66 90 0f 1f 44 00 00 55 83 fe 61 48 89 e5 77 27 89 f0 48 8d 04 40 48 c1 e0 04 48 03 47 08 74 17 48 8b 50 28 48 89 c6 <48> 8b 52 08 48 85 d2 74 20 e8 1d 64 45 c9 5d c3 89 f2 48 c7 c7 f0 [ 27.266248] RSP: 0018:ffffa115824a3c08 EFLAGS: 00010082 [ 27.266270] RAX: ffffffffc0942c10 RBX: ffffffffc0942c10 RCX: 0000000000000000 [ 27.266288] RDX: 0000000000000000 RSI: ffffffffc0942c10 RDI: ffff88d509cba7a0 [ 27.266312] RBP: ffffa115824a3c08 R08: 0000000000000000 R09: 0000000000000001 [ 27.266335] R10: ffffa115824a3b20 R11: ffffa115824a3b58 R12: ffff88d509cba7a0 [ 27.266353] R13: 0000000000000000 R14: 0000000000000000 R15: 0000000000000246 [ 27.266377] FS: 00007fb3e2438580(0000) GS:ffff88d50dc00000(0000) knlGS:0000000000000000 [ 27.266402] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 27.266417] CR2: 0000000000000008 CR3: 000000083e5ac006 CR4: 00000000003706f0 [ 27.266441] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [ 27.266464] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 [ 27.266483] Call Trace: [ 27.266491] dal_irq_service_set+0x31/0x80 [amdgpu] [ 27.266639] dc_interrupt_set+0x24/0x30 [amdgpu] [ 27.266775] amdgpu_dm_set_dmub_trace_irq_state+0x22/0x30 [amdgpu] [ 27.266920] amdgpu_irq_update+0x57/0xa0 [amdgpu] [ 27.267030] amdgpu_irq_gpu_reset_resume_helper+0x64/0xa0 [amdgpu] [ 27.267135] amdgpu_do_asic_reset+0x211/0x420 [amdgpu] [ 27.267232] amdgpu_device_gpu_recover+0x517/0xa70 [amdgpu] [ 27.267325] gpu_recover_get+0x2e/0x60 [amdgpu] [ 27.267421] simple_attr_read+0x6b/0x130 [ 27.267441] debugfs_attr_read+0x49/0x70 [ 27.267454] full_proxy_read+0x5c/0x90 [ 27.267474] vfs_read+0xa1/0x190 [ 27.267486] ksys_read+0xa7/0xe0 [ 27.267501] __x64_sys_read+0x1a/0x20 [ 27.267521] do_syscall_64+0x37/0x80 [ 27.267541] entry_SYSCALL_64_after_hwframe+0x44/0xa9 [ 27.267562] RIP: 0033:0x7fb3e2356142 Signed-off-by: Guchun Chen <[email protected]> Reviewed-by: Leo (Hanghong) Ma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amdgpu: Add new PF2VF flags for VF register access methodRohit Khaire2-2/+26
Add 3 sub flags to notify guest for indirect reg access of gc, mmhub and ih The host sets these flags depending on L1 RAP version, asic and other scenarios. These flags ensure that there is compatibility between different guest/host/vbios versions. Signed-off-by: Rohit Khaire <[email protected]> Reviewed-by: Monk Liu <[email protected]> Acked-by: Alex Deucher <[email protected]> Acked-by: Luben Tuikov <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amdgpu/vangogh: don't check for dpm in is_dpm_running when in suspendAlex Deucher1-0/+5
Do the same thing we do for Renoir. We can check, but since the sbios has started DPM, it will always return true which causes the driver to skip some of the SMU init when it shouldn't. Reviewed-by: Zhan Liu <[email protected]> Acked-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amd/display: fix typo: liason -> liaisonDiego Viola1-1/+1
Signed-off-by: Diego Viola <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amd/display: Try YCbCr420 color when YCbCr444 failsWerner Sembach1-0/+9
When encoder validation of a display mode fails, retry with less bandwidth heavy YCbCr420 color mode, if available. This enables some HDMI 1.4 setups to support 4k60Hz output, which previously failed silently. On some setups, while the monitor and the gpu support display modes with pixel clocks of up to 600MHz, the link encoder might not. This prevents YCbCr444 and RGB encoding for 4k60Hz, but YCbCr420 encoding might still be possible. However, which color mode is used is decided before the link encoder capabilities are checked. This patch fixes the problem by retrying to find a display mode with YCbCr420 enforced and using it, if it is valid. Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Werner Sembach <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amd/display: 3.2.129Aric Cyr1-1/+1
This version brings along following features/fixes: - LTTPR improvements - Disable MALL when SMU not present - Fix bug in HW that causes P-State to hang when DPG is enabled in certain conditions - Update code path for enabling DPG - Update display endpoint control path - Add dynamic link encoder selection - Fix debugfs MST topology to dump from the root MST node - Enable DP DSC Compliance automation for Linux - ASSR is enabled only when DPCD is supported and the display connected is internal - Added kernel trace event to print real-time refresh rate value to debug VRR issues Signed-off-by: Aric Cyr <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Dan Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amd/display: Disable MALL when SMU not presentChris Park3-0/+14
[Why] Bring-up purpose code to disable DMUB calling into SMU and timeout for MALL when SMU is not present. [How] Disable MALL when SMU is not present. Signed-off-by: Chris Park <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Dan Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amd/display: [FW Promotion] Release 0.0.58Anthony Koo1-2/+2
Signed-off-by: Anthony Koo <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Dan Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amd/display: add log for automated testQingqing Zhuo1-0/+4
[Why&How] Add log for easier debug purposes. Signed-off-by: Qingqing Zhuo <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Dan Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amd/display: Set max TTU on DPG enableWesley Chalmers2-7/+25
[WHY] There is a bug in HW that causes P-State to hang when DPG is enabled in certain conditions. [HOW] The solution is to force MIN_TTU_VBLANK register to maximum value whenever DPG has been enabled. Make stream do a full update on test pattern change, so that the TTUs get updated. When DPG is enabled, update the ttu_regs.min_ttu_vblank field of each pipe in the stream's topology to the maximum value (0xffffff). v2: squash in build fix for when DCN is not defined (Alex) Signed-off-by: Wesley Chalmers <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Dan Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amd/display: New path for enabling DPGWesley Chalmers2-0/+23
[WHY] We want to make enabling test pattern a part of the stream update code path. This change is the first step towards that goal. Signed-off-by: Wesley Chalmers <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Dan Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amd/display: Update display endpoint control path.Jimmy Kizito4-8/+146
[Why] Some display endpoints may be dynamically mapped to the link encoders which drive them. [How] Update the code paths for display enabling/disabling to accommodate the dynamic association between links and link encoders. Signed-off-by: Jimmy Kizito <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Dan Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amd/display: Add dynamic link encoder selection.Jimmy Kizito11-7/+366
[Why] Some display endpoints may be programmably mapped to compatible link encoders. The assignment of link encoders to links has to be dynamic to accommodate the increased flexibility in comparison to conventional display endpoints. [How] - Add link encoder assignment tracking variables. - Execute link encoder assignment algorithm before enabling link and release link encoders from links once they are disabled. Signed-off-by: Jimmy Kizito <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Dan Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amd/display: Fix MST topology debugfsEryk Brol1-0/+4
[why] The drm dump_topology function was previously called on all DP connectors. This resulted in empty topology dumps for those connectors which weren't root MST nodes. [how] Make sure we only dump topology from the root MST node. Signed-off-by: Eryk Brol <[email protected]> Reviewed-by: Aurabindo Jayamohanan Pillai <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Dan Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amd/display: LTTPR config logicWesley Chalmers1-10/+41
[WHY] Some systems can enable LTTPR through bits in BIOS, while other systems can be configured at boot to enable LTTPR. Some configs enable Non-Transparent mode, while others enable Transparent mode. Signed-off-by: Wesley Chalmers <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Dan Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amd/display: Enumerate LTTPR modesWesley Chalmers3-12/+32
[WHY] There are three possible modes for LTTPR: - Non-LTTPR mode, where AUX timeout is 400 us and no per-hop link training is done - LTTPR Transparent mode, where AUX timeout is 3200 us and no per-hop link training is done - LTTPR Non-Transparent mode, where AUX timeout is 3200 us and per-hop link training is done [HOW] Use an enum instead of a bool to track LTTPR state; modify comparisons accordingly. Signed-off-by: Wesley Chalmers <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Dan Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amd/display: Interface for LTTPR interopWesley Chalmers3-12/+67
[WHY] The logic to toggle LTTPR transparent/non-transparent requires 2 flags provided by BIOS [HOW] Repurpose the interface to get dce caps so both LTTPR querying functions can use them. Signed-off-by: Wesley Chalmers <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Dan Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amd/display: Rename fs_params to hdr_tm_paramsKrunoslav Kovac2-5/+5
[Why&How] Renaming structure to better indicate its meaning. Signed-off-by: Krunoslav Kovac <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Anson Jacob <[email protected]> Acked-by: Anthony Koo <[email protected]> Tested-by: Dan Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amd/display: Fix typo for variable nameVladimir Stempen1-5/+5
[why] Word "remainder" was misspelled as "reminder" in reduceSizeAndFraction method variable. [how] Fix the spelling. Signed-off-by: Vladimir Stempen <[email protected]> Reviewed-by: Alexander Deucher <[email protected]> Reviewed-by: Bindu R <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Dan Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amd/display: add mod hdcp interface for supporting encryption state queryWenjing Liu7-29/+54
Signed-off-by: Wenjing Liu <[email protected]> Reviewed-by: George Shen <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Dan Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amd/display: define mod_hdcp_display_disable_option structWenjing Liu3-7/+13
Signed-off-by: Wenjing Liu <[email protected]> Reviewed-by: George Shen <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Dan Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amd/display: enable DP DSC Compliance automationQingqing Zhuo1-0/+40
[Why] Color depth data is not parsed during test requests. [How] Update display color depth according to color depth request from the test equipment. Signed-off-by: Qingqing Zhuo <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Dan Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amd/display: Guard ASSR with internal display flagStylon Wang1-17/+41
[Why] ASSR enabling only considers capability declared in DPCD. We also need to check whether the connector is internal. [How] ASSR enabling need to check both DPCD capability and internal display flag. Signed-off-by: Stylon Wang <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Dan Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amd/display: Fix static checker warnings on tracebuff_fbLeo (Hanghong) Ma1-74/+68
[Why] Static analysis on linux-next has found a potential null pointer dereference; [How] Refactor the function, add ASSERT and remove the unnecessary check. Signed-off-by: Leo (Hanghong) Ma <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Dan Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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