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Signed-off-by: Kuninori Morimoto <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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Current Koelsch I2C2 has 400kHz settings,
but, ak4643 audio codec chip which is connected to I2C2 can't
work such frequency.
Fixup I2C2 clock frequency to 100kHz.
Signed-off-by: Kuninori Morimoto <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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DMA transfer uses DVC
DMA DMApp
[MEM] -> [SRC] -> [DVC] -> [SSIU] -> [SSI]
DMA DMApp
[MEM] <- [DVC] <- [SRC] <- [SSIU] <- [SSI]
Signed-off-by: Kuninori Morimoto <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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DMA transfer to/from SRC
DMA DMApp
[MEM] -> [SRC] -> [SSIU] -> [SSI]
DMA DMApp
[MEM] <- [SRC] <- [SSIU] <- [SSI]
Current sound driver is supporting
SSI/SRC random connection.
So, this patch is tring
SSI0 -> SRC2
SSI1 <- SRC3
Signed-off-by: Kuninori Morimoto <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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DMA transfer to/from SSIU
DMA
[MEM] -> [SSIU] -> [SSI]
DMA
[MEM] <- [SSIU] <- [SSI]
Signed-off-by: Kuninori Morimoto <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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DMA transfer to/from SSI
DMA
[MEM] -> [SSI]
DMA
[MEM] <- [SSI]
Signed-off-by: Kuninori Morimoto <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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Signed-off-by: Kuninori Morimoto <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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Current Lager IIC2 is using default clock frequency,
but, ak4643 audio codec chip needs 100kHz
This patch clarifies IIC2 clock frequency as 100kHz.
Signed-off-by: Kuninori Morimoto <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
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Enable usb1 on Google Chromecast which is connected to micro-USB
plug used for external power supply, too.
Signed-off-by: Antoine Tenart <[email protected]>
Signed-off-by: Sebastian Hesselbarth <[email protected]>
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Adds nodes describing the Marvell Berlin BG2CD USB PHY and USB. The BG2CD
SoC has 2 USB ChipIdea controllers, with usb0 host-only and usb1 dual-role
capable.
Signed-off-by: Antoine Tenart <[email protected]>
Signed-off-by: Sebastian Hesselbarth <[email protected]>
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Enable the 2 available USB PHY and USB nodes on the Marvell Berlin BG2Q
DMP.
Signed-off-by: Antoine Tenart <[email protected]>
Signed-off-by: Sebastian Hesselbarth <[email protected]>
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Adds nodes describing the Marvell Berlin BG2Q USB PHY and USB. The BG2Q
SoC has 3 USB host controller, compatible with ChipIdea.
Signed-off-by: Antoine Tenart <[email protected]>
Signed-off-by: Sebastian Hesselbarth <[email protected]>
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Add nodes for I2C controllers A,B,AO, which are available in both
Meson6 and Meson8.
Signed-off-by: Beniamino Galvani <[email protected]>
Signed-off-by: Carlo Caione <[email protected]>
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This enables the L2 cache controller available in Amlogic SoCs.
Signed-off-by: Beniamino Galvani <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Signed-off-by: Carlo Caione <[email protected]>
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This adds a dtsi for Amlogic Meson8 SoCs. It differs from the Meson6
dtsi for the number of Cortex-A9 cores (4 vs 2) and for the frequency
of clk81.
Signed-off-by: Beniamino Galvani <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Signed-off-by: Carlo Caione <[email protected]>
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The board DTS is missing the machine compatible.
Signed-off-by: Carlo Caione <[email protected]>
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Following Arnds review comments, update the miphy365 to follow the
common convention of naming the phy node names as phy@addr.
Signed-off-by: Peter Griffin <[email protected]>
Suggested-by: Arnd Bergmann <[email protected]>
Signed-off-by: Maxime Coquelin <[email protected]>
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At the moment we don't take a reference on some core interconnect
clocks which means when CCF turns off unused clocks the SoC will
hang. As a temp soltuion we will boot with clk_ignore_unused
parameter for all b2120 boards.
Signed-off-by: Peter Griffin <[email protected]>
Acked-by: Lee Jones <[email protected]>
Signed-off-by: Maxime Coquelin <[email protected]>
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The STiH410 is an advanced multi-HD AVC processor with 3D graphics acceleration
and 1.5-GHz ARM Cortex-A9 SMP CPU part of the stih407 family.
It has wide connectivity including USB 3.0, PCI-e, SATA and gigabit ethernet.
Signed-off-by: Peter Griffin <[email protected]>
Signed-off-by: Maxime Coquelin <[email protected]>
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The stih410 soc which will be added in the following commit is very similar to
the stih407, to enable maximum re-use of the dt files this commit abstracts the
common parts into a shared dt file stihxxx-b2120 for the board, and also a shared
file stih407-family.dtsi for the SoC.
Signed-off-by: Peter Griffin <[email protected]>
Signed-off-by: Maxime Coquelin <[email protected]>
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This patch adds the required pin configiguration for the extra usb
controllers found on the stih410 device.
Signed-off-by: Peter Griffin <[email protected]>
Signed-off-by: Maxime Coquelin <[email protected]>
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Although most clock outputs are the same as stih407 SoC, stih410
also has some additional new clock outputs.
Signed-off-by: Peter Griffin <[email protected]>
Acked-by: Lee Jones <[email protected]>
Signed-off-by: Maxime Coquelin <[email protected]>
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This patch adds the DT nodes for the 4 usb ehci and ohci usb controllers
on the stih416 SoC.
Signed-off-by: Peter Griffin <[email protected]>
Signed-off-by: Maxime Coquelin <[email protected]>
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This usb picophy is found on stih415/6 SoC.
Signed-off-by: Peter Griffin <[email protected]>
Signed-off-by: Maxime Coquelin <[email protected]>
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This patch adds the required pin config for all usb controllers
on the stih416.
Signed-off-by: Peter Griffin <[email protected]>
Acked-by: Lee Jones <[email protected]>
Signed-off-by: Maxime Coquelin <[email protected]>
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The Mele M9 has an ethernet board, enable it.
Signed-off-by: Hans de Goede <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
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PLL6 on sun6i has multiple outputs, just like the other sunxi platforms.
Signed-off-by: Chen-Yu Tsai <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
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This enables user space access to the 3 PWM available on the Radxa Rock headers.
Signed-off-by: Julien CHAUVEAU <[email protected]>
Signed-off-by: Heiko Stuebner <[email protected]>
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This adds a DT binding documentation for the MT6592 SoC from Mediatek.
Signed-off-by: Howard Chen <[email protected]>
Signed-off-by: Matthias Brugger <[email protected]>
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The mt6592-evb is an evaluation board based on the MT6592 SoC.
Signed-off-by: Howard Chen <[email protected]>
Signed-off-by: Matthias Brugger <[email protected]>
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* A dtsi for boards based on Mediatek MT6592 SoCs
* Compatible string in arch/arm/mach-mediatek/mediatek.c
Signed-off-by: Howard Chen <[email protected]>
Signed-off-by: Matthias Brugger <[email protected]>
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Add MT8127 & MT8135 from Mediatek.
Signed-off-by: Joe.C <[email protected]>
Signed-off-by: Matthias Brugger <[email protected]>
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This allows the "make dtbs" to build the moose and mt8135-evbp1
for MediaTek SoC
Signed-off-by: Joe.C <[email protected]>
Signed-off-by: Matthias Brugger <[email protected]>
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This appears to be the best match for ePAPR.
Signed-off-by: Simon Horman <[email protected]>
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This appears to be the best match for ePAPR.
Signed-off-by: Simon Horman <[email protected]>
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This appears to be the best match for ePAPR.
Signed-off-by: Simon Horman <[email protected]>
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This appears to be the best match for ePAPR.
Signed-off-by: Simon Horman <[email protected]>
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The Mele M9 / A1000G quad has a blue status led, add support for this.
Signed-off-by: Hans de Goede <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
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The Mele M9 / A1000G quad uses both usb-ports, one goes to an internal
usb wifi card, the other to a build-in usb-hub, so neither need their
OHCI companion controller to be enabled since the are always connected at
USB-2 speeds.
The controller which is attached to the wifi also does not need a vbus
regulator.
Signed-off-by: Hans de Goede <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
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This avoids it getting briefly turned off between when the regulator getting
registered and the ahci driver turning it back on, thus avoiding the disk
going into emergency head park mode.
Reported-by: Bruno Prémont <[email protected]>
Tested-by: Bruno Prémont <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
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Unit addresses, whilst written in hex, don't contain a 0x prefix.
Signed-off-by: Julien CHAUVEAU <[email protected]>
Signed-off-by: Heiko Stuebner <[email protected]>
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Signed-off-by: Roman Byshko <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
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Cubietruck uses different pin for the USB OTG VBUS that
is why we override the one defined in sunxi-common-regulators.dtsi
Signed-off-by: Roman Byshko <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
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Signed-off-by: Roman Byshko <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
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Until now the regulator nodes for powering USB VBUS
existed only for the two host controllers. Now the regulator
is added for USB OTG too.
Signed-off-by: Roman Byshko <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
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Evbp1 is a tablet evaluation board based on MT8135 SoC.
Signed-off-by: Joe.C <[email protected]>
Signed-off-by: Matthias Brugger <[email protected]>
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This adds a basic dtsi for MT8135 based SoC.
Signed-off-by: Joe.C <[email protected]>
Signed-off-by: Matthias Brugger <[email protected]>
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Moose is a tablet evalutation board based on MT8127 SoC.
Signed-off-by: Joe.C <[email protected]>
Signed-off-by: Matthias Brugger <[email protected]>
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This adds a basic dtsi for MT8127 SoC.
Signed-off-by: Joe.C <[email protected]>
Signed-off-by: Matthias Brugger <[email protected]>
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