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2017-07-25drm/amdgpu/gmc6: disable legacy vga features in gmc init (v2)Alex Deucher1-1/+13
Needs to be done when the MC is set up. v2: make consistent with other asics Acked-by: Christian König <[email protected]> Acked-by: Harry Wentland <[email protected]> Reviewed-by: Junwei Zhang <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-07-25drm/radeon: Set depth on low mem to 16 bpp instead of 8 bppEgbert Eich1-2/+5
The radeon driver reduces the framebuffer resolution to 8bpp if a device with less than 32MB VRAM is found. This causes the framebuffer to run in 8 bit paletted mode. For a text console this is not an issue as 256 different colors is more than one gets on a VGA text console. However this leads to a poor 8bit pseudo-color visual when running X on fbdev, too, which is quite ugly. In this patch, we try to give some moderate compromise: limit the framebuffer bpp to 8 only when VRAM is 8MB or less, and use 16 bpp otherwise for 32MB or less VRAM. Reviewed-by: Michel Dänzer <[email protected]> Signed-off-by: Egbert Eich <[email protected]> Signed-off-by: Takashi Iwai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-07-25drm/amdgpu: fix the incorrect scratch reg number on gfx v6Huang Rui1-1/+1
Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Junwei Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-07-25drm/amdgpu: fix the incorrect scratch reg number on gfx v7Huang Rui1-1/+1
Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Junwei Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-07-25drm/amdgpu: fix the incorrect scratch reg number on gfx v8Huang Rui1-1/+1
Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Junwei Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-07-25drm/amdgpu: fix the incorrect scratch reg number on gfx v9Huang Rui1-1/+1
Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Junwei Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-07-25drm/amd/powerplay: add support for 3DP 4K@120Hz on vega10.Rex Zhu1-8/+80
Signed-off-by: Rex Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-07-25drm/amdgpu: enable huge page handling in the VM v5Alex Deucher2-20/+104
The hardware can use huge pages to map 2MB of address space with only one PDE. v2: few cleanups and rebased v3: skip PT updates if we are using the PDE v4: rebased, added support for CPU based updates v5: fix CPU based updates once more v6: fix ndw estimation Signed-off-by: Christian König <[email protected]> Reviewed-and-tested-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-07-25drm/amdgpu: increase fragmentation size for Vega10 v2Christian König5-7/+15
The fragment bits work differently for Vega10 compared to previous generations. Increase the fragment size to 2MB for now to better handle that. v2: handle the hardware setup as well Signed-off-by: Christian König <[email protected]> Reviewed-and-tested-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-07-25drm/amdgpu: ttm_bind only when user needs gpu_addr in bo pinChunming Zhou1-6/+7
Signed-off-by: Chunming Zhou <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-07-25drm/amdgpu: correct clock info for SRIOVXiangliang Yu1-2/+2
Currently, get clock info from default clk of pm if dpm is disable. Buf SRIOV doesn't support dpm and pm, can't get anything from pm. Only get clock info only from default clk of amdgpu for SRIOV. And driver get pm default clk also from amdgpu default clk and never be changed by others. So use amdgpu default clk value for SRIOV and non-dpm cases. Signed-off-by: Xiangliang Yu <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-07-25drm/amdgpu/gmc8: SRIOV need to program fb locationEmily Deng1-1/+15
SRIOV won't do vbios post in guest OS, and the mmMC_VM_FB_LOCATION is pf and vf copy, so still need to program fb location for SRIOV. v2: No need to stop mc, and update gmc_v8_0_vram_gtt_location as well. v3: New line after the stack variables BUG: SWDEV-126629 Signed-off-by: Emily Deng <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-07-25drm/amdgpu: disable firmware loading for psp v10Junwei Zhang1-0/+2
Now asd firmware is not ready for psp v10, will enable it when it's available Signed-off-by: Junwei Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-07-25drm/amdgpu:fix gfx fence allocate sizeMonk Liu3-8/+52
1, for sriov, we need 8dw for the gfx fence due to CP behaviour 2, cleanup wrong logic in wptr/rptr wb alloc and free Change-Id: Ifbfed17a4621dae57244942ffac7de1743de0294 Signed-off-by: Monk Liu <[email protected]> Signed-off-by: Xiangliang Yu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-07-25drm/amdgpu: Implement ttm_bo_driver.access_memory callback v2Felix Kuehling1-0/+62
Allows gdb to access contents of user mode mapped VRAM BOs. v2: return error for non-VRAM pools Signed-off-by: Felix Kuehling <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-07-25drm/ttm: Implement vm_operations_struct.access v2Felix Kuehling2-1/+95
Allows gdb to access contents of user mode mapped BOs. System memory is handled by TTM using kmap. Other memory pools require a new driver callback in ttm_bo_driver. v2: * kmap only one page at a time * swap in BO if needed * make driver callback more generic to handle private memory pools * document callback return value * WARN_ON -> WARN_ON_ONCE Signed-off-by: Felix Kuehling <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-07-25drm/amd/powerplay: fix AVFS voltage offset for Vega10Eric Huang1-9/+3
Signed-off-by: Eric Huang <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-07-25drm/amdgpu: read reg in each iterator of psp_wait_for loopZhang, Jerry2-4/+1
v2: fix the SOS loading failure for PSP v3.1 Signed-off-by: Junwei Zhang <[email protected]> Cc: [email protected] Acked-by: Alex Deucher <[email protected]> (v1) Acked-by: Huang Rui <[email protected]> (v1) Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-07-25drm/amdgpu/gfx9: simplify and fix GRBM index selectionNicolai Hähnle1-11/+13
Copy the approach taken by gfx8, which simplifies the code, and set the instance index properly. The latter is required for debugging, e.g. for reading wave status by UMR. Signed-off-by: Nicolai Hähnle <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-07-25drm/amdgpu: add ring_destroy for psp v10Junwei Zhang3-0/+30
Signed-off-by: Junwei Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-07-25drm/amdgpu: add ring_create function for psp v10Junwei Zhang3-0/+34
Signed-off-by: Junwei Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-07-25drm/amdgpu: add init microcode function for psp v10Junwei Zhang3-0/+48
Signed-off-by: Junwei Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-07-25drm/amdgpu: remove unncessary code in psp v10 ring init funcJunwei Zhang1-20/+0
Signed-off-by: Junwei Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-07-25drm/amdgpu: Fix blocking in RCU critical section(v2)Alex Xie1-3/+7
In RCU read-side critical sections, blocking or sleeping is prohibited. v2: Unlock RCU for the code path where result==NULL. (David Zhou) Update subject Tested-by and reported by: Dave Airlie <[email protected]> [ 141.965723] ============================= [ 141.965724] WARNING: suspicious RCU usage [ 141.965726] 4.12.0-rc7 #221 Not tainted [ 141.965727] ----------------------------- [ 141.965728] /home/airlied/devel/kernel/linux-2.6/include/linux/rcupdate.h:531 Illegal context switch in RCU read-side critical section! [ 141.965730] other info that might help us debug this: [ 141.965731] rcu_scheduler_active = 2, debug_locks = 0 [ 141.965732] 1 lock held by amdgpu_cs:0/1332: [ 141.965733] #0: (rcu_read_lock){......}, at: [<ffffffffa01a0d07>] amdgpu_bo_list_get+0x0/0x109 [amdgpu] [ 141.965774] stack backtrace: [ 141.965776] CPU: 6 PID: 1332 Comm: amdgpu_cs:0 Not tainted 4.12.0-rc7 #221 [ 141.965777] Hardware name: To be filled by O.E.M. To be filled by O.E.M./M5A97 R2.0, BIOS 2603 06/26/2015 [ 141.965778] Call Trace: [ 141.965782] dump_stack+0x68/0x92 [ 141.965785] lockdep_rcu_suspicious+0xf7/0x100 [ 141.965788] ___might_sleep+0x56/0x1fc [ 141.965790] __might_sleep+0x68/0x6f [ 141.965793] __mutex_lock+0x4e/0x7b5 [ 141.965817] ? amdgpu_bo_list_get+0xa4/0x109 [amdgpu] [ 141.965820] ? lock_acquire+0x125/0x1b9 [ 141.965844] ? amdgpu_bo_list_set+0x464/0x464 [amdgpu] [ 141.965846] mutex_lock_nested+0x16/0x18 [ 141.965848] ? mutex_lock_nested+0x16/0x18 [ 141.965872] amdgpu_bo_list_get+0xa4/0x109 [amdgpu] [ 141.965895] amdgpu_cs_ioctl+0x4a0/0x17dd [amdgpu] [ 141.965898] ? radix_tree_node_alloc.constprop.11+0x77/0xab [ 141.965916] drm_ioctl+0x264/0x393 [drm] [ 141.965939] ? amdgpu_cs_find_mapping+0x83/0x83 [amdgpu] [ 141.965942] ? trace_hardirqs_on_caller+0x16a/0x186 Signed-off-by: Alex Xie <[email protected]> Reviewed-by: Chunming Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-07-14drm/amd/powerplay: add profile mode for vega10.Rex Zhu2-25/+109
Signed-off-by: Rex Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-07-14drm/amdgpu: fix amdgpu_bo_gpu_accessible()Christian König1-1/+5
The test was relaxed a bit to much. Signed-off-by: Christian König <[email protected]> Acked-by: Tom St Denis <[email protected]> Reviewed-and-Tested-by: Roger He <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-07-14drm/amdgpu: map VM BOs for CPU based updates only onceChristian König1-36/+51
No need to try to map them every time. Signed-off-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-07-14drm/amdgpu: make sure BOs are always kunmappedChristian König1-0/+3
When a BO is moved or destroyed it shouldn't be kmapped any more. Signed-off-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-07-14drm/amdgpu: flush the HDP only once for CPU based VM updatesChristian König1-4/+12
No need to do this after every single update. Signed-off-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-07-14drm/amdgpu: trace setting VM page tables with the CPU as wellChristian König1-0/+2
Handy for debugging. Signed-off-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-07-14drm/amdgpu: remove VM shadow WARN_ONsAlex Deucher1-5/+1
Printing a warning into the logs that we will certainly run into a BUG() is completely nonsense, the BUG() is more than noisy enough. Signed-off-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-07-14drm/amdgpu: fix amdgpu_vm_bo_waitChristian König1-8/+9
We need to wait with the correct owner on unmap operations or otherwise can run into VM faults. Also always wait for the page directory since this is where the reservation object comes from. So rename the function to amdgpu_vm_wait_pd instead as well. Signed-off-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-07-14drm/amdgpu: fix VM flush for CPU based updatesChristian König1-3/+3
We don't have any update fence in that case, so the need for flushing isn't detected automatically. Signed-off-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-07-14drm/amdgpu/gfx: keep all compute queues on the same pipeAlex Deucher1-1/+2
Spreading them causes performance regressions using compute queues on Polaris 11. Cc: Jim Qu <[email protected]> Acked-by: Jim Qu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-07-14drm/amd/amdgpu: fix si_enable_smc_cac() failed issueJim Qu1-0/+1
Signed-off-by: Jim Qu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-07-14drm/amdgpu: Off by one sanity checksDan Carpenter3-3/+3
This is just future proofing code, not something that can be triggered in real life. We're testing to make sure we don't shift wrap when we do "1ull << i" so "i" has to be in the 0-63 range. If it's 64 then we have gone too far. Acked-by: Christian König <[email protected]> Signed-off-by: Dan Carpenter <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-07-14drm/amdgpu: implement si_read_bios_from_romAlex Deucher1-0/+28
This allows us to read the vbios image directly from ROM. This is already implemented for other asics, but was not yet available for SI. Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-07-14drm/amdgpu/soc15: drop dead functionAlex Deucher1-7/+0
Maybe a leftover from bringup? Reviewed-by: Chunming Zhou <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-07-14drm/amdgpu: call atomfirmware get_clock_info for atomfirmware systemsAlex Deucher1-1/+9
Rather than the legacy atombios version. Acked-by: Chunming Zhou <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-07-14drm/amdgpu: add get_clock_info for atomfirmwareAlex Deucher2-0/+94
The information has moved to different tables, notably smu_info for core refclk and umc_info for mem refclk. Acked-by: Chunming Zhou <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-07-14drm/amdgpu: Send no-retry XNACK for all fault typesJay Cornwall2-0/+6
A subset of VM fault types currently send retry XNACK to the client. This causes a storm of interrupts from the VM to the host. Until the storm is throttled by other means send no-retry XNACK for all fault types instead. No change in behavior to the client which will stall indefinitely with the current configuration in any case. Improves system stability under GC or MMHUB faults. Signed-off-by: Jay Cornwall <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Reviewed-by: John Bridgman <[email protected]> Acked-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-07-14drm/amdgpu: Correctly establish the suspend/resume hook for amdkfdYong Zhao2-8/+8
Signed-off-by: Yong Zhao <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Reviewed-by: Oded Gabbay <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-07-14drm/amdgpu: Make SDMA phase quantum configurableFelix Kuehling5-3/+100
Set a configurable SDMA phase quantum when enabling SDMA context switching. The default value significantly reduces SDMA latency in page table updates when user-mode SDMA queues have concurrent activity, compared to the initial HW setting. Signed-off-by: Felix Kuehling <[email protected]> Reviewed-by: Andres Rodriguez <[email protected]> Reviewed-by: Shaoyun Liu <[email protected]> Acked-by: Chunming Zhou <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-07-14drm/amdgpu: Enable SDMA context switching for CIKFelix Kuehling1-0/+30
Enable SDMA context switching on CIK (copied from sdma_v3_0.c). Signed-off-by: Felix Kuehling <[email protected]> Reviewed-by: Chunming Zhou <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-07-14drm/amdgpu: Enable SDMA_CNTL.ATC_L1_ENABLE for SDMA on CZshaoyunl1-2/+8
For GFX context, the ATC bit in SDMA*_GFX_VIRTUAL_ADDRESS can be cleared to perform in VM mode. For RLC context, to support ATC mode , ATC bit in SDMA*_RLC*_VIRTUAL_ADDRESS should be set. SDMA_CNTL.ATC_L1_ENABLE bit is global setting that enables the L1-L2 translation for ATC address. Signed-off-by: shaoyun liu <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-07-14drm/amdgpu: Try evicting from CPU visible to invisible VRAM firstMichel Dänzer1-0/+28
This gives BOs which haven't been accessed by the CPU since they were moved to visible VRAM another chance to stay in VRAM when another BO needs to go to visible VRAM. This should allow BOs to stay in VRAM longer in some cases. v2: * Only do this for BOs which don't have the AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED flag set. Reviewed-by: Christian König <[email protected]> Signed-off-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-07-14drm/amdgpu: Don't force BOs into visible VRAM for page faultsJohn Brooks1-7/+10
There is no need for page faults to force BOs into visible VRAM if it's full, and the time it takes to do so is great enough to cause noticeable stuttering. Add GTT as a possible placement so that if visible VRAM is full, page faults move BOs to GTT instead of evicting other BOs from VRAM. Suggested-by: Michel Dänzer <[email protected]> Signed-off-by: John Brooks <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-07-14drm/amdgpu: Set/clear CPU_ACCESS flag on page fault and move to VRAMJohn Brooks2-10/+19
When a BO is moved to VRAM, clear AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED. This allows it to potentially later move to invisible VRAM if the CPU does not access it again. Setting the CPU_ACCESS flag in amdgpu_bo_fault_reserve_notify() also means that we can remove the loop to restrict lpfn to the end of visible VRAM, because amdgpu_ttm_placement_init() will do it for us. v3 [Michel Dänzer] * Use AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED instead of a new flag (Christian König) * Clear flag in amdgpu_bo_move instead of amdgpu_move_ram_vram (Christian) * Explicitly mention amdgpu_bo_fault_reserve_notify in amdgpu_bo_move * Also clear flag in amdgpu_bo_create_restricted Suggested-by: Michel Dänzer <[email protected]> Signed-off-by: John Brooks <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-07-14drm/amdgpu: Throttle visible VRAM moves separatelyJohn Brooks3-23/+87
The BO move throttling code is designed to allow VRAM to fill quickly if it is relatively empty. However, this does not take into account situations where the visible VRAM is smaller than total VRAM, and total VRAM may not be close to full but the visible VRAM segment is under pressure. In such situations, visible VRAM would experience unrestricted swapping and performance would drop. Add a separate counter specifically for moves involving visible VRAM, and check it before moving BOs there. v2: Only perform calculations for separate counter if visible VRAM is smaller than total VRAM. (Michel Dänzer) v3: [Michel Dänzer] * Use BO's location rather than the AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED flag to determine whether to account a move for visible VRAM in most cases. * Use a single if (adev->mc.visible_vram_size < adev->mc.real_vram_size) { block in amdgpu_cs_get_threshold_for_moves. Fixes: 95844d20ae02 (drm/amdgpu: throttle buffer migrations at CS using a fixed MBps limit (v2)) Signed-off-by: John Brooks <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-07-14drm/amdgpu: Add vis_vramlimit module parameterJohn Brooks3-0/+13
Allow specifying a limit on visible VRAM via a module parameter. This is helpful for testing performance under visible VRAM pressure. v2: Add cast to 64-bit (Christian König) Signed-off-by: John Brooks <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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