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2017-04-07KVM: nVMX: support RDRAND and RDSEED exitingPaolo Bonzini2-0/+7
Signed-off-by: Paolo Bonzini <[email protected]> Reviewed-by: Jim Mattson <[email protected]> Signed-off-by: Radim Krčmář <[email protected]>
2017-04-07KVM: VMX: add missing exit reasonsPaolo Bonzini1-7/+18
In order to simplify adding exit reasons in the future, the array of exit reason names is now also sorted by exit reason code. Reviewed-by: David Hildenbrand <[email protected]> Signed-off-by: Paolo Bonzini <[email protected]> Signed-off-by: Radim Krčmář <[email protected]>
2017-04-07kvm: nVMX: support EPT accessed/dirty bitsPaolo Bonzini6-25/+54
Now use bit 6 of EPTP to optionally enable A/D bits for EPTP. Another thing to change is that, when EPT accessed and dirty bits are not in use, VMX treats accesses to guest paging structures as data reads. When they are in use (bit 6 of EPTP is set), they are treated as writes and the corresponding EPT dirty bit is set. The MMU didn't know this detail, so this patch adds it. We also have to fix up the exit qualification. It may be wrong because KVM sets bit 6 but the guest might not. L1 emulates EPT A/D bits using write permissions, so in principle it may be possible for EPT A/D bits to be used by L1 even though not available in hardware. The problem is that guest page-table walks will be treated as reads rather than writes, so they would not cause an EPT violation. Signed-off-by: Paolo Bonzini <[email protected]> [Fixed typo in walk_addr_generic() comment and changed bit clear + conditional-set pattern in handle_ept_violation() to conditional-clear] Signed-off-by: Radim Krčmář <[email protected]>
2017-04-07kvm: x86: MMU support for EPT accessed/dirty bitsPaolo Bonzini1-8/+15
This prepares the MMU paging code for EPT accessed and dirty bits, which can be enabled optionally at runtime. Code that updates the accessed and dirty bits will need a pointer to the struct kvm_mmu. Signed-off-by: Paolo Bonzini <[email protected]> Signed-off-by: Radim Krčmář <[email protected]>
2017-04-07KVM: VMX: remove bogus check for invalid EPT violationPaolo Bonzini1-14/+0
handle_ept_violation is checking for "guest-linear-address invalid" + "not a paging-structure walk". However, _all_ EPT violations without a valid guest linear address are paging structure walks, because those EPT violations happen when loading the guest PDPTEs. Therefore, the check can never be true, and even if it were, KVM doesn't care about the guest linear address; it only uses the guest *physical* address VMCS field. So, remove the check altogether. Signed-off-by: Paolo Bonzini <[email protected]> Reviewed-by: Jim Mattson <[email protected]> Reviewed-by: David Hildenbrand <[email protected]> Signed-off-by: Radim Krčmář <[email protected]>
2017-04-07KVM: nVMX: we support 1GB EPT pagesPaolo Bonzini1-3/+3
Large pages at the PDPE level can be emulated by the MMU, so the bit can be set unconditionally in the EPT capabilities MSR. The same is true of 2MB EPT pages, though all Intel processors with EPT in practice support those. Reviewed-by: David Hildenbrand <[email protected]> Signed-off-by: Paolo Bonzini <[email protected]>
2017-04-07KVM: x86: drop legacy device assignmentPaolo Bonzini9-1710/+1
Legacy device assignment has been deprecated since 4.2 (released 1.5 years ago). VFIO is better and everyone should have switched to it. If they haven't, this should convince them. :) Reviewed-by: Alex Williamson <[email protected]> Signed-off-by: Paolo Bonzini <[email protected]>
2017-04-07KVM: VMX: require virtual NMI supportPaolo Bonzini1-105/+38
Virtual NMIs are only missing in Prescott and Yonah chips. Both are obsolete for virtualization usage---Yonah is 32-bit only even---so drop vNMI emulation. Signed-off-by: Paolo Bonzini <[email protected]>
2017-04-07kvm/svm: Setup MCG_CAP on AMD properlyBorislav Petkov1-0/+7
MCG_CAP[63:9] bits are reserved on AMD. However, on an AMD guest, this MSR returns 0x100010a. More specifically, bit 24 is set, which is simply wrong. That bit is MCG_SER_P and is present only on Intel. Thus, clean up the reserved bits in order not to confuse guests. Signed-off-by: Borislav Petkov <[email protected]> Cc: Joerg Roedel <[email protected]> Cc: Paolo Bonzini <[email protected]> Cc: Radim Krčmář <[email protected]> Signed-off-by: Paolo Bonzini <[email protected]>
2017-04-07KVM: nVMX: single function for switching between vmcsDavid Hildenbrand1-15/+8
Let's combine it in a single function vmx_switch_vmcs(). Signed-off-by: David Hildenbrand <[email protected]> Reviewed-by: Paolo Bonzini <[email protected]> Reviewed-by: Jim Mattson <[email protected]> Signed-off-by: Radim Krčmář <[email protected]>
2017-04-07kvm: vmx: Don't use INVVPID when EPT is enabledJim Mattson1-1/+2
According to the Intel SDM, volume 3, section 28.3.2: Creating and Using Cached Translation Information, "No linear mappings are used while EPT is in use." INVEPT will invalidate both the guest-physical mappings and the combined mappings in the TLBs and paging-structure caches, so an INVVPID is superfluous. Signed-off-by: Jim Mattson <[email protected]> Reviewed-by: David Hildenbrand <[email protected]> Signed-off-by: Radim Krčmář <[email protected]>
2017-04-07KVM: s390: introduce AIS capabilityYi Min Zhao3-0/+24
Introduce a cap to enable AIS facility bit, and add documentation for this capability. Signed-off-by: Yi Min Zhao <[email protected]> Signed-off-by: Fei Li <[email protected]> Reviewed-by: Cornelia Huck <[email protected]> Signed-off-by: Christian Borntraeger <[email protected]>
2017-04-06Merge tag 'kvm_mips_4.12_1' of ↵Radim Krčmář29-367/+5010
git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/kvm-mips From: James Hogan <[email protected]> KVM: MIPS: VZ support, Octeon III, and TLBR Add basic support for the MIPS Virtualization Module (generally known as MIPS VZ) in KVM. We primarily support the ImgTec P5600, P6600, I6400, and Cavium Octeon III cores so far. Support is included for the following VZ / guest hardware features: - MIPS32 and MIPS64, r5 (VZ requires r5 or later) and r6 - TLBs with GuestID (IMG cores) or Root ASID Dealias (Octeon III) - Shared physical root/guest TLB (IMG cores) - FPU / MSA - Cop0 timer (up to 1GHz for now due to soft timer limit) - Segmentation control (EVA) - Hardware page table walker (HTW) both for root and guest TLB Also included is a proper implementation of the TLBR instruction for the trap & emulate MIPS KVM implementation. Preliminary MIPS architecture changes are applied directly with Ralf's ack.
2017-04-06KVM: s390: introduce adapter interrupt inject functionYi Min Zhao4-6/+78
Inject adapter interrupts on a specified adapter which allows to retrieve the adapter flags, e.g. if the adapter is subject to AIS facility or not. And add documentation for this interface. For adapters subject to AIS, handle the airq injection suppression for a given ISC according to the interruption mode: - before injection, if NO-Interruptions Mode, just return 0 and suppress, otherwise, allow the injection. - after injection, if SINGLE-Interruption Mode, change it to NO-Interruptions Mode to suppress the following interrupts. Besides, add tracepoint for suppressed airq and AIS mode transitions. Signed-off-by: Yi Min Zhao <[email protected]> Signed-off-by: Fei Li <[email protected]> Reviewed-by: Cornelia Huck <[email protected]> Signed-off-by: Christian Borntraeger <[email protected]>
2017-04-06KVM: s390: introduce ais mode modify functionFei Li6-0/+114
Provide an interface for userspace to modify AIS (adapter-interruption-suppression) mode state, and add documentation for the interface. Allowed target modes are ALL-Interruptions mode and SINGLE-Interruption mode. We introduce the 'simm' and 'nimm' fields in kvm_s390_float_interrupt to store interruption modes for each ISC. Each bit in 'simm' and 'nimm' targets to one ISC, and collaboratively indicate three modes: ALL-Interruptions, SINGLE-Interruption and NO-Interruptions. This interface can initiate most transitions between the states; transition from SINGLE-Interruption to NO-Interruptions via adapter interrupt injection will be introduced in a following patch. The meaningful combinations are as follows: interruption mode | simm bit | nimm bit ------------------|----------|---------- ALL | 0 | 0 SINGLE | 1 | 0 NO | 1 | 1 Besides, add tracepoint to track AIS mode transitions. Co-Authored-By: Yi Min Zhao <[email protected]> Signed-off-by: Yi Min Zhao <[email protected]> Signed-off-by: Fei Li <[email protected]> Reviewed-by: Cornelia Huck <[email protected]> Signed-off-by: Christian Borntraeger <[email protected]>
2017-04-06KVM: s390: interface for suppressible I/O adaptersFei Li4-4/+15
In order to properly implement adapter-interruption suppression, we need a way for userspace to specify which adapters are subject to suppression. Let's convert the existing (and unused) 'pad' field into a 'flags' field and define a flag value for suppressible adapters. Besides, add documentation for the interface. Signed-off-by: Fei Li <[email protected]> Reviewed-by: Cornelia Huck <[email protected]> Signed-off-by: Christian Borntraeger <[email protected]>
2017-03-30powerpc/vfio_spapr_tce: Add reference counting to iommu_tableAlexey Kardashevskiy7-17/+37
So far iommu_table obejcts were only used in virtual mode and had a single owner. We are going to change this by implementing in-kernel acceleration of DMA mapping requests. The proposed acceleration will handle requests in real mode and KVM will keep references to tables. This adds a kref to iommu_table and defines new helpers to update it. This replaces iommu_free_table() with iommu_tce_table_put() and makes iommu_free_table() static. iommu_tce_table_get() is not used in this patch but it will be in the following patch. Since this touches prototypes, this also removes @node_name parameter as it has never been really useful on powernv and carrying it for the pseries platform code to iommu_free_table() seems to be quite useless as well. This should cause no behavioral change. Signed-off-by: Alexey Kardashevskiy <[email protected]> Reviewed-by: David Gibson <[email protected]> Acked-by: Alex Williamson <[email protected]> Signed-off-by: Michael Ellerman <[email protected]>
2017-03-30powerpc/iommu/vfio_spapr_tce: Cleanup iommu_table disposalAlexey Kardashevskiy3-7/+9
At the moment iommu_table can be disposed by either calling iommu_table_free() directly or it_ops::free(); the only implementation of free() is in IODA2 - pnv_ioda2_table_free() - and it calls iommu_table_free() anyway. As we are going to have reference counting on tables, we need an unified way of disposing tables. This moves it_ops::free() call into iommu_free_table() and makes use of the latter. The free() callback now handles only platform-specific data. As from now on the iommu_free_table() calls it_ops->free(), we need to have it_ops initialized before calling iommu_free_table() so this moves this initialization in pnv_pci_ioda2_create_table(). This should cause no behavioral change. Signed-off-by: Alexey Kardashevskiy <[email protected]> Reviewed-by: David Gibson <[email protected]> Acked-by: Alex Williamson <[email protected]> Signed-off-by: Michael Ellerman <[email protected]>
2017-03-30powerpc/powernv/iommu: Add real mode version of iommu_table_ops::exchange()Alexey Kardashevskiy3-1/+57
In real mode, TCE tables are invalidated using special cache-inhibited store instructions which are not available in virtual mode This defines and implements exchange_rm() callback. This does not define set_rm/clear_rm/flush_rm callbacks as there is no user for those - exchange/exchange_rm are only to be used by KVM for VFIO. The exchange_rm callback is defined for IODA1/IODA2 powernv platforms. This replaces list_for_each_entry_rcu with its lockless version as from now on pnv_pci_ioda2_tce_invalidate() can be called in the real mode too. Signed-off-by: Alexey Kardashevskiy <[email protected]> Reviewed-by: David Gibson <[email protected]> Signed-off-by: Michael Ellerman <[email protected]>
2017-03-29tools/kvm_stat: add '%Total' columnStefan Raspl1-1/+8
Add column '%Total' next to 'Total' for easier comparison of numbers between hosts. Signed-off-by: Stefan Raspl <[email protected]> Marc Hartmayer <[email protected]> Signed-off-by: Radim Krčmář <[email protected]>
2017-03-29tools/kvm_stat: add interactive command 'r'Stefan Raspl2-14/+53
Provide an interactive command to reset the tracepoint statistics. Requires some extra work for debugfs, as the counters cannot be reset. On the up side, this offers us the opportunity to have debugfs values reset on startup and whenever a filter is modified, becoming consistent with the tracepoint provider. As a bonus, 'kvmstat -dt' will now provide useful output, instead of mixing values in totally different orders of magnitude. Furthermore, we avoid unnecessary resets when any of the filters is "changed" interactively to the previous value. Signed-off-by: Stefan Raspl <[email protected]> Acked-by: Janosch Frank <[email protected]> Signed-off-by: Radim Krčmář <[email protected]>
2017-03-29tools/kvm_stat: add interactive command 'c'Stefan Raspl2-4/+14
Provide a real simple way to erase any active filter. Signed-off-by: Stefan Raspl <[email protected]> Reviewed-by: Marc Hartmayer <[email protected]> Signed-off-by: Radim Krčmář <[email protected]>
2017-03-29tools/kvm_stat: add option '--guest'Stefan Raspl2-2/+105
Add a new option '-g'/'--guest' to select a particular process by providing the QEMU guest name. Notes: - The logic to figure out the pid corresponding to the guest name might look scary, but works pretty reliably in practice; in the unlikely event that it returns add'l flukes, it will bail out and hint at using '-p' instead, no harm done. - Mixing '-g' and '-p' is possible, and the final instance specified on the command line is the significant one. This is consistent with current behavior for '-p' which, if specified multiple times, also regards the final instance as the significant one. Signed-off-by: Stefan Raspl <[email protected]> Reviewed-by: Janosch Frank <[email protected]> Signed-off-by: Radim Krčmář <[email protected]>
2017-03-29tools/kvm_stat: remove regex filter on empty inputStefan Raspl1-0/+1
Behavior on empty/0 input for regex and pid filtering was inconsistent, as the former would keep the current filter, while the latter would (naturally) remove any pid filtering. Make things consistent by falling back to the default filter on empty input for the regex filter dialogue. Signed-off-by: Stefan Raspl <[email protected]> Reviewed-by: Marc Hartmayer <[email protected]> Signed-off-by: Radim Krčmář <[email protected]>
2017-03-29tools/kvm_stat: display regex when set to non-defaultStefan Raspl1-0/+6
If a user defines a regex filter through the interactive command, display the active regex in the header's second line. Signed-off-by: Stefan Raspl <[email protected]> Reviewed-by: Marc Hartmayer <[email protected]> Signed-off-by: Radim Krčmář <[email protected]>
2017-03-29tools/kvm_stat: print error messages on faulty pid filter inputStefan Raspl1-0/+4
Print helpful messages in case users enter invalid input or invalid pids in the interactive pid filter dialogue. Signed-off-by: Stefan Raspl <[email protected]> Reviewed-by: Marc Hartmayer <[email protected]> Signed-off-by: Radim Krčmář <[email protected]>
2017-03-29tools/kvm_stat: remove pid filter on empty inputStefan Raspl1-4/+7
Improve consistency in the interactive dialogue for pid filtering by removing any filters on empty input (in addition to entering 0). Signed-off-by: Stefan Raspl <[email protected]> Reviewed-by: Janosch Frank <[email protected]> Reviewed-by: Marc Hartmayer <[email protected]> Signed-off-by: Radim Krčmář <[email protected]>
2017-03-29tools/kvm_stat: display guest name when using pid filterStefan Raspl1-2/+39
When running kvm_stat with option '-p' to filter per process, display the QEMU guest name next to the pid, if available. Signed-off-by: Stefan Raspl <[email protected]> Reviewed-By: Janosch Frank <[email protected]> Signed-off-by: Radim Krčmář <[email protected]>
2017-03-29tools/kvm_stat: document list of interactive commandsStefan Raspl2-0/+23
Apart from the source code, there does not seem to be a place that documents the interactive capabilities of kvm_stat yet. Signed-off-by: Stefan Raspl <[email protected]> Signed-off-by: Radim Krčmář <[email protected]>
2017-03-29tools/kvm_stat: reduce perceived idle time on filter updatesStefan Raspl1-18/+30
Whenever a user adds a filter, we * redraw the header immediately for a snappy response * print a message indicating to the user that we're busy while the noticeable delay induced by updating all of the stats objects takes place * update the statistics ASAP (i.e. after 0.25s instead of 3s) to be consistent with behavior on startup To do so, we split the Tui's refresh() method to allow for drawing header and stats separately, and trigger a header refresh whenever we are about to do something that takes a while - like updating filters. Signed-off-by: Stefan Raspl <[email protected]> Signed-off-by: Radim Krčmář <[email protected]>
2017-03-29tools/kvm_stat: full PEP8 complianceStefan Raspl1-0/+22
Provides all missing empty lines as required for full PEP compliance. Signed-off-by: Stefan Raspl <[email protected]> Reviewed-by: Marc Hartmayer <[email protected]> Signed-off-by: Radim Krčmář <[email protected]>
2017-03-29tools/kvm_stat: fix trace setup glitch on field updates in TracepointProviderStefan Raspl1-2/+3
Updating the fields of the TracepointProvider does not propagate changes to the tracepoints. This shows when a pid filter is enabled, whereby subsequent extensions of the fields of the Tracepoint provider (e.g. by toggling drilldown) will not modify the tracepoints as required. To reproduce, select a specific process via interactive command 'p', and enable drilldown via 'x' - none of the fields with the braces will appear although they should. The fix will always leave all available fields in the TracepointProvider enabled. Signed-off-by: Stefan Raspl <[email protected]> Based-on-text-by: Janosch Frank <[email protected]> Signed-off-by: Radim Krčmář <[email protected]>
2017-03-29tools/kvm_stat: fix misc glitchesStefan Raspl1-13/+11
Addresses - eliminate extra import - missing variable initialization - type redefinition from int to float - passing of int type argument instead of string - a couple of PEP8-reported indentation/formatting glitches - remove unused variable drilldown in class Tui Signed-off-by: Stefan Raspl <[email protected]> Reviewed-by: Marc Hartmayer <[email protected]> Signed-off-by: Radim Krčmář <[email protected]>
2017-03-29tools/kvm_stat: handle SIGINT in log and batch modesStefan Raspl1-11/+17
SIGINT causes ugly unhandled exceptions in log and batch mode, which we prevent by catching the exceptions accordingly. Signed-off-by: Stefan Raspl <[email protected]> Reviewed-by: Marc Hartmayer <[email protected]> Signed-off-by: Radim Krčmář <[email protected]>
2017-03-29tools/kvm_stat: catch curses exceptions onlyStefan Raspl1-1/+1
The previous version was catching all exceptions, including SIGINT. We only want to catch the curses exceptions here. Signed-off-by: Stefan Raspl <[email protected]> Reviewed-by: Janosch Frank <[email protected]> Reviewed-by: Sascha Silbe <[email protected]> Reviewed-by: Marc Hartmayer <[email protected]> Signed-off-by: Radim Krčmář <[email protected]>
2017-03-29tools/kvm_stat: hide cursorStefan Raspl1-0/+7
When running kvm_stat in interactive mode, the cursor appears at the lower left corner, which looks a bit distracting. This patch hides the cursor by turning it invisible. Signed-off-by: Stefan Raspl <[email protected]> Reviewed-By: Sascha Silbe <[email protected]> Reviewed-by: Marc Hartmayer <[email protected]> Signed-off-by: Radim Krčmář <[email protected]>
2017-03-28KVM: MIPS/Emulate: Properly implement TLBR for T&EJames Hogan1-46/+53
Properly implement emulation of the TLBR instruction for Trap & Emulate. This instruction reads the TLB entry pointed at by the CP0_Index register into the other TLB registers, which may have the side effect of changing the current ASID. Therefore abstract the CP0_EntryHi and ASID changing code into a common function in the process. A comment indicated that Linux doesn't use TLBR, which is true during normal use, however dumping of the TLB does use it (for example with the relatively recent 'x' magic sysrq key), as does a wired TLB entries test case in my KVM tests. Signed-off-by: James Hogan <[email protected]> Acked-by: Ralf Baechle <[email protected]> Cc: Paolo Bonzini <[email protected]> Cc: "Radim Krčmář" <[email protected]> Cc: [email protected] Cc: [email protected]
2017-03-28MIPS: Allow KVM to be enabled on Octeon CPUsJames Hogan1-0/+1
Octeon III has VZ ASE support, so allow KVM to be enabled on Octeon CPUs as it should now be functional. Signed-off-by: James Hogan <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: David Daney <[email protected]> Cc: Andreas Herrmann <[email protected]> Cc: Paolo Bonzini <[email protected]> Cc: "Radim Krčmář" <[email protected]> Cc: [email protected] Cc: [email protected]
2017-03-28KVM: MIPS/VZ: Handle Octeon III guest.PRid registerJames Hogan2-2/+19
Octeon III implements a read-only guest CP0_PRid register, so add cases to the KVM register access API for Octeon to ensure the correct value is read and writes are ignored. Signed-off-by: James Hogan <[email protected]> Cc: Paolo Bonzini <[email protected]> Cc: "Radim Krčmář" <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: David Daney <[email protected]> Cc: Andreas Herrmann <[email protected]> Cc: [email protected] Cc: [email protected]
2017-03-28KVM: MIPS/VZ: Emulate hit CACHE ops for Octeon IIIJames Hogan1-0/+11
Octeon III doesn't implement the optional GuestCtl0.CG bit to allow guest mode to execute virtual address based CACHE instructions, so implement emulation of a few important ones specifically for Octeon III in response to a GPSI exception. Currently the main reason to perform these operations is for icache synchronisation, so they are implemented as a simple icache flush with local_flush_icache_range(). Signed-off-by: James Hogan <[email protected]> Cc: Paolo Bonzini <[email protected]> Cc: "Radim Krčmář" <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: David Daney <[email protected]> Cc: Andreas Herrmann <[email protected]> Cc: [email protected] Cc: [email protected]
2017-03-28KVM: MIPS/VZ: VZ hardware setup for Octeon IIIJames Hogan2-28/+108
Set up hardware virtualisation on Octeon III cores, configuring guest interrupt routing and carving out half of the root TLB for guest use, restoring it back again afterwards. We need to be careful to inhibit TLB shutdown machine check exceptions while invalidating guest TLB entries, since TLB invalidation is not available so guest entries must be invalidated by setting them to unique unmapped addresses, which could conflict with mappings set by the guest or root if recently repartitioned. Signed-off-by: James Hogan <[email protected]> Cc: Paolo Bonzini <[email protected]> Cc: "Radim Krčmář" <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: David Daney <[email protected]> Cc: Andreas Herrmann <[email protected]> Cc: [email protected] Cc: [email protected]
2017-03-28KVM: MIPS/T&E: Report correct dcache line sizeJames Hogan1-0/+8
Octeon CPUs don't report the correct dcache line size in CP0_Config1.DL, so encode the correct value for the guest CP0_Config1.DL based on cpu_dcache_line_size(). Signed-off-by: James Hogan <[email protected]> Cc: Paolo Bonzini <[email protected]> Cc: "Radim Krčmář" <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: David Daney <[email protected]> Cc: Andreas Herrmann <[email protected]> Cc: [email protected] Cc: [email protected]
2017-03-28KVM: MIPS/TLB: Handle virtually tagged icachesJames Hogan1-0/+14
When TLB entries are invalidated in the presence of a virtually tagged icache, such as that found on Octeon CPUs, flush the icache so that we don't get a reserved instruction exception even though the TLB mapping is removed. Signed-off-by: James Hogan <[email protected]> Cc: Paolo Bonzini <[email protected]> Cc: "Radim Krčmář" <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: David Daney <[email protected]> Cc: Andreas Herrmann <[email protected]> Cc: [email protected] Cc: [email protected]
2017-03-28KVM: MIPS/Emulate: Adapt T&E CACHE emulation for OcteonJames Hogan2-3/+28
Cache management is implemented separately for Cavium Octeon CPUs, so r4k_blast_[id]cache aren't available. Instead for Octeon perform a local icache flush using local_flush_icache_range(), and for other platforms which don't use c-r4k.c use __flush_cache_all() / flush_icache_all(). Signed-off-by: James Hogan <[email protected]> Cc: Paolo Bonzini <[email protected]> Cc: "Radim Krčmář" <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: David Daney <[email protected]> Cc: Andreas Herrmann <[email protected]> Cc: [email protected] Cc: [email protected]
2017-03-28MIPS: Add Octeon III register accessors & definitionsJames Hogan1-0/+36
Add accessors for some VZ related Cavium Octeon III specific COP0 registers, along with field definitions. These will mostly be used by KVM to set up interrupt routing and partition the TLB between root and guest. Signed-off-by: James Hogan <[email protected]> Acked-by: Ralf Baechle <[email protected]> Cc: David Daney <[email protected]> Cc: Andreas Herrmann <[email protected]> Cc: Paolo Bonzini <[email protected]> Cc: "Radim Krčmář" <[email protected]> Cc: [email protected] Cc: [email protected]
2017-03-28KVM: MIPS/VZ: Trace guest mode changesJames Hogan3-2/+69
Create a trace event for guest mode changes, and enable VZ's GuestCtl0.MC bit after the trace event is enabled to trap all guest mode changes. The MC bit causes Guest Hardware Field Change (GHFC) exceptions whenever a guest mode change occurs (such as an exception entry or return from exception), so we need to handle this exception now. The MC bit is only enabled when restoring register state, so enabling the trace event won't take immediate effect. Tracing guest mode changes can be particularly handy when trying to work out what a guest OS gets up to before something goes wrong, especially if the problem occurs as a result of some previous guest userland exception which would otherwise be invisible in the trace. Signed-off-by: James Hogan <[email protected]> Cc: Paolo Bonzini <[email protected]> Cc: "Radim Krčmář" <[email protected]> Cc: Steven Rostedt <[email protected]> Cc: Ingo Molnar <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: [email protected] Cc: [email protected]
2017-03-28KVM: MIPS/VZ: Support hardware guest timerJames Hogan4-11/+287
Transfer timer state to the VZ guest context (CP0_GTOffset & guest CP0_Count) when entering guest mode, enabling direct guest access to it, and transfer back to soft timer when saving guest register state. This usually allows guest code to directly read CP0_Count (via MFC0 and RDHWR) and read/write CP0_Compare, without trapping to the hypervisor for it to emulate the guest timer. Writing to CP0_Count or CP0_Cause.DC is much less common and still triggers a hypervisor GPSI exception, in which case the timer state is transferred back to an hrtimer before emulating the write. We are careful to prevent small amounts of drift from building up due to undeterministic time intervals between reading of the ktime and reading of CP0_Count. Some drift is expected however, since the system clocksource may use a different timer to the local CP0_Count timer used by VZ. This is permitted to prevent guest CP0_Count from appearing to go backwards. Signed-off-by: James Hogan <[email protected]> Cc: Paolo Bonzini <[email protected]> Cc: "Radim Krčmář" <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: [email protected] Cc: [email protected]
2017-03-28KVM: MIPS/VZ: Emulate MAARs when necessaryJames Hogan5-5/+137
Add emulation of Memory Accessibility Attribute Registers (MAARs) when necessary. We can't actually do anything with whatever the guest provides, but it may not be possible to clear Guest.Config5.MRP so we have to emulate at least a pair of MAARs. Signed-off-by: James Hogan <[email protected]> Cc: Paolo Bonzini <[email protected]> Cc: "Radim Krčmář" <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: Jonathan Corbet <[email protected]> Cc: Steven Rostedt <[email protected]> Cc: Ingo Molnar <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected]
2017-03-28KVM: MIPS/VZ: Support guest load-linked bitJames Hogan1-0/+24
When restoring guest state after another VCPU has run, be sure to clear CP0_LLAddr.LLB in order to break any interrupted atomic critical section. Without this SMP guest atomics don't work when LLB is present as one guest can complete the atomic section started by another guest. MIPS VZ guest read of CP0_LLAddr causes Guest Privileged Sensitive Instruction (GPSI) exception due to the address being root physical. Handle this by reporting only the LLB bit, which contains the bit for whether a ll/sc atomic is in progress without any reason for failure. Similarly on P5600 a guest write to CP0_LLAddr also causes a GPSI exception. Handle this also by clearing the guest LLB bit from root mode. Signed-off-by: James Hogan <[email protected]> Cc: Paolo Bonzini <[email protected]> Cc: "Radim Krčmář" <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: [email protected] Cc: [email protected]
2017-03-28KVM: MIPS/VZ: Support guest hardware page table walkerJames Hogan3-0/+92
Add support for VZ guest CP0_PWBase, CP0_PWField, CP0_PWSize, and CP0_PWCtl registers for controlling the guest hardware page table walker (HTW) present on P5600 and P6600 cores. These guest registers need initialising on R6, context switching, and exposing via the KVM ioctl API when they are present. Signed-off-by: James Hogan <[email protected]> Cc: Paolo Bonzini <[email protected]> Cc: "Radim Krčmář" <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: Jonathan Corbet <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected]
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