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2018-05-14drm/i915: Update DRIVER_DATE to 20180514Jani Nikula1-2/+2
Signed-off-by: Jani Nikula <[email protected]>
2018-05-14drm/i915: Mark up nested spinlocksChris Wilson1-1/+1
When we process the outstanding requests upon banning a context, we need to acquire both the engine and the client's timeline, nesting the locks. This requires explicit markup as the two timelines are now of the same class, since commit a89d1f921c15 ("drm/i915: Split i915_gem_timeline into individual timelines"). Testcase: igt/gem_eio/banned Fixes: a89d1f921c15 ("drm/i915: Split i915_gem_timeline into individual timelines") Signed-off-by: Chris Wilson <[email protected]> Cc: Tvrtko Ursulin <[email protected]> Cc: Joonas Lahtinen <[email protected]> Cc: Michel Thierry <[email protected]> Reviewed-by: Tvrtko Ursulin <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-05-14drm/i915/execlists: Relax CSB force-mmio for VT-dChris Wilson1-8/+0
The original switch to use CSB from the HWSP was plagued by the effect of read ordering on VT-d; we would read the WRITE pointer from the HWSP before it had completed writing the CSB contents. The mystery comes down to the lack of rmb() for correct ordering with respect to the writes from HW, and with that resolved we can remove the VT-d special casing. Signed-off-by: Chris Wilson <[email protected]> Cc: Mika Kuoppala <[email protected]> Cc: Joonas Lahtinen <[email protected]> Cc: Tvrtko Ursulin <[email protected]> Cc: Michał Winiarski <[email protected]> Cc: Michel Thierry <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Tested-by: Mika Kuoppala <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]>
2018-05-14Merge tag 'gvt-next-2018-05-14' of https://github.com/intel/gvt-linux into ↵Jani Nikula5-28/+39
drm-intel-next-queued - Improve the emulation of virtual non-priv register. (Yan) - Reverse the hack of host of preeption of GVT-g. (Weinan) - Improve untracked warning message.(Changbin) Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-05-14Revert "drm/i915/gvt: set max priority for gvt context"Weinan Li1-3/+0
This reverts commit 11474e9091cf2002e948647fd9f63a7f027e488a. There are issues which will block the host preemption before, instead of disabling it use one workaround "setting max priority for gvt context" to avoid the gvt context be preempted by the host. Now the issues have been cleared, so revert this patch to enable host preemption. v2: - refine description(Zhenyu) Signed-off-by: Weinan Li <[email protected]> Signed-off-by: Zhenyu Wang <[email protected]> Signed-off-by: Zhi Wang <[email protected]>
2018-05-14Merge branch 'drm-intel-next-queued' into gvt-nextZhi Wang13195-811450/+529384
Signed-off-by: Zhi Wang <[email protected]>
2018-05-14drm/i915/gvt: let force_to_nonpriv cmd handler only valid for LRI cmdZhao Yan1-3/+11
the cmd_reg_handler() is called by cmds LRM, PIPE_CTRL, SRM... for LRM, SRM, we cannot get write data in a simple way. On other side, the force_to_nonpriv reigsters will only be written in LRI in current drivers. so we don't want to bother the handler to handle those memory access cmds, just leave a print message here. Signed-off-by: Zhao Yan <[email protected]> Signed-off-by: Zhenyu Wang <[email protected]>
2018-05-14drm/i915/gvt: do not return error on handling force_to_nonpriv registersZhao Yan2-2/+3
Return error will cause vm hang and enter failsafe mode. However, we don't want that happen on detecting an wrong force_to_nonpriv register write. Therefore, we just omit the wrong write or patch it to default value. v2: only return 0 on detecting lri write of registers outside whitelist, but still return error on other error conditions. (zhenyu wang) Signed-off-by: Zhao Yan <[email protected]> Reviewed-by: Zhang Yulei <[email protected]> Signed-off-by: Zhenyu Wang <[email protected]>
2018-05-14drm/i915/gvt: let NOPID be the default value of force_to_nonpriv registersZhao Yan2-9/+22
Each ring has a NOPID register and currently they are regarded as default value of force_to_nonpriv registers in guest drivers Signed-off-by: Zhao Yan <[email protected]> Signed-off-by: Zhenyu Wang <[email protected]>
2018-05-14drm/i915/gvt: Remove disable_warn_untrack and print untracked mmio with ↵Changbin Du3-11/+3
debug level The disable_warn_untrack never prevent gvt from printing untracked mmio errors. We were disturbed by this error storm and the fix is just adding them to the list with no essential new change. This message is only useful for enabling new platform during developing process. So lower the message level to debug and then remove disable_warn_untrack. Signed-off-by: Changbin Du <[email protected]> Signed-off-by: Zhenyu Wang <[email protected]>
2018-05-13drm/i915/gen9: Add WaClearHIZ_WM_CHICKEN3 for bxt and glkMichel Thierry2-0/+7
Factor in clear values wherever required while updating destination min/max. References: HSDES#1604444184 Signed-off-by: Michel Thierry <[email protected]> Cc: [email protected] Cc: Mika Kuoppala <[email protected]> Cc: Oscar Mateo <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Cc: [email protected]
2018-05-13drm/i915/selftests: scrub 64KMatthew Auld3-0/+25
We write all 4K page entries, even when using 64K pages. In order to verify that the HW isn't cheating by using the 4K PTE instead of the 64K PTE, we want to remove all the surplus entries. If the HW skipped the 64K PTE, it will read/write into the scratch page instead - which we detect as missing results during selftests. v2: much improved commentary (Chris) Signed-off-by: Matthew Auld <[email protected]> Cc: Chris Wilson <[email protected]> Cc: Changbin Du <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-05-11drm/i915/oa: Check that OA is disabled before unpinningChris Wilson1-0/+8
Before we unpin the buffer used for OA reports and return it to the system, we need to be sure that the HW has finished writing into it. For lack of a better idea, poll OACONTROL to check it is switched off. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106379 Signed-off-by: Chris Wilson <[email protected]> Cc: Lionel Landwerlin <[email protected]> Cc: Matthew Auld <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Tested-by: Lionel Landwerlin <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-05-11Revert "drm/i915/cnl: Use mmio access to context status buffer"Chris Wilson1-3/+0
In the previous patch (to include a rmb() after readig the CSB WRITE pointer from the HWSP) we believe we have fixed the underlying bug, and so can re-enable using the HWSP on Cannolake. This reverts commit 61bf9719fa17 ("drm/i915/cnl: Use mmio access to context status buffer"). References: https://bugs.freedesktop.org/show_bug.cgi?id=105888 References: https://bugs.freedesktop.org/show_bug.cgi?id=106185 References: 61bf9719fa17 ("drm/i915/cnl: Use mmio access to context status buffer") Signed-off-by: Chris Wilson <[email protected]> Cc: Mika Kuoppala <[email protected]> Cc: Joonas Lahtinen <[email protected]> Cc: Tvrtko Ursulin <[email protected]> Cc: Michał Winiarski <[email protected]> Cc: Rafael Antognolli <[email protected]> Cc: Michel Thierry <[email protected]> Cc: Timo Aaltonen <[email protected]> Tested-by: Timo Aaltonen <[email protected]> Acked-by: Michel Thierry <[email protected]> Acked-by: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-05-11drm/i915/execlists: Use rmb() to order CSB readsChris Wilson1-0/+1
We assume that the CSB is written using the normal ringbuffer coherency protocols, as outlined in kernel/events/ring_buffer.c: * (HW) (DRIVER) * * if (LOAD ->data_tail) { LOAD ->data_head * (A) smp_rmb() (C) * STORE $data LOAD $data * smp_wmb() (B) smp_mb() (D) * STORE ->data_head STORE ->data_tail * } So we assume that the HW fulfils its ordering requirements (B), and so we should use a complimentary rmb (C) to ensure that our read of its WRITE pointer is completed before we start accessing the data. The final mb (D) is implied by the uncached mmio we perform to inform the HW of our READ pointer. References: https://bugs.freedesktop.org/show_bug.cgi?id=105064 References: https://bugs.freedesktop.org/show_bug.cgi?id=105888 References: https://bugs.freedesktop.org/show_bug.cgi?id=106185 Fixes: 767a983ab255 ("drm/i915/execlists: Read the context-status HEAD from the HWSP") References: 61bf9719fa17 ("drm/i915/cnl: Use mmio access to context status buffer") Suggested-by: Mika Kuoppala <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Cc: Mika Kuoppala <[email protected]> Cc: Joonas Lahtinen <[email protected]> Cc: Tvrtko Ursulin <[email protected]> Cc: Michał Winiarski <[email protected]> Cc: Rafael Antognolli <[email protected]> Cc: Michel Thierry <[email protected]> Cc: Timo Aaltonen <[email protected]> Tested-by: Timo Aaltonen <[email protected]> Acked-by: Michel Thierry <[email protected]> Acked-by: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-05-11drm/i915/icl: WaForwardProgressSoftResetOscar Mateo2-0/+12
Avoids a hang during soft reset. v2: Rebased on top of the WA refactoring v3: Added References (Mika) v4: - Rebased - C, not lisp (Chris) - Which steppings affected by this are not clear. For the moment, apply unconditionally as per the BSpec (Mika) - Add reference to another HSD also related References: HSDES#1405476379 References: HSDES#2006612137 Cc: Mika Kuoppala <[email protected]> Signed-off-by: Oscar Mateo <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> Signed-off-by: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-05-11drm/i915/icl: Wa_1406838659Oscar Mateo2-0/+9
Disable CGPSF unit clock gating to prevent an issue. v2: Rebased on top of the WA refactoring v3: Added References (Mika) v4: - Rebased - C, not lisp (Chris) - Remove unintentional whitespaces (Mika) - Fixed in C0 (Mika) References: HSDES#1406838659 Signed-off-by: Oscar Mateo <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> Signed-off-by: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-05-11drm/i915/icl: Wa_1604302699Oscar Mateo2-1/+8
Disable I2M Write for performance reasons. v2: Rebased on top of the WA refactoring v3: Added References (Mika) v4: - Rebased - C, not lisp (Chris) - GEN7 chicken bit in the wrong side of the fence (Mika) - Use two spaces to align bit macros References: HSDES#1604302699 Signed-off-by: Oscar Mateo <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> Signed-off-by: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-05-11drm/i915/icl: Wa_1406680159Oscar Mateo1-0/+5
Disable GWL clock gating to prevent an issue that might cause hangs. v2: Rebased on top of the WA refactoring v3: Wa_2201832410 officially merged with Wa_1406680159 v4: Added References (Mika) v5: - Rebased - C, not lisp (Chris) - Add reference where WA is better explained (Rodrigo) - Add reference to WA that got merged with this References: HSDES#1406681710 References: HSDES#1406680159 References: HSDES#2201832410 Signed-off-by: Oscar Mateo <[email protected]> Cc: Mika Kuoppala <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Signed-off-by: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-05-11drm/i915/icl: Wa_1405779004Oscar Mateo2-0/+7
Disable MSC clock gating to prevent data corruption. BSpec: 19257 v2: Rebased on top of the WA refactoring v3: Added References (Mika) v4: - Rebased - C, not lisp (Chris) - A0 only (Mika) References: HSDES#1405779004 Signed-off-by: Oscar Mateo <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> Signed-off-by: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-05-11drm/i915/icl: WaDisCtxReloadOscar Mateo2-0/+9
Revert to the legacy implementation to avoid a system hang. v2: Correct the address for GAMW_ECO_DEV_RW_IA_REG v3: Renamed to Wa_220166154 v4: Rebased on top of the WA refactoring v5: Added References (Mika) v6: - Rebased - C, not lisp (Chris) References: HSDES#220166154 Signed-off-by: Oscar Mateo <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> Signed-off-by: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-05-11drm/i915/icl: WaCL2SFHalfMaxAllocOscar Mateo2-0/+11
This workarounds an issue with insufficient storage for the CL2 and SF units. v2: Renamed to Wa_1405766107 v3: Wrapped the commit message v4: Rebased on top of the WA refactoring v5: Added References (Mika) v6: - Rebased - s/MACALLOC/MAXALLOC (Mika) - C, not lisp (Chris) References: HSDES#1405766107 Signed-off-by: Oscar Mateo <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> Signed-off-by: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-05-11drm/i915/icl: WaDisableCleanEvictsOscar Mateo2-2/+9
Avoids an undefined LLC behavior. BSpec: 9613 v2: Renamed to Wa_1405733216 v3: Spaces around '<<' and fix surrounding code v4: Rebased on top of the WA refactoring v5: Added References (Mika) v6: - Rebased - C, not lisp (Chris) References: HSDES#1405733216 Signed-off-by: Oscar Mateo <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> Signed-off-by: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-05-11drm/i915/icl: WaModifyGamTlbPartitioningOscar Mateo2-0/+10
Adjust default GAM TLB partitioning for performance reasons. v2: Only touch the bits that we really need v3: Rebased on top of the WA refactoring v4: - Added References (Mika) - Rebased v5: - Rebased - C, not lisp (Chris) - Correct reference number (Mika) References: HSDES#220160670 Signed-off-by: Oscar Mateo <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> Signed-off-by: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-05-11drm/i915/icl: WaL3BankAddressHashingOscar Mateo2-0/+16
Revert to an L3 non-hash model, for performance reasons. v2: - Place the WA name above the actual change - Improve the register naming v3: - Rebased - Renamed to Wa_1604223664 v4: Rebased on top of the WA refactoring v5: - Added References (Mika) - Fixed wrong mask and value (Mika) - Do not apply together with another WA for the same register (not worth the hassle) v6: - Rebased - C, not lisp (Chris) References: HSDES#1604223664 Signed-off-by: Oscar Mateo <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> Signed-off-by: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-05-11drm/i915/icl: WaGAPZPrioritySchemeOscar Mateo2-2/+9
The default GAPZ arbitrer priority value at power-on has been found to be incorrect. v2: Now renamed to Wa_1405543622 v3: Rebased on top of the WA refactoring v4: Added HSDES reference number (Mika) v5: - Rebased - C, not lisp (Chris) References: HSDES#1405543622 Signed-off-by: Oscar Mateo <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> Signed-off-by: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-05-11drm/i915/icl: Enable Sampler DFROscar Mateo2-1/+11
Sampler Dynamic Frequency Rebalancing (DFR) aims to reduce Sampler power by dynamically changing its clock frequency in low-throughput conditions. This patches enables it by default on Gen11. v2: Wrong operation to clear the bit (Praveen) v3: Rebased on top of the WA refactoring v4: Move to icl_init_clock_gating, since it's not a WA (Rodrigo) v5: C, not lisp (Chris) Signed-off-by: Oscar Mateo <[email protected]> Cc: Praveen Paneri <[email protected]> Cc: Mika Kuoppala <[email protected]> Reviewed-by: Sagar Arun Kamble <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Signed-off-by: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-05-11drm/i915/icl: Introduce initial Icelake WorkaroundsOscar Mateo7-6/+69
Inherit workarounds from previous platforms that are still valid for Icelake. v2: GEN7_ROW_CHICKEN2 is masked v3: - Since it has been fixed already in upstream, removed the TODO comment about WA_SET_BIT for WaInPlaceDecompressionHang. - Squashed with this patch: drm/i915/icl: add icelake_init_clock_gating() from Paulo Zanoni <[email protected]> - Squashed with this patch: drm/i915/icl: WaForceEnableNonCoherent from Oscar Mateo <[email protected]> - WaPushConstantDereferenceHoldDisable is now Wa_1604370585 and applies to B0 as well. - WaPipeControlBefore3DStateSamplePattern WABB was being applied to ICL incorrectly. v4: - Wrap the commit message - s/dev_priv/p to please checkpatch v5: Rebased on top of the WA refactoring v6: Rebased on top of further whitelist registers refactoring (Michel) v7: Added WaRsForcewakeAddDelayForAck v8: s/ICL_HDC_CHICKEN0/ICL_HDC_MODE (Mika) v9: - C, not lisp (Chris) - WaIncreaseDefaultTLBEntries is the same for GEN > 9_LP (Tvrtko) Signed-off-by: Oscar Mateo <[email protected]> Cc: Rodrigo Vivi <[email protected]> Cc: Tomasz Lis <[email protected]> Cc: Mika Kuoppala <[email protected]> Cc: Tvrtko Ursulin <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> Signed-off-by: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-05-11drm/i915/gtt: Trust the uncached store to flush wcbMika Kuoppala1-10/+8
Not all architectures guarantee that uncached read will flush the write combining buffer. So marking it explicitly is recommended [1]. However we know the architecture we are operating on and can avoid wmb as the UC store will flush the wcb [2]. Omit the wmb() before invalidate as redudant. v2: squash combining and removal (Chris) v3: remove obsolete comments about posting reads (Chris) References: http://yarchive.net/comp/linux/write_combining.html [1] References: http://download.intel.com/design/PentiumII/applnots/24442201.pdf [2] Cc: Chris Wilson <[email protected]> Cc: Matthew Auld <[email protected]> Signed-off-by: Mika Kuoppala <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-05-11drm/i915: Add NV12 as supported format for sprite planeChandra Konduru1-2/+22
This patch adds NV12 to list of supported formats for sprite plane. v2: Rebased (me) v3: Review comments by Ville addressed - Removed skl_plane_formats_with_nv12 and added NV12 case in existing skl_plane_formats - Added the 10bpc RGB formats v4: Addressed review comments from Clinton A Taylor "Why are we adding 10 bit RGB formats with the NV12 series patches? Trying to set XR30 or AB30 results in error returned even though the modes are advertised for the planes" - Removed 10bit RGB formats added previously with NV12 series v5: Missed the Tested-by/Reviewed-by in the previous series Adding the same to commit message in this version. Addressed review comments from Clinton A Taylor "Why are we adding 10 bit RGB formats with the NV12 series patches? Trying to set XR30 or AB30 results in error returned even though the modes are advertised for the planes" - Previous version has 10bit RGB format removed from VLV formats by mistake. Fixing that in this version. Removed 10bit RGB formats added previously with NV12 series for SKL. v6: Addressed review comments by Ville Restricting the NV12 to BXT and PIPE A and B v7: Rebased (me) v8: Rebased (me) Restricting NV12 changes to BXT and KBL Restricting NV12 changes for plane 0 (overlay) v9: Rebased (me) v10: Addressed review comments from Maarten. Adding NV12 to skl_plane_formats itself. v11: Addressed review comments from Shashank Sharma v12: Addressed review comments from Shashank Sharma Made the condition in intel_sprite_plane_create simple and easy to read as suggested. v13: Adding reviewed by tag from Shashank Sharma Addressed review comments from Juha-Pekka Heikkila "NV12 not to be supported by SKL" v14: Addressed review comments from Ville Added skl_planar_formats to include NV12 and a check skl_plane_has_planar in sprite create Added NV12 format to skl_mod_supported. These were review comments from Kristian Høgsberg <[email protected]> v15: Added reviewed by from Juha-Pekka Heikkila v16: Rebased the series v17: Added all tiling under mod supported for NV12 Credits to Megha Aggarwal v18: Added RB by Maarten and Kristian v19: Addressed review comments from Maarten Made modification to skl_mod_supported Credits-to: Megha Aggarwal <[email protected]> Credits-to: Kristian Høgsberg <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Maarten Lankhorst <[email protected]> Tested-by: Clinton Taylor <[email protected]> Reviewed-by: Juha-Pekka Heikkila <[email protected]> Reviewed-by: Shashank Sharma <[email protected]> Reviewed-by: Clinton Taylor <[email protected]> Signed-off-by: Chandra Konduru <[email protected]> Signed-off-by: Nabendu Maiti <[email protected]> Signed-off-by: Vidya Srinivas <[email protected]> Signed-off-by: Maarten Lankhorst <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-05-11drm/i915: Add NV12 as supported format for primary planeChandra Konduru2-2/+50
This patch adds NV12 to list of supported formats for primary plane v2: Rebased (Chandra Konduru) v3: Rebased (me) v4: Review comments by Ville addressed Removed the skl_primary_formats_with_nv12 and added NV12 case in existing skl_primary_formats v5: Rebased (me) v6: Missed the Tested-by/Reviewed-by in the previous series Adding the same to commit message in this version. v7: Review comments by Ville addressed Restricting the NV12 for BXT and on PIPE A and B Rebased (me) v8: Rebased (me) Modified restricting the NV12 support for both BXT and KBL. v9: Rebased (me) v10: Addressed review comments from Maarten. Adding NV12 inside skl_primary_formats itself. v11: Adding Reviewed By tag from Shashank Sharma v12: Addressed review comments from Juha-Pekka Heikkila "NV12 not to be supported by SKL" v13: Addressed review comments from Ville Added skl_pri_planar_formats to include NV12 and skl_plane_has_planar function to check for NV12 support on plane. Added NV12 format to skl_mod_supported. These were review comments from Kristian Høgsberg <[email protected]> v14: Added reviewed by from Juha-Pekka Heikkila v15: Rebased the series v16: Added all tiling support under mod supported for NV12. Credits to Megha Aggarwal v17: Added RB by Maarten and Kristian v18: Review comments from Maarten addressed - Removing BROXTON support for NV12 due to WA826 v19: Addressed review comments from Maarten Make changes to skl_mod_supported Credits-to: Megha Aggarwal [email protected] Credits-to: Maarten Lankhorst <[email protected]> Tested-by: Clinton Taylor <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Maarten Lankhorst <[email protected]> Reviewed-by: Juha-Pekka Heikkila <[email protected]> Reviewed-by: Clinton Taylor <[email protected]> Reviewed-by: Shashank Sharma <[email protected]> Signed-off-by: Chandra Konduru <[email protected]> Signed-off-by: Nabendu Maiti <[email protected]> Signed-off-by: Vidya Srinivas <[email protected]> Signed-off-by: Maarten Lankhorst <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-05-11drm/i915: Add NV12 support to intel_framebuffer_initChandra Konduru1-0/+22
This patch adds NV12 as supported format to intel_framebuffer_init and performs various checks. v2: -Fix an issue in checks added (Chandra Konduru) v3: rebased (me) v4: Review comments by Ville addressed Added platform check for NV12 in intel_framebuffer_init Removed offset checks for NV12 case v5: Addressed review comments by Clinton A Taylor This NV12 support only correctly works on SKL. Plane color space conversion is different on GLK and later platforms causing the colors to display incorrectly. Ville's plane color space property patch series in review will fix this issue. - Restricted the NV12 case in intel_framebuffer_init to SKL and BXT only. v6: Rebased (me) v7: Addressed review comments by Ville Restricting the NV12 to BXT for now. v8: Rebased (me) Restricting the NV12 changes to BXT and KBL for now. v9: Rebased (me) v10: NV12 supported by all GEN >= 9. Making this change in intel_framebuffer_init. This is part of addressing Maarten's review comments. Comment under v8 no longer applicable v11: Addressed review comments from Shashank Sharma v12: Adding Reviewed By from Shashank Sharma v13: Addressed review comments from Juha-Pekka Heikkila "NV12 not to be supported by SKL" v14: Addressed review comments from Maarten. Add checks for fb width height for NV12 and fail the fb creation if check fails. Added reviewed by from Juha-Pekka Heikkila v15: Rebased the series v16: Setting the minimum value during fb creating to 16 as per Bspec for NV12. Earlier minimum was expected to be > 16. Now changed it to >=16. v17: Adding restriction to framebuffer_init - the fb width and height should be a multiplier of 4 v18: Added RB from Maarten. Included Maarten's review comments Dont allow CCS formats for fb creation of NV12 v19: Review comments from Maarten addressed - Removing BROXTON support for NV12 due to WA826 Credits-to: Maarten Lankhorst <[email protected]> Tested-by: Clinton Taylor <[email protected]> Reviewed-by: Maarten Lankhorst <[email protected]> Reviewed-by: Shashank Sharma <[email protected]> Reviewed-by: Clinton Taylor <[email protected]> Reviewed-by: Juha-Pekka Heikkila <[email protected]> Signed-off-by: Chandra Konduru <[email protected]> Signed-off-by: Nabendu Maiti <[email protected]> Signed-off-by: Vidya Srinivas <[email protected]> Signed-off-by: Maarten Lankhorst <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-05-11drm/i915: Add skl_check_nv12_surface for NV12Maarten Lankhorst2-3/+29
We skip src trunction/adjustments for NV12 case and handle the sizes directly. Without this, pipe fifo underruns are seen on APL/KBL. v2: For NV12, making the src coordinates multiplier of 4 v3: Moving all the src coords handling code for NV12 to skl_check_nv12_surface v4: Added RB from Mika v5: Rebased the series. Removed checks of mult of 4 in skl_update_scaler, Added NV12 condition in intel_check_sprite_plane where src x/w is being checked for mult of 2 for yuv planes. v6: Made changes to skl_check_nv12_surface as per WA#1106 Reviewed-by: Mika Kahola <[email protected]> Signed-off-by: Vidya Srinivas <[email protected]> Signed-off-by: Maarten Lankhorst <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-05-11drm/i915: Enable Display WA 0528Vidya Srinivas1-3/+19
Possible hang with NV12 plane surface formats. WA: When the plane source pixel format is NV12, the CHICKEN_PIPESL_* register bit 22 must be set to 1 and the render decompression must not be enabled on any of the planes in that pipe. v2: removed unnecessary POSTING_READ v3: Added RB from Maarten v4: Removed support for NV12 for BROXTON Credits-to: Maarten Lankhorst <[email protected]> Reviewed-by: Maarten Lankhorst <[email protected]> Signed-off-by: Vidya Srinivas <[email protected]> Signed-off-by: Maarten Lankhorst <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-05-11drm/i915: Enable display workaround 827 for all planes, v2.Maarten Lankhorst3-18/+33
The workaround was applied only to the primary plane, but is required on all planes. Iterate over all planes in the crtc atomic check to see if the workaround is enabled, and only perform the actual toggling in the pre/post plane update functions. Changes since v1: - Track active NV12 planes in a nv12_planes bitmask. (Ville) v2: Removing BROXTON support for NV12 due to WA826 Signed-off-by: Maarten Lankhorst <[email protected]> Cc: Ville Syrjälä <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Signed-off-by: Maarten Lankhorst <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-05-09drm/i915/psr: Check if VBT says PSR can be enabled.Dhinakaran Pandiyan3-2/+7
Driver features data block has a boolean flag for PSR, use this to decide whether PSR should be enabled on a platform. The module parameter can still be used to override this. Note: The feature currently remains disabled by default for all platforms irrespective of what VBT says. Cc: Rodrigo Vivi <[email protected]> Signed-off-by: Dhinakaran Pandiyan <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-05-09drm/i915/guc: Make submission tasklet hardirq safeChris Wilson1-9/+25
Prepare to allow the GuC submission to be run from underneath a hardirq timer context (and not just the current softirq context) as is required for fast preemption resets and context switches. Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Tvrtko Ursulin <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-05-09drm/i915/execlists: Make submission tasklet hardirq safeChris Wilson1-13/+29
Prepare to allow the execlists submission to be run from underneath a hardirq timer context (and not just the current softirq context) as is required for fast preemption resets and context switches. Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Tvrtko Ursulin <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-05-09drm/i915/selftests: Only switch to kernel context when lockedChris Wilson1-1/+2
In igt_flush_test() we try to switch back to the kernel context, but we are only able to do so when we are called with struct_mutex held. More of my CI fallout from lockdep being temporarily suppressed :( Fixes: 4cdf65ce8cc2 ("drm/i915/selftests: Return to kernel context after each test") Signed-off-by: Chris Wilson <[email protected]> Cc: Mika Kuoppala <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-05-09drm/i915/selftests: Create mock_engine() under struct_mutexChris Wilson1-3/+6
Calling mock_engine() calls i915_timeline_init() and that requires struct_mutex to be held as it adds itself to the global list of timelines. This error was introduced by commit a89d1f921c15 ("drm/i915: Split i915_gem_timeline into individual timelines") but the issue was masked in CI by the earlier lockdep spam. Fixes: a89d1f921c15 ("drm/i915: Split i915_gem_timeline into individual timelines") Signed-off-by: Chris Wilson <[email protected]> Cc: Tvrtko Ursulin <[email protected]> Cc: Joonas Lahtinen <[email protected]> Cc: Michel Thierry <[email protected]> Reviewed-by: Michel Thierry <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-05-08drm/i915: Annotate timeline lock nestingChris Wilson1-1/+1
CI noticed <4>[ 23.430701] ============================================ <4>[ 23.430706] WARNING: possible recursive locking detected <4>[ 23.430713] 4.17.0-rc4-CI-CI_DRM_4156+ #1 Not tainted <4>[ 23.430720] -------------------------------------------- <4>[ 23.430725] systemd-udevd/169 is trying to acquire lock: <4>[ 23.430732] (ptrval) (&(&timeline->lock)->rlock){....}, at: move_to_timeline+0x48/0x12c [i915] <4>[ 23.430888] but task is already holding lock: <4>[ 23.430894] (ptrval) (&(&timeline->lock)->rlock){....}, at: i915_request_submit+0x1a/0x40 [i915] <4>[ 23.430995] other info that might help us debug this: <4>[ 23.431002] Possible unsafe locking scenario: <4>[ 23.431007] CPU0 <4>[ 23.431010] ---- <4>[ 23.431013] lock(&(&timeline->lock)->rlock); <4>[ 23.431021] lock(&(&timeline->lock)->rlock); <4>[ 23.431028] *** DEADLOCK *** <4>[ 23.431036] May be due to missing lock nesting notation <4>[ 23.431044] 5 locks held by systemd-udevd/169: <4>[ 23.431049] #0: (ptrval) (&dev->mutex){....}, at: __driver_attach+0x42/0xe0 <4>[ 23.431065] #1: (ptrval) (&dev->mutex){....}, at: __driver_attach+0x50/0xe0 <4>[ 23.431078] #2: (ptrval) (&dev->struct_mutex){+.+.}, at: i915_gem_init+0xca/0x630 [i915] <4>[ 23.431174] #3: (ptrval) (rcu_read_lock){....}, at: submit_notify+0x35/0x124 [i915] <4>[ 23.431271] #4: (ptrval) (&(&timeline->lock)->rlock){....}, at: i915_request_submit+0x1a/0x40 [i915] <4>[ 23.431369] stack backtrace: <4>[ 23.431377] CPU: 0 PID: 169 Comm: systemd-udevd Not tainted 4.17.0-rc4-CI-CI_DRM_4156+ #1 <4>[ 23.431385] Hardware name: Dell Inc. OptiPlex GX280 /0G8310, BIOS A04 02/09/2005 <4>[ 23.431394] Call Trace: <4>[ 23.431403] dump_stack+0x67/0x9b <4>[ 23.431411] __lock_acquire+0xc67/0x1b50 <4>[ 23.431421] ? ring_buffer_lock_reserve+0x154/0x3f0 <4>[ 23.431429] ? lock_acquire+0xa6/0x210 <4>[ 23.431435] lock_acquire+0xa6/0x210 <4>[ 23.431530] ? move_to_timeline+0x48/0x12c [i915] <4>[ 23.431540] _raw_spin_lock+0x2a/0x40 <4>[ 23.431634] ? move_to_timeline+0x48/0x12c [i915] <4>[ 23.431730] move_to_timeline+0x48/0x12c [i915] <4>[ 23.431826] __i915_request_submit+0xfa/0x280 [i915] <4>[ 23.431923] i915_request_submit+0x25/0x40 [i915] <4>[ 23.432024] i9xx_submit_request+0x11/0x140 [i915] <4>[ 23.432120] submit_notify+0x8d/0x124 [i915] <4>[ 23.432202] __i915_sw_fence_complete+0x81/0x250 [i915] <4>[ 23.432300] __i915_request_add+0x31c/0x7c0 [i915] <4>[ 23.432395] i915_gem_init+0x621/0x630 [i915] <4>[ 23.432476] i915_driver_load+0xbee/0x10b0 [i915] <4>[ 23.432485] ? trace_hardirqs_on_caller+0xe0/0x1b0 <4>[ 23.432566] i915_pci_probe+0x29/0x90 [i915] <4>[ 23.432574] pci_device_probe+0xa1/0x130 <4>[ 23.432582] driver_probe_device+0x306/0x480 <4>[ 23.432589] __driver_attach+0xb7/0xe0 <4>[ 23.432596] ? driver_probe_device+0x480/0x480 <4>[ 23.432602] ? driver_probe_device+0x480/0x480 <4>[ 23.432609] bus_for_each_dev+0x74/0xc0 <4>[ 23.432616] bus_add_driver+0x15f/0x250 <4>[ 23.432623] ? 0xffffffffa02d7000 <4>[ 23.432629] driver_register+0x52/0xc0 <4>[ 23.432635] ? 0xffffffffa02d7000 <4>[ 23.432642] do_one_initcall+0x58/0x370 <4>[ 23.432653] ? do_init_module+0x1d/0x1ea <4>[ 23.432660] ? rcu_read_lock_sched_held+0x6f/0x80 <4>[ 23.432667] ? kmem_cache_alloc_trace+0x282/0x2e0 <4>[ 23.432675] do_init_module+0x56/0x1ea <4>[ 23.432682] load_module+0x2435/0x2b20 <4>[ 23.432694] ? __se_sys_finit_module+0xd3/0xf0 <4>[ 23.432701] __se_sys_finit_module+0xd3/0xf0 <4>[ 23.432710] do_syscall_64+0x55/0x190 <4>[ 23.432717] entry_SYSCALL_64_after_hwframe+0x49/0xbe <4>[ 23.432724] RIP: 0033:0x7fa780782839 <4>[ 23.432729] RSP: 002b:00007ffcea73e668 EFLAGS: 00000246 ORIG_RAX: 0000000000000139 <4>[ 23.432738] RAX: ffffffffffffffda RBX: 0000561a472a4b30 RCX: 00007fa780782839 <4>[ 23.432745] RDX: 0000000000000000 RSI: 00007fa7804610e5 RDI: 000000000000000e <4>[ 23.432752] RBP: 00007fa7804610e5 R08: 0000000000000000 R09: 00007ffcea73e780 <4>[ 23.432758] R10: 000000000000000e R11: 0000000000000246 R12: 0000000000000000 <4>[ 23.432765] R13: 0000561a47296450 R14: 0000000000020000 R15: 0000561a472a4b30 but did not report it as an issue as it only occurred during the first module on boot. This is due to the removal of the distinct global timeline, and its separate lock class. So instead mark up the expected nesting. An alternative would be to define a separate lock class for the engine, but since we only expect to have a single point of nesting, we can avoid having multiple lock classes for the struct. Fixes: a89d1f921c15 ("drm/i915: Split i915_gem_timeline into individual timelines") Signed-off-by: Chris Wilson <[email protected]> Cc: Chris Wilson <[email protected]> Cc: Tvrtko Ursulin <[email protected]> Cc: Joonas Lahtinen <[email protected]> Tested-by: Michel Thierry <[email protected]> Reviewed-by: Tvrtko Ursulin <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-05-08drm/i915: Remove unused i915_flip tracepointsChris Wilson1-36/+0
The i915_flip* tracepoints are no longer in use since the removal of CS flip in commit 8b5d27b911d7 ("drm/i915: Remove intel_flip_work infrastructure") References: 8b5d27b911d7 ("drm/i915: Remove intel_flip_work infrastructure") Signed-off-by: Chris Wilson <[email protected]> Cc: Maarten Lankhorst <[email protected]> Cc: Ville Syrjälä <[email protected]> Cc: Daniel Vetter <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-05-08drm/i915: Disable tasklet scheduling across initial schedulingChris Wilson1-3/+2
During request submission, we call the engine->schedule() function so that we may reorder the active requests as required for inheriting the new request's priority. This may schedule several tasklets to run on the local CPU, but we will need to schedule the tasklets again for the new request. Delay all the local tasklets until the end, so that we only have to process the queue just once. v2: Beware PREEMPT_RCU, as then local_bh_disable() is then not a superset of rcu_read_lock(). Signed-off-by: Chris Wilson <[email protected]> Cc: Tvrtko Ursulin <[email protected]> Cc: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Tvrtko Ursulin <[email protected]>
2018-05-08drm/i915: Flush submission tasklet after bumping priorityChris Wilson1-1/+3
When called from process context tasklet_schedule() defers itself to ksoftirqd. From experience this may cause unacceptable latencies of over 200ms in executing the submission tasklet, our goal is to reprioritise the HW execution queue and trigger HW preemption immediately, so disable bh over the call to schedule and force the tasklet to run afterwards if scheduled. v2: Keep rcu_read_lock() around for PREEMPT_RCU Signed-off-by: Chris Wilson <[email protected]> Cc: Tvrtko Ursulin <[email protected]> Cc: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Tvrtko Ursulin <[email protected]>
2018-05-08drm/i915/selftests: Return to kernel context after each testChris Wilson1-0/+5
As we flush each test and wait for idle before the next, also switch back to the kernel context. This helps limit the amount of collateral damage a test may cause by resetting to the default state each time (and also helps clean up temporaries used by the test). Signed-off-by: Chris Wilson <[email protected]> Cc: Mika Kuoppala <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-05-08drm/i915: don't leak the pin_map on errorMatthew Auld1-4/+6
Add some onion to populate_lr_context. v2: prefer err_unpin_ctx drop the fixes tag, worst case we just spew a warn before everything is cleaned up and balance is restored Signed-off-by: Matthew Auld <[email protected]> Cc: Chris Wilson <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-05-08drm/i915/selftests: Flush GPU activity before completing live_contextsChris Wilson1-0/+3
igt_ctx_exec() expects that we retire all active requests/objects before completing, so that when we clean up the files afterwards they are ready to be freed. Before we do so, it is then prudent to ensure that we have indeed retired the GPU activity, raising an error if it fails. If we do not, we run the risk of triggering an assertion when freeing the object: __i915_gem_free_objects:4793 GEM_BUG_ON(i915_gem_object_is_active(obj)) Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-05-08drm/i915/selftests: Refactor common flush_test()Chris Wilson5-122/+93
Pull igt_flush_test() out into its own library before copying and pasting the code for a third time. Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-05-08drm/i915/userptr: reject zero user_sizeMatthew Auld1-0/+3
Operating on a zero sized GEM userptr object will lead to explosions. Fixes: 5cc9ed4b9a7a ("drm/i915: Introduce mapping of user pages into video memory (userptr) ioctl") Testcase: igt/gem_userptr_blits/input-checking Signed-off-by: Matthew Auld <[email protected]> Cc: Chris Wilson <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-05-08drm/i915/execlists: Cache the priolist when reschedulingChris Wilson1-3/+10
When rescheduling a change of dependencies, they all need to be added to the same priolist (at least the ones on the same engine!). Since we likely want to move a batch of requests, keep the priolist around. v2: Throw in an assert to catch trivial errors quickly. Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Joonas Lahtinen <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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