aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2018-06-18drm/i915/icl: GSE interrupt moves from DE_MISC to GU_MISCDhinakaran Pandiyan2-1/+52
The Graphics System Event(GSE) interrupt bit has a new location in the GU_MISC_INTERRUPT_{IIR, ISR, IMR, IER} registers. Since GSE was the only DE_MISC interrupt that was enabled, with this change we don't enable/handle any of DE_MISC interrupts for gen11. Credits to Paulo for pointing out the register change. v2: from DK raw_reg_[read/write], branch prediction hint and drop platform check (Mika) v3: From DK Early re-enable of master interrupt (Chris) Cc: Chris Wilson <[email protected]> Cc: Mika Kuoppala <[email protected]> Reviewed-by: Paulo Zanoni <[email protected]> Signed-off-by: Dhinakaran Pandiyan <[email protected]> [Paulo: bikesheds and rebases] Signed-off-by: Paulo Zanoni <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-06-18drm/i915/i915_reg.h: fix the checkpatch MACRO_ARG_PRECEDENCE issuesPaulo Zanoni1-21/+21
While I don't see any issue with the way these macros are being called today, let's protect them against operator precedence issues before they happen. Reviewed-by: Rodrigo Vivi <[email protected]> Signed-off-by: Paulo Zanoni <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-06-18drm/i915/i915_reg.h: fix the checkpatch SPACE_BEFORE_TAB issuesPaulo Zanoni1-7/+7
Since I'm touching the file I might as well fix this class of errors since they are just a few. Also drive-by fix the styling of the VLV_TURBO_SOC_OVERRIDE definitions instead of just the spaces before the tabs. Reviewed-by: Rodrigo Vivi <[email protected]> Signed-off-by: Paulo Zanoni <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-06-18drm/i915/i915_reg.h: fix the checkpatch SPACING issuesPaulo Zanoni1-1592/+1592
Because OCD. Now seriously, commit 1aa920ea0e85 ("drm/i915: add register macro definition style guide") has finally established a coding standard to be followed by the rest of the file, and I've been trying to request everybody to adhere to that since then. The problem is that when someone adds a new line to a register that has the wrong style, these people generally propagate the wrong style and I have to keep asking them to drive-by fix the whole register, which is not something I like to do and also creates extra work for them. Or I can ignore the propagation of the wrong coding style and feel anxious about it. On top of that, we now have our CI happily reminding us about these problems, which makes everything worse. So IMHO the best way to proceed is to fix the spacing issues in the file once and for all. Contributors will stop propagating the bad style when adding new bits to registers that already have bad style, we will stop asking them to redo their patches and the CI emails will become more relevant by having less semi-false errors. Yes, there will be some pain involved for backporters, but at least spacing issues like that are easy to spot and fix in the patch files. This patch was generated by: ../../../../scripts/checkpatch.pl -f --strict --types SPACING \ --fix-inplace i915_reg.h I manually checked the output and everything seems sane. v2: Single conflict around the addition of DP_TP_CTL_LINK_TRAIN_PAT4. Cc: Jani Nikula <[email protected]> Cc: Rodrigo Vivi <[email protected]> Cc: Joonas Lahtinen <[email protected]> Acked-by: Rodrigo Vivi <[email protected]> Reviewed-by: Jani Nikula <[email protected]> Signed-off-by: Paulo Zanoni <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-06-18drm/i915/audio: Add 810 MHz clock entries to dp_aud_n_m tableRadhakrishna Sripada1-0/+10
Expand the Maud/Naud table according to DP 1.4 spec to include entries for 810 MHz clock. This is required for audio to work with HBR3. Cc: Dhinakaran Pandiyan <[email protected]> Cc: Jani Nikula <[email protected]> Signed-off-by: Radhakrishna Sripada <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-06-18drm/i915/aml: Introducing Amber Lake platformJosé Roberto de Souza2-2/+8
Amber Lake uses the same gen graphics as Kaby Lake, including a id that were previously marked as reserved on Kaby Lake, but that now is moved to AML page. So, let's just move it to AML macro that will feed into KBL macro just to keep it better organized to make easier future code review but it will be handled as a KBL. Reviewed-by: Rodrigo Vivi <[email protected]> Signed-off-by: José Roberto de Souza <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-06-18drm/i915/whl: Introducing Whiskey Lake platformJosé Roberto de Souza2-11/+21
Whiskey Lake uses the same gen graphics as Coffe Lake, including some ids that were previously marked as reserved on Coffe Lake, but that now are moved to WHL page. So, let's just move them to WHL macros that will feed into CFL macro just to keep it better organized to make easier future code review but it will be handled as a CFL. v2: Fixing GT level of some ids Cc: Rodrigo Vivi <[email protected]> Signed-off-by: José Roberto de Souza <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-06-18drm/i915/execlists: Pull the w/a LRI emission into a helperChris Wilson2-17/+45
Having the w/a registers as an open-coded table leaves a trap for the unwary; it would be easy to miss incrementing the LRI counter when adding a new register to the list. Instead, pull the list of registers into a table, so that we only need add new registers to that table rather than try and remember important side-effects of earlier chunks of GPU instructions. Suggested-by: Joonas Lahtinen <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Cc: Joonas Lahtinen <[email protected]> Reviewed-by: Joonas Lahtinen <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-06-18drm/i915: Only show debug for state changes when banningChris Wilson1-5/+5
Since we trigger 10,000s of hangs and resets during selftesting, we emit many, many thousands of lines of useless debug messages. Reduce the frequency by only logging a change in state of a guilty context. Fixes: 14921f3cef85 ("drm/i915: Fix context ban and hang accounting for client") Signed-off-by: Chris Wilson <[email protected]> Cc: Mika Kuoppala <[email protected]> Reviewed-by: Joonas Lahtinen <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-06-18drm/i915/lspcon: switch to kernel unsigned int typesJani Nikula1-1/+1
We have fairly mixed uintN_t vs. uN usage throughout the driver, but try to stick to kernel types at least where it's more prevalent. Reviewed-by: Ville Syrjälä <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/1e132575785d9b615208eb60ee5e388df5991172.1528794959.git.jani.nikula@intel.com
2018-06-18drm/i915/audio: switch to kernel unsigned int typesJani Nikula1-18/+18
We have fairly mixed uintN_t vs. uN usage throughout the driver, but try to stick to kernel types at least where it's more prevalent. Reviewed-by: Ville Syrjälä <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/808b06e1f0a95a4ee892553abf11fdbc30025571.1528794959.git.jani.nikula@intel.com
2018-06-18drm/i915/backlight: switch to kernel unsigned int typesJani Nikula2-10/+10
We have fairly mixed uintN_t vs. uN usage throughout the driver, but try to stick to kernel types at least where it's more prevalent. Reviewed-by: Ville Syrjälä <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/e68c3f16738eb3ab9f276d797f20326ed6d15848.1528794959.git.jani.nikula@intel.com
2018-06-18drm/i915/dvo: switch to kernel unsigned int typesJani Nikula7-70/+70
We have fairly mixed uintN_t vs. uN usage throughout the driver, but try to stick to kernel types at least where it's more prevalent. v2: fix checkpatch warning on indentation Reviewed-by: Ville Syrjälä <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-06-18drm/i915/uncore: switch to kernel unsigned int typesJani Nikula1-11/+11
We have fairly mixed uintN_t vs. uN usage throughout the driver, but try to stick to kernel types at least where it's more prevalent. Reviewed-by: Ville Syrjälä <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/4af5f30fc9665d1bed1eed09e7f749737749d739.1528794959.git.jani.nikula@intel.com
2018-06-18drm/i915/hdmi: switch to kernel unsigned int typesJani Nikula1-7/+7
We have fairly mixed uintN_t vs. uN usage throughout the driver, but try to stick to kernel types at least where it's more prevalent. Reviewed-by: Ville Syrjälä <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/d8b79de3d52e1fcaeabf3abfbb2ed99c4397ff2b.1528794959.git.jani.nikula@intel.com
2018-06-18drm/i915/vbt: switch to kernel unsigned int typesJani Nikula2-3/+3
We have fairly mixed uintN_t vs. uN usage throughout the driver, but try to stick to kernel types at least where it's more prevalent. Reviewed-by: Ville Syrjälä <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/ed5de29c280797b20eb625d52592dcbba8326684.1528794959.git.jani.nikula@intel.com
2018-06-18drm/i915: Fix fallout of fake reset along resumeChris Wilson5-17/+31
commit b2209e62a450 ("drm/i915/execlists: Reset the CSB head tracking on reset/sanitization") and commit 1288786b18f7 ("drm/i915: Move GEM sanitize from resume_early to resume") show the conflicting requirements on the code. We must reset the GPU before trashing live state on a fast resume (hibernation debug, or error paths), but we must only reset our state tracking iff the GPU is reset (or power cycled). This is tricky if we are disabling GPU reset to simulate broken hardware; we reset our state tracking but the GPU is left intact and recovers from its stale state. v2: Again without the assertion for forcewake, no longer required since commit b3ee09a4de33 ("drm/i915/ringbuffer: Fix context restore upon reset") as the contexts are reset from the CS ensuring everything is powered up. Fixes: b2209e62a450 ("drm/i915/execlists: Reset the CSB head tracking on reset/sanitization") Fixes: 1288786b18f7 ("drm/i915: Move GEM sanitize from resume_early to resume") Signed-off-by: Chris Wilson <[email protected]> Cc: Tvrtko Ursulin <[email protected]> Cc: Mika Kuoppala <[email protected]> Cc: Joonas Lahtinen <[email protected]> Reviewed-by: Joonas Lahtinen <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-06-18drm/i915: Enable provoking vertex fix on Gen9 systems.Kenneth Graunke2-1/+16
The SF and clipper units mishandle the provoking vertex in some cases, which can cause misrendering with shaders that use flat shaded inputs. There are chicken bits in 3D_CHICKEN3 (for SF) and FF_SLICE_CHICKEN (for the clipper) that work around the issue. These registers are unfortunately not part of the logical context (even the power context), and so we must reload them every time we start executing in a context. Bugzilla: https://bugs.freedesktop.org/103047 Signed-off-by: Kenneth Graunke <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Joonas Lahtinen <[email protected]> Cc: [email protected]
2018-06-15drm/i915/icl: update VBT's child_device_config flags2 fieldPaulo Zanoni1-1/+3
Some bits from the flags2 field are going to be used in the next patches, so replace the whole-byte definition with the actual bits and document their versions. This patch is based on a patch by Animesh Manna. Cc: Animesh Manna <[email protected]> Credits-to: Animesh Manna <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Signed-off-by: Paulo Zanoni <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-06-15drm/i915/icl: implement DVFS for ICLPaulo Zanoni2-3/+45
ICL DVFS is almost the same as CNL, except for the CDCLK/DDICLK table. Implement it just like CNL does. References: commit 48469eced282 ("drm/i915: Use cdclk_state->voltage on CNL") References: commit 53e9bf5e8159 ("drm/i915: Adjust system agent voltage on CNL if required by DDI ports") Cc: Ville Syrjälä <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Signed-off-by: Paulo Zanoni <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-06-15drm/i915: s/IS_G4X && !IS_GM45/IS_G45/Ville Syrjälä3-3/+3
We have IS_G45 these days. Let's use it instead of the 'IS_G4X && !IS_GM45' construct. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Chris Wilson <[email protected]>
2018-06-15drm/i915/execlists: Reset the CSB head tracking on reset/sanitizationChris Wilson1-9/+6
We can avoid the mmio read of the CSB pointers after reset based on the knowledge that the HW always start writing at entry 0 in the CSB buffer. We need to reset our CSB head tracking after GPU reset (and on sanitization after resume) so that we are expecting to read from entry 0, hence we reset our head tracking back to the entry before (the last entry in the ring). Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Tvrtko Ursulin <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-06-15drm/i915: Be irqsafe inside resetChris Wilson1-2/+4
As we want to be able to call i915_reset_engine and co from a softirq or timer context, we need to be irqsafe at all times. So we have to forgo the simple spin_lock_irq for the full spin_lock_irqsave. Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Tvrtko Ursulin <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-06-15drm/i915: Fix context ban and hang accounting for clientMika Kuoppala3-25/+55
If client is smart or lucky enough to create a new context after each hang, our context banning mechanism will never catch up, and as a result of that it will be saved from client banning. This can result in a never ending streak of gpu hangs caused by bad or malicious client, preventing access from other legit gpu clients. Fix this by always incrementing per client ban score if it hangs in short successions regardless of context ban scoring. The exception are non bannable contexts. They remain detached from client ban scoring mechanism. v2: xchg timestamp, tidyup (Chris) v3: comment, bannable & banned together (Chris) Fixes: b083a0870c79 ("drm/i915: Add per client max context ban limit") Cc: Chris Wilson <[email protected]> Signed-off-by: Mika Kuoppala <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-06-15drm/i915: Keep the ctx workarounds tightly packedChris Wilson3-38/+52
For each platform, we have a few registers that are rewritten with different values -- they are not part of a sequence, just different parts of a masked register set at different times (e.g. platform and gen workarounds). Consolidate these into a single register write to keep the table compact, important since we are running of room in the current fixed sized buffer. While adjusting the construction of the wa table, make it non fatal so that the driver still loads but keeping the warning and extra details for inspection. Inspecting the changes for a Kabylake system, Before: Address val mask read 0x07014 0x20002000 0x00002000 0x00002100 0x0E194 0x01000100 0x00000100 0x00000114 0x0E4F0 0x81008100 0x00008100 0xFFFF8120 0x0E184 0x00200020 0x00000020 0x00000022 0x0E194 0x00140014 0x00000014 0x00000114 0x07004 0x00420042 0x00000042 0x000029C2 0x0E188 0x00080000 0x00000008 0x00008030 0x07300 0x80208020 0x00008020 0x00008830 0x07300 0x00100010 0x00000010 0x00008830 0x0E184 0x00020002 0x00000002 0x00000022 0x0E180 0x20002000 0x00002000 0x00002000 0x02580 0x00010000 0x00000001 0x00000004 0x02580 0x00060004 0x00000006 0x00000004 0x07014 0x01000100 0x00000100 0x00002100 0x0E100 0x00100010 0x00000010 0x00008050 After: Address val mask read 0x02580 0x00070004 0x00000007 0x00000004 0x07004 0x00420042 0x00000042 0x000029C2 0x07014 0x21002100 0x00002100 0x00002100 0x07300 0x80308030 0x00008030 0x00008830 0x0E100 0x00100010 0x00000010 0x00008050 0x0E180 0x20002000 0x00002000 0x00002000 0x0E184 0x00220022 0x00000022 0x00000022 0x0E188 0x00080000 0x00000008 0x00008030 0x0E194 0x01140114 0x00000114 0x00000114 0x0E4F0 0x81008100 0x00008100 0xFFFF8120 Signed-off-by: Chris Wilson <[email protected]> Cc: Oscar Mateo <[email protected]> Cc: Mika Kuoppala <[email protected]> Cc: Joonas Lahtinen <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-06-14drm/i915/dp: Add support for HBR3 and TPS4 during link trainingManasi Navare4-14/+44
DP spec 1.4 supports training pattern set 4 (TPS4) for HBR3 link rate. This will be used in link training's channel equalization phase if supported by both source and sink. This patch adds the helpers to check if HBR3 is supported and uses TPS4 in training pattern selection during link training. Cc: Rodrigo Vivi <[email protected]> Cc: Jani Nikula <[email protected]> Reviewed-by: James Ausmus <[email protected]> Signed-off-by: Manasi Navare <[email protected]> Signed-off-by: Paulo Zanoni <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-06-14drm/i915/icl: Add allowed DP rates for IcelakeManasi Navare1-2/+16
For ICL, on Combo PHY the allowed max rates are: - HBR3 8.1 eDP (DDIA) - HBR2 5.4 DisplayPort (DDIB) and for MG PHY/TC DDI Ports allowed DP rates are: - HBR3 8.1 DisplayPort (DP alternate mode, DP over TBT, - DP on legacy connector - DDIC/D/E/F) v2 (from Paulo): Remove misleading comment (Ville). Cc: Rodrigo Vivi <[email protected]> Cc: Jani Nikula <[email protected]> Reviewed-by: James Ausmus <[email protected]> Signed-off-by: Manasi Navare <[email protected]> Signed-off-by: James Ausmus <[email protected]> [Paulo: bikeshed to keep future platforms on "else", v2.] Signed-off-by: Paulo Zanoni <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-06-14drm/i915/icl: start adding the TBT pllPaulo Zanoni4-9/+47
This commit just adds the register addresses and the basic skeleton of the code. The next commits will expand on more specific functions. Reviewed-by: Lucas De Marchi <[email protected]> Signed-off-by: Paulo Zanoni <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-06-14drm/i915/icl: unconditionally init DDI for every portPaulo Zanoni1-1/+8
On ICP, port present straps (from SFUSE_STRAP PCH register) are no longer supported. Software should determine the presence through BIOS VBT, hotplug or other mechanisms. v2: Improve commit message (Lucas). Reviewed-by: Lucas De Marchi <[email protected]> Signed-off-by: Paulo Zanoni <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-06-14drm/i915/icl: add icelake_get_ddi_pll()Paulo Zanoni1-1/+41
Implement the hardware state readout code. Thanks to Animesh Manna for spotting this problem. Cc: Animesh Manna <[email protected]> Credits-to: Animesh Manna <[email protected]> Reviewed-by: Lucas De Marchi <[email protected]> Signed-off-by: Paulo Zanoni <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-06-14drm/i915/gtt: Reduce a pair of runtime assertsChris Wilson2-3/+3
We can stop asserting using WARN_ON as given sufficient CI coverage, we can rely on using GEM_BUG_ON() to catch problems before merging. Signed-off-by: Chris Wilson <[email protected]> Cc: Joonas Lahtinen <[email protected]> Cc: Mika Kuoppala <[email protected]> Cc: Matthew Auld <[email protected]> Reviewed-by: Matthew Auld <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-06-14drm/i915/gtt: Cache the PTE encoding of the scratch pageChris Wilson2-10/+11
As the most frequent PTE encoding is for the scratch page, cache it upon creation. Signed-off-by: Chris Wilson <[email protected]> Cc: Joonas Lahtinen <[email protected]> Cc: Mika Kuoppala <[email protected]> Cc: Matthew Auld <[email protected]> Reviewed-by: Matthew Auld <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-06-14drm/i915/gtt: Free unused page tables on unbind the contextChris Wilson2-5/+40
As we cannot reliably change used page tables while the context is active, the earliest opportunity we have to recover excess pages is when the context becomes idle. So whenever we unbind the context (it must be idle, and indeed being evicted) free the unused ptes. Signed-off-by: Chris Wilson <[email protected]> Cc: Joonas Lahtinen <[email protected]> Cc: Mika Kuoppala <[email protected]> Cc: Matthew Auld <[email protected]> Reviewed-by: Matthew Auld <[email protected]> Reviewed-by: Joonas Lahtinen <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-06-14drm/i915/gtt: Lazily allocate page directories for gen7Chris Wilson1-41/+26
As we were only supporting aliasing_ppgtt on gen7 for some time, we saved a few checks by preallocating the page directories on creation. However, since we need 2MiB of page directories for each ppgtt, to support arbitrary numbers of user contexts, we need to be more prudent in our allocations, and defer the page allocation until it is used. We don't recover unused pages yet as we found that doing so on the fly (i.e. altering TLB entries) would confuse the GPU. Signed-off-by: Chris Wilson <[email protected]> Cc: Joonas Lahtinen <[email protected]> Cc: Mika Kuoppala <[email protected]> Cc: Matthew Auld <[email protected]> Reviewed-by: Matthew Auld <[email protected]> Reviewed-by: Joonas Lahtinen <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-06-14drm/i915: Declare the driver wedged if hangcheck makes no progressChris Wilson4-4/+23
Hangcheck is our back up in case the GPU or the driver gets stuck. It detects when the GPU is not making any progress and issues a GPU reset. However, if the driver is failing to make any progress, we can get ourselves into a situation where we continually try resetting the GPU to no avail. Employ a second timeout such that if we continue to see the same seqno (the stalled engine has made no progress at all) over the course of several hangchecks, declare the driver wedged and attempt to start afresh. Signed-off-by: Chris Wilson <[email protected]> Cc: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Mika Kuoppala <[email protected]>
2018-06-14drm/i915/execlists: Push the tasklet kick after reset to reset_finishChris Wilson1-6/+7
In the unlikely case where we have failed to keep submitting to the GPU, we end up with the ELSP queue empty but a pending queue of requests. Here, we skip the per-engine reset as there is no guilty request, but in doing so we also skip the engine restart leaving ourselves with a permanently hung engine. A quick way to recover is by moving the tasklet kick to execlists_reset_finish() (from init_hw). We still emit the error on hanging, so the error is not lost but we should be able to recover. Signed-off-by: Chris Wilson <[email protected]> Cc: Mika Kuoppala <[email protected]> Cc: Tvrtko Ursulin <[email protected]> Cc: Michel Thierry <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Mika Kuoppala <[email protected]>
2018-06-14drm/i915/selftests: Initialise request to silence a compilerChris Wilson1-2/+2
With an old (4.7.3 on 32bit) gcc, it emits a warning for In file included from drivers/gpu/drm/i915/i915_request.c:1425:0: drivers/gpu/drm/i915/selftests/i915_request.c: In function ‘live_nop_request’: drivers/gpu/drm/i915/selftests/i915_request.c:380:21: error: ‘request’ may be used uninitialized in this function [-Werror=maybe-uninitialized] Silence it by just setting it to NULL on initialisation. Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-06-14drm/i915: Turn off g4x DP port in .post_disable()Ville Syrjälä1-16/+8
While Bspec doesn't list a specific sequence for turning off the DP port on g4x we are getting an underrun if the port is disabled in the .disable() hook. Looks like the pipe stops when the port stops, and by that time the plane disable may not have completed yet. Also the plane(s) seem to end up in some wonky state when this happens as they also signal another underrun immediately after we turn them back on during the next enable sequence. We could add a vblank wait in .disable() to avoid wedging the planes, but I assume we're still tripping up the pipe in some way. So it seems better to me to just follow the ILK+ sequence and turn off the DP port in .post_disable() instead. This sequence doesn't seem to suffer from this problem. Could be it was always the intended sequence for DP and the gen4 bspec was just never updated to include it. Originally we used the bad sequence even on ilk+, but I changed that in commit 08aff3fe26ae ("drm/i915: Move DP port disable to post_disable for pch platforms") as it was causing issues on those platforms as well. I left out g4x then only because I didn't have the hardware to test it. Now that I do it's fairly clear that the ilk+ sequence is also the right choice for g4x. v2: Fix whitespace fail (Jani) Mention the ilk+ commit (Jani) Cc: [email protected] Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Jani Nikula <[email protected]>
2018-06-14drm/i915: Disallow interlaced modes on g4x DP outputsVille Syrjälä1-2/+2
Looks like interlaced DP output doesn't work on g4x either. Not all that surprising considering we already established that interlaced DP output is busted on VLV/CHV. Cc: [email protected] Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-06-14drm/i915: Fix PIPESTAT irq ack on i965/g4xVille Syrjälä1-2/+10
On i965/g4x IIR is edge triggered. So in order for IIR to notice that there is still a pending interrupt we have to force and edge in ISR. For the ISR/IIR pipe event bits we can do that by temporarily clearing all the PIPESTAT enable bits when we ack the status bits. This will force the ISR pipe event bit low, and it can then go back high when we restore the PIPESTAT enable bits. This avoids the following race: 1. stat = read(PIPESTAT) 2. an enabled PIPESTAT status bit goes high 3. write(PIPESTAT, enable|stat); 4. write(IIR, PIPE_EVENT) The end result is IIR==0 and ISR!=0. This can lead to nasty vblank wait/flip_done timeouts if another interrupt source doesn't trick us into looking at the PIPESTAT status bits despite the IIR PIPE_EVENT bit being low. Before i965 IIR was level triggered so this problem can't actually happen there. And curiously VLV/CHV went back to the level triggered scheme as well. But for simplicity we'll use the same i965/g4x compatible code for all platforms. Cc: [email protected] Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106033 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105225 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106030 Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Chris Wilson <[email protected]>
2018-06-14drm/i915/ddi: Removed unused var from hsw_write_infoframe()Imre Deak1-3/+0
Cc: Vandita Kulkarni <[email protected]> Cc: Paulo Zanoni <[email protected]> Cc: Ville Syrjälä <[email protected]> Signed-off-by: Imre Deak <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-06-14drm/i915/ddi: Set HDMI infoframes with pipe clocks enabledImre Deak1-5/+5
On ICL for setting the HDMI infoframe the pipe clock needs to be enabled, otherwise accessing the VIDEO_DIP_CTL register will hang the machine. Cc: Vandita Kulkarni <[email protected]> Cc: Paulo Zanoni <[email protected]> Cc: Ville Syrjälä <[email protected]> Signed-off-by: Imre Deak <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-06-14drm/i915/ddi: Check transcoder instead of port when setting HDMI infoframeImre Deak1-2/+11
The only requirement by BSpec for setting the HDMI infoframes is on DDI platforms to do that before enabling the HDMI transcoder function, see VIDEO_DIP_CTL bit 16. Accordingly check for the transcoder function disabled state instead of the port's disabled state on DDI platforms. This is needed by the next patch as it will set the infoframe during crtc disabling where the port is still enabled. Suggested-by: Ville Syrjälä <[email protected]> Cc: Vandita Kulkarni <[email protected]> Cc: Paulo Zanoni <[email protected]> Cc: Ville Syrjälä <[email protected]> Signed-off-by: Imre Deak <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-06-14drm/i915/ddi: Push pipe clock enabling to encodersImre Deak3-6/+12
On ICL the pipe clock needs to be enabled before setting the HDMI infoframe, but these steps are in the reverse order atm. Move the pipe clock enabling to the encoders, so reordering of the two steps can be done in a clean way. No functional change. v2: - Rebased on drm-tip. Cc: Vandita Kulkarni <[email protected]> Cc: Paulo Zanoni <[email protected]> Cc: Ville Syrjälä <[email protected]> Signed-off-by: Imre Deak <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-06-14drm/i915/ddi: s/crtc->config/old_crtc_state in haswell_crtc_disable()Imre Deak1-4/+4
crtc->config points to the old crtc state at the point display.crtc_disable() is called, so use the more descriptive pointer instead. v2: - Convert one remaining instance of the ptr in the function. (Ville) Cc: Vandita Kulkarni <[email protected]> Cc: Paulo Zanoni <[email protected]> Cc: Ville Syrjälä <[email protected]> Signed-off-by: Imre Deak <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-06-14drm/i915/psr: Kill delays when activating psr back.Rodrigo Vivi3-25/+8
The immediate enabling was actually not an issue for the HW perspective for core platforms that have HW tracking. HW will wait few identical idle frames before transitioning to actual psr active anyways. Now that we removed VLV/CHV out of the picture completely we can safely remove any delays. Note that this patch also remove the delayed activation on HSW and BDW introduced by commit 'd0ac896a477d ("drm/i915: Delay first PSR activation.")'. This was introduced to fix a blank screen on VLV/CHV and also masked some frozen screens on other core platforms. Probably the same that we are now properly hunting and fixing. v2:(DK): Remove unnecessary WARN_ONs and make some other VLV | CHV more readable. v3: Do it regardless the timer rework. v4: (DK/CI): Add VLV || CHV check on cancel work at psr_disable. v5: Kill remaining items and fully rework activation functions. v6: Rebase on top of VLV/CHV clean-up and keep the reactivation on a regular non-delayed work to avoid extra delays on exit calls and allow us to add few more safety checks before real activation. Cc: Dhinakaran Pandiyan <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]> Reviewed-by: José Roberto de Souza <[email protected]> Reviewed-by: Dhinakaran Pandiyan <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-06-14drm/i915/gtt: Only keep gen6 page directories pinned while activeChris Wilson3-15/+54
In order to be able to evict the gen6 ppgtt, we have to unpin it at some point. We can simply use our context activity tracking to know when the ppgtt is no longer in use by hardware, and so only keep it pinned while being used a request. For the kernel_context (and thus aliasing_ppgtt), it remains pinned at all times, as the kernel_context itself is pinned at all times. Signed-off-by: Chris Wilson <[email protected]> Cc: Joonas Lahtinen <[email protected]> Cc: Mika Kuoppala <[email protected]> Cc: Matthew Auld <[email protected]> Reviewed-by: Joonas Lahtinen <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-06-14drm/i915: Show CCID in engine dumpsChris Wilson1-0/+2
For debugging context issues, knowing what context the GPU is loading/using is helpful. Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Joonas Lahtinen <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-06-14drm/i915: Make the hexdump row offset visually distinctChris Wilson1-1/+1
Currently we use %08x for the row offset, and %08x for the binary contents of the buffer. This makes it very easily to confuse the two, so switch to using [%04x] for the start-of-row offset. Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Joonas Lahtinen <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-06-14drm/i915: Dump the ringbuffer of the active request for debuggingChris Wilson1-5/+36
Sometimes we need to see what instructions we emitted for a request to try and gather a glimmer of insight into what the GPU is doing when it stops responding. v2: Move ring dumping into its own routine Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Joonas Lahtinen <[email protected]>
Powered by cgit, Gruvboxed by Blaster4385.