diff options
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/sandybridge/cache.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/sandybridge/cache.json | 173 |
1 files changed, 173 insertions, 0 deletions
diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/cache.json b/tools/perf/pmu-events/arch/x86/sandybridge/cache.json index 4e5572ee7dfe..b5b1e160eba1 100644 --- a/tools/perf/pmu-events/arch/x86/sandybridge/cache.json +++ b/tools/perf/pmu-events/arch/x86/sandybridge/cache.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Allocated L1D data cache lines in M state.", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "L1D.ALLOCATED_IN_M", "SampleAfterValue": "2000003", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Cache lines in M state evicted out of L1D due to Snoop HitM or dirty line replacement.", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "L1D.ALL_M_REPLACEMENT", "SampleAfterValue": "2000003", @@ -15,6 +17,7 @@ }, { "BriefDescription": "L1D data cache lines in M state evicted due to replacement.", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "L1D.EVICTION", "SampleAfterValue": "2000003", @@ -22,6 +25,7 @@ }, { "BriefDescription": "L1D data line replacements.", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "L1D.REPLACEMENT", "PublicDescription": "This event counts L1D data line replacements. Replacements occur when a new line is brought into the cache, causing eviction of a line loaded earlier.", @@ -30,6 +34,7 @@ }, { "BriefDescription": "Cycles when dispatched loads are cancelled due to L1D bank conflicts with other load ports.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xBF", "EventName": "L1D_BLOCKS.BANK_CONFLICT_CYCLES", @@ -38,6 +43,7 @@ }, { "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers unavailability.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.FB_FULL", @@ -46,6 +52,7 @@ }, { "BriefDescription": "L1D miss outstanding duration in cycles.", + "Counter": "2", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING", "SampleAfterValue": "2000003", @@ -53,6 +60,7 @@ }, { "BriefDescription": "Cycles with L1D load Misses outstanding.", + "Counter": "2", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING_CYCLES", @@ -62,6 +70,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.", + "Counter": "2", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", @@ -70,6 +79,7 @@ }, { "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L2_L1D_WB_RQSTS.ALL", "SampleAfterValue": "200003", @@ -77,6 +87,7 @@ }, { "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L2_L1D_WB_RQSTS.HIT_E", "SampleAfterValue": "200003", @@ -84,6 +95,7 @@ }, { "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L2_L1D_WB_RQSTS.HIT_M", "SampleAfterValue": "200003", @@ -91,6 +103,7 @@ }, { "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in S state.", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L2_L1D_WB_RQSTS.HIT_S", "SampleAfterValue": "200003", @@ -98,6 +111,7 @@ }, { "BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.).", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L2_L1D_WB_RQSTS.MISS", "SampleAfterValue": "200003", @@ -105,6 +119,7 @@ }, { "BriefDescription": "L2 cache lines filling L2.", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.ALL", "PublicDescription": "This event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2 cache when there was an L2 miss.", @@ -113,6 +128,7 @@ }, { "BriefDescription": "L2 cache lines in E state filling L2.", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.E", "SampleAfterValue": "100003", @@ -120,6 +136,7 @@ }, { "BriefDescription": "L2 cache lines in I state filling L2.", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.I", "SampleAfterValue": "100003", @@ -127,6 +144,7 @@ }, { "BriefDescription": "L2 cache lines in S state filling L2.", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.S", "SampleAfterValue": "100003", @@ -134,6 +152,7 @@ }, { "BriefDescription": "Clean L2 cache lines evicted by demand.", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_CLEAN", "SampleAfterValue": "100003", @@ -141,6 +160,7 @@ }, { "BriefDescription": "Dirty L2 cache lines evicted by demand.", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_DIRTY", "SampleAfterValue": "100003", @@ -148,6 +168,7 @@ }, { "BriefDescription": "Dirty L2 cache lines filling the L2.", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DIRTY_ALL", "SampleAfterValue": "100003", @@ -155,6 +176,7 @@ }, { "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch.", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.PF_CLEAN", "SampleAfterValue": "100003", @@ -162,6 +184,7 @@ }, { "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch.", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.PF_DIRTY", "SampleAfterValue": "100003", @@ -169,6 +192,7 @@ }, { "BriefDescription": "L2 code requests.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_CODE_RD", "SampleAfterValue": "200003", @@ -176,6 +200,7 @@ }, { "BriefDescription": "Demand Data Read requests.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", "SampleAfterValue": "200003", @@ -183,6 +208,7 @@ }, { "BriefDescription": "Requests from L2 hardware prefetchers.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_PF", "SampleAfterValue": "200003", @@ -190,6 +216,7 @@ }, { "BriefDescription": "RFO requests to L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_RFO", "SampleAfterValue": "200003", @@ -197,6 +224,7 @@ }, { "BriefDescription": "L2 cache hits when fetching instructions, code reads.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.CODE_RD_HIT", "SampleAfterValue": "200003", @@ -204,6 +232,7 @@ }, { "BriefDescription": "L2 cache misses when fetching instructions.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.CODE_RD_MISS", "SampleAfterValue": "200003", @@ -211,6 +240,7 @@ }, { "BriefDescription": "Demand Data Read requests that hit L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", "SampleAfterValue": "200003", @@ -218,6 +248,7 @@ }, { "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.PF_HIT", "SampleAfterValue": "200003", @@ -225,6 +256,7 @@ }, { "BriefDescription": "Requests from the L2 hardware prefetchers that miss L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.PF_MISS", "SampleAfterValue": "200003", @@ -232,6 +264,7 @@ }, { "BriefDescription": "RFO requests that hit L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_HIT", "SampleAfterValue": "200003", @@ -239,6 +272,7 @@ }, { "BriefDescription": "RFO requests that miss L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_MISS", "SampleAfterValue": "200003", @@ -246,6 +280,7 @@ }, { "BriefDescription": "RFOs that access cache lines in any state.", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_STORE_LOCK_RQSTS.ALL", "SampleAfterValue": "200003", @@ -253,6 +288,7 @@ }, { "BriefDescription": "RFOs that hit cache lines in E state.", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_STORE_LOCK_RQSTS.HIT_E", "SampleAfterValue": "200003", @@ -260,6 +296,7 @@ }, { "BriefDescription": "RFOs that hit cache lines in M state.", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_STORE_LOCK_RQSTS.HIT_M", "SampleAfterValue": "200003", @@ -267,6 +304,7 @@ }, { "BriefDescription": "RFOs that miss cache lines.", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_STORE_LOCK_RQSTS.MISS", "SampleAfterValue": "200003", @@ -274,6 +312,7 @@ }, { "BriefDescription": "L2 or LLC HW prefetches that access L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.ALL_PF", "SampleAfterValue": "200003", @@ -281,6 +320,7 @@ }, { "BriefDescription": "Transactions accessing L2 pipe.", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.ALL_REQUESTS", "SampleAfterValue": "200003", @@ -288,6 +328,7 @@ }, { "BriefDescription": "L2 cache accesses when fetching instructions.", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.CODE_RD", "SampleAfterValue": "200003", @@ -295,6 +336,7 @@ }, { "BriefDescription": "Demand Data Read requests that access L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.DEMAND_DATA_RD", "SampleAfterValue": "200003", @@ -302,6 +344,7 @@ }, { "BriefDescription": "L1D writebacks that access L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.L1D_WB", "SampleAfterValue": "200003", @@ -309,6 +352,7 @@ }, { "BriefDescription": "L2 fill requests that access L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.L2_FILL", "SampleAfterValue": "200003", @@ -316,6 +360,7 @@ }, { "BriefDescription": "L2 writebacks that access L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.L2_WB", "SampleAfterValue": "200003", @@ -323,6 +368,7 @@ }, { "BriefDescription": "RFO requests that access L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.RFO", "SampleAfterValue": "200003", @@ -330,6 +376,7 @@ }, { "BriefDescription": "Cycles when L1D is locked.", + "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", "SampleAfterValue": "2000003", @@ -337,6 +384,7 @@ }, { "BriefDescription": "Core-originated cacheable demand requests missed LLC.", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.MISS", "SampleAfterValue": "100003", @@ -344,6 +392,7 @@ }, { "BriefDescription": "Core-originated cacheable demand requests that refer to LLC.", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.REFERENCE", "SampleAfterValue": "100003", @@ -351,6 +400,7 @@ }, { "BriefDescription": "Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache. (Precise Event - PEBS).", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", "PEBS": "1", @@ -360,6 +410,7 @@ }, { "BriefDescription": "Retired load uops which data sources were HitM responses from shared LLC. (Precise Event - PEBS).", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", "PEBS": "1", @@ -369,6 +420,7 @@ }, { "BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. (Precise Event - PEBS).", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", "PEBS": "1", @@ -377,6 +429,7 @@ }, { "BriefDescription": "Retired load uops which data sources were hits in LLC without snoops required. (Precise Event - PEBS).", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", "PEBS": "1", @@ -385,6 +438,7 @@ }, { "BriefDescription": "Retired load uops with unknown information as data source in cache serviced the load. (Precise Event - PEBS).", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS", "PEBS": "1", @@ -394,6 +448,7 @@ }, { "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. (Precise Event - PEBS).", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", "PEBS": "1", @@ -402,6 +457,7 @@ }, { "BriefDescription": "Retired load uops with L1 cache hits as data sources. (Precise Event - PEBS).", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", "PEBS": "1", @@ -410,6 +466,7 @@ }, { "BriefDescription": "Retired load uops with L2 cache hits as data sources. (Precise Event - PEBS).", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", "PEBS": "1", @@ -418,6 +475,7 @@ }, { "BriefDescription": "Retired load uops which data sources were data hits in LLC without snoops required. (Precise Event - PEBS).", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT", "PEBS": "1", @@ -427,6 +485,7 @@ }, { "BriefDescription": "All retired load uops. (Precise Event - PEBS).", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", "PEBS": "1", @@ -436,6 +495,7 @@ }, { "BriefDescription": "All retired store uops. (Precise Event - PEBS).", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.ALL_STORES", "PEBS": "1", @@ -445,6 +505,7 @@ }, { "BriefDescription": "Retired load uops with locked access. (Precise Event - PEBS).", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", "PEBS": "1", @@ -453,6 +514,7 @@ }, { "BriefDescription": "Retired load uops that split across a cacheline boundary. (Precise Event - PEBS).", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", "PEBS": "1", @@ -462,6 +524,7 @@ }, { "BriefDescription": "Retired store uops that split across a cacheline boundary. (Precise Event - PEBS).", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", "PEBS": "1", @@ -471,6 +534,7 @@ }, { "BriefDescription": "Retired load uops that miss the STLB. (Precise Event - PEBS).", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", "PEBS": "1", @@ -479,6 +543,7 @@ }, { "BriefDescription": "Retired store uops that miss the STLB. (Precise Event - PEBS).", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", "PEBS": "1", @@ -487,6 +552,7 @@ }, { "BriefDescription": "Demand and prefetch data reads.", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", "SampleAfterValue": "100003", @@ -494,6 +560,7 @@ }, { "BriefDescription": "Cacheable and noncacheable code read requests.", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", "SampleAfterValue": "100003", @@ -501,6 +568,7 @@ }, { "BriefDescription": "Demand Data Read requests sent to uncore.", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", "SampleAfterValue": "100003", @@ -508,6 +576,7 @@ }, { "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM.", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", "SampleAfterValue": "100003", @@ -515,6 +584,7 @@ }, { "BriefDescription": "Cases when offcore requests buffer cannot take more entries for core.", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", "SampleAfterValue": "2000003", @@ -522,6 +592,7 @@ }, { "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore.", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", "SampleAfterValue": "2000003", @@ -529,6 +600,7 @@ }, { "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", @@ -537,6 +609,7 @@ }, { "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", @@ -545,6 +618,7 @@ }, { "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", @@ -553,6 +627,7 @@ }, { "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", "SampleAfterValue": "2000003", @@ -560,6 +635,7 @@ }, { "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.", + "Counter": "0,1,2,3", "CounterMask": "6", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_C6", @@ -568,6 +644,7 @@ }, { "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore.", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", "SampleAfterValue": "2000003", @@ -575,6 +652,7 @@ }, { "BriefDescription": "Counts demand & prefetch code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -584,6 +662,7 @@ }, { "BriefDescription": "Counts demand & prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -593,6 +672,7 @@ }, { "BriefDescription": "Counts demand & prefetch code reads that hit in the LLC and the snoops sent to sibling cores return clean response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -602,6 +682,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -611,6 +692,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads that hit in the LLC.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -620,6 +702,7 @@ }, { "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -629,6 +712,7 @@ }, { "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -638,6 +722,7 @@ }, { "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -647,6 +732,7 @@ }, { "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops sent to sibling cores return clean response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -656,6 +742,7 @@ }, { "BriefDescription": "Counts all prefetch code reads that hit in the LLC.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -665,6 +752,7 @@ }, { "BriefDescription": "Counts prefetch code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -674,6 +762,7 @@ }, { "BriefDescription": "Counts prefetch code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -683,6 +772,7 @@ }, { "BriefDescription": "Counts prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -692,6 +782,7 @@ }, { "BriefDescription": "Counts prefetch code reads that hit in the LLC and the snoops sent to sibling cores return clean response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -701,6 +792,7 @@ }, { "BriefDescription": "Counts all prefetch data reads that hit in the LLC.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -710,6 +802,7 @@ }, { "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -719,6 +812,7 @@ }, { "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -728,6 +822,7 @@ }, { "BriefDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -737,6 +832,7 @@ }, { "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoops sent to sibling cores return clean response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -746,6 +842,7 @@ }, { "BriefDescription": "Counts all prefetch RFOs that hit in the LLC.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -755,6 +852,7 @@ }, { "BriefDescription": "Counts prefetch RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -764,6 +862,7 @@ }, { "BriefDescription": "Counts prefetch RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -773,6 +872,7 @@ }, { "BriefDescription": "Counts prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -782,6 +882,7 @@ }, { "BriefDescription": "Counts prefetch RFOs that hit in the LLC and the snoops sent to sibling cores return clean response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -791,6 +892,7 @@ }, { "BriefDescription": "Counts all data/code/rfo references (demand & prefetch) .", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -800,6 +902,7 @@ }, { "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -809,6 +912,7 @@ }, { "BriefDescription": "Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -818,6 +922,7 @@ }, { "BriefDescription": "Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -827,6 +932,7 @@ }, { "BriefDescription": "Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -836,6 +942,7 @@ }, { "BriefDescription": "Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops sent to sibling cores return clean response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -845,6 +952,7 @@ }, { "BriefDescription": "Counts all demand & prefetch prefetch RFOs .", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -854,6 +962,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs that hit in the LLC.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -863,6 +972,7 @@ }, { "BriefDescription": "Counts demand & prefetch RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -872,6 +982,7 @@ }, { "BriefDescription": "Counts demand & prefetch RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -881,6 +992,7 @@ }, { "BriefDescription": "Counts demand & prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -890,6 +1002,7 @@ }, { "BriefDescription": "Counts demand & prefetch RFOs that hit in the LLC and the snoops sent to sibling cores return clean response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -899,6 +1012,7 @@ }, { "BriefDescription": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -908,6 +1022,7 @@ }, { "BriefDescription": "REQUEST = DATA_INTO_CORE and RESPONSE = ANY_RESPONSE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -917,6 +1032,7 @@ }, { "BriefDescription": "Counts all demand code reads.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -926,6 +1042,7 @@ }, { "BriefDescription": "Counts all demand code reads that hit in the LLC.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -935,6 +1052,7 @@ }, { "BriefDescription": "Counts demand code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -944,6 +1062,7 @@ }, { "BriefDescription": "Counts demand code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -953,6 +1072,7 @@ }, { "BriefDescription": "Counts demand code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -962,6 +1082,7 @@ }, { "BriefDescription": "Counts demand code reads that hit in the LLC and the snoops sent to sibling cores return clean response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -971,6 +1092,7 @@ }, { "BriefDescription": "Counts all demand data reads .", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -980,6 +1102,7 @@ }, { "BriefDescription": "Counts all demand data reads that hit in the LLC.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -989,6 +1112,7 @@ }, { "BriefDescription": "Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -998,6 +1122,7 @@ }, { "BriefDescription": "Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1007,6 +1132,7 @@ }, { "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1016,6 +1142,7 @@ }, { "BriefDescription": "Counts demand data reads that hit in the LLC and the snoops sent to sibling cores return clean response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1025,6 +1152,7 @@ }, { "BriefDescription": "Counts all demand rfo's .", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1034,6 +1162,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) that hit in the LLC.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1043,6 +1172,7 @@ }, { "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1052,6 +1182,7 @@ }, { "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1061,6 +1192,7 @@ }, { "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1070,6 +1202,7 @@ }, { "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoops sent to sibling cores return clean response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1079,6 +1212,7 @@ }, { "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_M and SNOOP = HITM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_M.HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1088,6 +1222,7 @@ }, { "BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sent to LLC to keep a line from being evicted out of the core caches.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1097,6 +1232,7 @@ }, { "BriefDescription": "Counts L2 hints sent to LLC to keep a line from being evicted out of the core caches.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.LRU_HINTS", "MSRIndex": "0x1a6,0x1a7", @@ -1106,6 +1242,7 @@ }, { "BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.PORTIO_MMIO_UC", "MSRIndex": "0x1a6,0x1a7", @@ -1115,6 +1252,7 @@ }, { "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ANY_RESPONSE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1124,6 +1262,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that hit in the LLC.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1133,6 +1272,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1142,6 +1282,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1151,6 +1292,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1160,6 +1302,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoops sent to sibling cores return clean response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1169,6 +1312,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) data reads that hit in the LLC.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1178,6 +1322,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1187,6 +1332,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1196,6 +1342,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1205,6 +1352,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops sent to sibling cores return clean response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1214,6 +1362,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the LLC.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1223,6 +1372,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1232,6 +1382,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1241,6 +1392,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1250,6 +1402,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoops sent to sibling cores return clean response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1259,6 +1412,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the LLC.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1268,6 +1422,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1277,6 +1432,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1286,6 +1442,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1295,6 +1452,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoops sent to sibling cores return clean response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1304,6 +1462,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the LLC.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1313,6 +1472,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1322,6 +1482,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1331,6 +1492,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1340,6 +1502,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1349,6 +1512,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the LLC.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1358,6 +1522,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1367,6 +1532,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1376,6 +1542,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1385,6 +1552,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoops sent to sibling cores return clean response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1394,6 +1562,7 @@ }, { "BriefDescription": "REQUEST = PF_LLC_DATA_RD and RESPONSE = ANY_RESPONSE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1403,6 +1572,7 @@ }, { "BriefDescription": "REQUEST = PF_LLC_IFETCH and RESPONSE = ANY_RESPONSE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L_IFETCH.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1412,6 +1582,7 @@ }, { "BriefDescription": "Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1421,6 +1592,7 @@ }, { "BriefDescription": "Counts non-temporal stores.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1430,6 +1602,7 @@ }, { "BriefDescription": "Split locks in SQ.", + "Counter": "0,1,2,3", "EventCode": "0xF4", "EventName": "SQ_MISC.SPLIT_LOCK", "SampleAfterValue": "100003", |