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-rw-r--r--tools/perf/pmu-events/arch/x86/ivybridge/cache.json104
1 files changed, 104 insertions, 0 deletions
diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/cache.json b/tools/perf/pmu-events/arch/x86/ivybridge/cache.json
index 46570b522095..563ec3f71c5a 100644
--- a/tools/perf/pmu-events/arch/x86/ivybridge/cache.json
+++ b/tools/perf/pmu-events/arch/x86/ivybridge/cache.json
@@ -1,6 +1,7 @@
[
{
"BriefDescription": "L1D data line replacements",
+ "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "L1D.REPLACEMENT",
"PublicDescription": "Counts the number of lines brought into the L1 data cache.",
@@ -9,6 +10,7 @@
},
{
"BriefDescription": "Cycles a demand request was blocked due to Fill Buffers unavailability",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.FB_FULL",
@@ -18,6 +20,7 @@
},
{
"BriefDescription": "L1D miss outstanding duration in cycles",
+ "Counter": "2",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING",
"PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.",
@@ -26,6 +29,7 @@
},
{
"BriefDescription": "Cycles with L1D load Misses outstanding.",
+ "Counter": "2",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES",
@@ -35,6 +39,7 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core",
+ "Counter": "2",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
@@ -44,6 +49,7 @@
},
{
"BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L2_L1D_WB_RQSTS.ALL",
"SampleAfterValue": "200003",
@@ -51,6 +57,7 @@
},
{
"BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L2_L1D_WB_RQSTS.HIT_E",
"PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.",
@@ -59,6 +66,7 @@
},
{
"BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L2_L1D_WB_RQSTS.HIT_M",
"PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.",
@@ -67,6 +75,7 @@
},
{
"BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.)",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L2_L1D_WB_RQSTS.MISS",
"PublicDescription": "Not rejected writebacks that missed LLC.",
@@ -75,6 +84,7 @@
},
{
"BriefDescription": "L2 cache lines filling L2",
+ "Counter": "0,1,2,3",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.ALL",
"PublicDescription": "L2 cache lines filling L2.",
@@ -83,6 +93,7 @@
},
{
"BriefDescription": "L2 cache lines in E state filling L2",
+ "Counter": "0,1,2,3",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.E",
"PublicDescription": "L2 cache lines in E state filling L2.",
@@ -91,6 +102,7 @@
},
{
"BriefDescription": "L2 cache lines in I state filling L2",
+ "Counter": "0,1,2,3",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.I",
"PublicDescription": "L2 cache lines in I state filling L2.",
@@ -99,6 +111,7 @@
},
{
"BriefDescription": "L2 cache lines in S state filling L2",
+ "Counter": "0,1,2,3",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.S",
"PublicDescription": "L2 cache lines in S state filling L2.",
@@ -107,6 +120,7 @@
},
{
"BriefDescription": "Clean L2 cache lines evicted by demand",
+ "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.DEMAND_CLEAN",
"PublicDescription": "Clean L2 cache lines evicted by demand.",
@@ -115,6 +129,7 @@
},
{
"BriefDescription": "Dirty L2 cache lines evicted by demand",
+ "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.DEMAND_DIRTY",
"PublicDescription": "Dirty L2 cache lines evicted by demand.",
@@ -123,6 +138,7 @@
},
{
"BriefDescription": "Dirty L2 cache lines filling the L2",
+ "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.DIRTY_ALL",
"PublicDescription": "Dirty L2 cache lines filling the L2.",
@@ -131,6 +147,7 @@
},
{
"BriefDescription": "Clean L2 cache lines evicted by L2 prefetch",
+ "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.PF_CLEAN",
"PublicDescription": "Clean L2 cache lines evicted by the MLC prefetcher.",
@@ -139,6 +156,7 @@
},
{
"BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch",
+ "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.PF_DIRTY",
"PublicDescription": "Dirty L2 cache lines evicted by the MLC prefetcher.",
@@ -147,6 +165,7 @@
},
{
"BriefDescription": "L2 code requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_CODE_RD",
"PublicDescription": "Counts all L2 code requests.",
@@ -155,6 +174,7 @@
},
{
"BriefDescription": "Demand Data Read requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
"PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.",
@@ -163,6 +183,7 @@
},
{
"BriefDescription": "Requests from L2 hardware prefetchers",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_PF",
"PublicDescription": "Counts all L2 HW prefetcher requests.",
@@ -171,6 +192,7 @@
},
{
"BriefDescription": "RFO requests to L2 cache",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_RFO",
"PublicDescription": "Counts all L2 store RFO requests.",
@@ -179,6 +201,7 @@
},
{
"BriefDescription": "L2 cache hits when fetching instructions, code reads.",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_HIT",
"PublicDescription": "Number of instruction fetches that hit the L2 cache.",
@@ -187,6 +210,7 @@
},
{
"BriefDescription": "L2 cache misses when fetching instructions",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_MISS",
"PublicDescription": "Number of instruction fetches that missed the L2 cache.",
@@ -195,6 +219,7 @@
},
{
"BriefDescription": "Demand Data Read requests that hit L2 cache",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
"PublicDescription": "Demand Data Read requests that hit L2 cache.",
@@ -203,6 +228,7 @@
},
{
"BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.PF_HIT",
"PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.",
@@ -211,6 +237,7 @@
},
{
"BriefDescription": "Requests from the L2 hardware prefetchers that miss L2 cache",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.PF_MISS",
"PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.",
@@ -219,6 +246,7 @@
},
{
"BriefDescription": "RFO requests that hit L2 cache",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_HIT",
"PublicDescription": "RFO requests that hit L2 cache.",
@@ -227,6 +255,7 @@
},
{
"BriefDescription": "RFO requests that miss L2 cache",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_MISS",
"PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.",
@@ -235,6 +264,7 @@
},
{
"BriefDescription": "RFOs that access cache lines in any state",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_STORE_LOCK_RQSTS.ALL",
"PublicDescription": "RFOs that access cache lines in any state.",
@@ -243,6 +273,7 @@
},
{
"BriefDescription": "RFOs that hit cache lines in M state",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_STORE_LOCK_RQSTS.HIT_M",
"PublicDescription": "RFOs that hit cache lines in M state.",
@@ -251,6 +282,7 @@
},
{
"BriefDescription": "RFOs that miss cache lines",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_STORE_LOCK_RQSTS.MISS",
"PublicDescription": "RFOs that miss cache lines.",
@@ -259,6 +291,7 @@
},
{
"BriefDescription": "L2 or LLC HW prefetches that access L2 cache",
+ "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANS.ALL_PF",
"PublicDescription": "Any MLC or LLC HW prefetch accessing L2, including rejects.",
@@ -267,6 +300,7 @@
},
{
"BriefDescription": "Transactions accessing L2 pipe",
+ "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANS.ALL_REQUESTS",
"PublicDescription": "Transactions accessing L2 pipe.",
@@ -275,6 +309,7 @@
},
{
"BriefDescription": "L2 cache accesses when fetching instructions",
+ "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANS.CODE_RD",
"PublicDescription": "L2 cache accesses when fetching instructions.",
@@ -283,6 +318,7 @@
},
{
"BriefDescription": "Demand Data Read requests that access L2 cache",
+ "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANS.DEMAND_DATA_RD",
"PublicDescription": "Demand Data Read requests that access L2 cache.",
@@ -291,6 +327,7 @@
},
{
"BriefDescription": "L1D writebacks that access L2 cache",
+ "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANS.L1D_WB",
"PublicDescription": "L1D writebacks that access L2 cache.",
@@ -299,6 +336,7 @@
},
{
"BriefDescription": "L2 fill requests that access L2 cache",
+ "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANS.L2_FILL",
"PublicDescription": "L2 fill requests that access L2 cache.",
@@ -307,6 +345,7 @@
},
{
"BriefDescription": "L2 writebacks that access L2 cache",
+ "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANS.L2_WB",
"PublicDescription": "L2 writebacks that access L2 cache.",
@@ -315,6 +354,7 @@
},
{
"BriefDescription": "RFO requests that access L2 cache",
+ "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANS.RFO",
"PublicDescription": "RFO requests that access L2 cache.",
@@ -323,6 +363,7 @@
},
{
"BriefDescription": "Cycles when L1D is locked",
+ "Counter": "0,1,2,3",
"EventCode": "0x63",
"EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
"PublicDescription": "Cycles in which the L1D is locked.",
@@ -331,6 +372,7 @@
},
{
"BriefDescription": "Core-originated cacheable demand requests missed LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.MISS",
"PublicDescription": "This event counts each cache miss condition for references to the last level cache.",
@@ -339,6 +381,7 @@
},
{
"BriefDescription": "Core-originated cacheable demand requests that refer to LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
"PublicDescription": "This event counts requests originating from the core that reference a cache line in the last level cache.",
@@ -347,6 +390,7 @@
},
{
"BriefDescription": "Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache.",
+ "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT",
"PEBS": "1",
@@ -355,6 +399,7 @@
},
{
"BriefDescription": "Retired load uops which data sources were HitM responses from shared LLC.",
+ "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM",
"PEBS": "1",
@@ -363,6 +408,7 @@
},
{
"BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache.",
+ "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS",
"PEBS": "1",
@@ -371,6 +417,7 @@
},
{
"BriefDescription": "Retired load uops which data sources were hits in LLC without snoops required.",
+ "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE",
"PEBS": "1",
@@ -379,6 +426,7 @@
},
{
"BriefDescription": "Retired load uops which data sources missed LLC but serviced from local dram.",
+ "Counter": "0,1,2,3",
"EventCode": "0xD3",
"EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM",
"PublicDescription": "Retired load uops whose data source was local memory (cross-socket snoop not needed or missed).",
@@ -387,6 +435,7 @@
},
{
"BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.",
+ "Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB",
"PEBS": "1",
@@ -395,6 +444,7 @@
},
{
"BriefDescription": "Retired load uops with L1 cache hits as data sources.",
+ "Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
"PEBS": "1",
@@ -403,6 +453,7 @@
},
{
"BriefDescription": "Retired load uops which data sources following L1 data-cache miss.",
+ "Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
"PEBS": "1",
@@ -411,6 +462,7 @@
},
{
"BriefDescription": "Retired load uops with L2 cache hits as data sources.",
+ "Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
"PEBS": "1",
@@ -419,6 +471,7 @@
},
{
"BriefDescription": "Retired load uops with L2 cache misses as data sources.",
+ "Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
"PEBS": "1",
@@ -427,6 +480,7 @@
},
{
"BriefDescription": "Retired load uops which data sources were data hits in LLC without snoops required.",
+ "Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT",
"PEBS": "1",
@@ -435,6 +489,7 @@
},
{
"BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",
+ "Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.LLC_MISS",
"PEBS": "1",
@@ -443,6 +498,7 @@
},
{
"BriefDescription": "All retired load uops. (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
"PEBS": "1",
@@ -451,6 +507,7 @@
},
{
"BriefDescription": "All retired store uops. (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.ALL_STORES",
"PEBS": "1",
@@ -459,6 +516,7 @@
},
{
"BriefDescription": "Retired load uops with locked access. (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
"PEBS": "1",
@@ -467,6 +525,7 @@
},
{
"BriefDescription": "Retired load uops that split across a cacheline boundary. (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
"PEBS": "1",
@@ -475,6 +534,7 @@
},
{
"BriefDescription": "Retired store uops that split across a cacheline boundary. (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
"PEBS": "1",
@@ -483,6 +543,7 @@
},
{
"BriefDescription": "Retired load uops that miss the STLB. (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS",
"PEBS": "1",
@@ -491,6 +552,7 @@
},
{
"BriefDescription": "Retired store uops that miss the STLB. (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",
"PEBS": "1",
@@ -499,6 +561,7 @@
},
{
"BriefDescription": "Demand and prefetch data reads",
+ "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
"PublicDescription": "Data read requests sent to uncore (demand and prefetch).",
@@ -507,6 +570,7 @@
},
{
"BriefDescription": "Cacheable and noncacheable code read requests",
+ "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
"PublicDescription": "Demand code read requests sent to uncore.",
@@ -515,6 +579,7 @@
},
{
"BriefDescription": "Demand Data Read requests sent to uncore",
+ "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
"PublicDescription": "Demand data read requests sent to uncore.",
@@ -523,6 +588,7 @@
},
{
"BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
+ "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
"PublicDescription": "Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.",
@@ -531,6 +597,7 @@
},
{
"BriefDescription": "Cases when offcore requests buffer cannot take more entries for core",
+ "Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
"PublicDescription": "Cases when offcore requests buffer cannot take more entries for core.",
@@ -539,6 +606,7 @@
},
{
"BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
+ "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
"PublicDescription": "Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
@@ -547,6 +615,7 @@
},
{
"BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
@@ -556,6 +625,7 @@
},
{
"BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD",
@@ -565,6 +635,7 @@
},
{
"BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
@@ -574,6 +645,7 @@
},
{
"BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
@@ -583,6 +655,7 @@
},
{
"BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
+ "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
"PublicDescription": "Offcore outstanding Demand Code Read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
@@ -591,6 +664,7 @@
},
{
"BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
+ "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
"PublicDescription": "Offcore outstanding Demand Data Read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
@@ -599,6 +673,7 @@
},
{
"BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue",
+ "Counter": "0,1,2,3",
"CounterMask": "6",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",
@@ -608,6 +683,7 @@
},
{
"BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",
+ "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
"PublicDescription": "Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles.",
@@ -616,6 +692,7 @@
},
{
"BriefDescription": "Counts all demand & prefetch code reads that hit in the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -625,6 +702,7 @@
},
{
"BriefDescription": "Counts demand & prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
@@ -634,6 +712,7 @@
},
{
"BriefDescription": "Counts all demand & prefetch data reads",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -643,6 +722,7 @@
},
{
"BriefDescription": "Counts all demand & prefetch data reads that hit in the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -652,6 +732,7 @@
},
{
"BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
@@ -661,6 +742,7 @@
},
{
"BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
@@ -670,6 +752,7 @@
},
{
"BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
@@ -679,6 +762,7 @@
},
{
"BriefDescription": "Counts all data/code/rfo references (demand & prefetch)",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -688,6 +772,7 @@
},
{
"BriefDescription": "Counts all demand & prefetch prefetch RFOs",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -697,6 +782,7 @@
},
{
"BriefDescription": "Counts all demand & prefetch RFOs that hit in the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -706,6 +792,7 @@
},
{
"BriefDescription": "Counts demand & prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
@@ -715,6 +802,7 @@
},
{
"BriefDescription": "Counts all writebacks from the core to the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -724,6 +812,7 @@
},
{
"BriefDescription": "Counts all demand code reads",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -733,6 +822,7 @@
},
{
"BriefDescription": "Counts all demand code reads that hit in the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -742,6 +832,7 @@
},
{
"BriefDescription": "Counts demand code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
@@ -751,6 +842,7 @@
},
{
"BriefDescription": "Counts all demand data reads",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -760,6 +852,7 @@
},
{
"BriefDescription": "Counts all demand data reads that hit in the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -769,6 +862,7 @@
},
{
"BriefDescription": "Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
@@ -778,6 +872,7 @@
},
{
"BriefDescription": "Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
@@ -787,6 +882,7 @@
},
{
"BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
@@ -796,6 +892,7 @@
},
{
"BriefDescription": "Counts all demand rfo's",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -805,6 +902,7 @@
},
{
"BriefDescription": "Counts all demand data writes (RFOs) that hit in the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -814,6 +912,7 @@
},
{
"BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
@@ -823,6 +922,7 @@
},
{
"BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
@@ -832,6 +932,7 @@
},
{
"BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sent to LLC to keep a line from being evicted out of the core caches",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -841,6 +942,7 @@
},
{
"BriefDescription": "Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -850,6 +952,7 @@
},
{
"BriefDescription": "Counts non-temporal stores",
+ "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -859,6 +962,7 @@
},
{
"BriefDescription": "Split locks in SQ",
+ "Counter": "0,1,2,3",
"EventCode": "0xF4",
"EventName": "SQ_MISC.SPLIT_LOCK",
"SampleAfterValue": "100003",
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