diff options
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/haswell/cache.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/haswell/cache.json | 94 |
1 files changed, 94 insertions, 0 deletions
diff --git a/tools/perf/pmu-events/arch/x86/haswell/cache.json b/tools/perf/pmu-events/arch/x86/haswell/cache.json index 0831f14b3cc6..29b408d036c2 100644 --- a/tools/perf/pmu-events/arch/x86/haswell/cache.json +++ b/tools/perf/pmu-events/arch/x86/haswell/cache.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "L1D data line replacements", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "L1D.REPLACEMENT", "PublicDescription": "This event counts when new data lines are brought into the L1 Data cache, which cause other lines to be evicted from the cache.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers unavailability.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.FB_FULL", @@ -17,6 +19,7 @@ }, { "BriefDescription": "L1D miss outstanding duration in cycles", + "Counter": "2", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING", "PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Cycles with L1D load Misses outstanding.", + "Counter": "2", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING_CYCLES", @@ -34,6 +38,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.", + "Counter": "2", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", @@ -42,6 +47,7 @@ }, { "BriefDescription": "Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch. HWP are e.", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.REQUEST_FB_FULL", "SampleAfterValue": "2000003", @@ -49,6 +55,7 @@ }, { "BriefDescription": "Not rejected writebacks that hit L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_DEMAND_RQSTS.WB_HIT", "PublicDescription": "Not rejected writebacks that hit L2 cache.", @@ -57,6 +64,7 @@ }, { "BriefDescription": "L2 cache lines filling L2", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.ALL", "PublicDescription": "This event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2 cache when there was an L2 miss.", @@ -65,6 +73,7 @@ }, { "BriefDescription": "L2 cache lines in E state filling L2", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.E", "PublicDescription": "L2 cache lines in E state filling L2.", @@ -73,6 +82,7 @@ }, { "BriefDescription": "L2 cache lines in I state filling L2", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.I", "PublicDescription": "L2 cache lines in I state filling L2.", @@ -81,6 +91,7 @@ }, { "BriefDescription": "L2 cache lines in S state filling L2", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.S", "PublicDescription": "L2 cache lines in S state filling L2.", @@ -89,6 +100,7 @@ }, { "BriefDescription": "Clean L2 cache lines evicted by demand", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_CLEAN", "PublicDescription": "Clean L2 cache lines evicted by demand.", @@ -97,6 +109,7 @@ }, { "BriefDescription": "Dirty L2 cache lines evicted by demand", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_DIRTY", "PublicDescription": "Dirty L2 cache lines evicted by demand.", @@ -105,6 +118,7 @@ }, { "BriefDescription": "L2 code requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_CODE_RD", "PublicDescription": "Counts all L2 code requests.", @@ -113,6 +127,7 @@ }, { "BriefDescription": "Demand Data Read requests", + "Counter": "0,1,2,3", "Errata": "HSD78, HSM80", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", @@ -122,6 +137,7 @@ }, { "BriefDescription": "Demand requests that miss L2 cache", + "Counter": "0,1,2,3", "Errata": "HSD78, HSM80", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_MISS", @@ -131,6 +147,7 @@ }, { "BriefDescription": "Demand requests to L2 cache", + "Counter": "0,1,2,3", "Errata": "HSD78, HSM80", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", @@ -140,6 +157,7 @@ }, { "BriefDescription": "Requests from L2 hardware prefetchers", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_PF", "PublicDescription": "Counts all L2 HW prefetcher requests.", @@ -148,6 +166,7 @@ }, { "BriefDescription": "RFO requests to L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_RFO", "PublicDescription": "Counts all L2 store RFO requests.", @@ -156,6 +175,7 @@ }, { "BriefDescription": "L2 cache hits when fetching instructions, code reads.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.CODE_RD_HIT", "PublicDescription": "Number of instruction fetches that hit the L2 cache.", @@ -164,6 +184,7 @@ }, { "BriefDescription": "L2 cache misses when fetching instructions", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.CODE_RD_MISS", "PublicDescription": "Number of instruction fetches that missed the L2 cache.", @@ -172,6 +193,7 @@ }, { "BriefDescription": "Demand Data Read requests that hit L2 cache", + "Counter": "0,1,2,3", "Errata": "HSD78, HSM80", "EventCode": "0x24", "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", @@ -181,6 +203,7 @@ }, { "BriefDescription": "Demand Data Read miss L2, no rejects", + "Counter": "0,1,2,3", "Errata": "HSD78, HSM80", "EventCode": "0x24", "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", @@ -190,6 +213,7 @@ }, { "BriefDescription": "L2 prefetch requests that hit L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.L2_PF_HIT", "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.", @@ -198,6 +222,7 @@ }, { "BriefDescription": "L2 prefetch requests that miss L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.L2_PF_MISS", "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.", @@ -206,6 +231,7 @@ }, { "BriefDescription": "All requests that miss L2 cache", + "Counter": "0,1,2,3", "Errata": "HSD78, HSM80", "EventCode": "0x24", "EventName": "L2_RQSTS.MISS", @@ -215,6 +241,7 @@ }, { "BriefDescription": "All L2 requests", + "Counter": "0,1,2,3", "Errata": "HSD78, HSM80", "EventCode": "0x24", "EventName": "L2_RQSTS.REFERENCES", @@ -224,6 +251,7 @@ }, { "BriefDescription": "RFO requests that hit L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_HIT", "PublicDescription": "Counts the number of store RFO requests that hit the L2 cache.", @@ -232,6 +260,7 @@ }, { "BriefDescription": "RFO requests that miss L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_MISS", "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.", @@ -240,6 +269,7 @@ }, { "BriefDescription": "L2 or L3 HW prefetches that access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0xf0", "EventName": "L2_TRANS.ALL_PF", "PublicDescription": "Any MLC or L3 HW prefetch accessing L2, including rejects.", @@ -248,6 +278,7 @@ }, { "BriefDescription": "Transactions accessing L2 pipe", + "Counter": "0,1,2,3", "EventCode": "0xf0", "EventName": "L2_TRANS.ALL_REQUESTS", "PublicDescription": "Transactions accessing L2 pipe.", @@ -256,6 +287,7 @@ }, { "BriefDescription": "L2 cache accesses when fetching instructions", + "Counter": "0,1,2,3", "EventCode": "0xf0", "EventName": "L2_TRANS.CODE_RD", "PublicDescription": "L2 cache accesses when fetching instructions.", @@ -264,6 +296,7 @@ }, { "BriefDescription": "Demand Data Read requests that access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0xf0", "EventName": "L2_TRANS.DEMAND_DATA_RD", "PublicDescription": "Demand data read requests that access L2 cache.", @@ -272,6 +305,7 @@ }, { "BriefDescription": "L1D writebacks that access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0xf0", "EventName": "L2_TRANS.L1D_WB", "PublicDescription": "L1D writebacks that access L2 cache.", @@ -280,6 +314,7 @@ }, { "BriefDescription": "L2 fill requests that access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0xf0", "EventName": "L2_TRANS.L2_FILL", "PublicDescription": "L2 fill requests that access L2 cache.", @@ -288,6 +323,7 @@ }, { "BriefDescription": "L2 writebacks that access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0xf0", "EventName": "L2_TRANS.L2_WB", "PublicDescription": "L2 writebacks that access L2 cache.", @@ -296,6 +332,7 @@ }, { "BriefDescription": "RFO requests that access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0xf0", "EventName": "L2_TRANS.RFO", "PublicDescription": "RFO requests that access L2 cache.", @@ -304,6 +341,7 @@ }, { "BriefDescription": "Cycles when L1D is locked", + "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", "PublicDescription": "Cycles in which the L1D is locked.", @@ -312,6 +350,7 @@ }, { "BriefDescription": "Core-originated cacheable demand requests missed L3", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.MISS", "PublicDescription": "This event counts each cache miss condition for references to the last level cache.", @@ -320,6 +359,7 @@ }, { "BriefDescription": "Core-originated cacheable demand requests that refer to L3", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.REFERENCE", "PublicDescription": "This event counts requests originating from the core that reference a cache line in the last level cache.", @@ -328,6 +368,7 @@ }, { "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSD29, HSD25, HSM26, HSM30", "EventCode": "0xD2", @@ -338,6 +379,7 @@ }, { "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSD29, HSD25, HSM26, HSM30", "EventCode": "0xD2", @@ -348,6 +390,7 @@ }, { "BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSD29, HSD25, HSM26, HSM30", "EventCode": "0xD2", @@ -358,6 +401,7 @@ }, { "BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", "EventCode": "0xD2", @@ -368,6 +412,7 @@ }, { "BriefDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSD74, HSD29, HSD25, HSM30", "EventCode": "0xD3", @@ -379,6 +424,7 @@ }, { "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSM30", "EventCode": "0xD1", @@ -389,6 +435,7 @@ }, { "BriefDescription": "Retired load uops with L1 cache hits as data sources.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSD29, HSM30", "EventCode": "0xD1", @@ -399,6 +446,7 @@ }, { "BriefDescription": "Retired load uops misses in L1 cache as data sources.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSM30", "EventCode": "0xD1", @@ -410,6 +458,7 @@ }, { "BriefDescription": "Retired load uops with L2 cache hits as data sources.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSD76, HSD29, HSM30", "EventCode": "0xD1", @@ -420,6 +469,7 @@ }, { "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSD29, HSM30", "EventCode": "0xD1", @@ -431,6 +481,7 @@ }, { "BriefDescription": "Retired load uops which data sources were data hits in L3 without snoops required.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", "EventCode": "0xD1", @@ -442,6 +493,7 @@ }, { "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", "EventCode": "0xD1", @@ -453,6 +505,7 @@ }, { "BriefDescription": "Retired load uops.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSD29, HSM30", "EventCode": "0xD0", @@ -464,6 +517,7 @@ }, { "BriefDescription": "Retired store uops.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSD29, HSM30", "EventCode": "0xD0", @@ -475,6 +529,7 @@ }, { "BriefDescription": "Retired load uops with locked access.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSD76, HSD29, HSM30", "EventCode": "0xD0", @@ -485,6 +540,7 @@ }, { "BriefDescription": "Retired load uops that split across a cacheline boundary.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSD29, HSM30", "EventCode": "0xD0", @@ -495,6 +551,7 @@ }, { "BriefDescription": "Retired store uops that split across a cacheline boundary.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSD29, HSM30", "EventCode": "0xD0", @@ -505,6 +562,7 @@ }, { "BriefDescription": "Retired load uops that miss the STLB.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSD29, HSM30", "EventCode": "0xD0", @@ -515,6 +573,7 @@ }, { "BriefDescription": "Retired store uops that miss the STLB.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSD29, HSM30", "EventCode": "0xD0", @@ -525,6 +584,7 @@ }, { "BriefDescription": "Demand and prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", "PublicDescription": "Data read requests sent to uncore (demand and prefetch).", @@ -533,6 +593,7 @@ }, { "BriefDescription": "Cacheable and noncacheable code read requests", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", "PublicDescription": "Demand code read requests sent to uncore.", @@ -541,6 +602,7 @@ }, { "BriefDescription": "Demand Data Read requests sent to uncore", + "Counter": "0,1,2,3", "Errata": "HSD78, HSM80", "EventCode": "0xb0", "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", @@ -550,6 +612,7 @@ }, { "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", "PublicDescription": "Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.", @@ -558,6 +621,7 @@ }, { "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.", + "Counter": "0,1,2,3", "EventCode": "0xb2", "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", "SampleAfterValue": "2000003", @@ -565,6 +629,7 @@ }, { "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", "Errata": "HSD62, HSD61, HSM63", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", @@ -574,6 +639,7 @@ }, { "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.", + "Counter": "0,1,2,3", "CounterMask": "1", "Errata": "HSD62, HSD61, HSM63", "EventCode": "0x60", @@ -583,6 +649,7 @@ }, { "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.", + "Counter": "0,1,2,3", "CounterMask": "1", "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80", "EventCode": "0x60", @@ -592,6 +659,7 @@ }, { "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.", + "Counter": "0,1,2,3", "CounterMask": "1", "Errata": "HSD62, HSD61, HSM63", "EventCode": "0x60", @@ -601,6 +669,7 @@ }, { "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle", + "Counter": "0,1,2,3", "Errata": "HSD62, HSD61, HSM63", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", @@ -610,6 +679,7 @@ }, { "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.", + "Counter": "0,1,2,3", "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", @@ -619,6 +689,7 @@ }, { "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.", + "Counter": "0,1,2,3", "CounterMask": "6", "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80", "EventCode": "0x60", @@ -628,6 +699,7 @@ }, { "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", "Errata": "HSD62, HSD61, HSM63", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", @@ -637,6 +709,7 @@ }, { "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE", "SampleAfterValue": "100003", @@ -644,6 +717,7 @@ }, { "BriefDescription": "Counts all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -653,6 +727,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -662,6 +737,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -671,6 +747,7 @@ }, { "BriefDescription": "hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -680,6 +757,7 @@ }, { "BriefDescription": "hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -689,6 +767,7 @@ }, { "BriefDescription": "Counts all requests hit in the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.L3_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -698,6 +777,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -707,6 +787,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -716,6 +797,7 @@ }, { "BriefDescription": "Counts all demand code reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -725,6 +807,7 @@ }, { "BriefDescription": "Counts all demand code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -734,6 +817,7 @@ }, { "BriefDescription": "Counts demand data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -743,6 +827,7 @@ }, { "BriefDescription": "Counts demand data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -752,6 +837,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -761,6 +847,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -770,6 +857,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads hit in the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -779,6 +867,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data reads hit in the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -788,6 +877,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs hit in the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -797,6 +887,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads hit in the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -806,6 +897,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads hit in the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -815,6 +907,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs hit in the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -824,6 +917,7 @@ }, { "BriefDescription": "Split locks in SQ", + "Counter": "0,1,2,3", "EventCode": "0xf4", "EventName": "SQ_MISC.SPLIT_LOCK", "SampleAfterValue": "100003", |