diff options
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/bonnell/frontend.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/bonnell/frontend.json | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/tools/perf/pmu-events/arch/x86/bonnell/frontend.json b/tools/perf/pmu-events/arch/x86/bonnell/frontend.json index 42284c02c11d..7657fd6d3a11 100644 --- a/tools/perf/pmu-events/arch/x86/bonnell/frontend.json +++ b/tools/perf/pmu-events/arch/x86/bonnell/frontend.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "BACLEARS asserted.", + "Counter": "0,1", "EventCode": "0xE6", "EventName": "BACLEARS.ANY", "SampleAfterValue": "2000000", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Cycles during which instruction fetches are stalled.", + "Counter": "0,1", "EventCode": "0x86", "EventName": "CYCLES_ICACHE_MEM_STALLED.ICACHE_MEM_STALLED", "SampleAfterValue": "2000000", @@ -15,6 +17,7 @@ }, { "BriefDescription": "Decode stall due to IQ full", + "Counter": "0,1", "EventCode": "0x87", "EventName": "DECODE_STALL.IQ_FULL", "SampleAfterValue": "2000000", @@ -22,6 +25,7 @@ }, { "BriefDescription": "Decode stall due to PFB empty", + "Counter": "0,1", "EventCode": "0x87", "EventName": "DECODE_STALL.PFB_EMPTY", "SampleAfterValue": "2000000", @@ -29,6 +33,7 @@ }, { "BriefDescription": "Instruction fetches.", + "Counter": "0,1", "EventCode": "0x80", "EventName": "ICACHE.ACCESSES", "SampleAfterValue": "200000", @@ -36,6 +41,7 @@ }, { "BriefDescription": "Icache hit", + "Counter": "0,1", "EventCode": "0x80", "EventName": "ICACHE.HIT", "SampleAfterValue": "200000", @@ -43,6 +49,7 @@ }, { "BriefDescription": "Icache miss", + "Counter": "0,1", "EventCode": "0x80", "EventName": "ICACHE.MISSES", "SampleAfterValue": "200000", @@ -50,6 +57,7 @@ }, { "BriefDescription": "All Instructions decoded", + "Counter": "0,1", "EventCode": "0xAA", "EventName": "MACRO_INSTS.ALL_DECODED", "SampleAfterValue": "2000000", @@ -57,6 +65,7 @@ }, { "BriefDescription": "CISC macro instructions decoded", + "Counter": "0,1", "EventCode": "0xAA", "EventName": "MACRO_INSTS.CISC_DECODED", "SampleAfterValue": "2000000", @@ -64,6 +73,7 @@ }, { "BriefDescription": "Non-CISC macro instructions decoded", + "Counter": "0,1", "EventCode": "0xAA", "EventName": "MACRO_INSTS.NON_CISC_DECODED", "SampleAfterValue": "2000000", @@ -71,6 +81,7 @@ }, { "BriefDescription": "This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ.", + "Counter": "0,1", "CounterMask": "1", "EventCode": "0xA9", "EventName": "UOPS.MS_CYCLES", |