diff options
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/bonnell/cache.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/bonnell/cache.json | 93 |
1 files changed, 93 insertions, 0 deletions
diff --git a/tools/perf/pmu-events/arch/x86/bonnell/cache.json b/tools/perf/pmu-events/arch/x86/bonnell/cache.json index 1ca95a70d48a..86582bb8aa39 100644 --- a/tools/perf/pmu-events/arch/x86/bonnell/cache.json +++ b/tools/perf/pmu-events/arch/x86/bonnell/cache.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "L1 Data Cacheable reads and writes", + "Counter": "0,1", "EventCode": "0x40", "EventName": "L1D_CACHE.ALL_CACHE_REF", "SampleAfterValue": "2000000", @@ -8,6 +9,7 @@ }, { "BriefDescription": "L1 Data reads and writes", + "Counter": "0,1", "EventCode": "0x40", "EventName": "L1D_CACHE.ALL_REF", "SampleAfterValue": "2000000", @@ -15,6 +17,7 @@ }, { "BriefDescription": "Modified cache lines evicted from the L1 data cache", + "Counter": "0,1", "EventCode": "0x40", "EventName": "L1D_CACHE.EVICT", "SampleAfterValue": "200000", @@ -22,6 +25,7 @@ }, { "BriefDescription": "L1 Cacheable Data Reads", + "Counter": "0,1", "EventCode": "0x40", "EventName": "L1D_CACHE.LD", "SampleAfterValue": "2000000", @@ -29,6 +33,7 @@ }, { "BriefDescription": "L1 Data line replacements", + "Counter": "0,1", "EventCode": "0x40", "EventName": "L1D_CACHE.REPL", "SampleAfterValue": "200000", @@ -36,6 +41,7 @@ }, { "BriefDescription": "Modified cache lines allocated in the L1 data cache", + "Counter": "0,1", "EventCode": "0x40", "EventName": "L1D_CACHE.REPLM", "SampleAfterValue": "200000", @@ -43,6 +49,7 @@ }, { "BriefDescription": "L1 Cacheable Data Writes", + "Counter": "0,1", "EventCode": "0x40", "EventName": "L1D_CACHE.ST", "SampleAfterValue": "2000000", @@ -50,6 +57,7 @@ }, { "BriefDescription": "Cycles L2 address bus is in use.", + "Counter": "0,1", "EventCode": "0x21", "EventName": "L2_ADS.SELF", "SampleAfterValue": "200000", @@ -57,6 +65,7 @@ }, { "BriefDescription": "All data requests from the L1 data cache", + "Counter": "0,1", "EventCode": "0x2C", "EventName": "L2_DATA_RQSTS.SELF.E_STATE", "SampleAfterValue": "200000", @@ -64,6 +73,7 @@ }, { "BriefDescription": "All data requests from the L1 data cache", + "Counter": "0,1", "EventCode": "0x2C", "EventName": "L2_DATA_RQSTS.SELF.I_STATE", "SampleAfterValue": "200000", @@ -71,6 +81,7 @@ }, { "BriefDescription": "All data requests from the L1 data cache", + "Counter": "0,1", "EventCode": "0x2C", "EventName": "L2_DATA_RQSTS.SELF.MESI", "SampleAfterValue": "200000", @@ -78,6 +89,7 @@ }, { "BriefDescription": "All data requests from the L1 data cache", + "Counter": "0,1", "EventCode": "0x2C", "EventName": "L2_DATA_RQSTS.SELF.M_STATE", "SampleAfterValue": "200000", @@ -85,6 +97,7 @@ }, { "BriefDescription": "All data requests from the L1 data cache", + "Counter": "0,1", "EventCode": "0x2C", "EventName": "L2_DATA_RQSTS.SELF.S_STATE", "SampleAfterValue": "200000", @@ -92,6 +105,7 @@ }, { "BriefDescription": "Cycles the L2 cache data bus is busy.", + "Counter": "0,1", "EventCode": "0x22", "EventName": "L2_DBUS_BUSY.SELF", "SampleAfterValue": "200000", @@ -99,6 +113,7 @@ }, { "BriefDescription": "Cycles the L2 transfers data to the core.", + "Counter": "0,1", "EventCode": "0x23", "EventName": "L2_DBUS_BUSY_RD.SELF", "SampleAfterValue": "200000", @@ -106,6 +121,7 @@ }, { "BriefDescription": "L2 cacheable instruction fetch requests", + "Counter": "0,1", "EventCode": "0x28", "EventName": "L2_IFETCH.SELF.E_STATE", "SampleAfterValue": "200000", @@ -113,6 +129,7 @@ }, { "BriefDescription": "L2 cacheable instruction fetch requests", + "Counter": "0,1", "EventCode": "0x28", "EventName": "L2_IFETCH.SELF.I_STATE", "SampleAfterValue": "200000", @@ -120,6 +137,7 @@ }, { "BriefDescription": "L2 cacheable instruction fetch requests", + "Counter": "0,1", "EventCode": "0x28", "EventName": "L2_IFETCH.SELF.MESI", "SampleAfterValue": "200000", @@ -127,6 +145,7 @@ }, { "BriefDescription": "L2 cacheable instruction fetch requests", + "Counter": "0,1", "EventCode": "0x28", "EventName": "L2_IFETCH.SELF.M_STATE", "SampleAfterValue": "200000", @@ -134,6 +153,7 @@ }, { "BriefDescription": "L2 cacheable instruction fetch requests", + "Counter": "0,1", "EventCode": "0x28", "EventName": "L2_IFETCH.SELF.S_STATE", "SampleAfterValue": "200000", @@ -141,6 +161,7 @@ }, { "BriefDescription": "L2 cache reads", + "Counter": "0,1", "EventCode": "0x29", "EventName": "L2_LD.SELF.ANY.E_STATE", "SampleAfterValue": "200000", @@ -148,6 +169,7 @@ }, { "BriefDescription": "L2 cache reads", + "Counter": "0,1", "EventCode": "0x29", "EventName": "L2_LD.SELF.ANY.I_STATE", "SampleAfterValue": "200000", @@ -155,6 +177,7 @@ }, { "BriefDescription": "L2 cache reads", + "Counter": "0,1", "EventCode": "0x29", "EventName": "L2_LD.SELF.ANY.MESI", "SampleAfterValue": "200000", @@ -162,6 +185,7 @@ }, { "BriefDescription": "L2 cache reads", + "Counter": "0,1", "EventCode": "0x29", "EventName": "L2_LD.SELF.ANY.M_STATE", "SampleAfterValue": "200000", @@ -169,6 +193,7 @@ }, { "BriefDescription": "L2 cache reads", + "Counter": "0,1", "EventCode": "0x29", "EventName": "L2_LD.SELF.ANY.S_STATE", "SampleAfterValue": "200000", @@ -176,6 +201,7 @@ }, { "BriefDescription": "L2 cache reads", + "Counter": "0,1", "EventCode": "0x29", "EventName": "L2_LD.SELF.DEMAND.E_STATE", "SampleAfterValue": "200000", @@ -183,6 +209,7 @@ }, { "BriefDescription": "L2 cache reads", + "Counter": "0,1", "EventCode": "0x29", "EventName": "L2_LD.SELF.DEMAND.I_STATE", "SampleAfterValue": "200000", @@ -190,6 +217,7 @@ }, { "BriefDescription": "L2 cache reads", + "Counter": "0,1", "EventCode": "0x29", "EventName": "L2_LD.SELF.DEMAND.MESI", "SampleAfterValue": "200000", @@ -197,6 +225,7 @@ }, { "BriefDescription": "L2 cache reads", + "Counter": "0,1", "EventCode": "0x29", "EventName": "L2_LD.SELF.DEMAND.M_STATE", "SampleAfterValue": "200000", @@ -204,6 +233,7 @@ }, { "BriefDescription": "L2 cache reads", + "Counter": "0,1", "EventCode": "0x29", "EventName": "L2_LD.SELF.DEMAND.S_STATE", "SampleAfterValue": "200000", @@ -211,6 +241,7 @@ }, { "BriefDescription": "L2 cache reads", + "Counter": "0,1", "EventCode": "0x29", "EventName": "L2_LD.SELF.PREFETCH.E_STATE", "SampleAfterValue": "200000", @@ -218,6 +249,7 @@ }, { "BriefDescription": "L2 cache reads", + "Counter": "0,1", "EventCode": "0x29", "EventName": "L2_LD.SELF.PREFETCH.I_STATE", "SampleAfterValue": "200000", @@ -225,6 +257,7 @@ }, { "BriefDescription": "L2 cache reads", + "Counter": "0,1", "EventCode": "0x29", "EventName": "L2_LD.SELF.PREFETCH.MESI", "SampleAfterValue": "200000", @@ -232,6 +265,7 @@ }, { "BriefDescription": "L2 cache reads", + "Counter": "0,1", "EventCode": "0x29", "EventName": "L2_LD.SELF.PREFETCH.M_STATE", "SampleAfterValue": "200000", @@ -239,6 +273,7 @@ }, { "BriefDescription": "L2 cache reads", + "Counter": "0,1", "EventCode": "0x29", "EventName": "L2_LD.SELF.PREFETCH.S_STATE", "SampleAfterValue": "200000", @@ -246,6 +281,7 @@ }, { "BriefDescription": "All read requests from L1 instruction and data caches", + "Counter": "0,1", "EventCode": "0x2D", "EventName": "L2_LD_IFETCH.SELF.E_STATE", "SampleAfterValue": "200000", @@ -253,6 +289,7 @@ }, { "BriefDescription": "All read requests from L1 instruction and data caches", + "Counter": "0,1", "EventCode": "0x2D", "EventName": "L2_LD_IFETCH.SELF.I_STATE", "SampleAfterValue": "200000", @@ -260,6 +297,7 @@ }, { "BriefDescription": "All read requests from L1 instruction and data caches", + "Counter": "0,1", "EventCode": "0x2D", "EventName": "L2_LD_IFETCH.SELF.MESI", "SampleAfterValue": "200000", @@ -267,6 +305,7 @@ }, { "BriefDescription": "All read requests from L1 instruction and data caches", + "Counter": "0,1", "EventCode": "0x2D", "EventName": "L2_LD_IFETCH.SELF.M_STATE", "SampleAfterValue": "200000", @@ -274,6 +313,7 @@ }, { "BriefDescription": "All read requests from L1 instruction and data caches", + "Counter": "0,1", "EventCode": "0x2D", "EventName": "L2_LD_IFETCH.SELF.S_STATE", "SampleAfterValue": "200000", @@ -281,6 +321,7 @@ }, { "BriefDescription": "L2 cache misses.", + "Counter": "0,1", "EventCode": "0x24", "EventName": "L2_LINES_IN.SELF.ANY", "SampleAfterValue": "200000", @@ -288,6 +329,7 @@ }, { "BriefDescription": "L2 cache misses.", + "Counter": "0,1", "EventCode": "0x24", "EventName": "L2_LINES_IN.SELF.DEMAND", "SampleAfterValue": "200000", @@ -295,6 +337,7 @@ }, { "BriefDescription": "L2 cache misses.", + "Counter": "0,1", "EventCode": "0x24", "EventName": "L2_LINES_IN.SELF.PREFETCH", "SampleAfterValue": "200000", @@ -302,6 +345,7 @@ }, { "BriefDescription": "L2 cache lines evicted.", + "Counter": "0,1", "EventCode": "0x26", "EventName": "L2_LINES_OUT.SELF.ANY", "SampleAfterValue": "200000", @@ -309,6 +353,7 @@ }, { "BriefDescription": "L2 cache lines evicted.", + "Counter": "0,1", "EventCode": "0x26", "EventName": "L2_LINES_OUT.SELF.DEMAND", "SampleAfterValue": "200000", @@ -316,6 +361,7 @@ }, { "BriefDescription": "L2 cache lines evicted.", + "Counter": "0,1", "EventCode": "0x26", "EventName": "L2_LINES_OUT.SELF.PREFETCH", "SampleAfterValue": "200000", @@ -323,6 +369,7 @@ }, { "BriefDescription": "L2 locked accesses", + "Counter": "0,1", "EventCode": "0x2B", "EventName": "L2_LOCK.SELF.E_STATE", "SampleAfterValue": "200000", @@ -330,6 +377,7 @@ }, { "BriefDescription": "L2 locked accesses", + "Counter": "0,1", "EventCode": "0x2B", "EventName": "L2_LOCK.SELF.I_STATE", "SampleAfterValue": "200000", @@ -337,6 +385,7 @@ }, { "BriefDescription": "L2 locked accesses", + "Counter": "0,1", "EventCode": "0x2B", "EventName": "L2_LOCK.SELF.MESI", "SampleAfterValue": "200000", @@ -344,6 +393,7 @@ }, { "BriefDescription": "L2 locked accesses", + "Counter": "0,1", "EventCode": "0x2B", "EventName": "L2_LOCK.SELF.M_STATE", "SampleAfterValue": "200000", @@ -351,6 +401,7 @@ }, { "BriefDescription": "L2 locked accesses", + "Counter": "0,1", "EventCode": "0x2B", "EventName": "L2_LOCK.SELF.S_STATE", "SampleAfterValue": "200000", @@ -358,6 +409,7 @@ }, { "BriefDescription": "L2 cache line modifications.", + "Counter": "0,1", "EventCode": "0x25", "EventName": "L2_M_LINES_IN.SELF", "SampleAfterValue": "200000", @@ -365,6 +417,7 @@ }, { "BriefDescription": "Modified lines evicted from the L2 cache", + "Counter": "0,1", "EventCode": "0x27", "EventName": "L2_M_LINES_OUT.SELF.ANY", "SampleAfterValue": "200000", @@ -372,6 +425,7 @@ }, { "BriefDescription": "Modified lines evicted from the L2 cache", + "Counter": "0,1", "EventCode": "0x27", "EventName": "L2_M_LINES_OUT.SELF.DEMAND", "SampleAfterValue": "200000", @@ -379,6 +433,7 @@ }, { "BriefDescription": "Modified lines evicted from the L2 cache", + "Counter": "0,1", "EventCode": "0x27", "EventName": "L2_M_LINES_OUT.SELF.PREFETCH", "SampleAfterValue": "200000", @@ -386,6 +441,7 @@ }, { "BriefDescription": "Cycles no L2 cache requests are pending", + "Counter": "0,1", "EventCode": "0x32", "EventName": "L2_NO_REQ.SELF", "SampleAfterValue": "200000", @@ -393,6 +449,7 @@ }, { "BriefDescription": "Rejected L2 cache requests", + "Counter": "0,1", "EventCode": "0x30", "EventName": "L2_REJECT_BUSQ.SELF.ANY.E_STATE", "SampleAfterValue": "200000", @@ -400,6 +457,7 @@ }, { "BriefDescription": "Rejected L2 cache requests", + "Counter": "0,1", "EventCode": "0x30", "EventName": "L2_REJECT_BUSQ.SELF.ANY.I_STATE", "SampleAfterValue": "200000", @@ -407,6 +465,7 @@ }, { "BriefDescription": "Rejected L2 cache requests", + "Counter": "0,1", "EventCode": "0x30", "EventName": "L2_REJECT_BUSQ.SELF.ANY.MESI", "SampleAfterValue": "200000", @@ -414,6 +473,7 @@ }, { "BriefDescription": "Rejected L2 cache requests", + "Counter": "0,1", "EventCode": "0x30", "EventName": "L2_REJECT_BUSQ.SELF.ANY.M_STATE", "SampleAfterValue": "200000", @@ -421,6 +481,7 @@ }, { "BriefDescription": "Rejected L2 cache requests", + "Counter": "0,1", "EventCode": "0x30", "EventName": "L2_REJECT_BUSQ.SELF.ANY.S_STATE", "SampleAfterValue": "200000", @@ -428,6 +489,7 @@ }, { "BriefDescription": "Rejected L2 cache requests", + "Counter": "0,1", "EventCode": "0x30", "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.E_STATE", "SampleAfterValue": "200000", @@ -435,6 +497,7 @@ }, { "BriefDescription": "Rejected L2 cache requests", + "Counter": "0,1", "EventCode": "0x30", "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.I_STATE", "SampleAfterValue": "200000", @@ -442,6 +505,7 @@ }, { "BriefDescription": "Rejected L2 cache requests", + "Counter": "0,1", "EventCode": "0x30", "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.MESI", "SampleAfterValue": "200000", @@ -449,6 +513,7 @@ }, { "BriefDescription": "Rejected L2 cache requests", + "Counter": "0,1", "EventCode": "0x30", "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.M_STATE", "SampleAfterValue": "200000", @@ -456,6 +521,7 @@ }, { "BriefDescription": "Rejected L2 cache requests", + "Counter": "0,1", "EventCode": "0x30", "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.S_STATE", "SampleAfterValue": "200000", @@ -463,6 +529,7 @@ }, { "BriefDescription": "Rejected L2 cache requests", + "Counter": "0,1", "EventCode": "0x30", "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.E_STATE", "SampleAfterValue": "200000", @@ -470,6 +537,7 @@ }, { "BriefDescription": "Rejected L2 cache requests", + "Counter": "0,1", "EventCode": "0x30", "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.I_STATE", "SampleAfterValue": "200000", @@ -477,6 +545,7 @@ }, { "BriefDescription": "Rejected L2 cache requests", + "Counter": "0,1", "EventCode": "0x30", "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.MESI", "SampleAfterValue": "200000", @@ -484,6 +553,7 @@ }, { "BriefDescription": "Rejected L2 cache requests", + "Counter": "0,1", "EventCode": "0x30", "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.M_STATE", "SampleAfterValue": "200000", @@ -491,6 +561,7 @@ }, { "BriefDescription": "Rejected L2 cache requests", + "Counter": "0,1", "EventCode": "0x30", "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.S_STATE", "SampleAfterValue": "200000", @@ -498,6 +569,7 @@ }, { "BriefDescription": "L2 cache requests", + "Counter": "0,1", "EventCode": "0x2E", "EventName": "L2_RQSTS.SELF.ANY.E_STATE", "SampleAfterValue": "200000", @@ -505,6 +577,7 @@ }, { "BriefDescription": "L2 cache requests", + "Counter": "0,1", "EventCode": "0x2E", "EventName": "L2_RQSTS.SELF.ANY.I_STATE", "SampleAfterValue": "200000", @@ -512,6 +585,7 @@ }, { "BriefDescription": "L2 cache requests", + "Counter": "0,1", "EventCode": "0x2E", "EventName": "L2_RQSTS.SELF.ANY.MESI", "SampleAfterValue": "200000", @@ -519,6 +593,7 @@ }, { "BriefDescription": "L2 cache requests", + "Counter": "0,1", "EventCode": "0x2E", "EventName": "L2_RQSTS.SELF.ANY.M_STATE", "SampleAfterValue": "200000", @@ -526,6 +601,7 @@ }, { "BriefDescription": "L2 cache requests", + "Counter": "0,1", "EventCode": "0x2E", "EventName": "L2_RQSTS.SELF.ANY.S_STATE", "SampleAfterValue": "200000", @@ -533,6 +609,7 @@ }, { "BriefDescription": "L2 cache requests", + "Counter": "0,1", "EventCode": "0x2E", "EventName": "L2_RQSTS.SELF.DEMAND.E_STATE", "SampleAfterValue": "200000", @@ -540,6 +617,7 @@ }, { "BriefDescription": "L2 cache demand requests from this core that missed the L2", + "Counter": "0,1", "EventCode": "0x2E", "EventName": "L2_RQSTS.SELF.DEMAND.I_STATE", "SampleAfterValue": "200000", @@ -547,6 +625,7 @@ }, { "BriefDescription": "L2 cache demand requests from this core", + "Counter": "0,1", "EventCode": "0x2E", "EventName": "L2_RQSTS.SELF.DEMAND.MESI", "SampleAfterValue": "200000", @@ -554,6 +633,7 @@ }, { "BriefDescription": "L2 cache requests", + "Counter": "0,1", "EventCode": "0x2E", "EventName": "L2_RQSTS.SELF.DEMAND.M_STATE", "SampleAfterValue": "200000", @@ -561,6 +641,7 @@ }, { "BriefDescription": "L2 cache requests", + "Counter": "0,1", "EventCode": "0x2E", "EventName": "L2_RQSTS.SELF.DEMAND.S_STATE", "SampleAfterValue": "200000", @@ -568,6 +649,7 @@ }, { "BriefDescription": "L2 cache requests", + "Counter": "0,1", "EventCode": "0x2E", "EventName": "L2_RQSTS.SELF.PREFETCH.E_STATE", "SampleAfterValue": "200000", @@ -575,6 +657,7 @@ }, { "BriefDescription": "L2 cache requests", + "Counter": "0,1", "EventCode": "0x2E", "EventName": "L2_RQSTS.SELF.PREFETCH.I_STATE", "SampleAfterValue": "200000", @@ -582,6 +665,7 @@ }, { "BriefDescription": "L2 cache requests", + "Counter": "0,1", "EventCode": "0x2E", "EventName": "L2_RQSTS.SELF.PREFETCH.MESI", "SampleAfterValue": "200000", @@ -589,6 +673,7 @@ }, { "BriefDescription": "L2 cache requests", + "Counter": "0,1", "EventCode": "0x2E", "EventName": "L2_RQSTS.SELF.PREFETCH.M_STATE", "SampleAfterValue": "200000", @@ -596,6 +681,7 @@ }, { "BriefDescription": "L2 cache requests", + "Counter": "0,1", "EventCode": "0x2E", "EventName": "L2_RQSTS.SELF.PREFETCH.S_STATE", "SampleAfterValue": "200000", @@ -603,6 +689,7 @@ }, { "BriefDescription": "L2 store requests", + "Counter": "0,1", "EventCode": "0x2A", "EventName": "L2_ST.SELF.E_STATE", "SampleAfterValue": "200000", @@ -610,6 +697,7 @@ }, { "BriefDescription": "L2 store requests", + "Counter": "0,1", "EventCode": "0x2A", "EventName": "L2_ST.SELF.I_STATE", "SampleAfterValue": "200000", @@ -617,6 +705,7 @@ }, { "BriefDescription": "L2 store requests", + "Counter": "0,1", "EventCode": "0x2A", "EventName": "L2_ST.SELF.MESI", "SampleAfterValue": "200000", @@ -624,6 +713,7 @@ }, { "BriefDescription": "L2 store requests", + "Counter": "0,1", "EventCode": "0x2A", "EventName": "L2_ST.SELF.M_STATE", "SampleAfterValue": "200000", @@ -631,6 +721,7 @@ }, { "BriefDescription": "L2 store requests", + "Counter": "0,1", "EventCode": "0x2A", "EventName": "L2_ST.SELF.S_STATE", "SampleAfterValue": "200000", @@ -638,6 +729,7 @@ }, { "BriefDescription": "Retired loads that hit the L2 cache (precise event).", + "Counter": "0,1", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.L2_HIT", "SampleAfterValue": "200000", @@ -645,6 +737,7 @@ }, { "BriefDescription": "Retired loads that miss the L2 cache", + "Counter": "0,1", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.L2_MISS", "SampleAfterValue": "10000", |