diff options
Diffstat (limited to 'sound/soc/dwc/designware_i2s.c')
| -rw-r--r-- | sound/soc/dwc/designware_i2s.c | 14 | 
1 files changed, 10 insertions, 4 deletions
diff --git a/sound/soc/dwc/designware_i2s.c b/sound/soc/dwc/designware_i2s.c index bff258d7bcea..0db69b7e9617 100644 --- a/sound/soc/dwc/designware_i2s.c +++ b/sound/soc/dwc/designware_i2s.c @@ -100,6 +100,7 @@ struct dw_i2s_dev {  	struct device *dev;  	u32 ccr;  	u32 xfer_resolution; +	u32 fifo_th;  	/* data related to DMA transfers b/w i2s and DMAC */  	union dw_i2s_snd_dma_data play_dma_data; @@ -147,17 +148,18 @@ static inline void i2s_clear_irqs(struct dw_i2s_dev *dev, u32 stream)  static void i2s_start(struct dw_i2s_dev *dev,  		      struct snd_pcm_substream *substream)  { +	struct i2s_clk_config_data *config = &dev->config;  	u32 i, irq;  	i2s_write_reg(dev->i2s_base, IER, 1);  	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { -		for (i = 0; i < 4; i++) { +		for (i = 0; i < (config->chan_nr / 2); i++) {  			irq = i2s_read_reg(dev->i2s_base, IMR(i));  			i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x30);  		}  		i2s_write_reg(dev->i2s_base, ITER, 1);  	} else { -		for (i = 0; i < 4; i++) { +		for (i = 0; i < (config->chan_nr / 2); i++) {  			irq = i2s_read_reg(dev->i2s_base, IMR(i));  			i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x03);  		} @@ -231,14 +233,16 @@ static void dw_i2s_config(struct dw_i2s_dev *dev, int stream)  		if (stream == SNDRV_PCM_STREAM_PLAYBACK) {  			i2s_write_reg(dev->i2s_base, TCR(ch_reg),  				      dev->xfer_resolution); -			i2s_write_reg(dev->i2s_base, TFCR(ch_reg), 0x02); +			i2s_write_reg(dev->i2s_base, TFCR(ch_reg), +				      dev->fifo_th - 1);  			irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg));  			i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x30);  			i2s_write_reg(dev->i2s_base, TER(ch_reg), 1);  		} else {  			i2s_write_reg(dev->i2s_base, RCR(ch_reg),  				      dev->xfer_resolution); -			i2s_write_reg(dev->i2s_base, RFCR(ch_reg), 0x07); +			i2s_write_reg(dev->i2s_base, RFCR(ch_reg), +				      dev->fifo_th - 1);  			irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg));  			i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x03);  			i2s_write_reg(dev->i2s_base, RER(ch_reg), 1); @@ -498,6 +502,7 @@ static int dw_configure_dai(struct dw_i2s_dev *dev,  	 */  	u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1);  	u32 comp2 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp2); +	u32 fifo_depth = 1 << (1 + COMP1_FIFO_DEPTH_GLOBAL(comp1));  	u32 idx;  	if (dev->capability & DWC_I2S_RECORD && @@ -536,6 +541,7 @@ static int dw_configure_dai(struct dw_i2s_dev *dev,  		dev->capability |= DW_I2S_SLAVE;  	} +	dev->fifo_th = fifo_depth / 2;  	return 0;  }  |