diff options
Diffstat (limited to 'include')
130 files changed, 3329 insertions, 675 deletions
diff --git a/include/acpi/acpi_bus.h b/include/acpi/acpi_bus.h index e44be31115a6..0584e9f6e339 100644 --- a/include/acpi/acpi_bus.h +++ b/include/acpi/acpi_bus.h @@ -534,6 +534,7 @@ int acpi_bus_update_power(acpi_handle handle, int *state_p); int acpi_device_update_power(struct acpi_device *device, int *state_p); bool acpi_bus_power_manageable(acpi_handle handle); void acpi_dev_power_up_children_with_adr(struct acpi_device *adev); +u8 acpi_dev_power_state_for_wake(struct acpi_device *adev); int acpi_device_power_add_dependent(struct acpi_device *adev, struct device *dev); void acpi_device_power_remove_dependent(struct acpi_device *adev, diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h index cdedccccc4f3..81b9e794424d 100644 --- a/include/acpi/actbl1.h +++ b/include/acpi/actbl1.h @@ -804,7 +804,7 @@ struct acpi_dmar_pci_path { struct acpi_dmar_hardware_unit { struct acpi_dmar_header header; u8 flags; - u8 reserved; + u8 size; /* Size of the register set */ u16 segment; u64 address; /* Register Base Address */ }; diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/qcom,ids.h index f7aef3f310d7..aa95439708dc 100644 --- a/include/dt-bindings/arm/qcom,ids.h +++ b/include/dt-bindings/arm/qcom,ids.h @@ -11,40 +11,70 @@ * The MSM chipset and hardware revision used by Qualcomm bootloaders, DTS for * older chipsets (qcom,msm-id) and in socinfo driver: */ +#define QCOM_ID_MSM8260 70 +#define QCOM_ID_MSM8660 71 +#define QCOM_ID_APQ8060 86 #define QCOM_ID_MSM8960 87 #define QCOM_ID_APQ8064 109 +#define QCOM_ID_MSM8930 116 +#define QCOM_ID_MSM8630 117 +#define QCOM_ID_MSM8230 118 +#define QCOM_ID_APQ8030 119 +#define QCOM_ID_MSM8627 120 +#define QCOM_ID_MSM8227 121 #define QCOM_ID_MSM8660A 122 #define QCOM_ID_MSM8260A 123 #define QCOM_ID_APQ8060A 124 #define QCOM_ID_MSM8974 126 +#define QCOM_ID_MSM8225 127 +#define QCOM_ID_MSM8625 129 #define QCOM_ID_MPQ8064 130 #define QCOM_ID_MSM8960AB 138 #define QCOM_ID_APQ8060AB 139 #define QCOM_ID_MSM8260AB 140 #define QCOM_ID_MSM8660AB 141 +#define QCOM_ID_MSM8930AA 142 +#define QCOM_ID_MSM8630AA 143 +#define QCOM_ID_MSM8230AA 144 #define QCOM_ID_MSM8626 145 #define QCOM_ID_MSM8610 147 #define QCOM_ID_APQ8064AB 153 +#define QCOM_ID_MSM8930AB 154 +#define QCOM_ID_MSM8630AB 155 +#define QCOM_ID_MSM8230AB 156 +#define QCOM_ID_APQ8030AB 157 #define QCOM_ID_MSM8226 158 #define QCOM_ID_MSM8526 159 +#define QCOM_ID_APQ8030AA 160 #define QCOM_ID_MSM8110 161 #define QCOM_ID_MSM8210 162 #define QCOM_ID_MSM8810 163 #define QCOM_ID_MSM8212 164 #define QCOM_ID_MSM8612 165 #define QCOM_ID_MSM8112 166 +#define QCOM_ID_MSM8125 167 #define QCOM_ID_MSM8225Q 168 #define QCOM_ID_MSM8625Q 169 #define QCOM_ID_MSM8125Q 170 #define QCOM_ID_APQ8064AA 172 #define QCOM_ID_APQ8084 178 +#define QCOM_ID_MSM8130 179 +#define QCOM_ID_MSM8130AA 180 +#define QCOM_ID_MSM8130AB 181 +#define QCOM_ID_MSM8627AA 182 +#define QCOM_ID_MSM8227AA 183 #define QCOM_ID_APQ8074 184 #define QCOM_ID_MSM8274 185 #define QCOM_ID_MSM8674 186 +#define QCOM_ID_MDM9635 187 #define QCOM_ID_MSM8974PRO_AC 194 #define QCOM_ID_MSM8126 198 #define QCOM_ID_APQ8026 199 #define QCOM_ID_MSM8926 200 +#define QCOM_ID_IPQ8062 201 +#define QCOM_ID_IPQ8064 202 +#define QCOM_ID_IPQ8066 203 +#define QCOM_ID_IPQ8068 204 #define QCOM_ID_MSM8326 205 #define QCOM_ID_MSM8916 206 #define QCOM_ID_MSM8994 207 @@ -68,34 +98,74 @@ #define QCOM_ID_MSM8510 225 #define QCOM_ID_MSM8512 226 #define QCOM_ID_MSM8936 233 +#define QCOM_ID_MDM9640 234 #define QCOM_ID_MSM8939 239 #define QCOM_ID_APQ8036 240 #define QCOM_ID_APQ8039 241 +#define QCOM_ID_MSM8236 242 +#define QCOM_ID_MSM8636 243 +#define QCOM_ID_MSM8909 245 #define QCOM_ID_MSM8996 246 #define QCOM_ID_APQ8016 247 #define QCOM_ID_MSM8216 248 #define QCOM_ID_MSM8116 249 #define QCOM_ID_MSM8616 250 #define QCOM_ID_MSM8992 251 +#define QCOM_ID_APQ8092 252 #define QCOM_ID_APQ8094 253 +#define QCOM_ID_MSM8209 258 +#define QCOM_ID_MSM8208 259 +#define QCOM_ID_MDM9209 260 +#define QCOM_ID_MDM9309 261 +#define QCOM_ID_MDM9609 262 +#define QCOM_ID_MSM8239 263 +#define QCOM_ID_MSM8952 264 +#define QCOM_ID_APQ8009 265 #define QCOM_ID_MSM8956 266 +#define QCOM_ID_MSM8929 268 +#define QCOM_ID_MSM8629 269 +#define QCOM_ID_MSM8229 270 +#define QCOM_ID_APQ8029 271 +#define QCOM_ID_APQ8056 274 +#define QCOM_ID_MSM8609 275 +#define QCOM_ID_APQ8076 277 #define QCOM_ID_MSM8976 278 +#define QCOM_ID_MDM9650 279 +#define QCOM_ID_IPQ8065 280 +#define QCOM_ID_IPQ8069 281 +#define QCOM_ID_MDM9655 283 +#define QCOM_ID_MDM9250 284 +#define QCOM_ID_MDM9255 285 +#define QCOM_ID_MDM9350 286 +#define QCOM_ID_APQ8052 289 #define QCOM_ID_MDM9607 290 #define QCOM_ID_APQ8096 291 #define QCOM_ID_MSM8998 292 #define QCOM_ID_MSM8953 293 +#define QCOM_ID_MSM8937 294 +#define QCOM_ID_APQ8037 295 #define QCOM_ID_MDM8207 296 #define QCOM_ID_MDM9207 297 #define QCOM_ID_MDM9307 298 #define QCOM_ID_MDM9628 299 +#define QCOM_ID_MSM8909W 300 +#define QCOM_ID_APQ8009W 301 +#define QCOM_ID_MSM8996L 302 +#define QCOM_ID_MSM8917 303 #define QCOM_ID_APQ8053 304 #define QCOM_ID_MSM8996SG 305 +#define QCOM_ID_APQ8017 307 +#define QCOM_ID_MSM8217 308 +#define QCOM_ID_MSM8617 309 #define QCOM_ID_MSM8996AU 310 #define QCOM_ID_APQ8096AU 311 #define QCOM_ID_APQ8096SG 312 +#define QCOM_ID_MSM8940 313 +#define QCOM_ID_SDX201 314 #define QCOM_ID_SDM660 317 #define QCOM_ID_SDM630 318 #define QCOM_ID_APQ8098 319 +#define QCOM_ID_MSM8920 320 #define QCOM_ID_SDM845 321 #define QCOM_ID_MDM9206 322 #define QCOM_ID_IPQ8074 323 @@ -103,6 +173,8 @@ #define QCOM_ID_SDM658 325 #define QCOM_ID_SDA658 326 #define QCOM_ID_SDA630 327 +#define QCOM_ID_MSM8905 331 +#define QCOM_ID_SDX202 333 #define QCOM_ID_SDM450 338 #define QCOM_ID_SM8150 339 #define QCOM_ID_SDA845 341 @@ -114,10 +186,15 @@ #define QCOM_ID_SDM632 349 #define QCOM_ID_SDA632 350 #define QCOM_ID_SDA450 351 +#define QCOM_ID_SDM439 353 +#define QCOM_ID_SDM429 354 #define QCOM_ID_SM8250 356 #define QCOM_ID_SA8155 362 +#define QCOM_ID_SDA439 363 +#define QCOM_ID_SDA429 364 #define QCOM_ID_IPQ8070 375 #define QCOM_ID_IPQ8071 376 +#define QCOM_ID_QM215 386 #define QCOM_ID_IPQ8072A 389 #define QCOM_ID_IPQ8074A 390 #define QCOM_ID_IPQ8076A 391 @@ -127,11 +204,14 @@ #define QCOM_ID_IPQ8071A 396 #define QCOM_ID_IPQ6018 402 #define QCOM_ID_IPQ6028 403 +#define QCOM_ID_SDM429W 416 #define QCOM_ID_SM4250 417 #define QCOM_ID_IPQ6000 421 #define QCOM_ID_IPQ6010 422 #define QCOM_ID_SC7180 425 #define QCOM_ID_SM6350 434 +#define QCOM_ID_QCM2150 436 +#define QCOM_ID_SDA429W 437 #define QCOM_ID_SM8350 439 #define QCOM_ID_SM6115 444 #define QCOM_ID_SC8280XP 449 @@ -155,6 +235,8 @@ #define QCOM_ID_QRU1032 588 #define QCOM_ID_QRU1052 589 #define QCOM_ID_QRU1062 590 +#define QCOM_ID_IPQ5332 592 +#define QCOM_ID_IPQ5322 593 /* * The board type and revision information, used by Qualcomm bootloaders and @@ -165,6 +247,7 @@ #define QCOM_BOARD_ID_MTP 8 #define QCOM_BOARD_ID_DRAGONBOARD 10 +#define QCOM_BOARD_ID_QRD 11 #define QCOM_BOARD_ID_SBC 24 #endif /* _DT_BINDINGS_ARM_QCOM_IDS_H */ diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h index e20c43cc36f6..e5b2a1ba02bc 100644 --- a/include/dt-bindings/clock/imx6qdl-clock.h +++ b/include/dt-bindings/clock/imx6qdl-clock.h @@ -273,6 +273,8 @@ #define IMX6QDL_CLK_MMDC_P0_IPG 263 #define IMX6QDL_CLK_DCIC1 264 #define IMX6QDL_CLK_DCIC2 265 -#define IMX6QDL_CLK_END 266 +#define IMX6QDL_CLK_ENET_REF_SEL 266 +#define IMX6QDL_CLK_ENET_REF_PAD 267 +#define IMX6QDL_CLK_END 268 #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */ diff --git a/include/dt-bindings/clock/imx6sll-clock.h b/include/dt-bindings/clock/imx6sll-clock.h index f446710fe63d..494fd0c37fb5 100644 --- a/include/dt-bindings/clock/imx6sll-clock.h +++ b/include/dt-bindings/clock/imx6sll-clock.h @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. * Copyright 2017-2018 NXP. diff --git a/include/dt-bindings/clock/imx6ul-clock.h b/include/dt-bindings/clock/imx6ul-clock.h index 79094338e6f1..66239ebc0e23 100644 --- a/include/dt-bindings/clock/imx6ul-clock.h +++ b/include/dt-bindings/clock/imx6ul-clock.h @@ -256,7 +256,12 @@ #define IMX6UL_CLK_GPIO4 247 #define IMX6UL_CLK_GPIO5 248 #define IMX6UL_CLK_MMDC_P1_IPG 249 +#define IMX6UL_CLK_ENET1_REF_125M 250 +#define IMX6UL_CLK_ENET1_REF_SEL 251 +#define IMX6UL_CLK_ENET1_REF_PAD 252 +#define IMX6UL_CLK_ENET2_REF_SEL 253 +#define IMX6UL_CLK_ENET2_REF_PAD 254 -#define IMX6UL_CLK_END 250 +#define IMX6UL_CLK_END 255 #endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */ diff --git a/include/dt-bindings/clock/imx8ulp-clock.h b/include/dt-bindings/clock/imx8ulp-clock.h index 953ecfe8ebcc..827404fadf5c 100644 --- a/include/dt-bindings/clock/imx8ulp-clock.h +++ b/include/dt-bindings/clock/imx8ulp-clock.h @@ -201,7 +201,7 @@ #define IMX8ULP_CLK_SAI7 2 #define IMX8ULP_CLK_SPDIF 3 #define IMX8ULP_CLK_ISI 4 -#define IMX8ULP_CLK_CSI_REGS 5 +#define IMX8ULP_CLK_CSI_REGS 5 #define IMX8ULP_CLK_PCTLD 6 #define IMX8ULP_CLK_CSI 7 #define IMX8ULP_CLK_DSI 8 @@ -212,7 +212,7 @@ #define IMX8ULP_CLK_GPU2D 13 #define IMX8ULP_CLK_GPU3D 14 #define IMX8ULP_CLK_DC_NANO 15 -#define IMX8ULP_CLK_CSI_CLK_UI 16 +#define IMX8ULP_CLK_CSI_CLK_UI 16 #define IMX8ULP_CLK_CSI_CLK_ESC 17 #define IMX8ULP_CLK_RGPIOD 18 #define IMX8ULP_CLK_DMA2_MP 19 diff --git a/include/dt-bindings/clock/loongson,ls2k-clk.h b/include/dt-bindings/clock/loongson,ls2k-clk.h new file mode 100644 index 000000000000..db1e27e792ff --- /dev/null +++ b/include/dt-bindings/clock/loongson,ls2k-clk.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Author: Yinbo Zhu <zhuyinbo@loongson.cn> + * Copyright (C) 2022-2023 Loongson Technology Corporation Limited + */ + +#ifndef __DT_BINDINGS_CLOCK_LOONGSON2_H +#define __DT_BINDINGS_CLOCK_LOONGSON2_H + +#define LOONGSON2_REF_100M 0 +#define LOONGSON2_NODE_PLL 1 +#define LOONGSON2_DDR_PLL 2 +#define LOONGSON2_DC_PLL 3 +#define LOONGSON2_PIX0_PLL 4 +#define LOONGSON2_PIX1_PLL 5 +#define LOONGSON2_NODE_CLK 6 +#define LOONGSON2_HDA_CLK 7 +#define LOONGSON2_GPU_CLK 8 +#define LOONGSON2_DDR_CLK 9 +#define LOONGSON2_GMAC_CLK 10 +#define LOONGSON2_DC_CLK 11 +#define LOONGSON2_APB_CLK 12 +#define LOONGSON2_USB_CLK 13 +#define LOONGSON2_SATA_CLK 14 +#define LOONGSON2_PIX0_CLK 15 +#define LOONGSON2_PIX1_CLK 16 +#define LOONGSON2_CLK_END 17 + +#endif diff --git a/include/dt-bindings/clock/mediatek,mt7981-clk.h b/include/dt-bindings/clock/mediatek,mt7981-clk.h new file mode 100644 index 000000000000..192f8cefb589 --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mt7981-clk.h @@ -0,0 +1,215 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021 MediaTek Inc. + * Author: Wenzhen.Yu <wenzhen.yu@mediatek.com> + * Author: Jianhui Zhao <zhaojh329@gmail.com> + * Author: Daniel Golle <daniel@makrotopia.org> + */ + +#ifndef _DT_BINDINGS_CLK_MT7981_H +#define _DT_BINDINGS_CLK_MT7981_H + +/* TOPCKGEN */ +#define CLK_TOP_CB_CKSQ_40M 0 +#define CLK_TOP_CB_M_416M 1 +#define CLK_TOP_CB_M_D2 2 +#define CLK_TOP_CB_M_D3 3 +#define CLK_TOP_M_D3_D2 4 +#define CLK_TOP_CB_M_D4 5 +#define CLK_TOP_CB_M_D8 6 +#define CLK_TOP_M_D8_D2 7 +#define CLK_TOP_CB_MM_720M 8 +#define CLK_TOP_CB_MM_D2 9 +#define CLK_TOP_CB_MM_D3 10 +#define CLK_TOP_CB_MM_D3_D5 11 +#define CLK_TOP_CB_MM_D4 12 +#define CLK_TOP_CB_MM_D6 13 +#define CLK_TOP_MM_D6_D2 14 +#define CLK_TOP_CB_MM_D8 15 +#define CLK_TOP_CB_APLL2_196M 16 +#define CLK_TOP_APLL2_D2 17 +#define CLK_TOP_APLL2_D4 18 +#define CLK_TOP_NET1_2500M 19 +#define CLK_TOP_CB_NET1_D4 20 +#define CLK_TOP_CB_NET1_D5 21 +#define CLK_TOP_NET1_D5_D2 22 +#define CLK_TOP_NET1_D5_D4 23 +#define CLK_TOP_CB_NET1_D8 24 +#define CLK_TOP_NET1_D8_D2 25 +#define CLK_TOP_NET1_D8_D4 26 +#define CLK_TOP_CB_NET2_800M 27 +#define CLK_TOP_CB_NET2_D2 28 +#define CLK_TOP_CB_NET2_D4 29 +#define CLK_TOP_NET2_D4_D2 30 +#define CLK_TOP_NET2_D4_D4 31 +#define CLK_TOP_CB_NET2_D6 32 +#define CLK_TOP_CB_WEDMCU_208M 33 +#define CLK_TOP_CB_SGM_325M 34 +#define CLK_TOP_CKSQ_40M_D2 35 +#define CLK_TOP_CB_RTC_32K 36 +#define CLK_TOP_CB_RTC_32P7K 37 +#define CLK_TOP_USB_TX250M 38 +#define CLK_TOP_FAUD 39 +#define CLK_TOP_NFI1X 40 +#define CLK_TOP_USB_EQ_RX250M 41 +#define CLK_TOP_USB_CDR_CK 42 +#define CLK_TOP_USB_LN0_CK 43 +#define CLK_TOP_SPINFI_BCK 44 +#define CLK_TOP_SPI 45 +#define CLK_TOP_SPIM_MST 46 +#define CLK_TOP_UART_BCK 47 +#define CLK_TOP_PWM_BCK 48 +#define CLK_TOP_I2C_BCK 49 +#define CLK_TOP_PEXTP_TL 50 +#define CLK_TOP_EMMC_208M 51 +#define CLK_TOP_EMMC_400M 52 +#define CLK_TOP_DRAMC_REF 53 +#define CLK_TOP_DRAMC_MD32 54 +#define CLK_TOP_SYSAXI 55 +#define CLK_TOP_SYSAPB 56 +#define CLK_TOP_ARM_DB_MAIN 57 +#define CLK_TOP_AP2CNN_HOST 58 +#define CLK_TOP_NETSYS 59 +#define CLK_TOP_NETSYS_500M 60 +#define CLK_TOP_NETSYS_WED_MCU 61 +#define CLK_TOP_NETSYS_2X 62 +#define CLK_TOP_SGM_325M 63 +#define CLK_TOP_SGM_REG 64 +#define CLK_TOP_F26M 65 +#define CLK_TOP_EIP97B 66 +#define CLK_TOP_USB3_PHY 67 +#define CLK_TOP_AUD 68 +#define CLK_TOP_A1SYS 69 +#define CLK_TOP_AUD_L 70 +#define CLK_TOP_A_TUNER 71 +#define CLK_TOP_U2U3_REF 72 +#define CLK_TOP_U2U3_SYS 73 +#define CLK_TOP_U2U3_XHCI 74 +#define CLK_TOP_USB_FRMCNT 75 +#define CLK_TOP_NFI1X_SEL 76 +#define CLK_TOP_SPINFI_SEL 77 +#define CLK_TOP_SPI_SEL 78 +#define CLK_TOP_SPIM_MST_SEL 79 +#define CLK_TOP_UART_SEL 80 +#define CLK_TOP_PWM_SEL 81 +#define CLK_TOP_I2C_SEL 82 +#define CLK_TOP_PEXTP_TL_SEL 83 +#define CLK_TOP_EMMC_208M_SEL 84 +#define CLK_TOP_EMMC_400M_SEL 85 +#define CLK_TOP_F26M_SEL 86 +#define CLK_TOP_DRAMC_SEL 87 +#define CLK_TOP_DRAMC_MD32_SEL 88 +#define CLK_TOP_SYSAXI_SEL 89 +#define CLK_TOP_SYSAPB_SEL 90 +#define CLK_TOP_ARM_DB_MAIN_SEL 91 +#define CLK_TOP_AP2CNN_HOST_SEL 92 +#define CLK_TOP_NETSYS_SEL 93 +#define CLK_TOP_NETSYS_500M_SEL 94 +#define CLK_TOP_NETSYS_MCU_SEL 95 +#define CLK_TOP_NETSYS_2X_SEL 96 +#define CLK_TOP_SGM_325M_SEL 97 +#define CLK_TOP_SGM_REG_SEL 98 +#define CLK_TOP_EIP97B_SEL 99 +#define CLK_TOP_USB3_PHY_SEL 100 +#define CLK_TOP_AUD_SEL 101 +#define CLK_TOP_A1SYS_SEL 102 +#define CLK_TOP_AUD_L_SEL 103 +#define CLK_TOP_A_TUNER_SEL 104 +#define CLK_TOP_U2U3_SEL 105 +#define CLK_TOP_U2U3_SYS_SEL 106 +#define CLK_TOP_U2U3_XHCI_SEL 107 +#define CLK_TOP_USB_FRMCNT_SEL 108 +#define CLK_TOP_AUD_I2S_M 109 + +/* INFRACFG */ +#define CLK_INFRA_66M_MCK 0 +#define CLK_INFRA_UART0_SEL 1 +#define CLK_INFRA_UART1_SEL 2 +#define CLK_INFRA_UART2_SEL 3 +#define CLK_INFRA_SPI0_SEL 4 +#define CLK_INFRA_SPI1_SEL 5 +#define CLK_INFRA_SPI2_SEL 6 +#define CLK_INFRA_PWM1_SEL 7 +#define CLK_INFRA_PWM2_SEL 8 +#define CLK_INFRA_PWM3_SEL 9 +#define CLK_INFRA_PWM_BSEL 10 +#define CLK_INFRA_PCIE_SEL 11 +#define CLK_INFRA_GPT_STA 12 +#define CLK_INFRA_PWM_HCK 13 +#define CLK_INFRA_PWM_STA 14 +#define CLK_INFRA_PWM1_CK 15 +#define CLK_INFRA_PWM2_CK 16 +#define CLK_INFRA_PWM3_CK 17 +#define CLK_INFRA_CQ_DMA_CK 18 +#define CLK_INFRA_AUD_BUS_CK 19 +#define CLK_INFRA_AUD_26M_CK 20 +#define CLK_INFRA_AUD_L_CK 21 +#define CLK_INFRA_AUD_AUD_CK 22 +#define CLK_INFRA_AUD_EG2_CK 23 +#define CLK_INFRA_DRAMC_26M_CK 24 +#define CLK_INFRA_DBG_CK 25 +#define CLK_INFRA_AP_DMA_CK 26 +#define CLK_INFRA_SEJ_CK 27 +#define CLK_INFRA_SEJ_13M_CK 28 +#define CLK_INFRA_THERM_CK 29 +#define CLK_INFRA_I2C0_CK 30 +#define CLK_INFRA_UART0_CK 31 +#define CLK_INFRA_UART1_CK 32 +#define CLK_INFRA_UART2_CK 33 +#define CLK_INFRA_SPI2_CK 34 +#define CLK_INFRA_SPI2_HCK_CK 35 +#define CLK_INFRA_NFI1_CK 36 +#define CLK_INFRA_SPINFI1_CK 37 +#define CLK_INFRA_NFI_HCK_CK 38 +#define CLK_INFRA_SPI0_CK 39 +#define CLK_INFRA_SPI1_CK 40 +#define CLK_INFRA_SPI0_HCK_CK 41 +#define CLK_INFRA_SPI1_HCK_CK 42 +#define CLK_INFRA_FRTC_CK 43 +#define CLK_INFRA_MSDC_CK 44 +#define CLK_INFRA_MSDC_HCK_CK 45 +#define CLK_INFRA_MSDC_133M_CK 46 +#define CLK_INFRA_MSDC_66M_CK 47 +#define CLK_INFRA_ADC_26M_CK 48 +#define CLK_INFRA_ADC_FRC_CK 49 +#define CLK_INFRA_FBIST2FPC_CK 50 +#define CLK_INFRA_I2C_MCK_CK 51 +#define CLK_INFRA_I2C_PCK_CK 52 +#define CLK_INFRA_IUSB_133_CK 53 +#define CLK_INFRA_IUSB_66M_CK 54 +#define CLK_INFRA_IUSB_SYS_CK 55 +#define CLK_INFRA_IUSB_CK 56 +#define CLK_INFRA_IPCIE_CK 57 +#define CLK_INFRA_IPCIE_PIPE_CK 58 +#define CLK_INFRA_IPCIER_CK 59 +#define CLK_INFRA_IPCIEB_CK 60 + +/* APMIXEDSYS */ +#define CLK_APMIXED_ARMPLL 0 +#define CLK_APMIXED_NET2PLL 1 +#define CLK_APMIXED_MMPLL 2 +#define CLK_APMIXED_SGMPLL 3 +#define CLK_APMIXED_WEDMCUPLL 4 +#define CLK_APMIXED_NET1PLL 5 +#define CLK_APMIXED_MPLL 6 +#define CLK_APMIXED_APLL2 7 + +/* SGMIISYS_0 */ +#define CLK_SGM0_TX_EN 0 +#define CLK_SGM0_RX_EN 1 +#define CLK_SGM0_CK0_EN 2 +#define CLK_SGM0_CDR_CK0_EN 3 + +/* SGMIISYS_1 */ +#define CLK_SGM1_TX_EN 0 +#define CLK_SGM1_RX_EN 1 +#define CLK_SGM1_CK1_EN 2 +#define CLK_SGM1_CDR_CK1_EN 3 + +/* ETHSYS */ +#define CLK_ETH_FE_EN 0 +#define CLK_ETH_GP2_EN 1 +#define CLK_ETH_GP1_EN 2 +#define CLK_ETH_WOCPU0_EN 3 + +#endif /* _DT_BINDINGS_CLK_MT7981_H */ diff --git a/include/dt-bindings/clock/qcom,gcc-apq8084.h b/include/dt-bindings/clock/qcom,gcc-apq8084.h index 7f657cf8cc8a..a985248d6332 100644 --- a/include/dt-bindings/clock/qcom,gcc-apq8084.h +++ b/include/dt-bindings/clock/qcom,gcc-apq8084.h @@ -339,6 +339,7 @@ #define GCC_PCIE_1_MSTR_AXI_CLK 330 #define GCC_PCIE_1_PIPE_CLK 331 #define GCC_PCIE_1_SLV_AXI_CLK 332 +#define GCC_MMSS_GPLL0_CLK_SRC 333 /* gdscs */ #define USB_HS_HSIC_GDSC 0 diff --git a/include/dt-bindings/clock/qcom,gcc-qcs404.h b/include/dt-bindings/clock/qcom,gcc-qcs404.h index bc3051543347..126a51898571 100644 --- a/include/dt-bindings/clock/qcom,gcc-qcs404.h +++ b/include/dt-bindings/clock/qcom,gcc-qcs404.h @@ -177,4 +177,8 @@ #define GCC_PCIE_0_PIPE_ARES 21 #define GCC_WDSP_RESTART 22 +/* Indexes for GDSCs */ +#define MDSS_GDSC 0 +#define OXILI_GDSC 1 + #endif diff --git a/include/dt-bindings/clock/qcom,gcc-sm8350.h b/include/dt-bindings/clock/qcom,gcc-sm8350.h index f6be3da5f781..529c1b8b0417 100644 --- a/include/dt-bindings/clock/qcom,gcc-sm8350.h +++ b/include/dt-bindings/clock/qcom,gcc-sm8350.h @@ -8,7 +8,6 @@ #define _DT_BINDINGS_CLK_QCOM_GCC_SM8350_H /* GCC HW clocks */ -#define CORE_BI_PLL_TEST_SE 0 #define PCIE_0_PIPE_CLK 1 #define PCIE_1_PIPE_CLK 2 #define UFS_CARD_RX_SYMBOL_0_CLK 3 diff --git a/include/dt-bindings/clock/qcom,gcc-sm8450.h b/include/dt-bindings/clock/qcom,gcc-sm8450.h index cf1469312c4c..9679410843a0 100644 --- a/include/dt-bindings/clock/qcom,gcc-sm8450.h +++ b/include/dt-bindings/clock/qcom,gcc-sm8450.h @@ -8,7 +8,6 @@ #define _DT_BINDINGS_CLK_QCOM_GCC_SM8450_H /* GCC HW clocks */ -#define CORE_BI_PLL_TEST_SE 0 #define PCIE_0_PIPE_CLK 1 #define PCIE_1_PHY_AUX_CLK 2 #define PCIE_1_PIPE_CLK 3 diff --git a/include/dt-bindings/clock/qcom,rpmcc.h b/include/dt-bindings/clock/qcom,rpmcc.h index c0ad624e930e..46309c9953b2 100644 --- a/include/dt-bindings/clock/qcom,rpmcc.h +++ b/include/dt-bindings/clock/qcom,rpmcc.h @@ -168,5 +168,7 @@ #define RPM_SMD_MSS_CFG_AHB_CLK 122 #define RPM_SMD_MSS_CFG_AHB_A_CLK 123 #define RPM_SMD_BIMC_FREQ_LOG 124 +#define RPM_SMD_LN_BB_CLK_PIN 125 +#define RPM_SMD_LN_BB_A_CLK_PIN 126 #endif diff --git a/include/dt-bindings/clock/qcom,sa8775p-gcc.h b/include/dt-bindings/clock/qcom,sa8775p-gcc.h new file mode 100644 index 000000000000..01f54234963d --- /dev/null +++ b/include/dt-bindings/clock/qcom,sa8775p-gcc.h @@ -0,0 +1,320 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SA8775P_H +#define _DT_BINDINGS_CLK_QCOM_GCC_SA8775P_H + +/* GCC clocks */ +#define GCC_GPLL0 0 +#define GCC_GPLL0_OUT_EVEN 1 +#define GCC_GPLL1 2 +#define GCC_GPLL4 3 +#define GCC_GPLL5 4 +#define GCC_GPLL7 5 +#define GCC_GPLL9 6 +#define GCC_AGGRE_NOC_QUPV3_AXI_CLK 7 +#define GCC_AGGRE_UFS_CARD_AXI_CLK 8 +#define GCC_AGGRE_UFS_PHY_AXI_CLK 9 +#define GCC_AGGRE_USB2_PRIM_AXI_CLK 10 +#define GCC_AGGRE_USB3_PRIM_AXI_CLK 11 +#define GCC_AGGRE_USB3_SEC_AXI_CLK 12 +#define GCC_AHB2PHY0_CLK 13 +#define GCC_AHB2PHY2_CLK 14 +#define GCC_AHB2PHY3_CLK 15 +#define GCC_BOOT_ROM_AHB_CLK 16 +#define GCC_CAMERA_AHB_CLK 17 +#define GCC_CAMERA_HF_AXI_CLK 18 +#define GCC_CAMERA_SF_AXI_CLK 19 +#define GCC_CAMERA_THROTTLE_XO_CLK 20 +#define GCC_CAMERA_XO_CLK 21 +#define GCC_CFG_NOC_USB2_PRIM_AXI_CLK 22 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 23 +#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 24 +#define GCC_DDRSS_GPU_AXI_CLK 25 +#define GCC_DISP1_AHB_CLK 26 +#define GCC_DISP1_HF_AXI_CLK 27 +#define GCC_DISP1_XO_CLK 28 +#define GCC_DISP_AHB_CLK 29 +#define GCC_DISP_HF_AXI_CLK 30 +#define GCC_DISP_XO_CLK 31 +#define GCC_EDP_REF_CLKREF_EN 32 +#define GCC_EMAC0_AXI_CLK 33 +#define GCC_EMAC0_PHY_AUX_CLK 34 +#define GCC_EMAC0_PHY_AUX_CLK_SRC 35 +#define GCC_EMAC0_PTP_CLK 36 +#define GCC_EMAC0_PTP_CLK_SRC 37 +#define GCC_EMAC0_RGMII_CLK 38 +#define GCC_EMAC0_RGMII_CLK_SRC 39 +#define GCC_EMAC0_SLV_AHB_CLK 40 +#define GCC_EMAC1_AXI_CLK 41 +#define GCC_EMAC1_PHY_AUX_CLK 42 +#define GCC_EMAC1_PHY_AUX_CLK_SRC 43 +#define GCC_EMAC1_PTP_CLK 44 +#define GCC_EMAC1_PTP_CLK_SRC 45 +#define GCC_EMAC1_RGMII_CLK 46 +#define GCC_EMAC1_RGMII_CLK_SRC 47 +#define GCC_EMAC1_SLV_AHB_CLK 48 +#define GCC_GP1_CLK 49 +#define GCC_GP1_CLK_SRC 50 +#define GCC_GP2_CLK 51 +#define GCC_GP2_CLK_SRC 52 +#define GCC_GP3_CLK 53 +#define GCC_GP3_CLK_SRC 54 +#define GCC_GP4_CLK 55 +#define GCC_GP4_CLK_SRC 56 +#define GCC_GP5_CLK 57 +#define GCC_GP5_CLK_SRC 58 +#define GCC_GPU_CFG_AHB_CLK 59 +#define GCC_GPU_GPLL0_CLK_SRC 60 +#define GCC_GPU_GPLL0_DIV_CLK_SRC 61 +#define GCC_GPU_MEMNOC_GFX_CLK 62 +#define GCC_GPU_SNOC_DVM_GFX_CLK 63 +#define GCC_GPU_TCU_THROTTLE_AHB_CLK 64 +#define GCC_GPU_TCU_THROTTLE_CLK 65 +#define GCC_PCIE_0_AUX_CLK 66 +#define GCC_PCIE_0_AUX_CLK_SRC 67 +#define GCC_PCIE_0_CFG_AHB_CLK 68 +#define GCC_PCIE_0_MSTR_AXI_CLK 69 +#define GCC_PCIE_0_PHY_AUX_CLK 70 +#define GCC_PCIE_0_PHY_AUX_CLK_SRC 71 +#define GCC_PCIE_0_PHY_RCHNG_CLK 72 +#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 73 +#define GCC_PCIE_0_PIPE_CLK 74 +#define GCC_PCIE_0_PIPE_CLK_SRC 75 +#define GCC_PCIE_0_PIPE_DIV_CLK_SRC 76 +#define GCC_PCIE_0_PIPEDIV2_CLK 77 +#define GCC_PCIE_0_SLV_AXI_CLK 78 +#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 79 +#define GCC_PCIE_1_AUX_CLK 80 +#define GCC_PCIE_1_AUX_CLK_SRC 81 +#define GCC_PCIE_1_CFG_AHB_CLK 82 +#define GCC_PCIE_1_MSTR_AXI_CLK 83 +#define GCC_PCIE_1_PHY_AUX_CLK 84 +#define GCC_PCIE_1_PHY_AUX_CLK_SRC 85 +#define GCC_PCIE_1_PHY_RCHNG_CLK 86 +#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 87 +#define GCC_PCIE_1_PIPE_CLK 88 +#define GCC_PCIE_1_PIPE_CLK_SRC 89 +#define GCC_PCIE_1_PIPE_DIV_CLK_SRC 90 +#define GCC_PCIE_1_PIPEDIV2_CLK 91 +#define GCC_PCIE_1_SLV_AXI_CLK 92 +#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 93 +#define GCC_PCIE_CLKREF_EN 94 +#define GCC_PCIE_THROTTLE_CFG_CLK 95 +#define GCC_PDM2_CLK 96 +#define GCC_PDM2_CLK_SRC 97 +#define GCC_PDM_AHB_CLK 98 +#define GCC_PDM_XO4_CLK 99 +#define GCC_QMIP_CAMERA_NRT_AHB_CLK 100 +#define GCC_QMIP_CAMERA_RT_AHB_CLK 101 +#define GCC_QMIP_DISP1_AHB_CLK 102 +#define GCC_QMIP_DISP1_ROT_AHB_CLK 103 +#define GCC_QMIP_DISP_AHB_CLK 104 +#define GCC_QMIP_DISP_ROT_AHB_CLK 105 +#define GCC_QMIP_VIDEO_CVP_AHB_CLK 106 +#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 107 +#define GCC_QMIP_VIDEO_VCPU_AHB_CLK 108 +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 109 +#define GCC_QUPV3_WRAP0_CORE_CLK 110 +#define GCC_QUPV3_WRAP0_S0_CLK 111 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 112 +#define GCC_QUPV3_WRAP0_S1_CLK 113 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 114 +#define GCC_QUPV3_WRAP0_S2_CLK 115 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 116 +#define GCC_QUPV3_WRAP0_S3_CLK 117 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 118 +#define GCC_QUPV3_WRAP0_S4_CLK 119 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 120 +#define GCC_QUPV3_WRAP0_S5_CLK 121 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 122 +#define GCC_QUPV3_WRAP0_S6_CLK 123 +#define GCC_QUPV3_WRAP0_S6_CLK_SRC 124 +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 125 +#define GCC_QUPV3_WRAP1_CORE_CLK 126 +#define GCC_QUPV3_WRAP1_S0_CLK 127 +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 128 +#define GCC_QUPV3_WRAP1_S1_CLK 129 +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 130 +#define GCC_QUPV3_WRAP1_S2_CLK 131 +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 132 +#define GCC_QUPV3_WRAP1_S3_CLK 133 +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 134 +#define GCC_QUPV3_WRAP1_S4_CLK 135 +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 136 +#define GCC_QUPV3_WRAP1_S5_CLK 137 +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 138 +#define GCC_QUPV3_WRAP1_S6_CLK 139 +#define GCC_QUPV3_WRAP1_S6_CLK_SRC 140 +#define GCC_QUPV3_WRAP2_CORE_2X_CLK 141 +#define GCC_QUPV3_WRAP2_CORE_CLK 142 +#define GCC_QUPV3_WRAP2_S0_CLK 143 +#define GCC_QUPV3_WRAP2_S0_CLK_SRC 144 +#define GCC_QUPV3_WRAP2_S1_CLK 145 +#define GCC_QUPV3_WRAP2_S1_CLK_SRC 146 +#define GCC_QUPV3_WRAP2_S2_CLK 147 +#define GCC_QUPV3_WRAP2_S2_CLK_SRC 148 +#define GCC_QUPV3_WRAP2_S3_CLK 149 +#define GCC_QUPV3_WRAP2_S3_CLK_SRC 150 +#define GCC_QUPV3_WRAP2_S4_CLK 151 +#define GCC_QUPV3_WRAP2_S4_CLK_SRC 152 +#define GCC_QUPV3_WRAP2_S5_CLK 153 +#define GCC_QUPV3_WRAP2_S5_CLK_SRC 154 +#define GCC_QUPV3_WRAP2_S6_CLK 155 +#define GCC_QUPV3_WRAP2_S6_CLK_SRC 156 +#define GCC_QUPV3_WRAP3_CORE_2X_CLK 157 +#define GCC_QUPV3_WRAP3_CORE_CLK 158 +#define GCC_QUPV3_WRAP3_QSPI_CLK 159 +#define GCC_QUPV3_WRAP3_S0_CLK 160 +#define GCC_QUPV3_WRAP3_S0_CLK_SRC 161 +#define GCC_QUPV3_WRAP3_S0_DIV_CLK_SRC 162 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 163 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 164 +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 165 +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 166 +#define GCC_QUPV3_WRAP_2_M_AHB_CLK 167 +#define GCC_QUPV3_WRAP_2_S_AHB_CLK 168 +#define GCC_QUPV3_WRAP_3_M_AHB_CLK 169 +#define GCC_QUPV3_WRAP_3_S_AHB_CLK 170 +#define GCC_SDCC1_AHB_CLK 171 +#define GCC_SDCC1_APPS_CLK 172 +#define GCC_SDCC1_APPS_CLK_SRC 173 +#define GCC_SDCC1_ICE_CORE_CLK 174 +#define GCC_SDCC1_ICE_CORE_CLK_SRC 175 +#define GCC_SGMI_CLKREF_EN 176 +#define GCC_TSCSS_AHB_CLK 177 +#define GCC_TSCSS_CNTR_CLK_SRC 178 +#define GCC_TSCSS_ETU_CLK 179 +#define GCC_TSCSS_GLOBAL_CNTR_CLK 180 +#define GCC_UFS_CARD_AHB_CLK 181 +#define GCC_UFS_CARD_AXI_CLK 182 +#define GCC_UFS_CARD_AXI_CLK_SRC 183 +#define GCC_UFS_CARD_ICE_CORE_CLK 184 +#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 185 +#define GCC_UFS_CARD_PHY_AUX_CLK 186 +#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 187 +#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 188 +#define GCC_UFS_CARD_RX_SYMBOL_0_CLK_SRC 189 +#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 190 +#define GCC_UFS_CARD_RX_SYMBOL_1_CLK_SRC 191 +#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 192 +#define GCC_UFS_CARD_TX_SYMBOL_0_CLK_SRC 193 +#define GCC_UFS_CARD_UNIPRO_CORE_CLK 194 +#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 195 +#define GCC_UFS_PHY_AHB_CLK 196 +#define GCC_UFS_PHY_AXI_CLK 197 +#define GCC_UFS_PHY_AXI_CLK_SRC 198 +#define GCC_UFS_PHY_ICE_CORE_CLK 199 +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 200 +#define GCC_UFS_PHY_PHY_AUX_CLK 201 +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 202 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 203 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 204 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 205 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 206 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 207 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 208 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 209 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 210 +#define GCC_USB20_MASTER_CLK 211 +#define GCC_USB20_MASTER_CLK_SRC 212 +#define GCC_USB20_MOCK_UTMI_CLK 213 +#define GCC_USB20_MOCK_UTMI_CLK_SRC 214 +#define GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC 215 +#define GCC_USB20_SLEEP_CLK 216 +#define GCC_USB30_PRIM_MASTER_CLK 217 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 218 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 219 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 220 +#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 221 +#define GCC_USB30_PRIM_SLEEP_CLK 222 +#define GCC_USB30_SEC_MASTER_CLK 223 +#define GCC_USB30_SEC_MASTER_CLK_SRC 224 +#define GCC_USB30_SEC_MOCK_UTMI_CLK 225 +#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 226 +#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 227 +#define GCC_USB30_SEC_SLEEP_CLK 228 +#define GCC_USB3_PRIM_PHY_AUX_CLK 229 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 230 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 231 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 232 +#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 233 +#define GCC_USB3_SEC_PHY_AUX_CLK 234 +#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 235 +#define GCC_USB3_SEC_PHY_COM_AUX_CLK 236 +#define GCC_USB3_SEC_PHY_PIPE_CLK 237 +#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 238 +#define GCC_USB_CLKREF_EN 239 +#define GCC_VIDEO_AHB_CLK 240 +#define GCC_VIDEO_AXI0_CLK 241 +#define GCC_VIDEO_AXI1_CLK 242 +#define GCC_VIDEO_XO_CLK 243 +#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 244 +#define GCC_UFS_PHY_AXI_HW_CTL_CLK 245 +#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 246 +#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 247 +#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 248 + +/* GCC resets */ +#define GCC_CAMERA_BCR 0 +#define GCC_DISPLAY1_BCR 1 +#define GCC_DISPLAY_BCR 2 +#define GCC_EMAC0_BCR 3 +#define GCC_EMAC1_BCR 4 +#define GCC_GPU_BCR 5 +#define GCC_MMSS_BCR 6 +#define GCC_PCIE_0_BCR 7 +#define GCC_PCIE_0_LINK_DOWN_BCR 8 +#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 9 +#define GCC_PCIE_0_PHY_BCR 10 +#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 11 +#define GCC_PCIE_1_BCR 12 +#define GCC_PCIE_1_LINK_DOWN_BCR 13 +#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 14 +#define GCC_PCIE_1_PHY_BCR 15 +#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 16 +#define GCC_PDM_BCR 17 +#define GCC_QUPV3_WRAPPER_0_BCR 18 +#define GCC_QUPV3_WRAPPER_1_BCR 19 +#define GCC_QUPV3_WRAPPER_2_BCR 20 +#define GCC_QUPV3_WRAPPER_3_BCR 21 +#define GCC_SDCC1_BCR 22 +#define GCC_TSCSS_BCR 23 +#define GCC_UFS_CARD_BCR 24 +#define GCC_UFS_PHY_BCR 25 +#define GCC_USB20_PRIM_BCR 26 +#define GCC_USB2_PHY_PRIM_BCR 27 +#define GCC_USB2_PHY_SEC_BCR 28 +#define GCC_USB30_PRIM_BCR 29 +#define GCC_USB30_SEC_BCR 30 +#define GCC_USB3_DP_PHY_PRIM_BCR 31 +#define GCC_USB3_DP_PHY_SEC_BCR 32 +#define GCC_USB3_PHY_PRIM_BCR 33 +#define GCC_USB3_PHY_SEC_BCR 34 +#define GCC_USB3_PHY_TERT_BCR 35 +#define GCC_USB3_UNIPHY_MP0_BCR 36 +#define GCC_USB3_UNIPHY_MP1_BCR 37 +#define GCC_USB3PHY_PHY_PRIM_BCR 38 +#define GCC_USB3PHY_PHY_SEC_BCR 39 +#define GCC_USB3UNIPHY_PHY_MP0_BCR 40 +#define GCC_USB3UNIPHY_PHY_MP1_BCR 41 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 42 +#define GCC_VIDEO_BCR 43 +#define GCC_VIDEO_AXI0_CLK_ARES 44 +#define GCC_VIDEO_AXI1_CLK_ARES 45 + +/* GCC GDSCs */ +#define PCIE_0_GDSC 0 +#define PCIE_1_GDSC 1 +#define UFS_CARD_GDSC 2 +#define UFS_PHY_GDSC 3 +#define USB20_PRIM_GDSC 4 +#define USB30_PRIM_GDSC 5 +#define USB30_SEC_GDSC 6 +#define EMAC0_GDSC 7 +#define EMAC1_GDSC 8 + +#endif /* _DT_BINDINGS_CLK_QCOM_GCC_SA8775P_H */ diff --git a/include/dt-bindings/clock/stih416-clks.h b/include/dt-bindings/clock/stih416-clks.h deleted file mode 100644 index 74302278024e..000000000000 --- a/include/dt-bindings/clock/stih416-clks.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants clk index STMicroelectronics - * STiH416 SoC. - */ -#ifndef _CLK_STIH416 -#define _CLK_STIH416 - -/* CLOCKGEN A0 */ -#define CLK_ICN_REG 0 -#define CLK_ETH1_PHY 4 - -/* CLOCKGEN A1 */ -#define CLK_ICN_IF_2 0 -#define CLK_GMAC0_PHY 3 - -#endif diff --git a/include/dt-bindings/clock/sun20i-d1-ccu.h b/include/dt-bindings/clock/sun20i-d1-ccu.h index e3ac53315e1a..e143b9929763 100644 --- a/include/dt-bindings/clock/sun20i-d1-ccu.h +++ b/include/dt-bindings/clock/sun20i-d1-ccu.h @@ -152,5 +152,7 @@ #define CLK_FANOUT0 142 #define CLK_FANOUT1 143 #define CLK_FANOUT2 144 +#define CLK_BUS_CAN0 145 +#define CLK_BUS_CAN1 146 #endif /* _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_ */ diff --git a/include/dt-bindings/firmware/qcom,scm.h b/include/dt-bindings/firmware/qcom,scm.h new file mode 100644 index 000000000000..1a4e68fa0744 --- /dev/null +++ b/include/dt-bindings/firmware/qcom,scm.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (c) 2010-2015, 2018-2019 The Linux Foundation. All rights reserved. + * Copyright (C) 2015 Linaro Ltd. + */ + +#ifndef _DT_BINDINGS_FIRMWARE_QCOM_SCM_H +#define _DT_BINDINGS_FIRMWARE_QCOM_SCM_H + +#define QCOM_SCM_VMID_HLOS 0x3 +#define QCOM_SCM_VMID_MSS_MSA 0xF +#define QCOM_SCM_VMID_WLAN 0x18 +#define QCOM_SCM_VMID_WLAN_CE 0x19 +#define QCOM_SCM_VMID_NAV 0x2B + +#endif diff --git a/include/dt-bindings/gpio/gpio.h b/include/dt-bindings/gpio/gpio.h index 5566e58196a2..b5d531237448 100644 --- a/include/dt-bindings/gpio/gpio.h +++ b/include/dt-bindings/gpio/gpio.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */ /* * This header provides constants for most GPIO bindings. * diff --git a/include/dt-bindings/power/allwinner,sun20i-d1-ppu.h b/include/dt-bindings/power/allwinner,sun20i-d1-ppu.h new file mode 100644 index 000000000000..23cfb57256d6 --- /dev/null +++ b/include/dt-bindings/power/allwinner,sun20i-d1-ppu.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_POWER_SUN20I_D1_PPU_H_ +#define _DT_BINDINGS_POWER_SUN20I_D1_PPU_H_ + +#define PD_CPU 0 +#define PD_VE 1 +#define PD_DSP 2 + +#endif /* _DT_BINDINGS_POWER_SUN20I_D1_PPU_H_ */ diff --git a/include/dt-bindings/power/mediatek,mt8188-power.h b/include/dt-bindings/power/mediatek,mt8188-power.h new file mode 100644 index 000000000000..57e75cf3aa2c --- /dev/null +++ b/include/dt-bindings/power/mediatek,mt8188-power.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Garmin Chang <garmin.chang@mediatek.com> + */ + +#ifndef _DT_BINDINGS_POWER_MT8188_POWER_H +#define _DT_BINDINGS_POWER_MT8188_POWER_H + +#define MT8188_POWER_DOMAIN_MFG0 0 +#define MT8188_POWER_DOMAIN_MFG1 1 +#define MT8188_POWER_DOMAIN_MFG2 2 +#define MT8188_POWER_DOMAIN_MFG3 3 +#define MT8188_POWER_DOMAIN_MFG4 4 +#define MT8188_POWER_DOMAIN_PEXTP_MAC_P0 5 +#define MT8188_POWER_DOMAIN_PEXTP_PHY_TOP 6 +#define MT8188_POWER_DOMAIN_CSIRX_TOP 7 +#define MT8188_POWER_DOMAIN_ETHER 8 +#define MT8188_POWER_DOMAIN_HDMI_TX 9 +#define MT8188_POWER_DOMAIN_ADSP_AO 10 +#define MT8188_POWER_DOMAIN_ADSP_INFRA 11 +#define MT8188_POWER_DOMAIN_ADSP 12 +#define MT8188_POWER_DOMAIN_AUDIO 13 +#define MT8188_POWER_DOMAIN_AUDIO_ASRC 14 +#define MT8188_POWER_DOMAIN_VPPSYS0 15 +#define MT8188_POWER_DOMAIN_VDOSYS0 16 +#define MT8188_POWER_DOMAIN_VDOSYS1 17 +#define MT8188_POWER_DOMAIN_DP_TX 18 +#define MT8188_POWER_DOMAIN_EDP_TX 19 +#define MT8188_POWER_DOMAIN_VPPSYS1 20 +#define MT8188_POWER_DOMAIN_WPE 21 +#define MT8188_POWER_DOMAIN_VDEC0 22 +#define MT8188_POWER_DOMAIN_VDEC1 23 +#define MT8188_POWER_DOMAIN_VENC 24 +#define MT8188_POWER_DOMAIN_IMG_VCORE 25 +#define MT8188_POWER_DOMAIN_IMG_MAIN 26 +#define MT8188_POWER_DOMAIN_DIP 27 +#define MT8188_POWER_DOMAIN_IPE 28 +#define MT8188_POWER_DOMAIN_CAM_VCORE 29 +#define MT8188_POWER_DOMAIN_CAM_MAIN 30 +#define MT8188_POWER_DOMAIN_CAM_SUBA 31 +#define MT8188_POWER_DOMAIN_CAM_SUBB 32 + +#endif /* _DT_BINDINGS_POWER_MT8188_POWER_H */ diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h index 278de6df425e..1bf8e87ecd7e 100644 --- a/include/dt-bindings/power/qcom-rpmpd.h +++ b/include/dt-bindings/power/qcom-rpmpd.h @@ -4,6 +4,25 @@ #ifndef _DT_BINDINGS_POWER_QCOM_RPMPD_H #define _DT_BINDINGS_POWER_QCOM_RPMPD_H +/* SA8775P Power Domain Indexes */ +#define SA8775P_CX 0 +#define SA8775P_CX_AO 1 +#define SA8775P_DDR 2 +#define SA8775P_EBI 3 +#define SA8775P_GFX 4 +#define SA8775P_LCX 5 +#define SA8775P_LMX 6 +#define SA8775P_MMCX 7 +#define SA8775P_MMCX_AO 8 +#define SA8775P_MSS 9 +#define SA8775P_MX 10 +#define SA8775P_MX_AO 11 +#define SA8775P_MXC 12 +#define SA8775P_MXC_AO 13 +#define SA8775P_NSP0 14 +#define SA8775P_NSP1 15 +#define SA8775P_XO 16 + /* SDM670 Power Domain Indexes */ #define SDM670_MX 0 #define SDM670_MX_AO 1 @@ -192,6 +211,7 @@ #define RPMH_REGULATOR_LEVEL_MIN_SVS 48 #define RPMH_REGULATOR_LEVEL_LOW_SVS_D1 56 #define RPMH_REGULATOR_LEVEL_LOW_SVS 64 +#define RPMH_REGULATOR_LEVEL_LOW_SVS_L1 80 #define RPMH_REGULATOR_LEVEL_SVS 128 #define RPMH_REGULATOR_LEVEL_SVS_L0 144 #define RPMH_REGULATOR_LEVEL_SVS_L1 192 @@ -307,16 +327,6 @@ #define SDM660_SSCMX 8 #define SDM660_SSCMX_VFL 9 -/* SM4250 Power Domains */ -#define SM4250_VDDCX 0 -#define SM4250_VDDCX_AO 1 -#define SM4250_VDDCX_VFL 2 -#define SM4250_VDDMX 3 -#define SM4250_VDDMX_AO 4 -#define SM4250_VDDMX_VFL 5 -#define SM4250_VDD_LPI_CX 6 -#define SM4250_VDD_LPI_MX 7 - /* SM6115 Power Domains */ #define SM6115_VDDCX 0 #define SM6115_VDDCX_AO 1 diff --git a/include/dt-bindings/power/r8a779g0-sysc.h b/include/dt-bindings/power/r8a779g0-sysc.h index 7daa70f1814e..c7b139fb075f 100644 --- a/include/dt-bindings/power/r8a779g0-sysc.h +++ b/include/dt-bindings/power/r8a779g0-sysc.h @@ -38,6 +38,7 @@ #define R8A779G0_PD_A3VIP2 58 #define R8A779G0_PD_A3ISP0 60 #define R8A779G0_PD_A3ISP1 61 +#define R8A779G0_PD_A3DUL 62 /* Always-on power area */ #define R8A779G0_PD_ALWAYS_ON 64 diff --git a/include/dt-bindings/power/starfive,jh7110-pmu.h b/include/dt-bindings/power/starfive,jh7110-pmu.h new file mode 100644 index 000000000000..132bfe401fc8 --- /dev/null +++ b/include/dt-bindings/power/starfive,jh7110-pmu.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Author: Walker Chen <walker.chen@starfivetech.com> + */ +#ifndef __DT_BINDINGS_POWER_JH7110_POWER_H__ +#define __DT_BINDINGS_POWER_JH7110_POWER_H__ + +#define JH7110_PD_SYSTOP 0 +#define JH7110_PD_CPU 1 +#define JH7110_PD_GPUA 2 +#define JH7110_PD_VDEC 3 +#define JH7110_PD_VOUT 4 +#define JH7110_PD_ISP 5 +#define JH7110_PD_VENC 6 + +#endif diff --git a/include/dt-bindings/reset/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h index 24ab3631dcea..e61660438d61 100644 --- a/include/dt-bindings/reset/mt8195-resets.h +++ b/include/dt-bindings/reset/mt8195-resets.h @@ -35,4 +35,49 @@ #define MT8195_INFRA_RST2_PCIE_P1_SWRST 4 #define MT8195_INFRA_RST2_USBSIF_P1_SWRST 5 +/* VDOSYS1 */ +#define MT8195_VDOSYS1_SW0_RST_B_SMI_LARB2 0 +#define MT8195_VDOSYS1_SW0_RST_B_SMI_LARB3 1 +#define MT8195_VDOSYS1_SW0_RST_B_GALS 2 +#define MT8195_VDOSYS1_SW0_RST_B_FAKE_ENG0 3 +#define MT8195_VDOSYS1_SW0_RST_B_FAKE_ENG1 4 +#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA0 5 +#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA1 6 +#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA2 7 +#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA3 8 +#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE0 9 +#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE1 10 +#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE2 11 +#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE3 12 +#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE4 13 +#define MT8195_VDOSYS1_SW0_RST_B_VPP2_TO_VDO1_DL_ASYNC 14 +#define MT8195_VDOSYS1_SW0_RST_B_VPP3_TO_VDO1_DL_ASYNC 15 +#define MT8195_VDOSYS1_SW0_RST_B_DISP_MUTEX 16 +#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA4 17 +#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA5 18 +#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA6 19 +#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA7 20 +#define MT8195_VDOSYS1_SW0_RST_B_DP_INTF0 21 +#define MT8195_VDOSYS1_SW0_RST_B_DPI0 22 +#define MT8195_VDOSYS1_SW0_RST_B_DPI1 23 +#define MT8195_VDOSYS1_SW0_RST_B_DISP_MONITOR 24 +#define MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC 25 +#define MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC 26 +#define MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC 27 +#define MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC 28 +#define MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC 29 +#define MT8195_VDOSYS1_SW0_RST_B_VDO0_DSC_TO_VDO1_DL_ASYNC 30 +#define MT8195_VDOSYS1_SW0_RST_B_VDO0_MERGE_TO_VDO1_DL_ASYNC 31 +#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0 32 +#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0 33 +#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE 34 +#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1 48 +#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1 49 +#define MT8195_VDOSYS1_SW1_RST_B_DISP_MIXER 50 +#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC 51 +#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC 52 +#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC 53 +#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC 54 +#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC 55 + #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */ diff --git a/include/dt-bindings/reset/sun20i-d1-ccu.h b/include/dt-bindings/reset/sun20i-d1-ccu.h index de9ff5203239..f8001cf50bf1 100644 --- a/include/dt-bindings/reset/sun20i-d1-ccu.h +++ b/include/dt-bindings/reset/sun20i-d1-ccu.h @@ -73,5 +73,7 @@ #define RST_BUS_DSP_CFG 63 #define RST_BUS_DSP_DBG 64 #define RST_BUS_RISCV_CFG 65 +#define RST_BUS_CAN0 66 +#define RST_BUS_CAN1 67 #endif /* _DT_BINDINGS_RST_SUN20I_D1_CCU_H_ */ diff --git a/include/kvm/arm_arch_timer.h b/include/kvm/arm_arch_timer.h index cd6d8f260eab..71916de7c6c4 100644 --- a/include/kvm/arm_arch_timer.h +++ b/include/kvm/arm_arch_timer.h @@ -60,7 +60,7 @@ struct arch_timer_cpu { bool enabled; }; -int kvm_timer_hyp_init(bool); +int __init kvm_timer_hyp_init(bool has_gic); int kvm_timer_enable(struct kvm_vcpu *vcpu); int kvm_timer_vcpu_reset(struct kvm_vcpu *vcpu); void kvm_timer_vcpu_init(struct kvm_vcpu *vcpu); @@ -104,4 +104,8 @@ void kvm_arm_timer_write_sysreg(struct kvm_vcpu *vcpu, u32 timer_get_ctl(struct arch_timer_context *ctxt); u64 timer_get_cval(struct arch_timer_context *ctxt); +/* CPU HP callbacks */ +void kvm_timer_cpu_up(void); +void kvm_timer_cpu_down(void); + #endif diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h index 6470f67e63c4..d3ad51fde9db 100644 --- a/include/kvm/arm_vgic.h +++ b/include/kvm/arm_vgic.h @@ -432,4 +432,8 @@ int vgic_v4_load(struct kvm_vcpu *vcpu); void vgic_v4_commit(struct kvm_vcpu *vcpu); int vgic_v4_put(struct kvm_vcpu *vcpu, bool need_db); +/* CPU HP callbacks */ +void kvm_vgic_cpu_up(void); +void kvm_vgic_cpu_down(void); + #endif /* __KVM_ARM_VGIC_H */ diff --git a/include/linux/capability.h b/include/linux/capability.h index 03c2a613ad40..0c356a517991 100644 --- a/include/linux/capability.h +++ b/include/linux/capability.h @@ -15,28 +15,25 @@ #include <uapi/linux/capability.h> #include <linux/uidgid.h> +#include <linux/bits.h> #define _KERNEL_CAPABILITY_VERSION _LINUX_CAPABILITY_VERSION_3 -#define _KERNEL_CAPABILITY_U32S _LINUX_CAPABILITY_U32S_3 extern int file_caps_enabled; -typedef struct kernel_cap_struct { - __u32 cap[_KERNEL_CAPABILITY_U32S]; -} kernel_cap_t; +typedef struct { u64 val; } kernel_cap_t; /* same as vfs_ns_cap_data but in cpu endian and always filled completely */ struct cpu_vfs_cap_data { __u32 magic_etc; + kuid_t rootid; kernel_cap_t permitted; kernel_cap_t inheritable; - kuid_t rootid; }; #define _USER_CAP_HEADER_SIZE (sizeof(struct __user_cap_header_struct)) #define _KERNEL_CAP_T_SIZE (sizeof(kernel_cap_t)) - struct file; struct inode; struct dentry; @@ -44,16 +41,6 @@ struct task_struct; struct user_namespace; struct mnt_idmap; -extern const kernel_cap_t __cap_empty_set; -extern const kernel_cap_t __cap_init_eff_set; - -/* - * Internal kernel functions only - */ - -#define CAP_FOR_EACH_U32(__capi) \ - for (__capi = 0; __capi < _KERNEL_CAPABILITY_U32S; ++__capi) - /* * CAP_FS_MASK and CAP_NFSD_MASKS: * @@ -67,94 +54,52 @@ extern const kernel_cap_t __cap_init_eff_set; * 2. The security.* and trusted.* xattrs are fs-related MAC permissions */ -# define CAP_FS_MASK_B0 (CAP_TO_MASK(CAP_CHOWN) \ - | CAP_TO_MASK(CAP_MKNOD) \ - | CAP_TO_MASK(CAP_DAC_OVERRIDE) \ - | CAP_TO_MASK(CAP_DAC_READ_SEARCH) \ - | CAP_TO_MASK(CAP_FOWNER) \ - | CAP_TO_MASK(CAP_FSETID)) - -# define CAP_FS_MASK_B1 (CAP_TO_MASK(CAP_MAC_OVERRIDE)) +# define CAP_FS_MASK (BIT_ULL(CAP_CHOWN) \ + | BIT_ULL(CAP_MKNOD) \ + | BIT_ULL(CAP_DAC_OVERRIDE) \ + | BIT_ULL(CAP_DAC_READ_SEARCH) \ + | BIT_ULL(CAP_FOWNER) \ + | BIT_ULL(CAP_FSETID) \ + | BIT_ULL(CAP_MAC_OVERRIDE)) +#define CAP_VALID_MASK (BIT_ULL(CAP_LAST_CAP+1)-1) -#if _KERNEL_CAPABILITY_U32S != 2 -# error Fix up hand-coded capability macro initializers -#else /* HAND-CODED capability initializers */ +# define CAP_EMPTY_SET ((kernel_cap_t) { 0 }) +# define CAP_FULL_SET ((kernel_cap_t) { CAP_VALID_MASK }) +# define CAP_FS_SET ((kernel_cap_t) { CAP_FS_MASK | BIT_ULL(CAP_LINUX_IMMUTABLE) }) +# define CAP_NFSD_SET ((kernel_cap_t) { CAP_FS_MASK | BIT_ULL(CAP_SYS_RESOURCE) }) -#define CAP_LAST_U32 ((_KERNEL_CAPABILITY_U32S) - 1) -#define CAP_LAST_U32_VALID_MASK (CAP_TO_MASK(CAP_LAST_CAP + 1) -1) +# define cap_clear(c) do { (c).val = 0; } while (0) -# define CAP_EMPTY_SET ((kernel_cap_t){{ 0, 0 }}) -# define CAP_FULL_SET ((kernel_cap_t){{ ~0, CAP_LAST_U32_VALID_MASK }}) -# define CAP_FS_SET ((kernel_cap_t){{ CAP_FS_MASK_B0 \ - | CAP_TO_MASK(CAP_LINUX_IMMUTABLE), \ - CAP_FS_MASK_B1 } }) -# define CAP_NFSD_SET ((kernel_cap_t){{ CAP_FS_MASK_B0 \ - | CAP_TO_MASK(CAP_SYS_RESOURCE), \ - CAP_FS_MASK_B1 } }) - -#endif /* _KERNEL_CAPABILITY_U32S != 2 */ - -# define cap_clear(c) do { (c) = __cap_empty_set; } while (0) - -#define cap_raise(c, flag) ((c).cap[CAP_TO_INDEX(flag)] |= CAP_TO_MASK(flag)) -#define cap_lower(c, flag) ((c).cap[CAP_TO_INDEX(flag)] &= ~CAP_TO_MASK(flag)) -#define cap_raised(c, flag) ((c).cap[CAP_TO_INDEX(flag)] & CAP_TO_MASK(flag)) - -#define CAP_BOP_ALL(c, a, b, OP) \ -do { \ - unsigned __capi; \ - CAP_FOR_EACH_U32(__capi) { \ - c.cap[__capi] = a.cap[__capi] OP b.cap[__capi]; \ - } \ -} while (0) - -#define CAP_UOP_ALL(c, a, OP) \ -do { \ - unsigned __capi; \ - CAP_FOR_EACH_U32(__capi) { \ - c.cap[__capi] = OP a.cap[__capi]; \ - } \ -} while (0) +#define cap_raise(c, flag) ((c).val |= BIT_ULL(flag)) +#define cap_lower(c, flag) ((c).val &= ~BIT_ULL(flag)) +#define cap_raised(c, flag) (((c).val & BIT_ULL(flag)) != 0) static inline kernel_cap_t cap_combine(const kernel_cap_t a, const kernel_cap_t b) { - kernel_cap_t dest; - CAP_BOP_ALL(dest, a, b, |); - return dest; + return (kernel_cap_t) { a.val | b.val }; } static inline kernel_cap_t cap_intersect(const kernel_cap_t a, const kernel_cap_t b) { - kernel_cap_t dest; - CAP_BOP_ALL(dest, a, b, &); - return dest; + return (kernel_cap_t) { a.val & b.val }; } static inline kernel_cap_t cap_drop(const kernel_cap_t a, const kernel_cap_t drop) { - kernel_cap_t dest; - CAP_BOP_ALL(dest, a, drop, &~); - return dest; + return (kernel_cap_t) { a.val &~ drop.val }; } -static inline kernel_cap_t cap_invert(const kernel_cap_t c) +static inline bool cap_isclear(const kernel_cap_t a) { - kernel_cap_t dest; - CAP_UOP_ALL(dest, c, ~); - return dest; + return !a.val; } -static inline bool cap_isclear(const kernel_cap_t a) +static inline bool cap_isidentical(const kernel_cap_t a, const kernel_cap_t b) { - unsigned __capi; - CAP_FOR_EACH_U32(__capi) { - if (a.cap[__capi] != 0) - return false; - } - return true; + return a.val == b.val; } /* @@ -166,39 +111,31 @@ static inline bool cap_isclear(const kernel_cap_t a) */ static inline bool cap_issubset(const kernel_cap_t a, const kernel_cap_t set) { - kernel_cap_t dest; - dest = cap_drop(a, set); - return cap_isclear(dest); + return !(a.val & ~set.val); } /* Used to decide between falling back on the old suser() or fsuser(). */ static inline kernel_cap_t cap_drop_fs_set(const kernel_cap_t a) { - const kernel_cap_t __cap_fs_set = CAP_FS_SET; - return cap_drop(a, __cap_fs_set); + return cap_drop(a, CAP_FS_SET); } static inline kernel_cap_t cap_raise_fs_set(const kernel_cap_t a, const kernel_cap_t permitted) { - const kernel_cap_t __cap_fs_set = CAP_FS_SET; - return cap_combine(a, - cap_intersect(permitted, __cap_fs_set)); + return cap_combine(a, cap_intersect(permitted, CAP_FS_SET)); } static inline kernel_cap_t cap_drop_nfsd_set(const kernel_cap_t a) { - const kernel_cap_t __cap_fs_set = CAP_NFSD_SET; - return cap_drop(a, __cap_fs_set); + return cap_drop(a, CAP_NFSD_SET); } static inline kernel_cap_t cap_raise_nfsd_set(const kernel_cap_t a, const kernel_cap_t permitted) { - const kernel_cap_t __cap_nfsd_set = CAP_NFSD_SET; - return cap_combine(a, - cap_intersect(permitted, __cap_nfsd_set)); + return cap_combine(a, cap_intersect(permitted, CAP_NFSD_SET)); } #ifdef CONFIG_MULTIUSER diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h index 6c6859bfc454..c6fab004104a 100644 --- a/include/linux/cpuhotplug.h +++ b/include/linux/cpuhotplug.h @@ -187,10 +187,6 @@ enum cpuhp_state { CPUHP_AP_CSKY_TIMER_STARTING, CPUHP_AP_TI_GP_TIMER_STARTING, CPUHP_AP_HYPERV_TIMER_STARTING, - CPUHP_AP_KVM_STARTING, - CPUHP_AP_KVM_ARM_VGIC_INIT_STARTING, - CPUHP_AP_KVM_ARM_VGIC_STARTING, - CPUHP_AP_KVM_ARM_TIMER_STARTING, /* Must be the last timer callback */ CPUHP_AP_DUMMY_TIMER_STARTING, CPUHP_AP_ARM_XEN_STARTING, @@ -205,6 +201,7 @@ enum cpuhp_state { /* Online section invoked on the hotplugged CPU from the hotplug thread */ CPUHP_AP_ONLINE_IDLE, + CPUHP_AP_KVM_ONLINE, CPUHP_AP_SCHED_WAIT_EMPTY, CPUHP_AP_SMPBOOT_THREADS, CPUHP_AP_X86_VDSO_VMA_ONLINE, @@ -221,6 +218,7 @@ enum cpuhp_state { CPUHP_AP_PERF_X86_CQM_ONLINE, CPUHP_AP_PERF_X86_CSTATE_ONLINE, CPUHP_AP_PERF_X86_IDXD_ONLINE, + CPUHP_AP_PERF_X86_IOMMU_PERF_ONLINE, CPUHP_AP_PERF_S390_CF_ONLINE, CPUHP_AP_PERF_S390_SF_ONLINE, CPUHP_AP_PERF_ARM_CCI_ONLINE, diff --git a/include/linux/dax.h b/include/linux/dax.h index 2b5ecb591059..bf6258472e49 100644 --- a/include/linux/dax.h +++ b/include/linux/dax.h @@ -262,11 +262,14 @@ static inline bool dax_mapping(struct address_space *mapping) } #ifdef CONFIG_DEV_DAX_HMEM_DEVICES -void hmem_register_device(int target_nid, struct resource *r); +void hmem_register_resource(int target_nid, struct resource *r); #else -static inline void hmem_register_device(int target_nid, struct resource *r) +static inline void hmem_register_resource(int target_nid, struct resource *r) { } #endif +typedef int (*walk_hmem_fn)(struct device *dev, int target_nid, + const struct resource *res); +int walk_hmem_resources(struct device *dev, walk_hmem_fn fn); #endif diff --git a/include/linux/dma/amd_xdma.h b/include/linux/dma/amd_xdma.h new file mode 100644 index 000000000000..ceba69ed7cb4 --- /dev/null +++ b/include/linux/dma/amd_xdma.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2022, Advanced Micro Devices, Inc. + */ + +#ifndef _DMAENGINE_AMD_XDMA_H +#define _DMAENGINE_AMD_XDMA_H + +#include <linux/interrupt.h> +#include <linux/platform_device.h> + +int xdma_enable_user_irq(struct platform_device *pdev, u32 irq_num); +void xdma_disable_user_irq(struct platform_device *pdev, u32 irq_num); +int xdma_get_user_irq(struct platform_device *pdev, u32 user_irq_index); + +#endif /* _DMAENGINE_AMD_XDMA_H */ diff --git a/include/linux/dma/edma.h b/include/linux/dma/edma.h index 7d8062e9c544..d2638d9259dc 100644 --- a/include/linux/dma/edma.h +++ b/include/linux/dma/edma.h @@ -18,13 +18,31 @@ struct dw_edma; struct dw_edma_region { - phys_addr_t paddr; - void __iomem *vaddr; + u64 paddr; + union { + void *mem; + void __iomem *io; + } vaddr; size_t sz; }; +/** + * struct dw_edma_core_ops - platform-specific eDMA methods + * @irq_vector: Get IRQ number of the passed eDMA channel. Note the + * method accepts the channel id in the end-to-end + * numbering with the eDMA write channels being placed + * first in the row. + * @pci_address: Get PCIe bus address corresponding to the passed CPU + * address. Note there is no need in specifying this + * function if the address translation is performed by + * the DW PCIe RP/EP controller with the DW eDMA device in + * subject and DMA_BYPASS isn't set for all the outbound + * iATU windows. That will be done by the controller + * automatically. + */ struct dw_edma_core_ops { int (*irq_vector)(struct device *dev, unsigned int nr); + u64 (*pci_address)(struct device *dev, phys_addr_t cpu_addr); }; enum dw_edma_map_format { @@ -61,7 +79,6 @@ enum dw_edma_chip_flags { */ struct dw_edma_chip { struct device *dev; - int id; int nr_irqs; const struct dw_edma_core_ops *ops; u32 flags; @@ -84,7 +101,7 @@ struct dw_edma_chip { }; /* Export to the platform drivers */ -#if IS_ENABLED(CONFIG_DW_EDMA) +#if IS_REACHABLE(CONFIG_DW_EDMA) int dw_edma_probe(struct dw_edma_chip *chip); int dw_edma_remove(struct dw_edma_chip *chip); #else diff --git a/include/linux/dma/imx-dma.h b/include/linux/dma/imx-dma.h index f487a4fa103a..cfec5f946e23 100644 --- a/include/linux/dma/imx-dma.h +++ b/include/linux/dma/imx-dma.h @@ -40,6 +40,7 @@ enum sdma_peripheral_type { IMX_DMATYPE_ASRC_SP, /* Shared ASRC */ IMX_DMATYPE_SAI, /* SAI */ IMX_DMATYPE_MULTI_SAI, /* MULTI FIFOs For Audio */ + IMX_DMATYPE_HDMI, /* HDMI Audio */ }; enum imx_dma_prio { diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index c923f4e60f24..c3656e590213 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -394,7 +394,7 @@ enum dma_slave_buswidth { * should be read (RX), if the source is memory this argument is * ignored. * @dst_addr: this is the physical address where DMA slave data - * should be written (TX), if the source is memory this argument + * should be written (TX), if the destination is memory this argument * is ignored. * @src_addr_width: this is the width in bytes of the source (RX) * register where DMA data shall be read. If the source @@ -773,6 +773,7 @@ struct dma_filter { /** * struct dma_device - info on the entity supplying DMA services + * @ref: reference is taken and put every time a channel is allocated or freed * @chancnt: how many DMA channels are supported * @privatecnt: how many DMA channels are requested by dma_request_channel * @channels: the list of struct dma_chan @@ -789,6 +790,7 @@ struct dma_filter { * @dev_id: unique device ID * @dev: struct device reference for dma mapping api * @owner: owner module (automatically set based on the provided dev) + * @chan_ida: unique channel ID * @src_addr_widths: bit mask of src addr widths the device supports * Width is specified in bytes, e.g. for a device supporting * a width of 4 the mask should have BIT(4) set. @@ -802,6 +804,7 @@ struct dma_filter { * @max_sg_burst: max number of SG list entries executed in a single burst * DMA tansaction with no software intervention for reinitialization. * Zero value means unlimited number of entries. + * @descriptor_reuse: a submitted transfer can be resubmitted after completion * @residue_granularity: granularity of the transfer residue reported * by tx_status * @device_alloc_chan_resources: allocate resources and return the @@ -839,7 +842,6 @@ struct dma_filter { * struct with auxiliary transfer status information, otherwise the call * will just return a simple status code * @device_issue_pending: push pending transactions to hardware - * @descriptor_reuse: a submitted transfer can be resubmitted after completion * @device_release: called sometime atfer dma_async_device_unregister() is * called and there are no further references to this structure. This * must be implemented to free resources however many existing drivers @@ -847,6 +849,7 @@ struct dma_filter { * @dbg_summary_show: optional routine to show contents in debugfs; default code * will be used when this is omitted, but custom code can show extra, * controller specific information. + * @dbg_dev_root: the root folder in debugfs for this device */ struct dma_device { struct kref ref; @@ -855,7 +858,7 @@ struct dma_device { struct list_head channels; struct list_head global_node; struct dma_filter filter; - dma_cap_mask_t cap_mask; + dma_cap_mask_t cap_mask; enum dma_desc_metadata_mode desc_metadata_modes; unsigned short max_xor; unsigned short max_pq; @@ -924,10 +927,8 @@ struct dma_device { struct dma_chan *chan, dma_addr_t dst, u64 data, unsigned long flags); - void (*device_caps)(struct dma_chan *chan, - struct dma_slave_caps *caps); - int (*device_config)(struct dma_chan *chan, - struct dma_slave_config *config); + void (*device_caps)(struct dma_chan *chan, struct dma_slave_caps *caps); + int (*device_config)(struct dma_chan *chan, struct dma_slave_config *config); int (*device_pause)(struct dma_chan *chan); int (*device_resume)(struct dma_chan *chan); int (*device_terminate_all)(struct dma_chan *chan); diff --git a/include/linux/dmar.h b/include/linux/dmar.h index d81a51978d01..725d5e6acec0 100644 --- a/include/linux/dmar.h +++ b/include/linux/dmar.h @@ -39,6 +39,7 @@ struct dmar_drhd_unit { struct list_head list; /* list of drhd units */ struct acpi_dmar_header *hdr; /* ACPI header */ u64 reg_base_addr; /* register base address*/ + unsigned long reg_size; /* size of register set */ struct dmar_dev_scope *devices;/* target device array */ int devices_cnt; /* target device count */ u16 segment; /* PCI domain */ diff --git a/include/linux/exportfs.h b/include/linux/exportfs.h index 9f4d4bcbf251..601700fedc91 100644 --- a/include/linux/exportfs.h +++ b/include/linux/exportfs.h @@ -131,7 +131,7 @@ struct fid { u32 parent_block; u32 parent_generation; } udf; - __u32 raw[0]; + DECLARE_FLEX_ARRAY(__u32, raw); }; }; diff --git a/include/linux/f2fs_fs.h b/include/linux/f2fs_fs.h index ee0d75d9a302..1701f25117ea 100644 --- a/include/linux/f2fs_fs.h +++ b/include/linux/f2fs_fs.h @@ -315,7 +315,7 @@ struct f2fs_inode { __u8 i_log_cluster_size; /* log of cluster size */ __le16 i_compress_flag; /* compress flag */ /* 0 bit: chksum flag - * [10,15] bits: compress level + * [8,15] bits: compress level */ __le32 i_extra_end[0]; /* for attribute size calculation */ } __packed; diff --git a/include/linux/qcom_scm.h b/include/linux/firmware/qcom/qcom_scm.h index f8335644a01a..1e449a5d7f5c 100644 --- a/include/linux/qcom_scm.h +++ b/include/linux/firmware/qcom/qcom_scm.h @@ -9,6 +9,8 @@ #include <linux/types.h> #include <linux/cpumask.h> +#include <dt-bindings/firmware/qcom,scm.h> + #define QCOM_SCM_VERSION(major, minor) (((major) << 16) | ((minor) & 0xFF)) #define QCOM_SCM_CPU_PWR_DOWN_L2_ON 0x0 #define QCOM_SCM_CPU_PWR_DOWN_L2_OFF 0x1 @@ -51,10 +53,6 @@ enum qcom_scm_ice_cipher { QCOM_SCM_ICE_CIPHER_AES_256_CBC = 4, }; -#define QCOM_SCM_VMID_HLOS 0x3 -#define QCOM_SCM_VMID_MSS_MSA 0xF -#define QCOM_SCM_VMID_WLAN 0x18 -#define QCOM_SCM_VMID_WLAN_CE 0x19 #define QCOM_SCM_PERM_READ 0x4 #define QCOM_SCM_PERM_WRITE 0x2 #define QCOM_SCM_PERM_EXEC 0x1 diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h index b09f443d3ab9..0e4c70987e6a 100644 --- a/include/linux/firmware/xlnx-zynqmp.h +++ b/include/linux/firmware/xlnx-zynqmp.h @@ -79,6 +79,10 @@ #define EVENT_ERROR_PSM_ERR1 (0x28108000U) #define EVENT_ERROR_PSM_ERR2 (0x2810C000U) +/* ZynqMP SD tap delay tuning */ +#define SD_ITAPDLY 0xFF180314 +#define SD_OTAPDLYSEL 0xFF180318 + enum pm_api_cb_id { PM_INIT_SUSPEND_CB = 30, PM_ACKNOWLEDGE_CB = 31, diff --git a/include/linux/intel-svm.h b/include/linux/intel-svm.h deleted file mode 100644 index f9a0d44f6fdb..000000000000 --- a/include/linux/intel-svm.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright © 2015 Intel Corporation. - * - * Authors: David Woodhouse <David.Woodhouse@intel.com> - */ - -#ifndef __INTEL_SVM_H__ -#define __INTEL_SVM_H__ - -/* Page Request Queue depth */ -#define PRQ_ORDER 4 -#define PRQ_RING_MASK ((0x1000 << PRQ_ORDER) - 0x20) -#define PRQ_DEPTH ((0x1000 << PRQ_ORDER) >> 5) - -#endif /* __INTEL_SVM_H__ */ diff --git a/include/linux/iommu.h b/include/linux/iommu.h index 46e1347bfa22..6595454d4f48 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -120,7 +120,6 @@ static inline bool iommu_is_dma_domain(struct iommu_domain *domain) enum iommu_cap { IOMMU_CAP_CACHE_COHERENCY, /* IOMMU_CACHE is supported */ - IOMMU_CAP_INTR_REMAP, /* IOMMU supports interrupt isolation */ IOMMU_CAP_NOEXEC, /* IOMMU_NOEXEC flag */ IOMMU_CAP_PRE_BOOT_PROTECTION, /* Firmware says it used the IOMMU for DMA protection and we should too */ @@ -228,6 +227,9 @@ struct iommu_iotlb_gather { * @release_device: Remove device from iommu driver handling * @probe_finalize: Do final setup work after the device is added to an IOMMU * group and attached to the groups domain + * @set_platform_dma_ops: Returning control back to the platform DMA ops. This op + * is to support old IOMMU drivers, new drivers should use + * default domains, and the common IOMMU DMA ops. * @device_group: find iommu group for a particular device * @get_resv_regions: Request list of reserved regions for a device * @of_xlate: add OF master IDs to iommu grouping @@ -256,6 +258,7 @@ struct iommu_ops { struct iommu_device *(*probe_device)(struct device *dev); void (*release_device)(struct device *dev); void (*probe_finalize)(struct device *dev); + void (*set_platform_dma_ops)(struct device *dev); struct iommu_group *(*device_group)(struct device *dev); /* Request/Free a list of reserved regions for a device */ @@ -295,7 +298,6 @@ struct iommu_ops { * * EBUSY - device is attached to a domain and cannot be changed * * ENODEV - device specific errors, not able to be attached * * <others> - treated as ENODEV by the caller. Use is discouraged - * @detach_dev: detach an iommu domain from a device * @set_dev_pasid: set an iommu domain to a pasid of device * @map: map a physically contiguous memory region to an iommu domain * @map_pages: map a physically contiguous set of pages of the same size to @@ -316,7 +318,6 @@ struct iommu_ops { */ struct iommu_domain_ops { int (*attach_dev)(struct iommu_domain *domain, struct device *dev); - void (*detach_dev)(struct iommu_domain *domain, struct device *dev); int (*set_dev_pasid)(struct iommu_domain *domain, struct device *dev, ioasid_t pasid); @@ -401,6 +402,7 @@ struct iommu_fault_param { * @iommu_dev: IOMMU device this device is linked to * @priv: IOMMU Driver private data * @max_pasids: number of PASIDs this device can consume + * @attach_deferred: the dma domain attachment is deferred * * TODO: migrate other per device data pointers under iommu_dev_data, e.g. * struct iommu_group *iommu_group; @@ -413,6 +415,7 @@ struct dev_iommu { struct iommu_device *iommu_dev; void *priv; u32 max_pasids; + u32 attach_deferred:1; }; int iommu_device_register(struct iommu_device *iommu, @@ -455,6 +458,7 @@ static inline const struct iommu_ops *dev_iommu_ops(struct device *dev) extern int bus_iommu_probe(struct bus_type *bus); extern bool iommu_present(struct bus_type *bus); extern bool device_iommu_capable(struct device *dev, enum iommu_cap cap); +extern bool iommu_group_has_isolated_msi(struct iommu_group *group); extern struct iommu_domain *iommu_domain_alloc(struct bus_type *bus); extern struct iommu_group *iommu_group_get_by_id(int id); extern void iommu_domain_free(struct iommu_domain *domain); @@ -467,19 +471,15 @@ extern int iommu_sva_unbind_gpasid(struct iommu_domain *domain, extern struct iommu_domain *iommu_get_domain_for_dev(struct device *dev); extern struct iommu_domain *iommu_get_dma_domain(struct device *dev); extern int iommu_map(struct iommu_domain *domain, unsigned long iova, - phys_addr_t paddr, size_t size, int prot); -extern int iommu_map_atomic(struct iommu_domain *domain, unsigned long iova, - phys_addr_t paddr, size_t size, int prot); + phys_addr_t paddr, size_t size, int prot, gfp_t gfp); extern size_t iommu_unmap(struct iommu_domain *domain, unsigned long iova, size_t size); extern size_t iommu_unmap_fast(struct iommu_domain *domain, unsigned long iova, size_t size, struct iommu_iotlb_gather *iotlb_gather); extern ssize_t iommu_map_sg(struct iommu_domain *domain, unsigned long iova, - struct scatterlist *sg, unsigned int nents, int prot); -extern ssize_t iommu_map_sg_atomic(struct iommu_domain *domain, - unsigned long iova, struct scatterlist *sg, - unsigned int nents, int prot); + struct scatterlist *sg, unsigned int nents, + int prot, gfp_t gfp); extern phys_addr_t iommu_iova_to_phys(struct iommu_domain *domain, dma_addr_t iova); extern void iommu_set_fault_handler(struct iommu_domain *domain, iommu_fault_handler_t handler, void *token); @@ -773,14 +773,7 @@ static inline struct iommu_domain *iommu_get_domain_for_dev(struct device *dev) } static inline int iommu_map(struct iommu_domain *domain, unsigned long iova, - phys_addr_t paddr, size_t size, int prot) -{ - return -ENODEV; -} - -static inline int iommu_map_atomic(struct iommu_domain *domain, - unsigned long iova, phys_addr_t paddr, - size_t size, int prot) + phys_addr_t paddr, size_t size, int prot, gfp_t gfp) { return -ENODEV; } @@ -800,14 +793,7 @@ static inline size_t iommu_unmap_fast(struct iommu_domain *domain, static inline ssize_t iommu_map_sg(struct iommu_domain *domain, unsigned long iova, struct scatterlist *sg, - unsigned int nents, int prot) -{ - return -ENODEV; -} - -static inline ssize_t iommu_map_sg_atomic(struct iommu_domain *domain, - unsigned long iova, struct scatterlist *sg, - unsigned int nents, int prot) + unsigned int nents, int prot, gfp_t gfp) { return -ENODEV; } @@ -1118,7 +1104,8 @@ iommu_get_domain_for_dev_pasid(struct device *dev, ioasid_t pasid, static inline size_t iommu_map_sgtable(struct iommu_domain *domain, unsigned long iova, struct sg_table *sgt, int prot) { - return iommu_map_sg(domain, iova, sgt->sgl, sgt->orig_nents, prot); + return iommu_map_sg(domain, iova, sgt->sgl, sgt->orig_nents, prot, + GFP_KERNEL); } #ifdef CONFIG_IOMMU_DEBUGFS diff --git a/include/linux/iommufd.h b/include/linux/iommufd.h index 650d45629647..c0b5b3ac34f1 100644 --- a/include/linux/iommufd.h +++ b/include/linux/iommufd.h @@ -57,7 +57,9 @@ void iommufd_access_unpin_pages(struct iommufd_access *access, unsigned long iova, unsigned long length); int iommufd_access_rw(struct iommufd_access *access, unsigned long iova, void *data, size_t len, unsigned int flags); -int iommufd_vfio_compat_ioas_id(struct iommufd_ctx *ictx, u32 *out_ioas_id); +int iommufd_vfio_compat_ioas_get_id(struct iommufd_ctx *ictx, u32 *out_ioas_id); +int iommufd_vfio_compat_ioas_create(struct iommufd_ctx *ictx); +int iommufd_vfio_compat_set_no_iommu(struct iommufd_ctx *ictx); #else /* !CONFIG_IOMMUFD */ static inline struct iommufd_ctx *iommufd_ctx_from_file(struct file *file) { @@ -89,8 +91,12 @@ static inline int iommufd_access_rw(struct iommufd_access *access, unsigned long return -EOPNOTSUPP; } -static inline int iommufd_vfio_compat_ioas_id(struct iommufd_ctx *ictx, - u32 *out_ioas_id) +static inline int iommufd_vfio_compat_ioas_create(struct iommufd_ctx *ictx) +{ + return -EOPNOTSUPP; +} + +static inline int iommufd_vfio_compat_set_no_iommu(struct iommufd_ctx *ictx) { return -EOPNOTSUPP; } diff --git a/include/linux/irqdomain.h b/include/linux/irqdomain.h index d320d15d4fba..51c254b7fec2 100644 --- a/include/linux/irqdomain.h +++ b/include/linux/irqdomain.h @@ -194,8 +194,10 @@ enum { /* Irq domain implements MSIs */ IRQ_DOMAIN_FLAG_MSI = (1 << 4), - /* Irq domain implements MSI remapping */ - IRQ_DOMAIN_FLAG_MSI_REMAP = (1 << 5), + /* + * Irq domain implements isolated MSI, see msi_device_has_isolated_msi() + */ + IRQ_DOMAIN_FLAG_ISOLATED_MSI = (1 << 5), /* Irq domain doesn't translate anything */ IRQ_DOMAIN_FLAG_NO_MAP = (1 << 6), @@ -278,7 +280,6 @@ struct irq_domain *irq_domain_create_legacy(struct fwnode_handle *fwnode, void *host_data); extern struct irq_domain *irq_find_matching_fwspec(struct irq_fwspec *fwspec, enum irq_domain_bus_token bus_token); -extern bool irq_domain_check_msi_remap(void); extern void irq_set_default_host(struct irq_domain *host); extern struct irq_domain *irq_get_default_host(void); extern int irq_domain_alloc_descs(int virq, unsigned int nr_irqs, @@ -561,13 +562,6 @@ static inline bool irq_domain_is_msi(struct irq_domain *domain) return domain->flags & IRQ_DOMAIN_FLAG_MSI; } -static inline bool irq_domain_is_msi_remap(struct irq_domain *domain) -{ - return domain->flags & IRQ_DOMAIN_FLAG_MSI_REMAP; -} - -extern bool irq_domain_hierarchical_is_msi_remap(struct irq_domain *domain); - static inline bool irq_domain_is_msi_parent(struct irq_domain *domain) { return domain->flags & IRQ_DOMAIN_FLAG_MSI_PARENT; @@ -613,17 +607,6 @@ static inline bool irq_domain_is_msi(struct irq_domain *domain) return false; } -static inline bool irq_domain_is_msi_remap(struct irq_domain *domain) -{ - return false; -} - -static inline bool -irq_domain_hierarchical_is_msi_remap(struct irq_domain *domain) -{ - return false; -} - static inline bool irq_domain_is_msi_parent(struct irq_domain *domain) { return false; @@ -643,10 +626,6 @@ static inline struct irq_domain *irq_find_matching_fwnode( { return NULL; } -static inline bool irq_domain_check_msi_remap(void) -{ - return false; -} #endif /* !CONFIG_IRQ_DOMAIN */ #endif /* _LINUX_IRQDOMAIN_H */ diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h index 4f26b244f6d0..8ada23756b0e 100644 --- a/include/linux/kvm_host.h +++ b/include/linux/kvm_host.h @@ -324,7 +324,7 @@ struct kvm_vcpu { #endif int cpu; int vcpu_id; /* id given by userspace at creation */ - int vcpu_idx; /* index in kvm->vcpus array */ + int vcpu_idx; /* index into kvm->vcpu_array */ int ____srcu_idx; /* Don't use this directly. You've been warned. */ #ifdef CONFIG_PROVE_RCU int srcu_depth; @@ -956,8 +956,7 @@ static inline void kvm_irqfd_exit(void) { } #endif -int kvm_init(void *opaque, unsigned vcpu_size, unsigned vcpu_align, - struct module *module); +int kvm_init(unsigned vcpu_size, unsigned vcpu_align, struct module *module); void kvm_exit(void); void kvm_get_kvm(struct kvm *kvm); @@ -1354,7 +1353,7 @@ void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu); bool kvm_vcpu_wake_up(struct kvm_vcpu *vcpu); void kvm_vcpu_kick(struct kvm_vcpu *vcpu); int kvm_vcpu_yield_to(struct kvm_vcpu *target); -void kvm_vcpu_on_spin(struct kvm_vcpu *vcpu, bool usermode_vcpu_not_eligible); +void kvm_vcpu_on_spin(struct kvm_vcpu *vcpu, bool yield_to_kernel_mode); void kvm_flush_remote_tlbs(struct kvm *kvm); @@ -1423,9 +1422,6 @@ int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg); int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu); -int kvm_arch_init(void *opaque); -void kvm_arch_exit(void); - void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu); void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu); @@ -1445,11 +1441,10 @@ void kvm_arch_create_vcpu_debugfs(struct kvm_vcpu *vcpu, struct dentry *debugfs_ static inline void kvm_create_vcpu_debugfs(struct kvm_vcpu *vcpu) {} #endif +#ifdef CONFIG_KVM_GENERIC_HARDWARE_ENABLING int kvm_arch_hardware_enable(void); void kvm_arch_hardware_disable(void); -int kvm_arch_hardware_setup(void *opaque); -void kvm_arch_hardware_unsetup(void); -int kvm_arch_check_processor_compat(void *opaque); +#endif int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu); bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu); int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu); @@ -1466,7 +1461,7 @@ int kvm_arch_create_vm_debugfs(struct kvm *kvm); */ static inline struct kvm *kvm_arch_alloc_vm(void) { - return kzalloc(sizeof(struct kvm), GFP_KERNEL); + return kzalloc(sizeof(struct kvm), GFP_KERNEL_ACCOUNT); } #endif @@ -2081,7 +2076,9 @@ static inline bool kvm_check_request(int req, struct kvm_vcpu *vcpu) } } +#ifdef CONFIG_KVM_GENERIC_HARDWARE_ENABLING extern bool kvm_rebooting; +#endif extern unsigned int halt_poll_ns; extern unsigned int halt_poll_ns_grow; diff --git a/include/linux/kvm_types.h b/include/linux/kvm_types.h index 76de36e56cdf..2728d49bbdf6 100644 --- a/include/linux/kvm_types.h +++ b/include/linux/kvm_types.h @@ -40,7 +40,7 @@ typedef unsigned long gva_t; typedef u64 gpa_t; typedef u64 gfn_t; -#define GPA_INVALID (~(gpa_t)0) +#define INVALID_GPA (~(gpa_t)0) typedef unsigned long hva_t; typedef u64 hpa_t; diff --git a/include/linux/libnvdimm.h b/include/linux/libnvdimm.h index af38252ad704..e772aae71843 100644 --- a/include/linux/libnvdimm.h +++ b/include/linux/libnvdimm.h @@ -41,6 +41,9 @@ enum { */ NDD_INCOHERENT = 7, + /* dimm provider wants synchronous registration by __nvdimm_create() */ + NDD_REGISTER_SYNC = 8, + /* need to set a limit somewhere, but yes, this is likely overkill */ ND_IOCTL_MAX_BUFLEN = SZ_4M, ND_CMD_MAX_ELEM = 5, diff --git a/include/linux/mdio/mdio-mscc-miim.h b/include/linux/mdio/mdio-mscc-miim.h index 5b4ed2c3cbb9..1ce699740af6 100644 --- a/include/linux/mdio/mdio-mscc-miim.h +++ b/include/linux/mdio/mdio-mscc-miim.h @@ -14,6 +14,6 @@ int mscc_miim_setup(struct device *device, struct mii_bus **bus, const char *name, struct regmap *mii_regmap, - int status_offset); + int status_offset, bool ignore_read_errors); #endif diff --git a/include/linux/memregion.h b/include/linux/memregion.h index bf83363807ac..c01321467789 100644 --- a/include/linux/memregion.h +++ b/include/linux/memregion.h @@ -3,10 +3,12 @@ #define _MEMREGION_H_ #include <linux/types.h> #include <linux/errno.h> +#include <linux/range.h> #include <linux/bug.h> struct memregion_info { int target_node; + struct range range; }; #ifdef CONFIG_MEMREGION diff --git a/include/linux/memremap.h b/include/linux/memremap.h index 7fcaf3180a5b..1314d9c5f05b 100644 --- a/include/linux/memremap.h +++ b/include/linux/memremap.h @@ -135,7 +135,7 @@ struct dev_pagemap { int nr_range; union { struct range range; - struct range ranges[0]; + DECLARE_FLEX_ARRAY(struct range, ranges); }; }; diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h index d4b5e527a7a3..09c6b3184bb0 100644 --- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h @@ -451,8 +451,10 @@ #define IMX6SX_GPR12_PCIE_RX_EQ_2 (0x2 << 0) /* For imx6ul iomux gpr register field define */ -#define IMX6UL_GPR1_ENET1_CLK_DIR (0x1 << 17) -#define IMX6UL_GPR1_ENET2_CLK_DIR (0x1 << 18) +#define IMX6UL_GPR1_ENET2_TX_CLK_DIR BIT(18) +#define IMX6UL_GPR1_ENET1_TX_CLK_DIR BIT(17) +#define IMX6UL_GPR1_ENET2_CLK_SEL BIT(14) +#define IMX6UL_GPR1_ENET1_CLK_SEL BIT(13) #define IMX6UL_GPR1_ENET1_CLK_OUTPUT (0x1 << 17) #define IMX6UL_GPR1_ENET2_CLK_OUTPUT (0x1 << 18) #define IMX6UL_GPR1_ENET_CLK_DIR (0x3 << 17) diff --git a/include/linux/mlx4/qp.h b/include/linux/mlx4/qp.h index b6b626157b03..b9a7b1319f5d 100644 --- a/include/linux/mlx4/qp.h +++ b/include/linux/mlx4/qp.h @@ -504,4 +504,5 @@ static inline u16 folded_qp(u32 q) u16 mlx4_qp_roce_entropy(struct mlx4_dev *dev, u32 qpn); +void mlx4_put_qp(struct mlx4_qp *qp); #endif /* MLX4_QP_H */ diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h index a170c8565779..f33389b42209 100644 --- a/include/linux/mlx5/driver.h +++ b/include/linux/mlx5/driver.h @@ -742,7 +742,6 @@ enum { enum { MKEY_CACHE_LAST_STD_ENTRY = 20, - MLX5_IMR_MTT_CACHE_ENTRY, MLX5_IMR_KSM_CACHE_ENTRY, MAX_MKEY_CACHE_ENTRIES }; diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index 5ad5126615a1..66d76e97a087 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -1510,7 +1510,9 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 relaxed_ordering_write[0x1]; u8 relaxed_ordering_read[0x1]; u8 log_max_mkey[0x6]; - u8 reserved_at_f0[0x8]; + u8 reserved_at_f0[0x6]; + u8 terminate_scatter_list_mkey[0x1]; + u8 repeated_mkey[0x1]; u8 dump_fill_mkey[0x1]; u8 reserved_at_f9[0x2]; u8 fast_teardown[0x1]; @@ -2183,6 +2185,17 @@ struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { u8 reserved_at_360[0x4a0]; }; +struct mlx5_ifc_cong_control_r_roce_general_bits { + u8 reserved_at_0[0x80]; + + u8 reserved_at_80[0x10]; + u8 rtt_resp_dscp_valid[0x1]; + u8 reserved_at_91[0x9]; + u8 rtt_resp_dscp[0x6]; + + u8 reserved_at_a0[0x760]; +}; + struct mlx5_ifc_cong_control_802_1qau_rp_bits { u8 reserved_at_0[0x80]; @@ -4353,6 +4366,7 @@ union mlx5_ifc_cong_control_roce_ecn_auto_bits { struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; + struct mlx5_ifc_cong_control_r_roce_general_bits cong_control_r_roce_general; u8 reserved_at_0[0x800]; }; @@ -5261,7 +5275,11 @@ struct mlx5_ifc_query_special_contexts_out_bits { u8 null_mkey[0x20]; - u8 reserved_at_a0[0x60]; + u8 terminate_scatter_list_mkey[0x20]; + + u8 repeated_mkey[0x20]; + + u8 reserved_at_a0[0x20]; }; struct mlx5_ifc_query_special_contexts_in_bits { diff --git a/include/linux/mlx5/qp.h b/include/linux/mlx5/qp.h index 4657d5c54abe..df55fbb65717 100644 --- a/include/linux/mlx5/qp.h +++ b/include/linux/mlx5/qp.h @@ -36,7 +36,7 @@ #include <linux/mlx5/device.h> #include <linux/mlx5/driver.h> -#define MLX5_INVALID_LKEY 0x100 +#define MLX5_TERMINATE_SCATTER_LIST_LKEY cpu_to_be32(0x100) /* UMR (3 WQE_BB's) + SIG (3 WQE_BB's) + PSV (mem) + PSV (wire) */ #define MLX5_SIG_WQE_SIZE (MLX5_SEND_WQE_BB * 8) #define MLX5_DIF_SIZE 8 diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h index 8fdd3cf971a3..812e6b583b25 100644 --- a/include/linux/mmc/host.h +++ b/include/linux/mmc/host.h @@ -527,6 +527,7 @@ struct mmc_host { struct device_node; struct mmc_host *mmc_alloc_host(int extra, struct device *); +struct mmc_host *devm_mmc_alloc_host(struct device *dev, int extra); int mmc_add_host(struct mmc_host *); void mmc_remove_host(struct mmc_host *); void mmc_free_host(struct mmc_host *); diff --git a/include/linux/mmc/slot-gpio.h b/include/linux/mmc/slot-gpio.h index 4ae2f2908f99..5d3d15e97868 100644 --- a/include/linux/mmc/slot-gpio.h +++ b/include/linux/mmc/slot-gpio.h @@ -15,6 +15,7 @@ struct mmc_host; int mmc_gpio_get_ro(struct mmc_host *host); int mmc_gpio_get_cd(struct mmc_host *host); +void mmc_gpio_set_cd_irq(struct mmc_host *host, int irq); int mmc_gpiod_request_cd(struct mmc_host *host, const char *con_id, unsigned int idx, bool override_active_level, unsigned int debounce); diff --git a/include/linux/mount.h b/include/linux/mount.h index 52f452b2259a..1ea326c368f7 100644 --- a/include/linux/mount.h +++ b/include/linux/mount.h @@ -86,6 +86,7 @@ extern void mnt_drop_write(struct vfsmount *mnt); extern void mnt_drop_write_file(struct file *file); extern void mntput(struct vfsmount *mnt); extern struct vfsmount *mntget(struct vfsmount *mnt); +extern void mnt_make_shortterm(struct vfsmount *mnt); extern struct vfsmount *mnt_clone_internal(const struct path *path); extern bool __mnt_is_readonly(struct vfsmount *mnt); extern bool mnt_may_suid(struct vfsmount *mnt); diff --git a/include/linux/msi.h b/include/linux/msi.h index a112b913fff9..13c9b74a4575 100644 --- a/include/linux/msi.h +++ b/include/linux/msi.h @@ -48,6 +48,10 @@ typedef struct arch_msi_msg_data { } __attribute__ ((packed)) arch_msi_msg_data_t; #endif +#ifndef arch_is_isolated_msi +#define arch_is_isolated_msi() false +#endif + /** * msi_msg - Representation of a MSI message * @address_lo: Low 32 bits of msi message address @@ -649,6 +653,19 @@ int platform_msi_device_domain_alloc(struct irq_domain *domain, unsigned int vir void platform_msi_device_domain_free(struct irq_domain *domain, unsigned int virq, unsigned int nvec); void *platform_msi_get_host_data(struct irq_domain *domain); + +bool msi_device_has_isolated_msi(struct device *dev); +#else /* CONFIG_GENERIC_MSI_IRQ */ +static inline bool msi_device_has_isolated_msi(struct device *dev) +{ + /* + * Arguably if the platform does not enable MSI support then it has + * "isolated MSI", as an interrupt controller that cannot receive MSIs + * is inherently isolated by our definition. The default definition for + * arch_is_isolated_msi() is conservative and returns false anyhow. + */ + return arch_is_isolated_msi(); +} #endif /* CONFIG_GENERIC_MSI_IRQ */ /* PCI specific interfaces */ diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index dcf90144d70b..f8d4be9c587a 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -67,6 +67,8 @@ struct gpio_desc; /* Extended commands for large page devices */ #define NAND_CMD_READSTART 0x30 +#define NAND_CMD_READCACHESEQ 0x31 +#define NAND_CMD_READCACHEEND 0x3f #define NAND_CMD_RNDOUTSTART 0xE0 #define NAND_CMD_CACHEDPROG 0x15 @@ -1094,10 +1096,20 @@ struct nand_controller_ops { * * @lock: lock used to serialize accesses to the NAND controller * @ops: NAND controller operations. + * @supported_op: NAND controller known-to-be-supported operations, + * only writable by the core after initial checking. + * @supported_op.data_only_read: The controller supports reading more data from + * the bus without restarting an entire read operation nor + * changing the column. + * @supported_op.cont_read: The controller supports sequential cache reads. */ struct nand_controller { struct mutex lock; const struct nand_controller_ops *ops; + struct { + unsigned int data_only_read: 1; + unsigned int cont_read: 1; + } supported_op; }; static inline void nand_controller_init(struct nand_controller *nfc) @@ -1248,6 +1260,10 @@ struct nand_secure_region { * @read_retries: The number of read retry modes supported * @secure_regions: Structure containing the secure regions info * @nr_secure_regions: Number of secure regions + * @cont_read: Sequential page read internals + * @cont_read.ongoing: Whether a continuous read is ongoing or not + * @cont_read.first_page: Start of the continuous read operation + * @cont_read.last_page: End of the continuous read operation * @controller: The hardware controller structure which is shared among multiple * independent devices * @ecc: The ECC controller structure @@ -1300,6 +1316,11 @@ struct nand_chip { int read_retries; struct nand_secure_region *secure_regions; u8 nr_secure_regions; + struct { + bool ongoing; + unsigned int first_page; + unsigned int last_page; + } cont_read; /* Externals */ struct nand_controller *controller; diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index 6d3392a7edc6..01be9f0f008a 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -260,6 +260,7 @@ struct spinand_manufacturer { }; /* SPI NAND manufacturers */ +extern const struct spinand_manufacturer alliancememory_spinand_manufacturer; extern const struct spinand_manufacturer ato_spinand_manufacturer; extern const struct spinand_manufacturer gigadevice_spinand_manufacturer; extern const struct spinand_manufacturer macronix_spinand_manufacturer; diff --git a/include/linux/mtd/ubi.h b/include/linux/mtd/ubi.h index 7d48ea368c5e..a529347fd75b 100644 --- a/include/linux/mtd/ubi.h +++ b/include/linux/mtd/ubi.h @@ -110,6 +110,7 @@ struct ubi_volume_info { int name_len; const char *name; dev_t cdev; + struct device *dev; }; /** diff --git a/include/linux/netfilter.h b/include/linux/netfilter.h index 6863e271a9de..c8e03bcaecaa 100644 --- a/include/linux/netfilter.h +++ b/include/linux/netfilter.h @@ -491,4 +491,9 @@ extern const struct nfnl_ct_hook __rcu *nfnl_ct_hook; */ DECLARE_PER_CPU(bool, nf_skb_duplicated); +/** + * Contains bitmask of ctnetlink event subscribers, if any. + * Can't be pernet due to NETLINK_LISTEN_ALL_NSID setsockopt flag. + */ +extern u8 nf_ctnetlink_has_listener; #endif /*__LINUX_NETFILTER_H*/ diff --git a/include/linux/of.h b/include/linux/of.h index 98c252d2d851..0af611307db2 100644 --- a/include/linux/of.h +++ b/include/linux/of.h @@ -100,8 +100,19 @@ struct of_reconfig_data { struct property *old_prop; }; +/** + * of_node_init - initialize a devicetree node + * @node: Pointer to device node that has been created by kzalloc() + * @phandle_name: Name of property holding a phandle value + * + * On return the device_node refcount is set to one. Use of_node_put() + * on @node when done to free the memory allocated for it. If the node + * is NOT a dynamic node the memory will not be freed. The decision of + * whether to free the memory will be done by node->release(), which is + * of_node_release(). + */ /* initialize a node */ -extern struct kobj_type of_node_ktype; +extern const struct kobj_type of_node_ktype; extern const struct fwnode_operations of_fwnode_ops; static inline void of_node_init(struct device_node *node) { @@ -1180,7 +1191,8 @@ static inline int of_property_read_string_index(const struct device_node *np, * @np: device node from which the property value is to be read. * @propname: name of the property to be searched. * - * Search for a property in a device node. + * Search for a boolean property in a device node. Usage on non-boolean + * property types is deprecated. * * Return: true if the property exists false otherwise. */ @@ -1193,6 +1205,20 @@ static inline bool of_property_read_bool(const struct device_node *np, } /** + * of_property_present - Test if a property is present in a node + * @np: device node to search for the property. + * @propname: name of the property to be searched. + * + * Test for a property present in a device node. + * + * Return: true if the property exists false otherwise. + */ +static inline bool of_property_present(const struct device_node *np, const char *propname) +{ + return of_property_read_bool(np, propname); +} + +/** * of_property_read_u8_array - Find and read an array of u8 from a property. * * @np: device node from which the property value is to be read. diff --git a/include/linux/of_address.h b/include/linux/of_address.h index 265f26eeaf6b..376671594746 100644 --- a/include/linux/of_address.h +++ b/include/linux/of_address.h @@ -38,6 +38,8 @@ struct of_pci_range { /* Translate a DMA address from device space to CPU space */ extern u64 of_translate_dma_address(struct device_node *dev, const __be32 *in_addr); +extern const __be32 *of_translate_dma_region(struct device_node *dev, const __be32 *addr, + phys_addr_t *start, size_t *length); #ifdef CONFIG_OF_ADDRESS extern u64 of_translate_address(struct device_node *np, const __be32 *addr); diff --git a/include/linux/of_iommu.h b/include/linux/of_iommu.h index 55c1eb300a86..9a5e6b410dd2 100644 --- a/include/linux/of_iommu.h +++ b/include/linux/of_iommu.h @@ -12,6 +12,9 @@ extern const struct iommu_ops *of_iommu_configure(struct device *dev, struct device_node *master_np, const u32 *id); +extern void of_iommu_get_resv_regions(struct device *dev, + struct list_head *list); + #else static inline const struct iommu_ops *of_iommu_configure(struct device *dev, @@ -21,6 +24,11 @@ static inline const struct iommu_ops *of_iommu_configure(struct device *dev, return NULL; } +static inline void of_iommu_get_resv_regions(struct device *dev, + struct list_head *list) +{ +} + #endif /* CONFIG_OF_IOMMU */ #endif /* __OF_IOMMU_H */ diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index a48778e1a4ee..301bb0e53707 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -122,6 +122,7 @@ struct pci_epc_mem { * struct pci_epc - represents the PCI EPC device * @dev: PCI EPC device * @pci_epf: list of endpoint functions present in this EPC device + * list_lock: Mutex for protecting pci_epf list * @ops: function pointers for performing endpoint operations * @windows: array of address space of the endpoint controller * @mem: first window of the endpoint controller, which corresponds to @@ -134,11 +135,11 @@ struct pci_epc_mem { * @group: configfs group representing the PCI EPC device * @lock: mutex to protect pci_epc ops * @function_num_map: bitmap to manage physical function number - * @notifier: used to notify EPF of any EPC events (like linkup) */ struct pci_epc { struct device dev; struct list_head pci_epf; + struct mutex list_lock; const struct pci_epc_ops *ops; struct pci_epc_mem **windows; struct pci_epc_mem *mem; @@ -149,7 +150,6 @@ struct pci_epc { /* mutex to protect against concurrent access of EP controller */ struct mutex lock; unsigned long function_num_map; - struct atomic_notifier_head notifier; }; /** @@ -192,12 +192,6 @@ static inline void *epc_get_drvdata(struct pci_epc *epc) return dev_get_drvdata(&epc->dev); } -static inline int -pci_epc_register_notifier(struct pci_epc *epc, struct notifier_block *nb) -{ - return atomic_notifier_chain_register(&epc->notifier, nb); -} - struct pci_epc * __devm_pci_epc_create(struct device *dev, const struct pci_epc_ops *ops, struct module *owner); diff --git a/include/linux/pci-epf.h b/include/linux/pci-epf.h index 009a07147c61..a215dc8ce693 100644 --- a/include/linux/pci-epf.h +++ b/include/linux/pci-epf.h @@ -17,11 +17,6 @@ struct pci_epf; enum pci_epc_interface_type; -enum pci_notify_event { - CORE_INIT, - LINK_UP, -}; - enum pci_barno { NO_BAR = -1, BAR_0, @@ -73,6 +68,16 @@ struct pci_epf_ops { }; /** + * struct pci_epf_event_ops - Callbacks for capturing the EPC events + * @core_init: Callback for the EPC initialization complete event + * @link_up: Callback for the EPC link up event + */ +struct pci_epc_event_ops { + int (*core_init)(struct pci_epf *epf); + int (*link_up)(struct pci_epf *epf); +}; + +/** * struct pci_epf_driver - represents the PCI EPF driver * @probe: ops to perform when a new EPF device has been bound to the EPF driver * @remove: ops to perform when the binding between the EPF device and EPF @@ -127,7 +132,6 @@ struct pci_epf_bar { * @epf_pf: the physical EPF device to which this virtual EPF device is bound * @driver: the EPF driver to which this EPF device is bound * @list: to add pci_epf as a list of PCI endpoint functions to pci_epc - * @nb: notifier block to notify EPF of any EPC events (like linkup) * @lock: mutex to protect pci_epf_ops * @sec_epc: the secondary EPC device to which this EPF device is bound * @sec_epc_list: to add pci_epf as list of PCI endpoint functions to secondary @@ -139,6 +143,7 @@ struct pci_epf_bar { * @is_vf: true - virtual function, false - physical function * @vfunction_num_map: bitmap to manage virtual function number * @pci_vepf: list of virtual endpoint functions associated with this function + * @event_ops: Callbacks for capturing the EPC events */ struct pci_epf { struct device dev; @@ -154,7 +159,6 @@ struct pci_epf { struct pci_epf *epf_pf; struct pci_epf_driver *driver; struct list_head list; - struct notifier_block nb; /* mutex to protect against concurrent access of pci_epf_ops */ struct mutex lock; @@ -168,6 +172,7 @@ struct pci_epf { unsigned int is_vf; unsigned long vfunction_num_map; struct list_head pci_vepf; + const struct pci_epc_event_ops *event_ops; }; /** diff --git a/include/linux/pci.h b/include/linux/pci.h index 254c8a4126a8..fafd8020c6d7 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -572,12 +572,14 @@ struct pci_host_bridge { void *release_data; unsigned int ignore_reset_delay:1; /* For entire hierarchy */ unsigned int no_ext_tags:1; /* No Extended Tags */ + unsigned int no_inc_mrrs:1; /* No Increase MRRS */ unsigned int native_aer:1; /* OS may use PCIe AER */ unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */ unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */ unsigned int native_pme:1; /* OS may use PCIe PME */ unsigned int native_ltr:1; /* OS may use PCIe LTR */ unsigned int native_dpc:1; /* OS may use PCIe DPC */ + unsigned int native_cxl_error:1; /* OS may use CXL RAS/Events */ unsigned int preserve_config:1; /* Preserve FW resource setup */ unsigned int size_windows:1; /* Enable root bus sizing */ unsigned int msi_domain:1; /* Bridge wants MSI domain */ @@ -1697,10 +1699,15 @@ extern bool pcie_ports_native; #define PCIE_LINK_STATE_L1_2 BIT(4) #define PCIE_LINK_STATE_L1_1_PCIPM BIT(5) #define PCIE_LINK_STATE_L1_2_PCIPM BIT(6) +#define PCIE_LINK_STATE_ALL (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |\ + PCIE_LINK_STATE_CLKPM | PCIE_LINK_STATE_L1_1 |\ + PCIE_LINK_STATE_L1_2 | PCIE_LINK_STATE_L1_1_PCIPM |\ + PCIE_LINK_STATE_L1_2_PCIPM) #ifdef CONFIG_PCIEASPM int pci_disable_link_state(struct pci_dev *pdev, int state); int pci_disable_link_state_locked(struct pci_dev *pdev, int state); +int pci_enable_link_state(struct pci_dev *pdev, int state); void pcie_no_aspm(void); bool pcie_aspm_support_enabled(void); bool pcie_aspm_enabled(struct pci_dev *pdev); @@ -1709,6 +1716,8 @@ static inline int pci_disable_link_state(struct pci_dev *pdev, int state) { return 0; } static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state) { return 0; } +static inline int pci_enable_link_state(struct pci_dev *pdev, int state) +{ return 0; } static inline void pcie_no_aspm(void) { } static inline bool pcie_aspm_support_enabled(void) { return false; } static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; } diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index b362d90eb9b0..45c3d62e616d 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -3012,6 +3012,8 @@ #define PCI_DEVICE_ID_INTEL_VMD_9A0B 0x9a0b #define PCI_DEVICE_ID_INTEL_S21152BB 0xb152 +#define PCI_VENDOR_ID_WANGXUN 0x8088 + #define PCI_VENDOR_ID_SCALEMP 0x8686 #define PCI_DEVICE_ID_SCALEMP_VSMP_CTL 0x1010 @@ -3092,6 +3094,8 @@ #define PCI_VENDOR_ID_3COM_2 0xa727 +#define PCI_VENDOR_ID_SOLIDRUN 0xd063 + #define PCI_VENDOR_ID_DIGIUM 0xd161 #define PCI_DEVICE_ID_DIGIUM_HFC4S 0xb410 diff --git a/include/linux/perf/riscv_pmu.h b/include/linux/perf/riscv_pmu.h index e17e86ad6f3a..43fc892aa7d9 100644 --- a/include/linux/perf/riscv_pmu.h +++ b/include/linux/perf/riscv_pmu.h @@ -26,6 +26,8 @@ #define RISCV_PMU_STOP_FLAG_RESET 1 +#define RISCV_PMU_CONFIG1_GUEST_EVENTS 0x1 + struct cpu_hw_events { /* currently enabled events */ int n_events; @@ -73,6 +75,9 @@ void riscv_pmu_legacy_skip_init(void); static inline void riscv_pmu_legacy_skip_init(void) {}; #endif struct riscv_pmu *riscv_pmu_alloc(void); +#ifdef CONFIG_RISCV_PMU_SBI +int riscv_pmu_get_hpm_info(u32 *hw_ctr_width, u32 *num_hw_ctr); +#endif #endif /* CONFIG_RISCV_PMU */ diff --git a/include/linux/phy.h b/include/linux/phy.h index 727bff531a14..36bf0bbc8efa 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -575,6 +575,8 @@ struct macsec_ops; * @advertising: Currently advertised linkmodes * @adv_old: Saved advertised while power saving for WoL * @supported_eee: supported PHY EEE linkmodes + * @advertising_eee: Currently advertised EEE linkmodes + * @eee_enabled: Flag indicating whether the EEE feature is enabled * @lp_advertising: Current link partner advertised linkmodes * @host_interfaces: PHY interface modes supported by host * @eee_broken_modes: Energy efficient ethernet modes which should be prohibited @@ -681,6 +683,8 @@ struct phy_device { __ETHTOOL_DECLARE_LINK_MODE_MASK(adv_old); /* used for eee validation */ __ETHTOOL_DECLARE_LINK_MODE_MASK(supported_eee); + __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising_eee); + bool eee_enabled; /* Host supported PHY interface types. Should be ignored if empty. */ DECLARE_PHY_INTERFACE_MASK(host_interfaces); @@ -1765,6 +1769,8 @@ int genphy_c45_ethtool_get_eee(struct phy_device *phydev, int genphy_c45_ethtool_set_eee(struct phy_device *phydev, struct ethtool_eee *data); int genphy_c45_write_eee_adv(struct phy_device *phydev, unsigned long *adv); +int genphy_c45_an_config_eee_aneg(struct phy_device *phydev); +int genphy_c45_read_eee_adv(struct phy_device *phydev, unsigned long *adv); /* Generic C45 PHY driver */ extern struct phy_driver genphy_c45_driver; diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h index b1413757fcc3..3a570bc59fc7 100644 --- a/include/linux/phy/phy.h +++ b/include/linux/phy/phy.h @@ -250,11 +250,12 @@ static inline void phy_set_bus_width(struct phy *phy, int bus_width) phy->attrs.bus_width = bus_width; } struct phy *phy_get(struct device *dev, const char *string); -struct phy *phy_optional_get(struct device *dev, const char *string); struct phy *devm_phy_get(struct device *dev, const char *string); struct phy *devm_phy_optional_get(struct device *dev, const char *string); struct phy *devm_of_phy_get(struct device *dev, struct device_node *np, const char *con_id); +struct phy *devm_of_phy_optional_get(struct device *dev, struct device_node *np, + const char *con_id); struct phy *devm_of_phy_get_by_index(struct device *dev, struct device_node *np, int index); void of_phy_put(struct phy *phy); @@ -426,12 +427,6 @@ static inline struct phy *phy_get(struct device *dev, const char *string) return ERR_PTR(-ENOSYS); } -static inline struct phy *phy_optional_get(struct device *dev, - const char *string) -{ - return ERR_PTR(-ENOSYS); -} - static inline struct phy *devm_phy_get(struct device *dev, const char *string) { return ERR_PTR(-ENOSYS); @@ -450,6 +445,13 @@ static inline struct phy *devm_of_phy_get(struct device *dev, return ERR_PTR(-ENOSYS); } +static inline struct phy *devm_of_phy_optional_get(struct device *dev, + struct device_node *np, + const char *con_id) +{ + return NULL; +} + static inline struct phy *devm_of_phy_get_by_index(struct device *dev, struct device_node *np, int index) diff --git a/include/linux/pinctrl/devinfo.h b/include/linux/pinctrl/devinfo.h index 9e8b559e1253..bb6653af4f92 100644 --- a/include/linux/pinctrl/devinfo.h +++ b/include/linux/pinctrl/devinfo.h @@ -18,6 +18,8 @@ struct device; #ifdef CONFIG_PINCTRL +#include <linux/device.h> + /* The device core acts as a consumer toward pinctrl */ #include <linux/pinctrl/consumer.h> @@ -44,6 +46,14 @@ struct dev_pin_info { extern int pinctrl_bind_pins(struct device *dev); extern int pinctrl_init_done(struct device *dev); +static inline struct pinctrl *dev_pinctrl(struct device *dev) +{ + if (!dev->pins) + return NULL; + + return dev->pins->p; +} + #else /* Stubs if we're not using pinctrl */ @@ -58,5 +68,10 @@ static inline int pinctrl_init_done(struct device *dev) return 0; } +static inline struct pinctrl *dev_pinctrl(struct device *dev) +{ + return NULL; +} + #endif /* CONFIG_PINCTRL */ #endif /* PINCTRL_DEVINFO_H */ diff --git a/include/linux/platform_data/amd_xdma.h b/include/linux/platform_data/amd_xdma.h new file mode 100644 index 000000000000..b5e23e14bac8 --- /dev/null +++ b/include/linux/platform_data/amd_xdma.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2022, Advanced Micro Devices, Inc. + */ + +#ifndef _PLATDATA_AMD_XDMA_H +#define _PLATDATA_AMD_XDMA_H + +#include <linux/dmaengine.h> + +/** + * struct xdma_chan_info - DMA channel information + * This information is used to match channel when request dma channel + * @dir: Channel transfer direction + */ +struct xdma_chan_info { + enum dma_transfer_direction dir; +}; + +#define XDMA_FILTER_PARAM(chan_info) ((void *)(chan_info)) + +struct dma_slave_map; + +/** + * struct xdma_platdata - platform specific data for XDMA engine + * @max_dma_channels: Maximum dma channels in each direction + */ +struct xdma_platdata { + u32 max_dma_channels; + u32 device_map_cnt; + struct dma_slave_map *device_map; +}; + +#endif /* _PLATDATA_AMD_XDMA_H */ diff --git a/include/linux/platform_data/cros_ec_commands.h b/include/linux/platform_data/cros_ec_commands.h index b3b3df163efc..7e9c76aedd2d 100644 --- a/include/linux/platform_data/cros_ec_commands.h +++ b/include/linux/platform_data/cros_ec_commands.h @@ -3481,6 +3481,9 @@ struct ec_response_get_next_event_v1 { #define EC_MKBP_VOL_UP 1 #define EC_MKBP_VOL_DOWN 2 #define EC_MKBP_RECOVERY 3 +#define EC_MKBP_BRI_UP 4 +#define EC_MKBP_BRI_DOWN 5 +#define EC_MKBP_SCREEN_LOCK 6 /* Switches */ #define EC_MKBP_LID_OPEN 0 diff --git a/include/linux/platform_data/i2c-gpio.h b/include/linux/platform_data/i2c-gpio.h index a907774fd177..545639bcca72 100644 --- a/include/linux/platform_data/i2c-gpio.h +++ b/include/linux/platform_data/i2c-gpio.h @@ -16,16 +16,25 @@ * isn't actively driven high when setting the output value high. * gpio_get_value() must return the actual pin state even if the * pin is configured as an output. + * @sda_is_output_only: SDA output drivers can't be turned off. + * This is for clients that can only read SDA/SCL. + * @sda_has_no_pullup: SDA is used in a non-compliant way and has no pull-up. + * Therefore disable open-drain. * @scl_is_open_drain: SCL is set up as open drain. Same requirements * as for sda_is_open_drain apply. * @scl_is_output_only: SCL output drivers cannot be turned off. + * @scl_has_no_pullup: SCL is used in a non-compliant way and has no pull-up. + * Therefore disable open-drain. */ struct i2c_gpio_platform_data { int udelay; int timeout; unsigned int sda_is_open_drain:1; + unsigned int sda_is_output_only:1; + unsigned int sda_has_no_pullup:1; unsigned int scl_is_open_drain:1; unsigned int scl_is_output_only:1; + unsigned int scl_has_no_pullup:1; }; #endif /* _LINUX_I2C_GPIO_H */ diff --git a/include/linux/pm_domain.h b/include/linux/pm_domain.h index 1cd41bdf73cf..f776fb93eaa0 100644 --- a/include/linux/pm_domain.h +++ b/include/linux/pm_domain.h @@ -136,6 +136,7 @@ struct generic_pm_domain { unsigned int prepared_count; /* Suspend counter of prepared devices */ unsigned int performance_state; /* Aggregated max performance state */ cpumask_var_t cpus; /* A cpumask of the attached CPUs */ + bool synced_poweroff; /* A consumer needs a synced poweroff */ int (*power_off)(struct generic_pm_domain *domain); int (*power_on)(struct generic_pm_domain *domain); struct raw_notifier_head power_notifiers; /* Power on/off notifiers */ @@ -235,6 +236,7 @@ int dev_pm_genpd_add_notifier(struct device *dev, struct notifier_block *nb); int dev_pm_genpd_remove_notifier(struct device *dev); void dev_pm_genpd_set_next_wakeup(struct device *dev, ktime_t next); ktime_t dev_pm_genpd_get_next_hrtimer(struct device *dev); +void dev_pm_genpd_synced_poweroff(struct device *dev); extern struct dev_power_governor simple_qos_governor; extern struct dev_power_governor pm_domain_always_on_gov; @@ -300,6 +302,9 @@ static inline ktime_t dev_pm_genpd_get_next_hrtimer(struct device *dev) { return KTIME_MAX; } +static inline void dev_pm_genpd_synced_poweroff(struct device *dev) +{ } + #define simple_qos_governor (*(struct dev_power_governor *)(NULL)) #define pm_domain_always_on_gov (*(struct dev_power_governor *)(NULL)) #endif diff --git a/include/linux/pwm.h b/include/linux/pwm.h index 161e91167b9c..7b7b93b6fb81 100644 --- a/include/linux/pwm.h +++ b/include/linux/pwm.h @@ -440,13 +440,6 @@ static inline int pwm_config(struct pwm_device *pwm, int duty_ns, return -EINVAL; } -static inline int pwm_capture(struct pwm_device *pwm, - struct pwm_capture *result, - unsigned long timeout) -{ - return -EINVAL; -} - static inline int pwm_enable(struct pwm_device *pwm) { might_sleep(); @@ -458,6 +451,13 @@ static inline void pwm_disable(struct pwm_device *pwm) might_sleep(); } +static inline int pwm_capture(struct pwm_device *pwm, + struct pwm_capture *result, + unsigned long timeout) +{ + return -EINVAL; +} + static inline int pwm_set_chip_data(struct pwm_device *pwm, void *data) { return -EINVAL; diff --git a/include/linux/range.h b/include/linux/range.h index 274681cc3154..7efb6a9b069b 100644 --- a/include/linux/range.h +++ b/include/linux/range.h @@ -13,6 +13,11 @@ static inline u64 range_len(const struct range *range) return range->end - range->start + 1; } +static inline bool range_contains(struct range *r1, struct range *r2) +{ + return r1->start <= r2->start && r1->end >= r2->end; +} + int add_range(struct range *range, int az, int nr_range, u64 start, u64 end); diff --git a/include/linux/remoteproc/pruss.h b/include/linux/remoteproc/pruss.h new file mode 100644 index 000000000000..039b50d58df2 --- /dev/null +++ b/include/linux/remoteproc/pruss.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * PRU-ICSS Subsystem user interfaces + * + * Copyright (C) 2015-2022 Texas Instruments Incorporated - http://www.ti.com + * Suman Anna <s-anna@ti.com> + */ + +#ifndef __LINUX_PRUSS_H +#define __LINUX_PRUSS_H + +#include <linux/device.h> +#include <linux/types.h> + +#define PRU_RPROC_DRVNAME "pru-rproc" + +/** + * enum pruss_pru_id - PRU core identifiers + * @PRUSS_PRU0: PRU Core 0. + * @PRUSS_PRU1: PRU Core 1. + * @PRUSS_NUM_PRUS: Total number of PRU Cores available. + * + */ + +enum pruss_pru_id { + PRUSS_PRU0 = 0, + PRUSS_PRU1, + PRUSS_NUM_PRUS, +}; + +/* + * enum pru_ctable_idx - Configurable Constant table index identifiers + */ +enum pru_ctable_idx { + PRU_C24 = 0, + PRU_C25, + PRU_C26, + PRU_C27, + PRU_C28, + PRU_C29, + PRU_C30, + PRU_C31, +}; + +struct device_node; +struct rproc; + +#if IS_ENABLED(CONFIG_PRU_REMOTEPROC) + +struct rproc *pru_rproc_get(struct device_node *np, int index, + enum pruss_pru_id *pru_id); +void pru_rproc_put(struct rproc *rproc); +int pru_rproc_set_ctable(struct rproc *rproc, enum pru_ctable_idx c, u32 addr); + +#else + +static inline struct rproc * +pru_rproc_get(struct device_node *np, int index, enum pruss_pru_id *pru_id) +{ + return ERR_PTR(-EOPNOTSUPP); +} + +static inline void pru_rproc_put(struct rproc *rproc) { } + +static inline int pru_rproc_set_ctable(struct rproc *rproc, + enum pru_ctable_idx c, u32 addr) +{ + return -EOPNOTSUPP; +} + +#endif /* CONFIG_PRU_REMOTEPROC */ + +static inline bool is_pru_rproc(struct device *dev) +{ + const char *drv_name = dev_driver_string(dev); + + if (strncmp(drv_name, PRU_RPROC_DRVNAME, sizeof(PRU_RPROC_DRVNAME))) + return false; + + return true; +} + +#endif /* __LINUX_PRUSS_H */ diff --git a/include/linux/rpmsg/qcom_glink.h b/include/linux/rpmsg/qcom_glink.h index 22fc3a69b683..bfbd48f435fa 100644 --- a/include/linux/rpmsg/qcom_glink.h +++ b/include/linux/rpmsg/qcom_glink.h @@ -5,7 +5,7 @@ #include <linux/device.h> -struct qcom_glink; +struct qcom_glink_smem; #if IS_ENABLED(CONFIG_RPMSG_QCOM_GLINK) void qcom_glink_ssr_notify(const char *ssr_name); @@ -15,20 +15,20 @@ static inline void qcom_glink_ssr_notify(const char *ssr_name) {} #if IS_ENABLED(CONFIG_RPMSG_QCOM_GLINK_SMEM) -struct qcom_glink *qcom_glink_smem_register(struct device *parent, - struct device_node *node); -void qcom_glink_smem_unregister(struct qcom_glink *glink); +struct qcom_glink_smem *qcom_glink_smem_register(struct device *parent, + struct device_node *node); +void qcom_glink_smem_unregister(struct qcom_glink_smem *glink); #else -static inline struct qcom_glink * +static inline struct qcom_glink_smem * qcom_glink_smem_register(struct device *parent, struct device_node *node) { return NULL; } -static inline void qcom_glink_smem_unregister(struct qcom_glink *glink) {} +static inline void qcom_glink_smem_unregister(struct qcom_glink_smem *glink) {} #endif #endif diff --git a/include/linux/scmi_protocol.h b/include/linux/scmi_protocol.h index 4f765bc788ff..0ce5746a4470 100644 --- a/include/linux/scmi_protocol.h +++ b/include/linux/scmi_protocol.h @@ -804,11 +804,6 @@ struct scmi_device { #define to_scmi_dev(d) container_of(d, struct scmi_device, dev) -struct scmi_device * -scmi_device_create(struct device_node *np, struct device *parent, int protocol, - const char *name); -void scmi_device_destroy(struct scmi_device *scmi_dev); - struct scmi_device_id { u8 protocol_id; const char *name; diff --git a/include/linux/sh_intc.h b/include/linux/sh_intc.h index c255273b0281..37ad81058d6a 100644 --- a/include/linux/sh_intc.h +++ b/include/linux/sh_intc.h @@ -97,7 +97,10 @@ struct intc_hw_desc { unsigned int nr_subgroups; }; -#define _INTC_ARRAY(a) a, __same_type(a, NULL) ? 0 : sizeof(a)/sizeof(*a) +#define _INTC_SIZEOF_OR_ZERO(a) (_Generic(a, \ + typeof(NULL): 0, \ + default: sizeof(a))) +#define _INTC_ARRAY(a) a, _INTC_SIZEOF_OR_ZERO(a)/sizeof(*a) #define INTC_HW_DESC(vectors, groups, mask_regs, \ prio_regs, sense_regs, ack_regs) \ diff --git a/include/linux/soc/apple/rtkit.h b/include/linux/soc/apple/rtkit.h index c9cabb679cd1..fc456f75c131 100644 --- a/include/linux/soc/apple/rtkit.h +++ b/include/linux/soc/apple/rtkit.h @@ -22,6 +22,7 @@ * @size: Size of the shared memory buffer. * @iova: Device VA of shared memory buffer. * @is_mapped: Shared memory buffer is managed by the co-processor. + * @private: Private data pointer for the parent driver. */ struct apple_rtkit_shmem { @@ -30,6 +31,7 @@ struct apple_rtkit_shmem { size_t size; dma_addr_t iova; bool is_mapped; + void *private; }; /* @@ -78,6 +80,25 @@ struct apple_rtkit *devm_apple_rtkit_init(struct device *dev, void *cookie, const struct apple_rtkit_ops *ops); /* + * Non-devm version of devm_apple_rtkit_init. Must be freed with + * apple_rtkit_free. + * + * @dev: Pointer to the device node this coprocessor is assocated with + * @cookie: opaque cookie passed to all functions defined in rtkit_ops + * @mbox_name: mailbox name used to communicate with the co-processor + * @mbox_idx: mailbox index to be used if mbox_name is NULL + * @ops: pointer to rtkit_ops to be used for this co-processor + */ +struct apple_rtkit *apple_rtkit_init(struct device *dev, void *cookie, + const char *mbox_name, int mbox_idx, + const struct apple_rtkit_ops *ops); + +/* + * Free an instance of apple_rtkit. + */ +void apple_rtkit_free(struct apple_rtkit *rtk); + +/* * Reinitialize internal structures. Must only be called with the co-processor * is held in reset. */ @@ -105,6 +126,11 @@ int apple_rtkit_wake(struct apple_rtkit *rtk); int apple_rtkit_shutdown(struct apple_rtkit *rtk); /* + * Put the co-processor into idle mode + */ +int apple_rtkit_idle(struct apple_rtkit *rtk); + +/* * Checks if RTKit is running and ready to handle messages. */ bool apple_rtkit_is_running(struct apple_rtkit *rtk); diff --git a/include/linux/soc/mediatek/infracfg.h b/include/linux/soc/mediatek/infracfg.h index 50804ac748bd..07f67b3d8e97 100644 --- a/include/linux/soc/mediatek/infracfg.h +++ b/include/linux/soc/mediatek/infracfg.h @@ -140,6 +140,127 @@ #define MT8192_TOP_AXI_PROT_EN_MM_2_MDP_2ND BIT(13) #define MT8192_TOP_AXI_PROT_EN_VDNR_CAM BIT(21) +#define MT8188_TOP_AXI_PROT_EN_SET 0x2A0 +#define MT8188_TOP_AXI_PROT_EN_CLR 0x2A4 +#define MT8188_TOP_AXI_PROT_EN_STA 0x228 +#define MT8188_TOP_AXI_PROT_EN_1_SET 0x2A8 +#define MT8188_TOP_AXI_PROT_EN_1_CLR 0x2AC +#define MT8188_TOP_AXI_PROT_EN_1_STA 0x258 +#define MT8188_TOP_AXI_PROT_EN_2_SET 0x714 +#define MT8188_TOP_AXI_PROT_EN_2_CLR 0x718 +#define MT8188_TOP_AXI_PROT_EN_2_STA 0x724 + +#define MT8188_TOP_AXI_PROT_EN_MM_SET 0x2D4 +#define MT8188_TOP_AXI_PROT_EN_MM_CLR 0x2D8 +#define MT8188_TOP_AXI_PROT_EN_MM_STA 0x2EC +#define MT8188_TOP_AXI_PROT_EN_MM_2_SET 0xDCC +#define MT8188_TOP_AXI_PROT_EN_MM_2_CLR 0xDD0 +#define MT8188_TOP_AXI_PROT_EN_MM_2_STA 0xDD8 + +#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET 0xB84 +#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR 0xB88 +#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA 0xB90 +#define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET 0xBCC +#define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR 0xBD0 +#define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA 0xBD8 + +#define MT8188_TOP_AXI_PROT_EN_MFG1_STEP1 BIT(11) +#define MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP2 BIT(7) +#define MT8188_TOP_AXI_PROT_EN_1_MFG1_STEP3 BIT(19) +#define MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP4 BIT(5) +#define MT8188_TOP_AXI_PROT_EN_MFG1_STEP5 GENMASK(22, 21) +#define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1_STEP6 BIT(17) + +#define MT8188_TOP_AXI_PROT_EN_PEXTP_MAC_P0_STEP1 BIT(2) +#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_PEXTP_MAC_P0_STEP2 (BIT(8) | BIT(18) | BIT(30)) +#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_ETHER_STEP1 BIT(24) +#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_HDMI_TX_STEP1 BIT(20) +#define MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP1 GENMASK(31, 29) +#define MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP2 (GENMASK(4, 3) | BIT(28)) +#define MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP1 (GENMASK(16, 14) | BIT(23) | \ + BIT(27)) +#define MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP2 (GENMASK(19, 17) | GENMASK(26, 25)) +#define MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP1 GENMASK(11, 8) +#define MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP2 GENMASK(22, 21) +#define MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP1 BIT(20) +#define MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP2 BIT(12) +#define MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP1 BIT(24) +#define MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP2 BIT(13) + +#define MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP1 BIT(10) +#define MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP2 GENMASK(9, 8) +#define MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP3 BIT(23) +#define MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP4 (BIT(1) | BIT(4) | BIT(11)) +#define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0_STEP5 (BIT(20)) +#define MT8188_TOP_AXI_PROT_EN_MM_VDOSYS0_STEP1 (GENMASK(18, 17) | GENMASK(21, 20)) +#define MT8188_TOP_AXI_PROT_EN_VDOSYS0_STEP2 BIT(6) +#define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0_STEP3 BIT(21) +#define MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP1 GENMASK(31, 30) +#define MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP2 BIT(22) +#define MT8188_TOP_AXI_PROT_EN_MM_2_VDOSYS1_STEP3 BIT(10) +#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_DP_TX_STEP1 BIT(23) +#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_EDP_TX_STEP1 BIT(22) + +#define MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP1 GENMASK(6, 5) +#define MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP2 BIT(23) +#define MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS1_STEP3 BIT(18) +#define MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP1 BIT(23) +#define MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP2 BIT(21) +#define MT8188_TOP_AXI_PROT_EN_MM_VDEC0_STEP1 BIT(13) +#define MT8188_TOP_AXI_PROT_EN_MM_2_VDEC0_STEP2 BIT(13) +#define MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP1 BIT(14) +#define MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP2 BIT(29) +#define MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP1 (BIT(9) | BIT(11)) +#define MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP2 BIT(26) +#define MT8188_TOP_AXI_PROT_EN_MM_2_VENC_STEP3 BIT(2) +#define MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP1 (BIT(1) | BIT(3)) +#define MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP2 BIT(25) +#define MT8188_TOP_AXI_PROT_EN_MM_2_IMG_VCORE_STEP3 BIT(16) +#define MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP1 GENMASK(27, 26) +#define MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP2 GENMASK(25, 24) +#define MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP1 (BIT(2) | BIT(4)) +#define MT8188_TOP_AXI_PROT_EN_2_CAM_VCORE_STEP2 BIT(0) +#define MT8188_TOP_AXI_PROT_EN_1_CAM_VCORE_STEP3 BIT(22) +#define MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP4 BIT(24) +#define MT8188_TOP_AXI_PROT_EN_MM_2_CAM_VCORE_STEP5 BIT(17) +#define MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP1 GENMASK(31, 30) +#define MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP2 BIT(2) +#define MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP3 GENMASK(29, 28) +#define MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP4 BIT(1) + +#define MT8188_SMI_COMMON_CLAMP_EN_STA 0x3C0 +#define MT8188_SMI_COMMON_CLAMP_EN_SET 0x3C4 +#define MT8188_SMI_COMMON_CLAMP_EN_CLR 0x3C8 + +#define MT8188_SMI_COMMON_SMI_CLAMP_DIP_TO_VDO0 GENMASK(3, 1) +#define MT8188_SMI_COMMON_SMI_CLAMP_DIP_TO_VPP1 GENMASK(2, 1) +#define MT8188_SMI_COMMON_SMI_CLAMP_IPE_TO_VPP1 BIT(0) + +#define MT8188_SMI_COMMON_SMI_CLAMP_CAM_SUBA_TO_VPP0 GENMASK(3, 2) +#define MT8188_SMI_COMMON_SMI_CLAMP_CAM_SUBB_TO_VDO0 GENMASK(3, 2) + +#define MT8188_SMI_LARB10_RESET_ADDR 0xC +#define MT8188_SMI_LARB11A_RESET_ADDR 0xC +#define MT8188_SMI_LARB11C_RESET_ADDR 0xC +#define MT8188_SMI_LARB12_RESET_ADDR 0xC +#define MT8188_SMI_LARB11B_RESET_ADDR 0xC +#define MT8188_SMI_LARB15_RESET_ADDR 0xC +#define MT8188_SMI_LARB16B_RESET_ADDR 0xA0 +#define MT8188_SMI_LARB17B_RESET_ADDR 0xA0 +#define MT8188_SMI_LARB16A_RESET_ADDR 0xA0 +#define MT8188_SMI_LARB17A_RESET_ADDR 0xA0 + +#define MT8188_SMI_LARB10_RESET BIT(0) +#define MT8188_SMI_LARB11A_RESET BIT(0) +#define MT8188_SMI_LARB11C_RESET BIT(0) +#define MT8188_SMI_LARB12_RESET BIT(8) +#define MT8188_SMI_LARB11B_RESET BIT(0) +#define MT8188_SMI_LARB15_RESET BIT(0) +#define MT8188_SMI_LARB16B_RESET BIT(4) +#define MT8188_SMI_LARB17B_RESET BIT(4) +#define MT8188_SMI_LARB16A_RESET BIT(4) +#define MT8188_SMI_LARB17A_RESET BIT(4) + #define MT8186_TOP_AXI_PROT_EN_SET (0x2A0) #define MT8186_TOP_AXI_PROT_EN_CLR (0x2A4) #define MT8186_TOP_AXI_PROT_EN_STA (0x228) diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index b85f66db33e1..dc2963a0a0f7 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -6,6 +6,10 @@ #ifndef __MTK_MMSYS_H #define __MTK_MMSYS_H +#include <linux/mailbox_controller.h> +#include <linux/mailbox/mtk-cmdq-mailbox.h> +#include <linux/soc/mediatek/mtk-cmdq.h> + enum mtk_ddp_comp_id; struct device; @@ -36,7 +40,16 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_DSI1, DDP_COMPONENT_DSI2, DDP_COMPONENT_DSI3, + DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_GAMMA, + DDP_COMPONENT_MDP_RDMA0, + DDP_COMPONENT_MDP_RDMA1, + DDP_COMPONENT_MDP_RDMA2, + DDP_COMPONENT_MDP_RDMA3, + DDP_COMPONENT_MDP_RDMA4, + DDP_COMPONENT_MDP_RDMA5, + DDP_COMPONENT_MDP_RDMA6, + DDP_COMPONENT_MDP_RDMA7, DDP_COMPONENT_MERGE0, DDP_COMPONENT_MERGE1, DDP_COMPONENT_MERGE2, @@ -74,4 +87,16 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val); +void mtk_mmsys_merge_async_config(struct device *dev, int idx, int width, + int height, struct cmdq_pkt *cmdq_pkt); + +void mtk_mmsys_hdr_config(struct device *dev, int be_width, int be_height, + struct cmdq_pkt *cmdq_pkt); + +void mtk_mmsys_mixer_in_config(struct device *dev, int idx, bool alpha_sel, u16 alpha, + u8 mode, u32 biwidth, struct cmdq_pkt *cmdq_pkt); + +void mtk_mmsys_mixer_in_channel_swap(struct device *dev, int idx, bool channel_swap, + struct cmdq_pkt *cmdq_pkt); + #endif /* __MTK_MMSYS_H */ diff --git a/include/linux/soc/qcom/apr.h b/include/linux/soc/qcom/apr.h index 23c5b30f3511..be98aebcb3e1 100644 --- a/include/linux/soc/qcom/apr.h +++ b/include/linux/soc/qcom/apr.h @@ -153,7 +153,7 @@ typedef struct apr_device gpr_device_t; struct apr_driver { int (*probe)(struct apr_device *sl); - int (*remove)(struct apr_device *sl); + void (*remove)(struct apr_device *sl); int (*callback)(struct apr_device *a, struct apr_resp_pkt *d); int (*gpr_callback)(struct gpr_resp_pkt *d, void *data, int op); diff --git a/include/linux/soc/qcom/pmic_glink.h b/include/linux/soc/qcom/pmic_glink.h new file mode 100644 index 000000000000..fd124aa18c81 --- /dev/null +++ b/include/linux/soc/qcom/pmic_glink.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022, Linaro Ltd + */ +#ifndef __SOC_QCOM_PMIC_GLINK_H__ +#define __SOC_QCOM_PMIC_GLINK_H__ + +struct pmic_glink; +struct pmic_glink_client; + +#define PMIC_GLINK_OWNER_BATTMGR 32778 +#define PMIC_GLINK_OWNER_USBC 32779 +#define PMIC_GLINK_OWNER_USBC_PAN 32780 + +#define PMIC_GLINK_REQ_RESP 1 +#define PMIC_GLINK_NOTIFY 2 + +struct pmic_glink_hdr { + __le32 owner; + __le32 type; + __le32 opcode; +}; + +int pmic_glink_send(struct pmic_glink_client *client, void *data, size_t len); + +struct pmic_glink_client *devm_pmic_glink_register_client(struct device *dev, + unsigned int id, + void (*cb)(const void *, size_t, void *), + void (*pdr)(void *, int), + void *priv); + +#endif diff --git a/include/linux/soc/qcom/smd-rpm.h b/include/linux/soc/qcom/smd-rpm.h index 62de54992e49..2990f425fdef 100644 --- a/include/linux/soc/qcom/smd-rpm.h +++ b/include/linux/soc/qcom/smd-rpm.h @@ -43,7 +43,6 @@ struct qcom_smd_rpm; #define QCOM_SMD_RPM_HWKM_CLK 0x6d6b7768 #define QCOM_SMD_RPM_PKA_CLK 0x616b70 #define QCOM_SMD_RPM_MCFG_CLK 0x6766636d -#define QCOM_SMD_RPM_MMXI_CLK 0x69786d6d int qcom_rpm_smd_write(struct qcom_smd_rpm *rpm, int state, diff --git a/include/linux/soundwire/sdw.h b/include/linux/soundwire/sdw.h index 7d9fbf9359e4..ef645de13ae9 100644 --- a/include/linux/soundwire/sdw.h +++ b/include/linux/soundwire/sdw.h @@ -4,6 +4,7 @@ #ifndef __SOUNDWIRE_H #define __SOUNDWIRE_H +#include <linux/bug.h> #include <linux/mod_devicetable.h> #include <linux/bitfield.h> @@ -365,7 +366,9 @@ struct sdw_dpn_prop { * @sink_dpn_prop: Sink Data Port N properties * @scp_int1_mask: SCP_INT1_MASK desired settings * @quirks: bitmask identifying deltas from the MIPI specification - * @is_sdca: the Slave supports the SDCA specification + * @clock_reg_supported: the Peripheral implements the clock base and scale + * registers introduced with the SoundWire 1.2 specification. SDCA devices + * do not need to set this boolean property as the registers are required. */ struct sdw_slave_prop { u32 mipi_revision; @@ -389,7 +392,7 @@ struct sdw_slave_prop { struct sdw_dpn_prop *sink_dpn_prop; u8 scp_int1_mask; u32 quirks; - bool is_sdca; + bool clock_reg_supported; }; #define SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY BIT(0) @@ -836,8 +839,8 @@ struct sdw_defer { * @read_prop: Read Master properties * @override_adr: Override value read from firmware (quirk for buggy firmware) * @xfer_msg: Transfer message callback - * @xfer_msg_defer: Defer version of transfer message callback - * @reset_page_addr: Reset the SCP page address registers + * @xfer_msg_defer: Defer version of transfer message callback. The message is handled with the + * bus struct @sdw_defer * @set_bus_conf: Set the bus configuration * @pre_bank_switch: Callback for pre bank switch * @post_bank_switch: Callback for post bank switch @@ -851,10 +854,7 @@ struct sdw_master_ops { enum sdw_command_response (*xfer_msg) (struct sdw_bus *bus, struct sdw_msg *msg); enum sdw_command_response (*xfer_msg_defer) - (struct sdw_bus *bus, struct sdw_msg *msg, - struct sdw_defer *defer); - enum sdw_command_response (*reset_page_addr) - (struct sdw_bus *bus, unsigned int dev_num); + (struct sdw_bus *bus); int (*set_bus_conf)(struct sdw_bus *bus, struct sdw_bus_params *params); int (*pre_bank_switch)(struct sdw_bus *bus); @@ -1023,15 +1023,8 @@ int sdw_stream_add_master(struct sdw_bus *bus, struct sdw_port_config *port_config, unsigned int num_ports, struct sdw_stream_runtime *stream); -int sdw_stream_add_slave(struct sdw_slave *slave, - struct sdw_stream_config *stream_config, - struct sdw_port_config *port_config, - unsigned int num_ports, - struct sdw_stream_runtime *stream); int sdw_stream_remove_master(struct sdw_bus *bus, struct sdw_stream_runtime *stream); -int sdw_stream_remove_slave(struct sdw_slave *slave, - struct sdw_stream_runtime *stream); int sdw_startup_stream(void *sdw_substream); int sdw_prepare_stream(struct sdw_stream_runtime *stream); int sdw_enable_stream(struct sdw_stream_runtime *stream); @@ -1042,18 +1035,111 @@ int sdw_bus_prep_clk_stop(struct sdw_bus *bus); int sdw_bus_clk_stop(struct sdw_bus *bus); int sdw_bus_exit_clk_stop(struct sdw_bus *bus); -/* messaging and data APIs */ +int sdw_compare_devid(struct sdw_slave *slave, struct sdw_slave_id id); +void sdw_extract_slave_id(struct sdw_bus *bus, u64 addr, struct sdw_slave_id *id); +#if IS_ENABLED(CONFIG_SOUNDWIRE) + +int sdw_stream_add_slave(struct sdw_slave *slave, + struct sdw_stream_config *stream_config, + struct sdw_port_config *port_config, + unsigned int num_ports, + struct sdw_stream_runtime *stream); +int sdw_stream_remove_slave(struct sdw_slave *slave, + struct sdw_stream_runtime *stream); + +/* messaging and data APIs */ int sdw_read(struct sdw_slave *slave, u32 addr); int sdw_write(struct sdw_slave *slave, u32 addr, u8 value); int sdw_write_no_pm(struct sdw_slave *slave, u32 addr, u8 value); int sdw_read_no_pm(struct sdw_slave *slave, u32 addr); int sdw_nread(struct sdw_slave *slave, u32 addr, size_t count, u8 *val); +int sdw_nread_no_pm(struct sdw_slave *slave, u32 addr, size_t count, u8 *val); int sdw_nwrite(struct sdw_slave *slave, u32 addr, size_t count, const u8 *val); +int sdw_nwrite_no_pm(struct sdw_slave *slave, u32 addr, size_t count, const u8 *val); int sdw_update(struct sdw_slave *slave, u32 addr, u8 mask, u8 val); int sdw_update_no_pm(struct sdw_slave *slave, u32 addr, u8 mask, u8 val); -int sdw_compare_devid(struct sdw_slave *slave, struct sdw_slave_id id); -void sdw_extract_slave_id(struct sdw_bus *bus, u64 addr, struct sdw_slave_id *id); +#else + +static inline int sdw_stream_add_slave(struct sdw_slave *slave, + struct sdw_stream_config *stream_config, + struct sdw_port_config *port_config, + unsigned int num_ports, + struct sdw_stream_runtime *stream) +{ + WARN_ONCE(1, "SoundWire API is disabled"); + return -EINVAL; +} + +static inline int sdw_stream_remove_slave(struct sdw_slave *slave, + struct sdw_stream_runtime *stream) +{ + WARN_ONCE(1, "SoundWire API is disabled"); + return -EINVAL; +} + +/* messaging and data APIs */ +static inline int sdw_read(struct sdw_slave *slave, u32 addr) +{ + WARN_ONCE(1, "SoundWire API is disabled"); + return -EINVAL; +} + +static inline int sdw_write(struct sdw_slave *slave, u32 addr, u8 value) +{ + WARN_ONCE(1, "SoundWire API is disabled"); + return -EINVAL; +} + +static inline int sdw_write_no_pm(struct sdw_slave *slave, u32 addr, u8 value) +{ + WARN_ONCE(1, "SoundWire API is disabled"); + return -EINVAL; +} + +static inline int sdw_read_no_pm(struct sdw_slave *slave, u32 addr) +{ + WARN_ONCE(1, "SoundWire API is disabled"); + return -EINVAL; +} + +static inline int sdw_nread(struct sdw_slave *slave, u32 addr, size_t count, u8 *val) +{ + WARN_ONCE(1, "SoundWire API is disabled"); + return -EINVAL; +} + +static inline int sdw_nread_no_pm(struct sdw_slave *slave, u32 addr, size_t count, u8 *val) +{ + WARN_ONCE(1, "SoundWire API is disabled"); + return -EINVAL; +} + +static inline int sdw_nwrite(struct sdw_slave *slave, u32 addr, size_t count, const u8 *val) +{ + WARN_ONCE(1, "SoundWire API is disabled"); + return -EINVAL; +} + +static inline int sdw_nwrite_no_pm(struct sdw_slave *slave, u32 addr, size_t count, const u8 *val) +{ + WARN_ONCE(1, "SoundWire API is disabled"); + return -EINVAL; +} + +static inline int sdw_update(struct sdw_slave *slave, u32 addr, u8 mask, u8 val) +{ + WARN_ONCE(1, "SoundWire API is disabled"); + return -EINVAL; +} + +static inline int sdw_update_no_pm(struct sdw_slave *slave, u32 addr, u8 mask, u8 val) +{ + WARN_ONCE(1, "SoundWire API is disabled"); + return -EINVAL; +} + +#endif /* CONFIG_SOUNDWIRE */ #endif /* __SOUNDWIRE_H */ diff --git a/include/linux/swiotlb.h b/include/linux/swiotlb.h index 35bc4e281c21..bcef10e20ea4 100644 --- a/include/linux/swiotlb.h +++ b/include/linux/swiotlb.h @@ -121,7 +121,6 @@ static inline bool is_swiotlb_force_bounce(struct device *dev) void swiotlb_init(bool addressing_limited, unsigned int flags); void __init swiotlb_exit(void); -unsigned int swiotlb_max_segment(void); size_t swiotlb_max_mapping_size(struct device *dev); bool is_swiotlb_active(struct device *dev); void __init swiotlb_adjust_size(unsigned long size); @@ -140,10 +139,6 @@ static inline bool is_swiotlb_force_bounce(struct device *dev) static inline void swiotlb_exit(void) { } -static inline unsigned int swiotlb_max_segment(void) -{ - return 0; -} static inline size_t swiotlb_max_mapping_size(struct device *dev) { return SIZE_MAX; diff --git a/include/linux/vdpa.h b/include/linux/vdpa.h index 6d0f5e4e82c2..43f59ef10cc9 100644 --- a/include/linux/vdpa.h +++ b/include/linux/vdpa.h @@ -219,7 +219,10 @@ struct vdpa_map_file { * @reset: Reset device * @vdev: vdpa device * Returns integer: success (0) or error (< 0) - * @suspend: Suspend or resume the device (optional) + * @suspend: Suspend the device (optional) + * @vdev: vdpa device + * Returns integer: success (0) or error (< 0) + * @resume: Resume the device (optional) * @vdev: vdpa device * Returns integer: success (0) or error (< 0) * @get_config_size: Get the size of the configuration space includes @@ -282,6 +285,11 @@ struct vdpa_map_file { * @iova: iova to be unmapped * @size: size of the area * Returns integer: success (0) or error (< 0) + * @get_vq_dma_dev: Get the dma device for a specific + * virtqueue (optional) + * @vdev: vdpa device + * @idx: virtqueue index + * Returns pointer to structure device or error (NULL) * @free: Free resources that belongs to vDPA (optional) * @vdev: vdpa device */ @@ -324,6 +332,7 @@ struct vdpa_config_ops { void (*set_status)(struct vdpa_device *vdev, u8 status); int (*reset)(struct vdpa_device *vdev); int (*suspend)(struct vdpa_device *vdev); + int (*resume)(struct vdpa_device *vdev); size_t (*get_config_size)(struct vdpa_device *vdev); void (*get_config)(struct vdpa_device *vdev, unsigned int offset, void *buf, unsigned int len); @@ -341,6 +350,7 @@ struct vdpa_config_ops { u64 iova, u64 size); int (*set_group_asid)(struct vdpa_device *vdev, unsigned int group, unsigned int asid); + struct device *(*get_vq_dma_dev)(struct vdpa_device *vdev, u16 idx); /* Free device resources */ void (*free)(struct vdpa_device *vdev); diff --git a/include/linux/vfio.h b/include/linux/vfio.h index 35be78e9ae57..93134b023968 100644 --- a/include/linux/vfio.h +++ b/include/linux/vfio.h @@ -46,7 +46,6 @@ struct vfio_device { struct vfio_device_set *dev_set; struct list_head dev_set_list; unsigned int migration_flags; - /* Driver must reference the kvm during open_device or never touch it */ struct kvm *kvm; /* Members below here are private, not for driver use */ @@ -58,6 +57,7 @@ struct vfio_device { struct list_head group_next; struct list_head iommu_entry; struct iommufd_access *iommufd_access; + void (*put_kvm)(struct kvm *kvm); #if IS_ENABLED(CONFIG_IOMMUFD) struct iommufd_device *iommufd_device; struct iommufd_ctx *iommufd_ictx; @@ -70,6 +70,10 @@ struct vfio_device { * * @init: initialize private fields in device structure * @release: Reclaim private fields in device structure + * @bind_iommufd: Called when binding the device to an iommufd + * @unbind_iommufd: Opposite of bind_iommufd + * @attach_ioas: Called when attaching device to an IOAS/HWPT managed by the + * bound iommufd. Undo in unbind_iommufd. * @open_device: Called when the first file descriptor is opened for this device * @close_device: Opposite of open_device * @read: Perform read(2) on device file descriptor diff --git a/include/linux/virtio_config.h b/include/linux/virtio_config.h index 4b517649cfe8..2b3438de2c4d 100644 --- a/include/linux/virtio_config.h +++ b/include/linux/virtio_config.h @@ -16,8 +16,10 @@ struct virtio_shm_region { u64 len; }; +typedef void vq_callback_t(struct virtqueue *); + /** - * virtio_config_ops - operations for configuring a virtio device + * struct virtio_config_ops - operations for configuring a virtio device * Note: Do not assume that a transport implements all of the operations * getting/setting a value as a simple read/write! Generally speaking, * any of @get/@set, @get_status/@set_status, or @get_features/ @@ -69,7 +71,8 @@ struct virtio_shm_region { * vdev: the virtio_device * This sends the driver feature bits to the device: it can change * the dev->feature bits if it wants. - * Note: despite the name this can be called any number of times. + * Note that despite the name this can be called any number of + * times. * Returns 0 on success or error status * @bus_name: return the bus name associated with the device (optional) * vdev: the virtio_device @@ -91,7 +94,6 @@ struct virtio_shm_region { * If disable_vq_and_reset is set, then enable_vq_after_reset must also be * set. */ -typedef void vq_callback_t(struct virtqueue *); struct virtio_config_ops { void (*get)(struct virtio_device *vdev, unsigned offset, void *buf, unsigned len); diff --git a/include/linux/virtio_ring.h b/include/linux/virtio_ring.h index 8b8af1a38991..8b95b69ef694 100644 --- a/include/linux/virtio_ring.h +++ b/include/linux/virtio_ring.h @@ -77,6 +77,22 @@ struct virtqueue *vring_create_virtqueue(unsigned int index, const char *name); /* + * Creates a virtqueue and allocates the descriptor ring with per + * virtqueue DMA device. + */ +struct virtqueue *vring_create_virtqueue_dma(unsigned int index, + unsigned int num, + unsigned int vring_align, + struct virtio_device *vdev, + bool weak_barriers, + bool may_reduce_num, + bool ctx, + bool (*notify)(struct virtqueue *vq), + void (*callback)(struct virtqueue *vq), + const char *name, + struct device *dma_dev); + +/* * Creates a virtqueue with a standard layout but a caller-allocated * ring. */ diff --git a/include/linux/vringh.h b/include/linux/vringh.h index 212892cf9822..1991a02c6431 100644 --- a/include/linux/vringh.h +++ b/include/linux/vringh.h @@ -92,7 +92,7 @@ struct vringh_iov { }; /** - * struct vringh_iov - kvec mangler. + * struct vringh_kiov - kvec mangler. * * Mangles kvec in place, and restores it. * Remaining data is iov + i, of used - i elements. diff --git a/include/media/davinci/ccdc_types.h b/include/media/davinci/ccdc_types.h deleted file mode 100644 index 971984dc1ce4..000000000000 --- a/include/media/davinci/ccdc_types.h +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (C) 2008-2009 Texas Instruments Inc - * - **************************************************************************/ -#ifndef _CCDC_TYPES_H -#define _CCDC_TYPES_H -enum ccdc_pixfmt { - CCDC_PIXFMT_RAW, - CCDC_PIXFMT_YCBCR_16BIT, - CCDC_PIXFMT_YCBCR_8BIT -}; - -enum ccdc_frmfmt { - CCDC_FRMFMT_PROGRESSIVE, - CCDC_FRMFMT_INTERLACED -}; - -/* PIXEL ORDER IN MEMORY from LSB to MSB */ -/* only applicable for 8-bit input mode */ -enum ccdc_pixorder { - CCDC_PIXORDER_YCBYCR, - CCDC_PIXORDER_CBYCRY, -}; - -enum ccdc_buftype { - CCDC_BUFTYPE_FLD_INTERLEAVED, - CCDC_BUFTYPE_FLD_SEPARATED -}; -#endif diff --git a/include/media/drv-intf/saa7146.h b/include/media/drv-intf/saa7146.h new file mode 100644 index 000000000000..71ce63c99cb4 --- /dev/null +++ b/include/media/drv-intf/saa7146.h @@ -0,0 +1,472 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __SAA7146__ +#define __SAA7146__ + +#include <linux/delay.h> /* for delay-stuff */ +#include <linux/slab.h> /* for kmalloc/kfree */ +#include <linux/pci.h> /* for pci-config-stuff, vendor ids etc. */ +#include <linux/init.h> /* for "__init" */ +#include <linux/interrupt.h> /* for IMMEDIATE_BH */ +#include <linux/kmod.h> /* for kernel module loader */ +#include <linux/i2c.h> /* for i2c subsystem */ +#include <asm/io.h> /* for accessing devices */ +#include <linux/stringify.h> +#include <linux/mutex.h> +#include <linux/scatterlist.h> +#include <media/v4l2-device.h> +#include <media/v4l2-ctrls.h> + +#include <linux/vmalloc.h> /* for vmalloc() */ +#include <linux/mm.h> /* for vmalloc_to_page() */ + +#define saa7146_write(sxy,adr,dat) writel((dat),(sxy->mem+(adr))) +#define saa7146_read(sxy,adr) readl(sxy->mem+(adr)) + +extern unsigned int saa7146_debug; + +#ifndef DEBUG_VARIABLE + #define DEBUG_VARIABLE saa7146_debug +#endif + +#define ERR(fmt, ...) pr_err("%s: " fmt, __func__, ##__VA_ARGS__) + +#define _DBG(mask, fmt, ...) \ +do { \ + if (DEBUG_VARIABLE & mask) \ + pr_debug("%s(): " fmt, __func__, ##__VA_ARGS__); \ +} while (0) + +/* simple debug messages */ +#define DEB_S(fmt, ...) _DBG(0x01, fmt, ##__VA_ARGS__) +/* more detailed debug messages */ +#define DEB_D(fmt, ...) _DBG(0x02, fmt, ##__VA_ARGS__) +/* print enter and exit of functions */ +#define DEB_EE(fmt, ...) _DBG(0x04, fmt, ##__VA_ARGS__) +/* i2c debug messages */ +#define DEB_I2C(fmt, ...) _DBG(0x08, fmt, ##__VA_ARGS__) +/* vbi debug messages */ +#define DEB_VBI(fmt, ...) _DBG(0x10, fmt, ##__VA_ARGS__) +/* interrupt debug messages */ +#define DEB_INT(fmt, ...) _DBG(0x20, fmt, ##__VA_ARGS__) +/* capture debug messages */ +#define DEB_CAP(fmt, ...) _DBG(0x40, fmt, ##__VA_ARGS__) + +#define SAA7146_ISR_CLEAR(x,y) \ + saa7146_write(x, ISR, (y)); + +struct module; + +struct saa7146_dev; +struct saa7146_extension; +struct saa7146_vv; + +/* saa7146 page table */ +struct saa7146_pgtable { + unsigned int size; + __le32 *cpu; + dma_addr_t dma; + /* used for offsets for u,v planes for planar capture modes */ + unsigned long offset; + /* used for custom pagetables (used for example by budget dvb cards) */ + struct scatterlist *slist; + int nents; +}; + +struct saa7146_pci_extension_data { + struct saa7146_extension *ext; + void *ext_priv; /* most likely a name string */ +}; + +#define MAKE_EXTENSION_PCI(x_var, x_vendor, x_device) \ + { \ + .vendor = PCI_VENDOR_ID_PHILIPS, \ + .device = PCI_DEVICE_ID_PHILIPS_SAA7146, \ + .subvendor = x_vendor, \ + .subdevice = x_device, \ + .driver_data = (unsigned long)& x_var, \ + } + +struct saa7146_extension +{ + char name[32]; /* name of the device */ +#define SAA7146_USE_I2C_IRQ 0x1 +#define SAA7146_I2C_SHORT_DELAY 0x2 + int flags; + + /* pairs of subvendor and subdevice ids for + supported devices, last entry 0xffff, 0xfff */ + struct module *module; + struct pci_driver driver; + const struct pci_device_id *pci_tbl; + + /* extension functions */ + int (*probe)(struct saa7146_dev *); + int (*attach)(struct saa7146_dev *, struct saa7146_pci_extension_data *); + int (*detach)(struct saa7146_dev*); + + u32 irq_mask; /* mask to indicate, which irq-events are handled by the extension */ + void (*irq_func)(struct saa7146_dev*, u32* irq_mask); +}; + +struct saa7146_dma +{ + dma_addr_t dma_handle; + __le32 *cpu_addr; +}; + +struct saa7146_dev +{ + struct module *module; + + struct v4l2_device v4l2_dev; + struct v4l2_ctrl_handler ctrl_handler; + + /* different device locks */ + spinlock_t slock; + struct mutex v4l2_lock; + + unsigned char __iomem *mem; /* pointer to mapped IO memory */ + u32 revision; /* chip revision; needed for bug-workarounds*/ + + /* pci-device & irq stuff*/ + char name[32]; + struct pci_dev *pci; + u32 int_todo; + spinlock_t int_slock; + + /* extension handling */ + struct saa7146_extension *ext; /* indicates if handled by extension */ + void *ext_priv; /* pointer for extension private use (most likely some private data) */ + struct saa7146_ext_vv *ext_vv_data; + + /* per device video/vbi information (if available) */ + struct saa7146_vv *vv_data; + void (*vv_callback)(struct saa7146_dev *dev, unsigned long status); + + /* i2c-stuff */ + struct mutex i2c_lock; + + u32 i2c_bitrate; + struct saa7146_dma d_i2c; /* pointer to i2c memory */ + wait_queue_head_t i2c_wq; + int i2c_op; + + /* memories */ + struct saa7146_dma d_rps0; + struct saa7146_dma d_rps1; +}; + +static inline struct saa7146_dev *to_saa7146_dev(struct v4l2_device *v4l2_dev) +{ + return container_of(v4l2_dev, struct saa7146_dev, v4l2_dev); +} + +/* from saa7146_i2c.c */ +int saa7146_i2c_adapter_prepare(struct saa7146_dev *dev, struct i2c_adapter *i2c_adapter, u32 bitrate); + +/* from saa7146_core.c */ +int saa7146_register_extension(struct saa7146_extension*); +int saa7146_unregister_extension(struct saa7146_extension*); +struct saa7146_format* saa7146_format_by_fourcc(struct saa7146_dev *dev, int fourcc); +int saa7146_pgtable_alloc(struct pci_dev *pci, struct saa7146_pgtable *pt); +void saa7146_pgtable_free(struct pci_dev *pci, struct saa7146_pgtable *pt); +int saa7146_pgtable_build_single(struct pci_dev *pci, struct saa7146_pgtable *pt, struct scatterlist *list, int length ); +void *saa7146_vmalloc_build_pgtable(struct pci_dev *pci, long length, struct saa7146_pgtable *pt); +void saa7146_vfree_destroy_pgtable(struct pci_dev *pci, void *mem, struct saa7146_pgtable *pt); +void saa7146_setgpio(struct saa7146_dev *dev, int port, u32 data); +int saa7146_wait_for_debi_done(struct saa7146_dev *dev, int nobusyloop); + +/* some memory sizes */ +#define SAA7146_I2C_MEM ( 1*PAGE_SIZE) +#define SAA7146_RPS_MEM ( 1*PAGE_SIZE) + +/* some i2c constants */ +#define SAA7146_I2C_TIMEOUT 100 /* i2c-timeout-value in ms */ +#define SAA7146_I2C_RETRIES 3 /* how many times shall we retry an i2c-operation? */ +#define SAA7146_I2C_DELAY 5 /* time we wait after certain i2c-operations */ + +/* unsorted defines */ +#define ME1 0x0000000800 +#define PV1 0x0000000008 + +/* gpio defines */ +#define SAA7146_GPIO_INPUT 0x00 +#define SAA7146_GPIO_IRQHI 0x10 +#define SAA7146_GPIO_IRQLO 0x20 +#define SAA7146_GPIO_IRQHL 0x30 +#define SAA7146_GPIO_OUTLO 0x40 +#define SAA7146_GPIO_OUTHI 0x50 + +/* debi defines */ +#define DEBINOSWAP 0x000e0000 + +/* define for the register programming sequencer (rps) */ +#define CMD_NOP 0x00000000 /* No operation */ +#define CMD_CLR_EVENT 0x00000000 /* Clear event */ +#define CMD_SET_EVENT 0x10000000 /* Set signal event */ +#define CMD_PAUSE 0x20000000 /* Pause */ +#define CMD_CHECK_LATE 0x30000000 /* Check late */ +#define CMD_UPLOAD 0x40000000 /* Upload */ +#define CMD_STOP 0x50000000 /* Stop */ +#define CMD_INTERRUPT 0x60000000 /* Interrupt */ +#define CMD_JUMP 0x80000000 /* Jump */ +#define CMD_WR_REG 0x90000000 /* Write (load) register */ +#define CMD_RD_REG 0xa0000000 /* Read (store) register */ +#define CMD_WR_REG_MASK 0xc0000000 /* Write register with mask */ + +#define CMD_OAN MASK_27 +#define CMD_INV MASK_26 +#define CMD_SIG4 MASK_25 +#define CMD_SIG3 MASK_24 +#define CMD_SIG2 MASK_23 +#define CMD_SIG1 MASK_22 +#define CMD_SIG0 MASK_21 +#define CMD_O_FID_B MASK_14 +#define CMD_E_FID_B MASK_13 +#define CMD_O_FID_A MASK_12 +#define CMD_E_FID_A MASK_11 + +/* some events and command modifiers for rps1 squarewave generator */ +#define EVT_HS (1<<15) // Source Line Threshold reached +#define EVT_VBI_B (1<<9) // VSYNC Event +#define RPS_OAN (1<<27) // 1: OR events, 0: AND events +#define RPS_INV (1<<26) // Invert (compound) event +#define GPIO3_MSK 0xFF000000 // GPIO #3 control bits + +/* Bit mask constants */ +#define MASK_00 0x00000001 /* Mask value for bit 0 */ +#define MASK_01 0x00000002 /* Mask value for bit 1 */ +#define MASK_02 0x00000004 /* Mask value for bit 2 */ +#define MASK_03 0x00000008 /* Mask value for bit 3 */ +#define MASK_04 0x00000010 /* Mask value for bit 4 */ +#define MASK_05 0x00000020 /* Mask value for bit 5 */ +#define MASK_06 0x00000040 /* Mask value for bit 6 */ +#define MASK_07 0x00000080 /* Mask value for bit 7 */ +#define MASK_08 0x00000100 /* Mask value for bit 8 */ +#define MASK_09 0x00000200 /* Mask value for bit 9 */ +#define MASK_10 0x00000400 /* Mask value for bit 10 */ +#define MASK_11 0x00000800 /* Mask value for bit 11 */ +#define MASK_12 0x00001000 /* Mask value for bit 12 */ +#define MASK_13 0x00002000 /* Mask value for bit 13 */ +#define MASK_14 0x00004000 /* Mask value for bit 14 */ +#define MASK_15 0x00008000 /* Mask value for bit 15 */ +#define MASK_16 0x00010000 /* Mask value for bit 16 */ +#define MASK_17 0x00020000 /* Mask value for bit 17 */ +#define MASK_18 0x00040000 /* Mask value for bit 18 */ +#define MASK_19 0x00080000 /* Mask value for bit 19 */ +#define MASK_20 0x00100000 /* Mask value for bit 20 */ +#define MASK_21 0x00200000 /* Mask value for bit 21 */ +#define MASK_22 0x00400000 /* Mask value for bit 22 */ +#define MASK_23 0x00800000 /* Mask value for bit 23 */ +#define MASK_24 0x01000000 /* Mask value for bit 24 */ +#define MASK_25 0x02000000 /* Mask value for bit 25 */ +#define MASK_26 0x04000000 /* Mask value for bit 26 */ +#define MASK_27 0x08000000 /* Mask value for bit 27 */ +#define MASK_28 0x10000000 /* Mask value for bit 28 */ +#define MASK_29 0x20000000 /* Mask value for bit 29 */ +#define MASK_30 0x40000000 /* Mask value for bit 30 */ +#define MASK_31 0x80000000 /* Mask value for bit 31 */ + +#define MASK_B0 0x000000ff /* Mask value for byte 0 */ +#define MASK_B1 0x0000ff00 /* Mask value for byte 1 */ +#define MASK_B2 0x00ff0000 /* Mask value for byte 2 */ +#define MASK_B3 0xff000000 /* Mask value for byte 3 */ + +#define MASK_W0 0x0000ffff /* Mask value for word 0 */ +#define MASK_W1 0xffff0000 /* Mask value for word 1 */ + +#define MASK_PA 0xfffffffc /* Mask value for physical address */ +#define MASK_PR 0xfffffffe /* Mask value for protection register */ +#define MASK_ER 0xffffffff /* Mask value for the entire register */ + +#define MASK_NONE 0x00000000 /* No mask */ + +/* register aliases */ +#define BASE_ODD1 0x00 /* Video DMA 1 registers */ +#define BASE_EVEN1 0x04 +#define PROT_ADDR1 0x08 +#define PITCH1 0x0C +#define BASE_PAGE1 0x10 /* Video DMA 1 base page */ +#define NUM_LINE_BYTE1 0x14 + +#define BASE_ODD2 0x18 /* Video DMA 2 registers */ +#define BASE_EVEN2 0x1C +#define PROT_ADDR2 0x20 +#define PITCH2 0x24 +#define BASE_PAGE2 0x28 /* Video DMA 2 base page */ +#define NUM_LINE_BYTE2 0x2C + +#define BASE_ODD3 0x30 /* Video DMA 3 registers */ +#define BASE_EVEN3 0x34 +#define PROT_ADDR3 0x38 +#define PITCH3 0x3C +#define BASE_PAGE3 0x40 /* Video DMA 3 base page */ +#define NUM_LINE_BYTE3 0x44 + +#define PCI_BT_V1 0x48 /* Video/FIFO 1 */ +#define PCI_BT_V2 0x49 /* Video/FIFO 2 */ +#define PCI_BT_V3 0x4A /* Video/FIFO 3 */ +#define PCI_BT_DEBI 0x4B /* DEBI */ +#define PCI_BT_A 0x4C /* Audio */ + +#define DD1_INIT 0x50 /* Init setting of DD1 interface */ + +#define DD1_STREAM_B 0x54 /* DD1 B video data stream handling */ +#define DD1_STREAM_A 0x56 /* DD1 A video data stream handling */ + +#define BRS_CTRL 0x58 /* BRS control register */ +#define HPS_CTRL 0x5C /* HPS control register */ +#define HPS_V_SCALE 0x60 /* HPS vertical scale */ +#define HPS_V_GAIN 0x64 /* HPS vertical ACL and gain */ +#define HPS_H_PRESCALE 0x68 /* HPS horizontal prescale */ +#define HPS_H_SCALE 0x6C /* HPS horizontal scale */ +#define BCS_CTRL 0x70 /* BCS control */ +#define CHROMA_KEY_RANGE 0x74 +#define CLIP_FORMAT_CTRL 0x78 /* HPS outputs formats & clipping */ + +#define DEBI_CONFIG 0x7C +#define DEBI_COMMAND 0x80 +#define DEBI_PAGE 0x84 +#define DEBI_AD 0x88 + +#define I2C_TRANSFER 0x8C +#define I2C_STATUS 0x90 + +#define BASE_A1_IN 0x94 /* Audio 1 input DMA */ +#define PROT_A1_IN 0x98 +#define PAGE_A1_IN 0x9C + +#define BASE_A1_OUT 0xA0 /* Audio 1 output DMA */ +#define PROT_A1_OUT 0xA4 +#define PAGE_A1_OUT 0xA8 + +#define BASE_A2_IN 0xAC /* Audio 2 input DMA */ +#define PROT_A2_IN 0xB0 +#define PAGE_A2_IN 0xB4 + +#define BASE_A2_OUT 0xB8 /* Audio 2 output DMA */ +#define PROT_A2_OUT 0xBC +#define PAGE_A2_OUT 0xC0 + +#define RPS_PAGE0 0xC4 /* RPS task 0 page register */ +#define RPS_PAGE1 0xC8 /* RPS task 1 page register */ + +#define RPS_THRESH0 0xCC /* HBI threshold for task 0 */ +#define RPS_THRESH1 0xD0 /* HBI threshold for task 1 */ + +#define RPS_TOV0 0xD4 /* RPS timeout for task 0 */ +#define RPS_TOV1 0xD8 /* RPS timeout for task 1 */ + +#define IER 0xDC /* Interrupt enable register */ + +#define GPIO_CTRL 0xE0 /* GPIO 0-3 register */ + +#define EC1SSR 0xE4 /* Event cnt set 1 source select */ +#define EC2SSR 0xE8 /* Event cnt set 2 source select */ +#define ECT1R 0xEC /* Event cnt set 1 thresholds */ +#define ECT2R 0xF0 /* Event cnt set 2 thresholds */ + +#define ACON1 0xF4 +#define ACON2 0xF8 + +#define MC1 0xFC /* Main control register 1 */ +#define MC2 0x100 /* Main control register 2 */ + +#define RPS_ADDR0 0x104 /* RPS task 0 address register */ +#define RPS_ADDR1 0x108 /* RPS task 1 address register */ + +#define ISR 0x10C /* Interrupt status register */ +#define PSR 0x110 /* Primary status register */ +#define SSR 0x114 /* Secondary status register */ + +#define EC1R 0x118 /* Event counter set 1 register */ +#define EC2R 0x11C /* Event counter set 2 register */ + +#define PCI_VDP1 0x120 /* Video DMA pointer of FIFO 1 */ +#define PCI_VDP2 0x124 /* Video DMA pointer of FIFO 2 */ +#define PCI_VDP3 0x128 /* Video DMA pointer of FIFO 3 */ +#define PCI_ADP1 0x12C /* Audio DMA pointer of audio out 1 */ +#define PCI_ADP2 0x130 /* Audio DMA pointer of audio in 1 */ +#define PCI_ADP3 0x134 /* Audio DMA pointer of audio out 2 */ +#define PCI_ADP4 0x138 /* Audio DMA pointer of audio in 2 */ +#define PCI_DMA_DDP 0x13C /* DEBI DMA pointer */ + +#define LEVEL_REP 0x140, +#define A_TIME_SLOT1 0x180, /* from 180 - 1BC */ +#define A_TIME_SLOT2 0x1C0, /* from 1C0 - 1FC */ + +/* isr masks */ +#define SPCI_PPEF 0x80000000 /* PCI parity error */ +#define SPCI_PABO 0x40000000 /* PCI access error (target or master abort) */ +#define SPCI_PPED 0x20000000 /* PCI parity error on 'real time data' */ +#define SPCI_RPS_I1 0x10000000 /* Interrupt issued by RPS1 */ +#define SPCI_RPS_I0 0x08000000 /* Interrupt issued by RPS0 */ +#define SPCI_RPS_LATE1 0x04000000 /* RPS task 1 is late */ +#define SPCI_RPS_LATE0 0x02000000 /* RPS task 0 is late */ +#define SPCI_RPS_E1 0x01000000 /* RPS error from task 1 */ +#define SPCI_RPS_E0 0x00800000 /* RPS error from task 0 */ +#define SPCI_RPS_TO1 0x00400000 /* RPS timeout task 1 */ +#define SPCI_RPS_TO0 0x00200000 /* RPS timeout task 0 */ +#define SPCI_UPLD 0x00100000 /* RPS in upload */ +#define SPCI_DEBI_S 0x00080000 /* DEBI status */ +#define SPCI_DEBI_E 0x00040000 /* DEBI error */ +#define SPCI_IIC_S 0x00020000 /* I2C status */ +#define SPCI_IIC_E 0x00010000 /* I2C error */ +#define SPCI_A2_IN 0x00008000 /* Audio 2 input DMA protection / limit */ +#define SPCI_A2_OUT 0x00004000 /* Audio 2 output DMA protection / limit */ +#define SPCI_A1_IN 0x00002000 /* Audio 1 input DMA protection / limit */ +#define SPCI_A1_OUT 0x00001000 /* Audio 1 output DMA protection / limit */ +#define SPCI_AFOU 0x00000800 /* Audio FIFO over- / underflow */ +#define SPCI_V_PE 0x00000400 /* Video protection address */ +#define SPCI_VFOU 0x00000200 /* Video FIFO over- / underflow */ +#define SPCI_FIDA 0x00000100 /* Field ID video port A */ +#define SPCI_FIDB 0x00000080 /* Field ID video port B */ +#define SPCI_PIN3 0x00000040 /* GPIO pin 3 */ +#define SPCI_PIN2 0x00000020 /* GPIO pin 2 */ +#define SPCI_PIN1 0x00000010 /* GPIO pin 1 */ +#define SPCI_PIN0 0x00000008 /* GPIO pin 0 */ +#define SPCI_ECS 0x00000004 /* Event counter 1, 2, 4, 5 */ +#define SPCI_EC3S 0x00000002 /* Event counter 3 */ +#define SPCI_EC0S 0x00000001 /* Event counter 0 */ + +/* i2c */ +#define SAA7146_I2C_ABORT (1<<7) +#define SAA7146_I2C_SPERR (1<<6) +#define SAA7146_I2C_APERR (1<<5) +#define SAA7146_I2C_DTERR (1<<4) +#define SAA7146_I2C_DRERR (1<<3) +#define SAA7146_I2C_AL (1<<2) +#define SAA7146_I2C_ERR (1<<1) +#define SAA7146_I2C_BUSY (1<<0) + +#define SAA7146_I2C_START (0x3) +#define SAA7146_I2C_CONT (0x2) +#define SAA7146_I2C_STOP (0x1) +#define SAA7146_I2C_NOP (0x0) + +#define SAA7146_I2C_BUS_BIT_RATE_6400 (0x500) +#define SAA7146_I2C_BUS_BIT_RATE_3200 (0x100) +#define SAA7146_I2C_BUS_BIT_RATE_480 (0x400) +#define SAA7146_I2C_BUS_BIT_RATE_320 (0x600) +#define SAA7146_I2C_BUS_BIT_RATE_240 (0x700) +#define SAA7146_I2C_BUS_BIT_RATE_120 (0x000) +#define SAA7146_I2C_BUS_BIT_RATE_80 (0x200) +#define SAA7146_I2C_BUS_BIT_RATE_60 (0x300) + +static inline void SAA7146_IER_DISABLE(struct saa7146_dev *x, unsigned y) +{ + unsigned long flags; + spin_lock_irqsave(&x->int_slock, flags); + saa7146_write(x, IER, saa7146_read(x, IER) & ~y); + spin_unlock_irqrestore(&x->int_slock, flags); +} + +static inline void SAA7146_IER_ENABLE(struct saa7146_dev *x, unsigned y) +{ + unsigned long flags; + spin_lock_irqsave(&x->int_slock, flags); + saa7146_write(x, IER, saa7146_read(x, IER) | y); + spin_unlock_irqrestore(&x->int_slock, flags); +} + +#endif diff --git a/include/media/drv-intf/saa7146_vv.h b/include/media/drv-intf/saa7146_vv.h new file mode 100644 index 000000000000..635805fb35e8 --- /dev/null +++ b/include/media/drv-intf/saa7146_vv.h @@ -0,0 +1,266 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __SAA7146_VV__ +#define __SAA7146_VV__ + +#include <media/v4l2-common.h> +#include <media/v4l2-ioctl.h> +#include <media/v4l2-fh.h> +#include <media/drv-intf/saa7146.h> +#include <media/videobuf-dma-sg.h> + +#define MAX_SAA7146_CAPTURE_BUFFERS 32 /* arbitrary */ +#define BUFFER_TIMEOUT (HZ/2) /* 0.5 seconds */ + +#define WRITE_RPS0(x) do { \ + dev->d_rps0.cpu_addr[ count++ ] = cpu_to_le32(x); \ + } while (0); + +#define WRITE_RPS1(x) do { \ + dev->d_rps1.cpu_addr[ count++ ] = cpu_to_le32(x); \ + } while (0); + +struct saa7146_video_dma { + u32 base_odd; + u32 base_even; + u32 prot_addr; + u32 pitch; + u32 base_page; + u32 num_line_byte; +}; + +#define FORMAT_BYTE_SWAP 0x1 +#define FORMAT_IS_PLANAR 0x2 + +struct saa7146_format { + u32 pixelformat; + u32 trans; + u8 depth; + u8 flags; + u8 swap; +}; + +struct saa7146_standard +{ + char *name; + v4l2_std_id id; + + int v_offset; /* number of lines of vertical offset before processing */ + int v_field; /* number of lines in a field for HPS to process */ + + int h_offset; /* horizontal offset of processing window */ + int h_pixels; /* number of horizontal pixels to process */ + + int v_max_out; + int h_max_out; +}; + +/* buffer for one video/vbi frame */ +struct saa7146_buf { + /* common v4l buffer stuff -- must be first */ + struct videobuf_buffer vb; + + /* saa7146 specific */ + struct v4l2_pix_format *fmt; + int (*activate)(struct saa7146_dev *dev, + struct saa7146_buf *buf, + struct saa7146_buf *next); + + /* page tables */ + struct saa7146_pgtable pt[3]; +}; + +struct saa7146_dmaqueue { + struct saa7146_dev *dev; + struct saa7146_buf *curr; + struct list_head queue; + struct timer_list timeout; +}; + +struct saa7146_overlay { + struct saa7146_fh *fh; + struct v4l2_window win; + struct v4l2_clip clips[16]; + int nclips; +}; + +/* per open data */ +struct saa7146_fh { + /* Must be the first field! */ + struct v4l2_fh fh; + struct saa7146_dev *dev; + + /* video capture */ + struct videobuf_queue video_q; + + /* vbi capture */ + struct videobuf_queue vbi_q; + + unsigned int resources; /* resource management for device open */ +}; + +#define STATUS_OVERLAY 0x01 +#define STATUS_CAPTURE 0x02 + +struct saa7146_vv +{ + /* vbi capture */ + struct saa7146_dmaqueue vbi_dmaq; + struct v4l2_vbi_format vbi_fmt; + struct timer_list vbi_read_timeout; + struct file *vbi_read_timeout_file; + /* vbi workaround interrupt queue */ + wait_queue_head_t vbi_wq; + int vbi_fieldcount; + struct saa7146_fh *vbi_streaming; + + int video_status; + struct saa7146_fh *video_fh; + + /* video overlay */ + struct saa7146_overlay ov; + struct v4l2_framebuffer ov_fb; + struct saa7146_format *ov_fmt; + struct saa7146_fh *ov_suspend; + + /* video capture */ + struct saa7146_dmaqueue video_dmaq; + struct v4l2_pix_format video_fmt; + enum v4l2_field last_field; + + /* common: fixme? shouldn't this be in saa7146_fh? + (this leads to a more complicated question: shall the driver + store the different settings (for example S_INPUT) for every open + and restore it appropriately, or should all settings be common for + all opens? currently, we do the latter, like all other + drivers do... */ + struct saa7146_standard *standard; + + int vflip; + int hflip; + int current_hps_source; + int current_hps_sync; + + struct saa7146_dma d_clipping; /* pointer to clipping memory */ + + unsigned int resources; /* resource management for device */ +}; + +/* flags */ +#define SAA7146_USE_PORT_B_FOR_VBI 0x2 /* use input port b for vbi hardware bug workaround */ + +struct saa7146_ext_vv +{ + /* information about the video capabilities of the device */ + int inputs; + int audios; + u32 capabilities; + int flags; + + /* additionally supported transmission standards */ + struct saa7146_standard *stds; + int num_stds; + int (*std_callback)(struct saa7146_dev*, struct saa7146_standard *); + + /* the extension can override this */ + struct v4l2_ioctl_ops vid_ops; + struct v4l2_ioctl_ops vbi_ops; + /* pointer to the saa7146 core ops */ + const struct v4l2_ioctl_ops *core_ops; + + struct v4l2_file_operations vbi_fops; +}; + +struct saa7146_use_ops { + void (*init)(struct saa7146_dev *, struct saa7146_vv *); + int(*open)(struct saa7146_dev *, struct file *); + void (*release)(struct saa7146_dev *, struct file *); + void (*irq_done)(struct saa7146_dev *, unsigned long status); + ssize_t (*read)(struct file *, char __user *, size_t, loff_t *); +}; + +/* from saa7146_fops.c */ +int saa7146_register_device(struct video_device *vid, struct saa7146_dev *dev, char *name, int type); +int saa7146_unregister_device(struct video_device *vid, struct saa7146_dev *dev); +void saa7146_buffer_finish(struct saa7146_dev *dev, struct saa7146_dmaqueue *q, int state); +void saa7146_buffer_next(struct saa7146_dev *dev, struct saa7146_dmaqueue *q,int vbi); +int saa7146_buffer_queue(struct saa7146_dev *dev, struct saa7146_dmaqueue *q, struct saa7146_buf *buf); +void saa7146_buffer_timeout(struct timer_list *t); +void saa7146_dma_free(struct saa7146_dev* dev,struct videobuf_queue *q, + struct saa7146_buf *buf); + +int saa7146_vv_init(struct saa7146_dev* dev, struct saa7146_ext_vv *ext_vv); +int saa7146_vv_release(struct saa7146_dev* dev); + +/* from saa7146_hlp.c */ +int saa7146_enable_overlay(struct saa7146_fh *fh); +void saa7146_disable_overlay(struct saa7146_fh *fh); + +void saa7146_set_capture(struct saa7146_dev *dev, struct saa7146_buf *buf, struct saa7146_buf *next); +void saa7146_write_out_dma(struct saa7146_dev* dev, int which, struct saa7146_video_dma* vdma) ; +void saa7146_set_hps_source_and_sync(struct saa7146_dev *saa, int source, int sync); +void saa7146_set_gpio(struct saa7146_dev *saa, u8 pin, u8 data); + +/* from saa7146_video.c */ +extern const struct v4l2_ioctl_ops saa7146_video_ioctl_ops; +extern const struct v4l2_ioctl_ops saa7146_vbi_ioctl_ops; +extern const struct saa7146_use_ops saa7146_video_uops; +int saa7146_start_preview(struct saa7146_fh *fh); +int saa7146_stop_preview(struct saa7146_fh *fh); +long saa7146_video_do_ioctl(struct file *file, unsigned int cmd, void *arg); +int saa7146_s_ctrl(struct v4l2_ctrl *ctrl); + +/* from saa7146_vbi.c */ +extern const struct saa7146_use_ops saa7146_vbi_uops; + +/* resource management functions */ +int saa7146_res_get(struct saa7146_fh *fh, unsigned int bit); +void saa7146_res_free(struct saa7146_fh *fh, unsigned int bits); + +#define RESOURCE_DMA1_HPS 0x1 +#define RESOURCE_DMA2_CLP 0x2 +#define RESOURCE_DMA3_BRS 0x4 + +/* saa7146 source inputs */ +#define SAA7146_HPS_SOURCE_PORT_A 0x00 +#define SAA7146_HPS_SOURCE_PORT_B 0x01 +#define SAA7146_HPS_SOURCE_YPB_CPA 0x02 +#define SAA7146_HPS_SOURCE_YPA_CPB 0x03 + +/* sync inputs */ +#define SAA7146_HPS_SYNC_PORT_A 0x00 +#define SAA7146_HPS_SYNC_PORT_B 0x01 + +/* some memory sizes */ +/* max. 16 clipping rectangles */ +#define SAA7146_CLIPPING_MEM (16 * 4 * sizeof(u32)) + +/* some defines for the various clipping-modes */ +#define SAA7146_CLIPPING_RECT 0x4 +#define SAA7146_CLIPPING_RECT_INVERTED 0x5 +#define SAA7146_CLIPPING_MASK 0x6 +#define SAA7146_CLIPPING_MASK_INVERTED 0x7 + +/* output formats: each entry holds four information */ +#define RGB08_COMPOSED 0x0217 /* composed is used in the sense of "not-planar" */ +/* this means: planar?=0, yuv2rgb-conversation-mode=2, dither=yes(=1), format-mode = 7 */ +#define RGB15_COMPOSED 0x0213 +#define RGB16_COMPOSED 0x0210 +#define RGB24_COMPOSED 0x0201 +#define RGB32_COMPOSED 0x0202 + +#define Y8 0x0006 +#define YUV411_COMPOSED 0x0003 +#define YUV422_COMPOSED 0x0000 +/* this means: planar?=1, yuv2rgb-conversion-mode=0, dither=no(=0), format-mode = b */ +#define YUV411_DECOMPOSED 0x100b +#define YUV422_DECOMPOSED 0x1009 +#define YUV420_DECOMPOSED 0x100a + +#define IS_PLANAR(x) (x & 0xf000) + +/* misc defines */ +#define SAA7146_NO_SWAP (0x0) +#define SAA7146_TWO_BYTE_SWAP (0x1) +#define SAA7146_FOUR_BYTE_SWAP (0x2) + +#endif diff --git a/include/media/i2c/s5c73m3.h b/include/media/i2c/s5c73m3.h deleted file mode 100644 index df0769d64523..000000000000 --- a/include/media/i2c/s5c73m3.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Samsung LSI S5C73M3 8M pixel camera driver - * - * Copyright (C) 2012, Samsung Electronics, Co., Ltd. - * Sylwester Nawrocki <s.nawrocki@samsung.com> - * Andrzej Hajda <a.hajda@samsung.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ -#ifndef MEDIA_S5C73M3__ -#define MEDIA_S5C73M3__ - -#include <linux/videodev2.h> -#include <media/v4l2-mediabus.h> - -/** - * struct s5c73m3_platform_data - s5c73m3 driver platform data - * @mclk_frequency: sensor's master clock frequency in Hz - * @bus_type: bus type - * @nlanes: maximum number of MIPI-CSI lanes used - * @horiz_flip: default horizontal image flip value, non zero to enable - * @vert_flip: default vertical image flip value, non zero to enable - */ - -struct s5c73m3_platform_data { - unsigned long mclk_frequency; - - enum v4l2_mbus_type bus_type; - u8 nlanes; - u8 horiz_flip; - u8 vert_flip; -}; - -#endif /* MEDIA_S5C73M3__ */ diff --git a/include/media/media-entity.h b/include/media/media-entity.h index 85ed08ddee9d..741f9c629c6f 100644 --- a/include/media/media-entity.h +++ b/include/media/media-entity.h @@ -131,6 +131,26 @@ struct media_pipeline_pad { }; /** + * struct media_pipeline_pad_iter - Iterator for media_pipeline_for_each_pad + * + * @cursor: The current element + */ +struct media_pipeline_pad_iter { + struct list_head *cursor; +}; + +/** + * struct media_pipeline_entity_iter - Iterator for media_pipeline_for_each_entity + * + * @ent_enum: The entity enumeration tracker + * @cursor: The current element + */ +struct media_pipeline_entity_iter { + struct media_entity_enum ent_enum; + struct list_head *cursor; +}; + +/** * struct media_link - A link object part of a media graph. * * @graph_obj: Embedded structure containing the media object common data @@ -242,7 +262,9 @@ struct media_pad { * part of the same pipeline and enabling one of the pads * means that the other pad will become "locked" and * doesn't allow configuration changes. pad0 and pad1 are - * guaranteed to not both be sinks or sources. + * guaranteed to not both be sinks or sources. Never call + * the .has_pad_interdep() operation directly, always use + * media_entity_has_pad_interdep(). * Optional: If the operation isn't implemented all pads * will be considered as interdependent. * @@ -1066,6 +1088,8 @@ int media_entity_get_fwnode_pad(struct media_entity *entity, * @graph: Media graph structure that will be used to walk the graph * @mdev: Pointer to the &media_device that contains the object * + * This function is deprecated, use media_pipeline_for_each_pad() instead. + * * The caller is required to hold the media_device graph_mutex during the graph * walk until the graph state is released. * @@ -1078,6 +1102,8 @@ __must_check int media_graph_walk_init( * media_graph_walk_cleanup - Release resources used by graph walk. * * @graph: Media graph structure that will be used to walk the graph + * + * This function is deprecated, use media_pipeline_for_each_pad() instead. */ void media_graph_walk_cleanup(struct media_graph *graph); @@ -1088,6 +1114,8 @@ void media_graph_walk_cleanup(struct media_graph *graph); * @graph: Media graph structure that will be used to walk the graph * @entity: Starting entity * + * This function is deprecated, use media_pipeline_for_each_pad() instead. + * * Before using this function, media_graph_walk_init() must be * used to allocate resources used for walking the graph. This * function initializes the graph traversal structure to walk the @@ -1103,6 +1131,8 @@ void media_graph_walk_start(struct media_graph *graph, * media_graph_walk_next - Get the next entity in the graph * @graph: Media graph structure * + * This function is deprecated, use media_pipeline_for_each_pad() instead. + * * Perform a depth-first traversal of the given media entities graph. * * The graph structure must have been previously initialized with a call to @@ -1163,6 +1193,76 @@ void media_pipeline_stop(struct media_pad *pad); */ void __media_pipeline_stop(struct media_pad *pad); +struct media_pad * +__media_pipeline_pad_iter_next(struct media_pipeline *pipe, + struct media_pipeline_pad_iter *iter, + struct media_pad *pad); + +/** + * media_pipeline_for_each_pad - Iterate on all pads in a media pipeline + * @pipe: The pipeline + * @iter: The iterator (struct media_pipeline_pad_iter) + * @pad: The iterator pad + * + * Iterate on all pads in a media pipeline. This is only valid after the + * pipeline has been built with media_pipeline_start() and before it gets + * destroyed with media_pipeline_stop(). + */ +#define media_pipeline_for_each_pad(pipe, iter, pad) \ + for (pad = __media_pipeline_pad_iter_next((pipe), iter, NULL); \ + pad != NULL; \ + pad = __media_pipeline_pad_iter_next((pipe), iter, pad)) + +/** + * media_pipeline_entity_iter_init - Initialize a pipeline entity iterator + * @pipe: The pipeline + * @iter: The iterator + * + * This function must be called to initialize the iterator before using it in a + * media_pipeline_for_each_entity() loop. The iterator must be destroyed by a + * call to media_pipeline_entity_iter_cleanup after the loop (including in code + * paths that break from the loop). + * + * The same iterator can be used in multiple consecutive loops without being + * destroyed and reinitialized. + * + * Return: 0 on success or a negative error code otherwise. + */ +int media_pipeline_entity_iter_init(struct media_pipeline *pipe, + struct media_pipeline_entity_iter *iter); + +/** + * media_pipeline_entity_iter_cleanup - Destroy a pipeline entity iterator + * @iter: The iterator + * + * This function must be called to destroy iterators initialized with + * media_pipeline_entity_iter_init(). + */ +void media_pipeline_entity_iter_cleanup(struct media_pipeline_entity_iter *iter); + +struct media_entity * +__media_pipeline_entity_iter_next(struct media_pipeline *pipe, + struct media_pipeline_entity_iter *iter, + struct media_entity *entity); + +/** + * media_pipeline_for_each_entity - Iterate on all entities in a media pipeline + * @pipe: The pipeline + * @iter: The iterator (struct media_pipeline_entity_iter) + * @entity: The iterator entity + * + * Iterate on all entities in a media pipeline. This is only valid after the + * pipeline has been built with media_pipeline_start() and before it gets + * destroyed with media_pipeline_stop(). The iterator must be initialized with + * media_pipeline_entity_iter_init() before iteration, and destroyed with + * media_pipeline_entity_iter_cleanup() after (including in code paths that + * break from the loop). + */ +#define media_pipeline_for_each_entity(pipe, iter, entity) \ + for (entity = __media_pipeline_entity_iter_next((pipe), iter, NULL); \ + entity != NULL; \ + entity = __media_pipeline_entity_iter_next((pipe), iter, entity)) + /** * media_pipeline_alloc_start - Mark a pipeline as streaming * @pad: Starting pad diff --git a/include/media/ov_16bit_addr_reg_helpers.h b/include/media/ov_16bit_addr_reg_helpers.h new file mode 100644 index 000000000000..1c60a50bd795 --- /dev/null +++ b/include/media/ov_16bit_addr_reg_helpers.h @@ -0,0 +1,92 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * I2C register access helpers for Omnivision OVxxxx image sensors which expect + * a 16 bit register address in big-endian format and which have 1-3 byte + * wide registers, in big-endian format (for the higher width registers). + * + * Based on the register helpers from drivers/media/i2c/ov2680.c which is: + * Copyright (C) 2018 Linaro Ltd + */ +#ifndef __OV_16BIT_ADDR_REG_HELPERS_H +#define __OV_16BIT_ADDR_REG_HELPERS_H + +#include <asm/unaligned.h> +#include <linux/dev_printk.h> +#include <linux/i2c.h> + +static inline int ov_read_reg(struct i2c_client *client, u16 reg, + unsigned int len, u32 *val) +{ + u8 addr_buf[2], data_buf[4] = { }; + struct i2c_msg msgs[2]; + int ret; + + if (len > 4) + return -EINVAL; + + put_unaligned_be16(reg, addr_buf); + + msgs[0].addr = client->addr; + msgs[0].flags = 0; + msgs[0].len = ARRAY_SIZE(addr_buf); + msgs[0].buf = addr_buf; + + msgs[1].addr = client->addr; + msgs[1].flags = I2C_M_RD; + msgs[1].len = len; + msgs[1].buf = &data_buf[4 - len]; + + ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); + if (ret != ARRAY_SIZE(msgs)) { + dev_err(&client->dev, "read error: reg=0x%4x: %d\n", reg, ret); + return -EIO; + } + + *val = get_unaligned_be32(data_buf); + + return 0; +} + +#define ov_read_reg8(s, r, v) ov_read_reg(s, r, 1, v) +#define ov_read_reg16(s, r, v) ov_read_reg(s, r, 2, v) +#define ov_read_reg24(s, r, v) ov_read_reg(s, r, 3, v) + +static inline int ov_write_reg(struct i2c_client *client, u16 reg, + unsigned int len, u32 val) +{ + u8 buf[6]; + int ret; + + if (len > 4) + return -EINVAL; + + put_unaligned_be16(reg, buf); + put_unaligned_be32(val << (8 * (4 - len)), buf + 2); + ret = i2c_master_send(client, buf, len + 2); + if (ret != len + 2) { + dev_err(&client->dev, "write error: reg=0x%4x: %d\n", reg, ret); + return -EIO; + } + + return 0; +} + +#define ov_write_reg8(s, r, v) ov_write_reg(s, r, 1, v) +#define ov_write_reg16(s, r, v) ov_write_reg(s, r, 2, v) +#define ov_write_reg24(s, r, v) ov_write_reg(s, r, 3, v) + +static inline int ov_update_reg(struct i2c_client *client, u16 reg, u8 mask, u8 val) +{ + u32 readval; + int ret; + + ret = ov_read_reg8(client, reg, &readval); + if (ret < 0) + return ret; + + val = (readval & ~mask) | (val & mask); + + return ov_write_reg8(client, reg, val); +} + +#endif diff --git a/include/media/v4l2-subdev.h b/include/media/v4l2-subdev.h index f3fe9b6e26d4..7245887ef002 100644 --- a/include/media/v4l2-subdev.h +++ b/include/media/v4l2-subdev.h @@ -346,6 +346,7 @@ enum v4l2_mbus_frame_desc_flags { * struct v4l2_mbus_frame_desc_entry - media bus frame description structure * * @flags: bitmask flags, as defined by &enum v4l2_mbus_frame_desc_flags. + * @stream: stream in routing configuration * @pixelcode: media bus pixel code, valid if @flags * %FRAME_DESC_FL_BLOB is not set. * @length: number of octets per frame, valid if @flags @@ -355,6 +356,7 @@ enum v4l2_mbus_frame_desc_flags { */ struct v4l2_mbus_frame_desc_entry { enum v4l2_mbus_frame_desc_flags flags; + u32 stream; u32 pixelcode; u32 length; union { @@ -702,11 +704,59 @@ struct v4l2_subdev_pad_config { }; /** + * struct v4l2_subdev_stream_config - Used for storing stream configuration. + * + * @pad: pad number + * @stream: stream number + * @enabled: has the stream been enabled with v4l2_subdev_enable_stream() + * @fmt: &struct v4l2_mbus_framefmt + * @crop: &struct v4l2_rect to be used for crop + * @compose: &struct v4l2_rect to be used for compose + * + * This structure stores configuration for a stream. + */ +struct v4l2_subdev_stream_config { + u32 pad; + u32 stream; + bool enabled; + + struct v4l2_mbus_framefmt fmt; + struct v4l2_rect crop; + struct v4l2_rect compose; +}; + +/** + * struct v4l2_subdev_stream_configs - A collection of stream configs. + * + * @num_configs: number of entries in @config. + * @configs: an array of &struct v4l2_subdev_stream_configs. + */ +struct v4l2_subdev_stream_configs { + u32 num_configs; + struct v4l2_subdev_stream_config *configs; +}; + +/** + * struct v4l2_subdev_krouting - subdev routing table + * + * @num_routes: number of routes + * @routes: &struct v4l2_subdev_route + * + * This structure contains the routing table for a subdev. + */ +struct v4l2_subdev_krouting { + unsigned int num_routes; + struct v4l2_subdev_route *routes; +}; + +/** * struct v4l2_subdev_state - Used for storing subdev state information. * * @_lock: default for 'lock' * @lock: mutex for the state. May be replaced by the user. * @pads: &struct v4l2_subdev_pad_config array + * @routing: routing table for the subdev + * @stream_configs: stream configurations (only for V4L2_SUBDEV_FL_STREAMS) * * This structure only needs to be passed to the pad op if the 'which' field * of the main argument is set to %V4L2_SUBDEV_FORMAT_TRY. For @@ -717,6 +767,8 @@ struct v4l2_subdev_state { struct mutex _lock; struct mutex *lock; struct v4l2_subdev_pad_config *pads; + struct v4l2_subdev_krouting routing; + struct v4l2_subdev_stream_configs stream_configs; }; /** @@ -769,6 +821,21 @@ struct v4l2_subdev_state { * this operation as close as possible to stream on time. The * operation shall fail if the pad index it has been called on * is not valid or in case of unrecoverable failures. + * + * @set_routing: enable or disable data connection routes described in the + * subdevice routing table. + * + * @enable_streams: Enable the streams defined in streams_mask on the given + * source pad. Subdevs that implement this operation must use the active + * state management provided by the subdev core (enabled through a call to + * v4l2_subdev_init_finalize() at initialization time). Do not call + * directly, use v4l2_subdev_enable_streams() instead. + * + * @disable_streams: Disable the streams defined in streams_mask on the given + * source pad. Subdevs that implement this operation must use the active + * state management provided by the subdev core (enabled through a call to + * v4l2_subdev_init_finalize() at initialization time). Do not call + * directly, use v4l2_subdev_disable_streams() instead. */ struct v4l2_subdev_pad_ops { int (*init_cfg)(struct v4l2_subdev *sd, @@ -811,6 +878,16 @@ struct v4l2_subdev_pad_ops { struct v4l2_mbus_frame_desc *fd); int (*get_mbus_config)(struct v4l2_subdev *sd, unsigned int pad, struct v4l2_mbus_config *config); + int (*set_routing)(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state, + enum v4l2_subdev_format_whence which, + struct v4l2_subdev_krouting *route); + int (*enable_streams)(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state, u32 pad, + u64 streams_mask); + int (*disable_streams)(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state, u32 pad, + u64 streams_mask); }; /** @@ -885,6 +962,17 @@ struct v4l2_subdev_internal_ops { * should set this flag. */ #define V4L2_SUBDEV_FL_HAS_EVENTS (1U << 3) +/* + * Set this flag if this subdev supports multiplexed streams. This means + * that the driver supports routing and handles the stream parameter in its + * v4l2_subdev_pad_ops handlers. More specifically, this means: + * + * - Centrally managed subdev active state is enabled + * - Legacy pad config is _not_ supported (state->pads is NULL) + * - Routing ioctls are available + * - Multiple streams per pad are supported + */ +#define V4L2_SUBDEV_FL_STREAMS (1U << 4) struct regulator_bulk_data; @@ -946,6 +1034,10 @@ struct v4l2_subdev_platform_data { * @active_state: Active state for the subdev (NULL for subdevs tracking the * state internally). Initialized by calling * v4l2_subdev_init_finalize(). + * @enabled_streams: Bitmask of enabled streams used by + * v4l2_subdev_enable_streams() and + * v4l2_subdev_disable_streams() helper functions for fallback + * cases. * * Each instance of a subdev driver should create this struct, either * stand-alone or embedded in a larger struct. @@ -993,6 +1085,7 @@ struct v4l2_subdev { * doesn't support it. */ struct v4l2_subdev_state *active_state; + u64 enabled_streams; }; @@ -1218,6 +1311,24 @@ int v4l2_subdev_link_validate_default(struct v4l2_subdev *sd, int v4l2_subdev_link_validate(struct media_link *link); /** + * v4l2_subdev_has_pad_interdep - MC has_pad_interdep implementation for subdevs + * + * @entity: pointer to &struct media_entity + * @pad0: pad number for the first pad + * @pad1: pad number for the second pad + * + * This function is an implementation of the + * media_entity_operations.has_pad_interdep operation for subdevs that + * implement the multiplexed streams API (as indicated by the + * V4L2_SUBDEV_FL_STREAMS subdev flag). + * + * It considers two pads interdependent if there is an active route between pad0 + * and pad1. + */ +bool v4l2_subdev_has_pad_interdep(struct media_entity *entity, + unsigned int pad0, unsigned int pad1); + +/** * __v4l2_subdev_state_alloc - allocate v4l2_subdev_state * * @sd: pointer to &struct v4l2_subdev for which the state is being allocated. @@ -1377,6 +1488,272 @@ v4l2_subdev_lock_and_get_active_state(struct v4l2_subdev *sd) int v4l2_subdev_get_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_state *state, struct v4l2_subdev_format *format); +/** + * v4l2_subdev_set_routing() - Set given routing to subdev state + * @sd: The subdevice + * @state: The subdevice state + * @routing: Routing that will be copied to subdev state + * + * This will release old routing table (if any) from the state, allocate + * enough space for the given routing, and copy the routing. + * + * This can be used from the subdev driver's set_routing op, after validating + * the routing. + */ +int v4l2_subdev_set_routing(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state, + const struct v4l2_subdev_krouting *routing); + +struct v4l2_subdev_route * +__v4l2_subdev_next_active_route(const struct v4l2_subdev_krouting *routing, + struct v4l2_subdev_route *route); + +/** + * for_each_active_route - iterate on all active routes of a routing table + * @routing: The routing table + * @route: The route iterator + */ +#define for_each_active_route(routing, route) \ + for ((route) = NULL; \ + ((route) = __v4l2_subdev_next_active_route((routing), (route)));) + +/** + * v4l2_subdev_set_routing_with_fmt() - Set given routing and format to subdev + * state + * @sd: The subdevice + * @state: The subdevice state + * @routing: Routing that will be copied to subdev state + * @fmt: Format used to initialize all the streams + * + * This is the same as v4l2_subdev_set_routing, but additionally initializes + * all the streams using the given format. + */ +int v4l2_subdev_set_routing_with_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state, + struct v4l2_subdev_krouting *routing, + const struct v4l2_mbus_framefmt *fmt); + +/** + * v4l2_subdev_state_get_stream_format() - Get pointer to a stream format + * @state: subdevice state + * @pad: pad id + * @stream: stream id + * + * This returns a pointer to &struct v4l2_mbus_framefmt for the given pad + + * stream in the subdev state. + * + * If the state does not contain the given pad + stream, NULL is returned. + */ +struct v4l2_mbus_framefmt * +v4l2_subdev_state_get_stream_format(struct v4l2_subdev_state *state, + unsigned int pad, u32 stream); + +/** + * v4l2_subdev_state_get_stream_crop() - Get pointer to a stream crop rectangle + * @state: subdevice state + * @pad: pad id + * @stream: stream id + * + * This returns a pointer to crop rectangle for the given pad + stream in the + * subdev state. + * + * If the state does not contain the given pad + stream, NULL is returned. + */ +struct v4l2_rect * +v4l2_subdev_state_get_stream_crop(struct v4l2_subdev_state *state, + unsigned int pad, u32 stream); + +/** + * v4l2_subdev_state_get_stream_compose() - Get pointer to a stream compose + * rectangle + * @state: subdevice state + * @pad: pad id + * @stream: stream id + * + * This returns a pointer to compose rectangle for the given pad + stream in the + * subdev state. + * + * If the state does not contain the given pad + stream, NULL is returned. + */ +struct v4l2_rect * +v4l2_subdev_state_get_stream_compose(struct v4l2_subdev_state *state, + unsigned int pad, u32 stream); + +/** + * v4l2_subdev_routing_find_opposite_end() - Find the opposite stream + * @routing: routing used to find the opposite side + * @pad: pad id + * @stream: stream id + * @other_pad: pointer used to return the opposite pad + * @other_stream: pointer used to return the opposite stream + * + * This function uses the routing table to find the pad + stream which is + * opposite the given pad + stream. + * + * @other_pad and/or @other_stream can be NULL if the caller does not need the + * value. + * + * Returns 0 on success, or -EINVAL if no matching route is found. + */ +int v4l2_subdev_routing_find_opposite_end(const struct v4l2_subdev_krouting *routing, + u32 pad, u32 stream, u32 *other_pad, + u32 *other_stream); + +/** + * v4l2_subdev_state_get_opposite_stream_format() - Get pointer to opposite + * stream format + * @state: subdevice state + * @pad: pad id + * @stream: stream id + * + * This returns a pointer to &struct v4l2_mbus_framefmt for the pad + stream + * that is opposite the given pad + stream in the subdev state. + * + * If the state does not contain the given pad + stream, NULL is returned. + */ +struct v4l2_mbus_framefmt * +v4l2_subdev_state_get_opposite_stream_format(struct v4l2_subdev_state *state, + u32 pad, u32 stream); + +/** + * v4l2_subdev_state_xlate_streams() - Translate streams from one pad to another + * + * @state: Subdevice state + * @pad0: The first pad + * @pad1: The second pad + * @streams: Streams bitmask on the first pad + * + * Streams on sink pads of a subdev are routed to source pads as expressed in + * the subdev state routing table. Stream numbers don't necessarily match on + * the sink and source side of a route. This function translates stream numbers + * on @pad0, expressed as a bitmask in @streams, to the corresponding streams + * on @pad1 using the routing table from the @state. It returns the stream mask + * on @pad1, and updates @streams with the streams that have been found in the + * routing table. + * + * @pad0 and @pad1 must be a sink and a source, in any order. + * + * Return: The bitmask of streams of @pad1 that are routed to @streams on @pad0. + */ +u64 v4l2_subdev_state_xlate_streams(const struct v4l2_subdev_state *state, + u32 pad0, u32 pad1, u64 *streams); + +/** + * enum v4l2_subdev_routing_restriction - Subdevice internal routing restrictions + * + * @V4L2_SUBDEV_ROUTING_NO_1_TO_N: + * an input stream may not be routed to multiple output streams (stream + * duplication) + * @V4L2_SUBDEV_ROUTING_NO_N_TO_1: + * multiple input streams may not be routed to the same output stream + * (stream merging) + * @V4L2_SUBDEV_ROUTING_NO_STREAM_MIX: + * streams on the same pad may not be routed to streams on different pads + * @V4L2_SUBDEV_ROUTING_ONLY_1_TO_1: + * only non-overlapping 1-to-1 stream routing is allowed (a combination of + * @V4L2_SUBDEV_ROUTING_NO_1_TO_N and @V4L2_SUBDEV_ROUTING_NO_N_TO_1) + */ +enum v4l2_subdev_routing_restriction { + V4L2_SUBDEV_ROUTING_NO_1_TO_N = BIT(0), + V4L2_SUBDEV_ROUTING_NO_N_TO_1 = BIT(1), + V4L2_SUBDEV_ROUTING_NO_STREAM_MIX = BIT(2), + V4L2_SUBDEV_ROUTING_ONLY_1_TO_1 = + V4L2_SUBDEV_ROUTING_NO_1_TO_N | + V4L2_SUBDEV_ROUTING_NO_N_TO_1, +}; + +/** + * v4l2_subdev_routing_validate() - Verify that routes comply with driver + * constraints + * @sd: The subdevice + * @routing: Routing to verify + * @disallow: Restrictions on routes + * + * This verifies that the given routing complies with the @disallow constraints. + * + * Returns 0 on success, error value otherwise. + */ +int v4l2_subdev_routing_validate(struct v4l2_subdev *sd, + const struct v4l2_subdev_krouting *routing, + enum v4l2_subdev_routing_restriction disallow); + +/** + * v4l2_subdev_enable_streams() - Enable streams on a pad + * @sd: The subdevice + * @pad: The pad + * @streams_mask: Bitmask of streams to enable + * + * This function enables streams on a source @pad of a subdevice. The pad is + * identified by its index, while the streams are identified by the + * @streams_mask bitmask. This allows enabling multiple streams on a pad at + * once. + * + * Enabling a stream that is already enabled isn't allowed. If @streams_mask + * contains an already enabled stream, this function returns -EALREADY without + * performing any operation. + * + * Per-stream enable is only available for subdevs that implement the + * .enable_streams() and .disable_streams() operations. For other subdevs, this + * function implements a best-effort compatibility by calling the .s_stream() + * operation, limited to subdevs that have a single source pad. + * + * Return: + * * 0: Success + * * -EALREADY: One of the streams in streams_mask is already enabled + * * -EINVAL: The pad index is invalid, or doesn't correspond to a source pad + * * -EOPNOTSUPP: Falling back to the legacy .s_stream() operation is + * impossible because the subdev has multiple source pads + */ +int v4l2_subdev_enable_streams(struct v4l2_subdev *sd, u32 pad, + u64 streams_mask); + +/** + * v4l2_subdev_disable_streams() - Disable streams on a pad + * @sd: The subdevice + * @pad: The pad + * @streams_mask: Bitmask of streams to disable + * + * This function disables streams on a source @pad of a subdevice. The pad is + * identified by its index, while the streams are identified by the + * @streams_mask bitmask. This allows disabling multiple streams on a pad at + * once. + * + * Disabling a streams that is not enabled isn't allowed. If @streams_mask + * contains a disabled stream, this function returns -EALREADY without + * performing any operation. + * + * Per-stream disable is only available for subdevs that implement the + * .enable_streams() and .disable_streams() operations. For other subdevs, this + * function implements a best-effort compatibility by calling the .s_stream() + * operation, limited to subdevs that have a single source pad. + * + * Return: + * * 0: Success + * * -EALREADY: One of the streams in streams_mask is not enabled + * * -EINVAL: The pad index is invalid, or doesn't correspond to a source pad + * * -EOPNOTSUPP: Falling back to the legacy .s_stream() operation is + * impossible because the subdev has multiple source pads + */ +int v4l2_subdev_disable_streams(struct v4l2_subdev *sd, u32 pad, + u64 streams_mask); + +/** + * v4l2_subdev_s_stream_helper() - Helper to implement the subdev s_stream + * operation using enable_streams and disable_streams + * @sd: The subdevice + * @enable: Enable or disable streaming + * + * Subdevice drivers that implement the streams-aware + * &v4l2_subdev_pad_ops.enable_streams and &v4l2_subdev_pad_ops.disable_streams + * operations can use this helper to implement the legacy + * &v4l2_subdev_video_ops.s_stream operation. + * + * This helper can only be used by subdevs that have a single source pad. + * + * Return: 0 on success, or a negative error code otherwise. + */ +int v4l2_subdev_s_stream_helper(struct v4l2_subdev *sd, int enable); + #endif /* CONFIG_VIDEO_V4L2_SUBDEV_API */ #endif /* CONFIG_MEDIA_CONTROLLER */ diff --git a/include/memory/renesas-rpc-if.h b/include/memory/renesas-rpc-if.h index 862eff613dc7..b8fa30fd6b50 100644 --- a/include/memory/renesas-rpc-if.h +++ b/include/memory/renesas-rpc-if.h @@ -65,41 +65,15 @@ enum rpcif_type { struct rpcif { struct device *dev; - void __iomem *base; void __iomem *dirmap; - struct regmap *regmap; - struct reset_control *rstc; size_t size; - enum rpcif_type type; - enum rpcif_data_dir dir; - u8 bus_size; - u8 xfer_size; - void *buffer; - u32 xferlen; - u32 smcr; - u32 smadr; - u32 command; /* DRCMR or SMCMR */ - u32 option; /* DROPR or SMOPR */ - u32 enable; /* DRENR or SMENR */ - u32 dummy; /* DRDMCR or SMDMCR */ - u32 ddr; /* DRDRENR or SMDRENR */ }; int rpcif_sw_init(struct rpcif *rpc, struct device *dev); -int rpcif_hw_init(struct rpcif *rpc, bool hyperflash); -void rpcif_prepare(struct rpcif *rpc, const struct rpcif_op *op, u64 *offs, +int rpcif_hw_init(struct device *dev, bool hyperflash); +void rpcif_prepare(struct device *dev, const struct rpcif_op *op, u64 *offs, size_t *len); -int rpcif_manual_xfer(struct rpcif *rpc); -ssize_t rpcif_dirmap_read(struct rpcif *rpc, u64 offs, size_t len, void *buf); - -static inline void rpcif_enable_rpm(struct rpcif *rpc) -{ - pm_runtime_enable(rpc->dev); -} - -static inline void rpcif_disable_rpm(struct rpcif *rpc) -{ - pm_runtime_disable(rpc->dev); -} +int rpcif_manual_xfer(struct device *dev); +ssize_t rpcif_dirmap_read(struct device *dev, u64 offs, size_t len, void *buf); #endif // __RENESAS_RPC_IF_H diff --git a/include/net/netns/conntrack.h b/include/net/netns/conntrack.h index e1290c159184..1f463b3957c7 100644 --- a/include/net/netns/conntrack.h +++ b/include/net/netns/conntrack.h @@ -95,7 +95,6 @@ struct nf_ip_net { struct netns_ct { #ifdef CONFIG_NF_CONNTRACK_EVENTS - u8 ctnetlink_has_listener; bool ecache_dwork_pending; #endif u8 sysctl_log_invalid; /* Log invalid packets */ diff --git a/include/net/sctp/structs.h b/include/net/sctp/structs.h index afa3781e3ca2..e1f6e7fc2b11 100644 --- a/include/net/sctp/structs.h +++ b/include/net/sctp/structs.h @@ -1412,6 +1412,7 @@ struct sctp_stream_priorities { /* The next stream in line */ struct sctp_stream_out_ext *next; __u16 prio; + __u16 users; }; struct sctp_stream_out_ext { diff --git a/include/rdma/ib_sa.h b/include/rdma/ib_sa.h index e930bec33b31..b46353fc53bf 100644 --- a/include/rdma/ib_sa.h +++ b/include/rdma/ib_sa.h @@ -414,7 +414,7 @@ int ib_sa_path_rec_get(struct ib_sa_client *client, struct ib_device *device, ib_sa_comp_mask comp_mask, unsigned long timeout_ms, gfp_t gfp_mask, void (*callback)(int status, struct sa_path_rec *resp, - int num_prs, void *context), + unsigned int num_prs, void *context), void *context, struct ib_sa_query **query); struct ib_sa_multicast { diff --git a/include/rdma/ib_umem.h b/include/rdma/ib_umem.h index 92a673cd9b4f..95896472a82b 100644 --- a/include/rdma/ib_umem.h +++ b/include/rdma/ib_umem.h @@ -25,7 +25,6 @@ struct ib_umem { u32 writable : 1; u32 is_odp : 1; u32 is_dmabuf : 1; - struct work_struct work; struct sg_append_table sgt_append; }; diff --git a/include/rdma/ib_verbs.h b/include/rdma/ib_verbs.h index a9a429172c0a..949cf4ffc536 100644 --- a/include/rdma/ib_verbs.h +++ b/include/rdma/ib_verbs.h @@ -1168,7 +1168,7 @@ enum ib_qp_create_flags { */ struct ib_qp_init_attr { - /* Consumer's event_handler callback must not block */ + /* This callback occurs in workqueue context */ void (*event_handler)(struct ib_event *, void *); void *qp_context; diff --git a/include/rdma/rdma_cm.h b/include/rdma/rdma_cm.h index cdc7cafab572..8a8ab2f793ab 100644 --- a/include/rdma/rdma_cm.h +++ b/include/rdma/rdma_cm.h @@ -49,7 +49,6 @@ struct rdma_addr { struct rdma_dev_addr dev_addr; }; -#define RDMA_PRIMARY_PATH_MAX_REC_NUM 3 struct rdma_route { struct rdma_addr addr; struct sa_path_rec *path_rec; diff --git a/include/rdma/restrack.h b/include/rdma/restrack.h index 79d109c47242..8b7c46daeb07 100644 --- a/include/rdma/restrack.h +++ b/include/rdma/restrack.h @@ -162,8 +162,8 @@ struct rdma_restrack_entry *rdma_restrack_get_byid(struct ib_device *dev, * rdma_restrack_no_track() - don't add resource to the DB * @res: resource entry * - * Every user of thie API should be cross examined. - * Probaby you don't need to use this function. + * Every user of this API should be cross examined. + * Probably you don't need to use this function. */ static inline void rdma_restrack_no_track(struct rdma_restrack_entry *res) { diff --git a/include/trace/events/cxl.h b/include/trace/events/cxl.h deleted file mode 100644 index ad085a2534ef..000000000000 --- a/include/trace/events/cxl.h +++ /dev/null @@ -1,112 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#undef TRACE_SYSTEM -#define TRACE_SYSTEM cxl - -#if !defined(_CXL_EVENTS_H) || defined(TRACE_HEADER_MULTI_READ) -#define _CXL_EVENTS_H - -#include <linux/tracepoint.h> - -#define CXL_HEADERLOG_SIZE SZ_512 -#define CXL_HEADERLOG_SIZE_U32 SZ_512 / sizeof(u32) - -#define CXL_RAS_UC_CACHE_DATA_PARITY BIT(0) -#define CXL_RAS_UC_CACHE_ADDR_PARITY BIT(1) -#define CXL_RAS_UC_CACHE_BE_PARITY BIT(2) -#define CXL_RAS_UC_CACHE_DATA_ECC BIT(3) -#define CXL_RAS_UC_MEM_DATA_PARITY BIT(4) -#define CXL_RAS_UC_MEM_ADDR_PARITY BIT(5) -#define CXL_RAS_UC_MEM_BE_PARITY BIT(6) -#define CXL_RAS_UC_MEM_DATA_ECC BIT(7) -#define CXL_RAS_UC_REINIT_THRESH BIT(8) -#define CXL_RAS_UC_RSVD_ENCODE BIT(9) -#define CXL_RAS_UC_POISON BIT(10) -#define CXL_RAS_UC_RECV_OVERFLOW BIT(11) -#define CXL_RAS_UC_INTERNAL_ERR BIT(14) -#define CXL_RAS_UC_IDE_TX_ERR BIT(15) -#define CXL_RAS_UC_IDE_RX_ERR BIT(16) - -#define show_uc_errs(status) __print_flags(status, " | ", \ - { CXL_RAS_UC_CACHE_DATA_PARITY, "Cache Data Parity Error" }, \ - { CXL_RAS_UC_CACHE_ADDR_PARITY, "Cache Address Parity Error" }, \ - { CXL_RAS_UC_CACHE_BE_PARITY, "Cache Byte Enable Parity Error" }, \ - { CXL_RAS_UC_CACHE_DATA_ECC, "Cache Data ECC Error" }, \ - { CXL_RAS_UC_MEM_DATA_PARITY, "Memory Data Parity Error" }, \ - { CXL_RAS_UC_MEM_ADDR_PARITY, "Memory Address Parity Error" }, \ - { CXL_RAS_UC_MEM_BE_PARITY, "Memory Byte Enable Parity Error" }, \ - { CXL_RAS_UC_MEM_DATA_ECC, "Memory Data ECC Error" }, \ - { CXL_RAS_UC_REINIT_THRESH, "REINIT Threshold Hit" }, \ - { CXL_RAS_UC_RSVD_ENCODE, "Received Unrecognized Encoding" }, \ - { CXL_RAS_UC_POISON, "Received Poison From Peer" }, \ - { CXL_RAS_UC_RECV_OVERFLOW, "Receiver Overflow" }, \ - { CXL_RAS_UC_INTERNAL_ERR, "Component Specific Error" }, \ - { CXL_RAS_UC_IDE_TX_ERR, "IDE Tx Error" }, \ - { CXL_RAS_UC_IDE_RX_ERR, "IDE Rx Error" } \ -) - -TRACE_EVENT(cxl_aer_uncorrectable_error, - TP_PROTO(const struct device *dev, u32 status, u32 fe, u32 *hl), - TP_ARGS(dev, status, fe, hl), - TP_STRUCT__entry( - __string(dev_name, dev_name(dev)) - __field(u32, status) - __field(u32, first_error) - __array(u32, header_log, CXL_HEADERLOG_SIZE_U32) - ), - TP_fast_assign( - __assign_str(dev_name, dev_name(dev)); - __entry->status = status; - __entry->first_error = fe; - /* - * Embed the 512B headerlog data for user app retrieval and - * parsing, but no need to print this in the trace buffer. - */ - memcpy(__entry->header_log, hl, CXL_HEADERLOG_SIZE); - ), - TP_printk("%s: status: '%s' first_error: '%s'", - __get_str(dev_name), - show_uc_errs(__entry->status), - show_uc_errs(__entry->first_error) - ) -); - -#define CXL_RAS_CE_CACHE_DATA_ECC BIT(0) -#define CXL_RAS_CE_MEM_DATA_ECC BIT(1) -#define CXL_RAS_CE_CRC_THRESH BIT(2) -#define CLX_RAS_CE_RETRY_THRESH BIT(3) -#define CXL_RAS_CE_CACHE_POISON BIT(4) -#define CXL_RAS_CE_MEM_POISON BIT(5) -#define CXL_RAS_CE_PHYS_LAYER_ERR BIT(6) - -#define show_ce_errs(status) __print_flags(status, " | ", \ - { CXL_RAS_CE_CACHE_DATA_ECC, "Cache Data ECC Error" }, \ - { CXL_RAS_CE_MEM_DATA_ECC, "Memory Data ECC Error" }, \ - { CXL_RAS_CE_CRC_THRESH, "CRC Threshold Hit" }, \ - { CLX_RAS_CE_RETRY_THRESH, "Retry Threshold" }, \ - { CXL_RAS_CE_CACHE_POISON, "Received Cache Poison From Peer" }, \ - { CXL_RAS_CE_MEM_POISON, "Received Memory Poison From Peer" }, \ - { CXL_RAS_CE_PHYS_LAYER_ERR, "Received Error From Physical Layer" } \ -) - -TRACE_EVENT(cxl_aer_correctable_error, - TP_PROTO(const struct device *dev, u32 status), - TP_ARGS(dev, status), - TP_STRUCT__entry( - __string(dev_name, dev_name(dev)) - __field(u32, status) - ), - TP_fast_assign( - __assign_str(dev_name, dev_name(dev)); - __entry->status = status; - ), - TP_printk("%s: status: '%s'", - __get_str(dev_name), show_ce_errs(__entry->status) - ) -); - -#endif /* _CXL_EVENTS_H */ - -/* This part must be outside protection */ -#undef TRACE_INCLUDE_FILE -#define TRACE_INCLUDE_FILE cxl -#include <trace/define_trace.h> diff --git a/include/trace/events/f2fs.h b/include/trace/events/f2fs.h index 31d994e6b4ca..1322d34a5dfc 100644 --- a/include/trace/events/f2fs.h +++ b/include/trace/events/f2fs.h @@ -569,10 +569,10 @@ TRACE_EVENT(f2fs_file_write_iter, ); TRACE_EVENT(f2fs_map_blocks, - TP_PROTO(struct inode *inode, struct f2fs_map_blocks *map, - int create, int flag, int ret), + TP_PROTO(struct inode *inode, struct f2fs_map_blocks *map, int flag, + int ret), - TP_ARGS(inode, map, create, flag, ret), + TP_ARGS(inode, map, flag, ret), TP_STRUCT__entry( __field(dev_t, dev) @@ -584,7 +584,6 @@ TRACE_EVENT(f2fs_map_blocks, __field(int, m_seg_type) __field(bool, m_may_create) __field(bool, m_multidev_dio) - __field(int, create) __field(int, flag) __field(int, ret) ), @@ -599,7 +598,6 @@ TRACE_EVENT(f2fs_map_blocks, __entry->m_seg_type = map->m_seg_type; __entry->m_may_create = map->m_may_create; __entry->m_multidev_dio = map->m_multidev_dio; - __entry->create = create; __entry->flag = flag; __entry->ret = ret; ), @@ -607,7 +605,7 @@ TRACE_EVENT(f2fs_map_blocks, TP_printk("dev = (%d,%d), ino = %lu, file offset = %llu, " "start blkaddr = 0x%llx, len = 0x%llx, flags = %u, " "seg_type = %d, may_create = %d, multidevice = %d, " - "create = %d, flag = %d, err = %d", + "flag = %d, err = %d", show_dev_ino(__entry), (unsigned long long)__entry->m_lblk, (unsigned long long)__entry->m_pblk, @@ -616,7 +614,6 @@ TRACE_EVENT(f2fs_map_blocks, __entry->m_seg_type, __entry->m_may_create, __entry->m_multidev_dio, - __entry->create, __entry->flag, __entry->ret) ); @@ -1293,6 +1290,43 @@ DEFINE_EVENT(f2fs__page, f2fs_vm_page_mkwrite, TP_ARGS(page, type) ); +TRACE_EVENT(f2fs_replace_atomic_write_block, + + TP_PROTO(struct inode *inode, struct inode *cow_inode, pgoff_t index, + block_t old_addr, block_t new_addr, bool recovery), + + TP_ARGS(inode, cow_inode, index, old_addr, new_addr, recovery), + + TP_STRUCT__entry( + __field(dev_t, dev) + __field(ino_t, ino) + __field(ino_t, cow_ino) + __field(pgoff_t, index) + __field(block_t, old_addr) + __field(block_t, new_addr) + __field(bool, recovery) + ), + + TP_fast_assign( + __entry->dev = inode->i_sb->s_dev; + __entry->ino = inode->i_ino; + __entry->cow_ino = cow_inode->i_ino; + __entry->index = index; + __entry->old_addr = old_addr; + __entry->new_addr = new_addr; + __entry->recovery = recovery; + ), + + TP_printk("dev = (%d,%d), ino = %lu, cow_ino = %lu, index = %lu, " + "old_addr = 0x%llx, new_addr = 0x%llx, recovery = %d", + show_dev_ino(__entry), + __entry->cow_ino, + (unsigned long)__entry->index, + (unsigned long long)__entry->old_addr, + (unsigned long long)__entry->new_addr, + __entry->recovery) +); + TRACE_EVENT(f2fs_filemap_fault, TP_PROTO(struct inode *inode, pgoff_t index, unsigned long ret), @@ -1975,7 +2009,7 @@ TRACE_EVENT(f2fs_iostat, __entry->fs_cdrio = iostat[FS_CDATA_READ_IO]; __entry->fs_nrio = iostat[FS_NODE_READ_IO]; __entry->fs_mrio = iostat[FS_META_READ_IO]; - __entry->fs_discard = iostat[FS_DISCARD]; + __entry->fs_discard = iostat[FS_DISCARD_IO]; ), TP_printk("dev = (%d,%d), " @@ -2048,33 +2082,33 @@ TRACE_EVENT(f2fs_iostat_latency, TP_fast_assign( __entry->dev = sbi->sb->s_dev; - __entry->d_rd_peak = iostat_lat[0][DATA].peak_lat; - __entry->d_rd_avg = iostat_lat[0][DATA].avg_lat; - __entry->d_rd_cnt = iostat_lat[0][DATA].cnt; - __entry->n_rd_peak = iostat_lat[0][NODE].peak_lat; - __entry->n_rd_avg = iostat_lat[0][NODE].avg_lat; - __entry->n_rd_cnt = iostat_lat[0][NODE].cnt; - __entry->m_rd_peak = iostat_lat[0][META].peak_lat; - __entry->m_rd_avg = iostat_lat[0][META].avg_lat; - __entry->m_rd_cnt = iostat_lat[0][META].cnt; - __entry->d_wr_s_peak = iostat_lat[1][DATA].peak_lat; - __entry->d_wr_s_avg = iostat_lat[1][DATA].avg_lat; - __entry->d_wr_s_cnt = iostat_lat[1][DATA].cnt; - __entry->n_wr_s_peak = iostat_lat[1][NODE].peak_lat; - __entry->n_wr_s_avg = iostat_lat[1][NODE].avg_lat; - __entry->n_wr_s_cnt = iostat_lat[1][NODE].cnt; - __entry->m_wr_s_peak = iostat_lat[1][META].peak_lat; - __entry->m_wr_s_avg = iostat_lat[1][META].avg_lat; - __entry->m_wr_s_cnt = iostat_lat[1][META].cnt; - __entry->d_wr_as_peak = iostat_lat[2][DATA].peak_lat; - __entry->d_wr_as_avg = iostat_lat[2][DATA].avg_lat; - __entry->d_wr_as_cnt = iostat_lat[2][DATA].cnt; - __entry->n_wr_as_peak = iostat_lat[2][NODE].peak_lat; - __entry->n_wr_as_avg = iostat_lat[2][NODE].avg_lat; - __entry->n_wr_as_cnt = iostat_lat[2][NODE].cnt; - __entry->m_wr_as_peak = iostat_lat[2][META].peak_lat; - __entry->m_wr_as_avg = iostat_lat[2][META].avg_lat; - __entry->m_wr_as_cnt = iostat_lat[2][META].cnt; + __entry->d_rd_peak = iostat_lat[READ_IO][DATA].peak_lat; + __entry->d_rd_avg = iostat_lat[READ_IO][DATA].avg_lat; + __entry->d_rd_cnt = iostat_lat[READ_IO][DATA].cnt; + __entry->n_rd_peak = iostat_lat[READ_IO][NODE].peak_lat; + __entry->n_rd_avg = iostat_lat[READ_IO][NODE].avg_lat; + __entry->n_rd_cnt = iostat_lat[READ_IO][NODE].cnt; + __entry->m_rd_peak = iostat_lat[READ_IO][META].peak_lat; + __entry->m_rd_avg = iostat_lat[READ_IO][META].avg_lat; + __entry->m_rd_cnt = iostat_lat[READ_IO][META].cnt; + __entry->d_wr_s_peak = iostat_lat[WRITE_SYNC_IO][DATA].peak_lat; + __entry->d_wr_s_avg = iostat_lat[WRITE_SYNC_IO][DATA].avg_lat; + __entry->d_wr_s_cnt = iostat_lat[WRITE_SYNC_IO][DATA].cnt; + __entry->n_wr_s_peak = iostat_lat[WRITE_SYNC_IO][NODE].peak_lat; + __entry->n_wr_s_avg = iostat_lat[WRITE_SYNC_IO][NODE].avg_lat; + __entry->n_wr_s_cnt = iostat_lat[WRITE_SYNC_IO][NODE].cnt; + __entry->m_wr_s_peak = iostat_lat[WRITE_SYNC_IO][META].peak_lat; + __entry->m_wr_s_avg = iostat_lat[WRITE_SYNC_IO][META].avg_lat; + __entry->m_wr_s_cnt = iostat_lat[WRITE_SYNC_IO][META].cnt; + __entry->d_wr_as_peak = iostat_lat[WRITE_ASYNC_IO][DATA].peak_lat; + __entry->d_wr_as_avg = iostat_lat[WRITE_ASYNC_IO][DATA].avg_lat; + __entry->d_wr_as_cnt = iostat_lat[WRITE_ASYNC_IO][DATA].cnt; + __entry->n_wr_as_peak = iostat_lat[WRITE_ASYNC_IO][NODE].peak_lat; + __entry->n_wr_as_avg = iostat_lat[WRITE_ASYNC_IO][NODE].avg_lat; + __entry->n_wr_as_cnt = iostat_lat[WRITE_ASYNC_IO][NODE].cnt; + __entry->m_wr_as_peak = iostat_lat[WRITE_ASYNC_IO][META].peak_lat; + __entry->m_wr_as_avg = iostat_lat[WRITE_ASYNC_IO][META].avg_lat; + __entry->m_wr_as_cnt = iostat_lat[WRITE_ASYNC_IO][META].cnt; ), TP_printk("dev = (%d,%d), " diff --git a/include/trace/events/iommu.h b/include/trace/events/iommu.h index 29096fe12623..70743db1fb75 100644 --- a/include/trace/events/iommu.h +++ b/include/trace/events/iommu.h @@ -76,13 +76,6 @@ DEFINE_EVENT(iommu_device_event, attach_device_to_domain, TP_ARGS(dev) ); -DEFINE_EVENT(iommu_device_event, detach_device_from_domain, - - TP_PROTO(struct device *dev), - - TP_ARGS(dev) -); - TRACE_EVENT(map, TP_PROTO(unsigned long iova, phys_addr_t paddr, size_t size), diff --git a/include/trace/events/scmi.h b/include/trace/events/scmi.h index f160d68f961d..422c1ad9484d 100644 --- a/include/trace/events/scmi.h +++ b/include/trace/events/scmi.h @@ -139,11 +139,15 @@ TRACE_EVENT(scmi_rx_done, ); TRACE_EVENT(scmi_msg_dump, - TP_PROTO(u8 protocol_id, u8 msg_id, unsigned char *tag, u16 seq, - int status, void *buf, size_t len), - TP_ARGS(protocol_id, msg_id, tag, seq, status, buf, len), + TP_PROTO(int id, u8 channel_id, u8 protocol_id, u8 msg_id, + unsigned char *tag, u16 seq, int status, + void *buf, size_t len), + TP_ARGS(id, channel_id, protocol_id, msg_id, tag, seq, status, + buf, len), TP_STRUCT__entry( + __field(int, id) + __field(u8, channel_id) __field(u8, protocol_id) __field(u8, msg_id) __array(char, tag, 5) @@ -154,6 +158,8 @@ TRACE_EVENT(scmi_msg_dump, ), TP_fast_assign( + __entry->id = id; + __entry->channel_id = channel_id; __entry->protocol_id = protocol_id; __entry->msg_id = msg_id; strscpy(__entry->tag, tag, 5); @@ -163,9 +169,9 @@ TRACE_EVENT(scmi_msg_dump, memcpy(__get_dynamic_array(cmd), buf, __entry->len); ), - TP_printk("pt=%02X t=%s msg_id=%02X seq=%04X s=%d pyld=%s", - __entry->protocol_id, __entry->tag, __entry->msg_id, - __entry->seq, __entry->status, + TP_printk("id=%d ch=%02X pt=%02X t=%s msg_id=%02X seq=%04X s=%d pyld=%s", + __entry->id, __entry->channel_id, __entry->protocol_id, + __entry->tag, __entry->msg_id, __entry->seq, __entry->status, __print_hex_str(__get_dynamic_array(cmd), __entry->len)) ); #endif /* _TRACE_SCMI_H */ diff --git a/include/uapi/linux/cxl_mem.h b/include/uapi/linux/cxl_mem.h index c71021a2a9ed..86bbacf2a315 100644 --- a/include/uapi/linux/cxl_mem.h +++ b/include/uapi/linux/cxl_mem.h @@ -11,14 +11,19 @@ /** * DOC: UAPI * - * Not all of all commands that the driver supports are always available for use - * by userspace. Userspace must check the results from the QUERY command in - * order to determine the live set of commands. + * Not all of the commands that the driver supports are available for use by + * userspace at all times. Userspace can check the result of the QUERY command + * to determine the live set of commands. Alternatively, it can issue the + * command and check for failure. */ #define CXL_MEM_QUERY_COMMANDS _IOR(0xCE, 1, struct cxl_mem_query_commands) #define CXL_MEM_SEND_COMMAND _IOWR(0xCE, 2, struct cxl_send_command) +/* + * NOTE: New defines must be added to the end of the list to preserve + * compatibility because this enum is exported to user space. + */ #define CXL_CMDS \ ___C(INVALID, "Invalid Command"), \ ___C(IDENTIFY, "Identify Command"), \ @@ -68,6 +73,19 @@ static const struct { * struct cxl_command_info - Command information returned from a query. * @id: ID number for the command. * @flags: Flags that specify command behavior. + * + * CXL_MEM_COMMAND_FLAG_USER_ENABLED + * + * The given command id is supported by the driver and is supported by + * a related opcode on the device. + * + * CXL_MEM_COMMAND_FLAG_EXCLUSIVE + * + * Requests with the given command id will terminate with EBUSY as the + * kernel actively owns management of the given resource. For example, + * the label-storage-area can not be written while the kernel is + * actively managing that space. + * * @size_in: Expected input size, or ~0 if variable length. * @size_out: Expected output size, or ~0 if variable length. * @@ -77,7 +95,7 @@ static const struct { * bytes of output. * * - @id = 10 - * - @flags = 0 + * - @flags = CXL_MEM_COMMAND_FLAG_ENABLED * - @size_in = ~0 * - @size_out = 0 * @@ -87,7 +105,9 @@ struct cxl_command_info { __u32 id; __u32 flags; -#define CXL_MEM_COMMAND_FLAG_MASK GENMASK(0, 0) +#define CXL_MEM_COMMAND_FLAG_MASK GENMASK(1, 0) +#define CXL_MEM_COMMAND_FLAG_ENABLED BIT(0) +#define CXL_MEM_COMMAND_FLAG_EXCLUSIVE BIT(1) __u32 size_in; __u32 size_out; diff --git a/include/uapi/linux/elf.h b/include/uapi/linux/elf.h index 68de6f4c4eee..ac3da855fb19 100644 --- a/include/uapi/linux/elf.h +++ b/include/uapi/linux/elf.h @@ -445,6 +445,8 @@ typedef struct elf64_shdr { #define NT_LOONGARCH_LSX 0xa02 /* LoongArch Loongson SIMD Extension registers */ #define NT_LOONGARCH_LASX 0xa03 /* LoongArch Loongson Advanced SIMD Extension registers */ #define NT_LOONGARCH_LBT 0xa04 /* LoongArch Loongson Binary Translation registers */ +#define NT_LOONGARCH_HW_BREAK 0xa05 /* LoongArch hardware breakpoint registers */ +#define NT_LOONGARCH_HW_WATCH 0xa06 /* LoongArch hardware watchpoint registers */ /* Note types with note name "GNU" */ #define NT_GNU_PROPERTY_TYPE_0 5 diff --git a/include/uapi/linux/fuse.h b/include/uapi/linux/fuse.h index e3c54109bae9..1b9d0dfae72d 100644 --- a/include/uapi/linux/fuse.h +++ b/include/uapi/linux/fuse.h @@ -201,6 +201,11 @@ * 7.38 * - add FUSE_EXPIRE_ONLY flag to fuse_notify_inval_entry * - add FOPEN_PARALLEL_DIRECT_WRITES + * - add total_extlen to fuse_in_header + * - add FUSE_MAX_NR_SECCTX + * - add extension header + * - add FUSE_EXT_GROUPS + * - add FUSE_CREATE_SUPP_GROUP */ #ifndef _LINUX_FUSE_H @@ -362,6 +367,8 @@ struct fuse_file_lock { * FUSE_SECURITY_CTX: add security context to create, mkdir, symlink, and * mknod * FUSE_HAS_INODE_DAX: use per inode DAX + * FUSE_CREATE_SUPP_GROUP: add supplementary group info to create, mkdir, + * symlink and mknod (single group that matches parent) */ #define FUSE_ASYNC_READ (1 << 0) #define FUSE_POSIX_LOCKS (1 << 1) @@ -398,6 +405,7 @@ struct fuse_file_lock { /* bits 32..63 get shifted down 32 bits into the flags2 field */ #define FUSE_SECURITY_CTX (1ULL << 32) #define FUSE_HAS_INODE_DAX (1ULL << 33) +#define FUSE_CREATE_SUPP_GROUP (1ULL << 34) /** * CUSE INIT request/reply flags @@ -503,6 +511,17 @@ struct fuse_file_lock { */ #define FUSE_EXPIRE_ONLY (1 << 0) +/** + * extension type + * FUSE_MAX_NR_SECCTX: maximum value of &fuse_secctx_header.nr_secctx + * FUSE_EXT_GROUPS: &fuse_supp_groups extension + */ +enum fuse_ext_type { + /* Types 0..31 are reserved for fuse_secctx_header */ + FUSE_MAX_NR_SECCTX = 31, + FUSE_EXT_GROUPS = 32, +}; + enum fuse_opcode { FUSE_LOOKUP = 1, FUSE_FORGET = 2, /* no reply */ @@ -886,7 +905,8 @@ struct fuse_in_header { uint32_t uid; uint32_t gid; uint32_t pid; - uint32_t padding; + uint16_t total_extlen; /* length of extensions in 8byte units */ + uint16_t padding; }; struct fuse_out_header { @@ -1047,4 +1067,27 @@ struct fuse_secctx_header { uint32_t nr_secctx; }; +/** + * struct fuse_ext_header - extension header + * @size: total size of this extension including this header + * @type: type of extension + * + * This is made compatible with fuse_secctx_header by using type values > + * FUSE_MAX_NR_SECCTX + */ +struct fuse_ext_header { + uint32_t size; + uint32_t type; +}; + +/** + * struct fuse_supp_groups - Supplementary group extension + * @nr_groups: number of supplementary groups + * @groups: flexible array of group IDs + */ +struct fuse_supp_groups { + uint32_t nr_groups; + uint32_t groups[]; +}; + #endif /* _LINUX_FUSE_H */ diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h index 55155e262646..d77aef872a0a 100644 --- a/include/uapi/linux/kvm.h +++ b/include/uapi/linux/kvm.h @@ -583,6 +583,8 @@ struct kvm_s390_mem_op { struct { __u8 ar; /* the access register number */ __u8 key; /* access key, ignored if flag unset */ + __u8 pad1[6]; /* ignored */ + __u64 old_addr; /* ignored if cmpxchg flag unset */ }; __u32 sida_offset; /* offset into the sida */ __u8 reserved[32]; /* ignored */ @@ -595,11 +597,17 @@ struct kvm_s390_mem_op { #define KVM_S390_MEMOP_SIDA_WRITE 3 #define KVM_S390_MEMOP_ABSOLUTE_READ 4 #define KVM_S390_MEMOP_ABSOLUTE_WRITE 5 +#define KVM_S390_MEMOP_ABSOLUTE_CMPXCHG 6 + /* flags for kvm_s390_mem_op->flags */ #define KVM_S390_MEMOP_F_CHECK_ONLY (1ULL << 0) #define KVM_S390_MEMOP_F_INJECT_EXCEPTION (1ULL << 1) #define KVM_S390_MEMOP_F_SKEY_PROTECTION (1ULL << 2) +/* flags specifying extension support via KVM_CAP_S390_MEM_OP_EXTENSION */ +#define KVM_S390_MEMOP_EXTENSION_CAP_BASE (1 << 0) +#define KVM_S390_MEMOP_EXTENSION_CAP_CMPXCHG (1 << 1) + /* for KVM_INTERRUPT */ struct kvm_interrupt { /* in */ @@ -1175,6 +1183,7 @@ struct kvm_ppc_resize_hpt { #define KVM_CAP_DIRTY_LOG_RING_ACQ_REL 223 #define KVM_CAP_S390_PROTECTED_ASYNC_DISABLE 224 #define KVM_CAP_DIRTY_LOG_RING_WITH_BITMAP 225 +#define KVM_CAP_PMU_EVENT_MASKED_EVENTS 226 #ifdef KVM_CAP_IRQ_ROUTING diff --git a/include/uapi/linux/meye.h b/include/uapi/linux/meye.h deleted file mode 100644 index de9e3a954f3d..000000000000 --- a/include/uapi/linux/meye.h +++ /dev/null @@ -1,65 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */ -/* - * Motion Eye video4linux driver for Sony Vaio PictureBook - * - * Copyright (C) 2001-2003 Stelian Pop <stelian@popies.net> - * - * Copyright (C) 2001-2002 Alcôve <www.alcove.com> - * - * Copyright (C) 2000 Andrew Tridgell <tridge@valinux.com> - * - * Earlier work by Werner Almesberger, Paul `Rusty' Russell and Paul Mackerras. - * - * Some parts borrowed from various video4linux drivers, especially - * bttv-driver.c and zoran.c, see original files for credits. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef _MEYE_H_ -#define _MEYE_H_ - -/****************************************************************************/ -/* Private API for handling mjpeg capture / playback. */ -/****************************************************************************/ - -struct meye_params { - unsigned char subsample; - unsigned char quality; - unsigned char sharpness; - unsigned char agc; - unsigned char picture; - unsigned char framerate; -}; - -/* query the extended parameters */ -#define MEYEIOC_G_PARAMS _IOR ('v', BASE_VIDIOC_PRIVATE+0, struct meye_params) -/* set the extended parameters */ -#define MEYEIOC_S_PARAMS _IOW ('v', BASE_VIDIOC_PRIVATE+1, struct meye_params) -/* queue a buffer for mjpeg capture */ -#define MEYEIOC_QBUF_CAPT _IOW ('v', BASE_VIDIOC_PRIVATE+2, int) -/* sync a previously queued mjpeg buffer */ -#define MEYEIOC_SYNC _IOWR('v', BASE_VIDIOC_PRIVATE+3, int) -/* get a still uncompressed snapshot */ -#define MEYEIOC_STILLCAPT _IO ('v', BASE_VIDIOC_PRIVATE+4) -/* get a jpeg compressed snapshot */ -#define MEYEIOC_STILLJCAPT _IOR ('v', BASE_VIDIOC_PRIVATE+5, int) - -/* V4L2 private controls */ -#define V4L2_CID_MEYE_AGC (V4L2_CID_USER_MEYE_BASE + 0) -#define V4L2_CID_MEYE_PICTURE (V4L2_CID_USER_MEYE_BASE + 1) -#define V4L2_CID_MEYE_FRAMERATE (V4L2_CID_USER_MEYE_BASE + 2) - -#endif diff --git a/include/uapi/linux/netdev.h b/include/uapi/linux/netdev.h index 9ee459872600..588391447bfb 100644 --- a/include/uapi/linux/netdev.h +++ b/include/uapi/linux/netdev.h @@ -19,7 +19,7 @@ * @NETDEV_XDP_ACT_XSK_ZEROCOPY: This feature informs if netdev supports AF_XDP * in zero copy mode. * @NETDEV_XDP_ACT_HW_OFFLOAD: This feature informs if netdev supports XDP hw - * oflloading. + * offloading. * @NETDEV_XDP_ACT_RX_SG: This feature informs if netdev implements non-linear * XDP buffer support in the driver napi callback. * @NETDEV_XDP_ACT_NDO_XMIT_SG: This feature informs if netdev implements diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 85ab1278811e..dc2000e0fe3a 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -693,6 +693,7 @@ #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ #define PCI_EXP_LNKCTL2_HASD 0x0020 /* HW Autonomous Speed Disable */ #define PCI_EXP_LNKSTA2 0x32 /* Link Status 2 */ +#define PCI_EXP_LNKSTA2_FLIT 0x0400 /* Flit Mode Status */ #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 0x32 /* end of v2 EPs w/ link */ #define PCI_EXP_SLTCAP2 0x34 /* Slot Capabilities 2 */ #define PCI_EXP_SLTCAP2_IBPD 0x00000001 /* In-band PD Disable Supported */ diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4l2-controls.h index b73a8ba7df6c..5e80daa4ffe0 100644 --- a/include/uapi/linux/v4l2-controls.h +++ b/include/uapi/linux/v4l2-controls.h @@ -115,9 +115,13 @@ enum v4l2_colorfx { /* USER-class private control IDs */ -/* The base for the meye driver controls. See linux/meye.h for the list - * of controls. We reserve 16 controls for this driver. */ +#ifndef __KERNEL__ +/* + * The base for the meye driver controls. This driver was removed, but + * we keep this define in case any software still uses it. + */ #define V4L2_CID_USER_MEYE_BASE (V4L2_CID_USER_BASE + 0x1000) +#endif /* The base for the bttv driver controls. * We reserve 32 controls for this driver. */ diff --git a/include/uapi/linux/v4l2-subdev.h b/include/uapi/linux/v4l2-subdev.h index ecce4c79f5c5..654d659de835 100644 --- a/include/uapi/linux/v4l2-subdev.h +++ b/include/uapi/linux/v4l2-subdev.h @@ -11,6 +11,7 @@ #ifndef __LINUX_V4L2_SUBDEV_H #define __LINUX_V4L2_SUBDEV_H +#include <linux/const.h> #include <linux/ioctl.h> #include <linux/types.h> #include <linux/v4l2-common.h> @@ -31,13 +32,15 @@ enum v4l2_subdev_format_whence { * @which: format type (from enum v4l2_subdev_format_whence) * @pad: pad number, as reported by the media API * @format: media bus format (format code and frame size) + * @stream: stream number, defined in subdev routing * @reserved: drivers and applications must zero this array */ struct v4l2_subdev_format { __u32 which; __u32 pad; struct v4l2_mbus_framefmt format; - __u32 reserved[8]; + __u32 stream; + __u32 reserved[7]; }; /** @@ -45,13 +48,15 @@ struct v4l2_subdev_format { * @which: format type (from enum v4l2_subdev_format_whence) * @pad: pad number, as reported by the media API * @rect: pad crop rectangle boundaries + * @stream: stream number, defined in subdev routing * @reserved: drivers and applications must zero this array */ struct v4l2_subdev_crop { __u32 which; __u32 pad; struct v4l2_rect rect; - __u32 reserved[8]; + __u32 stream; + __u32 reserved[7]; }; #define V4L2_SUBDEV_MBUS_CODE_CSC_COLORSPACE 0x00000001 @@ -67,6 +72,7 @@ struct v4l2_subdev_crop { * @code: format code (MEDIA_BUS_FMT_ definitions) * @which: format type (from enum v4l2_subdev_format_whence) * @flags: flags set by the driver, (V4L2_SUBDEV_MBUS_CODE_*) + * @stream: stream number, defined in subdev routing * @reserved: drivers and applications must zero this array */ struct v4l2_subdev_mbus_code_enum { @@ -75,7 +81,8 @@ struct v4l2_subdev_mbus_code_enum { __u32 code; __u32 which; __u32 flags; - __u32 reserved[7]; + __u32 stream; + __u32 reserved[6]; }; /** @@ -88,6 +95,7 @@ struct v4l2_subdev_mbus_code_enum { * @min_height: minimum frame height, in pixels * @max_height: maximum frame height, in pixels * @which: format type (from enum v4l2_subdev_format_whence) + * @stream: stream number, defined in subdev routing * @reserved: drivers and applications must zero this array */ struct v4l2_subdev_frame_size_enum { @@ -99,19 +107,22 @@ struct v4l2_subdev_frame_size_enum { __u32 min_height; __u32 max_height; __u32 which; - __u32 reserved[8]; + __u32 stream; + __u32 reserved[7]; }; /** * struct v4l2_subdev_frame_interval - Pad-level frame rate * @pad: pad number, as reported by the media API * @interval: frame interval in seconds + * @stream: stream number, defined in subdev routing * @reserved: drivers and applications must zero this array */ struct v4l2_subdev_frame_interval { __u32 pad; struct v4l2_fract interval; - __u32 reserved[9]; + __u32 stream; + __u32 reserved[8]; }; /** @@ -123,6 +134,7 @@ struct v4l2_subdev_frame_interval { * @height: frame height in pixels * @interval: frame interval in seconds * @which: format type (from enum v4l2_subdev_format_whence) + * @stream: stream number, defined in subdev routing * @reserved: drivers and applications must zero this array */ struct v4l2_subdev_frame_interval_enum { @@ -133,7 +145,8 @@ struct v4l2_subdev_frame_interval_enum { __u32 height; struct v4l2_fract interval; __u32 which; - __u32 reserved[8]; + __u32 stream; + __u32 reserved[7]; }; /** @@ -145,6 +158,7 @@ struct v4l2_subdev_frame_interval_enum { * defined in v4l2-common.h; V4L2_SEL_TGT_* . * @flags: constraint flags, defined in v4l2-common.h; V4L2_SEL_FLAG_*. * @r: coordinates of the selection window + * @stream: stream number, defined in subdev routing * @reserved: for future use, set to zero for now * * Hardware may use multiple helper windows to process a video stream. @@ -157,7 +171,8 @@ struct v4l2_subdev_selection { __u32 target; __u32 flags; struct v4l2_rect r; - __u32 reserved[8]; + __u32 stream; + __u32 reserved[7]; }; /** @@ -175,6 +190,49 @@ struct v4l2_subdev_capability { /* The v4l2 sub-device video device node is registered in read-only mode. */ #define V4L2_SUBDEV_CAP_RO_SUBDEV 0x00000001 +/* The v4l2 sub-device supports routing and multiplexed streams. */ +#define V4L2_SUBDEV_CAP_STREAMS 0x00000002 + +/* + * Is the route active? An active route will start when streaming is enabled + * on a video node. + */ +#define V4L2_SUBDEV_ROUTE_FL_ACTIVE (1U << 0) + +/** + * struct v4l2_subdev_route - A route inside a subdev + * + * @sink_pad: the sink pad index + * @sink_stream: the sink stream identifier + * @source_pad: the source pad index + * @source_stream: the source stream identifier + * @flags: route flags V4L2_SUBDEV_ROUTE_FL_* + * @reserved: drivers and applications must zero this array + */ +struct v4l2_subdev_route { + __u32 sink_pad; + __u32 sink_stream; + __u32 source_pad; + __u32 source_stream; + __u32 flags; + __u32 reserved[5]; +}; + +/** + * struct v4l2_subdev_routing - Subdev routing information + * + * @which: configuration type (from enum v4l2_subdev_format_whence) + * @num_routes: the total number of routes in the routes array + * @routes: pointer to the routes array + * @reserved: drivers and applications must zero this array + */ +struct v4l2_subdev_routing { + __u32 which; + __u32 num_routes; + __u64 routes; + __u32 reserved[6]; +}; + /* Backwards compatibility define --- to be removed */ #define v4l2_subdev_edid v4l2_edid @@ -190,6 +248,8 @@ struct v4l2_subdev_capability { #define VIDIOC_SUBDEV_S_CROP _IOWR('V', 60, struct v4l2_subdev_crop) #define VIDIOC_SUBDEV_G_SELECTION _IOWR('V', 61, struct v4l2_subdev_selection) #define VIDIOC_SUBDEV_S_SELECTION _IOWR('V', 62, struct v4l2_subdev_selection) +#define VIDIOC_SUBDEV_G_ROUTING _IOWR('V', 38, struct v4l2_subdev_routing) +#define VIDIOC_SUBDEV_S_ROUTING _IOWR('V', 39, struct v4l2_subdev_routing) /* The following ioctls are identical to the ioctls in videodev2.h */ #define VIDIOC_SUBDEV_G_STD _IOR('V', 23, v4l2_std_id) #define VIDIOC_SUBDEV_S_STD _IOW('V', 24, v4l2_std_id) diff --git a/include/uapi/linux/vfio.h b/include/uapi/linux/vfio.h index 23105eb036fa..0552e8dcf0cb 100644 --- a/include/uapi/linux/vfio.h +++ b/include/uapi/linux/vfio.h @@ -49,7 +49,11 @@ /* Supports VFIO_DMA_UNMAP_FLAG_ALL */ #define VFIO_UNMAP_ALL 9 -/* Supports the vaddr flag for DMA map and unmap */ +/* + * Supports the vaddr flag for DMA map and unmap. Not supported for mediated + * devices, so this capability is subject to change as groups are added or + * removed. + */ #define VFIO_UPDATE_VADDR 10 /* @@ -1343,8 +1347,7 @@ struct vfio_iommu_type1_info_dma_avail { * Map process virtual addresses to IO virtual addresses using the * provided struct vfio_dma_map. Caller sets argsz. READ &/ WRITE required. * - * If flags & VFIO_DMA_MAP_FLAG_VADDR, update the base vaddr for iova, and - * unblock translation of host virtual addresses in the iova range. The vaddr + * If flags & VFIO_DMA_MAP_FLAG_VADDR, update the base vaddr for iova. The vaddr * must have previously been invalidated with VFIO_DMA_UNMAP_FLAG_VADDR. To * maintain memory consistency within the user application, the updated vaddr * must address the same memory object as originally mapped. Failure to do so @@ -1395,9 +1398,9 @@ struct vfio_bitmap { * must be 0. This cannot be combined with the get-dirty-bitmap flag. * * If flags & VFIO_DMA_UNMAP_FLAG_VADDR, do not unmap, but invalidate host - * virtual addresses in the iova range. Tasks that attempt to translate an - * iova's vaddr will block. DMA to already-mapped pages continues. This - * cannot be combined with the get-dirty-bitmap flag. + * virtual addresses in the iova range. DMA to already-mapped pages continues. + * Groups may not be added to the container while any addresses are invalid. + * This cannot be combined with the get-dirty-bitmap flag. */ struct vfio_iommu_type1_dma_unmap { __u32 argsz; diff --git a/include/uapi/linux/vhost.h b/include/uapi/linux/vhost.h index f9f115a7c75b..92e1b700b51c 100644 --- a/include/uapi/linux/vhost.h +++ b/include/uapi/linux/vhost.h @@ -180,4 +180,12 @@ */ #define VHOST_VDPA_SUSPEND _IO(VHOST_VIRTIO, 0x7D) +/* Resume a device so it can resume processing virtqueue requests + * + * After the return of this ioctl the device will have restored all the + * necessary states and it is fully operational to continue processing the + * virtqueue descriptors. + */ +#define VHOST_VDPA_RESUME _IO(VHOST_VIRTIO, 0x7E) + #endif diff --git a/include/uapi/linux/vhost_types.h b/include/uapi/linux/vhost_types.h index 53601ce2c20a..c5690a8992d8 100644 --- a/include/uapi/linux/vhost_types.h +++ b/include/uapi/linux/vhost_types.h @@ -163,5 +163,7 @@ struct vhost_vdpa_iova_range { #define VHOST_BACKEND_F_IOTLB_ASID 0x3 /* Device can be suspended */ #define VHOST_BACKEND_F_SUSPEND 0x4 +/* Device can be resumed */ +#define VHOST_BACKEND_F_RESUME 0x5 #endif diff --git a/include/uapi/linux/virtio_blk.h b/include/uapi/linux/virtio_blk.h index 58e70b24b504..5af2a0300bb9 100644 --- a/include/uapi/linux/virtio_blk.h +++ b/include/uapi/linux/virtio_blk.h @@ -41,6 +41,7 @@ #define VIRTIO_BLK_F_DISCARD 13 /* DISCARD is supported */ #define VIRTIO_BLK_F_WRITE_ZEROES 14 /* WRITE ZEROES is supported */ #define VIRTIO_BLK_F_SECURE_ERASE 16 /* Secure Erase is supported */ +#define VIRTIO_BLK_F_ZONED 17 /* Zoned block device */ /* Legacy feature bits */ #ifndef VIRTIO_BLK_NO_LEGACY @@ -137,6 +138,16 @@ struct virtio_blk_config { /* Secure erase commands must be aligned to this number of sectors. */ __virtio32 secure_erase_sector_alignment; + /* Zoned block device characteristics (if VIRTIO_BLK_F_ZONED) */ + struct virtio_blk_zoned_characteristics { + __le32 zone_sectors; + __le32 max_open_zones; + __le32 max_active_zones; + __le32 max_append_sectors; + __le32 write_granularity; + __u8 model; + __u8 unused2[3]; + } zoned; } __attribute__((packed)); /* @@ -174,6 +185,27 @@ struct virtio_blk_config { /* Secure erase command */ #define VIRTIO_BLK_T_SECURE_ERASE 14 +/* Zone append command */ +#define VIRTIO_BLK_T_ZONE_APPEND 15 + +/* Report zones command */ +#define VIRTIO_BLK_T_ZONE_REPORT 16 + +/* Open zone command */ +#define VIRTIO_BLK_T_ZONE_OPEN 18 + +/* Close zone command */ +#define VIRTIO_BLK_T_ZONE_CLOSE 20 + +/* Finish zone command */ +#define VIRTIO_BLK_T_ZONE_FINISH 22 + +/* Reset zone command */ +#define VIRTIO_BLK_T_ZONE_RESET 24 + +/* Reset All zones command */ +#define VIRTIO_BLK_T_ZONE_RESET_ALL 26 + #ifndef VIRTIO_BLK_NO_LEGACY /* Barrier before this op. */ #define VIRTIO_BLK_T_BARRIER 0x80000000 @@ -193,6 +225,72 @@ struct virtio_blk_outhdr { __virtio64 sector; }; +/* + * Supported zoned device models. + */ + +/* Regular block device */ +#define VIRTIO_BLK_Z_NONE 0 +/* Host-managed zoned device */ +#define VIRTIO_BLK_Z_HM 1 +/* Host-aware zoned device */ +#define VIRTIO_BLK_Z_HA 2 + +/* + * Zone descriptor. A part of VIRTIO_BLK_T_ZONE_REPORT command reply. + */ +struct virtio_blk_zone_descriptor { + /* Zone capacity */ + __le64 z_cap; + /* The starting sector of the zone */ + __le64 z_start; + /* Zone write pointer position in sectors */ + __le64 z_wp; + /* Zone type */ + __u8 z_type; + /* Zone state */ + __u8 z_state; + __u8 reserved[38]; +}; + +struct virtio_blk_zone_report { + __le64 nr_zones; + __u8 reserved[56]; + struct virtio_blk_zone_descriptor zones[]; +}; + +/* + * Supported zone types. + */ + +/* Conventional zone */ +#define VIRTIO_BLK_ZT_CONV 1 +/* Sequential Write Required zone */ +#define VIRTIO_BLK_ZT_SWR 2 +/* Sequential Write Preferred zone */ +#define VIRTIO_BLK_ZT_SWP 3 + +/* + * Zone states that are available for zones of all types. + */ + +/* Not a write pointer (conventional zones only) */ +#define VIRTIO_BLK_ZS_NOT_WP 0 +/* Empty */ +#define VIRTIO_BLK_ZS_EMPTY 1 +/* Implicitly Open */ +#define VIRTIO_BLK_ZS_IOPEN 2 +/* Explicitly Open */ +#define VIRTIO_BLK_ZS_EOPEN 3 +/* Closed */ +#define VIRTIO_BLK_ZS_CLOSED 4 +/* Read-Only */ +#define VIRTIO_BLK_ZS_RDONLY 13 +/* Full */ +#define VIRTIO_BLK_ZS_FULL 14 +/* Offline */ +#define VIRTIO_BLK_ZS_OFFLINE 15 + /* Unmap this range (only valid for write zeroes command) */ #define VIRTIO_BLK_WRITE_ZEROES_FLAG_UNMAP 0x00000001 @@ -219,4 +317,11 @@ struct virtio_scsi_inhdr { #define VIRTIO_BLK_S_OK 0 #define VIRTIO_BLK_S_IOERR 1 #define VIRTIO_BLK_S_UNSUPP 2 + +/* Error codes that are specific to zoned block devices */ +#define VIRTIO_BLK_S_ZONE_INVALID_CMD 3 +#define VIRTIO_BLK_S_ZONE_UNALIGNED_WP 4 +#define VIRTIO_BLK_S_ZONE_OPEN_RESOURCE 5 +#define VIRTIO_BLK_S_ZONE_ACTIVE_RESOURCE 6 + #endif /* _LINUX_VIRTIO_BLK_H */ diff --git a/include/uapi/rdma/hns-abi.h b/include/uapi/rdma/hns-abi.h index 745790ce3c26..2e68a8b0c92c 100644 --- a/include/uapi/rdma/hns-abi.h +++ b/include/uapi/rdma/hns-abi.h @@ -87,10 +87,14 @@ struct hns_roce_ib_create_qp_resp { enum { HNS_ROCE_EXSGE_FLAGS = 1 << 0, + HNS_ROCE_RQ_INLINE_FLAGS = 1 << 1, + HNS_ROCE_CQE_INLINE_FLAGS = 1 << 2, }; enum { HNS_ROCE_RSP_EXSGE_FLAGS = 1 << 0, + HNS_ROCE_RSP_RQ_INLINE_FLAGS = 1 << 1, + HNS_ROCE_RSP_CQE_INLINE_FLAGS = 1 << 2, }; struct hns_roce_ib_alloc_ucontext_resp { |