diff options
Diffstat (limited to 'include/linux/clk')
| -rw-r--r-- | include/linux/clk/at91_pmc.h | 12 | ||||
| -rw-r--r-- | include/linux/clk/renesas.h (renamed from include/linux/clk/shmobile.h) | 4 | ||||
| -rw-r--r-- | include/linux/clk/ti.h | 8 |
3 files changed, 6 insertions, 18 deletions
diff --git a/include/linux/clk/at91_pmc.h b/include/linux/clk/at91_pmc.h index 1e6932222e11..17f413bbbedf 100644 --- a/include/linux/clk/at91_pmc.h +++ b/include/linux/clk/at91_pmc.h @@ -16,18 +16,6 @@ #ifndef AT91_PMC_H #define AT91_PMC_H -#ifndef __ASSEMBLY__ -extern void __iomem *at91_pmc_base; - -#define at91_pmc_read(field) \ - readl_relaxed(at91_pmc_base + field) - -#define at91_pmc_write(field, value) \ - writel_relaxed(value, at91_pmc_base + field) -#else -.extern at91_pmc_base -#endif - #define AT91_PMC_SCER 0x00 /* System Clock Enable Register */ #define AT91_PMC_SCDR 0x04 /* System Clock Disable Register */ diff --git a/include/linux/clk/shmobile.h b/include/linux/clk/renesas.h index cb19cc1865ca..7adfd80fbf55 100644 --- a/include/linux/clk/shmobile.h +++ b/include/linux/clk/renesas.h @@ -11,8 +11,8 @@ * (at your option) any later version. */ -#ifndef __LINUX_CLK_SHMOBILE_H_ -#define __LINUX_CLK_SHMOBILE_H_ +#ifndef __LINUX_CLK_RENESAS_H_ +#define __LINUX_CLK_RENESAS_H_ #include <linux/types.h> diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index 9a638601cb09..dc5164a6df29 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -23,8 +23,8 @@ * @mult_div1_reg: register containing the DPLL M and N bitfields * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg - * @clk_bypass: struct clk pointer to the clock's bypass clock input - * @clk_ref: struct clk pointer to the clock's reference clock input + * @clk_bypass: struct clk_hw pointer to the clock's bypass clock input + * @clk_ref: struct clk_hw pointer to the clock's reference clock input * @control_reg: register containing the DPLL mode bitfield * @enable_mask: mask of the DPLL mode bitfield in @control_reg * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate() @@ -69,8 +69,8 @@ struct dpll_data { void __iomem *mult_div1_reg; u32 mult_mask; u32 div1_mask; - struct clk *clk_bypass; - struct clk *clk_ref; + struct clk_hw *clk_bypass; + struct clk_hw *clk_ref; void __iomem *control_reg; u32 enable_mask; unsigned long last_rounded_rate; |