diff options
Diffstat (limited to 'include/dt-bindings/reset')
| -rw-r--r-- | include/dt-bindings/reset/bcm63268-reset.h | 4 | ||||
| -rw-r--r-- | include/dt-bindings/reset/mediatek,mt6735-wdt.h | 17 | ||||
| -rw-r--r-- | include/dt-bindings/reset/qcom,ipq9574-gcc.h | 164 | ||||
| -rw-r--r-- | include/dt-bindings/reset/starfive,jh7110-crg.h | 154 | ||||
| -rw-r--r-- | include/dt-bindings/reset/stih415-resets.h | 28 | ||||
| -rw-r--r-- | include/dt-bindings/reset/stih416-resets.h | 52 |
6 files changed, 339 insertions, 80 deletions
diff --git a/include/dt-bindings/reset/bcm63268-reset.h b/include/dt-bindings/reset/bcm63268-reset.h index 6a6403a4c2d5..d87a7882782a 100644 --- a/include/dt-bindings/reset/bcm63268-reset.h +++ b/include/dt-bindings/reset/bcm63268-reset.h @@ -23,4 +23,8 @@ #define BCM63268_RST_PCIE_HARD 17 #define BCM63268_RST_GPHY 18 +#define BCM63268_TRST_SW 29 +#define BCM63268_TRST_HW 30 +#define BCM63268_TRST_POR 31 + #endif /* __DT_BINDINGS_RESET_BCM63268_H */ diff --git a/include/dt-bindings/reset/mediatek,mt6735-wdt.h b/include/dt-bindings/reset/mediatek,mt6735-wdt.h new file mode 100644 index 000000000000..c6056e676d46 --- /dev/null +++ b/include/dt-bindings/reset/mediatek,mt6735-wdt.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_RESET_MEDIATEK_MT6735_WDT_H_ +#define _DT_BINDINGS_RESET_MEDIATEK_MT6735_WDT_H_ + +#define MT6735_TOPRGU_MM_RST 1 +#define MT6735_TOPRGU_MFG_RST 2 +#define MT6735_TOPRGU_VENC_RST 3 +#define MT6735_TOPRGU_VDEC_RST 4 +#define MT6735_TOPRGU_IMG_RST 5 +#define MT6735_TOPRGU_MD_RST 7 +#define MT6735_TOPRGU_CONN_RST 9 +#define MT6735_TOPRGU_C2K_SW_RST 14 +#define MT6735_TOPRGU_C2K_RST 15 +#define MT6735_TOPRGU_RST_NUM 9 + +#endif diff --git a/include/dt-bindings/reset/qcom,ipq9574-gcc.h b/include/dt-bindings/reset/qcom,ipq9574-gcc.h new file mode 100644 index 000000000000..d01dc6a24cf1 --- /dev/null +++ b/include/dt-bindings/reset/qcom,ipq9574-gcc.h @@ -0,0 +1,164 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2018-2023, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_RESET_IPQ_GCC_9574_H +#define _DT_BINDINGS_RESET_IPQ_GCC_9574_H + +#define GCC_ADSS_BCR 0 +#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 1 +#define GCC_BLSP1_BCR 2 +#define GCC_BLSP1_QUP1_BCR 3 +#define GCC_BLSP1_QUP2_BCR 4 +#define GCC_BLSP1_QUP3_BCR 5 +#define GCC_BLSP1_QUP4_BCR 6 +#define GCC_BLSP1_QUP5_BCR 7 +#define GCC_BLSP1_QUP6_BCR 8 +#define GCC_BLSP1_UART1_BCR 9 +#define GCC_BLSP1_UART2_BCR 10 +#define GCC_BLSP1_UART3_BCR 11 +#define GCC_BLSP1_UART4_BCR 12 +#define GCC_BLSP1_UART5_BCR 13 +#define GCC_BLSP1_UART6_BCR 14 +#define GCC_BOOT_ROM_BCR 15 +#define GCC_MDIO_BCR 16 +#define GCC_NSS_BCR 17 +#define GCC_NSS_TBU_BCR 18 +#define GCC_PCIE0_BCR 19 +#define GCC_PCIE0_LINK_DOWN_BCR 20 +#define GCC_PCIE0_PHY_BCR 21 +#define GCC_PCIE0PHY_PHY_BCR 22 +#define GCC_PCIE1_BCR 23 +#define GCC_PCIE1_LINK_DOWN_BCR 24 +#define GCC_PCIE1_PHY_BCR 25 +#define GCC_PCIE1PHY_PHY_BCR 26 +#define GCC_PCIE2_BCR 27 +#define GCC_PCIE2_LINK_DOWN_BCR 28 +#define GCC_PCIE2_PHY_BCR 29 +#define GCC_PCIE2PHY_PHY_BCR 30 +#define GCC_PCIE3_BCR 31 +#define GCC_PCIE3_LINK_DOWN_BCR 32 +#define GCC_PCIE3_PHY_BCR 33 +#define GCC_PCIE3PHY_PHY_BCR 34 +#define GCC_PRNG_BCR 35 +#define GCC_QUSB2_0_PHY_BCR 36 +#define GCC_SDCC_BCR 37 +#define GCC_TLMM_BCR 38 +#define GCC_UNIPHY0_BCR 39 +#define GCC_UNIPHY1_BCR 40 +#define GCC_UNIPHY2_BCR 41 +#define GCC_USB0_PHY_BCR 42 +#define GCC_USB3PHY_0_PHY_BCR 43 +#define GCC_USB_BCR 44 +#define GCC_ANOC0_TBU_BCR 45 +#define GCC_ANOC1_TBU_BCR 46 +#define GCC_ANOC_BCR 47 +#define GCC_APSS_TCU_BCR 48 +#define GCC_CMN_BLK_BCR 49 +#define GCC_CMN_BLK_AHB_ARES 50 +#define GCC_CMN_BLK_SYS_ARES 51 +#define GCC_CMN_BLK_APU_ARES 52 +#define GCC_DCC_BCR 53 +#define GCC_DDRSS_BCR 54 +#define GCC_IMEM_BCR 55 +#define GCC_LPASS_BCR 56 +#define GCC_MPM_BCR 57 +#define GCC_MSG_RAM_BCR 58 +#define GCC_NSSNOC_MEMNOC_1_ARES 59 +#define GCC_NSSNOC_PCNOC_1_ARES 60 +#define GCC_NSSNOC_SNOC_1_ARES 61 +#define GCC_NSSNOC_XO_DCD_ARES 62 +#define GCC_NSSNOC_TS_ARES 63 +#define GCC_NSSCC_ARES 64 +#define GCC_NSSNOC_NSSCC_ARES 65 +#define GCC_NSSNOC_ATB_ARES 66 +#define GCC_NSSNOC_MEMNOC_ARES 67 +#define GCC_NSSNOC_QOSGEN_REF_ARES 68 +#define GCC_NSSNOC_SNOC_ARES 69 +#define GCC_NSSNOC_TIMEOUT_REF_ARES 70 +#define GCC_NSS_CFG_ARES 71 +#define GCC_UBI0_DBG_ARES 72 +#define GCC_PCIE0_AHB_ARES 73 +#define GCC_PCIE0_AUX_ARES 74 +#define GCC_PCIE0_AXI_M_ARES 75 +#define GCC_PCIE0_AXI_M_STICKY_ARES 76 +#define GCC_PCIE0_AXI_S_ARES 77 +#define GCC_PCIE0_AXI_S_STICKY_ARES 78 +#define GCC_PCIE0_CORE_STICKY_ARES 79 +#define GCC_PCIE0_PIPE_ARES 80 +#define GCC_PCIE1_AHB_ARES 81 +#define GCC_PCIE1_AUX_ARES 82 +#define GCC_PCIE1_AXI_M_ARES 83 +#define GCC_PCIE1_AXI_M_STICKY_ARES 84 +#define GCC_PCIE1_AXI_S_ARES 85 +#define GCC_PCIE1_AXI_S_STICKY_ARES 86 +#define GCC_PCIE1_CORE_STICKY_ARES 87 +#define GCC_PCIE1_PIPE_ARES 88 +#define GCC_PCIE2_AHB_ARES 89 +#define GCC_PCIE2_AUX_ARES 90 +#define GCC_PCIE2_AXI_M_ARES 91 +#define GCC_PCIE2_AXI_M_STICKY_ARES 92 +#define GCC_PCIE2_AXI_S_ARES 93 +#define GCC_PCIE2_AXI_S_STICKY_ARES 94 +#define GCC_PCIE2_CORE_STICKY_ARES 95 +#define GCC_PCIE2_PIPE_ARES 96 +#define GCC_PCIE3_AHB_ARES 97 +#define GCC_PCIE3_AUX_ARES 98 +#define GCC_PCIE3_AXI_M_ARES 99 +#define GCC_PCIE3_AXI_M_STICKY_ARES 100 +#define GCC_PCIE3_AXI_S_ARES 101 +#define GCC_PCIE3_AXI_S_STICKY_ARES 102 +#define GCC_PCIE3_CORE_STICKY_ARES 103 +#define GCC_PCIE3_PIPE_ARES 104 +#define GCC_PCNOC_BCR 105 +#define GCC_PCNOC_BUS_TIMEOUT0_BCR 106 +#define GCC_PCNOC_BUS_TIMEOUT1_BCR 107 +#define GCC_PCNOC_BUS_TIMEOUT2_BCR 108 +#define GCC_PCNOC_BUS_TIMEOUT3_BCR 109 +#define GCC_PCNOC_BUS_TIMEOUT4_BCR 110 +#define GCC_PCNOC_BUS_TIMEOUT5_BCR 111 +#define GCC_PCNOC_BUS_TIMEOUT6_BCR 112 +#define GCC_PCNOC_BUS_TIMEOUT7_BCR 113 +#define GCC_PCNOC_BUS_TIMEOUT8_BCR 114 +#define GCC_PCNOC_BUS_TIMEOUT9_BCR 115 +#define GCC_PCNOC_TBU_BCR 116 +#define GCC_Q6SS_DBG_ARES 117 +#define GCC_Q6_AHB_ARES 118 +#define GCC_Q6_AHB_S_ARES 119 +#define GCC_Q6_AXIM2_ARES 120 +#define GCC_Q6_AXIM_ARES 121 +#define GCC_QDSS_BCR 122 +#define GCC_QPIC_BCR 123 +#define GCC_QPIC_AHB_ARES 124 +#define GCC_QPIC_ARES 125 +#define GCC_RBCPR_BCR 126 +#define GCC_RBCPR_MX_BCR 127 +#define GCC_SEC_CTRL_BCR 128 +#define GCC_SMMU_CFG_BCR 129 +#define GCC_SNOC_BCR 130 +#define GCC_SPDM_BCR 131 +#define GCC_TME_BCR 132 +#define GCC_UNIPHY0_SYS_RESET 133 +#define GCC_UNIPHY0_AHB_RESET 134 +#define GCC_UNIPHY0_XPCS_RESET 135 +#define GCC_UNIPHY1_SYS_RESET 136 +#define GCC_UNIPHY1_AHB_RESET 137 +#define GCC_UNIPHY1_XPCS_RESET 138 +#define GCC_UNIPHY2_SYS_RESET 139 +#define GCC_UNIPHY2_AHB_RESET 140 +#define GCC_UNIPHY2_XPCS_RESET 141 +#define GCC_USB_MISC_RESET 142 +#define GCC_WCSSAON_RESET 143 +#define GCC_WCSS_ACMT_ARES 144 +#define GCC_WCSS_AHB_S_ARES 145 +#define GCC_WCSS_AXI_M_ARES 146 +#define GCC_WCSS_BCR 147 +#define GCC_WCSS_DBG_ARES 148 +#define GCC_WCSS_DBG_BDG_ARES 149 +#define GCC_WCSS_ECAHB_ARES 150 +#define GCC_WCSS_Q6_BCR 151 +#define GCC_WCSS_Q6_TBU_BCR 152 +#define GCC_TCSR_BCR 153 + +#endif diff --git a/include/dt-bindings/reset/starfive,jh7110-crg.h b/include/dt-bindings/reset/starfive,jh7110-crg.h new file mode 100644 index 000000000000..d78e38690ceb --- /dev/null +++ b/include/dt-bindings/reset/starfive,jh7110-crg.h @@ -0,0 +1,154 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk> + */ + +#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ +#define __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ + +/* SYSCRG resets */ +#define JH7110_SYSRST_JTAG_APB 0 +#define JH7110_SYSRST_SYSCON_APB 1 +#define JH7110_SYSRST_IOMUX_APB 2 +#define JH7110_SYSRST_BUS 3 +#define JH7110_SYSRST_DEBUG 4 +#define JH7110_SYSRST_CORE0 5 +#define JH7110_SYSRST_CORE1 6 +#define JH7110_SYSRST_CORE2 7 +#define JH7110_SYSRST_CORE3 8 +#define JH7110_SYSRST_CORE4 9 +#define JH7110_SYSRST_CORE0_ST 10 +#define JH7110_SYSRST_CORE1_ST 11 +#define JH7110_SYSRST_CORE2_ST 12 +#define JH7110_SYSRST_CORE3_ST 13 +#define JH7110_SYSRST_CORE4_ST 14 +#define JH7110_SYSRST_TRACE0 15 +#define JH7110_SYSRST_TRACE1 16 +#define JH7110_SYSRST_TRACE2 17 +#define JH7110_SYSRST_TRACE3 18 +#define JH7110_SYSRST_TRACE4 19 +#define JH7110_SYSRST_TRACE_COM 20 +#define JH7110_SYSRST_GPU_APB 21 +#define JH7110_SYSRST_GPU_DOMA 22 +#define JH7110_SYSRST_NOC_BUS_APB 23 +#define JH7110_SYSRST_NOC_BUS_AXICFG0_AXI 24 +#define JH7110_SYSRST_NOC_BUS_CPU_AXI 25 +#define JH7110_SYSRST_NOC_BUS_DISP_AXI 26 +#define JH7110_SYSRST_NOC_BUS_GPU_AXI 27 +#define JH7110_SYSRST_NOC_BUS_ISP_AXI 28 +#define JH7110_SYSRST_NOC_BUS_DDRC 29 +#define JH7110_SYSRST_NOC_BUS_STG_AXI 30 +#define JH7110_SYSRST_NOC_BUS_VDEC_AXI 31 + +#define JH7110_SYSRST_NOC_BUS_VENC_AXI 32 +#define JH7110_SYSRST_AXI_CFG1_AHB 33 +#define JH7110_SYSRST_AXI_CFG1_MAIN 34 +#define JH7110_SYSRST_AXI_CFG0_MAIN 35 +#define JH7110_SYSRST_AXI_CFG0_MAIN_DIV 36 +#define JH7110_SYSRST_AXI_CFG0_HIFI4 37 +#define JH7110_SYSRST_DDR_AXI 38 +#define JH7110_SYSRST_DDR_OSC 39 +#define JH7110_SYSRST_DDR_APB 40 +#define JH7110_SYSRST_ISP_TOP 41 +#define JH7110_SYSRST_ISP_TOP_AXI 42 +#define JH7110_SYSRST_VOUT_TOP_SRC 43 +#define JH7110_SYSRST_CODAJ12_AXI 44 +#define JH7110_SYSRST_CODAJ12_CORE 45 +#define JH7110_SYSRST_CODAJ12_APB 46 +#define JH7110_SYSRST_WAVE511_AXI 47 +#define JH7110_SYSRST_WAVE511_BPU 48 +#define JH7110_SYSRST_WAVE511_VCE 49 +#define JH7110_SYSRST_WAVE511_APB 50 +#define JH7110_SYSRST_VDEC_JPG 51 +#define JH7110_SYSRST_VDEC_MAIN 52 +#define JH7110_SYSRST_AXIMEM0_AXI 53 +#define JH7110_SYSRST_WAVE420L_AXI 54 +#define JH7110_SYSRST_WAVE420L_BPU 55 +#define JH7110_SYSRST_WAVE420L_VCE 56 +#define JH7110_SYSRST_WAVE420L_APB 57 +#define JH7110_SYSRST_AXIMEM1_AXI 58 +#define JH7110_SYSRST_AXIMEM2_AXI 59 +#define JH7110_SYSRST_INTMEM 60 +#define JH7110_SYSRST_QSPI_AHB 61 +#define JH7110_SYSRST_QSPI_APB 62 +#define JH7110_SYSRST_QSPI_REF 63 + +#define JH7110_SYSRST_SDIO0_AHB 64 +#define JH7110_SYSRST_SDIO1_AHB 65 +#define JH7110_SYSRST_GMAC1_AXI 66 +#define JH7110_SYSRST_GMAC1_AHB 67 +#define JH7110_SYSRST_MAILBOX_APB 68 +#define JH7110_SYSRST_SPI0_APB 69 +#define JH7110_SYSRST_SPI1_APB 70 +#define JH7110_SYSRST_SPI2_APB 71 +#define JH7110_SYSRST_SPI3_APB 72 +#define JH7110_SYSRST_SPI4_APB 73 +#define JH7110_SYSRST_SPI5_APB 74 +#define JH7110_SYSRST_SPI6_APB 75 +#define JH7110_SYSRST_I2C0_APB 76 +#define JH7110_SYSRST_I2C1_APB 77 +#define JH7110_SYSRST_I2C2_APB 78 +#define JH7110_SYSRST_I2C3_APB 79 +#define JH7110_SYSRST_I2C4_APB 80 +#define JH7110_SYSRST_I2C5_APB 81 +#define JH7110_SYSRST_I2C6_APB 82 +#define JH7110_SYSRST_UART0_APB 83 +#define JH7110_SYSRST_UART0_CORE 84 +#define JH7110_SYSRST_UART1_APB 85 +#define JH7110_SYSRST_UART1_CORE 86 +#define JH7110_SYSRST_UART2_APB 87 +#define JH7110_SYSRST_UART2_CORE 88 +#define JH7110_SYSRST_UART3_APB 89 +#define JH7110_SYSRST_UART3_CORE 90 +#define JH7110_SYSRST_UART4_APB 91 +#define JH7110_SYSRST_UART4_CORE 92 +#define JH7110_SYSRST_UART5_APB 93 +#define JH7110_SYSRST_UART5_CORE 94 +#define JH7110_SYSRST_SPDIF_APB 95 + +#define JH7110_SYSRST_PWMDAC_APB 96 +#define JH7110_SYSRST_PDM_DMIC 97 +#define JH7110_SYSRST_PDM_APB 98 +#define JH7110_SYSRST_I2SRX_APB 99 +#define JH7110_SYSRST_I2SRX_BCLK 100 +#define JH7110_SYSRST_I2STX0_APB 101 +#define JH7110_SYSRST_I2STX0_BCLK 102 +#define JH7110_SYSRST_I2STX1_APB 103 +#define JH7110_SYSRST_I2STX1_BCLK 104 +#define JH7110_SYSRST_TDM_AHB 105 +#define JH7110_SYSRST_TDM_CORE 106 +#define JH7110_SYSRST_TDM_APB 107 +#define JH7110_SYSRST_PWM_APB 108 +#define JH7110_SYSRST_WDT_APB 109 +#define JH7110_SYSRST_WDT_CORE 110 +#define JH7110_SYSRST_CAN0_APB 111 +#define JH7110_SYSRST_CAN0_CORE 112 +#define JH7110_SYSRST_CAN0_TIMER 113 +#define JH7110_SYSRST_CAN1_APB 114 +#define JH7110_SYSRST_CAN1_CORE 115 +#define JH7110_SYSRST_CAN1_TIMER 116 +#define JH7110_SYSRST_TIMER_APB 117 +#define JH7110_SYSRST_TIMER0 118 +#define JH7110_SYSRST_TIMER1 119 +#define JH7110_SYSRST_TIMER2 120 +#define JH7110_SYSRST_TIMER3 121 +#define JH7110_SYSRST_INT_CTRL_APB 122 +#define JH7110_SYSRST_TEMP_APB 123 +#define JH7110_SYSRST_TEMP_CORE 124 +#define JH7110_SYSRST_JTAG_CERTIFICATION 125 + +#define JH7110_SYSRST_END 126 + +/* AONCRG resets */ +#define JH7110_AONRST_GMAC0_AXI 0 +#define JH7110_AONRST_GMAC0_AHB 1 +#define JH7110_AONRST_IOMUX 2 +#define JH7110_AONRST_PMU_APB 3 +#define JH7110_AONRST_PMU_WKUP 4 +#define JH7110_AONRST_RTC_APB 5 +#define JH7110_AONRST_RTC_CAL 6 +#define JH7110_AONRST_RTC_32K 7 + +#define JH7110_AONRST_END 8 + +#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */ diff --git a/include/dt-bindings/reset/stih415-resets.h b/include/dt-bindings/reset/stih415-resets.h deleted file mode 100644 index 96f7831a1db0..000000000000 --- a/include/dt-bindings/reset/stih415-resets.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for the reset controller - * based peripheral powerdown requests on the STMicroelectronics - * STiH415 SoC. - */ -#ifndef _DT_BINDINGS_RESET_CONTROLLER_STIH415 -#define _DT_BINDINGS_RESET_CONTROLLER_STIH415 - -#define STIH415_EMISS_POWERDOWN 0 -#define STIH415_NAND_POWERDOWN 1 -#define STIH415_KEYSCAN_POWERDOWN 2 -#define STIH415_USB0_POWERDOWN 3 -#define STIH415_USB1_POWERDOWN 4 -#define STIH415_USB2_POWERDOWN 5 -#define STIH415_SATA0_POWERDOWN 6 -#define STIH415_SATA1_POWERDOWN 7 -#define STIH415_PCIE_POWERDOWN 8 - -#define STIH415_ETH0_SOFTRESET 0 -#define STIH415_ETH1_SOFTRESET 1 -#define STIH415_IRB_SOFTRESET 2 -#define STIH415_USB0_SOFTRESET 3 -#define STIH415_USB1_SOFTRESET 4 -#define STIH415_USB2_SOFTRESET 5 -#define STIH415_KEYSCAN_SOFTRESET 6 - -#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH415 */ diff --git a/include/dt-bindings/reset/stih416-resets.h b/include/dt-bindings/reset/stih416-resets.h deleted file mode 100644 index f682c906ed5a..000000000000 --- a/include/dt-bindings/reset/stih416-resets.h +++ /dev/null @@ -1,52 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for the reset controller - * based peripheral powerdown requests on the STMicroelectronics - * STiH416 SoC. - */ -#ifndef _DT_BINDINGS_RESET_CONTROLLER_STIH416 -#define _DT_BINDINGS_RESET_CONTROLLER_STIH416 - -#define STIH416_EMISS_POWERDOWN 0 -#define STIH416_NAND_POWERDOWN 1 -#define STIH416_KEYSCAN_POWERDOWN 2 -#define STIH416_USB0_POWERDOWN 3 -#define STIH416_USB1_POWERDOWN 4 -#define STIH416_USB2_POWERDOWN 5 -#define STIH416_USB3_POWERDOWN 6 -#define STIH416_SATA0_POWERDOWN 7 -#define STIH416_SATA1_POWERDOWN 8 -#define STIH416_PCIE0_POWERDOWN 9 -#define STIH416_PCIE1_POWERDOWN 10 - -#define STIH416_ETH0_SOFTRESET 0 -#define STIH416_ETH1_SOFTRESET 1 -#define STIH416_IRB_SOFTRESET 2 -#define STIH416_USB0_SOFTRESET 3 -#define STIH416_USB1_SOFTRESET 4 -#define STIH416_USB2_SOFTRESET 5 -#define STIH416_USB3_SOFTRESET 6 -#define STIH416_SATA0_SOFTRESET 7 -#define STIH416_SATA1_SOFTRESET 8 -#define STIH416_PCIE0_SOFTRESET 9 -#define STIH416_PCIE1_SOFTRESET 10 -#define STIH416_AUD_DAC_SOFTRESET 11 -#define STIH416_HDTVOUT_SOFTRESET 12 -#define STIH416_VTAC_M_RX_SOFTRESET 13 -#define STIH416_VTAC_A_RX_SOFTRESET 14 -#define STIH416_SYNC_HD_SOFTRESET 15 -#define STIH416_SYNC_SD_SOFTRESET 16 -#define STIH416_BLITTER_SOFTRESET 17 -#define STIH416_GPU_SOFTRESET 18 -#define STIH416_VTAC_M_TX_SOFTRESET 19 -#define STIH416_VTAC_A_TX_SOFTRESET 20 -#define STIH416_VTG_AUX_SOFTRESET 21 -#define STIH416_JPEG_DEC_SOFTRESET 22 -#define STIH416_HVA_SOFTRESET 23 -#define STIH416_COMPO_M_SOFTRESET 24 -#define STIH416_COMPO_A_SOFTRESET 25 -#define STIH416_VP8_DEC_SOFTRESET 26 -#define STIH416_VTG_MAIN_SOFTRESET 27 -#define STIH416_KEYSCAN_SOFTRESET 28 - -#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH416 */ |