static void ad_marker_response_received(struct bond_marker *marker,

struct port *port)

{

/* DO NOTHING, SINCE WE DECIDED NOT TO IMPLEMENT THIS FEATURE FOR NOW */

}

struct slave *slave;

struct list_head *iter;

struct bond_up_slave *new_arr, *old_arr;

int agg_id = 0;

int ret = 0;

}

goto out;

}

agg_id = ad_info.aggregator_id;

}

bond_for_each_slave(bond, slave, iter) {

ethernet switches chips.

config NET_DSA_MV88E6352

depends on NET_DSA

select NET_DSA_MV88E6XXX

select NET_DSA_TAG_EDSA

---help---

config NET_DSA_BCM_SF2

tristate "Broadcom Starfighter 2 Ethernet switch support"

struct fixed_phy_status *status)

{

struct bcm_sf2_priv *priv = ds_to_priv(ds);

u32 reg;

duplex = core_readl(priv, CORE_DUPSTS);

pause = core_readl(priv, CORE_PAUSESTS);

status->link = 0;

reg &= ~LINK_STS;

core_writel(priv, reg, CORE_STS_OVERRIDE_GMIIP_PORT(port));

if ((pause & (1 << port)) &&

(pause & (1 << (port + PAUSESTS_TX_PAUSE_SHIFT)))) {

status->asym_pause = 1;

return "Marvell 88E6172";

if ((ret & 0xfff0) == PORT_SWITCH_ID_6176)

return "Marvell 88E6176";

if (ret == PORT_SWITCH_ID_6352_A0)

return "Marvell 88E6352 (A0)";

if (ret == PORT_SWITCH_ID_6352_A1)

static int mv88e6352_get_temp(struct dsa_switch *ds, int *temp)

{

int ret;

*temp = 0;

if (ret < 0)

return ret;

static int mv88e6352_get_temp_limit(struct dsa_switch *ds, int *temp)

{

int ret;

*temp = 0;

if (ret < 0)

return ret;

static int mv88e6352_set_temp_limit(struct dsa_switch *ds, int temp)

{

int ret;

if (ret < 0)

return ret;

temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);

(ret & 0xe0ff) | (temp << 8));

}

static int mv88e6352_get_temp_alarm(struct dsa_switch *ds, bool *alarm)

{

int ret;

*alarm = false;

if (ret < 0)

return ret;

.fdb_getnext = mv88e6xxx_port_fdb_getnext,

};

MODULE_ALIAS("platform:mv88e6172");

return false;

}

static bool mv88e6xxx_6351_family(struct dsa_switch *ds)

{

struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);

{

int ret;

port = (port + 1) << 5;

/* Snapshot the hardware statistics counters for this port. */

if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||

mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||

mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||

/* MAC Forcing register: don't force link, speed,

* duplex or flow control state to any particular

* values on physical ports, but force the CPU port

if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||

mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||

mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||

reg = PORT_CONTROL_IGMP_MLD_SNOOP |

PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |

PORT_CONTROL_STATE_FORWARDING;

if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds))

reg |= PORT_CONTROL_DSA_TAG;

if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||

if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)

reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA;

else

if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||

mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||

mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||

if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)

reg |= PORT_CONTROL_EGRESS_ADD_TAG;

}

}

if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||

mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||

if (ds->dsa_port_mask & (1 << port))

reg |= PORT_CONTROL_FRAME_MODE_DSA;

if (port == dsa_upstream_port(ds))

reg = 0;

if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||

mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||

reg = PORT_CONTROL_2_MAP_DA;

if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||

reg |= PORT_CONTROL_2_JUMBO_10240;

if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds)) {

goto abort;

if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||

/* Do not limit the period of time that this port can

* be paused for by the remote end or the period of

* time that this port can pause the remote end.

if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||

mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||

/* Rate Control: disable ingress rate limiting. */

ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),

PORT_RATE_CONTROL, 0x0001);

(i << GLOBAL2_TRUNK_MAPPING_ID_SHIFT));

if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||

/* Send all frames with destination addresses matching

* 01:80:c2:00:00:2x to the CPU port.

*/

if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||

mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||

/* Disable ingress rate limiting by resetting all

* ingress rate limit registers to their initial

* state.

#define PORT_SWITCH_ID_6182 0x1a60

#define PORT_SWITCH_ID_6185 0x1a70

#define PORT_SWITCH_ID_6240 0x2400

#define PORT_SWITCH_ID_6350 0x3710

#define PORT_SWITCH_ID_6351 0x3750

#define PORT_SWITCH_ID_6352 0x3520

int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg);

int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page,

int reg, int val);

extern struct dsa_switch_driver mv88e6131_switch_driver;

extern struct dsa_switch_driver mv88e6123_61_65_switch_driver;

extern struct dsa_switch_driver mv88e6352_switch_driver;

*

* Copyright (c) 2007-2013 Broadcom Corporation

*

* This program is free software; you can redistribute it and/or modify

* it under the terms of the GNU General Public License as published by

* (you will need to reboot afterwards) */

/* #define BNX2X_STOP_ON_ERROR */

#define DRV_MODULE_RELDATE "2014/02/10"

#define BNX2X_BC_VER 0x040200

SUB_MF_MODE_UNKNOWN = 0,

SUB_MF_MODE_UFP,

SUB_MF_MODE_NPAR1_DOT_5,

};

struct bnx2x {

u8 mf_sub_mode;

#define IS_MF_UFP(bp) (IS_MF_SD(bp) && \

bp->mf_sub_mode == SUB_MF_MODE_UFP)

u8 wol;

void bnx2x_update_mng_version(struct bnx2x *bp);

#define MCPR_SCRATCH_BASE(bp) \

(CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)

*

* Copyright (c) 2007-2013 Broadcom Corporation

*

* This program is free software; you can redistribute it and/or modify

* it under the terms of the GNU General Public License as published by

if (rss_obj->udp_rss_v6)

__set_bit(BNX2X_RSS_IPV6_UDP, &params.rss_flags);

/* valid only for TUNN_MODE_GRE tunnel mode */

} else {

__set_bit(BNX2X_RSS_MODE_DISABLED, &params.rss_flags);

}

fp->mode = TPA_MODE_DISABLED;

}

int bnx2x_load_cnic(struct bnx2x *bp)

{

int i, rc, port = BP_PORT(bp);

/* mark driver is loaded in shmem2 */

u32 val;

val = SHMEM2_RD(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)]);

SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],

val | DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED |

DRV_FLAGS_CAPABILITIES_LOADED_L2);

return -EBUSY;

}

/* If PMF - send ADMIN DCBX msg to MFW to initiate DCBX FSM */

if (bp->port.pmf && (bp->state != BNX2X_STATE_DIAG))

bnx2x_dcbx_init(bp, false);

DP(NETIF_MSG_IFUP, "Ending successfully NIC load\n");

return 0;

DP(NETIF_MSG_IFUP, "Starting NIC unload\n");

/* mark driver is unloaded in shmem2 */

if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {

u32 val;

pbd2->fw_ip_hdr_to_payload_w =

hlen_w - ((sizeof(struct ipv6hdr)) >> 1);

pbd_e2->data.tunnel_data.flags |=

}

pbd2->tcp_send_seq = bswab32(inner_tcp_hdr(skb)->seq);

return NETDEV_TX_OK;

}

/**

* bnx2x_setup_tc - routine to configure net_device for multi tc

*

*/

int bnx2x_setup_tc(struct net_device *dev, u8 num_tc)

{

struct bnx2x *bp = netdev_priv(dev);

/* setup tc must be called under rtnl lock */

ASSERT_RTNL();

return -EINVAL;

}

/* configure priority to traffic class mapping */

for (prio = 0; prio < BNX2X_MAX_PRIORITY; prio++) {

DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,

"mapping priority %d to tc %d\n",

}

/* Use this configuration to differentiate tc0 from other COSes

if (netif_running(dev))

rc = bnx2x_set_eth_mac(bp, true);

return rc;

}

*/

dev->mtu = new_mtu;

return bnx2x_reload_if_running(dev);

}

*

* Copyright (c) 2007-2013 Broadcom Corporation

*

* This program is free software; you can redistribute it and/or modify

* it under the terms of the GNU General Public License as published by

*/

void bnx2x_tx_timeout(struct net_device *dev);

/*********************** Inlines **********************************/

/*********************** Fast path ********************************/

static inline void bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp)

start_params->mf_mode = bp->mf_mode;

start_params->sd_vlan_tag = bp->mf_ov;

if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp))

start_params->network_cos_mode = STATIC_COS;

else /* CHIP_IS_E1X */

start_params->network_cos_mode = FW_WRR;

if (IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {

start_params->class_fail_ethtype = ETH_P_FIP;

void bnx2x_schedule_sp_rtnl(struct bnx2x*, enum sp_rtnl_flag,

u32 verbose);

#endif /* BNX2X_CMN_H */

*

* Copyright 2009-2013 Broadcom Corporation

*

* agreement governing use of this software, this software is licensed to you

* under the terms of the GNU General Public License version 2, available

* at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").

*

* Notwithstanding the above, under no circumstances may you combine this

* consent.

*

* Maintained by: Ariel Elior <ariel.elior@qlogic.com>

if (bp->dcbx_port_params.ets.cos_params[cos].

pri_bitmask & pri_bit)

tt2cos[pri].cos = cos;

}

/* we never want the FW to add a 0 vlan tag */

*

* Copyright 2009-2013 Broadcom Corporation

*

* agreement governing use of this software, this software is licensed to you

* under the terms of the GNU General Public License version 2, available

* at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").

*

* Notwithstanding the above, under no circumstances may you combine this

* consent.

*

* Maintained by: Ariel Elior <ariel.elior@qlogic.com>

*

* Copyright (c) 2012-2013 Broadcom Corporation

*

* agreement governing use of this software, this software is licensed to you

* under the terms of the GNU General Public License version 2, available

* at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").

*

* Notwithstanding the above, under no circumstances may you combine this

* consent.

*/

*

* Copyright (c) 2007-2013 Broadcom Corporation

*

* This program is free software; you can redistribute it and/or modify

* it under the terms of the GNU General Public License as published by

} else

bp->wol = 0;

return 0;

}

info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |

(1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |

(1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |

info->tx_types = (1 << HWTSTAMP_TX_OFF)|(1 << HWTSTAMP_TX_ON);

*

* Copyright (c) 2007-2013 Broadcom Corporation

*

* This program is free software; you can redistribute it and/or modify

* it under the terms of the GNU General Public License as published by

#define MAX_COS_NUMBER 4

#define MAX_TRAFFIC_TYPES 8

#define MAX_PFC_PRIORITIES 8

/* used by array traffic_type_to_priority[] to mark traffic type \

that is not mapped to priority*/

#define LLFC_TRAFFIC_TYPE_TO_PRIORITY_UNMAPPED 0xFF

/* bnx2x_fw_file_hdr.h: FW binary file header structure.

*

* Copyright (c) 2007-2013 Broadcom Corporation

*

* This program is free software; you can redistribute it and/or modify

* it under the terms of the GNU General Public License as published by

*

* Copyright (c) 2007-2013 Broadcom Corporation

*

* This program is free software; you can redistribute it and/or modify

* it under the terms of the GNU General Public License as published by

#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722 0x00000f00

#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54616 0x00001000

#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84834 0x00001100

#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00

#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00

#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722 0x00000f00

#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616 0x00001000

#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834 0x00001100

#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC 0x0000fc00

#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00

#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00

#define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200

#define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT 0x00000300

#define SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE 0x00000400

#define SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE 0x00000600

#define SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE 0x00000700

#define FCOE_FEATURES4_FEATURE_SETTINGS_OFFSET 0

};

struct ncsi_oem_data {

u32 driver_version[4];

struct ncsi_oem_fcoe_features ncsi_oem_fcoe_features;

#define DRV_FLAGS_CAPABILITIES_LOADED_L2 0x00000002

#define DRV_FLAGS_CAPABILITIES_LOADED_FCOE 0x00000004

#define DRV_FLAGS_CAPABILITIES_LOADED_ISCSI 0x00000008

u32 extended_dev_info_shared_cfg_size;

u32 reserved4; /* Offset 0x150 */

u32 link_attr_sync[PORT_MAX]; /* Offset 0x154 */

#define LINK_ATTR_SYNC_KR2_ENABLE 0x00000001

#define LINK_SFP_EEPROM_COMP_CODE_MASK 0x0000ff00

#define LINK_SFP_EEPROM_COMP_CODE_SHIFT 8

#define LINK_SFP_EEPROM_COMP_CODE_SR 0x00001000

/* We use indication for each PF (0..3) */

#define MFW_DRV_IND_READ_DONE_OFFSET(_pf_) (1 << (_pf_))

};

};

#define BCM_5710_FW_MAJOR_VERSION 7

#define BCM_5710_FW_ENGINEERING_VERSION 0

#define BCM_5710_FW_COMPILE_FLAGS 1

__le16 len_on_bd;

struct parsing_flags pars_flags;

union eth_sgl_or_raw_data sgl_or_raw_data;

u32 marker;

};

__le16 pseudo_csum;

u8 ip_hdr_start_inner_w;

u8 flags;

#define ETH_TUNNEL_DATA_RESERVED (0x7F<<1)

#define ETH_TUNNEL_DATA_RESERVED_SHIFT 1

};

#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 6

#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_VXLAN_CAPABILITY (0x1<<7)

#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_VXLAN_CAPABILITY_SHIFT 7

u8 rss_result_mask;

u8 reserved3;

__le16 reserved4;

MAX_ETH_TUNNEL_NON_LSO_CSUM_LOCATION

};

/*

* Tx regular BD structure

*/

__le16 reserved1;

};

/*

* cfc delete event data

u8 dont_add_pri_0_en;

u8 reserved1;

__le32 reserved2;

};

u8 path_id;

u8 network_cos_mode;

u8 dmae_cmd_id;

__le16 vxlan_dst_port;

__le16 sd_accept_mf_clss_fail_ethtype;

__le16 sd_vlan_eth_type;

u8 sd_vlan_force_pri_flg;

u8 sd_vlan_force_pri_val;

};

struct function_update_data {

u8 tx_switch_suspend;

u8 echo;

u8 update_tunn_cfg_flg;

__le16 vxlan_dst_port;

u8 sd_vlan_force_pri_change_flg;

u8 sd_vlan_force_pri_flg;

u8 sd_vlan_force_pri_val;

u8 reserved1;

__le16 sd_vlan_tag;

__le16 sd_vlan_eth_type;

};

/*

#define __FW_VERSION_RESERVED_SHIFT 4

};

/*

* Dynamic Host-Coalescing - Driver(host) counters

*/

* Structures and macroes needed during the initialization.

*

* Copyright (c) 2007-2013 Broadcom Corporation

*

* This program is free software; you can redistribute it and/or modify

* it under the terms of the GNU General Public License as published by

* Static functions needed during the initialization.

* This file is "included" in bnx2x_main.c.

*

* Copyright (c) 2007-2013 Broadcom Corporation

*

* This program is free software; you can redistribute it and/or modify

* it under the terms of the GNU General Public License as published by

/* Copyright 2008-2013 Broadcom Corporation

*

* agreement governing use of this software, this software is licensed to you

* under the terms of the GNU General Public License version 2, available

*

* Notwithstanding the above, under no circumstances may you combine this

* consent.

*

* Written by Yaniv Rosner

/******************************************************************/

/* BCM8481/BCM84823/BCM84833 PHY SECTION */

/******************************************************************/

static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,

struct bnx2x *bp,

u8 port)

};

u16 fw_ver1;

bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1);

bnx2x_save_spirom_version(bp, port, fw_ver1 & 0xfff,

phy->ver_addr);

bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,

reg_set[i].val);

offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1;

else

offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1;

struct bnx2x *bp = params->bp;

switch (action) {

case PHY_INIT:

/* Save spirom version */

bnx2x_save_848xx_spirom_version(phy, bp, params->port);

}

/* Always write this if this is not 84833/4.

* For 84833/4, write it only when it's a forced speed.

*/

((autoneg_val & (1<<12)) == 0))

bnx2x_cl45_write(bp, phy,

MDIO_AN_DEVAD,

return bnx2x_848xx_cmn_config_init(phy, params, vars);

}

static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy,

struct link_params *params, u16 fw_cmd,

u16 cmd_args[], int argc)

struct bnx2x *bp = params->bp;

/* Write CMD_OPEN_OVERRIDE to STATUS reg */

bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,

PHY84833_STATUS_CMD_OPEN_OVERRIDE);

bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,

if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS)

break;

usleep_range(1000, 2000);

}

DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n");

return -EINVAL;

}

/* Prepare argument(s) and issue command */

for (idx = 0; idx < argc; idx++) {

bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,

cmd_args[idx]);

}

bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,

bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,

if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) ||

break;

usleep_range(1000, 2000);

}

DP(NETIF_MSG_LINK, "FW cmd failed.\n");

return -EINVAL;

}

/* Gather returning data */

for (idx = 0; idx < argc; idx++) {

bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,

&cmd_args[idx]);

}

bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,

PHY84833_STATUS_CMD_CLEAR_COMPLETE);

return 0;

}

{

u32 pair_swap;

int status;

struct bnx2x *bp = params->bp;

/* Only the second argument is used for this command */

data[1] = (u16)pair_swap;

if (status == 0)

DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data[1]);

DP(NETIF_MSG_LINK, "Don't Advertise 10GBase-T EEE\n");

/* Prevent Phy from working in EEE and advertising it */

if (rc) {

DP(NETIF_MSG_LINK, "EEE disable failed.\n");

return rc;

struct bnx2x *bp = params->bp;

u16 cmd_args = 1;

if (rc) {

DP(NETIF_MSG_LINK, "EEE enable failed.\n");

return rc;

u8 port, initialize = 1;

u16 val;

u32 actual_phy_selection;

int rc = 0;

usleep_range(1000, 2000);

/* Wait for GPHY to come out of reset */

msleep(50);

/* BCM84823 requires that XGXS links up first @ 10G for normal

* behavior.

*/

bnx2x_program_serdes(&params->phy[INT_PHY], params, vars);

vars->line_speed = temp;

}

bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,

MDIO_CTL_REG_84823_MEDIA, &val);

val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |

DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",

params->multi_phy_config, val);

/* Keep AutogrEEEn disabled. */

cmd_args[0] = 0x0;

cmd_args[1] = 0x0;

cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1;

cmd_args[3] = PHY84833_CONSTANT_LATENCY;

if (rc)

DP(NETIF_MSG_LINK, "Cfg AutogrEEEn failed.\n");

}

vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK;

}

/* Bring PHY out of super isolate mode as the final step. */

bnx2x_cl45_read_and_write(bp, phy,

MDIO_CTL_DEVAD,

LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;

/* Determine if EEE was negotiated */

bnx2x_eee_an_resolve(phy, params, vars);

}

.phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func

};

static const struct bnx2x_phy phy_54618se = {

.type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE,

.addr = 0xff,

case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:

*phy = phy_84834;

break;

case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616:

case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE:

*phy = phy_54618se;

}

phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);

/* Remove 100Mb link supported for BCM84833/4 when phy fw

* version lower than or equal to 1.39

*/

break;

case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:

case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:

/* GPIO3's are linked, and so both need to be toggled

* to obtain required 2us pulse.

*/

/* Copyright 2008-2013 Broadcom Corporation

*

* agreement governing use of this software, this software is licensed to you

* under the terms of the GNU General Public License version 2, available

*

* Notwithstanding the above, under no circumstances may you combine this

* consent.

*

* Written by Yaniv Rosner

*

* Copyright (c) 2007-2013 Broadcom Corporation

*

* This program is free software; you can redistribute it and/or modify

* it under the terms of the GNU General Public License as published by

#define TX_TIMEOUT (5*HZ)

static char version[] =

DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";

MODULE_AUTHOR("Eliezer Tamir");

"BCM57710/57711/57711E/"

"57712/57712_MF/57800/57800_MF/57810/57810_MF/"

"57840/57840_MF Driver");

static struct {

char *name;

} board_info[] = {

};

#ifndef PCI_DEVICE_ID_NX2_57710

func_params.f_obj = &bp->func_obj;

func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;

int func = BP_ABS_FUNC(bp);

u32 val;

BNX2X_ERR("Failed to configure FW of S-tag Change to %02x\n",

bp->mf_ov);

goto fail;

}

}

fail:

bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE, 0);

}

ethver, iscsiver, fcoever);

}

static void bnx2x_oem_event(struct bnx2x *bp, u32 event)

{

u32 cmd_ok, cmd_fail;

BNX2X_STATE_OPEN):

case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |

BNX2X_STATE_OPENING_WAIT4_PORT):

cid = elem->message.data.eth_event.echo &

BNX2X_SWCID_MASK;

DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",

} else

BNX2X_ERR("Bootcode is missing - can not initialize link\n");

return 0;

}

static int bnx2x_get_hwinfo(struct bnx2x *bp)

{

int /*abs*/func = BP_ABS_FUNC(bp);

u32 val = 0, val2 = 0;

int rc = 0;

bp->mf_mode = 0;

bp->mf_sub_mode = 0;

vn = BP_VN(bp);

if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {

BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",

} else

BNX2X_DEV_INFO("illegal OV for SD\n");

break;

case SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE:

bp->mf_mode = MULTI_FUNCTION_SD;

bp->mf_sub_mode = SUB_MF_MODE_UFP;

BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",

func, bp->mf_ov, bp->mf_ov);

dev_err(&bp->pdev->dev,

func);

bp->path_has_ovlan = true;

} else {

bnx2x_register_phc(bp);

return 0;

init_one_exit:

/* Power on: we can't let PCI layer write to us while we are in D3 */

if (IS_PF(bp)) {

bnx2x_set_power_state(bp, PCI_D0);

/* Set endianity registers to reset values in case next driver

* boots in different endianty environment.

*

* Copyright (c) 2012-2013 Broadcom Corporation

*

* This program is free software; you can redistribute it and/or modify

* it under the terms of the GNU General Public License as published by

*

* Copyright (c) 2007-2013 Broadcom Corporation

*

* This program is free software; you can redistribute it and/or modify

* it under the terms of the GNU General Public License as published by

/* [RW 1] When this bit is set; the LLH will expect all packets to be with

e1hov */

#define NIG_REG_LLH_E1HOV_MODE 0x160d8

/* [RW 1] When this bit is set; the LLH will classify the packet before

sending it to the BRB or calculating WoL on it. */

#define NIG_REG_LLH_MF_MODE 0x16024

#define PBF_REG_TQ_OCCUPANCY_Q0 0x1403ac

/* [R 13] Number of 8 bytes lines occupied in the task queue of queue 1. */

#define PBF_REG_TQ_OCCUPANCY_Q1 0x1403b0

/* [RW 2] Interrupt mask register #0 read/write */

#define PB_REG_PB_INT_MASK 0x28

/* [R 2] Interrupt register #0 read */

#define PRS_REG_TCM_CURRENT_CREDIT 0x40160

/* [R 8] debug only: TSDM current credit. Transaction based. */

#define PRS_REG_TSDM_CURRENT_CREDIT 0x4015c

#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT (0x1<<19)

#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF (0x1<<20)

#define PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN (0x1<<22)

#define MDIO_AN_REG_8481_LEGACY_MII_CTRL 0xffe0

#define MDIO_AN_REG_8481_MII_CTRL_FORCE_1G 0x40

#define MDIO_AN_REG_8481_LEGACY_MII_STATUS 0xffe1

#define MDIO_AN_REG_8481_LEGACY_AN_ADV 0xffe4

#define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION 0xffe6

#define MDIO_AN_REG_8481_1000T_CTRL 0xffe9

#define MDIO_84833_TOP_CFG_FW_NO_EEE 0x1f81

#define MDIO_84833_TOP_CFG_XGPHY_STRAP1 0x401a

#define MDIO_84833_SUPER_ISOLATE 0x8000

#define PHY84833_STATUS_CMD_RECEIVED 0x0001

#define PHY84833_STATUS_CMD_IN_PROGRESS 0x0002

#define PHY84833_STATUS_CMD_COMPLETE_PASS 0x0004

#define PHY84833_STATUS_CMD_CLEAR_COMPLETE 0x0080

#define PHY84833_STATUS_CMD_OPEN_OVERRIDE 0xa5a5

/* Warpcore clause 45 addressing */

#define MDIO_WC_DEVAD 0x3

*

*

* agreement governing use of this software, this software is licensed to you

* under the terms of the GNU General Public License version 2, available

*

* Notwithstanding the above, under no circumstances may you combine this

* consent.

*

* Maintained by: Ariel Elior <ariel.elior@qlogic.com>

if (test_bit(BNX2X_RSS_IPV6_UDP, &p->rss_flags))

caps |= ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY;

/* RSS keys */

if (test_bit(BNX2X_RSS_SET_SRCH, &p->rss_flags)) {

rdata->sd_vlan_tag = cpu_to_le16(start_params->sd_vlan_tag);

rdata->path_id = BP_PATH(bp);

rdata->network_cos_mode = start_params->network_cos_mode;

rdata->sd_accept_mf_clss_fail = start_params->class_fail;

if (start_params->class_fail_ethtype) {

rdata->sd_accept_mf_clss_fail_match_ethtype = 1;

cpu_to_le16(0x8100);

rdata->no_added_tags = start_params->no_added_tags;

/* No need for an explicit memory barrier here as long we would

* need to ensure the ordering of writing to the SPQ element

* and updating of the SPQ producer which involves a memory

if (test_bit(BNX2X_F_UPDATE_TUNNEL_CFG_CHNG,

&switch_update_params->changes)) {

rdata->update_tunn_cfg_flg = 1;

&switch_update_params->changes))

&switch_update_params->changes))

}

rdata->echo = SWITCH_UPDATE;

rdata->traffic_type_to_priority_cos[i] =

tx_start_params->traffic_type_to_priority_cos[i];

/* No need for an explicit memory barrier here as long as we

* ensure the ordering of writing to the SPQ element

* and updating of the SPQ producer which involves a memory

*

*

* agreement governing use of this software, this software is licensed to you

* under the terms of the GNU General Public License version 2, available

*

* Notwithstanding the above, under no circumstances may you combine this

* consent.

*

* Maintained by: Ariel Elior <ariel.elior@qlogic.com>

BNX2X_RSS_IPV6,

BNX2X_RSS_IPV6_TCP,

BNX2X_RSS_IPV6_UDP,

};

struct bnx2x_config_rss_params {

BNX2X_F_UPDATE_VLAN_FORCE_PRIO_CHNG,

BNX2X_F_UPDATE_VLAN_FORCE_PRIO_FLAG,

BNX2X_F_UPDATE_TUNNEL_CFG_CHNG,

};

/* Allowed Function states */

/* Function cos mode */

u8 network_cos_mode;

/* Allows accepting of packets failing MF classification, possibly

* only matching a given ethertype

/* Prevent inner vlans from being added by FW */

u8 no_added_tags;

};

struct bnx2x_func_switch_update_params {

u16 vlan;

u16 vlan_eth_type;

u8 vlan_force_prio;

};

struct bnx2x_func_afex_update_params {

u8 dcb_enabled;

u8 dcb_version;

u8 dont_add_pri_0_en;

};

struct bnx2x_func_set_timesync_params {

*

* Copyright 2009-2013 Broadcom Corporation

*

* agreement governing use of this software, this software is licensed to you

* under the terms of the GNU General Public License version 2, available

* at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").

*

* Notwithstanding the above, under no circumstances may you combine this

* consent.

*

* Maintained by: Ariel Elior <ariel.elior@qlogic.com>

mutex_init(&bp->vfdb->bulletin_mutex);

return 0;

failed:

DP(BNX2X_MSG_IOV, "Failed err=%d\n", err);

*

* Copyright 2009-2013 Broadcom Corporation

*

* agreement governing use of this software, this software is licensed to you

* under the terms of the GNU General Public License version 2, available

* at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").

*

* Notwithstanding the above, under no circumstances may you combine this

* consent.

*

* Maintained by: Ariel Elior <ariel.elior@qlogic.com>

*

* Copyright (c) 2007-2013 Broadcom Corporation

*

* This program is free software; you can redistribute it and/or modify

* it under the terms of the GNU General Public License as published by

*

* Copyright (c) 2007-2013 Broadcom Corporation

*

* This program is free software; you can redistribute it and/or modify

* it under the terms of the GNU General Public License as published by

*

* Copyright 2009-2013 Broadcom Corporation

*

* agreement governing use of this software, this software is licensed to you

* under the terms of the GNU General Public License version 2, available

* at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").

*

* Notwithstanding the above, under no circumstances may you combine this

* consent.

*

* Maintained by: Ariel Elior <ariel.elior@qlogic.com>

*

* Copyright (c) 2011-2013 Broadcom Corporation

*

* agreement governing use of this software, this software is licensed to you

*

*

* Maintained by: Ariel Elior <ariel.elior@qlogic.com>

* Written by: Ariel Elior <ariel.elior@qlogic.com>

}

bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);

if (mode == GENET_POWER_PASSIVE)

}

/* ioctl handle special commands that are not present in ethtool. */

int0_enable |= UMAC_IRQ_TXDMA_DONE;

/* Monitor cable plug/unplugged event for internal PHY */

int0_enable |= UMAC_IRQ_LINK_EVENT;

} else if (priv->ext_phy) {

int0_enable |= UMAC_IRQ_LINK_EVENT;

/* If this is an internal GPHY, power it back on now, before UniMAC is

* brought out of reset as absolutely no UniMAC activity is allowed

*/

bcmgenet_power_up(priv, GENET_POWER_PASSIVE);

/* take MAC out of reset */

bcmgenet_set_hw_addr(priv, dev->dev_addr);

reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);

reg |= EXT_ENERGY_DET_MASK;

bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);

goto err_irq0;

}

bcmgenet_netif_start(dev);

return 0;

err_irq0:

err_fini_dma:

bcmgenet_fini_dma(priv);

err_clk_disable:

free_irq(priv->irq0, priv);

free_irq(priv->irq1, priv);

ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);

if (!IS_ERR(priv->clk))

if (device_may_wakeup(d) && priv->wolopts) {

ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);

clk_prepare_enable(priv->clk_wol);

ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);

}

/* If this is an internal GPHY, power it back on now, before UniMAC is

* brought out of reset as absolutely no UniMAC activity is allowed

*/

bcmgenet_power_up(priv, GENET_POWER_PASSIVE);

bcmgenet_umac_reset(priv);

phy_init_hw(priv->phydev);

/* Speed settings must be restored */

/* disable ethernet MAC while updating its registers */

umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);

bcmgenet_set_hw_addr(priv, dev->dev_addr);

reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);

reg |= EXT_ENERGY_DET_MASK;

bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);

/* MDIO bus variables */

wait_queue_head_t wq;

struct phy_device *phydev;

struct device_node *phy_dn;

struct device_node *mdio_dn;

struct mii_bus *mii_bus;

/* MDIO routines */

int bcmgenet_mii_init(struct net_device *dev);

void bcmgenet_mii_exit(struct net_device *dev);

void bcmgenet_phy_power_set(struct net_device *dev, bool enable);

void bcmgenet_mii_setup(struct net_device *dev);

phy_print_status(phydev);

}

void bcmgenet_phy_power_set(struct net_device *dev, bool enable)

{

struct bcmgenet_priv *priv = netdev_priv(dev);

reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);

reg |= EXT_PWR_DN_EN_LD;

bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);

}

static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv)

bcmgenet_sys_writel(priv, reg, SYS_PORT_CTRL);

}

{

struct bcmgenet_priv *priv = netdev_priv(dev);

struct phy_device *phydev = priv->phydev;

u32 port_ctrl;

u32 reg;

(priv->phy_interface != PHY_INTERFACE_MODE_MOCA);

priv->phy_interface = PHY_INTERFACE_MODE_NA;

switch (priv->phy_interface) {

bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL);

phy_name = "internal PHY";

bcmgenet_internal_phy_setup(dev);

} else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {

bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);

}

return 0;

}

{

struct bcmgenet_priv *priv = netdev_priv(dev);

struct device_node *dn = priv->pdev->dev.of_node;

priv->old_pause = -1;

if (dn) {

phydev = of_phy_connect(dev, priv->phy_dn, bcmgenet_mii_setup,

phy_flags, priv->phy_interface);

if (!phydev) {

* PHY speed which is needed for bcmgenet_mii_config() to configure

* things appropriately.

*/

if (ret) {

phy_disconnect(priv->phydev);

return ret;

/* The internal PHY has its link interrupts routed to the

* Ethernet MAC ISRs

*/

priv->mii_bus->irq[phydev->addr] = PHY_IGNORE_INTERRUPT;

else

priv->mii_bus->irq[phydev->addr] = PHY_POLL;

return 0;

}

{

struct device_node *dn = priv->pdev->dev.of_node;

struct device *kdev = &priv->pdev->dev;

char *compat;

int ret;

compat = kasprintf(GFP_KERNEL, "brcm,genet-mdio-v%d", priv->version);

/* Fetch the PHY phandle */

priv->phy_dn = of_parse_phandle(dn, "phy-handle", 0);

/* Get the link mode */

return 0;

}

ret = bcmgenet_mii_bus_init(priv);

if (ret)

goto out;

return 0;

out:

of_node_put(priv->phy_dn);

mdiobus_unregister(priv->mii_bus);

kfree(priv->mii_bus->irq);

mdiobus_free(priv->mii_bus);

return ret;

static const struct macb_config zynqmp_config = {

.dma_burst_length = 16,

.clk_init = macb_clk_init,

.init = macb_init,

};

static const struct macb_config zynq_config = {

.dma_burst_length = 16,

.clk_init = macb_clk_init,

.init = macb_init,

bool tid_release_task_busy;

struct dentry *debugfs_root;

spinlock_t stats_lock;

spinlock_t win0_lock ____cacheline_aligned_in_smp;

"Auto Negotiated"

};

/* Initialize a port's Data Center Bridging state. Typically used after a

* Link Down event.

*/

struct port_info *pi = netdev2pinfo(dev);

struct port_dcb_info *dcb = &pi->dcb;

priority >= CXGB4_MAX_PRIORITY)

*pfccfg = 0;

else

struct adapter *adap = pi->adapter;

int err;

priority >= CXGB4_MAX_PRIORITY)

return;

{

struct port_info *pi = netdev2pinfo(dev);

return false;

return pi->dcb.pfcen != 0;

struct adapter *adap = pi->adapter;

int i;

return 0;

for (i = 0; i < CXGB4_MAX_DCBX_APP_SUPPORTED; i++) {

*/

static int cxgb4_getapp(struct net_device *dev, u8 app_idtype, u16 app_id)

{

}

/* Write a new Application User Priority Map for the specified Application ID

int i, err;

return -EINVAL;

/* DCB info gets thrown away on link up */

struct port_info *pi = netdev2pinfo(dev);

struct port_dcb_info *dcb = &pi->dcb;

(dcb->supported & DCB_CAP_DCBX_VER_IEEE));

}

/* Can't enable DCB if we haven't successfully negotiated it.

*/

return 1;

/* There's currently no mechanism to allow for the firmware DCBX

struct adapter *adap = pi->adapter;

int i, err = 0;

return 1;

info->willing = 0;

struct adapter *adap = pi->adapter;

int i, err = 0;

return 1;

for (i = 0; i < CXGB4_MAX_DCBX_APP_SUPPORTED; i++) {

if (!pcmd.u.dcb.app_priority.protocolid)

break;

table[i].protocol =

be16_to_cpu(pcmd.u.dcb.app_priority.protocolid);

table[i].priority =

for (i = 0; i < CXGB4_MAX_PRIORITY; i++)

pg->pg_bw[i] = pcmd.u.dcb.pgrate.pgrate[i];

return 0;

}

*/

pfc->pfc_en = bitswap_1(pi->dcb.pfcen);

return 0;

}

return 0;

}

static int cim_la_open(struct inode *inode, struct file *file)

{

int ret;

if (ret)

return ret;

if (!p)

return -ENOMEM;

de = debugfs_create_file_size("flash", S_IRUSR, adap->debugfs_root, adap,

&flash_debugfs_fops, adap->params.sf_size);

return 0;

}

*/

cfg_queues(adapter);

if (!adapter->l2t) {

/* We tolerate a lack of L2T, giving up some functionality */

dev_warn(&pdev->dev, "could not allocate L2T, continuing\n");

#define VLAN_NONE 0xfff

/* identifies sync vs async L2T_WRITE_REQs */

struct l2t_data {

rwlock_t lock;

atomic_t nfree; /* number of free entries */

struct l2t_entry *rover; /* starting point for next allocation */

};

static inline unsigned int vlan_prio(const struct l2t_entry *e)

/*

* To avoid having to check address families we do not allow v4 and v6

* neighbors to be on the same hash chain. We keep v4 entries in the first

*/

enum {

};

{

}

{

u32 xor = key[0] ^ key[1] ^ key[2] ^ key[3];

}

{

}

/*

*/

static int write_l2e(struct adapter *adap, struct l2t_entry *e, int sync)

{

struct sk_buff *skb;

struct cpl_l2t_write_req *req;

INIT_TP_WR(req, 0);

OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_L2T_WRITE_REQ,

TID_QID_V(adap->sge.fw_evtq.abs_id)));

req->params = htons(L2T_W_PORT_V(e->lport) | L2T_W_NOREPLY_V(!sync));

req->vlan = htons(e->vlan);

if (e->neigh && !(e->neigh->dev->flags & IFF_LOOPBACK))

memcpy(e->dmac, e->neigh->ha, sizeof(e->dmac));

*/

void do_l2t_write_rpl(struct adapter *adap, const struct cpl_l2t_write_rpl *rpl)

{

unsigned int tid = GET_TID(rpl);

if (unlikely(rpl->status != CPL_ERR_NONE)) {

dev_err(adap->pdev_dev,

"Unexpected L2T_WRITE_RPL status %u for entry %u\n",

return;

}

spin_lock(&e->lock);

if (e->state != L2T_STATE_SWITCHING) {

return NULL;

/* there's definitely a free entry */

if (atomic_read(&e->refcnt) == 0)

goto found;

int addr_len = neigh->tbl->key_len;

u32 *addr = (u32 *)neigh->primary_key;

int ifidx = neigh->dev->ifindex;

if (neigh->dev->flags & IFF_LOOPBACK)

lport = netdev2pinfo(physdev)->tx_chan + 4;

int addr_len = neigh->tbl->key_len;

u32 *addr = (u32 *) neigh->primary_key;

int ifidx = neigh->dev->ifindex;

read_lock_bh(&d->lock);

for (e = d->l2tab[hash].first; e; e = e->next)

return write_l2e(adap, e, 0);

}

{

int i;

struct l2t_data *d;

if (!d)

return NULL;

d->rover = d->l2tab;

rwlock_init(&d->lock);

d->l2tab[i].idx = i;

d->l2tab[i].state = L2T_STATE_UNUSED;

spin_lock_init(&d->l2tab[i].lock);

static inline void *l2t_get_idx(struct seq_file *seq, loff_t pos)

{

}

static void *l2t_seq_start(struct seq_file *seq, loff_t *pos)

"Ethernet address VLAN/P LP State Users Port\n");

else {

char ip[60];

struct l2t_entry *e = v;

spin_lock_bh(&e->lock);

else

sprintf(ip, e->v6 ? "%pI6c" : "%pI4", e->addr);

seq_printf(seq, "%4u %-25s %17pM %4d %u %2u %c %5u %s\n",

e->vlan & VLAN_VID_MASK, vlan_prio(e), e->lport,

l2e_state(e), atomic_read(&e->refcnt),

e->neigh ? e->neigh->dev->name : "");

struct adapter *adap = inode->i_private;

struct seq_file *seq = file->private_data;

}

return rc;

}

#include <linux/if_ether.h>

#include <linux/atomic.h>

struct adapter;

struct l2t_data;

struct neighbour;

*/

struct l2t_entry {

u16 state; /* entry state */

u32 addr[4]; /* next hop IP or IPv6 address */

int ifindex; /* neighbor's net_device's ifindex */

struct neighbour *neigh; /* associated neighbour */

struct l2t_entry *t4_l2t_alloc_switching(struct l2t_data *d);

int t4_l2t_set_switching(struct adapter *adap, struct l2t_entry *e, u16 vlan,

u8 port, u8 *eth_addr);

void do_l2t_write_rpl(struct adapter *p, const struct cpl_l2t_write_rpl *rpl);

extern const struct file_operations t4_l2t_fops;

*/

netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev)

{

u64 cntrl, *end;

int qidx, credits;

unsigned int flits, ndesc;

#endif /* CONFIG_CHELSIO_T4_FCOE */

}

cpl->pack = htons(0);

cpl->len = htons(skb->len);

cpl->ctrl1 = cpu_to_be64(cntrl);

0x5a80, 0x5a9c,

0x5b94, 0x5bfc,

0x5c10, 0x5ec0,

0x6000, 0x6040,

0x7700, 0x7798,

0x77c0, 0x7880,

0x78cc, 0x78fc,

0x9f00, 0x9f6c,

0x9f80, 0xa020,

0xd004, 0xd03c,

0xdfc0, 0xdfe0,

0xe000, 0xf008,

0x11000, 0x11014,

0x11048, 0x11110,

0x11118, 0x1117c,

0x11300, 0x1130c,

0x19040, 0x1906c,

0x19078, 0x19080,

0x1908c, 0x19124,

0x19150, 0x191b0,

0x191d0, 0x191e8,

0x193f8, 0x19474,

0x19490, 0x194cc,

0x194f0, 0x194f8,

0x30200, 0x30318,

0x30400, 0x3052c,

0x30540, 0x3061c,

0x308c0, 0x30908,

0x30910, 0x309b8,

0x30a00, 0x30a04,

0x34200, 0x34318,

0x34400, 0x3452c,

0x34540, 0x3461c,

0x348c0, 0x34908,

0x34910, 0x349b8,

0x34a00, 0x34a04,

return 0;

}

/**

* t4_fw_tp_pio_rw - Access TP PIO through LDST

* @adap: the adapter

*/

void t4_read_rss_key(struct adapter *adap, u32 *key)

{

t4_fw_tp_pio_rw(adap, key, 10, TP_RSS_SECRET_KEY0_A, 1);

else

t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10,

(vrt & KEYEXTEND_F) && (KEYMODE_G(vrt) == 3))

rss_key_addr_cnt = 32;

t4_fw_tp_pio_rw(adap, (void *)key, 10, TP_RSS_SECRET_KEY0_A, 0);

else

t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10,

void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,

u32 *valp)

{

t4_fw_tp_pio_rw(adapter, valp, 1,

TP_RSS_PF0_CONFIG_A + index, 1);

else

/* Grab the VFL/VFH values ...

*/

t4_fw_tp_pio_rw(adapter, vfl, 1, TP_RSS_VFL_CONFIG_A, 1);

t4_fw_tp_pio_rw(adapter, vfh, 1, TP_RSS_VFH_CONFIG_A, 1);

} else {

{

u32 pfmap;

t4_fw_tp_pio_rw(adapter, &pfmap, 1, TP_RSS_PF_MAP_A, 1);

else

t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,

{

u32 pfmask;

t4_fw_tp_pio_rw(adapter, &pfmask, 1, TP_RSS_PF_MSK_A, 1);

else

t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,

*/

void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st)

{

t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,

&st->ofld_no_neigh, 2, TP_MIB_OFD_ARP_DROP_A);

}

*/

void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st)

{

}

/**

/* Cache the adapter's Compressed Filter Mode and global Incress

* Configuration.

*/

t4_fw_tp_pio_rw(adap, &adap->params.tp.vlan_pri_map, 1,

TP_VLAN_PRI_MAP_A, 1);

t4_fw_tp_pio_rw(adap, &adap->params.tp.ingress_config, 1,

TCB_SIZE = 128, /* TCB size */

NMTUS = 16, /* size of MTU table */

NCCTRL_WIN = 32, /* # of congestion control windows */

PM_NSTATS = 5, /* # of PM stats */

MBOX_LEN = 64, /* mailbox size in bytes */

TRACE_LEN = 112, /* length of trace data and mask */

#define TXPKT_OVLAN_IDX_S 12

#define TXPKT_OVLAN_IDX_V(x) ((x) << TXPKT_OVLAN_IDX_S)

#define TXPKT_INTF_S 16

#define TXPKT_INTF_V(x) ((x) << TXPKT_INTF_S)

CH_PCI_ID_TABLE_FENTRY(0x5013), /* T580-chr */

CH_PCI_ID_TABLE_FENTRY(0x5014), /* T580-so */

CH_PCI_ID_TABLE_FENTRY(0x5015), /* T502-bt */

CH_PCI_ID_TABLE_FENTRY(0x5080), /* Custom T540-cr */

CH_PCI_ID_TABLE_FENTRY(0x5081), /* Custom T540-LL-cr */

CH_PCI_ID_TABLE_FENTRY(0x5082), /* Custom T504-cr */

CH_PCI_ID_TABLE_FENTRY(0x5090), /* Custom T540-CR */

CH_PCI_ID_TABLE_FENTRY(0x5091), /* Custom T522-CR */

CH_PCI_ID_TABLE_FENTRY(0x5092), /* Custom T520-CR */

CH_PCI_DEVICE_ID_TABLE_DEFINE_END;

#endif /* __T4_PCI_ID_TBL_H__ */

rspq->unhandled_irqs++;

val = CIDXINC_V(work_done) | SEINTARM_V(intr_params);

t4_write_reg(rspq->adapter,

T4VF_SGE_BASE_ADDR + SGE_VF_GTS,

val | INGRESSQID_V((u32)rspq->cntxt_id));

}

val = CIDXINC_V(work_done) | SEINTARM_V(intrq->intr_params);

t4_write_reg(adapter, T4VF_SGE_BASE_ADDR + SGE_VF_GTS,

val | INGRESSQID_V(intrq->cntxt_id));

writel(val | INGRESSQID_V(intrq->bar2_qid),

intrq->bar2_addr + SGE_UDB_GTS);

wmb();

struct enic *enic = netdev_priv(netdev);

struct enic_rx_coal *rxcoal = &enic->rx_coalesce_setting;

ecmd->rx_coalesce_usecs = enic->rx_coalesce_usecs;

if (rxcoal->use_adaptive_rx_coalesce)

ecmd->use_adaptive_rx_coalesce = 1;

return 0;

}

static int enic_set_coalesce(struct net_device *netdev,

struct ethtool_coalesce *ecmd)

{

u32 rx_coalesce_usecs_high;

u32 coalesce_usecs_max;

unsigned int i, intr;

struct enic_rx_coal *rxcoal = &enic->rx_coalesce_setting;

coalesce_usecs_max = vnic_dev_get_intr_coal_timer_max(enic->vdev);

tx_coalesce_usecs = min_t(u32, ecmd->tx_coalesce_usecs,

coalesce_usecs_max);

rx_coalesce_usecs_high = min_t(u32, ecmd->rx_coalesce_usecs_high,

coalesce_usecs_max);

for (i = 0; i < enic->wq_count; i++) {

intr = enic_msix_wq_intr(enic, i);

vnic_intr_coalescing_timer_set(&enic->intr[intr],

}

}

enic->rx_coalesce_usecs = rx_coalesce_usecs;

return 0;

return 0;

}

static int enic_poll(struct napi_struct *napi, int budget)

{

struct net_device *netdev = napi->dev;

if (err)

rq_work_done = rq_work_to_do;

if (rq_work_done < rq_work_to_do) {

*/

napi_complete(napi);

vnic_intr_unmask(&enic->intr[intr]);

}

return rq_work_done;

}

#ifdef CONFIG_RFS_ACCEL

static void enic_free_rx_cpu_rmap(struct enic *enic)

{

if (err)

work_done = work_to_do;

if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce)

*/

enic_calc_int_moderation(enic, &enic->rq[rq]);

int index = -1;

struct enic_rx_coal *rx_coal = &enic->rx_coalesce_setting;

/* 1. Read the link speed from fw

* 2. Pick the default range for the speed

* 3. Update it in enic->rx_coalesce_setting

.probe = ec_bhf_probe,

.remove = ec_bhf_remove,

};

module_param(polling_frequency, long, S_IRUGO);

MODULE_PARM_DESC(polling_frequency, "Polling timer frequency in ns");

#include "be_hw.h"

#include "be_roce.h"

#define DRV_NAME "be2net"

#define BE_NAME "Emulex BladeEngine2"

#define BE3_NAME "Emulex BladeEngine3"

return wrb->payload.embedded_payload;

}

{

struct be_queue_info *mccq = &adapter->mcc_obj.q;

u32 val = 0;

if (be_check_error(adapter, BE_ERROR_ANY))

val |= mccq->id & DB_MCCQ_RING_ID_MASK;

val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;

wmb();

iowrite32(val, adapter->db + DB_MCCQ_OFFSET);

}

/* To check if valid bit is set, check the entire word as we don't know

return;

}

if ((opcode == OPCODE_COMMON_WRITE_FLASHROM ||

opcode == OPCODE_COMMON_WRITE_OBJECT) &&

subsystem == CMD_SUBSYSTEM_COMMON) {

resp = be_decode_resp_hdr(wrb->tag0, wrb->tag1);

status = be_mcc_wait_compl(adapter);

if (status == -EIO)

else

hdr->version = 2;

adapter->stats_cmd_sent = true;

err:

req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num);

req->cmd_params.params.reset_stats = 0;

adapter->stats_cmd_sent = true;

err:

OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES,

sizeof(*req), wrb, NULL);

err:

spin_unlock_bh(&adapter->mcc_lock);

return status;

cpu_to_le32(set_eqd[i].delay_multiplier);

}

err:

spin_unlock_bh(&adapter->mcc_lock);

return status;

memcpy(req->mcast_mac[i++].byte, ha->addr, ETH_ALEN);

}

err:

spin_unlock_bh(&adapter->mcc_lock);

return status;

req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +

sizeof(struct lancer_cmd_req_write_object)));

spin_unlock_bh(&adapter->mcc_lock);

if (!wait_for_completion_timeout(&adapter->et_cmd_compl,

req->params.op_code = cpu_to_le32(flash_opcode);

req->params.data_buf_size = cpu_to_le32(buf_size);

spin_unlock_bh(&adapter->mcc_lock);

if (!wait_for_completion_timeout(&adapter->et_cmd_compl,

wrb = wrb_from_mccq(adapter);

if (!wrb) {

status = -EBUSY;

}

req = embedded_payload(wrb);

req->loopback_type = loopback_type;

req->loopback_state = enable;

spin_unlock_bh(&adapter->mcc_lock);

return status;

}

req->num_pkts = cpu_to_le32(num_pkts);

req->loopback_type = cpu_to_le32(loopback_type);

spin_unlock_bh(&adapter->mcc_lock);

#define BE_PME_D3COLD_CAP 0x80

/********************** LoopBack test *********************/

struct be_cmd_req_loopback_test {

struct be_cmd_req_hdr hdr;

u32 loopback_type;

/*********************** HSW Config ***********************/

#define PORT_FWD_TYPE_VEPA 0x3

#define PORT_FWD_TYPE_VEB 0x2

#define ENABLE_MAC_SPOOFCHK 0x2

#define DISABLE_MAC_SPOOFCHK 0x3

static u64 be_loopback_test(struct be_adapter *adapter, u8 loopback_type,

u64 *status)

{

*status = be_cmd_loopback_test(adapter, adapter->hba_port_num,

loopback_type, 1500, 2, 0xabc);

return *status;

}

if (is_udp_pkt((*skb))) {

struct udphdr *udp = udp_hdr((*skb));

case DHCP_CLIENT_PORT:

os2bmc = is_dhcp_client_filt_enabled(adapter);

goto done;

static int be_setup_wol(struct be_adapter *adapter, bool enable)

{

struct be_dma_mem cmd;

u8 mac[ETH_ALEN];

eth_zero_addr(mac);

cmd.size = sizeof(struct be_cmd_req_acpi_wol_magic_config);

if (!cmd.va)

return -ENOMEM;

PCICFG_PM_CONTROL_OFFSET,

PCICFG_PM_CONTROL_MASK);

if (status) {

}

} else {

}

return status;

}

{

if (!fhdr) {

dev_err(&adapter->pdev->dev, "Invalid FW UFI file");

}

/* First letter of the build version is used to identify

int status = 0;

u8 hsw_mode;

/* BE and Lancer chips support VEB mode only */

if (BEx_chip(adapter) || lancer_chip(adapter)) {

hsw_mode = PORT_FWD_TYPE_VEB;

NULL);

if (status)

return 0;

}

return ndo_dflt_bridge_getlink(skb, pid, seq, dev,

if (status)

return status;

pci_restore_state(pdev);

status = be_resume(adapter);

return PCI_ERS_RESULT_DISCONNECT;

pci_set_master(pdev);

pci_restore_state(pdev);

/* Check if card is ok and fw is ready */

break;

default:

fep->hwts_rx_en = 1;

config.rx_filter = HWTSTAMP_FILTER_ALL;

break;

#define TX_TIMEOUT (1*HZ)

static int gfar_enet_open(struct net_device *dev);

static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);

static void gfar_reset_task(struct work_struct *work);

static void gfar_timeout(struct net_device *dev);

static int gfar_close(struct net_device *dev);

static int gfar_set_mac_address(struct net_device *dev);

static int gfar_change_mtu(struct net_device *dev, int new_mtu);

static irqreturn_t gfar_error(int irq, void *dev_id);

#endif

int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);

static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);

static void gfar_halt_nodisable(struct gfar_private *priv);

static void gfar_clear_exact_match(struct net_device *dev);

static void gfar_set_mac_for_addr(struct net_device *dev, int num,

bdp->lstatus = cpu_to_be32(lstatus);

}

{

struct gfar_private *priv = netdev_priv(ndev);

struct gfar __iomem *regs = priv->gfargrp[0].regs;

struct gfar_priv_tx_q *tx_queue = NULL;

struct gfar_priv_rx_q *rx_queue = NULL;

struct txbd8 *txbdp;

u32 __iomem *rfbptr;

int i, j;

for (i = 0; i < priv->num_tx_queues; i++) {

tx_queue = priv->tx_queue[i];

rfbptr = &regs->rfbptr0;

for (i = 0; i < priv->num_rx_queues; i++) {

rx_queue = priv->rx_queue[i];

rx_queue->rfbptr = rfbptr;

rfbptr += 2;

}

}

static int gfar_alloc_skb_resources(struct net_device *ndev)

{

void *vaddr;

dma_addr_t addr;

struct gfar_private *priv = netdev_priv(ndev);

struct device *dev = priv->dev;

struct gfar_priv_tx_q *tx_queue = NULL;

rx_queue = priv->rx_queue[i];

rx_queue->rx_bd_base = vaddr;

rx_queue->rx_bd_dma_base = addr;

addr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;

vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;

}

if (!tx_queue->tx_skbuff)

goto cleanup;

}

for (i = 0; i < priv->num_rx_queues; i++) {

rx_queue = priv->rx_queue[i];

goto cleanup;

}

return 0;

}

}

{

/* set this when rx hw offload (TOE) functions are being used */

priv->uses_rxfcb = 0;

if (priv->hwts_rx_en)

priv->uses_rxfcb = 1;

}

static void gfar_mac_rx_config(struct gfar_private *priv)

if (!priv->rx_queue[i])

return -ENOMEM;

priv->rx_queue[i]->qindex = i;

}

return 0;

}

udelay(3);

/* Initialize the max receive frame/buffer lengths */

/* Initialize the Minimum Frame Length Register */

gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);

/* Initialize MACCFG2. */

tempval = MACCFG2_INIT_SETTINGS;

*/

tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;

gfar_write(&regs->maccfg2, tempval);

priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)

dev->needed_headroom = GMAC_FCB_LEN;

/* Initializing some of the rx/tx queue level parameters */

for (i = 0; i < priv->num_tx_queues; i++) {

priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;

return 0;

}

gfar_mac_reset(priv);

static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)

{

int i;

for (i = 0; i < rx_queue->rx_ring_size; i++) {

rxbdp->lstatus = 0;

rxbdp->bufPtr = 0;

rxbdp++;

}

}

/* If there are any tx skbs or rx skbs still around, free them.

for (i = 0; i < priv->num_rx_queues; i++) {

rx_queue = priv->rx_queue[i];

free_skb_rx_queue(rx_queue);

}

struct gfar_private *priv = netdev_priv(dev);

int frame_size = new_mtu + ETH_HLEN;

netif_err(priv, drv, dev, "Invalid MTU setting\n");

return -EINVAL;

}

schedule_work(&priv->reset_task);

}

/* Interrupt Handler for Transmit complete */

static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)

{

netdev_tx_completed_queue(txq, howmany, bytes_sent);

}

{

}

{

}

}

{

struct gfar_extra_stats *estats = &priv->extra_stats;

/* If the packet was truncated, none of the other errors matter */

stats->rx_length_errors++;

atomic64_inc(&estats->rx_trunc);

return;

}

/* Count the errors, if there were any */

stats->rx_length_errors++;

atomic64_inc(&estats->rx_large);

else

atomic64_inc(&estats->rx_short);

}

stats->rx_frame_errors++;

atomic64_inc(&estats->rx_nonoctet);

}

atomic64_inc(&estats->rx_crcerr);

stats->rx_crc_errors++;

}

atomic64_inc(&estats->rx_overrun);

}

}

return IRQ_HANDLED;

}

static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)

{

/* If valid headers were found, and valid sums

}

/* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */

{

struct rxfcb *fcb = NULL;

/* fcb is at the beginning if exists */

/* Remove the FCB from the skb

* Remove the padded bytes, if there are any

*/

/* Get receive timestamp from the skb */

if (priv->hwts_rx_en) {

if (priv->padding)

skb_pull(skb, priv->padding);

gfar_rx_checksum(skb, fcb);

/* Tell the skb what kind of packet this is */

/* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here.

* Even if vlan rx accel is disabled, on some chips

* RXFCB_VLN is pseudo randomly set.

*/

be16_to_cpu(fcb->flags) & RXFCB_VLN)

__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),

be16_to_cpu(fcb->vlctl));

}

/* gfar_clean_rx_ring() -- Processes each frame in the rx ring

*/

int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)

{

/* Get the first full descriptor */

rmb();

}

}

return howmany;

}

if ((tempval1 & MACCFG1_TX_FLOW) && !tx_flow_oldval) {

for (i = 0; i < priv->num_rx_queues; i++) {

rx_queue = priv->rx_queue[i];

}

priv->tx_actual_en = 1;

/* Number of bytes to align the rx bufs to */

#define RXBUF_ALIGNMENT 64

#define PHY_INIT_TIMEOUT 100000

#define DRV_NAME "gfar-enet"

#define DEFAULT_TX_RING_SIZE 256

#define DEFAULT_RX_RING_SIZE 256

#define GFAR_RX_MAX_RING_SIZE 256

#define GFAR_TX_MAX_RING_SIZE 256

#define DEFAULT_RX_LFC_THR 16

#define DEFAULT_LFC_PTVVAL 4

#define TX_RING_MOD_MASK(size) (size-1)

#define RX_RING_MOD_MASK(size) (size-1)

#define DEFAULT_FIFO_TX_THR 0x100

#define DEFAULT_FIFO_TX_STARVE 0x40

};

struct gfar_extra_stats {

atomic64_t rx_large;

atomic64_t rx_short;

atomic64_t rx_nonoctet;

atomic64_t eberr;

atomic64_t tx_babt;

atomic64_t tx_underrun;

atomic64_t tx_timeout;

};

unsigned long rx_dropped;

};

/**

* struct gfar_priv_rx_q - per rx queue structure

* @rx_bd_base: First rx buffer descriptor

* @qindex: index of this queue

* @rx_ring_size: Rx ring size

* @rxcoalescing: enable/disable rx-coalescing

* @rxic: receive interrupt coalescing vlaue

*/

struct gfar_priv_rx_q {

struct rxbd8 *rx_bd_base;

struct rx_q_stats stats;

unsigned char rxcoalescing;

unsigned long rxic;

};

enum gfar_irqinfo_id {

struct device *dev;

struct net_device *ndev;

enum gfar_errata errata;

u16 uses_rxfcb;

u16 padding;

bdp->lstatus = cpu_to_be32(lstatus);

}

irqreturn_t gfar_receive(int irq, void *dev_id);

int startup_gfar(struct net_device *dev);

void stop_gfar(struct net_device *dev);

struct ethtool_drvinfo *drvinfo);

static const char stat_gstrings[][ETH_GSTRING_LEN] = {

"rx-large-frame-errors",

"rx-short-frame-errors",

"rx-non-octet-errors",

"ethernet-bus-error",

"tx-babbling-errors",

"tx-underrun-errors",

"tx-timeout-errors",

"tx-rx-64-frames",

"tx-rx-65-127-frames",

"tx-rx-128-255-frames",

.remove = hip04_remove,

.driver = {

.name = DRV_NAME,

.of_match_table = hip04_mac_match,

},

};

.remove = hip04_mdio_remove,

.driver = {

.name = "hip04-mdio",

.of_match_table = hip04_mdio_match,

},

};

module_param(rx_flush, uint, 0644);

MODULE_PARM_DESC(rx_flush, "Flush receive buffers before use");

struct ibmveth_stat {

char name[ETH_GSTRING_LEN];

int offset;

{ "fw_enabled_ipv4_csum", IBMVETH_STAT_OFF(fw_ipv4_csum_support) },

{ "fw_enabled_ipv6_csum", IBMVETH_STAT_OFF(fw_ipv6_csum_support) },

{ "tx_large_packets", IBMVETH_STAT_OFF(tx_large_packets) },

};

/* simple methods of getting data from the current rxq entry */

return rc1 ? rc1 : rc2;

}

static int ibmveth_set_features(struct net_device *dev,

netdev_features_t features)

{

struct ibmveth_adapter *adapter = netdev_priv(dev);

int rx_csum = !!(features & NETIF_F_RXCSUM);

}

static void ibmveth_get_strings(struct net_device *dev, u32 stringset, u8 *data)

#define page_offset(v) ((unsigned long)(v) & ((1 << 12) - 1))

static int ibmveth_send(struct ibmveth_adapter *adapter,

{

unsigned long correlator;

unsigned int retry_count;

descs[0].desc, descs[1].desc,

descs[2].desc, descs[3].desc,

descs[4].desc, descs[5].desc,

} while ((ret == H_BUSY) && (retry_count--));

if (ret != H_SUCCESS && ret != H_DROPPED) {

int last, i;

int force_bounce = 0;

dma_addr_t dma_addr;

/*

* veth handles a maximum of 6 segments including the header, so

desc_flags = IBMVETH_BUF_VALID;

if (skb->ip_summed == CHECKSUM_PARTIAL) {

unsigned char *buf = skb_transport_header(skb) +

skb->csum_offset;

descs[0].fields.flags_len = desc_flags | skb->len;

descs[0].fields.address = adapter->bounce_buffer_dma;

adapter->tx_send_failed++;

netdev->stats.tx_dropped++;

} else {

descs[i+1].fields.address = dma_addr;

}

}

adapter->tx_send_failed++;

netdev->stats.tx_dropped++;

} else {

struct ibmveth_adapter *adapter;

unsigned char *mac_addr_p;

unsigned int *mcastFilterSize_p;

dev_dbg(&dev->dev, "entering ibmveth_probe for UA 0x%x\n",

dev->unit_address);

SET_NETDEV_DEV(netdev, &dev->dev);

netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM |

NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;

netdev->features |= netdev->hw_features;

memcpy(netdev->dev_addr, mac_addr_p, ETH_ALEN);

#define IbmVethMcastRemoveFilter 0x2UL

#define IbmVethMcastClearFilterTable 0x3UL

#define IBMVETH_ILLAN_PADDED_PKT_CSUM 0x0000000000002000UL

#define IBMVETH_ILLAN_TRUNK_PRI_MASK 0x0000000000000F00UL

#define IBMVETH_ILLAN_IPV6_TCP_CSUM 0x0000000000000004UL

static inline long h_send_logical_lan(unsigned long unit_address,

unsigned long desc1, unsigned long desc2, unsigned long desc3,

unsigned long desc4, unsigned long desc5, unsigned long desc6,

{

long rc;

unsigned long retbuf[PLPAR_HCALL9_BUFSIZE];

*corellator_out = retbuf[0];

struct ibmveth_rx_q rx_queue;

int pool_config;

int rx_csum;

void *bounce_buffer;

dma_addr_t bounce_buffer_dma;

u64 fw_ipv6_csum_support;

u64 fw_ipv4_csum_support;

/* adapter specific stats */

u64 replenish_task_cycles;

u64 replenish_no_mem;

#endif

#define IBMVETH_BUF_VALID 0x80000000

#define IBMVETH_BUF_TOGGLE 0x40000000

#define IBMVETH_BUF_NO_CSUM 0x02000000

#define IBMVETH_BUF_CSUM_GOOD 0x01000000

#define IBMVETH_BUF_LEN_MASK 0x00FFFFFF

*/

#define I40E_FW_API_VERSION_MAJOR 0x0001

struct i40e_aq_desc {

__le16 flags;

i40e_aqc_opc_list_func_capabilities = 0x000A,

i40e_aqc_opc_list_dev_capabilities = 0x000B,

/* LAA */

i40e_aqc_opc_mac_address_read = 0x0107,

i40e_aqc_opc_mac_address_write = 0x0108,

/* Tunnel commands */

i40e_aqc_opc_add_udp_tunnel = 0x0B00,

i40e_aqc_opc_del_udp_tunnel = 0x0B01,

/* Async Events */

i40e_aqc_opc_event_lan_overflow = 0x1001,

i40e_aqc_opc_oem_ocbb_initialize = 0xFE03,

/* debug commands */

i40e_aqc_opc_debug_read_reg = 0xFF03,

i40e_aqc_opc_debug_write_reg = 0xFF04,

i40e_aqc_opc_debug_modify_reg = 0xFF07,

#define I40E_AQC_SAN_ADDR_VALID 0x20

#define I40E_AQC_PORT_ADDR_VALID 0x40

#define I40E_AQC_WOL_ADDR_VALID 0x80

u8 reserved[6];

__le32 addr_high;

__le32 addr_low;

#define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000

#define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000

#define I40E_AQC_WRITE_TYPE_PORT 0x8000

__le16 mac_sah;

__le32 mac_sal;

u8 reserved[8];

__le16 seid;

#define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF

__le16 vlan_tag;

#define I40E_AQC_SET_VSI_VLAN_VALID 0x8000

u8 reserved[8];

};

#define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)

#define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8

#define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)

struct i40e_aqc_get_cee_dcb_cfg_v1_resp {

u8 reserved1;

u8 oper_num_tc;

#define I40E_DEV_FUNC_CAP_MSIX_VF 0x44

#define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45

#define I40E_DEV_FUNC_CAP_IEEE_1588 0x46

#define I40E_DEV_FUNC_CAP_CEM 0xF2

#define I40E_DEV_FUNC_CAP_IWARP 0x51

#define I40E_DEV_FUNC_CAP_LED 0x61

u32 valid_functions, num_functions;

u32 number, logical_id, phys_id;

struct i40e_hw_capabilities *p;

u32 i = 0;

u16 id;

number = le32_to_cpu(cap->number);

logical_id = le32_to_cpu(cap->logical_id);

phys_id = le32_to_cpu(cap->phys_id);

switch (id) {

case I40E_DEV_FUNC_CAP_SWITCH_MODE:

case I40E_DEV_FUNC_CAP_MSIX_VF:

p->num_msix_vectors_vf = number;

break;

break;

case I40E_DEV_FUNC_CAP_CEM:

if (number == 1)

/* Software override ensuring FCoE is disabled if npar or mfp

* mode because it is not supported in these modes.

*/

p->fcoe = false;

/* count the enabled ports (aka the "not disabled" ports) */

I40E_PF_STAT("fdir_flush_cnt", fd_flush_cnt),

I40E_PF_STAT("fdir_atr_match", stats.fd_atr_match),

I40E_PF_STAT("fdir_atr_tunnel_match", stats.fd_atr_tunnel_match),

I40E_PF_STAT("fdir_sb_match", stats.fd_sb_match),

/* LPI stats */

I40E_PF_STAT("tx_lpi_status", stats.tx_lpi_status),

info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);

info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |

return 0;

}

* @hw: pointer to our HW structure

* @hmc_info: pointer to the HMC configuration information structure

* @pd_index: which page descriptor index to manipulate

*

* This function:

* 1. Initializes the pd entry

**/

i40e_status i40e_add_pd_table_entry(struct i40e_hw *hw,

struct i40e_hmc_info *hmc_info,

{

i40e_status ret_code = 0;

struct i40e_hmc_pd_table *pd_table;

struct i40e_hmc_pd_entry *pd_entry;

struct i40e_dma_mem mem;

u32 sd_idx, rel_pd_idx;

u64 *pd_addr;

u64 page_desc;

pd_table = &hmc_info->sd_table.sd_entry[sd_idx].u.pd_table;

pd_entry = &pd_table->pd_entry[rel_pd_idx];

if (!pd_entry->valid) {

pd_entry->bp.sd_pd_index = pd_index;

pd_entry->bp.entry_type = I40E_SD_TYPE_PAGED;

/* Set page address and valid bit */

pd_addr = (u64 *)pd_table->pd_page_addr.va;

pd_addr += rel_pd_idx;

I40E_INVALIDATE_PF_HMC_PD(hw, sd_idx, idx);

/* free memory here */

if (ret_code)

goto exit;

if (!pd_table->ref_cnt)

struct i40e_hmc_pd_entry {

struct i40e_hmc_bp bp;

u32 sd_index;

bool valid;

};

i40e_status i40e_add_pd_table_entry(struct i40e_hw *hw,

struct i40e_hmc_info *hmc_info,

i40e_status i40e_remove_pd_bp(struct i40e_hw *hw,

struct i40e_hmc_info *hmc_info,

u32 idx);

/* update the pd table entry */

ret_code = i40e_add_pd_table_entry(hw,

info->hmc_info,

if (ret_code) {

pd_error = true;

break;

#define DRV_VERSION_MAJOR 1

#define DRV_VERSION_MINOR 3

#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \

__stringify(DRV_VERSION_MINOR) "." \

__stringify(DRV_VERSION_BUILD) DRV_KERN

pf->stat_offsets_loaded,

&osd->rx_lpi_count, &nsd->rx_lpi_count);

pf->stat_offsets_loaded = true;

}

}

/* MFP mode enabled */

pf->flags |= I40E_FLAG_MFP_ENABLED;

dev_info(&pf->pdev->dev, "MFP mode Enabled\n");

if (i40e_get_npar_bw_setting(pf))

return err;

}

/**

* i40e_ndo_bridge_setlink - Set the hardware bridge mode

* @dev: the netdev being configured

* bridge mode enabled.

**/

static int i40e_ndo_bridge_setlink(struct net_device *dev,

{

struct i40e_netdev_priv *np = netdev_priv(dev);

struct i40e_vsi *vsi = np->vsi;

* Return the mode in which the hardware bridge is operating in

* i.e VEB or VEPA.

**/

static int i40e_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,

struct net_device *dev,

u32 filter_mask, int nlflags)

{

struct i40e_netdev_priv *np = netdev_priv(dev);

struct i40e_vsi *vsi = np->vsi;

return ndo_dflt_bridge_getlink(skb, pid, seq, dev, veb->bridge_mode,

nlflags, 0, 0, filter_mask, NULL);

}

static const struct net_device_ops i40e_netdev_ops = {

.ndo_open = i40e_open,

#endif

.ndo_get_phys_port_id = i40e_get_phys_port_id,

.ndo_fdb_add = i40e_ndo_fdb_add,

.ndo_bridge_getlink = i40e_ndo_bridge_getlink,

.ndo_bridge_setlink = i40e_ndo_bridge_setlink,

};

/**

err = i40e_init_shared_code(hw);

if (err) {

goto err_pf_reset;

}

netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev,

tx_ring->queue_index)))

writel(i, tx_ring->tail);

return;

bool dcb;

bool fcoe;

bool iscsi; /* Indicates iSCSI enabled */

bool mgmt_cem;

bool ieee_1588;

bool iwarp;

u64 fd_atr_match;

u64 fd_sb_match;

u64 fd_atr_tunnel_match;

/* EEE LPI */

u32 tx_lpi_status;

u32 rx_lpi_status;

**/

static inline void i40e_vc_disable_vf(struct i40e_pf *pf, struct i40e_vf *vf)

{

}

/**

if (vf->port_vlan_id)

i40e_vsi_add_pvid(vsi, vf->port_vlan_id);

f = i40e_add_filter(vsi, vf->default_lan_addr.addr,

if (!f)

dev_info(&pf->pdev->dev,

"Could not allocate VF MAC addr\n");

true, false);

if (!f)

dev_info(&pf->pdev->dev,

i40e_alloc_vf_res(vf);

i40e_enable_vf_mappings(vf);

set_bit(I40E_VF_STAT_ACTIVE, &vf->vf_states);

/* tell the VF the reset is done */

wr32(hw, I40E_VFGEN_RSTAT1(vf->vf_id), I40E_VFR_VFACTIVE);

}

/* delete the temporary mac address */

true, false);

/* Delete all the filters for this VSI - we're going to kill it

goto error_pvid;

}

if (vsi->info.pvid == 0 && i40e_is_vsi_in_vlan(vsi)) {

dev_err(&pf->pdev->dev,

"VF %d has already configured VLAN filters and the administrator is requesting a port VLAN override.\nPlease unload and reload the VF driver for this change to take effect.\n",

*/

#define I40E_FW_API_VERSION_MAJOR 0x0001

#define I40E_FW_API_VERSION_A0_MINOR 0x0000

struct i40e_aq_desc {

i40e_aqc_opc_list_func_capabilities = 0x000A,

i40e_aqc_opc_list_dev_capabilities = 0x000B,

/* LAA */

i40e_aqc_opc_mac_address_read = 0x0107,

i40e_aqc_opc_mac_address_write = 0x0108,

/* Tunnel commands */

i40e_aqc_opc_add_udp_tunnel = 0x0B00,

i40e_aqc_opc_del_udp_tunnel = 0x0B01,

/* Async Events */

i40e_aqc_opc_event_lan_overflow = 0x1001,

i40e_aqc_opc_oem_ocbb_initialize = 0xFE03,

/* debug commands */

i40e_aqc_opc_debug_read_reg = 0xFF03,

i40e_aqc_opc_debug_write_reg = 0xFF04,

i40e_aqc_opc_debug_modify_reg = 0xFF07,

#define I40E_AQC_SAN_ADDR_VALID 0x20

#define I40E_AQC_PORT_ADDR_VALID 0x40

#define I40E_AQC_WOL_ADDR_VALID 0x80

u8 reserved[6];

__le32 addr_high;

__le32 addr_low;

#define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000

#define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000

#define I40E_AQC_WRITE_TYPE_PORT 0x8000

__le16 mac_sah;

__le32 mac_sal;

u8 reserved[8];

__le16 seid;

#define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF

__le16 vlan_tag;

#define I40E_AQC_SET_VSI_VLAN_VALID 0x8000

u8 reserved[8];

};

struct i40e_hmc_pd_entry {

struct i40e_hmc_bp bp;

u32 sd_index;

bool valid;

};

i40e_status i40e_add_pd_table_entry(struct i40e_hw *hw,

struct i40e_hmc_info *hmc_info,