diff options
Diffstat (limited to 'drivers/thermal/mediatek')
| -rw-r--r-- | drivers/thermal/mediatek/auxadc_thermal.c | 190 | ||||
| -rw-r--r-- | drivers/thermal/mediatek/lvts_thermal.c | 110 |
2 files changed, 214 insertions, 86 deletions
diff --git a/drivers/thermal/mediatek/auxadc_thermal.c b/drivers/thermal/mediatek/auxadc_thermal.c index ab730f9552d0..0b5528804bbd 100644 --- a/drivers/thermal/mediatek/auxadc_thermal.c +++ b/drivers/thermal/mediatek/auxadc_thermal.c @@ -31,6 +31,7 @@ #define AUXADC_CON2_V 0x010 #define AUXADC_DATA(channel) (0x14 + (channel) * 4) +#define APMIXED_SYS_TS_CON0 0x600 #define APMIXED_SYS_TS_CON1 0x604 /* Thermal Controller Registers */ @@ -115,6 +116,10 @@ /* The calibration coefficient of sensor */ #define MT8173_CALIBRATION 165 +/* Valid temperatures range */ +#define MT8173_TEMP_MIN -20000 +#define MT8173_TEMP_MAX 150000 + /* * Layout of the fuses providing the calibration data * These macros could be used for MT8183, MT8173, MT2701, and MT2712. @@ -281,6 +286,17 @@ enum mtk_thermal_version { /* The calibration coefficient of sensor */ #define MT7986_CALIBRATION 165 +/* MT8365 */ +#define MT8365_TEMP_AUXADC_CHANNEL 11 +#define MT8365_CALIBRATION 164 +#define MT8365_NUM_CONTROLLER 1 +#define MT8365_NUM_BANKS 1 +#define MT8365_NUM_SENSORS 3 +#define MT8365_NUM_SENSORS_PER_ZONE 3 +#define MT8365_TS1 0 +#define MT8365_TS2 1 +#define MT8365_TS3 2 + struct mtk_thermal; struct thermal_bank_cfg { @@ -307,6 +323,9 @@ struct mtk_thermal_data { bool need_switch_bank; struct thermal_bank_cfg bank_data[MAX_NUM_ZONES]; enum mtk_thermal_version version; + u32 apmixed_buffer_ctl_reg; + u32 apmixed_buffer_ctl_mask; + u32 apmixed_buffer_ctl_set; }; struct mtk_thermal { @@ -432,6 +451,24 @@ static const int mt7986_mux_values[MT7986_NUM_SENSORS] = { 0, }; static const int mt7986_vts_index[MT7986_NUM_SENSORS] = { VTS1 }; static const int mt7986_tc_offset[MT7986_NUM_CONTROLLER] = { 0x0, }; +/* MT8365 thermal sensor data */ +static const int mt8365_bank_data[MT8365_NUM_SENSORS] = { + MT8365_TS1, MT8365_TS2, MT8365_TS3 +}; + +static const int mt8365_msr[MT8365_NUM_SENSORS_PER_ZONE] = { + TEMP_MSR0, TEMP_MSR1, TEMP_MSR2 +}; + +static const int mt8365_adcpnp[MT8365_NUM_SENSORS_PER_ZONE] = { + TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2 +}; + +static const int mt8365_mux_values[MT8365_NUM_SENSORS] = { 0, 1, 2 }; +static const int mt8365_tc_offset[MT8365_NUM_CONTROLLER] = { 0 }; + +static const int mt8365_vts_index[MT8365_NUM_SENSORS] = { VTS1, VTS2, VTS3 }; + /* * The MT8173 thermal controller has four banks. Each bank can read up to * four temperature sensors simultaneously. The MT8173 has a total of 5 @@ -507,6 +544,40 @@ static const struct mtk_thermal_data mt2701_thermal_data = { }; /* + * The MT8365 thermal controller has one bank, which can read up to + * four temperature sensors simultaneously. The MT8365 has a total of 3 + * temperature sensors. + * + * The thermal core only gets the maximum temperature of this one bank, + * so the bank concept wouldn't be necessary here. However, the SVS (Smart + * Voltage Scaling) unit makes its decisions based on the same bank + * data. + */ +static const struct mtk_thermal_data mt8365_thermal_data = { + .auxadc_channel = MT8365_TEMP_AUXADC_CHANNEL, + .num_banks = MT8365_NUM_BANKS, + .num_sensors = MT8365_NUM_SENSORS, + .vts_index = mt8365_vts_index, + .cali_val = MT8365_CALIBRATION, + .num_controller = MT8365_NUM_CONTROLLER, + .controller_offset = mt8365_tc_offset, + .need_switch_bank = false, + .bank_data = { + { + .num_sensors = MT8365_NUM_SENSORS, + .sensors = mt8365_bank_data + }, + }, + .msr = mt8365_msr, + .adcpnp = mt8365_adcpnp, + .sensor_mux_values = mt8365_mux_values, + .version = MTK_THERMAL_V1, + .apmixed_buffer_ctl_reg = APMIXED_SYS_TS_CON0, + .apmixed_buffer_ctl_mask = (u32) ~GENMASK(29, 28), + .apmixed_buffer_ctl_set = 0, +}; + +/* * The MT2712 thermal controller has one bank, which can read up to * four temperature sensors simultaneously. The MT2712 has a total of 4 * temperature sensors. @@ -560,6 +631,9 @@ static const struct mtk_thermal_data mt7622_thermal_data = { .adcpnp = mt7622_adcpnp, .sensor_mux_values = mt7622_mux_values, .version = MTK_THERMAL_V2, + .apmixed_buffer_ctl_reg = APMIXED_SYS_TS_CON1, + .apmixed_buffer_ctl_mask = GENMASK(31, 6) | BIT(3), + .apmixed_buffer_ctl_set = BIT(0), }; /* @@ -619,6 +693,11 @@ static const struct mtk_thermal_data mt7986_thermal_data = { .version = MTK_THERMAL_V3, }; +static bool mtk_thermal_temp_is_valid(int temp) +{ + return (temp >= MT8173_TEMP_MIN) && (temp <= MT8173_TEMP_MAX); +} + /** * raw_to_mcelsius_v1 - convert a raw ADC value to mcelsius * @mt: The thermal controller @@ -745,14 +824,17 @@ static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) temp = mt->raw_to_mcelsius( mt, conf->bank_data[bank->id].sensors[i], raw); - /* - * The first read of a sensor often contains very high bogus - * temperature value. Filter these out so that the system does - * not immediately shut down. + * Depending on the filt/sen intervals and ADC polling time, + * we may need up to 60 milliseconds after initialization: this + * will result in the first reading containing an out of range + * temperature value. + * Validate the reading to both address the aforementioned issue + * and to eventually avoid bogus readings during runtime in the + * event that the AUXADC gets unstable due to high EMI, etc. */ - if (temp > 200000) - temp = 0; + if (!mtk_thermal_temp_is_valid(temp)) + temp = THERMAL_TEMP_INVALID; if (temp > max) max = temp; @@ -763,7 +845,7 @@ static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) static int mtk_read_temp(struct thermal_zone_device *tz, int *temperature) { - struct mtk_thermal *mt = tz->devdata; + struct mtk_thermal *mt = thermal_zone_device_priv(tz); int i; int tempmax = INT_MIN; @@ -897,14 +979,12 @@ static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num, static u64 of_get_phys_base(struct device_node *np) { - u64 size64; - const __be32 *regaddr_p; + struct resource res; - regaddr_p = of_get_address(np, 0, &size64, NULL); - if (!regaddr_p) + if (of_address_to_resource(np, 0, &res)) return OF_BAD_ADDR; - return of_translate_address(np, regaddr_p); + return res.start; } static int mtk_thermal_extract_efuse_v1(struct mtk_thermal *mt, u32 *buf) @@ -1074,19 +1154,27 @@ static const struct of_device_id mtk_thermal_of_match[] = { { .compatible = "mediatek,mt8183-thermal", .data = (void *)&mt8183_thermal_data, + }, + { + .compatible = "mediatek,mt8365-thermal", + .data = (void *)&mt8365_thermal_data, }, { }, }; MODULE_DEVICE_TABLE(of, mtk_thermal_of_match); -static void mtk_thermal_turn_on_buffer(void __iomem *apmixed_base) +static void mtk_thermal_turn_on_buffer(struct mtk_thermal *mt, + void __iomem *apmixed_base) { - int tmp; + u32 tmp; + + if (!mt->conf->apmixed_buffer_ctl_reg) + return; - tmp = readl(apmixed_base + APMIXED_SYS_TS_CON1); - tmp &= ~(0x37); - tmp |= 0x1; - writel(tmp, apmixed_base + APMIXED_SYS_TS_CON1); + tmp = readl(apmixed_base + mt->conf->apmixed_buffer_ctl_reg); + tmp &= mt->conf->apmixed_buffer_ctl_mask; + tmp |= mt->conf->apmixed_buffer_ctl_set; + writel(tmp, apmixed_base + mt->conf->apmixed_buffer_ctl_reg); udelay(200); } @@ -1116,14 +1204,6 @@ static int mtk_thermal_probe(struct platform_device *pdev) mt->conf = of_device_get_match_data(&pdev->dev); - mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); - if (IS_ERR(mt->clk_peri_therm)) - return PTR_ERR(mt->clk_peri_therm); - - mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc"); - if (IS_ERR(mt->clk_auxadc)) - return PTR_ERR(mt->clk_auxadc); - mt->thermal_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); if (IS_ERR(mt->thermal_base)) return PTR_ERR(mt->thermal_base); @@ -1142,7 +1222,12 @@ static int mtk_thermal_probe(struct platform_device *pdev) return -ENODEV; } - auxadc_base = of_iomap(auxadc, 0); + auxadc_base = devm_of_iomap(&pdev->dev, auxadc, 0, NULL); + if (IS_ERR(auxadc_base)) { + of_node_put(auxadc); + return PTR_ERR(auxadc_base); + } + auxadc_phys_base = of_get_phys_base(auxadc); of_node_put(auxadc); @@ -1158,7 +1243,12 @@ static int mtk_thermal_probe(struct platform_device *pdev) return -ENODEV; } - apmixed_base = of_iomap(apmixedsys, 0); + apmixed_base = devm_of_iomap(&pdev->dev, apmixedsys, 0, NULL); + if (IS_ERR(apmixed_base)) { + of_node_put(apmixedsys); + return PTR_ERR(apmixed_base); + } + apmixed_phys_base = of_get_phys_base(apmixedsys); of_node_put(apmixedsys); @@ -1172,22 +1262,24 @@ static int mtk_thermal_probe(struct platform_device *pdev) if (ret) return ret; - ret = clk_prepare_enable(mt->clk_auxadc); - if (ret) { + mt->clk_auxadc = devm_clk_get_enabled(&pdev->dev, "auxadc"); + if (IS_ERR(mt->clk_auxadc)) { + ret = PTR_ERR(mt->clk_auxadc); dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); return ret; } - ret = clk_prepare_enable(mt->clk_peri_therm); - if (ret) { + mt->clk_peri_therm = devm_clk_get_enabled(&pdev->dev, "therm"); + if (IS_ERR(mt->clk_peri_therm)) { + ret = PTR_ERR(mt->clk_peri_therm); dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); - goto err_disable_clk_auxadc; + return ret; } - if (mt->conf->version != MTK_THERMAL_V1) { - mtk_thermal_turn_on_buffer(apmixed_base); + mtk_thermal_turn_on_buffer(mt, apmixed_base); + + if (mt->conf->version != MTK_THERMAL_V2) mtk_thermal_release_periodic_ts(mt, auxadc_base); - } if (mt->conf->version == MTK_THERMAL_V1) mt->raw_to_mcelsius = raw_to_mcelsius_v1; @@ -1205,38 +1297,18 @@ static int mtk_thermal_probe(struct platform_device *pdev) tzdev = devm_thermal_of_zone_register(&pdev->dev, 0, mt, &mtk_thermal_ops); - if (IS_ERR(tzdev)) { - ret = PTR_ERR(tzdev); - goto err_disable_clk_peri_therm; - } + if (IS_ERR(tzdev)) + return PTR_ERR(tzdev); - ret = devm_thermal_add_hwmon_sysfs(tzdev); + ret = devm_thermal_add_hwmon_sysfs(&pdev->dev, tzdev); if (ret) dev_warn(&pdev->dev, "error in thermal_add_hwmon_sysfs"); return 0; - -err_disable_clk_peri_therm: - clk_disable_unprepare(mt->clk_peri_therm); -err_disable_clk_auxadc: - clk_disable_unprepare(mt->clk_auxadc); - - return ret; -} - -static int mtk_thermal_remove(struct platform_device *pdev) -{ - struct mtk_thermal *mt = platform_get_drvdata(pdev); - - clk_disable_unprepare(mt->clk_peri_therm); - clk_disable_unprepare(mt->clk_auxadc); - - return 0; } static struct platform_driver mtk_thermal_driver = { .probe = mtk_thermal_probe, - .remove = mtk_thermal_remove, .driver = { .name = "mtk-thermal", .of_match_table = mtk_thermal_of_match, diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/mediatek/lvts_thermal.c index 84ba65a27acf..d0a3f95b7884 100644 --- a/drivers/thermal/mediatek/lvts_thermal.c +++ b/drivers/thermal/mediatek/lvts_thermal.c @@ -66,7 +66,7 @@ #define LVTS_MONINT_CONF 0x9FBF7BDE #define LVTS_INT_SENSOR0 0x0009001F -#define LVTS_INT_SENSOR1 0X000881F0 +#define LVTS_INT_SENSOR1 0x001203E0 #define LVTS_INT_SENSOR2 0x00247C00 #define LVTS_INT_SENSOR3 0x1FC00000 @@ -252,7 +252,7 @@ static u32 lvts_temp_to_raw(int temperature) static int lvts_get_temp(struct thermal_zone_device *tz, int *temp) { - struct lvts_sensor *lvts_sensor = tz->devdata; + struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz); void __iomem *msr = lvts_sensor->msr; u32 value; @@ -290,7 +290,7 @@ static int lvts_get_temp(struct thermal_zone_device *tz, int *temp) static int lvts_set_trips(struct thermal_zone_device *tz, int low, int high) { - struct lvts_sensor *lvts_sensor = tz->devdata; + struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz); void __iomem *base = lvts_sensor->base; u32 raw_low = lvts_temp_to_raw(low); u32 raw_high = lvts_temp_to_raw(high); @@ -305,7 +305,8 @@ static int lvts_set_trips(struct thermal_zone_device *tz, int low, int high) * 14-0 : Raw temperature for threshold */ if (low != -INT_MAX) { - dev_dbg(&tz->device, "Setting low limit temperature interrupt: %d\n", low); + pr_debug("%s: Setting low limit temperature interrupt: %d\n", + thermal_zone_device_type(tz), low); writel(raw_low, LVTS_H2NTHRE(base)); } @@ -318,7 +319,8 @@ static int lvts_set_trips(struct thermal_zone_device *tz, int low, int high) * * 14-0 : Raw temperature for threshold */ - dev_dbg(&tz->device, "Setting high limit temperature interrupt: %d\n", high); + pr_debug("%s: Setting high limit temperature interrupt: %d\n", + thermal_zone_device_type(tz), high); writel(raw_high, LVTS_HTHRE(base)); return 0; @@ -393,8 +395,8 @@ static irqreturn_t lvts_ctrl_irq_handler(struct lvts_ctrl *lvts_ctrl) * => 0x1FC00000 * sensor 2 interrupt: 0000 0000 0010 0100 0111 1100 0000 0000 * => 0x00247C00 - * sensor 1 interrupt: 0000 0000 0001 0001 0000 0011 1110 0000 - * => 0X000881F0 + * sensor 1 interrupt: 0000 0000 0001 0010 0000 0011 1110 0000 + * => 0X001203E0 * sensor 0 interrupt: 0000 0000 0000 1001 0000 0000 0001 1111 * => 0x0009001F */ @@ -528,29 +530,33 @@ static int lvts_sensor_init(struct device *dev, struct lvts_ctrl *lvts_ctrl, * The efuse blob values follows the sensor enumeration per thermal * controller. The decoding of the stream is as follow: * - * <--?-> <----big0 ???---> <-sensor0-> <-0-> - * ------------------------------------------ - * index in the stream: : | 0x0 | 0x1 | 0x2 | 0x3 | 0x4 | 0x5 | 0x6 | - * ------------------------------------------ + * stream index map for MCU Domain : * - * <--sensor1--><-0-> <----big1 ???---> <-sen - * ------------------------------------------ - * | 0x7 | 0x8 | 0x9 | 0xA | 0xB | OxC | OxD | - * ------------------------------------------ + * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1-----> + * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 * - * sor0-> <-0-> <-sensor1-> <-0-> .......... - * ------------------------------------------ - * | 0x7 | 0x8 | 0x9 | 0xA | 0xB | OxC | OxD | - * ------------------------------------------ + * <-----mcu-tc#1-----> <-----sensor#2-----> <-----sensor#3-----> + * 0x0A | 0x0B | 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12 * - * And so on ... + * <-----mcu-tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7-----> + * 0x13 | 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21 + * + * stream index map for AP Domain : + * + * <-----ap--tc#0-----> <-----sensor#0-----> <-----sensor#1-----> + * 0x22 | 0x23 | 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A + * + * <-----ap--tc#1-----> <-----sensor#2-----> <-----sensor#3-----> + * 0x2B | 0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33 + * + * <-----ap--tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> + * 0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B | 0x3C | 0x3D | 0x3E | 0x3F + * + * <-----ap--tc#3-----> <-----sensor#7-----> <-----sensor#8-----> + * 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47 | 0x48 * * The data description gives the offset of the calibration data in * this bytes stream for each sensor. - * - * Each thermal controller can handle up to 4 sensors max, we don't - * care if there are less as the array of calibration is sized to 4 - * anyway. The unused sensor slot will be zeroed. */ static int lvts_calibration_init(struct device *dev, struct lvts_ctrl *lvts_ctrl, const struct lvts_ctrl_data *lvts_ctrl_data, @@ -1163,7 +1169,7 @@ static int lvts_remove(struct platform_device *pdev) return 0; } -static const struct lvts_ctrl_data mt8195_lvts_data_ctrl[] = { +static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = { { .cal_offset = { 0x04, 0x07 }, .lvts_sensor = { @@ -1198,13 +1204,63 @@ static const struct lvts_ctrl_data mt8195_lvts_data_ctrl[] = { } }; +static const struct lvts_ctrl_data mt8195_lvts_ap_data_ctrl[] = { + { + .cal_offset = { 0x25, 0x28 }, + .lvts_sensor = { + { .dt_id = MT8195_AP_VPU0 }, + { .dt_id = MT8195_AP_VPU1 } + }, + .num_lvts_sensor = 2, + .offset = 0x0, + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, + }, + { + .cal_offset = { 0x2e, 0x31 }, + .lvts_sensor = { + { .dt_id = MT8195_AP_GPU0 }, + { .dt_id = MT8195_AP_GPU1 } + }, + .num_lvts_sensor = 2, + .offset = 0x100, + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, + }, + { + .cal_offset = { 0x37, 0x3a, 0x3d }, + .lvts_sensor = { + { .dt_id = MT8195_AP_VDEC }, + { .dt_id = MT8195_AP_IMG }, + { .dt_id = MT8195_AP_INFRA }, + }, + .num_lvts_sensor = 3, + .offset = 0x200, + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, + }, + { + .cal_offset = { 0x43, 0x46 }, + .lvts_sensor = { + { .dt_id = MT8195_AP_CAM0 }, + { .dt_id = MT8195_AP_CAM1 } + }, + .num_lvts_sensor = 2, + .offset = 0x300, + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, + } +}; + static const struct lvts_data mt8195_lvts_mcu_data = { - .lvts_ctrl = mt8195_lvts_data_ctrl, - .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_data_ctrl), + .lvts_ctrl = mt8195_lvts_mcu_data_ctrl, + .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl), +}; + +static const struct lvts_data mt8195_lvts_ap_data = { + .lvts_ctrl = mt8195_lvts_ap_data_ctrl, + .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_ap_data_ctrl), }; static const struct of_device_id lvts_of_match[] = { { .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data }, + { .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data }, {}, }; MODULE_DEVICE_TABLE(of, lvts_of_match); |