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-rw-r--r--drivers/reset/Kconfig11
-rw-r--r--drivers/reset/Makefile2
-rw-r--r--drivers/reset/reset-ath79.c4
-rw-r--r--drivers/reset/reset-axs10x.c4
-rw-r--r--drivers/reset/reset-brcmstb-rescal.c4
-rw-r--r--drivers/reset/reset-hsdk.c7
-rw-r--r--drivers/reset/reset-lpc18xx.c4
-rw-r--r--drivers/reset/reset-ma35d1.c235
-rw-r--r--drivers/reset/reset-meson-audio-arb.c7
-rw-r--r--drivers/reset/reset-meson.c4
-rw-r--r--drivers/reset/reset-oxnas.c114
-rw-r--r--drivers/reset/starfive/Kconfig3
-rw-r--r--drivers/reset/sti/Kconfig4
-rw-r--r--drivers/reset/sti/Makefile4
-rw-r--r--drivers/reset/sti/reset-syscfg.c18
15 files changed, 260 insertions, 165 deletions
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 6aa8f243b30c..ccd59ddd7610 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -143,8 +143,12 @@ config RESET_NPCM
This enables the reset controller driver for Nuvoton NPCM
BMC SoCs.
-config RESET_OXNAS
- bool
+config RESET_NUVOTON_MA35D1
+ bool "Nuvoton MA35D1 Reset Driver"
+ depends on ARCH_MA35 || COMPILE_TEST
+ default ARCH_MA35
+ help
+ This enables the reset controller driver for Nuvoton MA35D1 SoC.
config RESET_PISTACHIO
bool "Pistachio Reset Driver"
@@ -154,7 +158,8 @@ config RESET_PISTACHIO
config RESET_POLARFIRE_SOC
bool "Microchip PolarFire SoC (MPFS) Reset Driver"
- depends on AUXILIARY_BUS && MCHP_CLK_MPFS
+ depends on MCHP_CLK_MPFS
+ select AUXILIARY_BUS
default MCHP_CLK_MPFS
help
This driver supports peripheral reset for the Microchip PolarFire SoC
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 7fec5af6c964..8270da8a4baa 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -21,7 +21,7 @@ obj-$(CONFIG_RESET_MCHP_SPARX5) += reset-microchip-sparx5.o
obj-$(CONFIG_RESET_MESON) += reset-meson.o
obj-$(CONFIG_RESET_MESON_AUDIO_ARB) += reset-meson-audio-arb.o
obj-$(CONFIG_RESET_NPCM) += reset-npcm.o
-obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
+obj-$(CONFIG_RESET_NUVOTON_MA35D1) += reset-ma35d1.o
obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
obj-$(CONFIG_RESET_POLARFIRE_SOC) += reset-mpfs.o
obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o
diff --git a/drivers/reset/reset-ath79.c b/drivers/reset/reset-ath79.c
index e48d8fcb3133..a8b8f5ea77ec 100644
--- a/drivers/reset/reset-ath79.c
+++ b/drivers/reset/reset-ath79.c
@@ -86,7 +86,6 @@ static int ath79_reset_restart_handler(struct notifier_block *nb,
static int ath79_reset_probe(struct platform_device *pdev)
{
struct ath79_reset *ath79_reset;
- struct resource *res;
int err;
ath79_reset = devm_kzalloc(&pdev->dev,
@@ -96,8 +95,7 @@ static int ath79_reset_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, ath79_reset);
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- ath79_reset->base = devm_ioremap_resource(&pdev->dev, res);
+ ath79_reset->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(ath79_reset->base))
return PTR_ERR(ath79_reset->base);
diff --git a/drivers/reset/reset-axs10x.c b/drivers/reset/reset-axs10x.c
index a854ef41364d..115f69e0db33 100644
--- a/drivers/reset/reset-axs10x.c
+++ b/drivers/reset/reset-axs10x.c
@@ -44,14 +44,12 @@ static const struct reset_control_ops axs10x_reset_ops = {
static int axs10x_reset_probe(struct platform_device *pdev)
{
struct axs10x_rst *rst;
- struct resource *mem;
rst = devm_kzalloc(&pdev->dev, sizeof(*rst), GFP_KERNEL);
if (!rst)
return -ENOMEM;
- mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- rst->regs_rst = devm_ioremap_resource(&pdev->dev, mem);
+ rst->regs_rst = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(rst->regs_rst))
return PTR_ERR(rst->regs_rst);
diff --git a/drivers/reset/reset-brcmstb-rescal.c b/drivers/reset/reset-brcmstb-rescal.c
index 433fa0c40e47..823317772bac 100644
--- a/drivers/reset/reset-brcmstb-rescal.c
+++ b/drivers/reset/reset-brcmstb-rescal.c
@@ -66,14 +66,12 @@ static const struct reset_control_ops brcm_rescal_reset_ops = {
static int brcm_rescal_reset_probe(struct platform_device *pdev)
{
struct brcm_rescal_reset *data;
- struct resource *res;
data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- data->base = devm_ioremap_resource(&pdev->dev, res);
+ data->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(data->base))
return PTR_ERR(data->base);
diff --git a/drivers/reset/reset-hsdk.c b/drivers/reset/reset-hsdk.c
index 4c7b8647b49c..98460e08752c 100644
--- a/drivers/reset/reset-hsdk.c
+++ b/drivers/reset/reset-hsdk.c
@@ -92,19 +92,16 @@ static const struct reset_control_ops hsdk_reset_ops = {
static int hsdk_reset_probe(struct platform_device *pdev)
{
struct hsdk_rst *rst;
- struct resource *mem;
rst = devm_kzalloc(&pdev->dev, sizeof(*rst), GFP_KERNEL);
if (!rst)
return -ENOMEM;
- mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- rst->regs_ctl = devm_ioremap_resource(&pdev->dev, mem);
+ rst->regs_ctl = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(rst->regs_ctl))
return PTR_ERR(rst->regs_ctl);
- mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
- rst->regs_rst = devm_ioremap_resource(&pdev->dev, mem);
+ rst->regs_rst = devm_platform_ioremap_resource(pdev, 1);
if (IS_ERR(rst->regs_rst))
return PTR_ERR(rst->regs_rst);
diff --git a/drivers/reset/reset-lpc18xx.c b/drivers/reset/reset-lpc18xx.c
index 35d8dd4cccfc..36ec95518905 100644
--- a/drivers/reset/reset-lpc18xx.c
+++ b/drivers/reset/reset-lpc18xx.c
@@ -139,7 +139,6 @@ static const struct reset_control_ops lpc18xx_rgu_ops = {
static int lpc18xx_rgu_probe(struct platform_device *pdev)
{
struct lpc18xx_rgu_data *rc;
- struct resource *res;
u32 fcclk, firc;
int ret;
@@ -147,8 +146,7 @@ static int lpc18xx_rgu_probe(struct platform_device *pdev)
if (!rc)
return -ENOMEM;
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- rc->base = devm_ioremap_resource(&pdev->dev, res);
+ rc->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(rc->base))
return PTR_ERR(rc->base);
diff --git a/drivers/reset/reset-ma35d1.c b/drivers/reset/reset-ma35d1.c
new file mode 100644
index 000000000000..54e53863c98a
--- /dev/null
+++ b/drivers/reset/reset-ma35d1.c
@@ -0,0 +1,235 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2023 Nuvoton Technology Corp.
+ * Author: Chi-Fang Li <cfli0@nuvoton.com>
+ */
+
+#include <linux/bits.h>
+#include <linux/container_of.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/reboot.h>
+#include <linux/reset-controller.h>
+#include <linux/spinlock.h>
+#include <dt-bindings/reset/nuvoton,ma35d1-reset.h>
+
+struct ma35d1_reset_data {
+ struct reset_controller_dev rcdev;
+ struct notifier_block restart_handler;
+ void __iomem *base;
+ /* protect registers against concurrent read-modify-write */
+ spinlock_t lock;
+};
+
+static const struct {
+ u32 reg_ofs;
+ u32 bit;
+} ma35d1_reset_map[] = {
+ [MA35D1_RESET_CHIP] = {0x20, 0},
+ [MA35D1_RESET_CA35CR0] = {0x20, 1},
+ [MA35D1_RESET_CA35CR1] = {0x20, 2},
+ [MA35D1_RESET_CM4] = {0x20, 3},
+ [MA35D1_RESET_PDMA0] = {0x20, 4},
+ [MA35D1_RESET_PDMA1] = {0x20, 5},
+ [MA35D1_RESET_PDMA2] = {0x20, 6},
+ [MA35D1_RESET_PDMA3] = {0x20, 7},
+ [MA35D1_RESET_DISP] = {0x20, 9},
+ [MA35D1_RESET_VCAP0] = {0x20, 10},
+ [MA35D1_RESET_VCAP1] = {0x20, 11},
+ [MA35D1_RESET_GFX] = {0x20, 12},
+ [MA35D1_RESET_VDEC] = {0x20, 13},
+ [MA35D1_RESET_WHC0] = {0x20, 14},
+ [MA35D1_RESET_WHC1] = {0x20, 15},
+ [MA35D1_RESET_GMAC0] = {0x20, 16},
+ [MA35D1_RESET_GMAC1] = {0x20, 17},
+ [MA35D1_RESET_HWSEM] = {0x20, 18},
+ [MA35D1_RESET_EBI] = {0x20, 19},
+ [MA35D1_RESET_HSUSBH0] = {0x20, 20},
+ [MA35D1_RESET_HSUSBH1] = {0x20, 21},
+ [MA35D1_RESET_HSUSBD] = {0x20, 22},
+ [MA35D1_RESET_USBHL] = {0x20, 23},
+ [MA35D1_RESET_SDH0] = {0x20, 24},
+ [MA35D1_RESET_SDH1] = {0x20, 25},
+ [MA35D1_RESET_NAND] = {0x20, 26},
+ [MA35D1_RESET_GPIO] = {0x20, 27},
+ [MA35D1_RESET_MCTLP] = {0x20, 28},
+ [MA35D1_RESET_MCTLC] = {0x20, 29},
+ [MA35D1_RESET_DDRPUB] = {0x20, 30},
+ [MA35D1_RESET_TMR0] = {0x24, 2},
+ [MA35D1_RESET_TMR1] = {0x24, 3},
+ [MA35D1_RESET_TMR2] = {0x24, 4},
+ [MA35D1_RESET_TMR3] = {0x24, 5},
+ [MA35D1_RESET_I2C0] = {0x24, 8},
+ [MA35D1_RESET_I2C1] = {0x24, 9},
+ [MA35D1_RESET_I2C2] = {0x24, 10},
+ [MA35D1_RESET_I2C3] = {0x24, 11},
+ [MA35D1_RESET_QSPI0] = {0x24, 12},
+ [MA35D1_RESET_SPI0] = {0x24, 13},
+ [MA35D1_RESET_SPI1] = {0x24, 14},
+ [MA35D1_RESET_SPI2] = {0x24, 15},
+ [MA35D1_RESET_UART0] = {0x24, 16},
+ [MA35D1_RESET_UART1] = {0x24, 17},
+ [MA35D1_RESET_UART2] = {0x24, 18},
+ [MA35D1_RESET_UART3] = {0x24, 19},
+ [MA35D1_RESET_UART4] = {0x24, 20},
+ [MA35D1_RESET_UART5] = {0x24, 21},
+ [MA35D1_RESET_UART6] = {0x24, 22},
+ [MA35D1_RESET_UART7] = {0x24, 23},
+ [MA35D1_RESET_CANFD0] = {0x24, 24},
+ [MA35D1_RESET_CANFD1] = {0x24, 25},
+ [MA35D1_RESET_EADC0] = {0x24, 28},
+ [MA35D1_RESET_I2S0] = {0x24, 29},
+ [MA35D1_RESET_SC0] = {0x28, 0},
+ [MA35D1_RESET_SC1] = {0x28, 1},
+ [MA35D1_RESET_QSPI1] = {0x28, 4},
+ [MA35D1_RESET_SPI3] = {0x28, 6},
+ [MA35D1_RESET_EPWM0] = {0x28, 16},
+ [MA35D1_RESET_EPWM1] = {0x28, 17},
+ [MA35D1_RESET_QEI0] = {0x28, 22},
+ [MA35D1_RESET_QEI1] = {0x28, 23},
+ [MA35D1_RESET_ECAP0] = {0x28, 26},
+ [MA35D1_RESET_ECAP1] = {0x28, 27},
+ [MA35D1_RESET_CANFD2] = {0x28, 28},
+ [MA35D1_RESET_ADC0] = {0x28, 31},
+ [MA35D1_RESET_TMR4] = {0x2C, 0},
+ [MA35D1_RESET_TMR5] = {0x2C, 1},
+ [MA35D1_RESET_TMR6] = {0x2C, 2},
+ [MA35D1_RESET_TMR7] = {0x2C, 3},
+ [MA35D1_RESET_TMR8] = {0x2C, 4},
+ [MA35D1_RESET_TMR9] = {0x2C, 5},
+ [MA35D1_RESET_TMR10] = {0x2C, 6},
+ [MA35D1_RESET_TMR11] = {0x2C, 7},
+ [MA35D1_RESET_UART8] = {0x2C, 8},
+ [MA35D1_RESET_UART9] = {0x2C, 9},
+ [MA35D1_RESET_UART10] = {0x2C, 10},
+ [MA35D1_RESET_UART11] = {0x2C, 11},
+ [MA35D1_RESET_UART12] = {0x2C, 12},
+ [MA35D1_RESET_UART13] = {0x2C, 13},
+ [MA35D1_RESET_UART14] = {0x2C, 14},
+ [MA35D1_RESET_UART15] = {0x2C, 15},
+ [MA35D1_RESET_UART16] = {0x2C, 16},
+ [MA35D1_RESET_I2S1] = {0x2C, 17},
+ [MA35D1_RESET_I2C4] = {0x2C, 18},
+ [MA35D1_RESET_I2C5] = {0x2C, 19},
+ [MA35D1_RESET_EPWM2] = {0x2C, 20},
+ [MA35D1_RESET_ECAP2] = {0x2C, 21},
+ [MA35D1_RESET_QEI2] = {0x2C, 22},
+ [MA35D1_RESET_CANFD3] = {0x2C, 23},
+ [MA35D1_RESET_KPI] = {0x2C, 24},
+ [MA35D1_RESET_GIC] = {0x2C, 28},
+ [MA35D1_RESET_SSMCC] = {0x2C, 30},
+ [MA35D1_RESET_SSPCC] = {0x2C, 31}
+};
+
+static int ma35d1_restart_handler(struct notifier_block *this, unsigned long mode, void *cmd)
+{
+ struct ma35d1_reset_data *data =
+ container_of(this, struct ma35d1_reset_data, restart_handler);
+ u32 id = MA35D1_RESET_CHIP;
+
+ writel_relaxed(BIT(ma35d1_reset_map[id].bit),
+ data->base + ma35d1_reset_map[id].reg_ofs);
+ return 0;
+}
+
+static int ma35d1_reset_update(struct reset_controller_dev *rcdev, unsigned long id, bool assert)
+{
+ struct ma35d1_reset_data *data = container_of(rcdev, struct ma35d1_reset_data, rcdev);
+ unsigned long flags;
+ u32 reg;
+
+ if (WARN_ON_ONCE(id >= ARRAY_SIZE(ma35d1_reset_map)))
+ return -EINVAL;
+
+ spin_lock_irqsave(&data->lock, flags);
+ reg = readl_relaxed(data->base + ma35d1_reset_map[id].reg_ofs);
+ if (assert)
+ reg |= BIT(ma35d1_reset_map[id].bit);
+ else
+ reg &= ~(BIT(ma35d1_reset_map[id].bit));
+ writel_relaxed(reg, data->base + ma35d1_reset_map[id].reg_ofs);
+ spin_unlock_irqrestore(&data->lock, flags);
+
+ return 0;
+}
+
+static int ma35d1_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
+{
+ return ma35d1_reset_update(rcdev, id, true);
+}
+
+static int ma35d1_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
+{
+ return ma35d1_reset_update(rcdev, id, false);
+}
+
+static int ma35d1_reset_status(struct reset_controller_dev *rcdev, unsigned long id)
+{
+ struct ma35d1_reset_data *data = container_of(rcdev, struct ma35d1_reset_data, rcdev);
+ u32 reg;
+
+ if (WARN_ON_ONCE(id >= ARRAY_SIZE(ma35d1_reset_map)))
+ return -EINVAL;
+
+ reg = readl_relaxed(data->base + ma35d1_reset_map[id].reg_ofs);
+ return !!(reg & BIT(ma35d1_reset_map[id].bit));
+}
+
+static const struct reset_control_ops ma35d1_reset_ops = {
+ .assert = ma35d1_reset_assert,
+ .deassert = ma35d1_reset_deassert,
+ .status = ma35d1_reset_status,
+};
+
+static const struct of_device_id ma35d1_reset_dt_ids[] = {
+ { .compatible = "nuvoton,ma35d1-reset" },
+ { },
+};
+
+static int ma35d1_reset_probe(struct platform_device *pdev)
+{
+ struct ma35d1_reset_data *reset_data;
+ struct device *dev = &pdev->dev;
+ int err;
+
+ if (!pdev->dev.of_node) {
+ dev_err(&pdev->dev, "Device tree node not found\n");
+ return -EINVAL;
+ }
+
+ reset_data = devm_kzalloc(dev, sizeof(*reset_data), GFP_KERNEL);
+ if (!reset_data)
+ return -ENOMEM;
+
+ reset_data->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(reset_data->base))
+ return PTR_ERR(reset_data->base);
+
+ reset_data->rcdev.owner = THIS_MODULE;
+ reset_data->rcdev.nr_resets = MA35D1_RESET_COUNT;
+ reset_data->rcdev.ops = &ma35d1_reset_ops;
+ reset_data->rcdev.of_node = dev->of_node;
+ reset_data->restart_handler.notifier_call = ma35d1_restart_handler;
+ reset_data->restart_handler.priority = 192;
+ spin_lock_init(&reset_data->lock);
+
+ err = register_restart_handler(&reset_data->restart_handler);
+ if (err)
+ dev_warn(&pdev->dev, "failed to register restart handler\n");
+
+ return devm_reset_controller_register(dev, &reset_data->rcdev);
+}
+
+static struct platform_driver ma35d1_reset_driver = {
+ .probe = ma35d1_reset_probe,
+ .driver = {
+ .name = "ma35d1-reset",
+ .of_match_table = ma35d1_reset_dt_ids,
+ },
+};
+
+builtin_platform_driver(ma35d1_reset_driver);
diff --git a/drivers/reset/reset-meson-audio-arb.c b/drivers/reset/reset-meson-audio-arb.c
index 1dc06e08a8da..6a3f6a6a3bbf 100644
--- a/drivers/reset/reset-meson-audio-arb.c
+++ b/drivers/reset/reset-meson-audio-arb.c
@@ -151,11 +151,8 @@ static int meson_audio_arb_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, arb);
arb->clk = devm_clk_get(dev, NULL);
- if (IS_ERR(arb->clk)) {
- if (PTR_ERR(arb->clk) != -EPROBE_DEFER)
- dev_err(dev, "failed to get clock\n");
- return PTR_ERR(arb->clk);
- }
+ if (IS_ERR(arb->clk))
+ return dev_err_probe(dev, PTR_ERR(arb->clk), "failed to get clock\n");
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
arb->regs = devm_ioremap_resource(dev, res);
diff --git a/drivers/reset/reset-meson.c b/drivers/reset/reset-meson.c
index 26dc54778615..13878ca2779d 100644
--- a/drivers/reset/reset-meson.c
+++ b/drivers/reset/reset-meson.c
@@ -116,14 +116,12 @@ MODULE_DEVICE_TABLE(of, meson_reset_dt_ids);
static int meson_reset_probe(struct platform_device *pdev)
{
struct meson_reset *data;
- struct resource *res;
data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- data->reg_base = devm_ioremap_resource(&pdev->dev, res);
+ data->reg_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(data->reg_base))
return PTR_ERR(data->reg_base);
diff --git a/drivers/reset/reset-oxnas.c b/drivers/reset/reset-oxnas.c
deleted file mode 100644
index 8209f922dc16..000000000000
--- a/drivers/reset/reset-oxnas.c
+++ /dev/null
@@ -1,114 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Oxford Semiconductor Reset Controller driver
- *
- * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
- * Copyright (C) 2014 Ma Haijun <mahaijuns@gmail.com>
- * Copyright (C) 2009 Oxford Semiconductor Ltd
- */
-#include <linux/err.h>
-#include <linux/init.h>
-#include <linux/of.h>
-#include <linux/platform_device.h>
-#include <linux/reset-controller.h>
-#include <linux/slab.h>
-#include <linux/delay.h>
-#include <linux/types.h>
-#include <linux/regmap.h>
-#include <linux/mfd/syscon.h>
-
-/* Regmap offsets */
-#define RST_SET_REGOFFSET 0x34
-#define RST_CLR_REGOFFSET 0x38
-
-struct oxnas_reset {
- struct regmap *regmap;
- struct reset_controller_dev rcdev;
-};
-
-static int oxnas_reset_reset(struct reset_controller_dev *rcdev,
- unsigned long id)
-{
- struct oxnas_reset *data =
- container_of(rcdev, struct oxnas_reset, rcdev);
-
- regmap_write(data->regmap, RST_SET_REGOFFSET, BIT(id));
- msleep(50);
- regmap_write(data->regmap, RST_CLR_REGOFFSET, BIT(id));
-
- return 0;
-}
-
-static int oxnas_reset_assert(struct reset_controller_dev *rcdev,
- unsigned long id)
-{
- struct oxnas_reset *data =
- container_of(rcdev, struct oxnas_reset, rcdev);
-
- regmap_write(data->regmap, RST_SET_REGOFFSET, BIT(id));
-
- return 0;
-}
-
-static int oxnas_reset_deassert(struct reset_controller_dev *rcdev,
- unsigned long id)
-{
- struct oxnas_reset *data =
- container_of(rcdev, struct oxnas_reset, rcdev);
-
- regmap_write(data->regmap, RST_CLR_REGOFFSET, BIT(id));
-
- return 0;
-}
-
-static const struct reset_control_ops oxnas_reset_ops = {
- .reset = oxnas_reset_reset,
- .assert = oxnas_reset_assert,
- .deassert = oxnas_reset_deassert,
-};
-
-static const struct of_device_id oxnas_reset_dt_ids[] = {
- { .compatible = "oxsemi,ox810se-reset", },
- { .compatible = "oxsemi,ox820-reset", },
- { /* sentinel */ },
-};
-
-static int oxnas_reset_probe(struct platform_device *pdev)
-{
- struct oxnas_reset *data;
- struct device *parent;
-
- parent = pdev->dev.parent;
- if (!parent) {
- dev_err(&pdev->dev, "no parent\n");
- return -ENODEV;
- }
-
- data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
- if (!data)
- return -ENOMEM;
-
- data->regmap = syscon_node_to_regmap(parent->of_node);
- if (IS_ERR(data->regmap)) {
- dev_err(&pdev->dev, "failed to get parent regmap\n");
- return PTR_ERR(data->regmap);
- }
-
- platform_set_drvdata(pdev, data);
-
- data->rcdev.owner = THIS_MODULE;
- data->rcdev.nr_resets = 32;
- data->rcdev.ops = &oxnas_reset_ops;
- data->rcdev.of_node = pdev->dev.of_node;
-
- return devm_reset_controller_register(&pdev->dev, &data->rcdev);
-}
-
-static struct platform_driver oxnas_reset_driver = {
- .probe = oxnas_reset_probe,
- .driver = {
- .name = "oxnas-reset",
- .of_match_table = oxnas_reset_dt_ids,
- },
-};
-builtin_platform_driver(oxnas_reset_driver);
diff --git a/drivers/reset/starfive/Kconfig b/drivers/reset/starfive/Kconfig
index 1fa706a2c3dc..d832339f61bc 100644
--- a/drivers/reset/starfive/Kconfig
+++ b/drivers/reset/starfive/Kconfig
@@ -13,7 +13,8 @@ config RESET_STARFIVE_JH7100
config RESET_STARFIVE_JH7110
bool "StarFive JH7110 Reset Driver"
- depends on AUXILIARY_BUS && CLK_STARFIVE_JH7110_SYS
+ depends on CLK_STARFIVE_JH7110_SYS
+ select AUXILIARY_BUS
select RESET_STARFIVE_JH71X0
default ARCH_STARFIVE
help
diff --git a/drivers/reset/sti/Kconfig b/drivers/reset/sti/Kconfig
index 9455e1c7a5aa..a2622e146b8b 100644
--- a/drivers/reset/sti/Kconfig
+++ b/drivers/reset/sti/Kconfig
@@ -1,11 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only
if ARCH_STI
-config STI_RESET_SYSCFG
- bool
-
config STIH407_RESET
bool
- select STI_RESET_SYSCFG
endif
diff --git a/drivers/reset/sti/Makefile b/drivers/reset/sti/Makefile
index 3eb30f7e8e3d..5e833496cee3 100644
--- a/drivers/reset/sti/Makefile
+++ b/drivers/reset/sti/Makefile
@@ -1,4 +1,2 @@
# SPDX-License-Identifier: GPL-2.0-only
-obj-$(CONFIG_STI_RESET_SYSCFG) += reset-syscfg.o
-
-obj-$(CONFIG_STIH407_RESET) += reset-stih407.o
+obj-$(CONFIG_STIH407_RESET) += reset-stih407.o reset-syscfg.o
diff --git a/drivers/reset/sti/reset-syscfg.c b/drivers/reset/sti/reset-syscfg.c
index b4b46e0f207e..c1ba04f6f155 100644
--- a/drivers/reset/sti/reset-syscfg.c
+++ b/drivers/reset/sti/reset-syscfg.c
@@ -64,22 +64,12 @@ static int syscfg_reset_program_hw(struct reset_controller_dev *rcdev,
return err;
if (ch->ack) {
- unsigned long timeout = jiffies + msecs_to_jiffies(1000);
u32 ack_val;
- while (true) {
- err = regmap_field_read(ch->ack, &ack_val);
- if (err)
- return err;
-
- if (ack_val == ctrl_val)
- break;
-
- if (time_after(jiffies, timeout))
- return -ETIME;
-
- cpu_relax();
- }
+ err = regmap_field_read_poll_timeout(ch->ack, ack_val, (ack_val == ctrl_val),
+ 100, USEC_PER_SEC);
+ if (err)
+ return err;
}
return 0;
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