diff options
Diffstat (limited to 'drivers/net/wireless/ralink/rt2x00/rt2800lib.c')
| -rw-r--r-- | drivers/net/wireless/ralink/rt2x00/rt2800lib.c | 2556 |
1 files changed, 2126 insertions, 430 deletions
diff --git a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c index 4fb79e05078f..0b75def39c6c 100644 --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c @@ -59,6 +59,9 @@ rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg)) #define WAIT_FOR_RFCSR(__dev, __reg) \ rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg)) +#define WAIT_FOR_RFCSR_MT7620(__dev, __reg) \ + rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY_MT7620, \ + (__reg)) #define WAIT_FOR_RF(__dev, __reg) \ rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg)) #define WAIT_FOR_MCU(__dev, __reg) \ @@ -107,10 +110,10 @@ static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev, mutex_unlock(&rt2x00dev->csr_mutex); } -static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev, - const unsigned int word, u8 *value) +static u8 rt2800_bbp_read(struct rt2x00_dev *rt2x00dev, const unsigned int word) { u32 reg; + u8 value; mutex_lock(&rt2x00dev->csr_mutex); @@ -134,9 +137,11 @@ static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev, WAIT_FOR_BBP(rt2x00dev, ®); } - *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE); + value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE); mutex_unlock(&rt2x00dev->csr_mutex); + + return value; } static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev, @@ -150,23 +155,61 @@ static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev, * Wait until the RFCSR becomes available, afterwards we * can safely write the new data into the register. */ - if (WAIT_FOR_RFCSR(rt2x00dev, ®)) { - reg = 0; - rt2x00_set_field32(®, RF_CSR_CFG_DATA, value); - rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); - rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 1); - rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); + switch (rt2x00dev->chip.rt) { + case RT6352: + if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®)) { + reg = 0; + rt2x00_set_field32(®, RF_CSR_CFG_DATA_MT7620, value); + rt2x00_set_field32(®, RF_CSR_CFG_REGNUM_MT7620, + word); + rt2x00_set_field32(®, RF_CSR_CFG_WRITE_MT7620, 1); + rt2x00_set_field32(®, RF_CSR_CFG_BUSY_MT7620, 1); + + rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); + } + break; - rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); + default: + if (WAIT_FOR_RFCSR(rt2x00dev, ®)) { + reg = 0; + rt2x00_set_field32(®, RF_CSR_CFG_DATA, value); + rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); + rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 1); + rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); + + rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); + } + break; } mutex_unlock(&rt2x00dev->csr_mutex); } -static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev, - const unsigned int word, u8 *value) +static void rt2800_rfcsr_write_bank(struct rt2x00_dev *rt2x00dev, const u8 bank, + const unsigned int reg, const u8 value) +{ + rt2800_rfcsr_write(rt2x00dev, (reg | (bank << 6)), value); +} + +static void rt2800_rfcsr_write_chanreg(struct rt2x00_dev *rt2x00dev, + const unsigned int reg, const u8 value) +{ + rt2800_rfcsr_write_bank(rt2x00dev, 4, reg, value); + rt2800_rfcsr_write_bank(rt2x00dev, 6, reg, value); +} + +static void rt2800_rfcsr_write_dccal(struct rt2x00_dev *rt2x00dev, + const unsigned int reg, const u8 value) +{ + rt2800_rfcsr_write_bank(rt2x00dev, 5, reg, value); + rt2800_rfcsr_write_bank(rt2x00dev, 7, reg, value); +} + +static u8 rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev, + const unsigned int word) { u32 reg; + u8 value; mutex_lock(&rt2x00dev->csr_mutex); @@ -178,20 +221,48 @@ static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev, * doesn't become available in time, reg will be 0xffffffff * which means we return 0xff to the caller. */ - if (WAIT_FOR_RFCSR(rt2x00dev, ®)) { - reg = 0; - rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); - rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 0); - rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); + switch (rt2x00dev->chip.rt) { + case RT6352: + if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®)) { + reg = 0; + rt2x00_set_field32(®, RF_CSR_CFG_REGNUM_MT7620, + word); + rt2x00_set_field32(®, RF_CSR_CFG_WRITE_MT7620, 0); + rt2x00_set_field32(®, RF_CSR_CFG_BUSY_MT7620, 1); - rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); + rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); - WAIT_FOR_RFCSR(rt2x00dev, ®); - } + WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®); + } + + value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA_MT7620); + break; + + default: + if (WAIT_FOR_RFCSR(rt2x00dev, ®)) { + reg = 0; + rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); + rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 0); + rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); + + rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); - *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA); + WAIT_FOR_RFCSR(rt2x00dev, ®); + } + + value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA); + break; + } mutex_unlock(&rt2x00dev->csr_mutex); + + return value; +} + +static u8 rt2800_rfcsr_read_bank(struct rt2x00_dev *rt2x00dev, const u8 bank, + const unsigned int reg) +{ + return rt2800_rfcsr_read(rt2x00dev, (reg | (bank << 6))); } static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev, @@ -250,6 +321,7 @@ static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = { [EEPROM_TSSI_BOUND_BG5] = 0x003b, [EEPROM_TXPOWER_A1] = 0x003c, [EEPROM_TXPOWER_A2] = 0x0053, + [EEPROM_TXPOWER_INIT] = 0x0068, [EEPROM_TSSI_BOUND_A1] = 0x006a, [EEPROM_TSSI_BOUND_A2] = 0x006b, [EEPROM_TSSI_BOUND_A3] = 0x006c, @@ -338,13 +410,13 @@ static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev, return rt2x00_eeprom_addr(rt2x00dev, index); } -static void rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev, - const enum rt2800_eeprom_word word, u16 *data) +static u16 rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev, + const enum rt2800_eeprom_word word) { unsigned int index; index = rt2800_eeprom_word_index(rt2x00dev, word); - rt2x00_eeprom_read(rt2x00dev, index, data); + return rt2x00_eeprom_read(rt2x00dev, index); } static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev, @@ -356,15 +428,14 @@ static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev, rt2x00_eeprom_write(rt2x00dev, index, data); } -static void rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev, - const enum rt2800_eeprom_word array, - unsigned int offset, - u16 *data) +static u16 rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev, + const enum rt2800_eeprom_word array, + unsigned int offset) { unsigned int index; index = rt2800_eeprom_word_index(rt2x00dev, array); - rt2x00_eeprom_read(rt2x00dev, index + offset, data); + return rt2x00_eeprom_read(rt2x00dev, index + offset); } static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev) @@ -372,10 +443,7 @@ static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev) u32 reg; int i, count; - rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, ®); - if (rt2x00_get_field32(reg, WLAN_EN)) - return 0; - + reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); rt2x00_set_field32(®, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff); rt2x00_set_field32(®, FRC_WL_ANT_SET, 1); rt2x00_set_field32(®, WLAN_CLK_EN, 0); @@ -390,7 +458,7 @@ static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev) * Check PLL_LD & XTAL_RDY. */ for (i = 0; i < REGISTER_BUSY_COUNT; i++) { - rt2800_register_read(rt2x00dev, CMB_CTRL, ®); + reg = rt2800_register_read(rt2x00dev, CMB_CTRL); if (rt2x00_get_field32(reg, PLL_LD) && rt2x00_get_field32(reg, XTAL_RDY)) break; @@ -413,7 +481,7 @@ static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev) count = 0; } - rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, ®); + reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 0); rt2x00_set_field32(®, WLAN_CLK_EN, 1); rt2x00_set_field32(®, WLAN_RESET, 1); @@ -468,7 +536,7 @@ int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev) u32 reg; for (i = 0; i < REGISTER_BUSY_COUNT; i++) { - rt2800_register_read(rt2x00dev, MAC_CSR0, ®); + reg = rt2800_register_read(rt2x00dev, MAC_CSR0); if (reg && reg != ~0) return 0; msleep(1); @@ -489,7 +557,7 @@ int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev) * before timing out. */ for (i = 0; i < REGISTER_BUSY_COUNT; i++) { - rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); + reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) && !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY)) return 0; @@ -506,7 +574,7 @@ void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev) { u32 reg; - rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); + reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); @@ -527,6 +595,7 @@ void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev, break; case RT5592: + case RT6352: *txwi_size = TXWI_DESC_SIZE_5WORDS; *rxwi_size = RXWI_DESC_SIZE_6WORDS; break; @@ -655,7 +724,7 @@ int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev, rt2x00_rt(rt2x00dev, RT3572) || rt2x00_rt(rt2x00dev, RT5390) || rt2x00_rt(rt2x00dev, RT5392)) { - rt2800_register_read(rt2x00dev, AUX_CTRL, ®); + reg = rt2800_register_read(rt2x00dev, AUX_CTRL); rt2x00_set_field32(®, AUX_CTRL_FORCE_PCIE_CLK, 1); rt2x00_set_field32(®, AUX_CTRL_WAKE_PCIE_EN, 1); rt2800_register_write(rt2x00dev, AUX_CTRL, reg); @@ -674,7 +743,7 @@ int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev, * Wait for device to stabilize. */ for (i = 0; i < REGISTER_BUSY_COUNT; i++) { - rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, ®); + reg = rt2800_register_read(rt2x00dev, PBF_SYS_CTRL); if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY)) break; msleep(1); @@ -716,7 +785,7 @@ void rt2800_write_tx_data(struct queue_entry *entry, /* * Initialize TX Info descriptor */ - rt2x00_desc_read(txwi, 0, &word); + word = rt2x00_desc_read(txwi, 0); rt2x00_set_field32(&word, TXWI_W0_FRAG, test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags)); rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, @@ -738,7 +807,7 @@ void rt2800_write_tx_data(struct queue_entry *entry, rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode); rt2x00_desc_write(txwi, 0, word); - rt2x00_desc_read(txwi, 1, &word); + word = rt2x00_desc_read(txwi, 1); rt2x00_set_field32(&word, TXWI_W1_ACK, test_bit(ENTRY_TXD_ACK, &txdesc->flags)); rt2x00_set_field32(&word, TXWI_W1_NSEQ, @@ -778,16 +847,16 @@ static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2) u8 offset2; if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) { - rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom); + eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG); offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0); offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1); - rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom); + eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2); offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2); } else { - rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom); + eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A); offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0); offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1); - rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom); + eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2); offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2); } @@ -816,18 +885,18 @@ void rt2800_process_rxwi(struct queue_entry *entry, __le32 *rxwi = (__le32 *) entry->skb->data; u32 word; - rt2x00_desc_read(rxwi, 0, &word); + word = rt2x00_desc_read(rxwi, 0); rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF); rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT); - rt2x00_desc_read(rxwi, 1, &word); + word = rt2x00_desc_read(rxwi, 1); if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI)) - rxdesc->flags |= RX_FLAG_SHORT_GI; + rxdesc->enc_flags |= RX_ENC_FLAG_SHORT_GI; if (rt2x00_get_field32(word, RXWI_W1_BW)) - rxdesc->flags |= RX_FLAG_40MHZ; + rxdesc->bw = RATE_INFO_BW_40; /* * Detect RX rate, always use MCS as signal type. @@ -842,7 +911,7 @@ void rt2800_process_rxwi(struct queue_entry *entry, if (rxdesc->rate_mode == RATE_MODE_CCK) rxdesc->signal &= ~0x8; - rt2x00_desc_read(rxwi, 2, &word); + word = rt2x00_desc_read(rxwi, 2); /* * Convert descriptor AGC value to RSSI value. @@ -855,26 +924,63 @@ void rt2800_process_rxwi(struct queue_entry *entry, } EXPORT_SYMBOL_GPL(rt2800_process_rxwi); -void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi) +static void rt2800_rate_from_status(struct skb_frame_desc *skbdesc, + u32 status, enum nl80211_band band) +{ + u8 flags = 0; + u8 idx = rt2x00_get_field32(status, TX_STA_FIFO_MCS); + + switch (rt2x00_get_field32(status, TX_STA_FIFO_PHYMODE)) { + case RATE_MODE_HT_GREENFIELD: + flags |= IEEE80211_TX_RC_GREEN_FIELD; + /* fall through */ + case RATE_MODE_HT_MIX: + flags |= IEEE80211_TX_RC_MCS; + break; + case RATE_MODE_OFDM: + if (band == NL80211_BAND_2GHZ) + idx += 4; + break; + case RATE_MODE_CCK: + if (idx >= 8) + idx -= 8; + break; + } + + if (rt2x00_get_field32(status, TX_STA_FIFO_BW)) + flags |= IEEE80211_TX_RC_40_MHZ_WIDTH; + + if (rt2x00_get_field32(status, TX_STA_FIFO_SGI)) + flags |= IEEE80211_TX_RC_SHORT_GI; + + skbdesc->tx_rate_idx = idx; + skbdesc->tx_rate_flags = flags; +} + +void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi, + bool match) { struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; + struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); struct txdone_entry_desc txdesc; u32 word; u16 mcs, real_mcs; - int aggr, ampdu; + int aggr, ampdu, wcid, ack_req; /* * Obtain the status about this packet. */ txdesc.flags = 0; - rt2x00_desc_read(txwi, 0, &word); + word = rt2x00_desc_read(txwi, 0); mcs = rt2x00_get_field32(word, TXWI_W0_MCS); ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU); real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS); aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE); + wcid = rt2x00_get_field32(status, TX_STA_FIFO_WCID); + ack_req = rt2x00_get_field32(status, TX_STA_FIFO_TX_ACK_REQUIRED); /* * If a frame was meant to be sent as a single non-aggregated MPDU @@ -891,15 +997,22 @@ void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi) * Hence, replace the requested rate with the real tx rate to not * confuse the rate control algortihm by providing clearly wrong * data. - */ - if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) { - skbdesc->tx_rate_idx = real_mcs; + * + * FIXME: if we do not find matching entry, we tell that frame was + * posted without any retries. We need to find a way to fix that + * and provide retry count. + */ + if (unlikely((aggr == 1 && ampdu == 0 && real_mcs != mcs)) || !match) { + rt2800_rate_from_status(skbdesc, status, rt2x00dev->curr_band); mcs = real_mcs; } if (aggr == 1 || ampdu == 1) __set_bit(TXDONE_AMPDU, &txdesc.flags); + if (!ack_req) + __set_bit(TXDONE_NO_ACK_REQ, &txdesc.flags); + /* * Ralink has a retry mechanism using a global fallback * table. We setup this fallback table to try the immediate @@ -931,7 +1044,18 @@ void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi) if (txdesc.retry) __set_bit(TXDONE_FALLBACK, &txdesc.flags); - rt2x00lib_txdone(entry, &txdesc); + if (!match) { + /* RCU assures non-null sta will not be freed by mac80211. */ + rcu_read_lock(); + if (likely(wcid >= WCID_START && wcid <= WCID_END)) + skbdesc->sta = drv_data->wcid_to_sta[wcid - WCID_START]; + else + skbdesc->sta = NULL; + rt2x00lib_txdone_nomatch(entry, &txdesc); + rcu_read_unlock(); + } else { + rt2x00lib_txdone(entry, &txdesc); + } } EXPORT_SYMBOL_GPL(rt2800_txdone_entry); @@ -967,15 +1091,13 @@ static void rt2800_update_beacons_setup(struct rt2x00_dev *rt2x00dev) bcn_num++; } - WARN_ON_ONCE(bcn_num != rt2x00dev->intf_beaconing); - rt2800_register_write(rt2x00dev, BCN_OFFSET0, (u32) reg); rt2800_register_write(rt2x00dev, BCN_OFFSET1, (u32) (reg >> 32)); /* * H/W sends up to MAC_BSSID_DW1_BSS_BCN_NUM + 1 consecutive beacons. */ - rt2800_register_read(rt2x00dev, MAC_BSSID_DW1, &bssid_dw1); + bssid_dw1 = rt2800_register_read(rt2x00dev, MAC_BSSID_DW1); rt2x00_set_field32(&bssid_dw1, MAC_BSSID_DW1_BSS_BCN_NUM, bcn_num > 0 ? bcn_num - 1 : 0); rt2800_register_write(rt2x00dev, MAC_BSSID_DW1, bssid_dw1); @@ -994,7 +1116,7 @@ void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc) * Disable beaconing while we are reloading the beacon data, * otherwise we might be sending out invalid data. */ - rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); + reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); orig_reg = reg; rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); @@ -1019,7 +1141,7 @@ void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc) /* * Dump beacon to userspace through debugfs. */ - rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb); + rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry); /* * Write entire beacon with TXWI and padding to register. @@ -1084,7 +1206,7 @@ void rt2800_clear_beacon(struct queue_entry *entry) * Disable beaconing while we are reloading the beacon data, * otherwise we might be sending out invalid data. */ - rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &orig_reg); + orig_reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); reg = orig_reg; rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); @@ -1157,10 +1279,10 @@ int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev) u32 reg; if (rt2x00_rt(rt2x00dev, RT3290)) { - rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, ®); + reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0); } else { - rt2800_register_read(rt2x00dev, GPIO_CTRL, ®); + reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); return rt2x00_get_field32(reg, GPIO_CTRL_VAL2); } } @@ -1185,7 +1307,7 @@ static void rt2800_brightness_set(struct led_classdev *led_cdev, /* Check for SoC (SOC devices don't support MCU requests) */ if (rt2x00_is_soc(led->rt2x00dev)) { - rt2800_register_read(led->rt2x00dev, LED_CFG, ®); + reg = rt2800_register_read(led->rt2x00dev, LED_CFG); /* Set LED Polarity */ rt2x00_set_field32(®, LED_CFG_LED_POLAR, polarity); @@ -1274,7 +1396,7 @@ static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev, * The BSS Idx numbers is split in a main value of 3 bits, * and a extended field for adding one additional bit to the value. */ - rt2800_register_read(rt2x00dev, offset, ®); + reg = rt2800_register_read(rt2x00dev, offset); rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7)); rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT, (bssidx & 0x8) >> 3); @@ -1292,7 +1414,7 @@ static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev, offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx); if (crypto->cmd == SET_KEY) { - rt2800_register_read(rt2x00dev, offset, ®); + reg = rt2800_register_read(rt2x00dev, offset); rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)); /* @@ -1308,7 +1430,7 @@ static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev, rt2800_register_write(rt2x00dev, offset, reg); } else { /* Delete the cipher without touching the bssidx */ - rt2800_register_read(rt2x00dev, offset, ®); + reg = rt2800_register_read(rt2x00dev, offset); rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, 0); rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, 0); rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0); @@ -1364,7 +1486,7 @@ int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev, offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8); - rt2800_register_read(rt2x00dev, offset, ®); + reg = rt2800_register_read(rt2x00dev, offset); rt2x00_set_field32(®, field, (crypto->cmd == SET_KEY) * crypto->cipher); rt2800_register_write(rt2x00dev, offset, reg); @@ -1418,6 +1540,23 @@ int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev, } EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key); +static void rt2800_set_max_psdu_len(struct rt2x00_dev *rt2x00dev) +{ + u8 i, max_psdu; + u32 reg; + struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; + + for (i = 0; i < 3; i++) + if (drv_data->ampdu_factor_cnt[i] > 0) + break; + + max_psdu = min(drv_data->max_psdu, i); + + reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG); + rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, max_psdu); + rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg); +} + int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif, struct ieee80211_sta *sta) { @@ -1426,6 +1565,17 @@ int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif, struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; /* + * Limit global maximum TX AMPDU length to smallest value of all + * connected stations. In AP mode this can be suboptimal, but we + * do not have a choice if some connected STA is not capable to + * receive the same amount of data like the others. + */ + if (sta->ht_cap.ht_supported) { + drv_data->ampdu_factor_cnt[sta->ht_cap.ampdu_factor & 3]++; + rt2800_set_max_psdu_len(rt2x00dev); + } + + /* * Search for the first free WCID entry and return the corresponding * index. */ @@ -1445,6 +1595,7 @@ int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif, return 0; __set_bit(wcid - WCID_START, drv_data->sta_ids); + drv_data->wcid_to_sta[wcid - WCID_START] = sta; /* * Clean up WCID attributes and write STA address to the device. @@ -1457,9 +1608,16 @@ int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif, } EXPORT_SYMBOL_GPL(rt2800_sta_add); -int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid) +int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, struct ieee80211_sta *sta) { struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; + struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta); + int wcid = sta_priv->wcid; + + if (sta->ht_cap.ht_supported) { + drv_data->ampdu_factor_cnt[sta->ht_cap.ampdu_factor & 3]--; + rt2800_set_max_psdu_len(rt2x00dev); + } if (wcid > WCID_END) return 0; @@ -1468,6 +1626,7 @@ int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid) * get renewed when the WCID is reused. */ rt2800_config_wcid(rt2x00dev, NULL, wcid); + drv_data->wcid_to_sta[wcid - WCID_START] = NULL; __clear_bit(wcid - WCID_START, drv_data->sta_ids); return 0; @@ -1485,7 +1644,7 @@ void rt2800_config_filter(struct rt2x00_dev *rt2x00dev, * and broadcast frames will always be accepted since * there is no filter for it at this time. */ - rt2800_register_read(rt2x00dev, RX_FILTER_CFG, ®); + reg = rt2800_register_read(rt2x00dev, RX_FILTER_CFG); rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CRC_ERROR, !(filter_flags & FIF_FCSFAIL)); rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PHY_ERROR, @@ -1529,7 +1688,7 @@ void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf, /* * Enable synchronisation. */ - rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); + reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, conf->sync); rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); @@ -1537,14 +1696,14 @@ void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf, /* * Tune beacon queue transmit parameters for AP mode */ - rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, ®); + reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG); rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 0); rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 1); rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 0); rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg); } else { - rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, ®); + reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG); rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 4); rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 2); rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); @@ -1663,22 +1822,22 @@ static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev, gf20_mode = gf40_mode = 1; /* Update HT protection config */ - rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®); + reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG); rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, mm20_rate); rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode); rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); - rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®); + reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG); rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, mm40_rate); rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode); rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); - rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®); + reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG); rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, gf20_rate); rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode); rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); - rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®); + reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG); rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, gf40_rate); rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode); rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); @@ -1690,14 +1849,14 @@ void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp, u32 reg; if (changed & BSS_CHANGED_ERP_PREAMBLE) { - rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, ®); + reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG); rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, !!erp->short_preamble); rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); } if (changed & BSS_CHANGED_ERP_CTS_PROT) { - rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®); + reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG); rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, erp->cts_protection ? 2 : 0); rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); @@ -1710,18 +1869,18 @@ void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp, } if (changed & BSS_CHANGED_ERP_SLOT) { - rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, ®); + reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG); rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time); rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); - rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, ®); + reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG); rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, erp->eifs); rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg); } if (changed & BSS_CHANGED_BEACON_INT) { - rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); + reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, erp->beacon_int * 16); rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); @@ -1738,7 +1897,7 @@ static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev) u16 eeprom; u8 led_ctrl, led_g_mode, led_r_mode; - rt2800_register_read(rt2x00dev, GPIO_SWITCH, ®); + reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) { rt2x00_set_field32(®, GPIO_SWITCH_0, 1); rt2x00_set_field32(®, GPIO_SWITCH_1, 1); @@ -1748,12 +1907,12 @@ static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev) } rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); - rt2800_register_read(rt2x00dev, LED_CFG, ®); + reg = rt2800_register_read(rt2x00dev, LED_CFG); led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0; led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3; if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) || led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) { - rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom); + eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ); led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE); if (led_ctrl == 0 || led_ctrl > 0x40) { rt2x00_set_field32(®, LED_CFG_G_LED_MODE, led_g_mode); @@ -1774,14 +1933,14 @@ static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev, u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1; if (rt2x00_is_pci(rt2x00dev)) { - rt2800_register_read(rt2x00dev, E2PROM_CSR, ®); + reg = rt2800_register_read(rt2x00dev, E2PROM_CSR); rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK, eesk_pin); rt2800_register_write(rt2x00dev, E2PROM_CSR, reg); } else if (rt2x00_is_usb(rt2x00dev)) rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff, eesk_pin, 0); - rt2800_register_read(rt2x00dev, GPIO_CTRL, ®); + reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0); rt2x00_set_field32(®, GPIO_CTRL_VAL3, gpio_bit3); rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); @@ -1793,8 +1952,8 @@ void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant) u8 r3; u16 eeprom; - rt2800_bbp_read(rt2x00dev, 1, &r1); - rt2800_bbp_read(rt2x00dev, 3, &r3); + r1 = rt2800_bbp_read(rt2x00dev, 1); + r3 = rt2800_bbp_read(rt2x00dev, 3); if (rt2x00_rt(rt2x00dev, RT3572) && rt2x00_has_cap_bt_coexist(rt2x00dev)) @@ -1828,8 +1987,8 @@ void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant) rt2x00_rt(rt2x00dev, RT3090) || rt2x00_rt(rt2x00dev, RT3352) || rt2x00_rt(rt2x00dev, RT3390)) { - rt2800_eeprom_read(rt2x00dev, - EEPROM_NIC_CONF1, &eeprom); + eeprom = rt2800_eeprom_read(rt2x00dev, + EEPROM_NIC_CONF1); if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY)) rt2800_set_ant_diversity(rt2x00dev, @@ -1872,28 +2031,28 @@ static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev, short lna_gain; if (libconf->rf.channel <= 14) { - rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom); + eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA); lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG); } else if (libconf->rf.channel <= 64) { - rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom); + eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA); lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0); } else if (libconf->rf.channel <= 128) { if (rt2x00_rt(rt2x00dev, RT3593)) { - rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom); + eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2); lna_gain = rt2x00_get_field16(eeprom, EEPROM_EXT_LNA2_A1); } else { - rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom); + eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2); lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1); } } else { if (rt2x00_rt(rt2x00dev, RT3593)) { - rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom); + eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2); lna_gain = rt2x00_get_field16(eeprom, EEPROM_EXT_LNA2_A2); } else { - rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom); + eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2); lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2); } @@ -1902,9 +2061,14 @@ static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev, rt2x00dev->lna_gain = lna_gain; } +static inline bool rt2800_clk_is_20mhz(struct rt2x00_dev *rt2x00dev) +{ + return clk_get_rate(rt2x00dev->clk) == 20000000; +} + #define FREQ_OFFSET_BOUND 0x5f -static void rt2800_adjust_freq_offset(struct rt2x00_dev *rt2x00dev) +static void rt2800_freq_cal_mode1(struct rt2x00_dev *rt2x00dev) { u8 freq_offset, prev_freq_offset; u8 rfcsr, prev_rfcsr; @@ -1912,7 +2076,7 @@ static void rt2800_adjust_freq_offset(struct rt2x00_dev *rt2x00dev) freq_offset = rt2x00_get_field8(rt2x00dev->freq_offset, RFCSR17_CODE); freq_offset = min_t(u8, freq_offset, FREQ_OFFSET_BOUND); - rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 17); prev_rfcsr = rfcsr; rt2x00_set_field8(&rfcsr, RFCSR17_CODE, freq_offset); @@ -2014,23 +2178,23 @@ static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev, rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1); - rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3); rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); - rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2); rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); - rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 12); rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1); rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); - rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 13); rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2); rt2800_rfcsr_write(rt2x00dev, 13, rfcsr); - rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, rt2x00dev->default_ant.rx_chain_num <= 1); @@ -2043,7 +2207,7 @@ static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev, rt2x00dev->default_ant.tx_chain_num <= 2); rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); - rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 23); rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset); rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); @@ -2060,22 +2224,24 @@ static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev, } } - rt2800_rfcsr_read(rt2x00dev, 24, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 24); rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx); rt2800_rfcsr_write(rt2x00dev, 24, rfcsr); - rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 31); rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx); rt2800_rfcsr_write(rt2x00dev, 31, rfcsr); - rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 7); rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); - rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1); rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); - msleep(1); + + usleep_range(1000, 1500); + rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0); rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); } @@ -2100,7 +2266,7 @@ static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev, rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1); rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3); - rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2); if (rf->channel <= 14) rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2); @@ -2108,14 +2274,14 @@ static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev, rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1); rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); - rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 5); if (rf->channel <= 14) rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1); else rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2); rt2800_rfcsr_write(rt2x00dev, 5, rfcsr); - rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 12); if (rf->channel <= 14) { rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3); rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, @@ -2128,7 +2294,7 @@ static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev, } rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); - rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 13); if (rf->channel <= 14) { rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3); rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, @@ -2141,7 +2307,7 @@ static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev, } rt2800_rfcsr_write(rt2x00dev, 13, rfcsr); - rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); @@ -2174,7 +2340,7 @@ static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev, } rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); - rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 23); rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset); rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); @@ -2204,7 +2370,7 @@ static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev, rt2800_rfcsr_write(rt2x00dev, 27, 0x00); rt2800_rfcsr_write(rt2x00dev, 29, 0x9b); } else { - rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 7); rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1); rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0); rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1); @@ -2237,7 +2403,7 @@ static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev, rt2800_rfcsr_write(rt2x00dev, 29, 0x9f); } - rt2800_register_read(rt2x00dev, GPIO_CTRL, ®); + reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); rt2x00_set_field32(®, GPIO_CTRL_DIR7, 0); if (rf->channel <= 14) rt2x00_set_field32(®, GPIO_CTRL_VAL7, 1); @@ -2245,7 +2411,7 @@ static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev, rt2x00_set_field32(®, GPIO_CTRL_VAL7, 0); rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); - rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 7); rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); } @@ -2263,12 +2429,12 @@ static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev, const bool txbf_enabled = false; /* TODO */ /* TODO: use TX{0,1,2}FinePowerControl values from EEPROM */ - rt2800_bbp_read(rt2x00dev, 109, &bbp); + bbp = rt2800_bbp_read(rt2x00dev, 109); rt2x00_set_field8(&bbp, BBP109_TX0_POWER, 0); rt2x00_set_field8(&bbp, BBP109_TX1_POWER, 0); rt2800_bbp_write(rt2x00dev, 109, bbp); - rt2800_bbp_read(rt2x00dev, 110, &bbp); + bbp = rt2800_bbp_read(rt2x00dev, 110); rt2x00_set_field8(&bbp, BBP110_TX2_POWER, 0); rt2800_bbp_write(rt2x00dev, 110, bbp); @@ -2288,11 +2454,11 @@ static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev, rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3 & 0xf); - rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); rt2x00_set_field8(&rfcsr, RFCSR11_R, (rf->rf2 & 0x3)); rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); - rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); rt2x00_set_field8(&rfcsr, RFCSR11_PLL_IDOH, 1); if (rf->channel <= 14) rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 1); @@ -2300,7 +2466,7 @@ static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev, rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 2); rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); - rt2800_rfcsr_read(rt2x00dev, 53, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 53); if (rf->channel <= 14) { rfcsr = 0; rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER, @@ -2315,7 +2481,7 @@ static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev, } rt2800_rfcsr_write(rt2x00dev, 53, rfcsr); - rt2800_rfcsr_read(rt2x00dev, 55, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 55); if (rf->channel <= 14) { rfcsr = 0; rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER, @@ -2330,7 +2496,7 @@ static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev, } rt2800_rfcsr_write(rt2x00dev, 55, rfcsr); - rt2800_rfcsr_read(rt2x00dev, 54, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 54); if (rf->channel <= 14) { rfcsr = 0; rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER, @@ -2345,7 +2511,7 @@ static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev, } rt2800_rfcsr_write(rt2x00dev, 54, rfcsr); - rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); @@ -2380,7 +2546,7 @@ static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev, } rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); - rt2800_adjust_freq_offset(rt2x00dev); + rt2800_freq_cal_mode1(rt2x00dev); if (conf_is_ht40(conf)) { txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw40, @@ -2397,7 +2563,7 @@ static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev, /* NOTE: the reference driver does not writes the new value * back to RFCSR 32 */ - rt2800_rfcsr_read(rt2x00dev, 32, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 32); rt2x00_set_field8(&rfcsr, RFCSR32_TX_AGC_FC, txrx_agc_fc); if (rf->channel <= 14) @@ -2406,34 +2572,34 @@ static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev, rfcsr = 0x80; rt2800_rfcsr_write(rt2x00dev, 31, rfcsr); - rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, txrx_h20m); rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, txrx_h20m); rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); /* Band selection */ - rt2800_rfcsr_read(rt2x00dev, 36, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 36); if (rf->channel <= 14) rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1); else rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0); rt2800_rfcsr_write(rt2x00dev, 36, rfcsr); - rt2800_rfcsr_read(rt2x00dev, 34, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 34); if (rf->channel <= 14) rfcsr = 0x3c; else rfcsr = 0x20; rt2800_rfcsr_write(rt2x00dev, 34, rfcsr); - rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 12); if (rf->channel <= 14) rfcsr = 0x1a; else rfcsr = 0x12; rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); - rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); if (rf->channel >= 1 && rf->channel <= 14) rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1); else if (rf->channel >= 36 && rf->channel <= 64) @@ -2444,7 +2610,7 @@ static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev, rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1); rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); - rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2); rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); @@ -2458,11 +2624,11 @@ static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev, rt2800_rfcsr_write(rt2x00dev, 13, 0x23); } - rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 51); rt2x00_set_field8(&rfcsr, RFCSR51_BITS01, 1); rt2800_rfcsr_write(rt2x00dev, 51, rfcsr); - rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 51); if (rf->channel <= 14) { rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 5); rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 3); @@ -2472,7 +2638,7 @@ static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev, } rt2800_rfcsr_write(rt2x00dev, 51, rfcsr); - rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 49); if (rf->channel <= 14) rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 3); else @@ -2483,11 +2649,11 @@ static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev, rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); - rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 50); rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO1_EN, 0); rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); - rt2800_rfcsr_read(rt2x00dev, 57, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 57); if (rf->channel <= 14) rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x1b); else @@ -2503,7 +2669,7 @@ static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev, } /* Initiate VCO calibration */ - rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); if (rf->channel <= 14) { rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); } else { @@ -2559,18 +2725,18 @@ static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev, rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); - rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2); rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); - rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 49); if (info->default_power1 > POWER_BOUND) rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND); else rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1); rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); - rt2800_adjust_freq_offset(rt2x00dev); + rt2800_freq_cal_mode1(rt2x00dev); if (rf->channel <= 14) { if (rf->channel == 6) @@ -2611,9 +2777,9 @@ static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev, else rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2); - rt2800_adjust_freq_offset(rt2x00dev); + rt2800_freq_cal_mode1(rt2x00dev); - rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); @@ -2644,11 +2810,11 @@ static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev, rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); - rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2); rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); - rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 49); if (info->default_power1 > POWER_BOUND) rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND); else @@ -2656,7 +2822,7 @@ static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev, rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); if (rt2x00_rt(rt2x00dev, RT5392)) { - rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 50); if (info->default_power2 > POWER_BOUND) rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND); else @@ -2665,7 +2831,7 @@ static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev, rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); } - rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); if (rt2x00_rt(rt2x00dev, RT5392)) { rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); @@ -2676,7 +2842,7 @@ static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev, rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); - rt2800_adjust_freq_offset(rt2x00dev); + rt2800_freq_cal_mode1(rt2x00dev); if (rf->channel <= 14) { int idx = rf->channel-1; @@ -2716,13 +2882,21 @@ static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev, rt2800_rfcsr_write(rt2x00dev, 59, r59_nonbt_rev[idx]); } else if (rt2x00_rt(rt2x00dev, RT5390) || - rt2x00_rt(rt2x00dev, RT5392)) { + rt2x00_rt(rt2x00dev, RT5392) || + rt2x00_rt(rt2x00dev, RT6352)) { static const char r59_non_bt[] = {0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d, 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86}; rt2800_rfcsr_write(rt2x00dev, 59, r59_non_bt[idx]); + } else if (rt2x00_rt(rt2x00dev, RT5350)) { + static const char r59_non_bt[] = {0x0b, 0x0b, + 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0a, + 0x0a, 0x09, 0x08, 0x07, 0x07, 0x06}; + + rt2800_rfcsr_write(rt2x00dev, 59, + r59_non_bt[idx]); } } } @@ -2741,7 +2915,7 @@ static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev, const bool is_11b = false; const bool is_type_ep = false; - rt2800_register_read(rt2x00dev, LDO_CFG0, ®); + reg = rt2800_register_read(rt2x00dev, LDO_CFG0); rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0); rt2800_register_write(rt2x00dev, LDO_CFG0, reg); @@ -2749,13 +2923,13 @@ static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev, /* Order of values on rf_channel entry: N, K, mod, R */ rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff); - rt2800_rfcsr_read(rt2x00dev, 9, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 9); rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf); rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8); rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2); rt2800_rfcsr_write(rt2x00dev, 9, rfcsr); - rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1); rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3); rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); @@ -2923,7 +3097,7 @@ static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev, ep_reg = 0x3; } - rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 49); if (info->default_power1 > power_bound) rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound); else @@ -2932,7 +3106,7 @@ static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev, rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg); rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); - rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 50); if (info->default_power2 > power_bound) rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound); else @@ -2941,7 +3115,7 @@ static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev, rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg); rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); - rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); @@ -2971,10 +3145,10 @@ static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev, } /* TODO proper frequency adjustment */ - rt2800_adjust_freq_offset(rt2x00dev); + rt2800_freq_cal_mode1(rt2x00dev); /* TODO merge with others */ - rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); @@ -3003,6 +3177,243 @@ static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev, rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F); } +static void rt2800_config_channel_rf7620(struct rt2x00_dev *rt2x00dev, + struct ieee80211_conf *conf, + struct rf_channel *rf, + struct channel_info *info) +{ + struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; + u8 rx_agc_fc, tx_agc_fc; + u8 rfcsr; + + /* Frequeny plan setting */ + /* Rdiv setting (set 0x03 if Xtal==20) + * R13[1:0] + */ + rfcsr = rt2800_rfcsr_read(rt2x00dev, 13); + rt2x00_set_field8(&rfcsr, RFCSR13_RDIV_MT7620, + rt2800_clk_is_20mhz(rt2x00dev) ? 3 : 0); + rt2800_rfcsr_write(rt2x00dev, 13, rfcsr); + + /* N setting + * R20[7:0] in rf->rf1 + * R21[0] always 0 + */ + rfcsr = rt2800_rfcsr_read(rt2x00dev, 20); + rfcsr = (rf->rf1 & 0x00ff); + rt2800_rfcsr_write(rt2x00dev, 20, rfcsr); + + rfcsr = rt2800_rfcsr_read(rt2x00dev, 21); + rt2x00_set_field8(&rfcsr, RFCSR21_BIT1, 0); + rt2800_rfcsr_write(rt2x00dev, 21, rfcsr); + + /* K setting (always 0) + * R16[3:0] (RF PLL freq selection) + */ + rfcsr = rt2800_rfcsr_read(rt2x00dev, 16); + rt2x00_set_field8(&rfcsr, RFCSR16_RF_PLL_FREQ_SEL_MT7620, 0); + rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); + + /* D setting (always 0) + * R22[2:0] (D=15, R22[2:0]=<111>) + */ + rfcsr = rt2800_rfcsr_read(rt2x00dev, 22); + rt2x00_set_field8(&rfcsr, RFCSR22_FREQPLAN_D_MT7620, 0); + rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); + + /* Ksd setting + * Ksd: R17<7:0> in rf->rf2 + * R18<7:0> in rf->rf3 + * R19<1:0> in rf->rf4 + */ + rfcsr = rt2800_rfcsr_read(rt2x00dev, 17); + rfcsr = rf->rf2; + rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); + + rfcsr = rt2800_rfcsr_read(rt2x00dev, 18); + rfcsr = rf->rf3; + rt2800_rfcsr_write(rt2x00dev, 18, rfcsr); + + rfcsr = rt2800_rfcsr_read(rt2x00dev, 19); + rt2x00_set_field8(&rfcsr, RFCSR19_K, rf->rf4); + rt2800_rfcsr_write(rt2x00dev, 19, rfcsr); + + /* Default: XO=20MHz , SDM mode */ + rfcsr = rt2800_rfcsr_read(rt2x00dev, 16); + rt2x00_set_field8(&rfcsr, RFCSR16_SDM_MODE_MT7620, 0x80); + rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); + + rfcsr = rt2800_rfcsr_read(rt2x00dev, 21); + rt2x00_set_field8(&rfcsr, RFCSR21_BIT8, 1); + rt2800_rfcsr_write(rt2x00dev, 21, rfcsr); + + rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); + rt2x00_set_field8(&rfcsr, RFCSR1_TX2_EN_MT7620, + rt2x00dev->default_ant.tx_chain_num != 1); + rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); + + rfcsr = rt2800_rfcsr_read(rt2x00dev, 2); + rt2x00_set_field8(&rfcsr, RFCSR2_TX2_EN_MT7620, + rt2x00dev->default_ant.tx_chain_num != 1); + rt2x00_set_field8(&rfcsr, RFCSR2_RX2_EN_MT7620, + rt2x00dev->default_ant.rx_chain_num != 1); + rt2800_rfcsr_write(rt2x00dev, 2, rfcsr); + + rfcsr = rt2800_rfcsr_read(rt2x00dev, 42); + rt2x00_set_field8(&rfcsr, RFCSR42_TX2_EN_MT7620, + rt2x00dev->default_ant.tx_chain_num != 1); + rt2800_rfcsr_write(rt2x00dev, 42, rfcsr); + + /* RF for DC Cal BW */ + if (conf_is_ht40(conf)) { + rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10); + rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10); + rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04); + rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10); + rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10); + } else { + rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x20); + rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x20); + rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x00); + rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x20); + rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x20); + } + + if (conf_is_ht40(conf)) { + rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x08); + rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x08); + } else { + rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x28); + rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x28); + } + + rfcsr = rt2800_rfcsr_read(rt2x00dev, 28); + rt2x00_set_field8(&rfcsr, RFCSR28_CH11_HT40, + conf_is_ht40(conf) && (rf->channel == 11)); + rt2800_rfcsr_write(rt2x00dev, 28, rfcsr); + + if (!test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags)) { + if (conf_is_ht40(conf)) { + rx_agc_fc = drv_data->rx_calibration_bw40; + tx_agc_fc = drv_data->tx_calibration_bw40; + } else { + rx_agc_fc = drv_data->rx_calibration_bw20; + tx_agc_fc = drv_data->tx_calibration_bw20; + } + rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6); + rfcsr &= (~0x3F); + rfcsr |= rx_agc_fc; + rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rfcsr); + rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7); + rfcsr &= (~0x3F); + rfcsr |= rx_agc_fc; + rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rfcsr); + rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 6); + rfcsr &= (~0x3F); + rfcsr |= rx_agc_fc; + rt2800_rfcsr_write_bank(rt2x00dev, 7, 6, rfcsr); + rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 7); + rfcsr &= (~0x3F); + rfcsr |= rx_agc_fc; + rt2800_rfcsr_write_bank(rt2x00dev, 7, 7, rfcsr); + + rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58); + rfcsr &= (~0x3F); + rfcsr |= tx_agc_fc; + rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rfcsr); + rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59); + rfcsr &= (~0x3F); + rfcsr |= tx_agc_fc; + rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rfcsr); + rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 58); + rfcsr &= (~0x3F); + rfcsr |= tx_agc_fc; + rt2800_rfcsr_write_bank(rt2x00dev, 7, 58, rfcsr); + rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 59); + rfcsr &= (~0x3F); + rfcsr |= tx_agc_fc; + rt2800_rfcsr_write_bank(rt2x00dev, 7, 59, rfcsr); + } +} + +static void rt2800_config_alc(struct rt2x00_dev *rt2x00dev, + struct ieee80211_channel *chan, + int power_level) { + u16 eeprom, target_power, max_power; + u32 mac_sys_ctrl, mac_status; + u32 reg; + u8 bbp; + int i; + + /* hardware unit is 0.5dBm, limited to 23.5dBm */ + power_level *= 2; + if (power_level > 0x2f) + power_level = 0x2f; + + max_power = chan->max_power * 2; + if (max_power > 0x2f) + max_power = 0x2f; + + reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_0); + rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_0, power_level); + rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_1, power_level); + rt2x00_set_field32(®, TX_ALC_CFG_0_LIMIT_0, max_power); + rt2x00_set_field32(®, TX_ALC_CFG_0_LIMIT_1, max_power); + + eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); + if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_INTERNAL_TX_ALC)) { + /* init base power by eeprom target power */ + target_power = rt2800_eeprom_read(rt2x00dev, + EEPROM_TXPOWER_INIT); + rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_0, target_power); + rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_1, target_power); + } + rt2800_register_write(rt2x00dev, TX_ALC_CFG_0, reg); + + reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1); + rt2x00_set_field32(®, TX_ALC_CFG_1_TX_TEMP_COMP, 0); + rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg); + + /* Save MAC SYS CTRL registers */ + mac_sys_ctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); + /* Disable Tx/Rx */ + rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0); + /* Check MAC Tx/Rx idle */ + for (i = 0; i < 10000; i++) { + mac_status = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG); + if (mac_status & 0x3) + usleep_range(50, 200); + else + break; + } + + if (i == 10000) + rt2x00_warn(rt2x00dev, "Wait MAC Status to MAX !!!\n"); + + if (chan->center_freq > 2457) { + bbp = rt2800_bbp_read(rt2x00dev, 30); + bbp = 0x40; + rt2800_bbp_write(rt2x00dev, 30, bbp); + rt2800_rfcsr_write(rt2x00dev, 39, 0); + if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) + rt2800_rfcsr_write(rt2x00dev, 42, 0xfb); + else + rt2800_rfcsr_write(rt2x00dev, 42, 0x7b); + } else { + bbp = rt2800_bbp_read(rt2x00dev, 30); + bbp = 0x1f; + rt2800_bbp_write(rt2x00dev, 30, bbp); + rt2800_rfcsr_write(rt2x00dev, 39, 0x80); + if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) + rt2800_rfcsr_write(rt2x00dev, 42, 0xdb); + else + rt2800_rfcsr_write(rt2x00dev, 42, 0x5b); + } + rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, mac_sys_ctrl); + + rt2800_vco_calibration(rt2x00dev); +} + static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev, const unsigned int word, const u8 value) @@ -3010,7 +3421,7 @@ static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev, u8 chain, reg; for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) { - rt2800_bbp_read(rt2x00dev, 27, ®); + reg = rt2800_bbp_read(rt2x00dev, 27); rt2x00_set_field8(®, BBP27_RX_CHAIN_SEL, chain); rt2800_bbp_write(rt2x00dev, 27, reg); @@ -3127,7 +3538,7 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, struct channel_info *info) { u32 reg; - unsigned int tx_pin; + u32 tx_pin; u8 bbp, rfcsr; info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel, @@ -3160,6 +3571,7 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info); break; case RF3070: + case RF5350: case RF5360: case RF5362: case RF5370: @@ -3171,6 +3583,9 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, case RF5592: rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info); break; + case RF7620: + rt2800_config_channel_rf7620(rt2x00dev, conf, rf, info); + break; default: rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info); } @@ -3178,18 +3593,28 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, if (rt2x00_rf(rt2x00dev, RF3070) || rt2x00_rf(rt2x00dev, RF3290) || rt2x00_rf(rt2x00dev, RF3322) || + rt2x00_rf(rt2x00dev, RF5350) || rt2x00_rf(rt2x00dev, RF5360) || rt2x00_rf(rt2x00dev, RF5362) || rt2x00_rf(rt2x00dev, RF5370) || rt2x00_rf(rt2x00dev, RF5372) || rt2x00_rf(rt2x00dev, RF5390) || rt2x00_rf(rt2x00dev, RF5392)) { - rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr); - rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0); - rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); + if (rt2x00_rf(rt2x00dev, RF3322)) { + rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_TX_H20M, + conf_is_ht40(conf)); + rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_RX_H20M, + conf_is_ht40(conf)); + } else { + rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, + conf_is_ht40(conf)); + rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, + conf_is_ht40(conf)); + } rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); - rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); } @@ -3197,11 +3622,18 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, /* * Change BBP settings */ + if (rt2x00_rt(rt2x00dev, RT3352)) { + rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); + rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); + rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); + rt2800_bbp_write(rt2x00dev, 27, 0x0); rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain); rt2800_bbp_write(rt2x00dev, 27, 0x20); rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain); + rt2800_bbp_write(rt2x00dev, 86, 0x38); + rt2800_bbp_write(rt2x00dev, 83, 0x6a); } else if (rt2x00_rt(rt2x00dev, RT3593)) { if (rf->channel > 14) { /* Disable CCK Packet detection on 5GHz */ @@ -3228,7 +3660,8 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, if (rf->channel <= 14) { if (!rt2x00_rt(rt2x00dev, RT5390) && - !rt2x00_rt(rt2x00dev, RT5392)) { + !rt2x00_rt(rt2x00dev, RT5392) && + !rt2x00_rt(rt2x00dev, RT6352)) { if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) { rt2800_bbp_write(rt2x00dev, 82, 0x62); rt2800_bbp_write(rt2x00dev, 75, 0x46); @@ -3248,7 +3681,7 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, rt2800_bbp_write(rt2x00dev, 82, 0x94); else if (rt2x00_rt(rt2x00dev, RT3593)) rt2800_bbp_write(rt2x00dev, 82, 0x82); - else + else if (!rt2x00_rt(rt2x00dev, RT6352)) rt2800_bbp_write(rt2x00dev, 82, 0xf2); if (rt2x00_rt(rt2x00dev, RT3593)) @@ -3260,7 +3693,7 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, rt2800_bbp_write(rt2x00dev, 75, 0x50); } - rt2800_register_read(rt2x00dev, TX_BAND_CFG, ®); + reg = rt2800_register_read(rt2x00dev, TX_BAND_CFG); rt2x00_set_field32(®, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf)); rt2x00_set_field32(®, TX_BAND_CFG_A, rf->channel > 14); rt2x00_set_field32(®, TX_BAND_CFG_BG, rf->channel <= 14); @@ -3269,7 +3702,7 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, if (rt2x00_rt(rt2x00dev, RT3572)) rt2800_rfcsr_write(rt2x00dev, 8, 0); - tx_pin = 0; + tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG); switch (rt2x00dev->default_ant.tx_chain_num) { case 3: @@ -3318,6 +3751,7 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1); rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1); + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFRX_EN, 1); /* mt7620 */ rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); @@ -3334,7 +3768,7 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, } if (rt2x00_rt(rt2x00dev, RT3593)) { - rt2800_register_read(rt2x00dev, GPIO_CTRL, ®); + reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); /* Band selection */ if (rt2x00_is_usb(rt2x00dev) || @@ -3376,22 +3810,36 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, usleep_range(1000, 1500); } - if (rt2x00_rt(rt2x00dev, RT5592)) { + if (rt2x00_rt(rt2x00dev, RT5592) || rt2x00_rt(rt2x00dev, RT6352)) { + reg = 0x10; + if (!conf_is_ht40(conf)) { + if (rt2x00_rt(rt2x00dev, RT6352) && + rt2x00_has_cap_external_lna_bg(rt2x00dev)) { + reg |= 0x5; + } else { + reg |= 0xa; + } + } rt2800_bbp_write(rt2x00dev, 195, 141); - rt2800_bbp_write(rt2x00dev, 196, conf_is_ht40(conf) ? 0x10 : 0x1a); + rt2800_bbp_write(rt2x00dev, 196, reg); /* AGC init */ - reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2 * rt2x00dev->lna_gain; + if (rt2x00_rt(rt2x00dev, RT6352)) + reg = 0x04; + else + reg = rf->channel <= 14 ? 0x1c : 0x24; + + reg += 2 * rt2x00dev->lna_gain; rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); rt2800_iq_calibrate(rt2x00dev, rf->channel); } - rt2800_bbp_read(rt2x00dev, 4, &bbp); + bbp = rt2800_bbp_read(rt2x00dev, 4); rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf)); rt2800_bbp_write(rt2x00dev, 4, bbp); - rt2800_bbp_read(rt2x00dev, 3, &bbp); + bbp = rt2800_bbp_read(rt2x00dev, 3); rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf)); rt2800_bbp_write(rt2x00dev, 3, bbp); @@ -3407,20 +3855,21 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, } } - msleep(1); + usleep_range(1000, 1500); /* * Clear channel statistic counters */ - rt2800_register_read(rt2x00dev, CH_IDLE_STA, ®); - rt2800_register_read(rt2x00dev, CH_BUSY_STA, ®); - rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, ®); + reg = rt2800_register_read(rt2x00dev, CH_IDLE_STA); + reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA); + reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC); /* * Clear update flag */ - if (rt2x00_rt(rt2x00dev, RT3352)) { - rt2800_bbp_read(rt2x00dev, 49, &bbp); + if (rt2x00_rt(rt2x00dev, RT3352) || + rt2x00_rt(rt2x00dev, RT5350)) { + bbp = rt2800_bbp_read(rt2x00dev, 49); rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0); rt2800_bbp_write(rt2x00dev, 49, bbp); } @@ -3437,7 +3886,7 @@ static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev) /* * First check if temperature compensation is supported. */ - rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom); + eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); if (!rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC)) return 0; @@ -3450,62 +3899,62 @@ static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev) * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00 */ if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) { - rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom); + eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1); tssi_bounds[0] = rt2x00_get_field16(eeprom, EEPROM_TSSI_BOUND_BG1_MINUS4); tssi_bounds[1] = rt2x00_get_field16(eeprom, EEPROM_TSSI_BOUND_BG1_MINUS3); - rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom); + eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2); tssi_bounds[2] = rt2x00_get_field16(eeprom, EEPROM_TSSI_BOUND_BG2_MINUS2); tssi_bounds[3] = rt2x00_get_field16(eeprom, EEPROM_TSSI_BOUND_BG2_MINUS1); - rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom); + eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3); tssi_bounds[4] = rt2x00_get_field16(eeprom, EEPROM_TSSI_BOUND_BG3_REF); tssi_bounds[5] = rt2x00_get_field16(eeprom, EEPROM_TSSI_BOUND_BG3_PLUS1); - rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom); + eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4); tssi_bounds[6] = rt2x00_get_field16(eeprom, EEPROM_TSSI_BOUND_BG4_PLUS2); tssi_bounds[7] = rt2x00_get_field16(eeprom, EEPROM_TSSI_BOUND_BG4_PLUS3); - rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom); + eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5); tssi_bounds[8] = rt2x00_get_field16(eeprom, EEPROM_TSSI_BOUND_BG5_PLUS4); step = rt2x00_get_field16(eeprom, EEPROM_TSSI_BOUND_BG5_AGC_STEP); } else { - rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom); + eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1); tssi_bounds[0] = rt2x00_get_field16(eeprom, EEPROM_TSSI_BOUND_A1_MINUS4); tssi_bounds[1] = rt2x00_get_field16(eeprom, EEPROM_TSSI_BOUND_A1_MINUS3); - rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom); + eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2); tssi_bounds[2] = rt2x00_get_field16(eeprom, EEPROM_TSSI_BOUND_A2_MINUS2); tssi_bounds[3] = rt2x00_get_field16(eeprom, EEPROM_TSSI_BOUND_A2_MINUS1); - rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom); + eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3); tssi_bounds[4] = rt2x00_get_field16(eeprom, EEPROM_TSSI_BOUND_A3_REF); tssi_bounds[5] = rt2x00_get_field16(eeprom, EEPROM_TSSI_BOUND_A3_PLUS1); - rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom); + eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4); tssi_bounds[6] = rt2x00_get_field16(eeprom, EEPROM_TSSI_BOUND_A4_PLUS2); tssi_bounds[7] = rt2x00_get_field16(eeprom, EEPROM_TSSI_BOUND_A4_PLUS3); - rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom); + eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5); tssi_bounds[8] = rt2x00_get_field16(eeprom, EEPROM_TSSI_BOUND_A5_PLUS4); @@ -3522,7 +3971,7 @@ static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev) /* * Read current TSSI (BBP 49). */ - rt2800_bbp_read(rt2x00dev, 49, ¤t_tssi); + current_tssi = rt2800_bbp_read(rt2x00dev, 49); /* * Compare TSSI value (BBP49) with the compensation boundaries @@ -3551,7 +4000,7 @@ static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev, u8 comp_type; int comp_value = 0; - rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom); + eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA); /* * HT40 compensation not required. @@ -3629,13 +4078,13 @@ static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b, * .11b data rate need add additional 4dbm * when calculating eirp txpower. */ - rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, - 1, &eeprom); + eeprom = rt2800_eeprom_read_from_array(rt2x00dev, + EEPROM_TXPOWER_BYRATE, + 1); criterion = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); - rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, - &eeprom); + eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER); if (band == NL80211_BAND_2GHZ) eirp_txpower_criterion = rt2x00_get_field16(eeprom, @@ -3704,8 +4153,8 @@ static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev, offset += 8; /* read the next four txpower values */ - rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, - offset, &eeprom); + eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, + offset); /* CCK 1MBS,2MBS */ txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); @@ -3752,8 +4201,8 @@ static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev, TX_PWR_CFG_0_EXT_OFDM12_CH2, txpower); /* read the next four txpower values */ - rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, - offset + 1, &eeprom); + eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, + offset + 1); /* OFDM 24MBS,36MBS */ txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); @@ -3789,8 +4238,8 @@ static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev, TX_PWR_CFG_7_OFDM54_CH2, txpower); /* read the next four txpower values */ - rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, - offset + 2, &eeprom); + eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, + offset + 2); /* MCS 0,1 */ txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); @@ -3837,8 +4286,8 @@ static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev, TX_PWR_CFG_2_EXT_MCS6_CH2, txpower); /* read the next four txpower values */ - rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, - offset + 3, &eeprom); + eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, + offset + 3); /* MCS 7 */ txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); @@ -3885,8 +4334,8 @@ static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev, TX_PWR_CFG_3_EXT_MCS12_CH2, txpower); /* read the next four txpower values */ - rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, - offset + 4, &eeprom); + eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, + offset + 4); /* MCS 14 */ txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); @@ -3933,8 +4382,8 @@ static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev, TX_PWR_CFG_5_MCS18_CH2, txpower); /* read the next four txpower values */ - rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, - offset + 5, &eeprom); + eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, + offset + 5); /* MCS 20,21 */ txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); @@ -3970,8 +4419,8 @@ static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev, TX_PWR_CFG_8_MCS23_CH2, txpower); /* read the next four txpower values */ - rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, - offset + 6, &eeprom); + eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, + offset + 6); /* STBC, MCS 0,1 */ txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); @@ -4014,8 +4463,8 @@ static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev, txpower); /* read the next four txpower values */ - rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, - offset + 7, &eeprom); + eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, + offset + 7); /* STBC, MCS 7 */ txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); @@ -4062,6 +4511,130 @@ static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev, (unsigned long) regs[i]); } +static void rt2800_config_txpower_rt6352(struct rt2x00_dev *rt2x00dev, + struct ieee80211_channel *chan, + int power_level) +{ + u32 reg, pwreg; + u16 eeprom; + u32 data, gdata; + u8 t, i; + enum nl80211_band band = chan->band; + int delta; + + /* Warn user if bw_comp is set in EEPROM */ + delta = rt2800_get_txpower_bw_comp(rt2x00dev, band); + + if (delta) + rt2x00_warn(rt2x00dev, "ignoring EEPROM HT40 power delta: %d\n", + delta); + + /* populate TX_PWR_CFG_0 up to TX_PWR_CFG_4 from EEPROM for HT20, limit + * value to 0x3f and replace 0x20 by 0x21 as this is what the vendor + * driver does as well, though it looks kinda wrong. + * Maybe some misunderstanding of what a signed 8-bit value is? Maybe + * the hardware has a problem handling 0x20, and as the code initially + * used a fixed offset between HT20 and HT40 rates they had to work- + * around that issue and most likely just forgot about it later on. + * Maybe we should use rt2800_get_txpower_bw_comp() here as well, + * however, the corresponding EEPROM value is not respected by the + * vendor driver, so maybe this is rather being taken care of the + * TXALC and the driver doesn't need to handle it...? + * Though this is all very awkward, just do as they did, as that's what + * board vendors expected when they populated the EEPROM... + */ + for (i = 0; i < 5; i++) { + eeprom = rt2800_eeprom_read_from_array(rt2x00dev, + EEPROM_TXPOWER_BYRATE, + i * 2); + + data = eeprom; + + t = eeprom & 0x3f; + if (t == 32) + t++; + + gdata = t; + + t = (eeprom & 0x3f00) >> 8; + if (t == 32) + t++; + + gdata |= (t << 8); + + eeprom = rt2800_eeprom_read_from_array(rt2x00dev, + EEPROM_TXPOWER_BYRATE, + (i * 2) + 1); + + t = eeprom & 0x3f; + if (t == 32) + t++; + + gdata |= (t << 16); + + t = (eeprom & 0x3f00) >> 8; + if (t == 32) + t++; + + gdata |= (t << 24); + data |= (eeprom << 16); + + if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) { + /* HT20 */ + if (data != 0xffffffff) + rt2800_register_write(rt2x00dev, + TX_PWR_CFG_0 + (i * 4), + data); + } else { + /* HT40 */ + if (gdata != 0xffffffff) + rt2800_register_write(rt2x00dev, + TX_PWR_CFG_0 + (i * 4), + gdata); + } + } + + /* Aparently Ralink ran out of space in the BYRATE calibration section + * of the EERPOM which is copied to the corresponding TX_PWR_CFG_x + * registers. As recent 2T chips use 8-bit instead of 4-bit values for + * power-offsets more space would be needed. Ralink decided to keep the + * EEPROM layout untouched and rather have some shared values covering + * multiple bitrates. + * Populate the registers not covered by the EEPROM in the same way the + * vendor driver does. + */ + + /* For OFDM 54MBS use value from OFDM 48MBS */ + pwreg = 0; + reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_1); + t = rt2x00_get_field32(reg, TX_PWR_CFG_1B_48MBS); + rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_54MBS, t); + + /* For MCS 7 use value from MCS 6 */ + reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_2); + t = rt2x00_get_field32(reg, TX_PWR_CFG_2B_MCS6_MCS7); + rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_MCS7, t); + rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, pwreg); + + /* For MCS 15 use value from MCS 14 */ + pwreg = 0; + reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_3); + t = rt2x00_get_field32(reg, TX_PWR_CFG_3B_MCS14); + rt2x00_set_field32(&pwreg, TX_PWR_CFG_8B_MCS15, t); + rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, pwreg); + + /* For STBC MCS 7 use value from STBC MCS 6 */ + pwreg = 0; + reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_4); + t = rt2x00_get_field32(reg, TX_PWR_CFG_4B_STBC_MCS6); + rt2x00_set_field32(&pwreg, TX_PWR_CFG_9B_STBC_MCS7, t); + rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, pwreg); + + rt2800_config_alc(rt2x00dev, chan, power_level); + + /* TODO: temperature compensation code! */ +} + /* * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values, @@ -4134,7 +4707,7 @@ static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev, } else { power_ctrl = 0; } - rt2800_bbp_read(rt2x00dev, 1, &r1); + r1 = rt2800_bbp_read(rt2x00dev, 1); rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl); rt2800_bbp_write(rt2x00dev, 1, r1); @@ -4145,11 +4718,12 @@ static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev, if (offset > TX_PWR_CFG_4) break; - rt2800_register_read(rt2x00dev, offset, ®); + reg = rt2800_register_read(rt2x00dev, offset); /* read the next four txpower values */ - rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, - i, &eeprom); + eeprom = rt2800_eeprom_read_from_array(rt2x00dev, + EEPROM_TXPOWER_BYRATE, + i); is_rate_b = i ? 0 : 1; /* @@ -4197,8 +4771,9 @@ static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev, rt2x00_set_field32(®, TX_PWR_CFG_RATE3, txpower); /* read the next four txpower values */ - rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, - i + 1, &eeprom); + eeprom = rt2800_eeprom_read_from_array(rt2x00dev, + EEPROM_TXPOWER_BYRATE, + i + 1); is_rate_b = 0; /* @@ -4258,6 +4833,8 @@ static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev, { if (rt2x00_rt(rt2x00dev, RT3593)) rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level); + else if (rt2x00_rt(rt2x00dev, RT6352)) + rt2800_config_txpower_rt6352(rt2x00dev, chan, power_level); else rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level); } @@ -4273,6 +4850,7 @@ void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev) { u32 tx_pin; u8 rfcsr; + unsigned long min_sleep = 0; /* * A voltage-controlled oscillator(VCO) is an electronic oscillator @@ -4282,7 +4860,7 @@ void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev) * periodically to adjust the frequency to be precision. */ - rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin); + tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG); tx_pin &= TX_PIN_CFG_PA_PE_DISABLE; rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); @@ -4293,30 +4871,44 @@ void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev) case RF3022: case RF3320: case RF3052: - rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 7); rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); break; case RF3053: case RF3070: case RF3290: + case RF5350: case RF5360: case RF5362: case RF5370: case RF5372: case RF5390: case RF5392: - rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr); + case RF5592: + rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); + min_sleep = 1000; + break; + case RF7620: + rt2800_rfcsr_write(rt2x00dev, 5, 0x40); + rt2800_rfcsr_write(rt2x00dev, 4, 0x0C); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 4); + rt2x00_set_field8(&rfcsr, RFCSR4_VCOCAL_EN, 1); + rt2800_rfcsr_write(rt2x00dev, 4, rfcsr); + min_sleep = 2000; break; default: + WARN_ONCE(1, "Not supported RF chipet %x for VCO recalibration", + rt2x00dev->chip.rf); return; } - mdelay(1); + if (min_sleep > 0) + usleep_range(min_sleep, min_sleep * 2); - rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin); + tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG); if (rt2x00dev->rf_channel <= 14) { switch (rt2x00dev->default_ant.tx_chain_num) { case 3: @@ -4346,6 +4938,42 @@ void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev) } rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); + if (rt2x00_rt(rt2x00dev, RT6352)) { + if (rt2x00dev->default_ant.rx_chain_num == 1) { + rt2800_bbp_write(rt2x00dev, 91, 0x07); + rt2800_bbp_write(rt2x00dev, 95, 0x1A); + rt2800_bbp_write(rt2x00dev, 195, 128); + rt2800_bbp_write(rt2x00dev, 196, 0xA0); + rt2800_bbp_write(rt2x00dev, 195, 170); + rt2800_bbp_write(rt2x00dev, 196, 0x12); + rt2800_bbp_write(rt2x00dev, 195, 171); + rt2800_bbp_write(rt2x00dev, 196, 0x10); + } else { + rt2800_bbp_write(rt2x00dev, 91, 0x06); + rt2800_bbp_write(rt2x00dev, 95, 0x9A); + rt2800_bbp_write(rt2x00dev, 195, 128); + rt2800_bbp_write(rt2x00dev, 196, 0xE0); + rt2800_bbp_write(rt2x00dev, 195, 170); + rt2800_bbp_write(rt2x00dev, 196, 0x30); + rt2800_bbp_write(rt2x00dev, 195, 171); + rt2800_bbp_write(rt2x00dev, 196, 0x30); + } + + if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) { + rt2800_bbp_write(rt2x00dev, 75, 0x68); + rt2800_bbp_write(rt2x00dev, 76, 0x4C); + rt2800_bbp_write(rt2x00dev, 79, 0x1C); + rt2800_bbp_write(rt2x00dev, 80, 0x0C); + rt2800_bbp_write(rt2x00dev, 82, 0xB6); + } + + /* On 11A, We should delay and wait RF/BBP to be stable + * and the appropriate time should be 1000 micro seconds + * 2005/06/05 - On 11G, we also need this delay time. + * Otherwise it's difficult to pass the WHQL. + */ + usleep_range(1000, 1500); + } } EXPORT_SYMBOL_GPL(rt2800_vco_calibration); @@ -4354,7 +4982,7 @@ static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev, { u32 reg; - rt2800_register_read(rt2x00dev, TX_RTY_CFG, ®); + reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG); rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, libconf->conf->short_frame_max_tx_count); rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, @@ -4373,7 +5001,7 @@ static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev, if (state == STATE_SLEEP) { rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0); - rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, ®); + reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG); rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5); rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, libconf->conf->listen_interval - 1); @@ -4382,7 +5010,7 @@ static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev, rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); } else { - rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, ®); + reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG); rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0); rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0); rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 0); @@ -4425,7 +5053,7 @@ void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual) /* * Update FCS error count from register. */ - rt2800_register_read(rt2x00dev, RX_STA_CNT0, ®); + reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0); qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR); } EXPORT_SYMBOL_GPL(rt2800_link_stats); @@ -4444,7 +5072,8 @@ static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev) rt2x00_rt(rt2x00dev, RT3593) || rt2x00_rt(rt2x00dev, RT5390) || rt2x00_rt(rt2x00dev, RT5392) || - rt2x00_rt(rt2x00dev, RT5592)) + rt2x00_rt(rt2x00dev, RT5592) || + rt2x00_rt(rt2x00dev, RT6352)) vgc = 0x1c + (2 * rt2x00dev->lna_gain); else vgc = 0x2e + rt2x00dev->lna_gain; @@ -4536,6 +5165,7 @@ EXPORT_SYMBOL_GPL(rt2800_link_tuner); */ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) { + struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; u32 reg; u16 eeprom; unsigned int i; @@ -4552,7 +5182,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000); - rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); + reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, 1600); rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 0); rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, 0); @@ -4563,43 +5193,43 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) rt2800_config_filter(rt2x00dev, FIF_ALLMULTI); - rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, ®); + reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG); rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, 9); rt2x00_set_field32(®, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2); rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); if (rt2x00_rt(rt2x00dev, RT3290)) { - rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, ®); + reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); if (rt2x00_get_field32(reg, WLAN_EN) == 1) { rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 1); rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); } - rt2800_register_read(rt2x00dev, CMB_CTRL, ®); + reg = rt2800_register_read(rt2x00dev, CMB_CTRL); if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) { rt2x00_set_field32(®, LDO0_EN, 1); rt2x00_set_field32(®, LDO_BGSEL, 3); rt2800_register_write(rt2x00dev, CMB_CTRL, reg); } - rt2800_register_read(rt2x00dev, OSC_CTRL, ®); + reg = rt2800_register_read(rt2x00dev, OSC_CTRL); rt2x00_set_field32(®, OSC_ROSC_EN, 1); rt2x00_set_field32(®, OSC_CAL_REQ, 1); rt2x00_set_field32(®, OSC_REF_CYCLE, 0x27); rt2800_register_write(rt2x00dev, OSC_CTRL, reg); - rt2800_register_read(rt2x00dev, COEX_CFG0, ®); + reg = rt2800_register_read(rt2x00dev, COEX_CFG0); rt2x00_set_field32(®, COEX_CFG_ANT, 0x5e); rt2800_register_write(rt2x00dev, COEX_CFG0, reg); - rt2800_register_read(rt2x00dev, COEX_CFG2, ®); + reg = rt2800_register_read(rt2x00dev, COEX_CFG2); rt2x00_set_field32(®, BT_COEX_CFG1, 0x00); rt2x00_set_field32(®, BT_COEX_CFG0, 0x17); rt2x00_set_field32(®, WL_COEX_CFG1, 0x93); rt2x00_set_field32(®, WL_COEX_CFG0, 0x7f); rt2800_register_write(rt2x00dev, COEX_CFG2, reg); - rt2800_register_read(rt2x00dev, PLL_CTRL, ®); + reg = rt2800_register_read(rt2x00dev, PLL_CTRL); rt2x00_set_field32(®, PLL_CONTROL, 1); rt2800_register_write(rt2x00dev, PLL_CTRL, reg); } @@ -4620,8 +5250,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) || rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) { - rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, - &eeprom); + eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST)) rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c); @@ -4656,8 +5285,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402); rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) { - rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, - &eeprom); + eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST)) rt2800_register_write(rt2x00dev, TX_SW_CFG2, @@ -4670,7 +5298,8 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) 0x00000000); } } else if (rt2x00_rt(rt2x00dev, RT5390) || - rt2x00_rt(rt2x00dev, RT5392)) { + rt2x00_rt(rt2x00dev, RT5392) || + rt2x00_rt(rt2x00dev, RT6352)) { rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); @@ -4678,12 +5307,32 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); + } else if (rt2x00_rt(rt2x00dev, RT5350)) { + rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); + } else if (rt2x00_rt(rt2x00dev, RT6352)) { + rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000401); + rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0000); + rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); + rt2800_register_write(rt2x00dev, MIMO_PS_CFG, 0x00000002); + rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x00150F0F); + rt2800_register_write(rt2x00dev, TX_ALC_VGA3, 0x06060606); + rt2800_register_write(rt2x00dev, TX0_BB_GAIN_ATTEN, 0x0); + rt2800_register_write(rt2x00dev, TX1_BB_GAIN_ATTEN, 0x0); + rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6C6C666C); + rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6C6C666C); + rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT, + 0x3630363A); + rt2800_register_write(rt2x00dev, TX1_RF_GAIN_CORRECT, + 0x3630363A); + reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1); + rt2x00_set_field32(®, TX_ALC_CFG_1_ROS_BUSY_EN, 0); + rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg); } else { rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000); rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); } - rt2800_register_read(rt2x00dev, TX_LINK_CFG, ®); + reg = rt2800_register_read(rt2x00dev, TX_LINK_CFG); rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32); rt2x00_set_field32(®, TX_LINK_CFG_MFB_ENABLE, 0); rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0); @@ -4694,25 +5343,29 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFS, 0); rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg); - rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, ®); + reg = rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG); rt2x00_set_field32(®, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9); rt2x00_set_field32(®, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32); rt2x00_set_field32(®, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10); rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg); - rt2800_register_read(rt2x00dev, MAX_LEN_CFG, ®); + reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG); rt2x00_set_field32(®, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE); - if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) || - rt2x00_rt(rt2x00dev, RT2883) || - rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E)) - rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, 2); - else - rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, 1); - rt2x00_set_field32(®, MAX_LEN_CFG_MIN_PSDU, 0); - rt2x00_set_field32(®, MAX_LEN_CFG_MIN_MPDU, 0); + if (rt2x00_is_usb(rt2x00dev)) { + drv_data->max_psdu = 3; + } else if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) || + rt2x00_rt(rt2x00dev, RT2883) || + rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E)) { + drv_data->max_psdu = 2; + } else { + drv_data->max_psdu = 1; + } + rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, drv_data->max_psdu); + rt2x00_set_field32(®, MAX_LEN_CFG_MIN_PSDU, 10); + rt2x00_set_field32(®, MAX_LEN_CFG_MIN_MPDU, 10); rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg); - rt2800_register_read(rt2x00dev, LED_CFG, ®); + reg = rt2800_register_read(rt2x00dev, LED_CFG); rt2x00_set_field32(®, LED_CFG_ON_PERIOD, 70); rt2x00_set_field32(®, LED_CFG_OFF_PERIOD, 30); rt2x00_set_field32(®, LED_CFG_SLOW_BLINK_PERIOD, 3); @@ -4724,16 +5377,16 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f); - rt2800_register_read(rt2x00dev, TX_RTY_CFG, ®); - rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, 15); - rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, 31); + reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG); + rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, 2); + rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, 2); rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_THRE, 2000); rt2x00_set_field32(®, TX_RTY_CFG_NON_AGG_RTY_MODE, 0); rt2x00_set_field32(®, TX_RTY_CFG_AGG_RTY_MODE, 0); rt2x00_set_field32(®, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1); rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg); - rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, ®); + reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG); rt2x00_set_field32(®, AUTO_RSP_CFG_AUTORESPONDER, 1); rt2x00_set_field32(®, AUTO_RSP_CFG_BAC_ACK_POLICY, 1); rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MMODE, 1); @@ -4743,7 +5396,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) rt2x00_set_field32(®, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0); rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); - rt2800_register_read(rt2x00dev, CCK_PROT_CFG, ®); + reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG); rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_RATE, 3); rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_CTRL, 0); rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1); @@ -4756,7 +5409,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, 1); rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); - rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®); + reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG); rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_RATE, 3); rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, 0); rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1); @@ -4769,7 +5422,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, 1); rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); - rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®); + reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG); rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, 0x4004); rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, 1); rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1); @@ -4782,7 +5435,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, 0); rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); - rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®); + reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG); rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, 0x4084); rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, 1); rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1); @@ -4795,7 +5448,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, 0); rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); - rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®); + reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG); rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, 0x4004); rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, 1); rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1); @@ -4808,7 +5461,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, 0); rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); - rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®); + reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG); rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, 0x4084); rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, 1); rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1); @@ -4824,7 +5477,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) if (rt2x00_is_usb(rt2x00dev)) { rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006); - rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); + reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); @@ -4841,7 +5494,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1 * although it is reserved. */ - rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, ®); + reg = rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG); rt2x00_set_field32(®, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1); rt2x00_set_field32(®, TXOP_CTRL_CFG_AC_TRUN_EN, 1); rt2x00_set_field32(®, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1); @@ -4857,11 +5510,11 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002; rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg); - rt2800_register_read(rt2x00dev, TX_RTS_CFG, ®); - rt2x00_set_field32(®, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32); + reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG); + rt2x00_set_field32(®, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 7); rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, IEEE80211_MAX_RTS_THRESHOLD); - rt2x00_set_field32(®, TX_RTS_CFG_RTS_FBK_EN, 0); + rt2x00_set_field32(®, TX_RTS_CFG_RTS_FBK_EN, 1); rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca); @@ -4873,7 +5526,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) * connection problems with 11g + CTS protection. Hence, use the same * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS. */ - rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, ®); + reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG); rt2x00_set_field32(®, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16); rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16); rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4); @@ -4903,16 +5556,16 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) rt2800_clear_beacon_register(rt2x00dev, i); if (rt2x00_is_usb(rt2x00dev)) { - rt2800_register_read(rt2x00dev, US_CYC_CNT, ®); + reg = rt2800_register_read(rt2x00dev, US_CYC_CNT); rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 30); rt2800_register_write(rt2x00dev, US_CYC_CNT, reg); } else if (rt2x00_is_pcie(rt2x00dev)) { - rt2800_register_read(rt2x00dev, US_CYC_CNT, ®); + reg = rt2800_register_read(rt2x00dev, US_CYC_CNT); rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 125); rt2800_register_write(rt2x00dev, US_CYC_CNT, reg); } - rt2800_register_read(rt2x00dev, HT_FBK_CFG0, ®); + reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG0); rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS0FBK, 0); rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS1FBK, 0); rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS2FBK, 1); @@ -4923,7 +5576,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS7FBK, 6); rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg); - rt2800_register_read(rt2x00dev, HT_FBK_CFG1, ®); + reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG1); rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS8FBK, 8); rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS9FBK, 8); rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS10FBK, 9); @@ -4934,7 +5587,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS15FBK, 14); rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg); - rt2800_register_read(rt2x00dev, LG_FBK_CFG0, ®); + reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG0); rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS0FBK, 8); rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS1FBK, 8); rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS2FBK, 9); @@ -4945,7 +5598,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS7FBK, 14); rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg); - rt2800_register_read(rt2x00dev, LG_FBK_CFG1, ®); + reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG1); rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS0FBK, 0); rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS1FBK, 0); rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS2FBK, 1); @@ -4955,7 +5608,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) /* * Do not force the BA window size, we use the TXWI to set it */ - rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, ®); + reg = rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE); rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0); rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0); rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg); @@ -4965,24 +5618,24 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) * These registers are cleared on read, * so we may pass a useless variable to store the value. */ - rt2800_register_read(rt2x00dev, RX_STA_CNT0, ®); - rt2800_register_read(rt2x00dev, RX_STA_CNT1, ®); - rt2800_register_read(rt2x00dev, RX_STA_CNT2, ®); - rt2800_register_read(rt2x00dev, TX_STA_CNT0, ®); - rt2800_register_read(rt2x00dev, TX_STA_CNT1, ®); - rt2800_register_read(rt2x00dev, TX_STA_CNT2, ®); + reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0); + reg = rt2800_register_read(rt2x00dev, RX_STA_CNT1); + reg = rt2800_register_read(rt2x00dev, RX_STA_CNT2); + reg = rt2800_register_read(rt2x00dev, TX_STA_CNT0); + reg = rt2800_register_read(rt2x00dev, TX_STA_CNT1); + reg = rt2800_register_read(rt2x00dev, TX_STA_CNT2); /* * Setup leadtime for pre tbtt interrupt to 6ms */ - rt2800_register_read(rt2x00dev, INT_TIMER_CFG, ®); + reg = rt2800_register_read(rt2x00dev, INT_TIMER_CFG); rt2x00_set_field32(®, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4); rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg); /* * Set up channel statistics timer */ - rt2800_register_read(rt2x00dev, CH_TIME_CFG, ®); + reg = rt2800_register_read(rt2x00dev, CH_TIME_CFG); rt2x00_set_field32(®, CH_TIME_CFG_EIFS_BUSY, 1); rt2x00_set_field32(®, CH_TIME_CFG_NAV_BUSY, 1); rt2x00_set_field32(®, CH_TIME_CFG_RX_BUSY, 1); @@ -4999,7 +5652,7 @@ static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev) u32 reg; for (i = 0; i < REGISTER_BUSY_COUNT; i++) { - rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, ®); + reg = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG); if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY)) return 0; @@ -5024,7 +5677,7 @@ static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev) msleep(1); for (i = 0; i < REGISTER_BUSY_COUNT; i++) { - rt2800_bbp_read(rt2x00dev, 0, &value); + value = rt2800_bbp_read(rt2x00dev, 0); if ((value != 0xff) && (value != 0x00)) return 0; udelay(REGISTER_BUSY_DELAY); @@ -5038,7 +5691,7 @@ static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev) { u8 value; - rt2800_bbp_read(rt2x00dev, 4, &value); + value = rt2800_bbp_read(rt2x00dev, 4); rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1); rt2800_bbp_write(rt2x00dev, 4, value); } @@ -5051,7 +5704,7 @@ static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev) static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev) { - const u8 glrt_table[] = { + static const u8 glrt_table[] = { 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */ 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */ 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */ @@ -5095,8 +5748,8 @@ static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev) u16 eeprom; u8 value; - rt2800_bbp_read(rt2x00dev, 138, &value); - rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom); + value = rt2800_bbp_read(rt2x00dev, 138); + eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1) value |= 0x20; if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1) @@ -5279,12 +5932,12 @@ static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev) rt2800_bbp_write(rt2x00dev, 155, 0x3b); rt2800_bbp_write(rt2x00dev, 253, 0x04); - rt2800_bbp_read(rt2x00dev, 47, &value); + value = rt2800_bbp_read(rt2x00dev, 47); rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1); rt2800_bbp_write(rt2x00dev, 47, value); /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */ - rt2800_bbp_read(rt2x00dev, 3, &value); + value = rt2800_bbp_read(rt2x00dev, 3); rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1); rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1); rt2800_bbp_write(rt2x00dev, 3, value); @@ -5319,9 +5972,13 @@ static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev) rt2800_bbp_write(rt2x00dev, 82, 0x62); - rt2800_bbp_write(rt2x00dev, 83, 0x6a); - - rt2800_bbp_write(rt2x00dev, 84, 0x99); + if (rt2x00_rt(rt2x00dev, RT5350)) { + rt2800_bbp_write(rt2x00dev, 83, 0x7a); + rt2800_bbp_write(rt2x00dev, 84, 0x9a); + } else { + rt2800_bbp_write(rt2x00dev, 83, 0x6a); + rt2800_bbp_write(rt2x00dev, 84, 0x99); + } rt2800_bbp_write(rt2x00dev, 86, 0x38); @@ -5335,9 +5992,13 @@ static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev) rt2800_bbp_write(rt2x00dev, 104, 0x92); - rt2800_bbp_write(rt2x00dev, 105, 0x34); - - rt2800_bbp_write(rt2x00dev, 106, 0x05); + if (rt2x00_rt(rt2x00dev, RT5350)) { + rt2800_bbp_write(rt2x00dev, 105, 0x3c); + rt2800_bbp_write(rt2x00dev, 106, 0x03); + } else { + rt2800_bbp_write(rt2x00dev, 105, 0x34); + rt2800_bbp_write(rt2x00dev, 106, 0x05); + } rt2800_bbp_write(rt2x00dev, 120, 0x50); @@ -5362,6 +6023,16 @@ static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev) rt2800_bbp_write(rt2x00dev, 143, 0xa2); rt2800_bbp_write(rt2x00dev, 148, 0xc8); + + if (rt2x00_rt(rt2x00dev, RT5350)) { + /* Antenna Software OFDM */ + rt2800_bbp_write(rt2x00dev, 150, 0x40); + /* Antenna Software CCK */ + rt2800_bbp_write(rt2x00dev, 151, 0x30); + rt2800_bbp_write(rt2x00dev, 152, 0xa3); + /* Clear previously selected antenna */ + rt2800_bbp_write(rt2x00dev, 154, 0); + } } static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev) @@ -5525,7 +6196,7 @@ static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev) rt2800_disable_unused_dac_adc(rt2x00dev); - rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom); + eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY); ant = (div_mode == 3) ? 1 : 0; @@ -5534,7 +6205,7 @@ static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev) if (rt2x00_has_cap_bt_coexist(rt2x00dev)) { u32 reg; - rt2800_register_read(rt2x00dev, GPIO_CTRL, ®); + reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0); rt2x00_set_field32(®, GPIO_CTRL_DIR6, 0); rt2x00_set_field32(®, GPIO_CTRL_VAL3, 0); @@ -5553,7 +6224,7 @@ static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev) rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */ } - rt2800_bbp_read(rt2x00dev, 152, &value); + value = rt2800_bbp_read(rt2x00dev, 152); if (ant == 0) rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1); else @@ -5571,7 +6242,7 @@ static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev) rt2800_init_bbp_early(rt2x00dev); - rt2800_bbp_read(rt2x00dev, 105, &value); + value = rt2800_bbp_read(rt2x00dev, 105); rt2x00_set_field8(&value, BBP105_MLD, rt2x00dev->default_ant.rx_chain_num == 2); rt2800_bbp_write(rt2x00dev, 105, value); @@ -5611,10 +6282,10 @@ static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev) rt2800_bbp4_mac_if_ctrl(rt2x00dev); - rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom); + eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY); ant = (div_mode == 3) ? 1 : 0; - rt2800_bbp_read(rt2x00dev, 152, &value); + value = rt2800_bbp_read(rt2x00dev, 152); if (ant == 0) { /* Main antenna */ rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1); @@ -5625,7 +6296,7 @@ static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev) rt2800_bbp_write(rt2x00dev, 152, value); if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) { - rt2800_bbp_read(rt2x00dev, 254, &value); + value = rt2800_bbp_read(rt2x00dev, 254); rt2x00_set_field8(&value, BBP254_BIT7, 1); rt2800_bbp_write(rt2x00dev, 254, value); } @@ -5637,6 +6308,230 @@ static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev) rt2800_bbp_write(rt2x00dev, 103, 0xc0); } +static void rt2800_bbp_glrt_write(struct rt2x00_dev *rt2x00dev, + const u8 reg, const u8 value) +{ + rt2800_bbp_write(rt2x00dev, 195, reg); + rt2800_bbp_write(rt2x00dev, 196, value); +} + +static void rt2800_bbp_dcoc_write(struct rt2x00_dev *rt2x00dev, + const u8 reg, const u8 value) +{ + rt2800_bbp_write(rt2x00dev, 158, reg); + rt2800_bbp_write(rt2x00dev, 159, value); +} + +static u8 rt2800_bbp_dcoc_read(struct rt2x00_dev *rt2x00dev, const u8 reg) +{ + rt2800_bbp_write(rt2x00dev, 158, reg); + return rt2800_bbp_read(rt2x00dev, 159); +} + +static void rt2800_init_bbp_6352(struct rt2x00_dev *rt2x00dev) +{ + u8 bbp; + + /* Apply Maximum Likelihood Detection (MLD) for 2 stream case */ + bbp = rt2800_bbp_read(rt2x00dev, 105); + rt2x00_set_field8(&bbp, BBP105_MLD, + rt2x00dev->default_ant.rx_chain_num == 2); + rt2800_bbp_write(rt2x00dev, 105, bbp); + + /* Avoid data loss and CRC errors */ + rt2800_bbp4_mac_if_ctrl(rt2x00dev); + + /* Fix I/Q swap issue */ + bbp = rt2800_bbp_read(rt2x00dev, 1); + bbp |= 0x04; + rt2800_bbp_write(rt2x00dev, 1, bbp); + + /* BBP for G band */ + rt2800_bbp_write(rt2x00dev, 3, 0x08); + rt2800_bbp_write(rt2x00dev, 4, 0x00); /* rt2800_bbp4_mac_if_ctrl? */ + rt2800_bbp_write(rt2x00dev, 6, 0x08); + rt2800_bbp_write(rt2x00dev, 14, 0x09); + rt2800_bbp_write(rt2x00dev, 15, 0xFF); + rt2800_bbp_write(rt2x00dev, 16, 0x01); + rt2800_bbp_write(rt2x00dev, 20, 0x06); + rt2800_bbp_write(rt2x00dev, 21, 0x00); + rt2800_bbp_write(rt2x00dev, 22, 0x00); + rt2800_bbp_write(rt2x00dev, 27, 0x00); + rt2800_bbp_write(rt2x00dev, 28, 0x00); + rt2800_bbp_write(rt2x00dev, 30, 0x00); + rt2800_bbp_write(rt2x00dev, 31, 0x48); + rt2800_bbp_write(rt2x00dev, 47, 0x40); + rt2800_bbp_write(rt2x00dev, 62, 0x00); + rt2800_bbp_write(rt2x00dev, 63, 0x00); + rt2800_bbp_write(rt2x00dev, 64, 0x00); + rt2800_bbp_write(rt2x00dev, 65, 0x2C); + rt2800_bbp_write(rt2x00dev, 66, 0x1C); + rt2800_bbp_write(rt2x00dev, 67, 0x20); + rt2800_bbp_write(rt2x00dev, 68, 0xDD); + rt2800_bbp_write(rt2x00dev, 69, 0x10); + rt2800_bbp_write(rt2x00dev, 70, 0x05); + rt2800_bbp_write(rt2x00dev, 73, 0x18); + rt2800_bbp_write(rt2x00dev, 74, 0x0F); + rt2800_bbp_write(rt2x00dev, 75, 0x60); + rt2800_bbp_write(rt2x00dev, 76, 0x44); + rt2800_bbp_write(rt2x00dev, 77, 0x59); + rt2800_bbp_write(rt2x00dev, 78, 0x1E); + rt2800_bbp_write(rt2x00dev, 79, 0x1C); + rt2800_bbp_write(rt2x00dev, 80, 0x0C); + rt2800_bbp_write(rt2x00dev, 81, 0x3A); + rt2800_bbp_write(rt2x00dev, 82, 0xB6); + rt2800_bbp_write(rt2x00dev, 83, 0x9A); + rt2800_bbp_write(rt2x00dev, 84, 0x9A); + rt2800_bbp_write(rt2x00dev, 86, 0x38); + rt2800_bbp_write(rt2x00dev, 88, 0x90); + rt2800_bbp_write(rt2x00dev, 91, 0x04); + rt2800_bbp_write(rt2x00dev, 92, 0x02); + rt2800_bbp_write(rt2x00dev, 95, 0x9A); + rt2800_bbp_write(rt2x00dev, 96, 0x00); + rt2800_bbp_write(rt2x00dev, 103, 0xC0); + rt2800_bbp_write(rt2x00dev, 104, 0x92); + /* FIXME BBP105 owerwrite */ + rt2800_bbp_write(rt2x00dev, 105, 0x3C); + rt2800_bbp_write(rt2x00dev, 106, 0x12); + rt2800_bbp_write(rt2x00dev, 109, 0x00); + rt2800_bbp_write(rt2x00dev, 134, 0x10); + rt2800_bbp_write(rt2x00dev, 135, 0xA6); + rt2800_bbp_write(rt2x00dev, 137, 0x04); + rt2800_bbp_write(rt2x00dev, 142, 0x30); + rt2800_bbp_write(rt2x00dev, 143, 0xF7); + rt2800_bbp_write(rt2x00dev, 160, 0xEC); + rt2800_bbp_write(rt2x00dev, 161, 0xC4); + rt2800_bbp_write(rt2x00dev, 162, 0x77); + rt2800_bbp_write(rt2x00dev, 163, 0xF9); + rt2800_bbp_write(rt2x00dev, 164, 0x00); + rt2800_bbp_write(rt2x00dev, 165, 0x00); + rt2800_bbp_write(rt2x00dev, 186, 0x00); + rt2800_bbp_write(rt2x00dev, 187, 0x00); + rt2800_bbp_write(rt2x00dev, 188, 0x00); + rt2800_bbp_write(rt2x00dev, 186, 0x00); + rt2800_bbp_write(rt2x00dev, 187, 0x01); + rt2800_bbp_write(rt2x00dev, 188, 0x00); + rt2800_bbp_write(rt2x00dev, 189, 0x00); + + rt2800_bbp_write(rt2x00dev, 91, 0x06); + rt2800_bbp_write(rt2x00dev, 92, 0x04); + rt2800_bbp_write(rt2x00dev, 93, 0x54); + rt2800_bbp_write(rt2x00dev, 99, 0x50); + rt2800_bbp_write(rt2x00dev, 148, 0x84); + rt2800_bbp_write(rt2x00dev, 167, 0x80); + rt2800_bbp_write(rt2x00dev, 178, 0xFF); + rt2800_bbp_write(rt2x00dev, 106, 0x13); + + /* BBP for G band GLRT function (BBP_128 ~ BBP_221) */ + rt2800_bbp_glrt_write(rt2x00dev, 0, 0x00); + rt2800_bbp_glrt_write(rt2x00dev, 1, 0x14); + rt2800_bbp_glrt_write(rt2x00dev, 2, 0x20); + rt2800_bbp_glrt_write(rt2x00dev, 3, 0x0A); + rt2800_bbp_glrt_write(rt2x00dev, 10, 0x16); + rt2800_bbp_glrt_write(rt2x00dev, 11, 0x06); + rt2800_bbp_glrt_write(rt2x00dev, 12, 0x02); + rt2800_bbp_glrt_write(rt2x00dev, 13, 0x07); + rt2800_bbp_glrt_write(rt2x00dev, 14, 0x05); + rt2800_bbp_glrt_write(rt2x00dev, 15, 0x09); + rt2800_bbp_glrt_write(rt2x00dev, 16, 0x20); + rt2800_bbp_glrt_write(rt2x00dev, 17, 0x08); + rt2800_bbp_glrt_write(rt2x00dev, 18, 0x4A); + rt2800_bbp_glrt_write(rt2x00dev, 19, 0x00); + rt2800_bbp_glrt_write(rt2x00dev, 20, 0x00); + rt2800_bbp_glrt_write(rt2x00dev, 128, 0xE0); + rt2800_bbp_glrt_write(rt2x00dev, 129, 0x1F); + rt2800_bbp_glrt_write(rt2x00dev, 130, 0x4F); + rt2800_bbp_glrt_write(rt2x00dev, 131, 0x32); + rt2800_bbp_glrt_write(rt2x00dev, 132, 0x08); + rt2800_bbp_glrt_write(rt2x00dev, 133, 0x28); + rt2800_bbp_glrt_write(rt2x00dev, 134, 0x19); + rt2800_bbp_glrt_write(rt2x00dev, 135, 0x0A); + rt2800_bbp_glrt_write(rt2x00dev, 138, 0x16); + rt2800_bbp_glrt_write(rt2x00dev, 139, 0x10); + rt2800_bbp_glrt_write(rt2x00dev, 140, 0x10); + rt2800_bbp_glrt_write(rt2x00dev, 141, 0x1A); + rt2800_bbp_glrt_write(rt2x00dev, 142, 0x36); + rt2800_bbp_glrt_write(rt2x00dev, 143, 0x2C); + rt2800_bbp_glrt_write(rt2x00dev, 144, 0x26); + rt2800_bbp_glrt_write(rt2x00dev, 145, 0x24); + rt2800_bbp_glrt_write(rt2x00dev, 146, 0x42); + rt2800_bbp_glrt_write(rt2x00dev, 147, 0x40); + rt2800_bbp_glrt_write(rt2x00dev, 148, 0x30); + rt2800_bbp_glrt_write(rt2x00dev, 149, 0x29); + rt2800_bbp_glrt_write(rt2x00dev, 150, 0x4C); + rt2800_bbp_glrt_write(rt2x00dev, 151, 0x46); + rt2800_bbp_glrt_write(rt2x00dev, 152, 0x3D); + rt2800_bbp_glrt_write(rt2x00dev, 153, 0x40); + rt2800_bbp_glrt_write(rt2x00dev, 154, 0x3E); + rt2800_bbp_glrt_write(rt2x00dev, 155, 0x38); + rt2800_bbp_glrt_write(rt2x00dev, 156, 0x3D); + rt2800_bbp_glrt_write(rt2x00dev, 157, 0x2F); + rt2800_bbp_glrt_write(rt2x00dev, 158, 0x3C); + rt2800_bbp_glrt_write(rt2x00dev, 159, 0x34); + rt2800_bbp_glrt_write(rt2x00dev, 160, 0x2C); + rt2800_bbp_glrt_write(rt2x00dev, 161, 0x2F); + rt2800_bbp_glrt_write(rt2x00dev, 162, 0x3C); + rt2800_bbp_glrt_write(rt2x00dev, 163, 0x35); + rt2800_bbp_glrt_write(rt2x00dev, 164, 0x2E); + rt2800_bbp_glrt_write(rt2x00dev, 165, 0x2F); + rt2800_bbp_glrt_write(rt2x00dev, 166, 0x49); + rt2800_bbp_glrt_write(rt2x00dev, 167, 0x41); + rt2800_bbp_glrt_write(rt2x00dev, 168, 0x36); + rt2800_bbp_glrt_write(rt2x00dev, 169, 0x39); + rt2800_bbp_glrt_write(rt2x00dev, 170, 0x30); + rt2800_bbp_glrt_write(rt2x00dev, 171, 0x30); + rt2800_bbp_glrt_write(rt2x00dev, 172, 0x0E); + rt2800_bbp_glrt_write(rt2x00dev, 173, 0x0D); + rt2800_bbp_glrt_write(rt2x00dev, 174, 0x28); + rt2800_bbp_glrt_write(rt2x00dev, 175, 0x21); + rt2800_bbp_glrt_write(rt2x00dev, 176, 0x1C); + rt2800_bbp_glrt_write(rt2x00dev, 177, 0x16); + rt2800_bbp_glrt_write(rt2x00dev, 178, 0x50); + rt2800_bbp_glrt_write(rt2x00dev, 179, 0x4A); + rt2800_bbp_glrt_write(rt2x00dev, 180, 0x43); + rt2800_bbp_glrt_write(rt2x00dev, 181, 0x50); + rt2800_bbp_glrt_write(rt2x00dev, 182, 0x10); + rt2800_bbp_glrt_write(rt2x00dev, 183, 0x10); + rt2800_bbp_glrt_write(rt2x00dev, 184, 0x10); + rt2800_bbp_glrt_write(rt2x00dev, 185, 0x10); + rt2800_bbp_glrt_write(rt2x00dev, 200, 0x7D); + rt2800_bbp_glrt_write(rt2x00dev, 201, 0x14); + rt2800_bbp_glrt_write(rt2x00dev, 202, 0x32); + rt2800_bbp_glrt_write(rt2x00dev, 203, 0x2C); + rt2800_bbp_glrt_write(rt2x00dev, 204, 0x36); + rt2800_bbp_glrt_write(rt2x00dev, 205, 0x4C); + rt2800_bbp_glrt_write(rt2x00dev, 206, 0x43); + rt2800_bbp_glrt_write(rt2x00dev, 207, 0x2C); + rt2800_bbp_glrt_write(rt2x00dev, 208, 0x2E); + rt2800_bbp_glrt_write(rt2x00dev, 209, 0x36); + rt2800_bbp_glrt_write(rt2x00dev, 210, 0x30); + rt2800_bbp_glrt_write(rt2x00dev, 211, 0x6E); + + /* BBP for G band DCOC function */ + rt2800_bbp_dcoc_write(rt2x00dev, 140, 0x0C); + rt2800_bbp_dcoc_write(rt2x00dev, 141, 0x00); + rt2800_bbp_dcoc_write(rt2x00dev, 142, 0x10); + rt2800_bbp_dcoc_write(rt2x00dev, 143, 0x10); + rt2800_bbp_dcoc_write(rt2x00dev, 144, 0x10); + rt2800_bbp_dcoc_write(rt2x00dev, 145, 0x10); + rt2800_bbp_dcoc_write(rt2x00dev, 146, 0x08); + rt2800_bbp_dcoc_write(rt2x00dev, 147, 0x40); + rt2800_bbp_dcoc_write(rt2x00dev, 148, 0x04); + rt2800_bbp_dcoc_write(rt2x00dev, 149, 0x04); + rt2800_bbp_dcoc_write(rt2x00dev, 150, 0x08); + rt2800_bbp_dcoc_write(rt2x00dev, 151, 0x08); + rt2800_bbp_dcoc_write(rt2x00dev, 152, 0x03); + rt2800_bbp_dcoc_write(rt2x00dev, 153, 0x03); + rt2800_bbp_dcoc_write(rt2x00dev, 154, 0x03); + rt2800_bbp_dcoc_write(rt2x00dev, 155, 0x02); + rt2800_bbp_dcoc_write(rt2x00dev, 156, 0x40); + rt2800_bbp_dcoc_write(rt2x00dev, 157, 0x40); + rt2800_bbp_dcoc_write(rt2x00dev, 158, 0x64); + rt2800_bbp_dcoc_write(rt2x00dev, 159, 0x64); + + rt2800_bbp4_mac_if_ctrl(rt2x00dev); +} + static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev) { unsigned int i; @@ -5662,6 +6557,7 @@ static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev) rt2800_init_bbp_3290(rt2x00dev); break; case RT3352: + case RT5350: rt2800_init_bbp_3352(rt2x00dev); break; case RT3390: @@ -5680,11 +6576,14 @@ static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev) case RT5592: rt2800_init_bbp_5592(rt2x00dev); return; + case RT6352: + rt2800_init_bbp_6352(rt2x00dev); + break; } for (i = 0; i < EEPROM_BBP_SIZE; i++) { - rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_BBP_START, i, - &eeprom); + eeprom = rt2800_eeprom_read_from_array(rt2x00dev, + EEPROM_BBP_START, i); if (eeprom != 0xffff && eeprom != 0x0000) { reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID); @@ -5698,7 +6597,7 @@ static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev) { u32 reg; - rt2800_register_read(rt2x00dev, OPT_14_CSR, ®); + reg = rt2800_register_read(rt2x00dev, OPT_14_CSR); rt2x00_set_field32(®, OPT_14_CSR_BIT0, 1); rt2800_register_write(rt2x00dev, OPT_14_CSR, reg); } @@ -5716,15 +6615,15 @@ static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40, rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); - rt2800_bbp_read(rt2x00dev, 4, &bbp); + bbp = rt2800_bbp_read(rt2x00dev, 4); rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40); rt2800_bbp_write(rt2x00dev, 4, bbp); - rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 31); rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40); rt2800_rfcsr_write(rt2x00dev, 31, rfcsr); - rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 22); rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1); rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); @@ -5737,7 +6636,7 @@ static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40, rt2800_bbp_write(rt2x00dev, 25, 0x90); msleep(1); - rt2800_bbp_read(rt2x00dev, 55, &passband); + passband = rt2800_bbp_read(rt2x00dev, 55); if (passband) break; } @@ -5751,7 +6650,7 @@ static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40, rt2800_bbp_write(rt2x00dev, 25, 0x90); msleep(1); - rt2800_bbp_read(rt2x00dev, 55, &stopband); + stopband = rt2800_bbp_read(rt2x00dev, 55); if ((passband - stopband) <= filter_target) { rfcsr24++; @@ -5773,7 +6672,7 @@ static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev, { u8 rfcsr; - rt2800_rfcsr_read(rt2x00dev, rf_reg, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, rf_reg); rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1); rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr); msleep(1); @@ -5807,22 +6706,22 @@ static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev) /* * Save BBP 25 & 26 values for later use in channel switching (for 3052) */ - rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25); - rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26); + drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25); + drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26); /* * Set back to initial state */ rt2800_bbp_write(rt2x00dev, 24, 0); - rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 22); rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0); rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); /* * Set BBP back to BW20 */ - rt2800_bbp_read(rt2x00dev, 4, &bbp); + bbp = rt2800_bbp_read(rt2x00dev, 4); rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0); rt2800_bbp_write(rt2x00dev, 4, bbp); } @@ -5833,7 +6732,7 @@ static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev) u8 min_gain, rfcsr, bbp; u16 eeprom; - rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 17); rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0); if (rt2x00_rt(rt2x00dev, RT3070) || @@ -5854,8 +6753,8 @@ static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev) if (rt2x00_rt(rt2x00dev, RT3090)) { /* Turn off unused DAC1 and ADC1 to reduce power consumption */ - rt2800_bbp_read(rt2x00dev, 138, &bbp); - rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom); + bbp = rt2800_bbp_read(rt2x00dev, 138); + eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1) rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0); if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1) @@ -5864,7 +6763,7 @@ static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev) } if (rt2x00_rt(rt2x00dev, RT3070)) { - rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 27); if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3); else @@ -5876,7 +6775,7 @@ static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev) } else if (rt2x00_rt(rt2x00dev, RT3071) || rt2x00_rt(rt2x00dev, RT3090) || rt2x00_rt(rt2x00dev, RT3390)) { - rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); @@ -5884,15 +6783,15 @@ static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev) rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); - rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 15); rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0); rt2800_rfcsr_write(rt2x00dev, 15, rfcsr); - rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 20); rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0); rt2800_rfcsr_write(rt2x00dev, 20, rfcsr); - rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 21); rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0); rt2800_rfcsr_write(rt2x00dev, 21, rfcsr); } @@ -5904,30 +6803,30 @@ static void rt2800_normal_mode_setup_3593(struct rt2x00_dev *rt2x00dev) u8 rfcsr; u8 tx_gain; - rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 50); rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO2_EN, 0); rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); - rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 51); tx_gain = rt2x00_get_field8(drv_data->txmixer_gain_24g, RFCSR17_TXMIXER_GAIN); rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, tx_gain); rt2800_rfcsr_write(rt2x00dev, 51, rfcsr); - rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 38); rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0); rt2800_rfcsr_write(rt2x00dev, 38, rfcsr); - rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 39); rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0); rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); - rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); - rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2); rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); @@ -5940,25 +6839,25 @@ static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev) u16 eeprom; /* Turn off unused DAC1 and ADC1 to reduce power consumption */ - rt2800_bbp_read(rt2x00dev, 138, ®); - rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom); + reg = rt2800_bbp_read(rt2x00dev, 138); + eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1) rt2x00_set_field8(®, BBP138_RX_ADC1, 0); if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1) rt2x00_set_field8(®, BBP138_TX_DAC1, 1); rt2800_bbp_write(rt2x00dev, 138, reg); - rt2800_rfcsr_read(rt2x00dev, 38, ®); + reg = rt2800_rfcsr_read(rt2x00dev, 38); rt2x00_set_field8(®, RFCSR38_RX_LO1_EN, 0); rt2800_rfcsr_write(rt2x00dev, 38, reg); - rt2800_rfcsr_read(rt2x00dev, 39, ®); + reg = rt2800_rfcsr_read(rt2x00dev, 39); rt2x00_set_field8(®, RFCSR39_RX_LO2_EN, 0); rt2800_rfcsr_write(rt2x00dev, 39, reg); rt2800_bbp4_mac_if_ctrl(rt2x00dev); - rt2800_rfcsr_read(rt2x00dev, 30, ®); + reg = rt2800_rfcsr_read(rt2x00dev, 30); rt2x00_set_field8(®, RFCSR30_RX_VCM, 2); rt2800_rfcsr_write(rt2x00dev, 30, reg); } @@ -6031,7 +6930,7 @@ static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev) rt2800_rfcsr_write(rt2x00dev, 29, 0x1f); if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) { - rt2800_register_read(rt2x00dev, LDO_CFG0, ®); + reg = rt2800_register_read(rt2x00dev, LDO_CFG0); rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); rt2800_register_write(rt2x00dev, LDO_CFG0, reg); @@ -6039,16 +6938,15 @@ static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev) rt2x00_rt(rt2x00dev, RT3090)) { rt2800_rfcsr_write(rt2x00dev, 31, 0x14); - rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1); rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); - rt2800_register_read(rt2x00dev, LDO_CFG0, ®); + reg = rt2800_register_read(rt2x00dev, LDO_CFG0); rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) { - rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, - &eeprom); + eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST)) rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); else @@ -6056,7 +6954,7 @@ static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev) } rt2800_register_write(rt2x00dev, LDO_CFG0, reg); - rt2800_register_read(rt2x00dev, GPIO_SWITCH, ®); + reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); rt2x00_set_field32(®, GPIO_SWITCH_5, 0); rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); } @@ -6125,7 +7023,7 @@ static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev) rt2800_rfcsr_write(rt2x00dev, 60, 0x45); rt2800_rfcsr_write(rt2x00dev, 61, 0xc1); - rt2800_rfcsr_read(rt2x00dev, 29, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 29); rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3); rt2800_rfcsr_write(rt2x00dev, 29, rfcsr); @@ -6135,6 +7033,12 @@ static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev) static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev) { + int tx0_ext_pa = test_bit(CAPABILITY_EXTERNAL_PA_TX0, + &rt2x00dev->cap_flags); + int tx1_ext_pa = test_bit(CAPABILITY_EXTERNAL_PA_TX1, + &rt2x00dev->cap_flags); + u8 rfcsr; + rt2800_rf_init_calibration(rt2x00dev, 30); rt2800_rfcsr_write(rt2x00dev, 0, 0xf0); @@ -6170,15 +7074,30 @@ static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev) rt2800_rfcsr_write(rt2x00dev, 31, 0x80); rt2800_rfcsr_write(rt2x00dev, 32, 0x80); rt2800_rfcsr_write(rt2x00dev, 33, 0x00); - rt2800_rfcsr_write(rt2x00dev, 34, 0x01); + rfcsr = 0x01; + if (tx0_ext_pa) + rt2x00_set_field8(&rfcsr, RFCSR34_TX0_EXT_PA, 1); + if (tx1_ext_pa) + rt2x00_set_field8(&rfcsr, RFCSR34_TX1_EXT_PA, 1); + rt2800_rfcsr_write(rt2x00dev, 34, rfcsr); rt2800_rfcsr_write(rt2x00dev, 35, 0x03); rt2800_rfcsr_write(rt2x00dev, 36, 0xbd); rt2800_rfcsr_write(rt2x00dev, 37, 0x3c); rt2800_rfcsr_write(rt2x00dev, 38, 0x5f); rt2800_rfcsr_write(rt2x00dev, 39, 0xc5); rt2800_rfcsr_write(rt2x00dev, 40, 0x33); - rt2800_rfcsr_write(rt2x00dev, 41, 0x5b); - rt2800_rfcsr_write(rt2x00dev, 42, 0x5b); + rfcsr = 0x52; + if (!tx0_ext_pa) { + rt2x00_set_field8(&rfcsr, RFCSR41_BIT1, 1); + rt2x00_set_field8(&rfcsr, RFCSR41_BIT4, 1); + } + rt2800_rfcsr_write(rt2x00dev, 41, rfcsr); + rfcsr = 0x52; + if (!tx1_ext_pa) { + rt2x00_set_field8(&rfcsr, RFCSR42_BIT1, 1); + rt2x00_set_field8(&rfcsr, RFCSR42_BIT4, 1); + } + rt2800_rfcsr_write(rt2x00dev, 42, rfcsr); rt2800_rfcsr_write(rt2x00dev, 43, 0xdb); rt2800_rfcsr_write(rt2x00dev, 44, 0xdb); rt2800_rfcsr_write(rt2x00dev, 45, 0xdb); @@ -6186,15 +7105,20 @@ static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev) rt2800_rfcsr_write(rt2x00dev, 47, 0x0d); rt2800_rfcsr_write(rt2x00dev, 48, 0x14); rt2800_rfcsr_write(rt2x00dev, 49, 0x00); - rt2800_rfcsr_write(rt2x00dev, 50, 0x2d); - rt2800_rfcsr_write(rt2x00dev, 51, 0x7f); - rt2800_rfcsr_write(rt2x00dev, 52, 0x00); - rt2800_rfcsr_write(rt2x00dev, 53, 0x52); - rt2800_rfcsr_write(rt2x00dev, 54, 0x1b); - rt2800_rfcsr_write(rt2x00dev, 55, 0x7f); - rt2800_rfcsr_write(rt2x00dev, 56, 0x00); - rt2800_rfcsr_write(rt2x00dev, 57, 0x52); - rt2800_rfcsr_write(rt2x00dev, 58, 0x1b); + rfcsr = 0x2d; + if (tx0_ext_pa) + rt2x00_set_field8(&rfcsr, RFCSR50_TX0_EXT_PA, 1); + if (tx1_ext_pa) + rt2x00_set_field8(&rfcsr, RFCSR50_TX1_EXT_PA, 1); + rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); + rt2800_rfcsr_write(rt2x00dev, 51, (tx0_ext_pa ? 0x52 : 0x7f)); + rt2800_rfcsr_write(rt2x00dev, 52, (tx0_ext_pa ? 0xc0 : 0x00)); + rt2800_rfcsr_write(rt2x00dev, 53, (tx0_ext_pa ? 0xd2 : 0x52)); + rt2800_rfcsr_write(rt2x00dev, 54, (tx0_ext_pa ? 0xc0 : 0x1b)); + rt2800_rfcsr_write(rt2x00dev, 55, (tx1_ext_pa ? 0x52 : 0x7f)); + rt2800_rfcsr_write(rt2x00dev, 56, (tx1_ext_pa ? 0xc0 : 0x00)); + rt2800_rfcsr_write(rt2x00dev, 57, (tx0_ext_pa ? 0x49 : 0x52)); + rt2800_rfcsr_write(rt2x00dev, 58, (tx1_ext_pa ? 0xc0 : 0x1b)); rt2800_rfcsr_write(rt2x00dev, 59, 0x00); rt2800_rfcsr_write(rt2x00dev, 60, 0x00); rt2800_rfcsr_write(rt2x00dev, 61, 0x00); @@ -6245,7 +7169,7 @@ static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev) rt2800_rfcsr_write(rt2x00dev, 30, 0x20); rt2800_rfcsr_write(rt2x00dev, 31, 0x0f); - rt2800_register_read(rt2x00dev, GPIO_SWITCH, ®); + reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); rt2x00_set_field32(®, GPIO_SWITCH_5, 0); rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); @@ -6297,16 +7221,16 @@ static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev) rt2800_rfcsr_write(rt2x00dev, 30, 0x09); rt2800_rfcsr_write(rt2x00dev, 31, 0x10); - rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1); rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); - rt2800_register_read(rt2x00dev, LDO_CFG0, ®); + reg = rt2800_register_read(rt2x00dev, LDO_CFG0); rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); rt2800_register_write(rt2x00dev, LDO_CFG0, reg); msleep(1); - rt2800_register_read(rt2x00dev, LDO_CFG0, ®); + reg = rt2800_register_read(rt2x00dev, LDO_CFG0); rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); rt2800_register_write(rt2x00dev, LDO_CFG0, reg); @@ -6321,7 +7245,7 @@ static void rt3593_post_bbp_init(struct rt2x00_dev *rt2x00dev) u8 bbp; bool txbf_enabled = false; /* FIXME */ - rt2800_bbp_read(rt2x00dev, 105, &bbp); + bbp = rt2800_bbp_read(rt2x00dev, 105); if (rt2x00dev->default_ant.rx_chain_num == 1) rt2x00_set_field8(&bbp, BBP105_MLD, 0); else @@ -6370,7 +7294,7 @@ static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev) u8 rfcsr; /* Disable GPIO #4 and #7 function for LAN PE control */ - rt2800_register_read(rt2x00dev, GPIO_SWITCH, ®); + reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); rt2x00_set_field32(®, GPIO_SWITCH_4, 0); rt2x00_set_field32(®, GPIO_SWITCH_7, 0); rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); @@ -6411,22 +7335,22 @@ static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev) /* Initiate calibration */ /* TODO: use rt2800_rf_init_calibration ? */ - rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 2); rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1); rt2800_rfcsr_write(rt2x00dev, 2, rfcsr); - rt2800_adjust_freq_offset(rt2x00dev); + rt2800_freq_cal_mode1(rt2x00dev); - rt2800_rfcsr_read(rt2x00dev, 18, &rfcsr); + rfcsr = rt2800_rfcsr_read(rt2x00dev, 18); rt2x00_set_field8(&rfcsr, RFCSR18_XO_TUNE_BYPASS, 1); rt2800_rfcsr_write(rt2x00dev, 18, rfcsr); - rt2800_register_read(rt2x00dev, LDO_CFG0, ®); + reg = rt2800_register_read(rt2x00dev, LDO_CFG0); rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); rt2800_register_write(rt2x00dev, LDO_CFG0, reg); usleep_range(1000, 1500); - rt2800_register_read(rt2x00dev, LDO_CFG0, ®); + reg = rt2800_register_read(rt2x00dev, LDO_CFG0); rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); rt2800_register_write(rt2x00dev, LDO_CFG0, reg); @@ -6435,8 +7359,8 @@ static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev) drv_data->calibration_bw40 = 0x2f; /* Save BBP 25 & 26 values for later use in channel switching */ - rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25); - rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26); + drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25); + drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26); rt2800_led_open_drain_enable(rt2x00dev); rt2800_normal_mode_setup_3593(rt2x00dev); @@ -6446,6 +7370,76 @@ static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev) /* TODO: enable stream mode support */ } +static void rt2800_init_rfcsr_5350(struct rt2x00_dev *rt2x00dev) +{ + rt2800_rfcsr_write(rt2x00dev, 0, 0xf0); + rt2800_rfcsr_write(rt2x00dev, 1, 0x23); + rt2800_rfcsr_write(rt2x00dev, 2, 0x50); + rt2800_rfcsr_write(rt2x00dev, 3, 0x08); + rt2800_rfcsr_write(rt2x00dev, 4, 0x49); + rt2800_rfcsr_write(rt2x00dev, 5, 0x10); + rt2800_rfcsr_write(rt2x00dev, 6, 0xe0); + rt2800_rfcsr_write(rt2x00dev, 7, 0x00); + rt2800_rfcsr_write(rt2x00dev, 8, 0xf1); + rt2800_rfcsr_write(rt2x00dev, 9, 0x02); + rt2800_rfcsr_write(rt2x00dev, 10, 0x53); + rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); + rt2800_rfcsr_write(rt2x00dev, 12, 0x46); + if (rt2800_clk_is_20mhz(rt2x00dev)) + rt2800_rfcsr_write(rt2x00dev, 13, 0x1f); + else + rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); + rt2800_rfcsr_write(rt2x00dev, 14, 0x00); + rt2800_rfcsr_write(rt2x00dev, 15, 0x00); + rt2800_rfcsr_write(rt2x00dev, 16, 0xc0); + rt2800_rfcsr_write(rt2x00dev, 18, 0x03); + rt2800_rfcsr_write(rt2x00dev, 19, 0x00); + rt2800_rfcsr_write(rt2x00dev, 20, 0x00); + rt2800_rfcsr_write(rt2x00dev, 21, 0x00); + rt2800_rfcsr_write(rt2x00dev, 22, 0x20); + rt2800_rfcsr_write(rt2x00dev, 23, 0x00); + rt2800_rfcsr_write(rt2x00dev, 24, 0x00); + rt2800_rfcsr_write(rt2x00dev, 25, 0x80); + rt2800_rfcsr_write(rt2x00dev, 26, 0x00); + rt2800_rfcsr_write(rt2x00dev, 27, 0x03); + rt2800_rfcsr_write(rt2x00dev, 28, 0x00); + rt2800_rfcsr_write(rt2x00dev, 29, 0xd0); + rt2800_rfcsr_write(rt2x00dev, 30, 0x10); + rt2800_rfcsr_write(rt2x00dev, 31, 0x80); + rt2800_rfcsr_write(rt2x00dev, 32, 0x80); + rt2800_rfcsr_write(rt2x00dev, 33, 0x00); + rt2800_rfcsr_write(rt2x00dev, 34, 0x07); + rt2800_rfcsr_write(rt2x00dev, 35, 0x12); + rt2800_rfcsr_write(rt2x00dev, 36, 0x00); + rt2800_rfcsr_write(rt2x00dev, 37, 0x08); + rt2800_rfcsr_write(rt2x00dev, 38, 0x85); + rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); + rt2800_rfcsr_write(rt2x00dev, 40, 0x0b); + rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); + rt2800_rfcsr_write(rt2x00dev, 42, 0xd5); + rt2800_rfcsr_write(rt2x00dev, 43, 0x9b); + rt2800_rfcsr_write(rt2x00dev, 44, 0x0c); + rt2800_rfcsr_write(rt2x00dev, 45, 0xa6); + rt2800_rfcsr_write(rt2x00dev, 46, 0x73); + rt2800_rfcsr_write(rt2x00dev, 47, 0x00); + rt2800_rfcsr_write(rt2x00dev, 48, 0x10); + rt2800_rfcsr_write(rt2x00dev, 49, 0x80); + rt2800_rfcsr_write(rt2x00dev, 50, 0x00); + rt2800_rfcsr_write(rt2x00dev, 51, 0x00); + rt2800_rfcsr_write(rt2x00dev, 52, 0x38); + rt2800_rfcsr_write(rt2x00dev, 53, 0x00); + rt2800_rfcsr_write(rt2x00dev, 54, 0x38); + rt2800_rfcsr_write(rt2x00dev, 55, 0x43); + rt2800_rfcsr_write(rt2x00dev, 56, 0x82); + rt2800_rfcsr_write(rt2x00dev, 57, 0x00); + rt2800_rfcsr_write(rt2x00dev, 58, 0x39); + rt2800_rfcsr_write(rt2x00dev, 59, 0x0b); + rt2800_rfcsr_write(rt2x00dev, 60, 0x45); + rt2800_rfcsr_write(rt2x00dev, 61, 0xd1); + rt2800_rfcsr_write(rt2x00dev, 62, 0x00); + rt2800_rfcsr_write(rt2x00dev, 63, 0x00); +} + static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev) { rt2800_rf_init_calibration(rt2x00dev, 2); @@ -6641,7 +7635,7 @@ static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev) rt2800_rfcsr_write(rt2x00dev, 2, 0x80); msleep(1); - rt2800_adjust_freq_offset(rt2x00dev); + rt2800_freq_cal_mode1(rt2x00dev); /* Enable DC filter */ if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) @@ -6655,6 +7649,617 @@ static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev) rt2800_led_open_drain_enable(rt2x00dev); } +static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev, + bool set_bw, bool is_ht40) +{ + u8 bbp_val; + + bbp_val = rt2800_bbp_read(rt2x00dev, 21); + bbp_val |= 0x1; + rt2800_bbp_write(rt2x00dev, 21, bbp_val); + usleep_range(100, 200); + + if (set_bw) { + bbp_val = rt2800_bbp_read(rt2x00dev, 4); + rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH, 2 * is_ht40); + rt2800_bbp_write(rt2x00dev, 4, bbp_val); + usleep_range(100, 200); + } + + bbp_val = rt2800_bbp_read(rt2x00dev, 21); + bbp_val &= (~0x1); + rt2800_bbp_write(rt2x00dev, 21, bbp_val); + usleep_range(100, 200); +} + +static int rt2800_rf_lp_config(struct rt2x00_dev *rt2x00dev, bool btxcal) +{ + u8 rf_val; + + if (btxcal) + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04); + else + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x02); + + rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x06); + + rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17); + rf_val |= 0x80; + rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, rf_val); + + if (btxcal) { + rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xC1); + rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x20); + rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02); + rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3); + rf_val &= (~0x3F); + rf_val |= 0x3F; + rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val); + rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4); + rf_val &= (~0x3F); + rf_val |= 0x3F; + rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val); + rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, 0x31); + } else { + rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xF1); + rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x18); + rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02); + rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3); + rf_val &= (~0x3F); + rf_val |= 0x34; + rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val); + rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4); + rf_val &= (~0x3F); + rf_val |= 0x34; + rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val); + } + + return 0; +} + +static char rt2800_lp_tx_filter_bw_cal(struct rt2x00_dev *rt2x00dev) +{ + unsigned int cnt; + u8 bbp_val; + char cal_val; + + rt2800_bbp_dcoc_write(rt2x00dev, 0, 0x82); + + cnt = 0; + do { + usleep_range(500, 2000); + bbp_val = rt2800_bbp_read(rt2x00dev, 159); + if (bbp_val == 0x02 || cnt == 20) + break; + + cnt++; + } while (cnt < 20); + + bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 0x39); + cal_val = bbp_val & 0x7F; + if (cal_val >= 0x40) + cal_val -= 128; + + return cal_val; +} + +static void rt2800_bw_filter_calibration(struct rt2x00_dev *rt2x00dev, + bool btxcal) +{ + struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; + u8 tx_agc_fc = 0, rx_agc_fc = 0, cmm_agc_fc; + u8 filter_target; + u8 tx_filter_target_20m = 0x09, tx_filter_target_40m = 0x02; + u8 rx_filter_target_20m = 0x27, rx_filter_target_40m = 0x31; + int loop = 0, is_ht40, cnt; + u8 bbp_val, rf_val; + char cal_r32_init, cal_r32_val, cal_diff; + u8 saverfb5r00, saverfb5r01, saverfb5r03, saverfb5r04, saverfb5r05; + u8 saverfb5r06, saverfb5r07; + u8 saverfb5r08, saverfb5r17, saverfb5r18, saverfb5r19, saverfb5r20; + u8 saverfb5r37, saverfb5r38, saverfb5r39, saverfb5r40, saverfb5r41; + u8 saverfb5r42, saverfb5r43, saverfb5r44, saverfb5r45, saverfb5r46; + u8 saverfb5r58, saverfb5r59; + u8 savebbp159r0, savebbp159r2, savebbpr23; + u32 MAC_RF_CONTROL0, MAC_RF_BYPASS0; + + /* Save MAC registers */ + MAC_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0); + MAC_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0); + + /* save BBP registers */ + savebbpr23 = rt2800_bbp_read(rt2x00dev, 23); + + savebbp159r0 = rt2800_bbp_dcoc_read(rt2x00dev, 0); + savebbp159r2 = rt2800_bbp_dcoc_read(rt2x00dev, 2); + + /* Save RF registers */ + saverfb5r00 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0); + saverfb5r01 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1); + saverfb5r03 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3); + saverfb5r04 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4); + saverfb5r05 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 5); + saverfb5r06 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6); + saverfb5r07 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7); + saverfb5r08 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8); + saverfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17); + saverfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18); + saverfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19); + saverfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20); + + saverfb5r37 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 37); + saverfb5r38 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 38); + saverfb5r39 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 39); + saverfb5r40 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 40); + saverfb5r41 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 41); + saverfb5r42 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 42); + saverfb5r43 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 43); + saverfb5r44 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 44); + saverfb5r45 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 45); + saverfb5r46 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 46); + + saverfb5r58 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58); + saverfb5r59 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59); + + rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0); + rf_val |= 0x3; + rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val); + + rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1); + rf_val |= 0x1; + rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, rf_val); + + cnt = 0; + do { + usleep_range(500, 2000); + rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1); + if (((rf_val & 0x1) == 0x00) || (cnt == 40)) + break; + cnt++; + } while (cnt < 40); + + rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0); + rf_val &= (~0x3); + rf_val |= 0x1; + rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val); + + /* I-3 */ + bbp_val = rt2800_bbp_read(rt2x00dev, 23); + bbp_val &= (~0x1F); + bbp_val |= 0x10; + rt2800_bbp_write(rt2x00dev, 23, bbp_val); + + do { + /* I-4,5,6,7,8,9 */ + if (loop == 0) { + is_ht40 = false; + + if (btxcal) + filter_target = tx_filter_target_20m; + else + filter_target = rx_filter_target_20m; + } else { + is_ht40 = true; + + if (btxcal) + filter_target = tx_filter_target_40m; + else + filter_target = rx_filter_target_40m; + } + + rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8); + rf_val &= (~0x04); + if (loop == 1) + rf_val |= 0x4; + + rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, rf_val); + + rt2800_bbp_core_soft_reset(rt2x00dev, true, is_ht40); + + rt2800_rf_lp_config(rt2x00dev, btxcal); + if (btxcal) { + tx_agc_fc = 0; + rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58); + rf_val &= (~0x7F); + rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val); + rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59); + rf_val &= (~0x7F); + rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val); + } else { + rx_agc_fc = 0; + rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6); + rf_val &= (~0x7F); + rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val); + rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7); + rf_val &= (~0x7F); + rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val); + } + + usleep_range(1000, 2000); + + bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 2); + bbp_val &= (~0x6); + rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val); + + rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40); + + cal_r32_init = rt2800_lp_tx_filter_bw_cal(rt2x00dev); + + bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 2); + bbp_val |= 0x6; + rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val); +do_cal: + if (btxcal) { + rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58); + rf_val &= (~0x7F); + rf_val |= tx_agc_fc; + rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val); + rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59); + rf_val &= (~0x7F); + rf_val |= tx_agc_fc; + rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val); + } else { + rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6); + rf_val &= (~0x7F); + rf_val |= rx_agc_fc; + rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val); + rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7); + rf_val &= (~0x7F); + rf_val |= rx_agc_fc; + rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val); + } + + usleep_range(500, 1000); + + rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40); + + cal_r32_val = rt2800_lp_tx_filter_bw_cal(rt2x00dev); + + cal_diff = cal_r32_init - cal_r32_val; + + if (btxcal) + cmm_agc_fc = tx_agc_fc; + else + cmm_agc_fc = rx_agc_fc; + + if (((cal_diff > filter_target) && (cmm_agc_fc == 0)) || + ((cal_diff < filter_target) && (cmm_agc_fc == 0x3f))) { + if (btxcal) + tx_agc_fc = 0; + else + rx_agc_fc = 0; + } else if ((cal_diff <= filter_target) && (cmm_agc_fc < 0x3f)) { + if (btxcal) + tx_agc_fc++; + else + rx_agc_fc++; + goto do_cal; + } + + if (btxcal) { + if (loop == 0) + drv_data->tx_calibration_bw20 = tx_agc_fc; + else + drv_data->tx_calibration_bw40 = tx_agc_fc; + } else { + if (loop == 0) + drv_data->rx_calibration_bw20 = rx_agc_fc; + else + drv_data->rx_calibration_bw40 = rx_agc_fc; + } + + loop++; + } while (loop <= 1); + + rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, saverfb5r00); + rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, saverfb5r01); + rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, saverfb5r03); + rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r04); + rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, saverfb5r05); + rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, saverfb5r06); + rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, saverfb5r07); + rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, saverfb5r08); + rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, saverfb5r17); + rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, saverfb5r18); + rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, saverfb5r19); + rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, saverfb5r20); + + rt2800_rfcsr_write_bank(rt2x00dev, 5, 37, saverfb5r37); + rt2800_rfcsr_write_bank(rt2x00dev, 5, 38, saverfb5r38); + rt2800_rfcsr_write_bank(rt2x00dev, 5, 39, saverfb5r39); + rt2800_rfcsr_write_bank(rt2x00dev, 5, 40, saverfb5r40); + rt2800_rfcsr_write_bank(rt2x00dev, 5, 41, saverfb5r41); + rt2800_rfcsr_write_bank(rt2x00dev, 5, 42, saverfb5r42); + rt2800_rfcsr_write_bank(rt2x00dev, 5, 43, saverfb5r43); + rt2800_rfcsr_write_bank(rt2x00dev, 5, 44, saverfb5r44); + rt2800_rfcsr_write_bank(rt2x00dev, 5, 45, saverfb5r45); + rt2800_rfcsr_write_bank(rt2x00dev, 5, 46, saverfb5r46); + + rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, saverfb5r58); + rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, saverfb5r59); + + rt2800_bbp_write(rt2x00dev, 23, savebbpr23); + + rt2800_bbp_dcoc_write(rt2x00dev, 0, savebbp159r0); + rt2800_bbp_dcoc_write(rt2x00dev, 2, savebbp159r2); + + bbp_val = rt2800_bbp_read(rt2x00dev, 4); + rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH, + 2 * test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)); + rt2800_bbp_write(rt2x00dev, 4, bbp_val); + + rt2800_register_write(rt2x00dev, RF_CONTROL0, MAC_RF_CONTROL0); + rt2800_register_write(rt2x00dev, RF_BYPASS0, MAC_RF_BYPASS0); +} + +static void rt2800_init_rfcsr_6352(struct rt2x00_dev *rt2x00dev) +{ + /* Initialize RF central register to default value */ + rt2800_rfcsr_write(rt2x00dev, 0, 0x02); + rt2800_rfcsr_write(rt2x00dev, 1, 0x03); + rt2800_rfcsr_write(rt2x00dev, 2, 0x33); + rt2800_rfcsr_write(rt2x00dev, 3, 0xFF); + rt2800_rfcsr_write(rt2x00dev, 4, 0x0C); + rt2800_rfcsr_write(rt2x00dev, 5, 0x40); + rt2800_rfcsr_write(rt2x00dev, 6, 0x00); + rt2800_rfcsr_write(rt2x00dev, 7, 0x00); + rt2800_rfcsr_write(rt2x00dev, 8, 0x00); + rt2800_rfcsr_write(rt2x00dev, 9, 0x00); + rt2800_rfcsr_write(rt2x00dev, 10, 0x00); + rt2800_rfcsr_write(rt2x00dev, 11, 0x00); + rt2800_rfcsr_write(rt2x00dev, 12, rt2x00dev->freq_offset); + rt2800_rfcsr_write(rt2x00dev, 13, 0x00); + rt2800_rfcsr_write(rt2x00dev, 14, 0x40); + rt2800_rfcsr_write(rt2x00dev, 15, 0x22); + rt2800_rfcsr_write(rt2x00dev, 16, 0x4C); + rt2800_rfcsr_write(rt2x00dev, 17, 0x00); + rt2800_rfcsr_write(rt2x00dev, 18, 0x00); + rt2800_rfcsr_write(rt2x00dev, 19, 0x00); + rt2800_rfcsr_write(rt2x00dev, 20, 0xA0); + rt2800_rfcsr_write(rt2x00dev, 21, 0x12); + rt2800_rfcsr_write(rt2x00dev, 22, 0x07); + rt2800_rfcsr_write(rt2x00dev, 23, 0x13); + rt2800_rfcsr_write(rt2x00dev, 24, 0xFE); + rt2800_rfcsr_write(rt2x00dev, 25, 0x24); + rt2800_rfcsr_write(rt2x00dev, 26, 0x7A); + rt2800_rfcsr_write(rt2x00dev, 27, 0x00); + rt2800_rfcsr_write(rt2x00dev, 28, 0x00); + rt2800_rfcsr_write(rt2x00dev, 29, 0x05); + rt2800_rfcsr_write(rt2x00dev, 30, 0x00); + rt2800_rfcsr_write(rt2x00dev, 31, 0x00); + rt2800_rfcsr_write(rt2x00dev, 32, 0x00); + rt2800_rfcsr_write(rt2x00dev, 33, 0x00); + rt2800_rfcsr_write(rt2x00dev, 34, 0x00); + rt2800_rfcsr_write(rt2x00dev, 35, 0x00); + rt2800_rfcsr_write(rt2x00dev, 36, 0x00); + rt2800_rfcsr_write(rt2x00dev, 37, 0x00); + rt2800_rfcsr_write(rt2x00dev, 38, 0x00); + rt2800_rfcsr_write(rt2x00dev, 39, 0x00); + rt2800_rfcsr_write(rt2x00dev, 40, 0x00); + rt2800_rfcsr_write(rt2x00dev, 41, 0xD0); + rt2800_rfcsr_write(rt2x00dev, 42, 0x5B); + rt2800_rfcsr_write(rt2x00dev, 43, 0x00); + + rt2800_rfcsr_write(rt2x00dev, 11, 0x21); + if (rt2800_clk_is_20mhz(rt2x00dev)) + rt2800_rfcsr_write(rt2x00dev, 13, 0x03); + else + rt2800_rfcsr_write(rt2x00dev, 13, 0x00); + rt2800_rfcsr_write(rt2x00dev, 14, 0x7C); + rt2800_rfcsr_write(rt2x00dev, 16, 0x80); + rt2800_rfcsr_write(rt2x00dev, 17, 0x99); + rt2800_rfcsr_write(rt2x00dev, 18, 0x99); + rt2800_rfcsr_write(rt2x00dev, 19, 0x09); + rt2800_rfcsr_write(rt2x00dev, 20, 0x50); + rt2800_rfcsr_write(rt2x00dev, 21, 0xB0); + rt2800_rfcsr_write(rt2x00dev, 22, 0x00); + rt2800_rfcsr_write(rt2x00dev, 23, 0x06); + rt2800_rfcsr_write(rt2x00dev, 24, 0x00); + rt2800_rfcsr_write(rt2x00dev, 25, 0x00); + rt2800_rfcsr_write(rt2x00dev, 26, 0x5D); + rt2800_rfcsr_write(rt2x00dev, 27, 0x00); + rt2800_rfcsr_write(rt2x00dev, 28, 0x61); + rt2800_rfcsr_write(rt2x00dev, 29, 0xB5); + rt2800_rfcsr_write(rt2x00dev, 43, 0x02); + + rt2800_rfcsr_write(rt2x00dev, 28, 0x62); + rt2800_rfcsr_write(rt2x00dev, 29, 0xAD); + rt2800_rfcsr_write(rt2x00dev, 39, 0x80); + + /* Initialize RF channel register to default value */ + rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x03); + rt2800_rfcsr_write_chanreg(rt2x00dev, 1, 0x00); + rt2800_rfcsr_write_chanreg(rt2x00dev, 2, 0x00); + rt2800_rfcsr_write_chanreg(rt2x00dev, 3, 0x00); + rt2800_rfcsr_write_chanreg(rt2x00dev, 4, 0x00); + rt2800_rfcsr_write_chanreg(rt2x00dev, 5, 0x08); + rt2800_rfcsr_write_chanreg(rt2x00dev, 6, 0x00); + rt2800_rfcsr_write_chanreg(rt2x00dev, 7, 0x51); + rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x53); + rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x16); + rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x61); + rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53); + rt2800_rfcsr_write_chanreg(rt2x00dev, 12, 0x22); + rt2800_rfcsr_write_chanreg(rt2x00dev, 13, 0x3D); + rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06); + rt2800_rfcsr_write_chanreg(rt2x00dev, 15, 0x13); + rt2800_rfcsr_write_chanreg(rt2x00dev, 16, 0x22); + rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x27); + rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x02); + rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7); + rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x01); + rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x52); + rt2800_rfcsr_write_chanreg(rt2x00dev, 22, 0x80); + rt2800_rfcsr_write_chanreg(rt2x00dev, 23, 0xB3); + rt2800_rfcsr_write_chanreg(rt2x00dev, 24, 0x00); + rt2800_rfcsr_write_chanreg(rt2x00dev, 25, 0x00); + rt2800_rfcsr_write_chanreg(rt2x00dev, 26, 0x00); + rt2800_rfcsr_write_chanreg(rt2x00dev, 27, 0x00); + rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x5C); + rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0x6B); + rt2800_rfcsr_write_chanreg(rt2x00dev, 30, 0x6B); + rt2800_rfcsr_write_chanreg(rt2x00dev, 31, 0x31); + rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x5D); + rt2800_rfcsr_write_chanreg(rt2x00dev, 33, 0x00); + rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xE6); + rt2800_rfcsr_write_chanreg(rt2x00dev, 35, 0x55); + rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x00); + rt2800_rfcsr_write_chanreg(rt2x00dev, 37, 0xBB); + rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB3); + rt2800_rfcsr_write_chanreg(rt2x00dev, 39, 0xB3); + rt2800_rfcsr_write_chanreg(rt2x00dev, 40, 0x03); + rt2800_rfcsr_write_chanreg(rt2x00dev, 41, 0x00); + rt2800_rfcsr_write_chanreg(rt2x00dev, 42, 0x00); + rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xB3); + rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xD3); + rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5); + rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x07); + rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x68); + rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xEF); + rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1C); + rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x07); + rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xA8); + rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0x85); + rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x10); + rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x07); + rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6A); + rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0x85); + rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x10); + rt2800_rfcsr_write_chanreg(rt2x00dev, 62, 0x1C); + rt2800_rfcsr_write_chanreg(rt2x00dev, 63, 0x00); + + rt2800_rfcsr_write_bank(rt2x00dev, 6, 45, 0xC5); + + rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47); + rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71); + rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x33); + rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x0E); + rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23); + rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA4); + rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x02); + rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x12); + rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x1C); + rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0xEB); + rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x7D); + rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xD6); + rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x08); + rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB4); + rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3); + rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3); + rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5); + rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27); + rt2800_rfcsr_write_bank(rt2x00dev, 4, 47, 0x67); + rt2800_rfcsr_write_bank(rt2x00dev, 6, 47, 0x69); + rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFF); + rt2800_rfcsr_write_bank(rt2x00dev, 4, 54, 0x27); + rt2800_rfcsr_write_bank(rt2x00dev, 6, 54, 0x20); + rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66); + rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF); + rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C); + rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20); + rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B); + rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7); + rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09); + + rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51); + rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06); + rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7); + rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C); + rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64); + rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51); + rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36); + rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53); + rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16); + + rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C); + rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC); + rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F); + rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27); + rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66); + rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B); + + /* Initialize RF channel register for DRQFN */ + rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3); + rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3); + rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5); + rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28); + rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68); + rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7); + rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02); + rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7); + + /* Initialize RF DC calibration register to default value */ + rt2800_rfcsr_write_dccal(rt2x00dev, 0, 0x47); + rt2800_rfcsr_write_dccal(rt2x00dev, 1, 0x00); + rt2800_rfcsr_write_dccal(rt2x00dev, 2, 0x00); + rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x00); + rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x00); + rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00); + rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10); + rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10); + rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04); + rt2800_rfcsr_write_dccal(rt2x00dev, 9, 0x00); + rt2800_rfcsr_write_dccal(rt2x00dev, 10, 0x07); + rt2800_rfcsr_write_dccal(rt2x00dev, 11, 0x01); + rt2800_rfcsr_write_dccal(rt2x00dev, 12, 0x07); + rt2800_rfcsr_write_dccal(rt2x00dev, 13, 0x07); + rt2800_rfcsr_write_dccal(rt2x00dev, 14, 0x07); + rt2800_rfcsr_write_dccal(rt2x00dev, 15, 0x20); + rt2800_rfcsr_write_dccal(rt2x00dev, 16, 0x22); + rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x00); + rt2800_rfcsr_write_dccal(rt2x00dev, 18, 0x00); + rt2800_rfcsr_write_dccal(rt2x00dev, 19, 0x00); + rt2800_rfcsr_write_dccal(rt2x00dev, 20, 0x00); + rt2800_rfcsr_write_dccal(rt2x00dev, 21, 0xF1); + rt2800_rfcsr_write_dccal(rt2x00dev, 22, 0x11); + rt2800_rfcsr_write_dccal(rt2x00dev, 23, 0x02); + rt2800_rfcsr_write_dccal(rt2x00dev, 24, 0x41); + rt2800_rfcsr_write_dccal(rt2x00dev, 25, 0x20); + rt2800_rfcsr_write_dccal(rt2x00dev, 26, 0x00); + rt2800_rfcsr_write_dccal(rt2x00dev, 27, 0xD7); + rt2800_rfcsr_write_dccal(rt2x00dev, 28, 0xA2); + rt2800_rfcsr_write_dccal(rt2x00dev, 29, 0x20); + rt2800_rfcsr_write_dccal(rt2x00dev, 30, 0x49); + rt2800_rfcsr_write_dccal(rt2x00dev, 31, 0x20); + rt2800_rfcsr_write_dccal(rt2x00dev, 32, 0x04); + rt2800_rfcsr_write_dccal(rt2x00dev, 33, 0xF1); + rt2800_rfcsr_write_dccal(rt2x00dev, 34, 0xA1); + rt2800_rfcsr_write_dccal(rt2x00dev, 35, 0x01); + rt2800_rfcsr_write_dccal(rt2x00dev, 41, 0x00); + rt2800_rfcsr_write_dccal(rt2x00dev, 42, 0x00); + rt2800_rfcsr_write_dccal(rt2x00dev, 43, 0x00); + rt2800_rfcsr_write_dccal(rt2x00dev, 44, 0x00); + rt2800_rfcsr_write_dccal(rt2x00dev, 45, 0x00); + rt2800_rfcsr_write_dccal(rt2x00dev, 46, 0x00); + rt2800_rfcsr_write_dccal(rt2x00dev, 47, 0x3E); + rt2800_rfcsr_write_dccal(rt2x00dev, 48, 0x3D); + rt2800_rfcsr_write_dccal(rt2x00dev, 49, 0x3E); + rt2800_rfcsr_write_dccal(rt2x00dev, 50, 0x3D); + rt2800_rfcsr_write_dccal(rt2x00dev, 51, 0x3E); + rt2800_rfcsr_write_dccal(rt2x00dev, 52, 0x3D); + rt2800_rfcsr_write_dccal(rt2x00dev, 53, 0x00); + rt2800_rfcsr_write_dccal(rt2x00dev, 54, 0x00); + rt2800_rfcsr_write_dccal(rt2x00dev, 55, 0x00); + rt2800_rfcsr_write_dccal(rt2x00dev, 56, 0x00); + rt2800_rfcsr_write_dccal(rt2x00dev, 57, 0x00); + rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10); + rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10); + rt2800_rfcsr_write_dccal(rt2x00dev, 60, 0x0A); + rt2800_rfcsr_write_dccal(rt2x00dev, 61, 0x00); + rt2800_rfcsr_write_dccal(rt2x00dev, 62, 0x00); + rt2800_rfcsr_write_dccal(rt2x00dev, 63, 0x00); + + rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x08); + rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x04); + rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x20); + + rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00); + rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C); + + rt2800_bw_filter_calibration(rt2x00dev, true); + rt2800_bw_filter_calibration(rt2x00dev, false); +} + static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev) { if (rt2800_is_305x_soc(rt2x00dev)) { @@ -6683,6 +8288,9 @@ static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev) case RT3593: rt2800_init_rfcsr_3593(rt2x00dev); break; + case RT5350: + rt2800_init_rfcsr_5350(rt2x00dev); + break; case RT5390: rt2800_init_rfcsr_5390(rt2x00dev); break; @@ -6692,6 +8300,9 @@ static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev) case RT5592: rt2800_init_rfcsr_5592(rt2x00dev); break; + case RT6352: + rt2800_init_rfcsr_6352(rt2x00dev); + break; } } @@ -6747,20 +8358,20 @@ int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev) /* * Enable RX. */ - rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®); + reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1); rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); udelay(50); - rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); + reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1); rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1); rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); - rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®); + reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1); rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 1); rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); @@ -6768,15 +8379,15 @@ int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev) /* * Initialize LED control */ - rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word); + word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF); rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff, word & 0xff, (word >> 8) & 0xff); - rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word); + word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF); rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff, word & 0xff, (word >> 8) & 0xff); - rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word); + word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY); rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff, word & 0xff, (word >> 8) & 0xff); @@ -6793,7 +8404,7 @@ void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev) /* Wait for DMA, ignore error */ rt2800_wait_wpdma_ready(rt2x00dev); - rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®); + reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 0); rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); @@ -6810,7 +8421,7 @@ int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev) else efuse_ctrl_reg = EFUSE_CTRL; - rt2800_register_read(rt2x00dev, efuse_ctrl_reg, ®); + reg = rt2800_register_read(rt2x00dev, efuse_ctrl_reg); return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT); } EXPORT_SYMBOL_GPL(rt2800_efuse_detect); @@ -6839,7 +8450,7 @@ static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i) } mutex_lock(&rt2x00dev->csr_mutex); - rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg, ®); + reg = rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg); rt2x00_set_field32(®, EFUSE_CTRL_ADDRESS_IN, i); rt2x00_set_field32(®, EFUSE_CTRL_MODE, 0); rt2x00_set_field32(®, EFUSE_CTRL_KICK, 1); @@ -6848,14 +8459,14 @@ static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i) /* Wait until the EEPROM has been loaded */ rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, ®); /* Apparently the data is read from end to start */ - rt2800_register_read_lock(rt2x00dev, efuse_data3_reg, ®); + reg = rt2800_register_read_lock(rt2x00dev, efuse_data3_reg); /* The returned value is in CPU order, but eeprom is le */ *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg); - rt2800_register_read_lock(rt2x00dev, efuse_data2_reg, ®); + reg = rt2800_register_read_lock(rt2x00dev, efuse_data2_reg); *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg); - rt2800_register_read_lock(rt2x00dev, efuse_data1_reg, ®); + reg = rt2800_register_read_lock(rt2x00dev, efuse_data1_reg); *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg); - rt2800_register_read_lock(rt2x00dev, efuse_data0_reg, ®); + reg = rt2800_register_read_lock(rt2x00dev, efuse_data0_reg); *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg); mutex_unlock(&rt2x00dev->csr_mutex); @@ -6879,7 +8490,7 @@ static u8 rt2800_get_txmixer_gain_24g(struct rt2x00_dev *rt2x00dev) if (rt2x00_rt(rt2x00dev, RT3593)) return 0; - rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &word); + word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG); if ((word & 0x00ff) != 0x00ff) return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL); @@ -6893,7 +8504,7 @@ static u8 rt2800_get_txmixer_gain_5g(struct rt2x00_dev *rt2x00dev) if (rt2x00_rt(rt2x00dev, RT3593)) return 0; - rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A, &word); + word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A); if ((word & 0x00ff) != 0x00ff) return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL); @@ -6921,7 +8532,7 @@ static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev) mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0); rt2x00lib_set_mac_address(rt2x00dev, mac); - rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word); + word = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); if (word == 0xffff) { rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2); rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1); @@ -6938,7 +8549,7 @@ static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev) rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word); } - rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word); + word = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); if (word == 0xffff) { rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0); rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0); @@ -6959,7 +8570,7 @@ static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev) rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word); } - rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &word); + word = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ); if ((word & 0x00ff) == 0x00ff) { rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0); rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word); @@ -6981,10 +8592,10 @@ static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev) * lna0 as correct value. Note that EEPROM_LNA * is never validated. */ - rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &word); + word = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA); default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0); - rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word); + word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG); if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10) rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0); if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10) @@ -6993,7 +8604,7 @@ static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev) drv_data->txmixer_gain_24g = rt2800_get_txmixer_gain_24g(rt2x00dev); - rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word); + word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2); if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10) rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0); if (!rt2x00_rt(rt2x00dev, RT3593)) { @@ -7006,14 +8617,14 @@ static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev) drv_data->txmixer_gain_5g = rt2800_get_txmixer_gain_5g(rt2x00dev); - rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word); + word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A); if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10) rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0); if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10) rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0); rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word); - rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word); + word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2); if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10) rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0); if (!rt2x00_rt(rt2x00dev, RT3593)) { @@ -7025,7 +8636,7 @@ static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev) rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word); if (rt2x00_rt(rt2x00dev, RT3593)) { - rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &word); + word = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2); if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0x00 || rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0xff) rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1, @@ -7049,7 +8660,7 @@ static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev) /* * Read EEPROM word for configuration. */ - rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom); + eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); /* * Identify RF chipset by EEPROM value @@ -7058,8 +8669,13 @@ static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev) */ if (rt2x00_rt(rt2x00dev, RT3290) || rt2x00_rt(rt2x00dev, RT5390) || - rt2x00_rt(rt2x00dev, RT5392)) - rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &rf); + rt2x00_rt(rt2x00dev, RT5392) || + rt2x00_rt(rt2x00dev, RT6352)) + rf = rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID); + else if (rt2x00_rt(rt2x00dev, RT3352)) + rf = RF3322; + else if (rt2x00_rt(rt2x00dev, RT5350)) + rf = RF5350; else rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE); @@ -7078,6 +8694,7 @@ static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev) case RF3290: case RF3320: case RF3322: + case RF5350: case RF5360: case RF5362: case RF5370: @@ -7085,6 +8702,7 @@ static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev) case RF5390: case RF5392: case RF5592: + case RF7620: break; default: rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n", @@ -7102,7 +8720,7 @@ static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev) rt2x00dev->default_ant.rx_chain_num = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH); - rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom); + eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); if (rt2x00_rt(rt2x00dev, RT3070) || rt2x00_rt(rt2x00dev, RT3090) || @@ -7149,13 +8767,14 @@ static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev) /* * Detect if this device has Bluetooth co-existence. */ - if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST)) + if (!rt2x00_rt(rt2x00dev, RT3352) && + rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST)) __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags); /* * Read frequency offset and RF programming sequence. */ - rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom); + eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ); rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET); /* @@ -7172,12 +8791,28 @@ static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev) /* * Check if support EIRP tx power limit feature. */ - rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom); + eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER); if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) < EIRP_MAX_TX_POWER_LIMIT) __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags); + /* + * Detect if device uses internal or external PA + */ + eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); + + if (rt2x00_rt(rt2x00dev, RT3352)) { + if (rt2x00_get_field16(eeprom, + EEPROM_NIC_CONF1_EXTERNAL_TX0_PA_3352)) + __set_bit(CAPABILITY_EXTERNAL_PA_TX0, + &rt2x00dev->cap_flags); + if (rt2x00_get_field16(eeprom, + EEPROM_NIC_CONF1_EXTERNAL_TX1_PA_3352)) + __set_bit(CAPABILITY_EXTERNAL_PA_TX1, + &rt2x00dev->cap_flags); + } + return 0; } @@ -7322,6 +8957,27 @@ static const struct rf_channel rf_vals_3x[] = { {173, 0x61, 0, 9}, }; +/* + * RF value list for rt3xxx with Xtal20MHz + * Supports: 2.4 GHz (all) (RF3322) + */ +static const struct rf_channel rf_vals_3x_xtal20[] = { + {1, 0xE2, 2, 0x14}, + {2, 0xE3, 2, 0x14}, + {3, 0xE4, 2, 0x14}, + {4, 0xE5, 2, 0x14}, + {5, 0xE6, 2, 0x14}, + {6, 0xE7, 2, 0x14}, + {7, 0xE8, 2, 0x14}, + {8, 0xE9, 2, 0x14}, + {9, 0xEA, 2, 0x14}, + {10, 0xEB, 2, 0x14}, + {11, 0xEC, 2, 0x14}, + {12, 0xED, 2, 0x14}, + {13, 0xEE, 2, 0x14}, + {14, 0xF0, 2, 0x18}, +}; + static const struct rf_channel rf_vals_5592_xtal20[] = { /* Channel, N, K, mod, R */ {1, 482, 4, 10, 3}, @@ -7454,6 +9110,23 @@ static const struct rf_channel rf_vals_5592_xtal40[] = { {196, 83, 0, 12, 1}, }; +static const struct rf_channel rf_vals_7620[] = { + {1, 0x50, 0x99, 0x99, 1}, + {2, 0x50, 0x44, 0x44, 2}, + {3, 0x50, 0xEE, 0xEE, 2}, + {4, 0x50, 0x99, 0x99, 3}, + {5, 0x51, 0x44, 0x44, 0}, + {6, 0x51, 0xEE, 0xEE, 0}, + {7, 0x51, 0x99, 0x99, 1}, + {8, 0x51, 0x44, 0x44, 2}, + {9, 0x51, 0xEE, 0xEE, 2}, + {10, 0x51, 0x99, 0x99, 3}, + {11, 0x52, 0x44, 0x44, 0}, + {12, 0x52, 0xEE, 0xEE, 0}, + {13, 0x52, 0x99, 0x99, 1}, + {14, 0x52, 0x33, 0x33, 3}, +}; + static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev) { struct hw_mode_spec *spec = &rt2x00dev->spec; @@ -7470,6 +9143,13 @@ static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev) rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; /* + * Change default retry settings to values corresponding more closely + * to rate[0].count setting of minstrel rate control algorithm. + */ + rt2x00dev->hw->wiphy->retry_short = 2; + rt2x00dev->hw->wiphy->retry_long = 2; + + /* * Initialize all hw fields. */ ieee80211_hw_set(rt2x00dev->hw, REPORTS_TX_ACK_STATUS); @@ -7536,6 +9216,7 @@ static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev) case RF3290: case RF3320: case RF3322: + case RF5350: case RF5360: case RF5362: case RF5370: @@ -7543,7 +9224,15 @@ static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev) case RF5390: case RF5392: spec->num_channels = 14; - spec->channels = rf_vals_3x; + if (rt2800_clk_is_20mhz(rt2x00dev)) + spec->channels = rf_vals_3x_xtal20; + else + spec->channels = rf_vals_3x; + break; + + case RF7620: + spec->num_channels = ARRAY_SIZE(rf_vals_7620); + spec->channels = rf_vals_7620; break; case RF3052: @@ -7553,7 +9242,7 @@ static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev) break; case RF5592: - rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX, ®); + reg = rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX); if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) { spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40); spec->channels = rf_vals_5592_xtal40; @@ -7593,7 +9282,7 @@ static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev) spec->ht.cap |= rx_chains << IEEE80211_HT_CAP_RX_STBC_SHIFT; - spec->ht.ampdu_factor = 3; + spec->ht.ampdu_factor = (rx_chains > 1) ? 3 : 2; spec->ht.ampdu_density = 4; spec->ht.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; if (tx_chains != rx_chains) { @@ -7669,12 +9358,15 @@ static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev) case RF3053: case RF3070: case RF3290: + case RF5350: case RF5360: case RF5362: case RF5370: case RF5372: case RF5390: case RF5392: + case RF5592: + case RF7620: __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags); break; } @@ -7689,9 +9381,9 @@ static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev) u32 rev; if (rt2x00_rt(rt2x00dev, RT3290)) - rt2800_register_read(rt2x00dev, MAC_CSR0_3290, ®); + reg = rt2800_register_read(rt2x00dev, MAC_CSR0_3290); else - rt2800_register_read(rt2x00dev, MAC_CSR0, ®); + reg = rt2800_register_read(rt2x00dev, MAC_CSR0); rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET); rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION); @@ -7708,6 +9400,7 @@ static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev) case RT3390: case RT3572: case RT3593: + case RT5350: case RT5390: case RT5392: case RT5592: @@ -7718,6 +9411,9 @@ static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev) return -ENODEV; } + if (rt == RT5390 && rt2x00_is_soc(rt2x00dev)) + rt = RT6352; + rt2x00_set_rt(rt2x00dev, rt, rev); return 0; @@ -7747,7 +9443,7 @@ int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev) * Enable rfkill polling by setting GPIO direction of the * rfkill switch GPIO pin correctly. */ - rt2800_register_read(rt2x00dev, GPIO_CTRL, ®); + reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); rt2x00_set_field32(®, GPIO_CTRL_DIR2, 1); rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); @@ -7822,31 +9518,31 @@ int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value) u32 reg; bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD); - rt2800_register_read(rt2x00dev, TX_RTS_CFG, ®); + reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG); rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, value); rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); - rt2800_register_read(rt2x00dev, CCK_PROT_CFG, ®); + reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG); rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, enabled); rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); - rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®); + reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG); rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, enabled); rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); - rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®); + reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG); rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, enabled); rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); - rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®); + reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG); rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, enabled); rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); - rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®); + reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG); rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, enabled); rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); - rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®); + reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG); rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, enabled); rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); @@ -7889,7 +9585,7 @@ int rt2800_conf_tx(struct ieee80211_hw *hw, field.bit_offset = (queue_idx & 1) * 16; field.bit_mask = 0xffff << field.bit_offset; - rt2800_register_read(rt2x00dev, offset, ®); + reg = rt2800_register_read(rt2x00dev, offset); rt2x00_set_field32(®, field, queue->txop); rt2800_register_write(rt2x00dev, offset, reg); @@ -7897,22 +9593,22 @@ int rt2800_conf_tx(struct ieee80211_hw *hw, field.bit_offset = queue_idx * 4; field.bit_mask = 0xf << field.bit_offset; - rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, ®); + reg = rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG); rt2x00_set_field32(®, field, queue->aifs); rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg); - rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, ®); + reg = rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG); rt2x00_set_field32(®, field, queue->cw_min); rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg); - rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, ®); + reg = rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG); rt2x00_set_field32(®, field, queue->cw_max); rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg); /* Update EDCA registers */ offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx); - rt2800_register_read(rt2x00dev, offset, ®); + reg = rt2800_register_read(rt2x00dev, offset); rt2x00_set_field32(®, EDCA_AC0_CFG_TX_OP, queue->txop); rt2x00_set_field32(®, EDCA_AC0_CFG_AIFSN, queue->aifs); rt2x00_set_field32(®, EDCA_AC0_CFG_CWMIN, queue->cw_min); @@ -7929,9 +9625,9 @@ u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) u64 tsf; u32 reg; - rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, ®); + reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW1); tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32; - rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, ®); + reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW0); tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD); return tsf; @@ -7998,9 +9694,9 @@ int rt2800_get_survey(struct ieee80211_hw *hw, int idx, survey->channel = conf->chandef.chan; - rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle); - rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy); - rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext); + idle = rt2800_register_read(rt2x00dev, CH_IDLE_STA); + busy = rt2800_register_read(rt2x00dev, CH_BUSY_STA); + busy_ext = rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC); if (idle || busy) { survey->filled = SURVEY_INFO_TIME | |