diff options
Diffstat (limited to 'drivers/net/ipa')
52 files changed, 5852 insertions, 2372 deletions
diff --git a/drivers/net/ipa/Makefile b/drivers/net/ipa/Makefile index 48255fc4b25c..cba199422f47 100644 --- a/drivers/net/ipa/Makefile +++ b/drivers/net/ipa/Makefile @@ -2,17 +2,22 @@ # # Makefile for the Qualcomm IPA driver. -IPA_VERSIONS := 3.1 3.5.1 4.2 4.5 4.9 4.11 +IPA_VERSIONS := 3.1 3.5.1 4.2 4.5 4.7 4.9 4.11 + +# Some IPA versions can reuse another set of GSI register definitions. +GSI_IPA_VERSIONS := 3.1 3.5.1 4.0 4.5 4.9 4.11 obj-$(CONFIG_QCOM_IPA) += ipa.o ipa-y := ipa_main.o ipa_power.o ipa_reg.o ipa_mem.o \ - ipa_table.o ipa_interrupt.o gsi.o gsi_trans.o \ - ipa_gsi.o ipa_smp2p.o ipa_uc.o \ + ipa_table.o ipa_interrupt.o gsi.o gsi_reg.o \ + gsi_trans.o ipa_gsi.o ipa_smp2p.o ipa_uc.o \ ipa_endpoint.o ipa_cmd.o ipa_modem.o \ ipa_resource.o ipa_qmi.o ipa_qmi_msg.o \ ipa_sysfs.o +ipa-y += $(GSI_IPA_VERSIONS:%=reg/gsi_reg-v%.o) + ipa-y += $(IPA_VERSIONS:%=reg/ipa_reg-v%.o) ipa-y += $(IPA_VERSIONS:%=data/ipa_data-v%.o) diff --git a/drivers/net/ipa/data/ipa_data-v3.1.c b/drivers/net/ipa/data/ipa_data-v3.1.c index e0d71f609272..3380fb3483b2 100644 --- a/drivers/net/ipa/data/ipa_data-v3.1.c +++ b/drivers/net/ipa/data/ipa_data-v3.1.c @@ -525,13 +525,14 @@ static const struct ipa_power_data ipa_power_data = { /* Configuration data for an SoC having IPA v3.1 */ const struct ipa_data ipa_data_v3_1 = { - .version = IPA_VERSION_3_1, - .backward_compat = BIT(BCR_CMDQ_L_LACK_ONE_ENTRY), - .qsb_count = ARRAY_SIZE(ipa_qsb_data), - .qsb_data = ipa_qsb_data, - .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data), - .endpoint_data = ipa_gsi_endpoint_data, - .resource_data = &ipa_resource_data, - .mem_data = &ipa_mem_data, - .power_data = &ipa_power_data, + .version = IPA_VERSION_3_1, + .backward_compat = BIT(BCR_CMDQ_L_LACK_ONE_ENTRY), + .qsb_count = ARRAY_SIZE(ipa_qsb_data), + .qsb_data = ipa_qsb_data, + .modem_route_count = 8, + .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data), + .endpoint_data = ipa_gsi_endpoint_data, + .resource_data = &ipa_resource_data, + .mem_data = &ipa_mem_data, + .power_data = &ipa_power_data, }; diff --git a/drivers/net/ipa/data/ipa_data-v3.5.1.c b/drivers/net/ipa/data/ipa_data-v3.5.1.c index 42f2c88a92d4..4287114b24db 100644 --- a/drivers/net/ipa/data/ipa_data-v3.5.1.c +++ b/drivers/net/ipa/data/ipa_data-v3.5.1.c @@ -406,17 +406,18 @@ static const struct ipa_power_data ipa_power_data = { /* Configuration data for an SoC having IPA v3.5.1 */ const struct ipa_data ipa_data_v3_5_1 = { - .version = IPA_VERSION_3_5_1, - .backward_compat = BIT(BCR_CMDQ_L_LACK_ONE_ENTRY) | - BIT(BCR_TX_NOT_USING_BRESP) | - BIT(BCR_SUSPEND_L2_IRQ) | - BIT(BCR_HOLB_DROP_L2_IRQ) | - BIT(BCR_DUAL_TX), - .qsb_count = ARRAY_SIZE(ipa_qsb_data), - .qsb_data = ipa_qsb_data, - .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data), - .endpoint_data = ipa_gsi_endpoint_data, - .resource_data = &ipa_resource_data, - .mem_data = &ipa_mem_data, - .power_data = &ipa_power_data, + .version = IPA_VERSION_3_5_1, + .backward_compat = BIT(BCR_CMDQ_L_LACK_ONE_ENTRY) | + BIT(BCR_TX_NOT_USING_BRESP) | + BIT(BCR_SUSPEND_L2_IRQ) | + BIT(BCR_HOLB_DROP_L2_IRQ) | + BIT(BCR_DUAL_TX), + .qsb_count = ARRAY_SIZE(ipa_qsb_data), + .qsb_data = ipa_qsb_data, + .modem_route_count = 8, + .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data), + .endpoint_data = ipa_gsi_endpoint_data, + .resource_data = &ipa_resource_data, + .mem_data = &ipa_mem_data, + .power_data = &ipa_power_data, }; diff --git a/drivers/net/ipa/data/ipa_data-v4.11.c b/drivers/net/ipa/data/ipa_data-v4.11.c index a204e439c23d..1b4b52501ee3 100644 --- a/drivers/net/ipa/data/ipa_data-v4.11.c +++ b/drivers/net/ipa/data/ipa_data-v4.11.c @@ -394,12 +394,13 @@ static const struct ipa_power_data ipa_power_data = { /* Configuration data for an SoC having IPA v4.11 */ const struct ipa_data ipa_data_v4_11 = { - .version = IPA_VERSION_4_11, - .qsb_count = ARRAY_SIZE(ipa_qsb_data), - .qsb_data = ipa_qsb_data, - .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data), - .endpoint_data = ipa_gsi_endpoint_data, - .resource_data = &ipa_resource_data, - .mem_data = &ipa_mem_data, - .power_data = &ipa_power_data, + .version = IPA_VERSION_4_11, + .qsb_count = ARRAY_SIZE(ipa_qsb_data), + .qsb_data = ipa_qsb_data, + .modem_route_count = 8, + .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data), + .endpoint_data = ipa_gsi_endpoint_data, + .resource_data = &ipa_resource_data, + .mem_data = &ipa_mem_data, + .power_data = &ipa_power_data, }; diff --git a/drivers/net/ipa/data/ipa_data-v4.2.c b/drivers/net/ipa/data/ipa_data-v4.2.c index 04f574fe006f..199ed0ed868b 100644 --- a/drivers/net/ipa/data/ipa_data-v4.2.c +++ b/drivers/net/ipa/data/ipa_data-v4.2.c @@ -372,13 +372,14 @@ static const struct ipa_power_data ipa_power_data = { /* Configuration data for an SoC having IPA v4.2 */ const struct ipa_data ipa_data_v4_2 = { - .version = IPA_VERSION_4_2, + .version = IPA_VERSION_4_2, /* backward_compat value is 0 */ - .qsb_count = ARRAY_SIZE(ipa_qsb_data), - .qsb_data = ipa_qsb_data, - .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data), - .endpoint_data = ipa_gsi_endpoint_data, - .resource_data = &ipa_resource_data, - .mem_data = &ipa_mem_data, - .power_data = &ipa_power_data, + .qsb_count = ARRAY_SIZE(ipa_qsb_data), + .qsb_data = ipa_qsb_data, + .modem_route_count = 8, + .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data), + .endpoint_data = ipa_gsi_endpoint_data, + .resource_data = &ipa_resource_data, + .mem_data = &ipa_mem_data, + .power_data = &ipa_power_data, }; diff --git a/drivers/net/ipa/data/ipa_data-v4.5.c b/drivers/net/ipa/data/ipa_data-v4.5.c index 684239e71f46..19b549f2998b 100644 --- a/drivers/net/ipa/data/ipa_data-v4.5.c +++ b/drivers/net/ipa/data/ipa_data-v4.5.c @@ -450,12 +450,13 @@ static const struct ipa_power_data ipa_power_data = { /* Configuration data for an SoC having IPA v4.5 */ const struct ipa_data ipa_data_v4_5 = { - .version = IPA_VERSION_4_5, - .qsb_count = ARRAY_SIZE(ipa_qsb_data), - .qsb_data = ipa_qsb_data, - .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data), - .endpoint_data = ipa_gsi_endpoint_data, - .resource_data = &ipa_resource_data, - .mem_data = &ipa_mem_data, - .power_data = &ipa_power_data, + .version = IPA_VERSION_4_5, + .qsb_count = ARRAY_SIZE(ipa_qsb_data), + .qsb_data = ipa_qsb_data, + .modem_route_count = 8, + .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data), + .endpoint_data = ipa_gsi_endpoint_data, + .resource_data = &ipa_resource_data, + .mem_data = &ipa_mem_data, + .power_data = &ipa_power_data, }; diff --git a/drivers/net/ipa/data/ipa_data-v4.7.c b/drivers/net/ipa/data/ipa_data-v4.7.c new file mode 100644 index 000000000000..b83390c48615 --- /dev/null +++ b/drivers/net/ipa/data/ipa_data-v4.7.c @@ -0,0 +1,405 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* Copyright (C) 2022 Linaro Ltd. */ + +#include <linux/log2.h> + +#include "../gsi.h" +#include "../ipa_data.h" +#include "../ipa_endpoint.h" +#include "../ipa_mem.h" + +/** enum ipa_resource_type - IPA resource types for an SoC having IPA v4.7 */ +enum ipa_resource_type { + /* Source resource types; first must have value 0 */ + IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS = 0, + IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS, + IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF, + IPA_RESOURCE_TYPE_SRC_HPS_DMARS, + IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES, + + /* Destination resource types; first must have value 0 */ + IPA_RESOURCE_TYPE_DST_DATA_SECTORS = 0, + IPA_RESOURCE_TYPE_DST_DPS_DMARS, +}; + +/* Resource groups used for an SoC having IPA v4.7 */ +enum ipa_rsrc_group_id { + /* Source resource group identifiers */ + IPA_RSRC_GROUP_SRC_UL_DL = 0, + IPA_RSRC_GROUP_SRC_UC_RX_Q, + IPA_RSRC_GROUP_SRC_COUNT, /* Last in set; not a source group */ + + /* Destination resource group identifiers */ + IPA_RSRC_GROUP_DST_UL_DL_DPL = 0, + IPA_RSRC_GROUP_DST_UNUSED_1, + IPA_RSRC_GROUP_DST_COUNT, /* Last; not a destination group */ +}; + +/* QSB configuration data for an SoC having IPA v4.7 */ +static const struct ipa_qsb_data ipa_qsb_data[] = { + [IPA_QSB_MASTER_DDR] = { + .max_writes = 8, + .max_reads = 0, /* no limit (hardware max) */ + .max_reads_beats = 120, + }, +}; + +/* Endpoint configuration data for an SoC having IPA v4.7 */ +static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = { + [IPA_ENDPOINT_AP_COMMAND_TX] = { + .ee_id = GSI_EE_AP, + .channel_id = 5, + .endpoint_id = 7, + .toward_ipa = true, + .channel = { + .tre_count = 256, + .event_count = 256, + .tlv_count = 20, + }, + .endpoint = { + .config = { + .resource_group = IPA_RSRC_GROUP_SRC_UL_DL, + .dma_mode = true, + .dma_endpoint = IPA_ENDPOINT_AP_LAN_RX, + .tx = { + .seq_type = IPA_SEQ_DMA, + }, + }, + }, + }, + [IPA_ENDPOINT_AP_LAN_RX] = { + .ee_id = GSI_EE_AP, + .channel_id = 14, + .endpoint_id = 9, + .toward_ipa = false, + .channel = { + .tre_count = 256, + .event_count = 256, + .tlv_count = 9, + }, + .endpoint = { + .config = { + .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL, + .aggregation = true, + .status_enable = true, + .rx = { + .buffer_size = 8192, + .pad_align = ilog2(sizeof(u32)), + .aggr_time_limit = 500, + }, + }, + }, + }, + [IPA_ENDPOINT_AP_MODEM_TX] = { + .ee_id = GSI_EE_AP, + .channel_id = 2, + .endpoint_id = 2, + .toward_ipa = true, + .channel = { + .tre_count = 512, + .event_count = 512, + .tlv_count = 16, + }, + .endpoint = { + .filter_support = true, + .config = { + .resource_group = IPA_RSRC_GROUP_SRC_UL_DL, + .qmap = true, + .status_enable = true, + .tx = { + .seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC, + .status_endpoint = + IPA_ENDPOINT_MODEM_AP_RX, + }, + }, + }, + }, + [IPA_ENDPOINT_AP_MODEM_RX] = { + .ee_id = GSI_EE_AP, + .channel_id = 7, + .endpoint_id = 16, + .toward_ipa = false, + .channel = { + .tre_count = 256, + .event_count = 256, + .tlv_count = 9, + }, + .endpoint = { + .config = { + .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL, + .qmap = true, + .aggregation = true, + .rx = { + .buffer_size = 8192, + .aggr_time_limit = 500, + .aggr_close_eof = true, + }, + }, + }, + }, + [IPA_ENDPOINT_MODEM_AP_TX] = { + .ee_id = GSI_EE_MODEM, + .channel_id = 0, + .endpoint_id = 5, + .toward_ipa = true, + .endpoint = { + .filter_support = true, + }, + }, + [IPA_ENDPOINT_MODEM_AP_RX] = { + .ee_id = GSI_EE_MODEM, + .channel_id = 7, + .endpoint_id = 14, + .toward_ipa = false, + }, + [IPA_ENDPOINT_MODEM_DL_NLO_TX] = { + .ee_id = GSI_EE_MODEM, + .channel_id = 2, + .endpoint_id = 8, + .toward_ipa = true, + .endpoint = { + .filter_support = true, + }, + }, +}; + +/* Source resource configuration data for an SoC having IPA v4.7 */ +static const struct ipa_resource ipa_resource_src[] = { + [IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = { + .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { + .min = 8, .max = 8, + }, + }, + [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = { + .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { + .min = 8, .max = 8, + }, + }, + [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = { + .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { + .min = 18, .max = 18, + }, + }, + [IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = { + .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { + .min = 2, .max = 2, + }, + }, + [IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = { + .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { + .min = 15, .max = 15, + }, + }, +}; + +/* Destination resource configuration data for an SoC having IPA v4.7 */ +static const struct ipa_resource ipa_resource_dst[] = { + [IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = { + .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = { + .min = 7, .max = 7, + }, + }, + [IPA_RESOURCE_TYPE_DST_DPS_DMARS] = { + .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = { + .min = 2, .max = 2, + }, + }, +}; + +/* Resource configuration data for an SoC having IPA v4.7 */ +static const struct ipa_resource_data ipa_resource_data = { + .rsrc_group_dst_count = IPA_RSRC_GROUP_DST_COUNT, + .rsrc_group_src_count = IPA_RSRC_GROUP_SRC_COUNT, + .resource_src_count = ARRAY_SIZE(ipa_resource_src), + .resource_src = ipa_resource_src, + .resource_dst_count = ARRAY_SIZE(ipa_resource_dst), + .resource_dst = ipa_resource_dst, +}; + +/* IPA-resident memory region data for an SoC having IPA v4.7 */ +static const struct ipa_mem ipa_mem_local_data[] = { + { + .id = IPA_MEM_UC_SHARED, + .offset = 0x0000, + .size = 0x0080, + .canary_count = 0, + }, + { + .id = IPA_MEM_UC_INFO, + .offset = 0x0080, + .size = 0x0200, + .canary_count = 0, + }, + { + .id = IPA_MEM_V4_FILTER_HASHED, + .offset = 0x0288, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_V4_FILTER, + .offset = 0x0308, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_V6_FILTER_HASHED, + .offset = 0x0388, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_V6_FILTER, + .offset = 0x0408, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_V4_ROUTE_HASHED, + .offset = 0x0488, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_V4_ROUTE, + .offset = 0x0508, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_V6_ROUTE_HASHED, + .offset = 0x0588, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_V6_ROUTE, + .offset = 0x0608, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_MODEM_HEADER, + .offset = 0x0688, + .size = 0x0240, + .canary_count = 2, + }, + { + .id = IPA_MEM_AP_HEADER, + .offset = 0x08c8, + .size = 0x0200, + .canary_count = 0, + }, + { + .id = IPA_MEM_MODEM_PROC_CTX, + .offset = 0x0ad0, + .size = 0x0200, + .canary_count = 2, + }, + { + .id = IPA_MEM_AP_PROC_CTX, + .offset = 0x0cd0, + .size = 0x0200, + .canary_count = 0, + }, + { + .id = IPA_MEM_NAT_TABLE, + .offset = 0x0ee0, + .size = 0x0d00, + .canary_count = 4, + }, + { + .id = IPA_MEM_PDN_CONFIG, + .offset = 0x1be8, + .size = 0x0050, + .canary_count = 0, + }, + { + .id = IPA_MEM_STATS_QUOTA_MODEM, + .offset = 0x1c40, + .size = 0x0030, + .canary_count = 4, + }, + { + .id = IPA_MEM_STATS_QUOTA_AP, + .offset = 0x1c70, + .size = 0x0048, + .canary_count = 0, + }, + { + .id = IPA_MEM_STATS_TETHERING, + .offset = 0x1cb8, + .size = 0x0238, + .canary_count = 0, + }, + { + .id = IPA_MEM_STATS_DROP, + .offset = 0x1ef0, + .size = 0x0020, + .canary_count = 0, + }, + { + .id = IPA_MEM_MODEM, + .offset = 0x1f18, + .size = 0x100c, + .canary_count = 2, + }, + { + .id = IPA_MEM_END_MARKER, + .offset = 0x3000, + .size = 0x0000, + .canary_count = 1, + }, +}; + +/* Memory configuration data for an SoC having IPA v4.7 */ +static const struct ipa_mem_data ipa_mem_data = { + .local_count = ARRAY_SIZE(ipa_mem_local_data), + .local = ipa_mem_local_data, + .imem_addr = 0x146a8000, + .imem_size = 0x00002000, + .smem_id = 497, + .smem_size = 0x00009000, +}; + +/* Interconnect rates are in 1000 byte/second units */ +static const struct ipa_interconnect_data ipa_interconnect_data[] = { + { + .name = "memory", + .peak_bandwidth = 600000, /* 600 MBps */ + .average_bandwidth = 150000, /* 150 MBps */ + }, + /* Average rate is unused for the next two interconnects */ + { + .name = "imem", + .peak_bandwidth = 450000, /* 450 MBps */ + .average_bandwidth = 75000, /* 75 MBps (unused?) */ + }, + { + .name = "config", + .peak_bandwidth = 171400, /* 171.4 MBps */ + .average_bandwidth = 0, /* unused */ + }, +}; + +/* Clock and interconnect configuration data for an SoC having IPA v4.7 */ +static const struct ipa_power_data ipa_power_data = { + /* XXX Downstream code says 150 MHz (DT SVS2), 60 MHz (code) */ + .core_clock_rate = 100 * 1000 * 1000, /* Hz (150? 60?) */ + .interconnect_count = ARRAY_SIZE(ipa_interconnect_data), + .interconnect_data = ipa_interconnect_data, +}; + +/* Configuration data for an SoC having IPA v4.7 */ +const struct ipa_data ipa_data_v4_7 = { + .version = IPA_VERSION_4_7, + .qsb_count = ARRAY_SIZE(ipa_qsb_data), + .qsb_data = ipa_qsb_data, + .modem_route_count = 8, + .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data), + .endpoint_data = ipa_gsi_endpoint_data, + .resource_data = &ipa_resource_data, + .mem_data = &ipa_mem_data, + .power_data = &ipa_power_data, +}; diff --git a/drivers/net/ipa/data/ipa_data-v4.9.c b/drivers/net/ipa/data/ipa_data-v4.9.c index 2333e15f9533..d30fc1fe6ca2 100644 --- a/drivers/net/ipa/data/ipa_data-v4.9.c +++ b/drivers/net/ipa/data/ipa_data-v4.9.c @@ -444,12 +444,13 @@ static const struct ipa_power_data ipa_power_data = { /* Configuration data for an SoC having IPA v4.9. */ const struct ipa_data ipa_data_v4_9 = { - .version = IPA_VERSION_4_9, - .qsb_count = ARRAY_SIZE(ipa_qsb_data), - .qsb_data = ipa_qsb_data, - .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data), - .endpoint_data = ipa_gsi_endpoint_data, - .resource_data = &ipa_resource_data, - .mem_data = &ipa_mem_data, - .power_data = &ipa_power_data, + .version = IPA_VERSION_4_9, + .qsb_count = ARRAY_SIZE(ipa_qsb_data), + .qsb_data = ipa_qsb_data, + .modem_route_count = 8, + .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data), + .endpoint_data = ipa_gsi_endpoint_data, + .resource_data = &ipa_resource_data, + .mem_data = &ipa_mem_data, + .power_data = &ipa_power_data, }; diff --git a/drivers/net/ipa/gsi.c b/drivers/net/ipa/gsi.c index bea2da1c4c51..9a0b1fe4a93a 100644 --- a/drivers/net/ipa/gsi.c +++ b/drivers/net/ipa/gsi.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. - * Copyright (C) 2018-2022 Linaro Ltd. + * Copyright (C) 2018-2023 Linaro Ltd. */ #include <linux/types.h> @@ -16,6 +16,7 @@ #include <linux/netdevice.h> #include "gsi.h" +#include "reg.h" #include "gsi_reg.h" #include "gsi_private.h" #include "gsi_trans.h" @@ -162,12 +163,6 @@ static void gsi_validate_build(void) * ensure the elements themselves meet the requirement. */ BUILD_BUG_ON(!is_power_of_2(GSI_RING_ELEMENT_SIZE)); - - /* The channel element size must fit in this field */ - BUILD_BUG_ON(GSI_RING_ELEMENT_SIZE > field_max(ELEMENT_SIZE_FMASK)); - - /* The event ring element size must fit in this field */ - BUILD_BUG_ON(GSI_RING_ELEMENT_SIZE > field_max(EV_ELEMENT_SIZE_FMASK)); } /* Return the channel id associated with a given channel */ @@ -182,21 +177,39 @@ static bool gsi_channel_initialized(struct gsi_channel *channel) return !!channel->gsi; } +/* Encode the channel protocol for the CH_C_CNTXT_0 register */ +static u32 ch_c_cntxt_0_type_encode(enum ipa_version version, + const struct reg *reg, + enum gsi_channel_type type) +{ + u32 val; + + val = reg_encode(reg, CHTYPE_PROTOCOL, type); + if (version < IPA_VERSION_4_5 || version >= IPA_VERSION_5_0) + return val; + + type >>= hweight32(reg_fmask(reg, CHTYPE_PROTOCOL)); + + return val | reg_encode(reg, CHTYPE_PROTOCOL_MSB, type); +} + /* Update the GSI IRQ type register with the cached value */ static void gsi_irq_type_update(struct gsi *gsi, u32 val) { + const struct reg *reg = gsi_reg(gsi, CNTXT_TYPE_IRQ_MSK); + gsi->type_enabled_bitmap = val; - iowrite32(val, gsi->virt + GSI_CNTXT_TYPE_IRQ_MSK_OFFSET); + iowrite32(val, gsi->virt + reg_offset(reg)); } static void gsi_irq_type_enable(struct gsi *gsi, enum gsi_irq_type_id type_id) { - gsi_irq_type_update(gsi, gsi->type_enabled_bitmap | BIT(type_id)); + gsi_irq_type_update(gsi, gsi->type_enabled_bitmap | type_id); } static void gsi_irq_type_disable(struct gsi *gsi, enum gsi_irq_type_id type_id) { - gsi_irq_type_update(gsi, gsi->type_enabled_bitmap & ~BIT(type_id)); + gsi_irq_type_update(gsi, gsi->type_enabled_bitmap & ~type_id); } /* Event ring commands are performed one at a time. Their completion @@ -207,22 +220,29 @@ static void gsi_irq_type_disable(struct gsi *gsi, enum gsi_irq_type_id type_id) static void gsi_irq_ev_ctrl_enable(struct gsi *gsi, u32 evt_ring_id) { u32 val = BIT(evt_ring_id); + const struct reg *reg; /* There's a small chance that a previous command completed * after the interrupt was disabled, so make sure we have no * pending interrupts before we enable them. */ - iowrite32(~0, gsi->virt + GSI_CNTXT_SRC_EV_CH_IRQ_CLR_OFFSET); + reg = gsi_reg(gsi, CNTXT_SRC_EV_CH_IRQ_CLR); + iowrite32(~0, gsi->virt + reg_offset(reg)); - iowrite32(val, gsi->virt + GSI_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET); + reg = gsi_reg(gsi, CNTXT_SRC_EV_CH_IRQ_MSK); + iowrite32(val, gsi->virt + reg_offset(reg)); gsi_irq_type_enable(gsi, GSI_EV_CTRL); } /* Disable event ring control interrupts */ static void gsi_irq_ev_ctrl_disable(struct gsi *gsi) { + const struct reg *reg; + gsi_irq_type_disable(gsi, GSI_EV_CTRL); - iowrite32(0, gsi->virt + GSI_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET); + + reg = gsi_reg(gsi, CNTXT_SRC_EV_CH_IRQ_MSK); + iowrite32(0, gsi->virt + reg_offset(reg)); } /* Channel commands are performed one at a time. Their completion is @@ -233,32 +253,43 @@ static void gsi_irq_ev_ctrl_disable(struct gsi *gsi) static void gsi_irq_ch_ctrl_enable(struct gsi *gsi, u32 channel_id) { u32 val = BIT(channel_id); + const struct reg *reg; /* There's a small chance that a previous command completed * after the interrupt was disabled, so make sure we have no * pending interrupts before we enable them. */ - iowrite32(~0, gsi->virt + GSI_CNTXT_SRC_CH_IRQ_CLR_OFFSET); + reg = gsi_reg(gsi, CNTXT_SRC_CH_IRQ_CLR); + iowrite32(~0, gsi->virt + reg_offset(reg)); + + reg = gsi_reg(gsi, CNTXT_SRC_CH_IRQ_MSK); + iowrite32(val, gsi->virt + reg_offset(reg)); - iowrite32(val, gsi->virt + GSI_CNTXT_SRC_CH_IRQ_MSK_OFFSET); gsi_irq_type_enable(gsi, GSI_CH_CTRL); } /* Disable channel control interrupts */ static void gsi_irq_ch_ctrl_disable(struct gsi *gsi) { + const struct reg *reg; + gsi_irq_type_disable(gsi, GSI_CH_CTRL); - iowrite32(0, gsi->virt + GSI_CNTXT_SRC_CH_IRQ_MSK_OFFSET); + + reg = gsi_reg(gsi, CNTXT_SRC_CH_IRQ_MSK); + iowrite32(0, gsi->virt + reg_offset(reg)); } static void gsi_irq_ieob_enable_one(struct gsi *gsi, u32 evt_ring_id) { bool enable_ieob = !gsi->ieob_enabled_bitmap; + const struct reg *reg; u32 val; gsi->ieob_enabled_bitmap |= BIT(evt_ring_id); + + reg = gsi_reg(gsi, CNTXT_SRC_IEOB_IRQ_MSK); val = gsi->ieob_enabled_bitmap; - iowrite32(val, gsi->virt + GSI_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET); + iowrite32(val, gsi->virt + reg_offset(reg)); /* Enable the interrupt type if this is the first channel enabled */ if (enable_ieob) @@ -267,6 +298,7 @@ static void gsi_irq_ieob_enable_one(struct gsi *gsi, u32 evt_ring_id) static void gsi_irq_ieob_disable(struct gsi *gsi, u32 event_mask) { + const struct reg *reg; u32 val; gsi->ieob_enabled_bitmap &= ~event_mask; @@ -275,8 +307,9 @@ static void gsi_irq_ieob_disable(struct gsi *gsi, u32 event_mask) if (!gsi->ieob_enabled_bitmap) gsi_irq_type_disable(gsi, GSI_IEOB); + reg = gsi_reg(gsi, CNTXT_SRC_IEOB_IRQ_MSK); val = gsi->ieob_enabled_bitmap; - iowrite32(val, gsi->virt + GSI_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET); + iowrite32(val, gsi->virt + reg_offset(reg)); } static void gsi_irq_ieob_disable_one(struct gsi *gsi, u32 evt_ring_id) @@ -287,34 +320,44 @@ static void gsi_irq_ieob_disable_one(struct gsi *gsi, u32 evt_ring_id) /* Enable all GSI_interrupt types */ static void gsi_irq_enable(struct gsi *gsi) { + const struct reg *reg; u32 val; /* Global interrupts include hardware error reports. Enable * that so we can at least report the error should it occur. */ - iowrite32(BIT(ERROR_INT), gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET); - gsi_irq_type_update(gsi, gsi->type_enabled_bitmap | BIT(GSI_GLOB_EE)); + reg = gsi_reg(gsi, CNTXT_GLOB_IRQ_EN); + iowrite32(ERROR_INT, gsi->virt + reg_offset(reg)); + + gsi_irq_type_update(gsi, gsi->type_enabled_bitmap | GSI_GLOB_EE); /* General GSI interrupts are reported to all EEs; if they occur * they are unrecoverable (without reset). A breakpoint interrupt * also exists, but we don't support that. We want to be notified * of errors so we can report them, even if they can't be handled. */ - val = BIT(BUS_ERROR); - val |= BIT(CMD_FIFO_OVRFLOW); - val |= BIT(MCS_STACK_OVRFLOW); - iowrite32(val, gsi->virt + GSI_CNTXT_GSI_IRQ_EN_OFFSET); - gsi_irq_type_update(gsi, gsi->type_enabled_bitmap | BIT(GSI_GENERAL)); + reg = gsi_reg(gsi, CNTXT_GSI_IRQ_EN); + val = BUS_ERROR; + val |= CMD_FIFO_OVRFLOW; + val |= MCS_STACK_OVRFLOW; + iowrite32(val, gsi->virt + reg_offset(reg)); + + gsi_irq_type_update(gsi, gsi->type_enabled_bitmap | GSI_GENERAL); } /* Disable all GSI interrupt types */ static void gsi_irq_disable(struct gsi *gsi) { + const struct reg *reg; + gsi_irq_type_update(gsi, 0); /* Clear the type-specific interrupt masks set by gsi_irq_enable() */ - iowrite32(0, gsi->virt + GSI_CNTXT_GSI_IRQ_EN_OFFSET); - iowrite32(0, gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET); + reg = gsi_reg(gsi, CNTXT_GSI_IRQ_EN); + iowrite32(0, gsi->virt + reg_offset(reg)); + + reg = gsi_reg(gsi, CNTXT_GLOB_IRQ_EN); + iowrite32(0, gsi->virt + reg_offset(reg)); } /* Return the virtual address associated with a ring index */ @@ -356,11 +399,12 @@ static bool gsi_command(struct gsi *gsi, u32 reg, u32 val) static enum gsi_evt_ring_state gsi_evt_ring_state(struct gsi *gsi, u32 evt_ring_id) { + const struct reg *reg = gsi_reg(gsi, EV_CH_E_CNTXT_0); u32 val; - val = ioread32(gsi->virt + GSI_EV_CH_E_CNTXT_0_OFFSET(evt_ring_id)); + val = ioread32(gsi->virt + reg_n_offset(reg, evt_ring_id)); - return u32_get_bits(val, EV_CHSTATE_FMASK); + return reg_decode(reg, EV_CHSTATE, val); } /* Issue an event ring command and wait for it to complete */ @@ -368,16 +412,18 @@ static void gsi_evt_ring_command(struct gsi *gsi, u32 evt_ring_id, enum gsi_evt_cmd_opcode opcode) { struct device *dev = gsi->dev; + const struct reg *reg; bool timeout; u32 val; /* Enable the completion interrupt for the command */ gsi_irq_ev_ctrl_enable(gsi, evt_ring_id); - val = u32_encode_bits(evt_ring_id, EV_CHID_FMASK); - val |= u32_encode_bits(opcode, EV_OPCODE_FMASK); + reg = gsi_reg(gsi, EV_CH_CMD); + val = reg_encode(reg, EV_CHID, evt_ring_id); + val |= reg_encode(reg, EV_OPCODE, opcode); - timeout = !gsi_command(gsi, GSI_EV_CH_CMD_OFFSET, val); + timeout = !gsi_command(gsi, reg_offset(reg), val); gsi_irq_ev_ctrl_disable(gsi); @@ -464,13 +510,16 @@ static void gsi_evt_ring_de_alloc_command(struct gsi *gsi, u32 evt_ring_id) /* Fetch the current state of a channel from hardware */ static enum gsi_channel_state gsi_channel_state(struct gsi_channel *channel) { + const struct reg *reg = gsi_reg(channel->gsi, CH_C_CNTXT_0); u32 channel_id = gsi_channel_id(channel); - void __iomem *virt = channel->gsi->virt; + struct gsi *gsi = channel->gsi; + void __iomem *virt = gsi->virt; u32 val; - val = ioread32(virt + GSI_CH_C_CNTXT_0_OFFSET(channel_id)); + reg = gsi_reg(gsi, CH_C_CNTXT_0); + val = ioread32(virt + reg_n_offset(reg, channel_id)); - return u32_get_bits(val, CHSTATE_FMASK); + return reg_decode(reg, CHSTATE, val); } /* Issue a channel command and wait for it to complete */ @@ -480,15 +529,18 @@ gsi_channel_command(struct gsi_channel *channel, enum gsi_ch_cmd_opcode opcode) u32 channel_id = gsi_channel_id(channel); struct gsi *gsi = channel->gsi; struct device *dev = gsi->dev; + const struct reg *reg; bool timeout; u32 val; /* Enable the completion interrupt for the command */ gsi_irq_ch_ctrl_enable(gsi, channel_id); - val = u32_encode_bits(channel_id, CH_CHID_FMASK); - val |= u32_encode_bits(opcode, CH_OPCODE_FMASK); - timeout = !gsi_command(gsi, GSI_CH_CMD_OFFSET, val); + reg = gsi_reg(gsi, CH_CMD); + val = reg_encode(reg, CH_CHID, channel_id); + val |= reg_encode(reg, CH_OPCODE, opcode); + + timeout = !gsi_command(gsi, reg_offset(reg), val); gsi_irq_ch_ctrl_disable(gsi); @@ -651,6 +703,7 @@ static void gsi_channel_de_alloc_command(struct gsi *gsi, u32 channel_id) */ static void gsi_evt_ring_doorbell(struct gsi *gsi, u32 evt_ring_id, u32 index) { + const struct reg *reg = gsi_reg(gsi, EV_CH_E_DOORBELL_0); struct gsi_ring *ring = &gsi->evt_ring[evt_ring_id].ring; u32 val; @@ -658,7 +711,7 @@ static void gsi_evt_ring_doorbell(struct gsi *gsi, u32 evt_ring_id, u32 index) /* Note: index *must* be used modulo the ring count here */ val = gsi_ring_addr(ring, (index - 1) % ring->count); - iowrite32(val, gsi->virt + GSI_EV_CH_E_DOORBELL_0_OFFSET(evt_ring_id)); + iowrite32(val, gsi->virt + reg_n_offset(reg, evt_ring_id)); } /* Program an event ring for use */ @@ -666,41 +719,56 @@ static void gsi_evt_ring_program(struct gsi *gsi, u32 evt_ring_id) { struct gsi_evt_ring *evt_ring = &gsi->evt_ring[evt_ring_id]; struct gsi_ring *ring = &evt_ring->ring; - size_t size; + const struct reg *reg; u32 val; + reg = gsi_reg(gsi, EV_CH_E_CNTXT_0); /* We program all event rings as GPI type/protocol */ - val = u32_encode_bits(GSI_CHANNEL_TYPE_GPI, EV_CHTYPE_FMASK); - val |= EV_INTYPE_FMASK; - val |= u32_encode_bits(GSI_RING_ELEMENT_SIZE, EV_ELEMENT_SIZE_FMASK); - iowrite32(val, gsi->virt + GSI_EV_CH_E_CNTXT_0_OFFSET(evt_ring_id)); + val = reg_encode(reg, EV_CHTYPE, GSI_CHANNEL_TYPE_GPI); + /* EV_EE field is 0 (GSI_EE_AP) */ + val |= reg_bit(reg, EV_INTYPE); + val |= reg_encode(reg, EV_ELEMENT_SIZE, GSI_RING_ELEMENT_SIZE); + iowrite32(val, gsi->virt + reg_n_offset(reg, evt_ring_id)); - size = ring->count * GSI_RING_ELEMENT_SIZE; - val = ev_r_length_encoded(gsi->version, size); - iowrite32(val, gsi->virt + GSI_EV_CH_E_CNTXT_1_OFFSET(evt_ring_id)); + reg = gsi_reg(gsi, EV_CH_E_CNTXT_1); + val = reg_encode(reg, R_LENGTH, ring->count * GSI_RING_ELEMENT_SIZE); + iowrite32(val, gsi->virt + reg_n_offset(reg, evt_ring_id)); /* The context 2 and 3 registers store the low-order and * high-order 32 bits of the address of the event ring, * respectively. */ + reg = gsi_reg(gsi, EV_CH_E_CNTXT_2); val = lower_32_bits(ring->addr); - iowrite32(val, gsi->virt + GSI_EV_CH_E_CNTXT_2_OFFSET(evt_ring_id)); + iowrite32(val, gsi->virt + reg_n_offset(reg, evt_ring_id)); + + reg = gsi_reg(gsi, EV_CH_E_CNTXT_3); val = upper_32_bits(ring->addr); - iowrite32(val, gsi->virt + GSI_EV_CH_E_CNTXT_3_OFFSET(evt_ring_id)); + iowrite32(val, gsi->virt + reg_n_offset(reg, evt_ring_id)); /* Enable interrupt moderation by setting the moderation delay */ - val = u32_encode_bits(GSI_EVT_RING_INT_MODT, MODT_FMASK); - val |= u32_encode_bits(1, MODC_FMASK); /* comes from channel */ - iowrite32(val, gsi->virt + GSI_EV_CH_E_CNTXT_8_OFFSET(evt_ring_id)); + reg = gsi_reg(gsi, EV_CH_E_CNTXT_8); + val = reg_encode(reg, EV_MODT, GSI_EVT_RING_INT_MODT); + val |= reg_encode(reg, EV_MODC, 1); /* comes from channel */ + /* EV_MOD_CNT is 0 (no counter-based interrupt coalescing) */ + iowrite32(val, gsi->virt + reg_n_offset(reg, evt_ring_id)); + + /* No MSI write data, and MSI high and low address is 0 */ + reg = gsi_reg(gsi, EV_CH_E_CNTXT_9); + iowrite32(0, gsi->virt + reg_n_offset(reg, evt_ring_id)); - /* No MSI write data, and MSI address high and low address is 0 */ - iowrite32(0, gsi->virt + GSI_EV_CH_E_CNTXT_9_OFFSET(evt_ring_id)); - iowrite32(0, gsi->virt + GSI_EV_CH_E_CNTXT_10_OFFSET(evt_ring_id)); - iowrite32(0, gsi->virt + GSI_EV_CH_E_CNTXT_11_OFFSET(evt_ring_id)); + reg = gsi_reg(gsi, EV_CH_E_CNTXT_10); + iowrite32(0, gsi->virt + reg_n_offset(reg, evt_ring_id)); + + reg = gsi_reg(gsi, EV_CH_E_CNTXT_11); + iowrite32(0, gsi->virt + reg_n_offset(reg, evt_ring_id)); /* We don't need to get event read pointer updates */ - iowrite32(0, gsi->virt + GSI_EV_CH_E_CNTXT_12_OFFSET(evt_ring_id)); - iowrite32(0, gsi->virt + GSI_EV_CH_E_CNTXT_13_OFFSET(evt_ring_id)); + reg = gsi_reg(gsi, EV_CH_E_CNTXT_12); + iowrite32(0, gsi->virt + reg_n_offset(reg, evt_ring_id)); + + reg = gsi_reg(gsi, EV_CH_E_CNTXT_13); + iowrite32(0, gsi->virt + reg_n_offset(reg, evt_ring_id)); /* Finally, tell the hardware our "last processed" event (arbitrary) */ gsi_evt_ring_doorbell(gsi, evt_ring_id, ring->index); @@ -761,39 +829,52 @@ static void gsi_channel_program(struct gsi_channel *channel, bool doorbell) union gsi_channel_scratch scr = { }; struct gsi_channel_scratch_gpi *gpi; struct gsi *gsi = channel->gsi; + const struct reg *reg; u32 wrr_weight = 0; + u32 offset; u32 val; + reg = gsi_reg(gsi, CH_C_CNTXT_0); + /* We program all channels as GPI type/protocol */ - val = chtype_protocol_encoded(gsi->version, GSI_CHANNEL_TYPE_GPI); + val = ch_c_cntxt_0_type_encode(gsi->version, reg, GSI_CHANNEL_TYPE_GPI); if (channel->toward_ipa) - val |= CHTYPE_DIR_FMASK; - val |= u32_encode_bits(channel->evt_ring_id, ERINDEX_FMASK); - val |= u32_encode_bits(GSI_RING_ELEMENT_SIZE, ELEMENT_SIZE_FMASK); - iowrite32(val, gsi->virt + GSI_CH_C_CNTXT_0_OFFSET(channel_id)); - - val = r_length_encoded(gsi->version, size); - iowrite32(val, gsi->virt + GSI_CH_C_CNTXT_1_OFFSET(channel_id)); + val |= reg_bit(reg, CHTYPE_DIR); + if (gsi->version < IPA_VERSION_5_0) + val |= reg_encode(reg, ERINDEX, channel->evt_ring_id); + val |= reg_encode(reg, ELEMENT_SIZE, GSI_RING_ELEMENT_SIZE); + iowrite32(val, gsi->virt + reg_n_offset(reg, channel_id)); + + reg = gsi_reg(gsi, CH_C_CNTXT_1); + val = reg_encode(reg, CH_R_LENGTH, size); + if (gsi->version >= IPA_VERSION_5_0) + val |= reg_encode(reg, CH_ERINDEX, channel->evt_ring_id); + iowrite32(val, gsi->virt + reg_n_offset(reg, channel_id)); /* The context 2 and 3 registers store the low-order and * high-order 32 bits of the address of the channel ring, * respectively. */ + reg = gsi_reg(gsi, CH_C_CNTXT_2); val = lower_32_bits(channel->tre_ring.addr); - iowrite32(val, gsi->virt + GSI_CH_C_CNTXT_2_OFFSET(channel_id)); + iowrite32(val, gsi->virt + reg_n_offset(reg, channel_id)); + + reg = gsi_reg(gsi, CH_C_CNTXT_3); val = upper_32_bits(channel->tre_ring.addr); - iowrite32(val, gsi->virt + GSI_CH_C_CNTXT_3_OFFSET(channel_id)); + iowrite32(val, gsi->virt + reg_n_offset(reg, channel_id)); + + reg = gsi_reg(gsi, CH_C_QOS); /* Command channel gets low weighted round-robin priority */ if (channel->command) - wrr_weight = field_max(WRR_WEIGHT_FMASK); - val = u32_encode_bits(wrr_weight, WRR_WEIGHT_FMASK); + wrr_weight = reg_field_max(reg, WRR_WEIGHT); + val = reg_encode(reg, WRR_WEIGHT, wrr_weight); /* Max prefetch is 1 segment (do not set MAX_PREFETCH_FMASK) */ /* No need to use the doorbell engine starting at IPA v4.0 */ if (gsi->version < IPA_VERSION_4_0 && doorbell) - val |= USE_DB_ENG_FMASK; + val |= reg_bit(reg, USE_DB_ENG); /* v4.0 introduces an escape buffer for prefetch. We use it * on all but the AP command channel. @@ -801,16 +882,15 @@ static void gsi_channel_program(struct gsi_channel *channel, bool doorbell) if (gsi->version >= IPA_VERSION_4_0 && !channel->command) { /* If not otherwise set, prefetch buffers are used */ if (gsi->version < IPA_VERSION_4_5) - val |= USE_ESCAPE_BUF_ONLY_FMASK; + val |= reg_bit(reg, USE_ESCAPE_BUF_ONLY); else - val |= u32_encode_bits(GSI_ESCAPE_BUF_ONLY, - PREFETCH_MODE_FMASK); + val |= reg_encode(reg, PREFETCH_MODE, ESCAPE_BUF_ONLY); } /* All channels set DB_IN_BYTES */ if (gsi->version >= IPA_VERSION_4_9) - val |= DB_IN_BYTES; + val |= reg_bit(reg, DB_IN_BYTES); - iowrite32(val, gsi->virt + GSI_CH_C_QOS_OFFSET(channel_id)); + iowrite32(val, gsi->virt + reg_n_offset(reg, channel_id)); /* Now update the scratch registers for GPI protocol */ gpi = &scr.gpi; @@ -818,22 +898,27 @@ static void gsi_channel_program(struct gsi_channel *channel, bool doorbell) GSI_RING_ELEMENT_SIZE; gpi->outstanding_threshold = 2 * GSI_RING_ELEMENT_SIZE; + reg = gsi_reg(gsi, CH_C_SCRATCH_0); val = scr.data.word1; - iowrite32(val, gsi->virt + GSI_CH_C_SCRATCH_0_OFFSET(channel_id)); + iowrite32(val, gsi->virt + reg_n_offset(reg, channel_id)); + reg = gsi_reg(gsi, CH_C_SCRATCH_1); val = scr.data.word2; - iowrite32(val, gsi->virt + GSI_CH_C_SCRATCH_1_OFFSET(channel_id)); + iowrite32(val, gsi->virt + reg_n_offset(reg, channel_id)); + reg = gsi_reg(gsi, CH_C_SCRATCH_2); val = scr.data.word3; - iowrite32(val, gsi->virt + GSI_CH_C_SCRATCH_2_OFFSET(channel_id)); + iowrite32(val, gsi->virt + reg_n_offset(reg, channel_id)); /* We must preserve the upper 16 bits of the last scratch register. * The next sequence assumes those bits remain unchanged between the * read and the write. */ - val = ioread32(gsi->virt + GSI_CH_C_SCRATCH_3_OFFSET(channel_id)); + reg = gsi_reg(gsi, CH_C_SCRATCH_3); + offset = reg_n_offset(reg, channel_id); + val = ioread32(gsi->virt + offset); val = (scr.data.word4 & GENMASK(31, 16)) | (val & GENMASK(15, 0)); - iowrite32(val, gsi->virt + GSI_CH_C_SCRATCH_3_OFFSET(channel_id)); + iowrite32(val, gsi->virt + offset); /* All done! */ } @@ -1049,10 +1134,14 @@ static void gsi_trans_tx_completed(struct gsi_trans *trans) /* Channel control interrupt handler */ static void gsi_isr_chan_ctrl(struct gsi *gsi) { + const struct reg *reg; u32 channel_mask; - channel_mask = ioread32(gsi->virt + GSI_CNTXT_SRC_CH_IRQ_OFFSET); - iowrite32(channel_mask, gsi->virt + GSI_CNTXT_SRC_CH_IRQ_CLR_OFFSET); + reg = gsi_reg(gsi, CNTXT_SRC_CH_IRQ); + channel_mask = ioread32(gsi->virt + reg_offset(reg)); + + reg = gsi_reg(gsi, CNTXT_SRC_CH_IRQ_CLR); + iowrite32(channel_mask, gsi->virt + reg_offset(reg)); while (channel_mask) { u32 channel_id = __ffs(channel_mask); @@ -1066,10 +1155,14 @@ static void gsi_isr_chan_ctrl(struct gsi *gsi) /* Event ring control interrupt handler */ static void gsi_isr_evt_ctrl(struct gsi *gsi) { + const struct reg *reg; u32 event_mask; - event_mask = ioread32(gsi->virt + GSI_CNTXT_SRC_EV_CH_IRQ_OFFSET); - iowrite32(event_mask, gsi->virt + GSI_CNTXT_SRC_EV_CH_IRQ_CLR_OFFSET); + reg = gsi_reg(gsi, CNTXT_SRC_EV_CH_IRQ); + event_mask = ioread32(gsi->virt + reg_offset(reg)); + + reg = gsi_reg(gsi, CNTXT_SRC_EV_CH_IRQ_CLR); + iowrite32(event_mask, gsi->virt + reg_offset(reg)); while (event_mask) { u32 evt_ring_id = __ffs(event_mask); @@ -1117,21 +1210,29 @@ gsi_isr_glob_evt_err(struct gsi *gsi, u32 err_ee, u32 evt_ring_id, u32 code) /* Global error interrupt handler */ static void gsi_isr_glob_err(struct gsi *gsi) { + const struct reg *log_reg; + const struct reg *clr_reg; enum gsi_err_type type; enum gsi_err_code code; + u32 offset; u32 which; u32 val; u32 ee; /* Get the logged error, then reinitialize the log */ - val = ioread32(gsi->virt + GSI_ERROR_LOG_OFFSET); - iowrite32(0, gsi->virt + GSI_ERROR_LOG_OFFSET); - iowrite32(~0, gsi->virt + GSI_ERROR_LOG_CLR_OFFSET); + log_reg = gsi_reg(gsi, ERROR_LOG); + offset = reg_offset(log_reg); + val = ioread32(gsi->virt + offset); + iowrite32(0, gsi->virt + offset); + + clr_reg = gsi_reg(gsi, ERROR_LOG_CLR); + iowrite32(~0, gsi->virt + reg_offset(clr_reg)); - ee = u32_get_bits(val, ERR_EE_FMASK); - type = u32_get_bits(val, ERR_TYPE_FMASK); - which = u32_get_bits(val, ERR_VIRT_IDX_FMASK); - code = u32_get_bits(val, ERR_CODE_FMASK); + /* Parse the error value */ + ee = reg_decode(log_reg, ERR_EE, val); + type = reg_decode(log_reg, ERR_TYPE, val); + which = reg_decode(log_reg, ERR_VIRT_IDX, val); + code = reg_decode(log_reg, ERR_CODE, val); if (type == GSI_ERR_TYPE_CHAN) gsi_isr_glob_chan_err(gsi, ee, which, code); @@ -1144,6 +1245,7 @@ static void gsi_isr_glob_err(struct gsi *gsi) /* Generic EE interrupt handler */ static void gsi_isr_gp_int1(struct gsi *gsi) { + const struct reg *reg; u32 result; u32 val; @@ -1166,8 +1268,9 @@ static void gsi_isr_gp_int1(struct gsi *gsi) * In either case, we silently ignore a INCORRECT_CHANNEL_STATE * error if we receive it. */ - val = ioread32(gsi->virt + GSI_CNTXT_SCRATCH_0_OFFSET); - result = u32_get_bits(val, GENERIC_EE_RESULT_FMASK); + reg = gsi_reg(gsi, CNTXT_SCRATCH_0); + val = ioread32(gsi->virt + reg_offset(reg)); + result = reg_decode(reg, GENERIC_EE_RESULT, val); switch (result) { case GENERIC_EE_SUCCESS: @@ -1191,19 +1294,22 @@ static void gsi_isr_gp_int1(struct gsi *gsi) /* Inter-EE interrupt handler */ static void gsi_isr_glob_ee(struct gsi *gsi) { + const struct reg *reg; u32 val; - val = ioread32(gsi->virt + GSI_CNTXT_GLOB_IRQ_STTS_OFFSET); + reg = gsi_reg(gsi, CNTXT_GLOB_IRQ_STTS); + val = ioread32(gsi->virt + reg_offset(reg)); - if (val & BIT(ERROR_INT)) + if (val & ERROR_INT) gsi_isr_glob_err(gsi); - iowrite32(val, gsi->virt + GSI_CNTXT_GLOB_IRQ_CLR_OFFSET); + reg = gsi_reg(gsi, CNTXT_GLOB_IRQ_CLR); + iowrite32(val, gsi->virt + reg_offset(reg)); - val &= ~BIT(ERROR_INT); + val &= ~ERROR_INT; - if (val & BIT(GP_INT1)) { - val ^= BIT(GP_INT1); + if (val & GP_INT1) { + val ^= GP_INT1; gsi_isr_gp_int1(gsi); } @@ -1214,11 +1320,16 @@ static void gsi_isr_glob_ee(struct gsi *gsi) /* I/O completion interrupt event */ static void gsi_isr_ieob(struct gsi *gsi) { + const struct reg *reg; u32 event_mask; - event_mask = ioread32(gsi->virt + GSI_CNTXT_SRC_IEOB_IRQ_OFFSET); + reg = gsi_reg(gsi, CNTXT_SRC_IEOB_IRQ); + event_mask = ioread32(gsi->virt + reg_offset(reg)); + gsi_irq_ieob_disable(gsi, event_mask); - iowrite32(event_mask, gsi->virt + GSI_CNTXT_SRC_IEOB_IRQ_CLR_OFFSET); + + reg = gsi_reg(gsi, CNTXT_SRC_IEOB_IRQ_CLR); + iowrite32(event_mask, gsi->virt + reg_offset(reg)); while (event_mask) { u32 evt_ring_id = __ffs(event_mask); @@ -1233,10 +1344,14 @@ static void gsi_isr_ieob(struct gsi *gsi) static void gsi_isr_general(struct gsi *gsi) { struct device *dev = gsi->dev; + const struct reg *reg; u32 val; - val = ioread32(gsi->virt + GSI_CNTXT_GSI_IRQ_STTS_OFFSET); - iowrite32(val, gsi->virt + GSI_CNTXT_GSI_IRQ_CLR_OFFSET); + reg = gsi_reg(gsi, CNTXT_GSI_IRQ_STTS); + val = ioread32(gsi->virt + reg_offset(reg)); + + reg = gsi_reg(gsi, CNTXT_GSI_IRQ_CLR); + iowrite32(val, gsi->virt + reg_offset(reg)); dev_err(dev, "unexpected general interrupt 0x%08x\n", val); } @@ -1252,31 +1367,39 @@ static void gsi_isr_general(struct gsi *gsi) static irqreturn_t gsi_isr(int irq, void *dev_id) { struct gsi *gsi = dev_id; + const struct reg *reg; u32 intr_mask; u32 cnt = 0; + u32 offset; + + reg = gsi_reg(gsi, CNTXT_TYPE_IRQ); + offset = reg_offset(reg); /* enum gsi_irq_type_id defines GSI interrupt types */ - while ((intr_mask = ioread32(gsi->virt + GSI_CNTXT_TYPE_IRQ_OFFSET))) { + while ((intr_mask = ioread32(gsi->virt + offset))) { /* intr_mask contains bitmask of pending GSI interrupts */ do { u32 gsi_intr = BIT(__ffs(intr_mask)); intr_mask ^= gsi_intr; + /* Note: the IRQ condition for each type is cleared + * when the type-specific register is updated. + */ switch (gsi_intr) { - case BIT(GSI_CH_CTRL): + case GSI_CH_CTRL: gsi_isr_chan_ctrl(gsi); break; - case BIT(GSI_EV_CTRL): + case GSI_EV_CTRL: gsi_isr_evt_ctrl(gsi); break; - case BIT(GSI_GLOB_EE): + case GSI_GLOB_EE: gsi_isr_glob_ee(gsi); break; - case BIT(GSI_IEOB): + case GSI_IEOB: gsi_isr_ieob(gsi); break; - case BIT(GSI_GENERAL): + case GSI_GENERAL: gsi_isr_general(gsi); break; default: @@ -1467,11 +1590,13 @@ void gsi_channel_doorbell(struct gsi_channel *channel) struct gsi_ring *tre_ring = &channel->tre_ring; u32 channel_id = gsi_channel_id(channel); struct gsi *gsi = channel->gsi; + const struct reg *reg; u32 val; + reg = gsi_reg(gsi, CH_C_DOORBELL_0); /* Note: index *must* be used modulo the ring count here */ val = gsi_ring_addr(tre_ring, tre_ring->index % tre_ring->count); - iowrite32(val, gsi->virt + GSI_CH_C_DOORBELL_0_OFFSET(channel_id)); + iowrite32(val, gsi->virt + reg_n_offset(reg, channel_id)); } /* Consult hardware, move newly completed transactions to completed state */ @@ -1482,6 +1607,7 @@ void gsi_channel_update(struct gsi_channel *channel) struct gsi_evt_ring *evt_ring; struct gsi_trans *trans; struct gsi_ring *ring; + const struct reg *reg; u32 offset; u32 index; @@ -1491,7 +1617,8 @@ void gsi_channel_update(struct gsi_channel *channel) /* See if there's anything new to process; if not, we're done. Note * that index always refers to an entry *within* the event ring. */ - offset = GSI_EV_CH_E_CNTXT_4_OFFSET(evt_ring_id); + reg = gsi_reg(gsi, EV_CH_E_CNTXT_4); + offset = reg_n_offset(reg, evt_ring_id); index = gsi_ring_index(ring, ioread32(gsi->virt + offset)); if (index == ring->index % ring->count) return; @@ -1642,7 +1769,9 @@ static int gsi_generic_command(struct gsi *gsi, u32 channel_id, enum gsi_generic_cmd_opcode opcode, u8 params) { + const struct reg *reg; bool timeout; + u32 offset; u32 val; /* The error global interrupt type is always enabled (until we tear @@ -1654,24 +1783,31 @@ static int gsi_generic_command(struct gsi *gsi, u32 channel_id, * channel), and only from this function. So we enable the GP_INT1 * IRQ type here, and disable it again after the command completes. */ - val = BIT(ERROR_INT) | BIT(GP_INT1); - iowrite32(val, gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET); + reg = gsi_reg(gsi, CNTXT_GLOB_IRQ_EN); + val = ERROR_INT | GP_INT1; + iowrite32(val, gsi->virt + reg_offset(reg)); /* First zero the result code field */ - val = ioread32(gsi->virt + GSI_CNTXT_SCRATCH_0_OFFSET); - val &= ~GENERIC_EE_RESULT_FMASK; - iowrite32(val, gsi->virt + GSI_CNTXT_SCRATCH_0_OFFSET); + reg = gsi_reg(gsi, CNTXT_SCRATCH_0); + offset = reg_offset(reg); + val = ioread32(gsi->virt + offset); + + val &= ~reg_fmask(reg, GENERIC_EE_RESULT); + iowrite32(val, gsi->virt + offset); /* Now issue the command */ - val = u32_encode_bits(opcode, GENERIC_OPCODE_FMASK); - val |= u32_encode_bits(channel_id, GENERIC_CHID_FMASK); - val |= u32_encode_bits(GSI_EE_MODEM, GENERIC_EE_FMASK); - val |= u32_encode_bits(params, GENERIC_PARAMS_FMASK); + reg = gsi_reg(gsi, GENERIC_CMD); + val = reg_encode(reg, GENERIC_OPCODE, opcode); + val |= reg_encode(reg, GENERIC_CHID, channel_id); + val |= reg_encode(reg, GENERIC_EE, GSI_EE_MODEM); + if (gsi->version >= IPA_VERSION_4_11) + val |= reg_encode(reg, GENERIC_PARAMS, params); - timeout = !gsi_command(gsi, GSI_GENERIC_CMD_OFFSET, val); + timeout = !gsi_command(gsi, reg_offset(reg), val); /* Disable the GP_INT1 IRQ type again */ - iowrite32(BIT(ERROR_INT), gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET); + reg = gsi_reg(gsi, CNTXT_GLOB_IRQ_EN); + iowrite32(ERROR_INT, gsi->virt + reg_offset(reg)); if (!timeout) return gsi->result; @@ -1828,32 +1964,40 @@ static void gsi_channel_teardown(struct gsi *gsi) /* Turn off all GSI interrupts initially */ static int gsi_irq_setup(struct gsi *gsi) { + const struct reg *reg; int ret; /* Writing 1 indicates IRQ interrupts; 0 would be MSI */ - iowrite32(1, gsi->virt + GSI_CNTXT_INTSET_OFFSET); + reg = gsi_reg(gsi, CNTXT_INTSET); + iowrite32(reg_bit(reg, INTYPE), gsi->virt + reg_offset(reg)); /* Disable all interrupt types */ gsi_irq_type_update(gsi, 0); /* Clear all type-specific interrupt masks */ - iowrite32(0, gsi->virt + GSI_CNTXT_SRC_CH_IRQ_MSK_OFFSET); - iowrite32(0, gsi->virt + GSI_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET); - iowrite32(0, gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET); - iowrite32(0, gsi->virt + GSI_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET); + reg = gsi_reg(gsi, CNTXT_SRC_CH_IRQ_MSK); + iowrite32(0, gsi->virt + reg_offset(reg)); + + reg = gsi_reg(gsi, CNTXT_SRC_EV_CH_IRQ_MSK); + iowrite32(0, gsi->virt + reg_offset(reg)); + + reg = gsi_reg(gsi, CNTXT_GLOB_IRQ_EN); + iowrite32(0, gsi->virt + reg_offset(reg)); + + reg = gsi_reg(gsi, CNTXT_SRC_IEOB_IRQ_MSK); + iowrite32(0, gsi->virt + reg_offset(reg)); /* The inter-EE interrupts are not supported for IPA v3.0-v3.1 */ if (gsi->version > IPA_VERSION_3_1) { - u32 offset; + reg = gsi_reg(gsi, INTER_EE_SRC_CH_IRQ_MSK); + iowrite32(0, gsi->virt + reg_offset(reg)); - /* These registers are in the non-adjusted address range */ - offset = GSI_INTER_EE_SRC_CH_IRQ_MSK_OFFSET; - iowrite32(0, gsi->virt_raw + offset); - offset = GSI_INTER_EE_SRC_EV_CH_IRQ_MSK_OFFSET; - iowrite32(0, gsi->virt_raw + offset); + reg = gsi_reg(gsi, INTER_EE_SRC_EV_CH_IRQ_MSK); + iowrite32(0, gsi->virt + reg_offset(reg)); } - iowrite32(0, gsi->virt + GSI_CNTXT_GSI_IRQ_EN_OFFSET); + reg = gsi_reg(gsi, CNTXT_GSI_IRQ_EN); + iowrite32(0, gsi->virt + reg_offset(reg)); ret = request_irq(gsi->irq, gsi_isr, 0, "gsi", gsi); if (ret) @@ -1871,6 +2015,7 @@ static void gsi_irq_teardown(struct gsi *gsi) static int gsi_ring_setup(struct gsi *gsi) { struct device *dev = gsi->dev; + const struct reg *reg; u32 count; u32 val; @@ -1882,9 +2027,10 @@ static int gsi_ring_setup(struct gsi *gsi) return 0; } - val = ioread32(gsi->virt + GSI_GSI_HW_PARAM_2_OFFSET); + reg = gsi_reg(gsi, HW_PARAM_2); + val = ioread32(gsi->virt + reg_offset(reg)); - count = u32_get_bits(val, NUM_CH_PER_EE_FMASK); + count = reg_decode(reg, NUM_CH_PER_EE, val); if (!count) { dev_err(dev, "GSI reports zero channels supported\n"); return -EINVAL; @@ -1896,7 +2042,12 @@ static int gsi_ring_setup(struct gsi *gsi) } gsi->channel_count = count; - count = u32_get_bits(val, NUM_EV_PER_EE_FMASK); + if (gsi->version < IPA_VERSION_5_0) { + count = reg_decode(reg, NUM_EV_PER_EE, val); + } else { + reg = gsi_reg(gsi, HW_PARAM_4); + count = reg_decode(reg, EV_PER_EE, val); + } if (!count) { dev_err(dev, "GSI reports zero event rings supported\n"); return -EINVAL; @@ -1915,12 +2066,14 @@ static int gsi_ring_setup(struct gsi *gsi) /* Setup function for GSI. GSI firmware must be loaded and initialized */ int gsi_setup(struct gsi *gsi) { + const struct reg *reg; u32 val; int ret; /* Here is where we first touch the GSI hardware */ - val = ioread32(gsi->virt + GSI_GSI_STATUS_OFFSET); - if (!(val & ENABLED_FMASK)) { + reg = gsi_reg(gsi, GSI_STATUS); + val = ioread32(gsi->virt + reg_offset(reg)); + if (!(val & reg_bit(reg, ENABLED))) { dev_err(gsi->dev, "GSI has not been enabled\n"); return -EIO; } @@ -1934,7 +2087,8 @@ int gsi_setup(struct gsi *gsi) goto err_irq_teardown; /* Initialize the error log */ - iowrite32(0, gsi->virt + GSI_ERROR_LOG_OFFSET); + reg = gsi_reg(gsi, ERROR_LOG); + iowrite32(0, gsi->virt + reg_offset(reg)); ret = gsi_channel_setup(gsi); if (ret) @@ -2205,67 +2359,37 @@ int gsi_init(struct gsi *gsi, struct platform_device *pdev, enum ipa_version version, u32 count, const struct ipa_gsi_endpoint_data *data) { - struct device *dev = &pdev->dev; - struct resource *res; - resource_size_t size; - u32 adjust; int ret; gsi_validate_build(); - gsi->dev = dev; + gsi->dev = &pdev->dev; gsi->version = version; /* GSI uses NAPI on all channels. Create a dummy network device * for the channel NAPI contexts to be associated with. */ init_dummy_netdev(&gsi->dummy_dev); - - /* Get GSI memory range and map it */ - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "gsi"); - if (!res) { - dev_err(dev, "DT error getting \"gsi\" memory property\n"); - return -ENODEV; - } - - size = resource_size(res); - if (res->start > U32_MAX || size > U32_MAX - res->start) { - dev_err(dev, "DT memory resource \"gsi\" out of range\n"); - return -EINVAL; - } - - /* Make sure we can make our pointer adjustment if necessary */ - adjust = gsi->version < IPA_VERSION_4_5 ? 0 : GSI_EE_REG_ADJUST; - if (res->start < adjust) { - dev_err(dev, "DT memory resource \"gsi\" too low (< %u)\n", - adjust); - return -EINVAL; - } - - gsi->virt_raw = ioremap(res->start, size); - if (!gsi->virt_raw) { - dev_err(dev, "unable to remap \"gsi\" memory\n"); - return -ENOMEM; - } - /* Most registers are accessed using an adjusted register range */ - gsi->virt = gsi->virt_raw - adjust; - init_completion(&gsi->completion); + ret = gsi_reg_init(gsi, pdev); + if (ret) + return ret; + ret = gsi_irq_init(gsi, pdev); /* No matching exit required */ if (ret) - goto err_iounmap; + goto err_reg_exit; ret = gsi_channel_init(gsi, count, data); if (ret) - goto err_iounmap; + goto err_reg_exit; mutex_init(&gsi->mutex); return 0; -err_iounmap: - iounmap(gsi->virt_raw); +err_reg_exit: + gsi_reg_exit(gsi); return ret; } @@ -2275,7 +2399,7 @@ void gsi_exit(struct gsi *gsi) { mutex_destroy(&gsi->mutex); gsi_channel_exit(gsi); - iounmap(gsi->virt_raw); + gsi_reg_exit(gsi); } /* The maximum number of outstanding TREs on a channel. This limits diff --git a/drivers/net/ipa/gsi.h b/drivers/net/ipa/gsi.h index 49dcadba4e0b..50bc80cb167c 100644 --- a/drivers/net/ipa/gsi.h +++ b/drivers/net/ipa/gsi.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. - * Copyright (C) 2018-2022 Linaro Ltd. + * Copyright (C) 2018-2023 Linaro Ltd. */ #ifndef _GSI_H_ #define _GSI_H_ @@ -140,8 +140,9 @@ struct gsi_evt_ring { struct gsi { struct device *dev; /* Same as IPA device */ enum ipa_version version; - void __iomem *virt_raw; /* I/O mapped address range */ - void __iomem *virt; /* Adjusted for most registers */ + void __iomem *virt; /* I/O mapped registers */ + const struct regs *regs; + u32 irq; u32 channel_count; u32 evt_ring_count; diff --git a/drivers/net/ipa/gsi_reg.c b/drivers/net/ipa/gsi_reg.c new file mode 100644 index 000000000000..1412b67304c8 --- /dev/null +++ b/drivers/net/ipa/gsi_reg.c @@ -0,0 +1,151 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* Copyright (C) 2023 Linaro Ltd. */ + +#include <linux/platform_device.h> +#include <linux/io.h> + +#include "gsi.h" +#include "reg.h" +#include "gsi_reg.h" + +/* Is this register ID valid for the current GSI version? */ +static bool gsi_reg_id_valid(struct gsi *gsi, enum gsi_reg_id reg_id) +{ + switch (reg_id) { + case INTER_EE_SRC_CH_IRQ_MSK: + case INTER_EE_SRC_EV_CH_IRQ_MSK: + case CH_C_CNTXT_0: + case CH_C_CNTXT_1: + case CH_C_CNTXT_2: + case CH_C_CNTXT_3: + case CH_C_QOS: + case CH_C_SCRATCH_0: + case CH_C_SCRATCH_1: + case CH_C_SCRATCH_2: + case CH_C_SCRATCH_3: + case EV_CH_E_CNTXT_0: + case EV_CH_E_CNTXT_1: + case EV_CH_E_CNTXT_2: + case EV_CH_E_CNTXT_3: + case EV_CH_E_CNTXT_4: + case EV_CH_E_CNTXT_8: + case EV_CH_E_CNTXT_9: + case EV_CH_E_CNTXT_10: + case EV_CH_E_CNTXT_11: + case EV_CH_E_CNTXT_12: + case EV_CH_E_CNTXT_13: + case EV_CH_E_SCRATCH_0: + case EV_CH_E_SCRATCH_1: + case CH_C_DOORBELL_0: + case EV_CH_E_DOORBELL_0: + case GSI_STATUS: + case CH_CMD: + case EV_CH_CMD: + case GENERIC_CMD: + case HW_PARAM_2: + case CNTXT_TYPE_IRQ: + case CNTXT_TYPE_IRQ_MSK: + case CNTXT_SRC_CH_IRQ: + case CNTXT_SRC_CH_IRQ_MSK: + case CNTXT_SRC_CH_IRQ_CLR: + case CNTXT_SRC_EV_CH_IRQ: + case CNTXT_SRC_EV_CH_IRQ_MSK: + case CNTXT_SRC_EV_CH_IRQ_CLR: + case CNTXT_SRC_IEOB_IRQ: + case CNTXT_SRC_IEOB_IRQ_MSK: + case CNTXT_SRC_IEOB_IRQ_CLR: + case CNTXT_GLOB_IRQ_STTS: + case CNTXT_GLOB_IRQ_EN: + case CNTXT_GLOB_IRQ_CLR: + case CNTXT_GSI_IRQ_STTS: + case CNTXT_GSI_IRQ_EN: + case CNTXT_GSI_IRQ_CLR: + case CNTXT_INTSET: + case ERROR_LOG: + case ERROR_LOG_CLR: + case CNTXT_SCRATCH_0: + return true; + + default: + return false; + } +} + +const struct reg *gsi_reg(struct gsi *gsi, enum gsi_reg_id reg_id) +{ + if (WARN(!gsi_reg_id_valid(gsi, reg_id), "invalid reg %u\n", reg_id)) + return NULL; + + return reg(gsi->regs, reg_id); +} + +static const struct regs *gsi_regs(struct gsi *gsi) +{ + switch (gsi->version) { + case IPA_VERSION_3_1: + return &gsi_regs_v3_1; + + case IPA_VERSION_3_5_1: + return &gsi_regs_v3_5_1; + + case IPA_VERSION_4_2: + return &gsi_regs_v4_0; + + case IPA_VERSION_4_5: + case IPA_VERSION_4_7: + return &gsi_regs_v4_5; + + case IPA_VERSION_4_9: + return &gsi_regs_v4_9; + + case IPA_VERSION_4_11: + return &gsi_regs_v4_11; + + default: + return NULL; + } +} + +/* Sets gsi->virt and I/O maps the "gsi" memory range for registers */ +int gsi_reg_init(struct gsi *gsi, struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct resource *res; + resource_size_t size; + + /* Get GSI memory range and map it */ + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "gsi"); + if (!res) { + dev_err(dev, "DT error getting \"gsi\" memory property\n"); + return -ENODEV; + } + + size = resource_size(res); + if (res->start > U32_MAX || size > U32_MAX - res->start) { + dev_err(dev, "DT memory resource \"gsi\" out of range\n"); + return -EINVAL; + } + + gsi->regs = gsi_regs(gsi); + if (!gsi->regs) { + dev_err(dev, "unsupported IPA version %u (?)\n", gsi->version); + return -EINVAL; + } + + gsi->virt = ioremap(res->start, size); + if (!gsi->virt) { + dev_err(dev, "unable to remap \"gsi\" memory\n"); + return -ENOMEM; + } + + return 0; +} + +/* Inverse of gsi_reg_init() */ +void gsi_reg_exit(struct gsi *gsi) +{ + iounmap(gsi->virt); + gsi->virt = NULL; + gsi->regs = NULL; +} diff --git a/drivers/net/ipa/gsi_reg.h b/drivers/net/ipa/gsi_reg.h index 3763359f208f..f62f0a5c653d 100644 --- a/drivers/net/ipa/gsi_reg.h +++ b/drivers/net/ipa/gsi_reg.h @@ -1,12 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. - * Copyright (C) 2018-2022 Linaro Ltd. + * Copyright (C) 2018-2023 Linaro Ltd. */ #ifndef _GSI_REG_H_ #define _GSI_REG_H_ -/* === Only "gsi.c" should include this file === */ +/* === Only "gsi.c" and "gsi_reg.c" should include this file === */ #include <linux/bits.h> @@ -38,29 +38,75 @@ * (though the actual limit is hardware-dependent). */ -/* GSI EE registers as a group are shifted downward by a fixed constant amount - * for IPA versions 4.5 and beyond. This applies to all GSI registers we use - * *except* the ones that disable inter-EE interrupts for channels and event - * channels. - * - * The "raw" (not adjusted) GSI register range is mapped, and a pointer to - * the mapped range is held in gsi->virt_raw. The inter-EE interrupt - * registers are accessed using that pointer. - * - * Most registers are accessed using gsi->virt, which is a copy of the "raw" - * pointer, adjusted downward by the fixed amount. - */ -#define GSI_EE_REG_ADJUST 0x0000d000 /* IPA v4.5+ */ - -/* The inter-EE IRQ registers are relative to gsi->virt_raw (IPA v3.5+) */ - -#define GSI_INTER_EE_SRC_CH_IRQ_MSK_OFFSET \ - (0x0000c020 + 0x1000 * GSI_EE_AP) - -#define GSI_INTER_EE_SRC_EV_CH_IRQ_MSK_OFFSET \ - (0x0000c024 + 0x1000 * GSI_EE_AP) +/* enum gsi_reg_id - GSI register IDs */ +enum gsi_reg_id { + INTER_EE_SRC_CH_IRQ_MSK, /* IPA v3.5+ */ + INTER_EE_SRC_EV_CH_IRQ_MSK, /* IPA v3.5+ */ + CH_C_CNTXT_0, + CH_C_CNTXT_1, + CH_C_CNTXT_2, + CH_C_CNTXT_3, + CH_C_QOS, + CH_C_SCRATCH_0, + CH_C_SCRATCH_1, + CH_C_SCRATCH_2, + CH_C_SCRATCH_3, + EV_CH_E_CNTXT_0, + EV_CH_E_CNTXT_1, + EV_CH_E_CNTXT_2, + EV_CH_E_CNTXT_3, + EV_CH_E_CNTXT_4, + EV_CH_E_CNTXT_8, + EV_CH_E_CNTXT_9, + EV_CH_E_CNTXT_10, + EV_CH_E_CNTXT_11, + EV_CH_E_CNTXT_12, + EV_CH_E_CNTXT_13, + EV_CH_E_SCRATCH_0, + EV_CH_E_SCRATCH_1, + CH_C_DOORBELL_0, + EV_CH_E_DOORBELL_0, + GSI_STATUS, + CH_CMD, + EV_CH_CMD, + GENERIC_CMD, + HW_PARAM_2, /* IPA v3.5.1+ */ + HW_PARAM_4, /* IPA v5.0+ */ + CNTXT_TYPE_IRQ, + CNTXT_TYPE_IRQ_MSK, + CNTXT_SRC_CH_IRQ, + CNTXT_SRC_CH_IRQ_MSK, + CNTXT_SRC_CH_IRQ_CLR, + CNTXT_SRC_EV_CH_IRQ, + CNTXT_SRC_EV_CH_IRQ_MSK, + CNTXT_SRC_EV_CH_IRQ_CLR, + CNTXT_SRC_IEOB_IRQ, + CNTXT_SRC_IEOB_IRQ_MSK, + CNTXT_SRC_IEOB_IRQ_CLR, + CNTXT_GLOB_IRQ_STTS, + CNTXT_GLOB_IRQ_EN, + CNTXT_GLOB_IRQ_CLR, + CNTXT_GSI_IRQ_STTS, + CNTXT_GSI_IRQ_EN, + CNTXT_GSI_IRQ_CLR, + CNTXT_INTSET, + ERROR_LOG, + ERROR_LOG_CLR, + CNTXT_SCRATCH_0, + GSI_REG_ID_COUNT, /* Last; not an ID */ +}; -/* All other register offsets are relative to gsi->virt */ +/* CH_C_CNTXT_0 register */ +enum gsi_reg_ch_c_cntxt_0_field_id { + CHTYPE_PROTOCOL, + CHTYPE_DIR, + CH_EE, + CHID, + CHTYPE_PROTOCOL_MSB, /* IPA v4.5-4.11 */ + ERINDEX, /* Not IPA v5.0+ */ + CHSTATE, + ELEMENT_SIZE, +}; /** enum gsi_channel_type - CHTYPE_PROTOCOL field values in CH_C_CNTXT_0 */ enum gsi_channel_type { @@ -76,155 +122,64 @@ enum gsi_channel_type { GSI_CHANNEL_TYPE_11AD = 0x9, }; -#define GSI_CH_C_CNTXT_0_OFFSET(ch) \ - (0x0001c000 + 0x4000 * GSI_EE_AP + 0x80 * (ch)) -#define CHTYPE_PROTOCOL_FMASK GENMASK(2, 0) -#define CHTYPE_DIR_FMASK GENMASK(3, 3) -#define EE_FMASK GENMASK(7, 4) -#define CHID_FMASK GENMASK(12, 8) -/* The next field is present for IPA v4.5 and above */ -#define CHTYPE_PROTOCOL_MSB_FMASK GENMASK(13, 13) -#define ERINDEX_FMASK GENMASK(18, 14) -#define CHSTATE_FMASK GENMASK(23, 20) -#define ELEMENT_SIZE_FMASK GENMASK(31, 24) - -/* Encoded value for CH_C_CNTXT_0 register channel protocol fields */ -static inline u32 -chtype_protocol_encoded(enum ipa_version version, enum gsi_channel_type type) -{ - u32 val; - - val = u32_encode_bits(type, CHTYPE_PROTOCOL_FMASK); - if (version < IPA_VERSION_4_5) - return val; - - /* Encode upper bit(s) as well */ - type >>= hweight32(CHTYPE_PROTOCOL_FMASK); - val |= u32_encode_bits(type, CHTYPE_PROTOCOL_MSB_FMASK); - - return val; -} - -#define GSI_CH_C_CNTXT_1_OFFSET(ch) \ - (0x0001c004 + 0x4000 * GSI_EE_AP + 0x80 * (ch)) - -/* Encoded value for CH_C_CNTXT_1 register R_LENGTH field */ -static inline u32 r_length_encoded(enum ipa_version version, u32 length) -{ - if (version < IPA_VERSION_4_9) - return u32_encode_bits(length, GENMASK(15, 0)); - return u32_encode_bits(length, GENMASK(19, 0)); -} - -#define GSI_CH_C_CNTXT_2_OFFSET(ch) \ - (0x0001c008 + 0x4000 * GSI_EE_AP + 0x80 * (ch)) - -#define GSI_CH_C_CNTXT_3_OFFSET(ch) \ - (0x0001c00c + 0x4000 * GSI_EE_AP + 0x80 * (ch)) - -#define GSI_CH_C_QOS_OFFSET(ch) \ - (0x0001c05c + 0x4000 * GSI_EE_AP + 0x80 * (ch)) -#define WRR_WEIGHT_FMASK GENMASK(3, 0) -#define MAX_PREFETCH_FMASK GENMASK(8, 8) -#define USE_DB_ENG_FMASK GENMASK(9, 9) -/* The next field is only present for IPA v4.0, v4.1, and v4.2 */ -#define USE_ESCAPE_BUF_ONLY_FMASK GENMASK(10, 10) -/* The next two fields are present for IPA v4.5 and above */ -#define PREFETCH_MODE_FMASK GENMASK(13, 10) -#define EMPTY_LVL_THRSHOLD_FMASK GENMASK(23, 16) -/* The next field is present for IPA v4.9 and above */ -#define DB_IN_BYTES GENMASK(24, 24) +/* CH_C_CNTXT_1 register */ +enum gsi_reg_ch_c_cntxt_1_field_id { + CH_R_LENGTH, + CH_ERINDEX, /* IPA v5.0+ */ +}; + +/* CH_C_QOS register */ +enum gsi_reg_ch_c_qos_field_id { + WRR_WEIGHT, + MAX_PREFETCH, + USE_DB_ENG, + USE_ESCAPE_BUF_ONLY, /* IPA v4.0-4.2 */ + PREFETCH_MODE, /* IPA v4.5+ */ + EMPTY_LVL_THRSHOLD, /* IPA v4.5+ */ + DB_IN_BYTES, /* IPA v4.9+ */ + LOW_LATENCY_EN, /* IPA v5.0+ */ +}; /** enum gsi_prefetch_mode - PREFETCH_MODE field in CH_C_QOS */ enum gsi_prefetch_mode { - GSI_USE_PREFETCH_BUFS = 0x0, - GSI_ESCAPE_BUF_ONLY = 0x1, - GSI_SMART_PREFETCH = 0x2, - GSI_FREE_PREFETCH = 0x3, + USE_PREFETCH_BUFS = 0, + ESCAPE_BUF_ONLY = 1, + SMART_PREFETCH = 2, + FREE_PREFETCH = 3, }; -#define GSI_CH_C_SCRATCH_0_OFFSET(ch) \ - (0x0001c060 + 0x4000 * GSI_EE_AP + 0x80 * (ch)) - -#define GSI_CH_C_SCRATCH_1_OFFSET(ch) \ - (0x0001c064 + 0x4000 * GSI_EE_AP + 0x80 * (ch)) - -#define GSI_CH_C_SCRATCH_2_OFFSET(ch) \ - (0x0001c068 + 0x4000 * GSI_EE_AP + 0x80 * (ch)) - -#define GSI_CH_C_SCRATCH_3_OFFSET(ch) \ - (0x0001c06c + 0x4000 * GSI_EE_AP + 0x80 * (ch)) - -#define GSI_EV_CH_E_CNTXT_0_OFFSET(ev) \ - (0x0001d000 + 0x4000 * GSI_EE_AP + 0x80 * (ev)) -/* enum gsi_channel_type defines EV_CHTYPE field values in EV_CH_E_CNTXT_0 */ -#define EV_CHTYPE_FMASK GENMASK(3, 0) -#define EV_EE_FMASK GENMASK(7, 4) -#define EV_EVCHID_FMASK GENMASK(15, 8) -#define EV_INTYPE_FMASK GENMASK(16, 16) -#define EV_CHSTATE_FMASK GENMASK(23, 20) -#define EV_ELEMENT_SIZE_FMASK GENMASK(31, 24) - -#define GSI_EV_CH_E_CNTXT_1_OFFSET(ev) \ - (0x0001d004 + 0x4000 * GSI_EE_AP + 0x80 * (ev)) -/* Encoded value for EV_CH_C_CNTXT_1 register EV_R_LENGTH field */ -static inline u32 ev_r_length_encoded(enum ipa_version version, u32 length) -{ - if (version < IPA_VERSION_4_9) - return u32_encode_bits(length, GENMASK(15, 0)); - return u32_encode_bits(length, GENMASK(19, 0)); -} - -#define GSI_EV_CH_E_CNTXT_2_OFFSET(ev) \ - (0x0001d008 + 0x4000 * GSI_EE_AP + 0x80 * (ev)) - -#define GSI_EV_CH_E_CNTXT_3_OFFSET(ev) \ - (0x0001d00c + 0x4000 * GSI_EE_AP + 0x80 * (ev)) - -#define GSI_EV_CH_E_CNTXT_4_OFFSET(ev) \ - (0x0001d010 + 0x4000 * GSI_EE_AP + 0x80 * (ev)) - -#define GSI_EV_CH_E_CNTXT_8_OFFSET(ev) \ - (0x0001d020 + 0x4000 * GSI_EE_AP + 0x80 * (ev)) -#define MODT_FMASK GENMASK(15, 0) -#define MODC_FMASK GENMASK(23, 16) -#define MOD_CNT_FMASK GENMASK(31, 24) - -#define GSI_EV_CH_E_CNTXT_9_OFFSET(ev) \ - (0x0001d024 + 0x4000 * GSI_EE_AP + 0x80 * (ev)) - -#define GSI_EV_CH_E_CNTXT_10_OFFSET(ev) \ - (0x0001d028 + 0x4000 * GSI_EE_AP + 0x80 * (ev)) - -#define GSI_EV_CH_E_CNTXT_11_OFFSET(ev) \ - (0x0001d02c + 0x4000 * GSI_EE_AP + 0x80 * (ev)) - -#define GSI_EV_CH_E_CNTXT_12_OFFSET(ev) \ - (0x0001d030 + 0x4000 * GSI_EE_AP + 0x80 * (ev)) - -#define GSI_EV_CH_E_CNTXT_13_OFFSET(ev) \ - (0x0001d034 + 0x4000 * GSI_EE_AP + 0x80 * (ev)) - -#define GSI_EV_CH_E_SCRATCH_0_OFFSET(ev) \ - (0x0001d048 + 0x4000 * GSI_EE_AP + 0x80 * (ev)) - -#define GSI_EV_CH_E_SCRATCH_1_OFFSET(ev) \ - (0x0001d04c + 0x4000 * GSI_EE_AP + 0x80 * (ev)) +/* EV_CH_E_CNTXT_0 register */ +enum gsi_reg_ch_c_ev_ch_e_cntxt_0_field_id { + EV_CHTYPE, /* enum gsi_channel_type */ + EV_EE, /* enum gsi_ee_id; always GSI_EE_AP for us */ + EV_EVCHID, + EV_INTYPE, + EV_CHSTATE, + EV_ELEMENT_SIZE, +}; -#define GSI_CH_C_DOORBELL_0_OFFSET(ch) \ - (0x0001e000 + 0x4000 * GSI_EE_AP + 0x08 * (ch)) +/* EV_CH_E_CNTXT_1 register */ +enum gsi_reg_ev_ch_c_cntxt_1_field_id { + R_LENGTH, +}; -#define GSI_EV_CH_E_DOORBELL_0_OFFSET(ev) \ - (0x0001e100 + 0x4000 * GSI_EE_AP + 0x08 * (ev)) +/* EV_CH_E_CNTXT_8 register */ +enum gsi_reg_ch_c_ev_ch_e_cntxt_8_field_id { + EV_MODT, + EV_MODC, + EV_MOD_CNT, +}; -#define GSI_GSI_STATUS_OFFSET \ - (0x0001f000 + 0x4000 * GSI_EE_AP) -#define ENABLED_FMASK GENMASK(0, 0) +/* GSI_STATUS register */ +enum gsi_reg_gsi_status_field_id { + ENABLED, +}; -#define GSI_CH_CMD_OFFSET \ - (0x0001f008 + 0x4000 * GSI_EE_AP) -#define CH_CHID_FMASK GENMASK(7, 0) -#define CH_OPCODE_FMASK GENMASK(31, 24) +/* CH_CMD register */ +enum gsi_reg_gsi_ch_cmd_field_id { + CH_CHID, + CH_OPCODE, +}; /** enum gsi_ch_cmd_opcode - CH_OPCODE field values in CH_CMD */ enum gsi_ch_cmd_opcode { @@ -236,10 +191,11 @@ enum gsi_ch_cmd_opcode { GSI_CH_DB_STOP = 0xb, }; -#define GSI_EV_CH_CMD_OFFSET \ - (0x0001f010 + 0x4000 * GSI_EE_AP) -#define EV_CHID_FMASK GENMASK(7, 0) -#define EV_OPCODE_FMASK GENMASK(31, 24) +/* EV_CH_CMD register */ +enum gsi_ev_ch_cmd_field_id { + EV_CHID, + EV_OPCODE, +}; /** enum gsi_evt_cmd_opcode - EV_OPCODE field values in EV_CH_CMD */ enum gsi_evt_cmd_opcode { @@ -248,12 +204,13 @@ enum gsi_evt_cmd_opcode { GSI_EVT_DE_ALLOC = 0xa, }; -#define GSI_GENERIC_CMD_OFFSET \ - (0x0001f018 + 0x4000 * GSI_EE_AP) -#define GENERIC_OPCODE_FMASK GENMASK(4, 0) -#define GENERIC_CHID_FMASK GENMASK(9, 5) -#define GENERIC_EE_FMASK GENMASK(13, 10) -#define GENERIC_PARAMS_FMASK GENMASK(31, 24) /* IPA v4.11+ */ +/* GENERIC_CMD register */ +enum gsi_generic_cmd_field_id { + GENERIC_OPCODE, + GENERIC_CHID, + GENERIC_EE, + GENERIC_PARAMS, /* IPA v4.11+ */ +}; /** enum gsi_generic_cmd_opcode - GENERIC_OPCODE field values in GENERIC_CMD */ enum gsi_generic_cmd_opcode { @@ -264,22 +221,20 @@ enum gsi_generic_cmd_opcode { GSI_GENERIC_QUERY_FLOW_CONTROL = 0x5, /* IPA v4.11+ */ }; -/* The next register is present for IPA v3.5.1 and above */ -#define GSI_GSI_HW_PARAM_2_OFFSET \ - (0x0001f040 + 0x4000 * GSI_EE_AP) -#define IRAM_SIZE_FMASK GENMASK(2, 0) -#define NUM_CH_PER_EE_FMASK GENMASK(7, 3) -#define NUM_EV_PER_EE_FMASK GENMASK(12, 8) -#define GSI_CH_PEND_TRANSLATE_FMASK GENMASK(13, 13) -#define GSI_CH_FULL_LOGIC_FMASK GENMASK(14, 14) -/* Fields below are present for IPA v4.0 and above */ -#define GSI_USE_SDMA_FMASK GENMASK(15, 15) -#define GSI_SDMA_N_INT_FMASK GENMASK(18, 16) -#define GSI_SDMA_MAX_BURST_FMASK GENMASK(26, 19) -#define GSI_SDMA_N_IOVEC_FMASK GENMASK(29, 27) -/* Fields below are present for IPA v4.2 and above */ -#define GSI_USE_RD_WR_ENG_FMASK GENMASK(30, 30) -#define GSI_USE_INTER_EE_FMASK GENMASK(31, 31) +/* HW_PARAM_2 register */ /* IPA v3.5.1+ */ +enum gsi_hw_param_2_field_id { + IRAM_SIZE, + NUM_CH_PER_EE, + NUM_EV_PER_EE, /* Not IPA v5.0+ */ + GSI_CH_PEND_TRANSLATE, + GSI_CH_FULL_LOGIC, + GSI_USE_SDMA, /* IPA v4.0+ */ + GSI_SDMA_N_INT, /* IPA v4.0+ */ + GSI_SDMA_MAX_BURST, /* IPA v4.0+ */ + GSI_SDMA_N_IOVEC, /* IPA v4.0+ */ + GSI_USE_RD_WR_ENG, /* IPA v4.2+ */ + GSI_USE_INTER_EE, /* IPA v4.2+ */ +}; /** enum gsi_iram_size - IRAM_SIZE field values in HW_PARAM_2 */ enum gsi_iram_size { @@ -293,93 +248,66 @@ enum gsi_iram_size { IRAM_SIZE_FOUR_KB = 0x5, }; -/* IRQ condition for each type is cleared by writing type-specific register */ -#define GSI_CNTXT_TYPE_IRQ_OFFSET \ - (0x0001f080 + 0x4000 * GSI_EE_AP) -#define GSI_CNTXT_TYPE_IRQ_MSK_OFFSET \ - (0x0001f088 + 0x4000 * GSI_EE_AP) +/* HW_PARAM_4 register */ /* IPA v5.0+ */ +enum gsi_hw_param_4_field_id { + EV_PER_EE, + IRAM_PROTOCOL_COUNT, +}; -/* Values here are bit positions in the TYPE_IRQ and TYPE_IRQ_MSK registers */ +/** + * enum gsi_irq_type_id: GSI IRQ types + * @GSI_CH_CTRL: Channel allocation, deallocation, etc. + * @GSI_EV_CTRL: Event ring allocation, deallocation, etc. + * @GSI_GLOB_EE: Global/general event + * @GSI_IEOB: Transfer (TRE) completion + * @GSI_INTER_EE_CH_CTRL: Remote-issued stop/reset (unused) + * @GSI_INTER_EE_EV_CTRL: Remote-issued event reset (unused) + * @GSI_GENERAL: General hardware event (bus error, etc.) + */ enum gsi_irq_type_id { - GSI_CH_CTRL = 0x0, /* channel allocation, etc. */ - GSI_EV_CTRL = 0x1, /* event ring allocation, etc. */ - GSI_GLOB_EE = 0x2, /* global/general event */ - GSI_IEOB = 0x3, /* TRE completion */ - GSI_INTER_EE_CH_CTRL = 0x4, /* remote-issued stop/reset (unused) */ - GSI_INTER_EE_EV_CTRL = 0x5, /* remote-issued event reset (unused) */ - GSI_GENERAL = 0x6, /* general-purpose event */ + GSI_CH_CTRL = BIT(0), + GSI_EV_CTRL = BIT(1), + GSI_GLOB_EE = BIT(2), + GSI_IEOB = BIT(3), + GSI_INTER_EE_CH_CTRL = BIT(4), + GSI_INTER_EE_EV_CTRL = BIT(5), + GSI_GENERAL = BIT(6), + /* IRQ types 7-31 (and their bit values) are reserved */ }; -#define GSI_CNTXT_SRC_CH_IRQ_OFFSET \ - (0x0001f090 + 0x4000 * GSI_EE_AP) - -#define GSI_CNTXT_SRC_EV_CH_IRQ_OFFSET \ - (0x0001f094 + 0x4000 * GSI_EE_AP) - -#define GSI_CNTXT_SRC_CH_IRQ_MSK_OFFSET \ - (0x0001f098 + 0x4000 * GSI_EE_AP) - -#define GSI_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET \ - (0x0001f09c + 0x4000 * GSI_EE_AP) - -#define GSI_CNTXT_SRC_CH_IRQ_CLR_OFFSET \ - (0x0001f0a0 + 0x4000 * GSI_EE_AP) - -#define GSI_CNTXT_SRC_EV_CH_IRQ_CLR_OFFSET \ - (0x0001f0a4 + 0x4000 * GSI_EE_AP) - -#define GSI_CNTXT_SRC_IEOB_IRQ_OFFSET \ - (0x0001f0b0 + 0x4000 * GSI_EE_AP) - -#define GSI_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET \ - (0x0001f0b8 + 0x4000 * GSI_EE_AP) - -#define GSI_CNTXT_SRC_IEOB_IRQ_CLR_OFFSET \ - (0x0001f0c0 + 0x4000 * GSI_EE_AP) - -#define GSI_CNTXT_GLOB_IRQ_STTS_OFFSET \ - (0x0001f100 + 0x4000 * GSI_EE_AP) -#define GSI_CNTXT_GLOB_IRQ_EN_OFFSET \ - (0x0001f108 + 0x4000 * GSI_EE_AP) -#define GSI_CNTXT_GLOB_IRQ_CLR_OFFSET \ - (0x0001f110 + 0x4000 * GSI_EE_AP) -/* Values here are bit positions in the GLOB_IRQ_* registers */ +/** enum gsi_global_irq_id: Global GSI interrupt events */ enum gsi_global_irq_id { - ERROR_INT = 0x0, - GP_INT1 = 0x1, - GP_INT2 = 0x2, - GP_INT3 = 0x3, + ERROR_INT = BIT(0), + GP_INT1 = BIT(1), + GP_INT2 = BIT(2), + GP_INT3 = BIT(3), + /* Global IRQ types 4-31 (and their bit values) are reserved */ }; -#define GSI_CNTXT_GSI_IRQ_STTS_OFFSET \ - (0x0001f118 + 0x4000 * GSI_EE_AP) -#define GSI_CNTXT_GSI_IRQ_EN_OFFSET \ - (0x0001f120 + 0x4000 * GSI_EE_AP) -#define GSI_CNTXT_GSI_IRQ_CLR_OFFSET \ - (0x0001f128 + 0x4000 * GSI_EE_AP) -/* Values here are bit positions in the (general) GSI_IRQ_* registers */ -enum gsi_general_id { - BREAK_POINT = 0x0, - BUS_ERROR = 0x1, - CMD_FIFO_OVRFLOW = 0x2, - MCS_STACK_OVRFLOW = 0x3, +/** enum gsi_general_irq_id: GSI general IRQ conditions */ +enum gsi_general_irq_id { + BREAK_POINT = BIT(0), + BUS_ERROR = BIT(1), + CMD_FIFO_OVRFLOW = BIT(2), + MCS_STACK_OVRFLOW = BIT(3), + /* General IRQ types 4-31 (and their bit values) are reserved */ }; -#define GSI_CNTXT_INTSET_OFFSET \ - (0x0001f180 + 0x4000 * GSI_EE_AP) -#define INTYPE_FMASK GENMASK(0, 0) - -#define GSI_ERROR_LOG_OFFSET \ - (0x0001f200 + 0x4000 * GSI_EE_AP) +/* CNTXT_INTSET register */ +enum gsi_cntxt_intset_field_id { + INTYPE, +}; -/* Fields below are present for IPA v3.5.1 and above */ -#define ERR_ARG3_FMASK GENMASK(3, 0) -#define ERR_ARG2_FMASK GENMASK(7, 4) -#define ERR_ARG1_FMASK GENMASK(11, 8) -#define ERR_CODE_FMASK GENMASK(15, 12) -#define ERR_VIRT_IDX_FMASK GENMASK(23, 19) -#define ERR_TYPE_FMASK GENMASK(27, 24) -#define ERR_EE_FMASK GENMASK(31, 28) +/* ERROR_LOG register */ +enum gsi_error_log_field_id { + ERR_ARG3, + ERR_ARG2, + ERR_ARG1, + ERR_CODE, + ERR_VIRT_IDX, + ERR_TYPE, + ERR_EE, +}; /** enum gsi_err_code - ERR_CODE field values in EE_ERR_LOG */ enum gsi_err_code { @@ -400,13 +328,11 @@ enum gsi_err_type { GSI_ERR_TYPE_EVT = 0x3, }; -#define GSI_ERROR_LOG_CLR_OFFSET \ - (0x0001f210 + 0x4000 * GSI_EE_AP) - -#define GSI_CNTXT_SCRATCH_0_OFFSET \ - (0x0001f400 + 0x4000 * GSI_EE_AP) -#define INTER_EE_RESULT_FMASK GENMASK(2, 0) -#define GENERIC_EE_RESULT_FMASK GENMASK(7, 5) +/* CNTXT_SCRATCH_0 register */ +enum gsi_cntxt_scratch_0_field_id { + INTER_EE_RESULT, + GENERIC_EE_RESULT, +}; /** enum gsi_generic_ee_result - GENERIC_EE_RESULT field values in SCRATCH_0 */ enum gsi_generic_ee_result { @@ -419,4 +345,34 @@ enum gsi_generic_ee_result { GENERIC_EE_NO_RESOURCES = 0x7, }; +extern const struct regs gsi_regs_v3_1; +extern const struct regs gsi_regs_v3_5_1; +extern const struct regs gsi_regs_v4_0; +extern const struct regs gsi_regs_v4_5; +extern const struct regs gsi_regs_v4_9; +extern const struct regs gsi_regs_v4_11; + +/** + * gsi_reg() - Return the structure describing a GSI register + * @gsi: GSI pointer + * @reg_id: GSI register ID + */ +const struct reg *gsi_reg(struct gsi *gsi, enum gsi_reg_id reg_id); + +/** + * gsi_reg_init() - Perform GSI register initialization + * @gsi: GSI pointer + * @pdev: GSI (IPA) platform device + * + * Initialize GSI registers, including looking up and I/O mapping + * the "gsi" memory space. + */ +int gsi_reg_init(struct gsi *gsi, struct platform_device *pdev); + +/** + * gsi_reg_exit() - Inverse of gsi_reg_init() + * @gsi: GSI pointer + */ +void gsi_reg_exit(struct gsi *gsi); + #endif /* _GSI_REG_H_ */ diff --git a/drivers/net/ipa/gsi_trans.c b/drivers/net/ipa/gsi_trans.c index 26b7f683a3e1..0f52c068c46d 100644 --- a/drivers/net/ipa/gsi_trans.c +++ b/drivers/net/ipa/gsi_trans.c @@ -87,6 +87,7 @@ struct gsi_tre { int gsi_trans_pool_init(struct gsi_trans_pool *pool, size_t size, u32 count, u32 max_alloc) { + size_t alloc_size; void *virt; if (!size) @@ -103,13 +104,15 @@ int gsi_trans_pool_init(struct gsi_trans_pool *pool, size_t size, u32 count, * If there aren't enough entries starting at the free index, * we just allocate free entries from the beginning of the pool. */ - virt = kcalloc(count + max_alloc - 1, size, GFP_KERNEL); + alloc_size = size_mul(count + max_alloc - 1, size); + alloc_size = kmalloc_size_roundup(alloc_size); + virt = kzalloc(alloc_size, GFP_KERNEL); if (!virt) return -ENOMEM; pool->base = virt; /* If the allocator gave us any extra memory, use it */ - pool->count = ksize(pool->base) / size; + pool->count = alloc_size / size; pool->free = 0; pool->max_alloc = max_alloc; pool->size = size; diff --git a/drivers/net/ipa/ipa.h b/drivers/net/ipa/ipa.h index 09ead433ec38..f3355e040a9e 100644 --- a/drivers/net/ipa/ipa.h +++ b/drivers/net/ipa/ipa.h @@ -39,10 +39,12 @@ struct ipa_interrupt; * @power: IPA power information * @table_addr: DMA address of filter/route table content * @table_virt: Virtual address of filter/route table content + * @route_count: Total number of entries in a routing table + * @modem_route_count: Number of modem entries in a routing table + * @filter_count: Maximum number of entries in a filter table * @interrupt: IPA Interrupt information * @uc_powered: true if power is active by proxy for microcontroller * @uc_loaded: true after microcontroller has reported it's ready - * @reg_addr: DMA address used for IPA register access * @reg_virt: Virtual address used for IPA register access * @regs: IPA register definitions * @mem_addr: DMA address of IPA-local memory space @@ -58,11 +60,13 @@ struct ipa_interrupt; * @zero_addr: DMA address of preallocated zero-filled memory * @zero_virt: Virtual address of preallocated zero-filled memory * @zero_size: Size (bytes) of preallocated zero-filled memory - * @available: Bit mask indicating endpoints hardware supports - * @filter_map: Bit mask indicating endpoints that support filtering - * @initialized: Bit mask indicating endpoints initialized - * @set_up: Bit mask indicating endpoints set up - * @enabled: Bit mask indicating endpoints enabled + * @endpoint_count: Number of defined bits in most bitmaps below + * @available_count: Number of defined bits in the available bitmap + * @defined: Bitmap of endpoints defined in config data + * @available: Bitmap of endpoints supported by hardware + * @filtered: Bitmap of endpoints that support filtering + * @set_up: Bitmap of endpoints that are set up for use + * @enabled: Bitmap of currently enabled endpoints * @modem_tx_count: Number of defined modem TX endoints * @endpoint: Array of endpoint information * @channel_map: Mapping of GSI channel to IPA endpoint @@ -84,14 +88,16 @@ struct ipa { dma_addr_t table_addr; __le64 *table_virt; + u32 route_count; + u32 modem_route_count; + u32 filter_count; struct ipa_interrupt *interrupt; bool uc_powered; bool uc_loaded; - dma_addr_t reg_addr; void __iomem *reg_virt; - const struct ipa_regs *regs; + const struct regs *regs; dma_addr_t mem_addr; void *mem_virt; @@ -110,12 +116,14 @@ struct ipa { void *zero_virt; size_t zero_size; - /* Bit masks indicating endpoint state */ - u32 available; /* supported by hardware */ - u32 filter_map; - u32 initialized; - u32 set_up; - u32 enabled; + /* Bitmaps indicating endpoint state */ + u32 endpoint_count; + u32 available_count; + unsigned long *defined; /* Defined in configuration data */ + unsigned long *available; /* Supported by hardware */ + u64 filtered; /* Support filtering (AP and modem) */ + unsigned long *set_up; + unsigned long *enabled; u32 modem_tx_count; struct ipa_endpoint endpoint[IPA_ENDPOINT_MAX]; diff --git a/drivers/net/ipa/ipa_cmd.c b/drivers/net/ipa/ipa_cmd.c index 26c3db9f52b1..f1419fbd776c 100644 --- a/drivers/net/ipa/ipa_cmd.c +++ b/drivers/net/ipa/ipa_cmd.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. - * Copyright (C) 2019-2022 Linaro Ltd. + * Copyright (C) 2019-2023 Linaro Ltd. */ #include <linux/types.h> @@ -94,11 +94,11 @@ struct ipa_cmd_register_write { /* IPA_CMD_IP_PACKET_INIT */ struct ipa_cmd_ip_packet_init { - u8 dest_endpoint; + u8 dest_endpoint; /* Full 8 bits used for IPA v5.0+ */ u8 reserved[7]; }; -/* Field masks for ipa_cmd_ip_packet_init dest_endpoint field */ +/* Field mask for ipa_cmd_ip_packet_init dest_endpoint field (unused v5.0+) */ #define IPA_PACKET_INIT_DEST_ENDPOINT_FMASK GENMASK(4, 0) /* IPA_CMD_DMA_SHARED_MEM */ @@ -145,44 +145,45 @@ union ipa_cmd_payload { static void ipa_cmd_validate_build(void) { - /* The sizes of a filter and route tables need to fit into fields - * in the ipa_cmd_hw_ip_fltrt_init structure. Although hashed tables + /* The size of a filter table needs to fit into fields in the + * ipa_cmd_hw_ip_fltrt_init structure. Although hashed tables * might not be used, non-hashed and hashed tables have the same * maximum size. IPv4 and IPv6 filter tables have the same number - * of entries, as and IPv4 and IPv6 route tables have the same number * of entries. */ -#define TABLE_SIZE (TABLE_COUNT_MAX * sizeof(__le64)) -#define TABLE_COUNT_MAX max_t(u32, IPA_ROUTE_COUNT_MAX, IPA_FILTER_COUNT_MAX) - BUILD_BUG_ON(TABLE_SIZE > field_max(IP_FLTRT_FLAGS_HASH_SIZE_FMASK)); - BUILD_BUG_ON(TABLE_SIZE > field_max(IP_FLTRT_FLAGS_NHASH_SIZE_FMASK)); -#undef TABLE_COUNT_MAX -#undef TABLE_SIZE - /* Hashed and non-hashed fields are assumed to be the same size */ BUILD_BUG_ON(field_max(IP_FLTRT_FLAGS_HASH_SIZE_FMASK) != field_max(IP_FLTRT_FLAGS_NHASH_SIZE_FMASK)); BUILD_BUG_ON(field_max(IP_FLTRT_FLAGS_HASH_ADDR_FMASK) != field_max(IP_FLTRT_FLAGS_NHASH_ADDR_FMASK)); - /* Valid endpoint numbers must fit in the IP packet init command */ - BUILD_BUG_ON(field_max(IPA_PACKET_INIT_DEST_ENDPOINT_FMASK) < - IPA_ENDPOINT_MAX - 1); + /* Prior to IPA v5.0, we supported no more than 32 endpoints, + * and this was reflected in some 5-bit fields that held + * endpoint numbers. Starting with IPA v5.0, the widths of + * these fields were extended to 8 bits, meaning up to 256 + * endpoints. If the driver claims to support more than + * that it's an error. + */ + BUILD_BUG_ON(IPA_ENDPOINT_MAX - 1 > U8_MAX); } /* Validate a memory region holding a table */ -bool ipa_cmd_table_valid(struct ipa *ipa, const struct ipa_mem *mem, bool route) +bool ipa_cmd_table_init_valid(struct ipa *ipa, const struct ipa_mem *mem, + bool route) { u32 offset_max = field_max(IP_FLTRT_FLAGS_NHASH_ADDR_FMASK); u32 size_max = field_max(IP_FLTRT_FLAGS_NHASH_SIZE_FMASK); const char *table = route ? "route" : "filter"; struct device *dev = &ipa->pdev->dev; + u32 size; + + size = route ? ipa->route_count : ipa->filter_count + 1; + size *= sizeof(__le64); /* Size must fit in the immediate command field that holds it */ - if (mem->size > size_max) { + if (size > size_max) { dev_err(dev, "%s table region size too large\n", table); - dev_err(dev, " (0x%04x > 0x%04x)\n", - mem->size, size_max); + dev_err(dev, " (0x%04x > 0x%04x)\n", size, size_max); return false; } @@ -197,21 +198,11 @@ bool ipa_cmd_table_valid(struct ipa *ipa, const struct ipa_mem *mem, bool route) return false; } - /* Entire memory range must fit within IPA-local memory */ - if (mem->offset > ipa->mem_size || - mem->size > ipa->mem_size - mem->offset) { - dev_err(dev, "%s table region out of range\n", table); - dev_err(dev, " (0x%04x + 0x%04x > 0x%04x)\n", - mem->offset, mem->size, ipa->mem_size); - - return false; - } - return true; } /* Validate the memory region that holds headers */ -static bool ipa_cmd_header_valid(struct ipa *ipa) +static bool ipa_cmd_header_init_local_valid(struct ipa *ipa) { struct device *dev = &ipa->pdev->dev; const struct ipa_mem *mem; @@ -257,15 +248,6 @@ static bool ipa_cmd_header_valid(struct ipa *ipa) return false; } - /* Make sure the entire combined area fits in IPA memory */ - if (size > ipa->mem_size || offset > ipa->mem_size - size) { - dev_err(dev, "header table region out of range\n"); - dev_err(dev, " (0x%04x + 0x%04x > 0x%04x)\n", - offset, size, ipa->mem_size); - - return false; - } - return true; } @@ -305,7 +287,7 @@ static bool ipa_cmd_register_write_offset_valid(struct ipa *ipa, /* Check whether offsets passed to register_write are valid */ static bool ipa_cmd_register_write_valid(struct ipa *ipa) { - const struct ipa_reg *reg; + const struct reg *reg; const char *name; u32 offset; @@ -313,8 +295,12 @@ static bool ipa_cmd_register_write_valid(struct ipa *ipa) * offset will fit in a register write IPA immediate command. */ if (ipa_table_hash_support(ipa)) { - reg = ipa_reg(ipa, FILT_ROUT_HASH_FLUSH); - offset = ipa_reg_offset(reg); + if (ipa->version < IPA_VERSION_5_0) + reg = ipa_reg(ipa, FILT_ROUT_HASH_FLUSH); + else + reg = ipa_reg(ipa, FILT_ROUT_CACHE_FLUSH); + + offset = reg_offset(reg); name = "filter/route hash flush"; if (!ipa_cmd_register_write_offset_valid(ipa, name, offset)) return false; @@ -328,7 +314,7 @@ static bool ipa_cmd_register_write_valid(struct ipa *ipa) * fits in the register write command field(s) that must hold it. */ reg = ipa_reg(ipa, ENDP_STATUS); - offset = ipa_reg_n_offset(reg, IPA_ENDPOINT_COUNT - 1); + offset = reg_n_offset(reg, IPA_ENDPOINT_COUNT - 1); name = "maximal endpoint status"; if (!ipa_cmd_register_write_offset_valid(ipa, name, offset)) return false; @@ -336,26 +322,11 @@ static bool ipa_cmd_register_write_valid(struct ipa *ipa) return true; } -bool ipa_cmd_data_valid(struct ipa *ipa) -{ - if (!ipa_cmd_header_valid(ipa)) - return false; - - if (!ipa_cmd_register_write_valid(ipa)) - return false; - - return true; -} - - int ipa_cmd_pool_init(struct gsi_channel *channel, u32 tre_max) { struct gsi_trans_info *trans_info = &channel->trans_info; struct device *dev = channel->gsi->dev; - /* This is as good a place as any to validate build constants */ - ipa_cmd_validate_build(); - /* Command payloads are allocated one at a time, but a single * transaction can require up to the maximum supported by the * channel; treat them as if they were allocated all at once. @@ -524,8 +495,13 @@ static void ipa_cmd_ip_packet_init_add(struct gsi_trans *trans, u8 endpoint_id) cmd_payload = ipa_cmd_payload_alloc(ipa, &payload_addr); payload = &cmd_payload->ip_packet_init; - payload->dest_endpoint = u8_encode_bits(endpoint_id, - IPA_PACKET_INIT_DEST_ENDPOINT_FMASK); + if (ipa->version < IPA_VERSION_5_0) { + payload->dest_endpoint = + u8_encode_bits(endpoint_id, + IPA_PACKET_INIT_DEST_ENDPOINT_FMASK); + } else { + payload->dest_endpoint = endpoint_id; + } gsi_trans_cmd_add(trans, payload, sizeof(*payload), payload_addr, opcode); @@ -655,3 +631,17 @@ struct gsi_trans *ipa_cmd_trans_alloc(struct ipa *ipa, u32 tre_count) return gsi_channel_trans_alloc(&ipa->gsi, endpoint->channel_id, tre_count, DMA_NONE); } + +/* Init function for immediate commands; there is no ipa_cmd_exit() */ +int ipa_cmd_init(struct ipa *ipa) +{ + ipa_cmd_validate_build(); + + if (!ipa_cmd_header_init_local_valid(ipa)) + return -EINVAL; + + if (!ipa_cmd_register_write_valid(ipa)) + return -EINVAL; + + return 0; +} diff --git a/drivers/net/ipa/ipa_cmd.h b/drivers/net/ipa/ipa_cmd.h index 8e4243c1f0bb..e2cf1c2b0ef2 100644 --- a/drivers/net/ipa/ipa_cmd.h +++ b/drivers/net/ipa/ipa_cmd.h @@ -47,15 +47,15 @@ enum ipa_cmd_opcode { }; /** - * ipa_cmd_table_valid() - Validate a memory region holding a table + * ipa_cmd_table_init_valid() - Validate a memory region holding a table * @ipa: - IPA pointer * @mem: - IPA memory region descriptor * @route: - Whether the region holds a route or filter table * * Return: true if region is valid, false otherwise */ -bool ipa_cmd_table_valid(struct ipa *ipa, const struct ipa_mem *mem, - bool route); +bool ipa_cmd_table_init_valid(struct ipa *ipa, const struct ipa_mem *mem, + bool route); /** * ipa_cmd_data_valid() - Validate command-realted configuration is valid @@ -162,4 +162,14 @@ void ipa_cmd_pipeline_clear_wait(struct ipa *ipa); */ struct gsi_trans *ipa_cmd_trans_alloc(struct ipa *ipa, u32 tre_count); +/** + * ipa_cmd_init() - Initialize IPA immediate commands + * @ipa: - IPA pointer + * + * Return: 0 if successful, or a negative error code + * + * There is no need for a matching ipa_cmd_exit() function. + */ +int ipa_cmd_init(struct ipa *ipa); + #endif /* _IPA_CMD_H_ */ diff --git a/drivers/net/ipa/ipa_data.h b/drivers/net/ipa/ipa_data.h index e5a6ce75c7dd..818e64114ed5 100644 --- a/drivers/net/ipa/ipa_data.h +++ b/drivers/net/ipa/ipa_data.h @@ -222,6 +222,7 @@ struct ipa_power_data { * @backward_compat: BCR register value (prior to IPA v4.5 only) * @qsb_count: number of entries in the qsb_data array * @qsb_data: Qualcomm System Bus configuration data + * @modem_route_count: number of modem entries in a routing table * @endpoint_count: number of entries in the endpoint_data array * @endpoint_data: IPA endpoint/GSI channel data * @resource_data: IPA resource configuration data @@ -233,6 +234,7 @@ struct ipa_data { u32 backward_compat; u32 qsb_count; /* number of entries in qsb_data[] */ const struct ipa_qsb_data *qsb_data; + u32 modem_route_count; u32 endpoint_count; /* number of entries in endpoint_data[] */ const struct ipa_gsi_endpoint_data *endpoint_data; const struct ipa_resource_data *resource_data; @@ -244,6 +246,7 @@ extern const struct ipa_data ipa_data_v3_1; extern const struct ipa_data ipa_data_v3_5_1; extern const struct ipa_data ipa_data_v4_2; extern const struct ipa_data ipa_data_v4_5; +extern const struct ipa_data ipa_data_v4_7; extern const struct ipa_data ipa_data_v4_9; extern const struct ipa_data ipa_data_v4_11; diff --git a/drivers/net/ipa/ipa_endpoint.c b/drivers/net/ipa/ipa_endpoint.c index 093e11ec7c2d..2ee80ed140b7 100644 --- a/drivers/net/ipa/ipa_endpoint.c +++ b/drivers/net/ipa/ipa_endpoint.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. - * Copyright (C) 2019-2022 Linaro Ltd. + * Copyright (C) 2019-2023 Linaro Ltd. */ #include <linux/types.h> @@ -34,41 +34,181 @@ #define IPA_ENDPOINT_RESET_AGGR_RETRY_MAX 3 -/** enum ipa_status_opcode - status element opcode hardware values */ -enum ipa_status_opcode { - IPA_STATUS_OPCODE_PACKET = 0x01, - IPA_STATUS_OPCODE_DROPPED_PACKET = 0x04, - IPA_STATUS_OPCODE_SUSPENDED_PACKET = 0x08, - IPA_STATUS_OPCODE_PACKET_2ND_PASS = 0x40, +/** enum ipa_status_opcode - IPA status opcode field hardware values */ +enum ipa_status_opcode { /* *Not* a bitmask */ + IPA_STATUS_OPCODE_PACKET = 1, + IPA_STATUS_OPCODE_NEW_RULE_PACKET = 2, + IPA_STATUS_OPCODE_DROPPED_PACKET = 4, + IPA_STATUS_OPCODE_SUSPENDED_PACKET = 8, + IPA_STATUS_OPCODE_LOG = 16, + IPA_STATUS_OPCODE_DCMP = 32, + IPA_STATUS_OPCODE_PACKET_2ND_PASS = 64, }; -/** enum ipa_status_exception - status element exception type */ -enum ipa_status_exception { +/** enum ipa_status_exception - IPA status exception field hardware values */ +enum ipa_status_exception { /* *Not* a bitmask */ /* 0 means no exception */ - IPA_STATUS_EXCEPTION_DEAGGR = 0x01, + IPA_STATUS_EXCEPTION_DEAGGR = 1, + IPA_STATUS_EXCEPTION_IPTYPE = 4, + IPA_STATUS_EXCEPTION_PACKET_LENGTH = 8, + IPA_STATUS_EXCEPTION_FRAG_RULE_MISS = 16, + IPA_STATUS_EXCEPTION_SW_FILTER = 32, + IPA_STATUS_EXCEPTION_NAT = 64, /* IPv4 */ + IPA_STATUS_EXCEPTION_IPV6_CONN_TRACK = 64, /* IPv6 */ + IPA_STATUS_EXCEPTION_UC = 128, + IPA_STATUS_EXCEPTION_INVALID_ENDPOINT = 129, + IPA_STATUS_EXCEPTION_HEADER_INSERT = 136, + IPA_STATUS_EXCEPTION_CHEKCSUM = 229, }; -/* Status element provided by hardware */ -struct ipa_status { - u8 opcode; /* enum ipa_status_opcode */ - u8 exception; /* enum ipa_status_exception */ - __le16 mask; - __le16 pkt_len; - u8 endp_src_idx; - u8 endp_dst_idx; - __le32 metadata; - __le32 flags1; - __le64 flags2; - __le32 flags3; - __le32 flags4; +/** enum ipa_status_mask - IPA status mask field bitmask hardware values */ +enum ipa_status_mask { + IPA_STATUS_MASK_FRAG_PROCESS = BIT(0), + IPA_STATUS_MASK_FILT_PROCESS = BIT(1), + IPA_STATUS_MASK_NAT_PROCESS = BIT(2), + IPA_STATUS_MASK_ROUTE_PROCESS = BIT(3), + IPA_STATUS_MASK_TAG_VALID = BIT(4), + IPA_STATUS_MASK_FRAGMENT = BIT(5), + IPA_STATUS_MASK_FIRST_FRAGMENT = BIT(6), + IPA_STATUS_MASK_V4 = BIT(7), + IPA_STATUS_MASK_CKSUM_PROCESS = BIT(8), + IPA_STATUS_MASK_AGGR_PROCESS = BIT(9), + IPA_STATUS_MASK_DEST_EOT = BIT(10), + IPA_STATUS_MASK_DEAGGR_PROCESS = BIT(11), + IPA_STATUS_MASK_DEAGG_FIRST = BIT(12), + IPA_STATUS_MASK_SRC_EOT = BIT(13), + IPA_STATUS_MASK_PREV_EOT = BIT(14), + IPA_STATUS_MASK_BYTE_LIMIT = BIT(15), }; -/* Field masks for struct ipa_status structure fields */ -#define IPA_STATUS_MASK_TAG_VALID_FMASK GENMASK(4, 4) -#define IPA_STATUS_SRC_IDX_FMASK GENMASK(4, 0) -#define IPA_STATUS_DST_IDX_FMASK GENMASK(4, 0) -#define IPA_STATUS_FLAGS1_RT_RULE_ID_FMASK GENMASK(31, 22) -#define IPA_STATUS_FLAGS2_TAG_FMASK GENMASK_ULL(63, 16) +/* Special IPA filter/router rule field value indicating "rule miss" */ +#define IPA_STATUS_RULE_MISS 0x3ff /* 10-bit filter/router rule fields */ + +/** The IPA status nat_type field uses enum ipa_nat_type hardware values */ + +/* enum ipa_status_field_id - IPA packet status structure field identifiers */ +enum ipa_status_field_id { + STATUS_OPCODE, /* enum ipa_status_opcode */ + STATUS_EXCEPTION, /* enum ipa_status_exception */ + STATUS_MASK, /* enum ipa_status_mask (bitmask) */ + STATUS_LENGTH, + STATUS_SRC_ENDPOINT, + STATUS_DST_ENDPOINT, + STATUS_METADATA, + STATUS_FILTER_LOCAL, /* Boolean */ + STATUS_FILTER_HASH, /* Boolean */ + STATUS_FILTER_GLOBAL, /* Boolean */ + STATUS_FILTER_RETAIN, /* Boolean */ + STATUS_FILTER_RULE_INDEX, + STATUS_ROUTER_LOCAL, /* Boolean */ + STATUS_ROUTER_HASH, /* Boolean */ + STATUS_UCP, /* Boolean */ + STATUS_ROUTER_TABLE, + STATUS_ROUTER_RULE_INDEX, + STATUS_NAT_HIT, /* Boolean */ + STATUS_NAT_INDEX, + STATUS_NAT_TYPE, /* enum ipa_nat_type */ + STATUS_TAG_LOW32, /* Low-order 32 bits of 48-bit tag */ + STATUS_TAG_HIGH16, /* High-order 16 bits of 48-bit tag */ + STATUS_SEQUENCE, + STATUS_TIME_OF_DAY, + STATUS_HEADER_LOCAL, /* Boolean */ + STATUS_HEADER_OFFSET, + STATUS_FRAG_HIT, /* Boolean */ + STATUS_FRAG_RULE_INDEX, +}; + +/* Size in bytes of an IPA packet status structure */ +#define IPA_STATUS_SIZE sizeof(__le32[4]) + +/* IPA status structure decoder; looks up field values for a structure */ +static u32 ipa_status_extract(struct ipa *ipa, const void *data, + enum ipa_status_field_id field) +{ + enum ipa_version version = ipa->version; + const __le32 *word = data; + + switch (field) { + case STATUS_OPCODE: + return le32_get_bits(word[0], GENMASK(7, 0)); + case STATUS_EXCEPTION: + return le32_get_bits(word[0], GENMASK(15, 8)); + case STATUS_MASK: + return le32_get_bits(word[0], GENMASK(31, 16)); + case STATUS_LENGTH: + return le32_get_bits(word[1], GENMASK(15, 0)); + case STATUS_SRC_ENDPOINT: + if (version < IPA_VERSION_5_0) + return le32_get_bits(word[1], GENMASK(20, 16)); + return le32_get_bits(word[1], GENMASK(23, 16)); + /* Status word 1, bits 21-23 are reserved (not IPA v5.0+) */ + /* Status word 1, bits 24-26 are reserved (IPA v5.0+) */ + case STATUS_DST_ENDPOINT: + if (version < IPA_VERSION_5_0) + return le32_get_bits(word[1], GENMASK(28, 24)); + return le32_get_bits(word[7], GENMASK(23, 16)); + /* Status word 1, bits 29-31 are reserved */ + case STATUS_METADATA: + return le32_to_cpu(word[2]); + case STATUS_FILTER_LOCAL: + return le32_get_bits(word[3], GENMASK(0, 0)); + case STATUS_FILTER_HASH: + return le32_get_bits(word[3], GENMASK(1, 1)); + case STATUS_FILTER_GLOBAL: + return le32_get_bits(word[3], GENMASK(2, 2)); + case STATUS_FILTER_RETAIN: + return le32_get_bits(word[3], GENMASK(3, 3)); + case STATUS_FILTER_RULE_INDEX: + return le32_get_bits(word[3], GENMASK(13, 4)); + /* ROUTER_TABLE is in word 3, bits 14-21 (IPA v5.0+) */ + case STATUS_ROUTER_LOCAL: + if (version < IPA_VERSION_5_0) + return le32_get_bits(word[3], GENMASK(14, 14)); + return le32_get_bits(word[1], GENMASK(27, 27)); + case STATUS_ROUTER_HASH: + if (version < IPA_VERSION_5_0) + return le32_get_bits(word[3], GENMASK(15, 15)); + return le32_get_bits(word[1], GENMASK(28, 28)); + case STATUS_UCP: + if (version < IPA_VERSION_5_0) + return le32_get_bits(word[3], GENMASK(16, 16)); + return le32_get_bits(word[7], GENMASK(31, 31)); + case STATUS_ROUTER_TABLE: + if (version < IPA_VERSION_5_0) + return le32_get_bits(word[3], GENMASK(21, 17)); + return le32_get_bits(word[3], GENMASK(21, 14)); + case STATUS_ROUTER_RULE_INDEX: + return le32_get_bits(word[3], GENMASK(31, 22)); + case STATUS_NAT_HIT: + return le32_get_bits(word[4], GENMASK(0, 0)); + case STATUS_NAT_INDEX: + return le32_get_bits(word[4], GENMASK(13, 1)); + case STATUS_NAT_TYPE: + return le32_get_bits(word[4], GENMASK(15, 14)); + case STATUS_TAG_LOW32: + return le32_get_bits(word[4], GENMASK(31, 16)) | + (le32_get_bits(word[5], GENMASK(15, 0)) << 16); + case STATUS_TAG_HIGH16: + return le32_get_bits(word[5], GENMASK(31, 16)); + case STATUS_SEQUENCE: + return le32_get_bits(word[6], GENMASK(7, 0)); + case STATUS_TIME_OF_DAY: + return le32_get_bits(word[6], GENMASK(31, 8)); + case STATUS_HEADER_LOCAL: + return le32_get_bits(word[7], GENMASK(0, 0)); + case STATUS_HEADER_OFFSET: + return le32_get_bits(word[7], GENMASK(10, 1)); + case STATUS_FRAG_HIT: + return le32_get_bits(word[7], GENMASK(11, 11)); + case STATUS_FRAG_RULE_INDEX: + return le32_get_bits(word[7], GENMASK(15, 12)); + /* Status word 7, bits 16-30 are reserved */ + /* Status word 7, bit 31 is reserved (not IPA v5.0+) */ + default: + WARN(true, "%s: bad field_id %u\n", __func__, field); + return 0; + } +} /* Compute the aggregation size value to use for a given buffer size */ static u32 ipa_aggr_size_kb(u32 rx_buffer_size, bool aggr_hard_limit) @@ -101,7 +241,7 @@ static bool ipa_endpoint_data_valid_one(struct ipa *ipa, u32 count, if (!data->toward_ipa) { const struct ipa_endpoint_rx *rx_config; - const struct ipa_reg *reg; + const struct reg *reg; u32 buffer_size; u32 aggr_size; u32 limit; @@ -164,7 +304,7 @@ static bool ipa_endpoint_data_valid_one(struct ipa *ipa, u32 count, rx_config->aggr_hard_limit); reg = ipa_reg(ipa, ENDP_INIT_AGGR); - limit = ipa_reg_field_max(reg, BYTE_LIMIT); + limit = reg_field_max(reg, BYTE_LIMIT); if (aggr_size > limit) { dev_err(dev, "aggregated size too large for RX endpoint %u (%u KB > %u KB)\n", data->endpoint_id, aggr_size, limit); @@ -243,42 +383,47 @@ static bool ipa_endpoint_data_valid_one(struct ipa *ipa, u32 count, return true; } -static bool ipa_endpoint_data_valid(struct ipa *ipa, u32 count, - const struct ipa_gsi_endpoint_data *data) +/* Validate endpoint configuration data. Return max defined endpoint ID */ +static u32 ipa_endpoint_max(struct ipa *ipa, u32 count, + const struct ipa_gsi_endpoint_data *data) { const struct ipa_gsi_endpoint_data *dp = data; struct device *dev = &ipa->pdev->dev; enum ipa_endpoint_name name; + u32 max; if (count > IPA_ENDPOINT_COUNT) { dev_err(dev, "too many endpoints specified (%u > %u)\n", count, IPA_ENDPOINT_COUNT); - return false; + return 0; } /* Make sure needed endpoints have defined data */ if (ipa_gsi_endpoint_data_empty(&data[IPA_ENDPOINT_AP_COMMAND_TX])) { dev_err(dev, "command TX endpoint not defined\n"); - return false; + return 0; } if (ipa_gsi_endpoint_data_empty(&data[IPA_ENDPOINT_AP_LAN_RX])) { dev_err(dev, "LAN RX endpoint not defined\n"); - return false; + return 0; } if (ipa_gsi_endpoint_data_empty(&data[IPA_ENDPOINT_AP_MODEM_TX])) { dev_err(dev, "AP->modem TX endpoint not defined\n"); - return false; + return 0; } if (ipa_gsi_endpoint_data_empty(&data[IPA_ENDPOINT_AP_MODEM_RX])) { dev_err(dev, "AP<-modem RX endpoint not defined\n"); - return false; + return 0; } - for (name = 0; name < count; name++, dp++) + max = 0; + for (name = 0; name < count; name++, dp++) { if (!ipa_endpoint_data_valid_one(ipa, count, data, dp)) - return false; + return 0; + max = max_t(u32, max, dp->endpoint_id); + } - return true; + return max; } /* Allocate a transaction to use on a non-command endpoint */ @@ -302,7 +447,7 @@ static bool ipa_endpoint_init_ctrl(struct ipa_endpoint *endpoint, bool suspend_delay) { struct ipa *ipa = endpoint->ipa; - const struct ipa_reg *reg; + const struct reg *reg; u32 field_id; u32 offset; bool state; @@ -315,11 +460,11 @@ ipa_endpoint_init_ctrl(struct ipa_endpoint *endpoint, bool suspend_delay) WARN_ON(ipa->version >= IPA_VERSION_4_0); reg = ipa_reg(ipa, ENDP_INIT_CTRL); - offset = ipa_reg_n_offset(reg, endpoint->endpoint_id); + offset = reg_n_offset(reg, endpoint->endpoint_id); val = ioread32(ipa->reg_virt + offset); field_id = endpoint->toward_ipa ? ENDP_DELAY : ENDP_SUSPEND; - mask = ipa_reg_bit(reg, field_id); + mask = reg_bit(reg, field_id); state = !!(val & mask); @@ -345,29 +490,32 @@ ipa_endpoint_program_delay(struct ipa_endpoint *endpoint, bool enable) static bool ipa_endpoint_aggr_active(struct ipa_endpoint *endpoint) { - u32 mask = BIT(endpoint->endpoint_id); + u32 endpoint_id = endpoint->endpoint_id; struct ipa *ipa = endpoint->ipa; - const struct ipa_reg *reg; + u32 unit = endpoint_id / 32; + const struct reg *reg; u32 val; - WARN_ON(!(mask & ipa->available)); + WARN_ON(!test_bit(endpoint_id, ipa->available)); reg = ipa_reg(ipa, STATE_AGGR_ACTIVE); - val = ioread32(ipa->reg_virt + ipa_reg_offset(reg)); + val = ioread32(ipa->reg_virt + reg_n_offset(reg, unit)); - return !!(val & mask); + return !!(val & BIT(endpoint_id % 32)); } static void ipa_endpoint_force_close(struct ipa_endpoint *endpoint) { - u32 mask = BIT(endpoint->endpoint_id); + u32 endpoint_id = endpoint->endpoint_id; + u32 mask = BIT(endpoint_id % 32); struct ipa *ipa = endpoint->ipa; - const struct ipa_reg *reg; + u32 unit = endpoint_id / 32; + const struct reg *reg; - WARN_ON(!(mask & ipa->available)); + WARN_ON(!test_bit(endpoint_id, ipa->available)); reg = ipa_reg(ipa, AGGR_FORCE_CLOSE); - iowrite32(mask, ipa->reg_virt + ipa_reg_offset(reg)); + iowrite32(mask, ipa->reg_virt + reg_n_offset(reg, unit)); } /** @@ -426,10 +574,10 @@ ipa_endpoint_program_suspend(struct ipa_endpoint *endpoint, bool enable) */ void ipa_endpoint_modem_pause_all(struct ipa *ipa, bool enable) { - u32 endpoint_id; + u32 endpoint_id = 0; - for (endpoint_id = 0; endpoint_id < IPA_ENDPOINT_MAX; endpoint_id++) { - struct ipa_endpoint *endpoint = &ipa->endpoint[endpoint_id]; + while (endpoint_id < ipa->endpoint_count) { + struct ipa_endpoint *endpoint = &ipa->endpoint[endpoint_id++]; if (endpoint->ee_id != GSI_EE_MODEM) continue; @@ -448,8 +596,8 @@ void ipa_endpoint_modem_pause_all(struct ipa *ipa, bool enable) /* Reset all modem endpoints to use the default exception endpoint */ int ipa_endpoint_modem_exception_reset_all(struct ipa *ipa) { - u32 initialized = ipa->initialized; struct gsi_trans *trans; + u32 endpoint_id; u32 count; /* We need one command per modem TX endpoint, plus the commands @@ -463,21 +611,18 @@ int ipa_endpoint_modem_exception_reset_all(struct ipa *ipa) return -EBUSY; } - while (initialized) { - u32 endpoint_id = __ffs(initialized); + for_each_set_bit(endpoint_id, ipa->defined, ipa->endpoint_count) { struct ipa_endpoint *endpoint; - const struct ipa_reg *reg; + const struct reg *reg; u32 offset; - initialized ^= BIT(endpoint_id); - /* We only reset modem TX endpoints */ endpoint = &ipa->endpoint[endpoint_id]; if (!(endpoint->ee_id == GSI_EE_MODEM && endpoint->toward_ipa)) continue; reg = ipa_reg(ipa, ENDP_STATUS); - offset = ipa_reg_n_offset(reg, endpoint_id); + offset = reg_n_offset(reg, endpoint_id); /* Value written is 0, and all bits are updated. That * means status is disabled on the endpoint, and as a @@ -500,7 +645,7 @@ static void ipa_endpoint_init_cfg(struct ipa_endpoint *endpoint) u32 endpoint_id = endpoint->endpoint_id; struct ipa *ipa = endpoint->ipa; enum ipa_cs_offload_en enabled; - const struct ipa_reg *reg; + const struct reg *reg; u32 val = 0; reg = ipa_reg(ipa, ENDP_INIT_CFG); @@ -513,7 +658,7 @@ static void ipa_endpoint_init_cfg(struct ipa_endpoint *endpoint) /* Checksum header offset is in 4-byte units */ off = sizeof(struct rmnet_map_header) / sizeof(u32); - val |= ipa_reg_encode(reg, CS_METADATA_HDR_OFFSET, off); + val |= reg_encode(reg, CS_METADATA_HDR_OFFSET, off); enabled = version < IPA_VERSION_4_5 ? IPA_CS_OFFLOAD_UL @@ -526,26 +671,26 @@ static void ipa_endpoint_init_cfg(struct ipa_endpoint *endpoint) } else { enabled = IPA_CS_OFFLOAD_NONE; } - val |= ipa_reg_encode(reg, CS_OFFLOAD_EN, enabled); + val |= reg_encode(reg, CS_OFFLOAD_EN, enabled); /* CS_GEN_QMB_MASTER_SEL is 0 */ - iowrite32(val, ipa->reg_virt + ipa_reg_n_offset(reg, endpoint_id)); + iowrite32(val, ipa->reg_virt + reg_n_offset(reg, endpoint_id)); } static void ipa_endpoint_init_nat(struct ipa_endpoint *endpoint) { u32 endpoint_id = endpoint->endpoint_id; struct ipa *ipa = endpoint->ipa; - const struct ipa_reg *reg; + const struct reg *reg; u32 val; if (!endpoint->toward_ipa) return; reg = ipa_reg(ipa, ENDP_INIT_NAT); - val = ipa_reg_encode(reg, NAT_EN, IPA_NAT_BYPASS); + val = reg_encode(reg, NAT_EN, IPA_NAT_TYPE_BYPASS); - iowrite32(val, ipa->reg_virt + ipa_reg_n_offset(reg, endpoint_id)); + iowrite32(val, ipa->reg_virt + reg_n_offset(reg, endpoint_id)); } static u32 @@ -571,13 +716,13 @@ ipa_qmap_header_size(enum ipa_version version, struct ipa_endpoint *endpoint) /* Encoded value for ENDP_INIT_HDR register HDR_LEN* field(s) */ static u32 ipa_header_size_encode(enum ipa_version version, - const struct ipa_reg *reg, u32 header_size) + const struct reg *reg, u32 header_size) { - u32 field_max = ipa_reg_field_max(reg, HDR_LEN); + u32 field_max = reg_field_max(reg, HDR_LEN); u32 val; /* We know field_max can be used as a mask (2^n - 1) */ - val = ipa_reg_encode(reg, HDR_LEN, header_size & field_max); + val = reg_encode(reg, HDR_LEN, header_size & field_max); if (version < IPA_VERSION_4_5) { WARN_ON(header_size > field_max); return val; @@ -585,21 +730,21 @@ static u32 ipa_header_size_encode(enum ipa_version version, /* IPA v4.5 adds a few more most-significant bits */ header_size >>= hweight32(field_max); - WARN_ON(header_size > ipa_reg_field_max(reg, HDR_LEN_MSB)); - val |= ipa_reg_encode(reg, HDR_LEN_MSB, header_size); + WARN_ON(header_size > reg_field_max(reg, HDR_LEN_MSB)); + val |= reg_encode(reg, HDR_LEN_MSB, header_size); return val; } /* Encoded value for ENDP_INIT_HDR register OFST_METADATA* field(s) */ static u32 ipa_metadata_offset_encode(enum ipa_version version, - const struct ipa_reg *reg, u32 offset) + const struct reg *reg, u32 offset) { - u32 field_max = ipa_reg_field_max(reg, HDR_OFST_METADATA); + u32 field_max = reg_field_max(reg, HDR_OFST_METADATA); u32 val; /* We know field_max can be used as a mask (2^n - 1) */ - val = ipa_reg_encode(reg, HDR_OFST_METADATA, offset); + val = reg_encode(reg, HDR_OFST_METADATA, offset); if (version < IPA_VERSION_4_5) { WARN_ON(offset > field_max); return val; @@ -607,8 +752,8 @@ static u32 ipa_metadata_offset_encode(enum ipa_version version, /* IPA v4.5 adds a few more most-significant bits */ offset >>= hweight32(field_max); - WARN_ON(offset > ipa_reg_field_max(reg, HDR_OFST_METADATA_MSB)); - val |= ipa_reg_encode(reg, HDR_OFST_METADATA_MSB, offset); + WARN_ON(offset > reg_field_max(reg, HDR_OFST_METADATA_MSB)); + val |= reg_encode(reg, HDR_OFST_METADATA_MSB, offset); return val; } @@ -638,7 +783,7 @@ static void ipa_endpoint_init_hdr(struct ipa_endpoint *endpoint) { u32 endpoint_id = endpoint->endpoint_id; struct ipa *ipa = endpoint->ipa; - const struct ipa_reg *reg; + const struct reg *reg; u32 val = 0; reg = ipa_reg(ipa, ENDP_INIT_HDR); @@ -661,13 +806,13 @@ static void ipa_endpoint_init_hdr(struct ipa_endpoint *endpoint) off = offsetof(struct rmnet_map_header, pkt_len); /* Upper bits are stored in HDR_EXT with IPA v4.5 */ if (version >= IPA_VERSION_4_5) - off &= ipa_reg_field_max(reg, HDR_OFST_PKT_SIZE); + off &= reg_field_max(reg, HDR_OFST_PKT_SIZE); - val |= ipa_reg_bit(reg, HDR_OFST_PKT_SIZE_VALID); - val |= ipa_reg_encode(reg, HDR_OFST_PKT_SIZE, off); + val |= reg_bit(reg, HDR_OFST_PKT_SIZE_VALID); + val |= reg_encode(reg, HDR_OFST_PKT_SIZE, off); } /* For QMAP TX, metadata offset is 0 (modem assumes this) */ - val |= ipa_reg_bit(reg, HDR_OFST_METADATA_VALID); + val |= reg_bit(reg, HDR_OFST_METADATA_VALID); /* HDR_ADDITIONAL_CONST_LEN is 0; (RX only) */ /* HDR_A5_MUX is 0 */ @@ -675,7 +820,7 @@ static void ipa_endpoint_init_hdr(struct ipa_endpoint *endpoint) /* HDR_METADATA_REG_VALID is 0 (TX only, version < v4.5) */ } - iowrite32(val, ipa->reg_virt + ipa_reg_n_offset(reg, endpoint_id)); + iowrite32(val, ipa->reg_virt + reg_n_offset(reg, endpoint_id)); } static void ipa_endpoint_init_hdr_ext(struct ipa_endpoint *endpoint) @@ -683,13 +828,13 @@ static void ipa_endpoint_init_hdr_ext(struct ipa_endpoint *endpoint) u32 pad_align = endpoint->config.rx.pad_align; u32 endpoint_id = endpoint->endpoint_id; struct ipa *ipa = endpoint->ipa; - const struct ipa_reg *reg; + const struct reg *reg; u32 val = 0; reg = ipa_reg(ipa, ENDP_INIT_HDR_EXT); if (endpoint->config.qmap) { /* We have a header, so we must specify its endianness */ - val |= ipa_reg_bit(reg, HDR_ENDIANNESS); /* big endian */ + val |= reg_bit(reg, HDR_ENDIANNESS); /* big endian */ /* A QMAP header contains a 6 bit pad field at offset 0. * The RMNet driver assumes this field is meaningful in @@ -699,16 +844,16 @@ static void ipa_endpoint_init_hdr_ext(struct ipa_endpoint *endpoint) * (although 0) should be ignored. */ if (!endpoint->toward_ipa) { - val |= ipa_reg_bit(reg, HDR_TOTAL_LEN_OR_PAD_VALID); + val |= reg_bit(reg, HDR_TOTAL_LEN_OR_PAD_VALID); /* HDR_TOTAL_LEN_OR_PAD is 0 (pad, not total_len) */ - val |= ipa_reg_bit(reg, HDR_PAYLOAD_LEN_INC_PADDING); + val |= reg_bit(reg, HDR_PAYLOAD_LEN_INC_PADDING); /* HDR_TOTAL_LEN_OR_PAD_OFFSET is 0 */ } } /* HDR_PAYLOAD_LEN_INC_PADDING is 0 */ if (!endpoint->toward_ipa) - val |= ipa_reg_encode(reg, HDR_PAD_TO_ALIGNMENT, pad_align); + val |= reg_encode(reg, HDR_PAD_TO_ALIGNMENT, pad_align); /* IPA v4.5 adds some most-significant bits to a few fields, * two of which are defined in the HDR (not HDR_EXT) register. @@ -716,25 +861,25 @@ static void ipa_endpoint_init_hdr_ext(struct ipa_endpoint *endpoint) if (ipa->version >= IPA_VERSION_4_5) { /* HDR_TOTAL_LEN_OR_PAD_OFFSET is 0, so MSB is 0 */ if (endpoint->config.qmap && !endpoint->toward_ipa) { - u32 mask = ipa_reg_field_max(reg, HDR_OFST_PKT_SIZE); + u32 mask = reg_field_max(reg, HDR_OFST_PKT_SIZE); u32 off; /* Field offset within header */ off = offsetof(struct rmnet_map_header, pkt_len); /* Low bits are in the ENDP_INIT_HDR register */ off >>= hweight32(mask); - val |= ipa_reg_encode(reg, HDR_OFST_PKT_SIZE_MSB, off); + val |= reg_encode(reg, HDR_OFST_PKT_SIZE_MSB, off); /* HDR_ADDITIONAL_CONST_LEN is 0 so MSB is 0 */ } } - iowrite32(val, ipa->reg_virt + ipa_reg_n_offset(reg, endpoint_id)); + iowrite32(val, ipa->reg_virt + reg_n_offset(reg, endpoint_id)); } static void ipa_endpoint_init_hdr_metadata_mask(struct ipa_endpoint *endpoint) { u32 endpoint_id = endpoint->endpoint_id; struct ipa *ipa = endpoint->ipa; - const struct ipa_reg *reg; + const struct reg *reg; u32 val = 0; u32 offset; @@ -742,7 +887,7 @@ static void ipa_endpoint_init_hdr_metadata_mask(struct ipa_endpoint *endpoint) return; /* Register not valid for TX endpoints */ reg = ipa_reg(ipa, ENDP_INIT_HDR_METADATA_MASK); - offset = ipa_reg_n_offset(reg, endpoint_id); + offset = reg_n_offset(reg, endpoint_id); /* Note that HDR_ENDIANNESS indicates big endian header fields */ if (endpoint->config.qmap) @@ -754,7 +899,7 @@ static void ipa_endpoint_init_hdr_metadata_mask(struct ipa_endpoint *endpoint) static void ipa_endpoint_init_mode(struct ipa_endpoint *endpoint) { struct ipa *ipa = endpoint->ipa; - const struct ipa_reg *reg; + const struct reg *reg; u32 offset; u32 val; @@ -766,82 +911,90 @@ static void ipa_endpoint_init_mode(struct ipa_endpoint *endpoint) enum ipa_endpoint_name name = endpoint->config.dma_endpoint; u32 dma_endpoint_id = ipa->name_map[name]->endpoint_id; - val = ipa_reg_encode(reg, ENDP_MODE, IPA_DMA); - val |= ipa_reg_encode(reg, DEST_PIPE_INDEX, dma_endpoint_id); + val = reg_encode(reg, ENDP_MODE, IPA_DMA); + val |= reg_encode(reg, DEST_PIPE_INDEX, dma_endpoint_id); } else { - val = ipa_reg_encode(reg, ENDP_MODE, IPA_BASIC); + val = reg_encode(reg, ENDP_MODE, IPA_BASIC); } /* All other bits unspecified (and 0) */ - offset = ipa_reg_n_offset(reg, endpoint->endpoint_id); + offset = reg_n_offset(reg, endpoint->endpoint_id); iowrite32(val, ipa->reg_virt + offset); } -/* For IPA v4.5+, times are expressed using Qtime. The AP uses one of two - * pulse generators (0 and 1) to measure elapsed time. In ipa_qtime_config() - * they're configured to have granularity 100 usec and 1 msec, respectively. - * - * The return value is the positive or negative Qtime value to use to - * express the (microsecond) time provided. A positive return value - * means pulse generator 0 can be used; otherwise use pulse generator 1. +/* For IPA v4.5+, times are expressed using Qtime. A time is represented + * at one of several available granularities, which are configured in + * ipa_qtime_config(). Three (or, starting with IPA v5.0, four) pulse + * generators are set up with different "tick" periods. A Qtime value + * encodes a tick count along with an indication of a pulse generator + * (which has a fixed tick period). Two pulse generators are always + * available to the AP; a third is available starting with IPA v5.0. + * This function determines which pulse generator most accurately + * represents the time period provided, and returns the tick count to + * use to represent that time. */ -static int ipa_qtime_val(u32 microseconds, u32 max) -{ - u32 val; - - /* Use 100 microsecond granularity if possible */ - val = DIV_ROUND_CLOSEST(microseconds, 100); - if (val <= max) - return (int)val; - - /* Have to use pulse generator 1 (millisecond granularity) */ - val = DIV_ROUND_CLOSEST(microseconds, 1000); - WARN_ON(val > max); +static u32 +ipa_qtime_val(struct ipa *ipa, u32 microseconds, u32 max, u32 *select) +{ + u32 which = 0; + u32 ticks; + + /* Pulse generator 0 has 100 microsecond granularity */ + ticks = DIV_ROUND_CLOSEST(microseconds, 100); + if (ticks <= max) + goto out; + + /* Pulse generator 1 has millisecond granularity */ + which = 1; + ticks = DIV_ROUND_CLOSEST(microseconds, 1000); + if (ticks <= max) + goto out; + + if (ipa->version >= IPA_VERSION_5_0) { + /* Pulse generator 2 has 10 millisecond granularity */ + which = 2; + ticks = DIV_ROUND_CLOSEST(microseconds, 100); + } + WARN_ON(ticks > max); +out: + *select = which; - return (int)-val; + return ticks; } /* Encode the aggregation timer limit (microseconds) based on IPA version */ -static u32 aggr_time_limit_encode(struct ipa *ipa, const struct ipa_reg *reg, +static u32 aggr_time_limit_encode(struct ipa *ipa, const struct reg *reg, u32 microseconds) { + u32 ticks; u32 max; - u32 val; if (!microseconds) return 0; /* Nothing to compute if time limit is 0 */ - max = ipa_reg_field_max(reg, TIME_LIMIT); + max = reg_field_max(reg, TIME_LIMIT); if (ipa->version >= IPA_VERSION_4_5) { - u32 gran_sel; - int ret; - - /* Compute the Qtime limit value to use */ - ret = ipa_qtime_val(microseconds, max); - if (ret < 0) { - val = -ret; - gran_sel = ipa_reg_bit(reg, AGGR_GRAN_SEL); - } else { - val = ret; - gran_sel = 0; - } + u32 select; + + ticks = ipa_qtime_val(ipa, microseconds, max, &select); - return gran_sel | ipa_reg_encode(reg, TIME_LIMIT, val); + return reg_encode(reg, AGGR_GRAN_SEL, select) | + reg_encode(reg, TIME_LIMIT, ticks); } /* We program aggregation granularity in ipa_hardware_config() */ - val = DIV_ROUND_CLOSEST(microseconds, IPA_AGGR_GRANULARITY); - WARN(val > max, "aggr_time_limit too large (%u > %u usec)\n", + ticks = DIV_ROUND_CLOSEST(microseconds, IPA_AGGR_GRANULARITY); + WARN(ticks > max, "aggr_time_limit too large (%u > %u usec)\n", microseconds, max * IPA_AGGR_GRANULARITY); - return ipa_reg_encode(reg, TIME_LIMIT, val); + return reg_encode(reg, TIME_LIMIT, ticks); } static void ipa_endpoint_init_aggr(struct ipa_endpoint *endpoint) { u32 endpoint_id = endpoint->endpoint_id; struct ipa *ipa = endpoint->ipa; - const struct ipa_reg *reg; + const struct reg *reg; u32 val = 0; reg = ipa_reg(ipa, ENDP_INIT_AGGR); @@ -852,13 +1005,13 @@ static void ipa_endpoint_init_aggr(struct ipa_endpoint *endpoint) u32 limit; rx_config = &endpoint->config.rx; - val |= ipa_reg_encode(reg, AGGR_EN, IPA_ENABLE_AGGR); - val |= ipa_reg_encode(reg, AGGR_TYPE, IPA_GENERIC); + val |= reg_encode(reg, AGGR_EN, IPA_ENABLE_AGGR); + val |= reg_encode(reg, AGGR_TYPE, IPA_GENERIC); buffer_size = rx_config->buffer_size; limit = ipa_aggr_size_kb(buffer_size - NET_SKB_PAD, rx_config->aggr_hard_limit); - val |= ipa_reg_encode(reg, BYTE_LIMIT, limit); + val |= reg_encode(reg, BYTE_LIMIT, limit); limit = rx_config->aggr_time_limit; val |= aggr_time_limit_encode(ipa, reg, limit); @@ -866,20 +1019,20 @@ static void ipa_endpoint_init_aggr(struct ipa_endpoint *endpoint) /* AGGR_PKT_LIMIT is 0 (unlimited) */ if (rx_config->aggr_close_eof) - val |= ipa_reg_bit(reg, SW_EOF_ACTIVE); + val |= reg_bit(reg, SW_EOF_ACTIVE); } else { - val |= ipa_reg_encode(reg, AGGR_EN, IPA_ENABLE_DEAGGR); - val |= ipa_reg_encode(reg, AGGR_TYPE, IPA_QCMAP); + val |= reg_encode(reg, AGGR_EN, IPA_ENABLE_DEAGGR); + val |= reg_encode(reg, AGGR_TYPE, IPA_QCMAP); /* other fields ignored */ } /* AGGR_FORCE_CLOSE is 0 */ /* AGGR_GRAN_SEL is 0 for IPA v4.5 */ } else { - val |= ipa_reg_encode(reg, AGGR_EN, IPA_BYPASS_AGGR); + val |= reg_encode(reg, AGGR_EN, IPA_BYPASS_AGGR); /* other fields ignored */ } - iowrite32(val, ipa->reg_virt + ipa_reg_n_offset(reg, endpoint_id)); + iowrite32(val, ipa->reg_virt + reg_n_offset(reg, endpoint_id)); } /* The head-of-line blocking timer is defined as a tick count. For @@ -890,7 +1043,7 @@ static void ipa_endpoint_init_aggr(struct ipa_endpoint *endpoint) * Return the encoded value representing the timeout period provided * that should be written to the ENDP_INIT_HOL_BLOCK_TIMER register. */ -static u32 hol_block_timer_encode(struct ipa *ipa, const struct ipa_reg *reg, +static u32 hol_block_timer_encode(struct ipa *ipa, const struct reg *reg, u32 microseconds) { u32 width; @@ -904,21 +1057,14 @@ static u32 hol_block_timer_encode(struct ipa *ipa, const struct ipa_reg *reg, return 0; /* Nothing to compute if timer period is 0 */ if (ipa->version >= IPA_VERSION_4_5) { - u32 max = ipa_reg_field_max(reg, TIMER_LIMIT); - u32 gran_sel; - int ret; - - /* Compute the Qtime limit value to use */ - ret = ipa_qtime_val(microseconds, max); - if (ret < 0) { - val = -ret; - gran_sel = ipa_reg_bit(reg, TIMER_GRAN_SEL); - } else { - val = ret; - gran_sel = 0; - } + u32 max = reg_field_max(reg, TIMER_LIMIT); + u32 select; + u32 ticks; + + ticks = ipa_qtime_val(ipa, microseconds, max, &select); - return gran_sel | ipa_reg_encode(reg, TIMER_LIMIT, val); + return reg_encode(reg, TIMER_GRAN_SEL, 1) | + reg_encode(reg, TIMER_LIMIT, ticks); } /* Use 64 bit arithmetic to avoid overflow */ @@ -926,11 +1072,11 @@ static u32 hol_block_timer_encode(struct ipa *ipa, const struct ipa_reg *reg, ticks = DIV_ROUND_CLOSEST(microseconds * rate, 128 * USEC_PER_SEC); /* We still need the result to fit into the field */ - WARN_ON(ticks > ipa_reg_field_max(reg, TIMER_BASE_VALUE)); + WARN_ON(ticks > reg_field_max(reg, TIMER_BASE_VALUE)); /* IPA v3.5.1 through v4.1 just record the tick count */ if (ipa->version < IPA_VERSION_4_2) - return ipa_reg_encode(reg, TIMER_BASE_VALUE, (u32)ticks); + return reg_encode(reg, TIMER_BASE_VALUE, (u32)ticks); /* For IPA v4.2, the tick count is represented by base and * scale fields within the 32-bit timer register, where: @@ -941,7 +1087,7 @@ static u32 hol_block_timer_encode(struct ipa *ipa, const struct ipa_reg *reg, * such that high bit is included. */ high = fls(ticks); /* 1..32 (or warning above) */ - width = hweight32(ipa_reg_fmask(reg, TIMER_BASE_VALUE)); + width = hweight32(reg_fmask(reg, TIMER_BASE_VALUE)); scale = high > width ? high - width : 0; if (scale) { /* If we're scaling, round up to get a closer result */ @@ -951,8 +1097,8 @@ static u32 hol_block_timer_encode(struct ipa *ipa, const struct ipa_reg *reg, scale++; } - val = ipa_reg_encode(reg, TIMER_SCALE, scale); - val |= ipa_reg_encode(reg, TIMER_BASE_VALUE, (u32)ticks >> scale); + val = reg_encode(reg, TIMER_SCALE, scale); + val |= reg_encode(reg, TIMER_BASE_VALUE, (u32)ticks >> scale); return val; } @@ -963,14 +1109,14 @@ static void ipa_endpoint_init_hol_block_timer(struct ipa_endpoint *endpoint, { u32 endpoint_id = endpoint->endpoint_id; struct ipa *ipa = endpoint->ipa; - const struct ipa_reg *reg; + const struct reg *reg; u32 val; /* This should only be changed when HOL_BLOCK_EN is disabled */ reg = ipa_reg(ipa, ENDP_INIT_HOL_BLOCK_TIMER); val = hol_block_timer_encode(ipa, reg, microseconds); - iowrite32(val, ipa->reg_virt + ipa_reg_n_offset(reg, endpoint_id)); + iowrite32(val, ipa->reg_virt + reg_n_offset(reg, endpoint_id)); } static void @@ -978,13 +1124,13 @@ ipa_endpoint_init_hol_block_en(struct ipa_endpoint *endpoint, bool enable) { u32 endpoint_id = endpoint->endpoint_id; struct ipa *ipa = endpoint->ipa; - const struct ipa_reg *reg; + const struct reg *reg; u32 offset; u32 val; reg = ipa_reg(ipa, ENDP_INIT_HOL_BLOCK_EN); - offset = ipa_reg_n_offset(reg, endpoint_id); - val = enable ? ipa_reg_bit(reg, HOL_BLOCK_EN) : 0; + offset = reg_n_offset(reg, endpoint_id); + val = enable ? reg_bit(reg, HOL_BLOCK_EN) : 0; iowrite32(val, ipa->reg_virt + offset); @@ -1008,10 +1154,10 @@ static void ipa_endpoint_init_hol_block_disable(struct ipa_endpoint *endpoint) void ipa_endpoint_modem_hol_block_clear_all(struct ipa *ipa) { - u32 i; + u32 endpoint_id = 0; - for (i = 0; i < IPA_ENDPOINT_MAX; i++) { - struct ipa_endpoint *endpoint = &ipa->endpoint[i]; + while (endpoint_id < ipa->endpoint_count) { + struct ipa_endpoint *endpoint = &ipa->endpoint[endpoint_id++]; if (endpoint->toward_ipa || endpoint->ee_id != GSI_EE_MODEM) continue; @@ -1025,7 +1171,7 @@ static void ipa_endpoint_init_deaggr(struct ipa_endpoint *endpoint) { u32 endpoint_id = endpoint->endpoint_id; struct ipa *ipa = endpoint->ipa; - const struct ipa_reg *reg; + const struct reg *reg; u32 val = 0; if (!endpoint->toward_ipa) @@ -1037,7 +1183,7 @@ static void ipa_endpoint_init_deaggr(struct ipa_endpoint *endpoint) /* PACKET_OFFSET_LOCATION is ignored (not valid) */ /* MAX_PACKET_LEN is 0 (not enforced) */ - iowrite32(val, ipa->reg_virt + ipa_reg_n_offset(reg, endpoint_id)); + iowrite32(val, ipa->reg_virt + reg_n_offset(reg, endpoint_id)); } static void ipa_endpoint_init_rsrc_grp(struct ipa_endpoint *endpoint) @@ -1045,20 +1191,20 @@ static void ipa_endpoint_init_rsrc_grp(struct ipa_endpoint *endpoint) u32 resource_group = endpoint->config.resource_group; u32 endpoint_id = endpoint->endpoint_id; struct ipa *ipa = endpoint->ipa; - const struct ipa_reg *reg; + const struct reg *reg; u32 val; reg = ipa_reg(ipa, ENDP_INIT_RSRC_GRP); - val = ipa_reg_encode(reg, ENDP_RSRC_GRP, resource_group); + val = reg_encode(reg, ENDP_RSRC_GRP, resource_group); - iowrite32(val, ipa->reg_virt + ipa_reg_n_offset(reg, endpoint_id)); + iowrite32(val, ipa->reg_virt + reg_n_offset(reg, endpoint_id)); } static void ipa_endpoint_init_seq(struct ipa_endpoint *endpoint) { u32 endpoint_id = endpoint->endpoint_id; struct ipa *ipa = endpoint->ipa; - const struct ipa_reg *reg; + const struct reg *reg; u32 val; if (!endpoint->toward_ipa) @@ -1067,14 +1213,14 @@ static void ipa_endpoint_init_seq(struct ipa_endpoint *endpoint) reg = ipa_reg(ipa, ENDP_INIT_SEQ); /* Low-order byte configures primary packet processing */ - val = ipa_reg_encode(reg, SEQ_TYPE, endpoint->config.tx.seq_type); + val = reg_encode(reg, SEQ_TYPE, endpoint->config.tx.seq_type); /* Second byte (if supported) configures replicated packet processing */ if (ipa->version < IPA_VERSION_4_5) - val |= ipa_reg_encode(reg, SEQ_REP_TYPE, - endpoint->config.tx.seq_rep_type); + val |= reg_encode(reg, SEQ_REP_TYPE, + endpoint->config.tx.seq_rep_type); - iowrite32(val, ipa->reg_virt + ipa_reg_n_offset(reg, endpoint_id)); + iowrite32(val, ipa->reg_virt + reg_n_offset(reg, endpoint_id)); } /** @@ -1124,12 +1270,12 @@ static void ipa_endpoint_status(struct ipa_endpoint *endpoint) { u32 endpoint_id = endpoint->endpoint_id; struct ipa *ipa = endpoint->ipa; - const struct ipa_reg *reg; + const struct reg *reg; u32 val = 0; reg = ipa_reg(ipa, ENDP_STATUS); if (endpoint->config.status_enable) { - val |= ipa_reg_bit(reg, STATUS_EN); + val |= reg_bit(reg, STATUS_EN); if (endpoint->toward_ipa) { enum ipa_endpoint_name name; u32 status_endpoint_id; @@ -1137,16 +1283,15 @@ static void ipa_endpoint_status(struct ipa_endpoint *endpoint) name = endpoint->config.tx.status_endpoint; status_endpoint_id = ipa->name_map[name]->endpoint_id; - val |= ipa_reg_encode(reg, STATUS_ENDP, - status_endpoint_id); + val |= reg_encode(reg, STATUS_ENDP, status_endpoint_id); } - /* STATUS_LOCATION is 0, meaning status element precedes - * packet (not present for IPA v4.5+) + /* STATUS_LOCATION is 0, meaning IPA packet status + * precedes the packet (not present for IPA v4.5+) */ /* STATUS_PKT_SUPPRESS_FMASK is 0 (not present for v4.0+) */ } - iowrite32(val, ipa->reg_virt + ipa_reg_n_offset(reg, endpoint_id)); + iowrite32(val, ipa->reg_virt + reg_n_offset(reg, endpoint_id)); } static int ipa_endpoint_replenish_one(struct ipa_endpoint *endpoint, @@ -1297,8 +1442,8 @@ static bool ipa_endpoint_skb_build(struct ipa_endpoint *endpoint, return skb != NULL; } -/* The format of a packet status element is the same for several status - * types (opcodes). Other types aren't currently supported. + /* The format of an IPA packet status structure is the same for several + * status types (opcodes). Other types aren't currently supported. */ static bool ipa_status_format_packet(enum ipa_status_opcode opcode) { @@ -1313,31 +1458,34 @@ static bool ipa_status_format_packet(enum ipa_status_opcode opcode) } } -static bool ipa_endpoint_status_skip(struct ipa_endpoint *endpoint, - const struct ipa_status *status) +static bool +ipa_endpoint_status_skip(struct ipa_endpoint *endpoint, const void *data) { + struct ipa *ipa = endpoint->ipa; + enum ipa_status_opcode opcode; u32 endpoint_id; - if (!ipa_status_format_packet(status->opcode)) + opcode = ipa_status_extract(ipa, data, STATUS_OPCODE); + if (!ipa_status_format_packet(opcode)) return true; - if (!status->pkt_len) - return true; - endpoint_id = u8_get_bits(status->endp_dst_idx, - IPA_STATUS_DST_IDX_FMASK); + + endpoint_id = ipa_status_extract(ipa, data, STATUS_DST_ENDPOINT); if (endpoint_id != endpoint->endpoint_id) return true; return false; /* Don't skip this packet, process it */ } -static bool ipa_endpoint_status_tag(struct ipa_endpoint *endpoint, - const struct ipa_status *status) +static bool +ipa_endpoint_status_tag_valid(struct ipa_endpoint *endpoint, const void *data) { struct ipa_endpoint *command_endpoint; + enum ipa_status_mask status_mask; struct ipa *ipa = endpoint->ipa; u32 endpoint_id; - if (!le16_get_bits(status->mask, IPA_STATUS_MASK_TAG_VALID_FMASK)) + status_mask = ipa_status_extract(ipa, data, STATUS_MASK); + if (!status_mask) return false; /* No valid tag */ /* The status contains a valid tag. We know the packet was sent to @@ -1345,8 +1493,7 @@ static bool ipa_endpoint_status_tag(struct ipa_endpoint *endpoint, * If the packet came from the AP->command TX endpoint we know * this packet was sent as part of the pipeline clear process. */ - endpoint_id = u8_get_bits(status->endp_src_idx, - IPA_STATUS_SRC_IDX_FMASK); + endpoint_id = ipa_status_extract(ipa, data, STATUS_SRC_ENDPOINT); command_endpoint = ipa->name_map[IPA_ENDPOINT_AP_COMMAND_TX]; if (endpoint_id == command_endpoint->endpoint_id) { complete(&ipa->completion); @@ -1360,23 +1507,26 @@ static bool ipa_endpoint_status_tag(struct ipa_endpoint *endpoint, } /* Return whether the status indicates the packet should be dropped */ -static bool ipa_endpoint_status_drop(struct ipa_endpoint *endpoint, - const struct ipa_status *status) +static bool +ipa_endpoint_status_drop(struct ipa_endpoint *endpoint, const void *data) { - u32 val; + enum ipa_status_exception exception; + struct ipa *ipa = endpoint->ipa; + u32 rule; /* If the status indicates a tagged transfer, we'll drop the packet */ - if (ipa_endpoint_status_tag(endpoint, status)) + if (ipa_endpoint_status_tag_valid(endpoint, data)) return true; /* Deaggregation exceptions we drop; all other types we consume */ - if (status->exception) - return status->exception == IPA_STATUS_EXCEPTION_DEAGGR; + exception = ipa_status_extract(ipa, data, STATUS_EXCEPTION); + if (exception) + return exception == IPA_STATUS_EXCEPTION_DEAGGR; /* Drop the packet if it fails to match a routing rule; otherwise no */ - val = le32_get_bits(status->flags1, IPA_STATUS_FLAGS1_RT_RULE_ID_FMASK); + rule = ipa_status_extract(ipa, data, STATUS_ROUTER_RULE_INDEX); - return val == field_max(IPA_STATUS_FLAGS1_RT_RULE_ID_FMASK); + return rule == IPA_STATUS_RULE_MISS; } static void ipa_endpoint_status_parse(struct ipa_endpoint *endpoint, @@ -1385,47 +1535,46 @@ static void ipa_endpoint_status_parse(struct ipa_endpoint *endpoint, u32 buffer_size = endpoint->config.rx.buffer_size; void *data = page_address(page) + NET_SKB_PAD; u32 unused = buffer_size - total_len; + struct ipa *ipa = endpoint->ipa; u32 resid = total_len; while (resid) { - const struct ipa_status *status = data; + u32 length; u32 align; u32 len; - if (resid < sizeof(*status)) { + if (resid < IPA_STATUS_SIZE) { dev_err(&endpoint->ipa->pdev->dev, "short message (%u bytes < %zu byte status)\n", - resid, sizeof(*status)); + resid, IPA_STATUS_SIZE); break; } /* Skip over status packets that lack packet data */ - if (ipa_endpoint_status_skip(endpoint, status)) { - data += sizeof(*status); - resid -= sizeof(*status); + length = ipa_status_extract(ipa, data, STATUS_LENGTH); + if (!length || ipa_endpoint_status_skip(endpoint, data)) { + data += IPA_STATUS_SIZE; + resid -= IPA_STATUS_SIZE; continue; } /* Compute the amount of buffer space consumed by the packet, - * including the status element. If the hardware is configured - * to pad packet data to an aligned boundary, account for that. + * including the status. If the hardware is configured to + * pad packet data to an aligned boundary, account for that. * And if checksum offload is enabled a trailer containing * computed checksum information will be appended. */ align = endpoint->config.rx.pad_align ? : 1; - len = le16_to_cpu(status->pkt_len); - len = sizeof(*status) + ALIGN(len, align); + len = IPA_STATUS_SIZE + ALIGN(length, align); if (endpoint->config.checksum) len += sizeof(struct rmnet_map_dl_csum_trailer); - if (!ipa_endpoint_status_drop(endpoint, status)) { + if (!ipa_endpoint_status_drop(endpoint, data)) { void *data2; u32 extra; - u32 len2; /* Client receives only packet data (no status) */ - data2 = data + sizeof(*status); - len2 = le16_to_cpu(status->pkt_len); + data2 = data + IPA_STATUS_SIZE; /* Have the true size reflect the extra unused space in * the original receive buffer. Distribute the "cost" @@ -1433,7 +1582,7 @@ static void ipa_endpoint_status_parse(struct ipa_endpoint *endpoint, * buffer. */ extra = DIV_ROUND_CLOSEST(unused * len, total_len); - ipa_endpoint_skb_copy(endpoint, data2, len2, extra); + ipa_endpoint_skb_copy(endpoint, data2, length, extra); } /* Consume status and the full packet it describes */ @@ -1486,18 +1635,18 @@ void ipa_endpoint_trans_release(struct ipa_endpoint *endpoint, void ipa_endpoint_default_route_set(struct ipa *ipa, u32 endpoint_id) { - const struct ipa_reg *reg; + const struct reg *reg; u32 val; reg = ipa_reg(ipa, ROUTE); /* ROUTE_DIS is 0 */ - val = ipa_reg_encode(reg, ROUTE_DEF_PIPE, endpoint_id); - val |= ipa_reg_bit(reg, ROUTE_DEF_HDR_TABLE); + val = reg_encode(reg, ROUTE_DEF_PIPE, endpoint_id); + val |= reg_bit(reg, ROUTE_DEF_HDR_TABLE); /* ROUTE_DEF_HDR_OFST is 0 */ - val |= ipa_reg_encode(reg, ROUTE_FRAG_DEF_PIPE, endpoint_id); - val |= ipa_reg_bit(reg, ROUTE_DEF_RETAIN_HDR); + val |= reg_encode(reg, ROUTE_FRAG_DEF_PIPE, endpoint_id); + val |= reg_bit(reg, ROUTE_DEF_RETAIN_HDR); - iowrite32(val, ipa->reg_virt + ipa_reg_offset(reg)); + iowrite32(val, ipa->reg_virt + reg_offset(reg)); } void ipa_endpoint_default_route_clear(struct ipa *ipa) @@ -1661,6 +1810,7 @@ static void ipa_endpoint_program(struct ipa_endpoint *endpoint) int ipa_endpoint_enable_one(struct ipa_endpoint *endpoint) { + u32 endpoint_id = endpoint->endpoint_id; struct ipa *ipa = endpoint->ipa; struct gsi *gsi = &ipa->gsi; int ret; @@ -1670,37 +1820,35 @@ int ipa_endpoint_enable_one(struct ipa_endpoint *endpoint) dev_err(&ipa->pdev->dev, "error %d starting %cX channel %u for endpoint %u\n", ret, endpoint->toward_ipa ? 'T' : 'R', - endpoint->channel_id, endpoint->endpoint_id); + endpoint->channel_id, endpoint_id); return ret; } if (!endpoint->toward_ipa) { - ipa_interrupt_suspend_enable(ipa->interrupt, - endpoint->endpoint_id); + ipa_interrupt_suspend_enable(ipa->interrupt, endpoint_id); ipa_endpoint_replenish_enable(endpoint); } - ipa->enabled |= BIT(endpoint->endpoint_id); + __set_bit(endpoint_id, ipa->enabled); return 0; } void ipa_endpoint_disable_one(struct ipa_endpoint *endpoint) { - u32 mask = BIT(endpoint->endpoint_id); + u32 endpoint_id = endpoint->endpoint_id; struct ipa *ipa = endpoint->ipa; struct gsi *gsi = &ipa->gsi; int ret; - if (!(ipa->enabled & mask)) + if (!test_bit(endpoint_id, ipa->enabled)) return; - ipa->enabled ^= mask; + __clear_bit(endpoint_id, endpoint->ipa->enabled); if (!endpoint->toward_ipa) { ipa_endpoint_replenish_disable(endpoint); - ipa_interrupt_suspend_disable(ipa->interrupt, - endpoint->endpoint_id); + ipa_interrupt_suspend_disable(ipa->interrupt, endpoint_id); } /* Note that if stop fails, the channel's state is not well-defined */ @@ -1708,7 +1856,7 @@ void ipa_endpoint_disable_one(struct ipa_endpoint *endpoint) if (ret) dev_err(&ipa->pdev->dev, "error %d attempting to stop endpoint %u\n", ret, - endpoint->endpoint_id); + endpoint_id); } void ipa_endpoint_suspend_one(struct ipa_endpoint *endpoint) @@ -1717,7 +1865,7 @@ void ipa_endpoint_suspend_one(struct ipa_endpoint *endpoint) struct gsi *gsi = &endpoint->ipa->gsi; int ret; - if (!(endpoint->ipa->enabled & BIT(endpoint->endpoint_id))) + if (!test_bit(endpoint->endpoint_id, endpoint->ipa->enabled)) return; if (!endpoint->toward_ipa) { @@ -1737,7 +1885,7 @@ void ipa_endpoint_resume_one(struct ipa_endpoint *endpoint) struct gsi *gsi = &endpoint->ipa->gsi; int ret; - if (!(endpoint->ipa->enabled & BIT(endpoint->endpoint_id))) + if (!test_bit(endpoint->endpoint_id, endpoint->ipa->enabled)) return; if (!endpoint->toward_ipa) @@ -1797,12 +1945,12 @@ static void ipa_endpoint_setup_one(struct ipa_endpoint *endpoint) ipa_endpoint_program(endpoint); - endpoint->ipa->set_up |= BIT(endpoint->endpoint_id); + __set_bit(endpoint->endpoint_id, endpoint->ipa->set_up); } static void ipa_endpoint_teardown_one(struct ipa_endpoint *endpoint) { - endpoint->ipa->set_up &= ~BIT(endpoint->endpoint_id); + __clear_bit(endpoint->endpoint_id, endpoint->ipa->set_up); if (!endpoint->toward_ipa) cancel_delayed_work_sync(&endpoint->replenish_work); @@ -1812,45 +1960,40 @@ static void ipa_endpoint_teardown_one(struct ipa_endpoint *endpoint) void ipa_endpoint_setup(struct ipa *ipa) { - u32 initialized = ipa->initialized; - - ipa->set_up = 0; - while (initialized) { - u32 endpoint_id = __ffs(initialized); - - initialized ^= BIT(endpoint_id); + u32 endpoint_id; + for_each_set_bit(endpoint_id, ipa->defined, ipa->endpoint_count) ipa_endpoint_setup_one(&ipa->endpoint[endpoint_id]); - } } void ipa_endpoint_teardown(struct ipa *ipa) { - u32 set_up = ipa->set_up; - - while (set_up) { - u32 endpoint_id = __fls(set_up); - - set_up ^= BIT(endpoint_id); + u32 endpoint_id; + for_each_set_bit(endpoint_id, ipa->set_up, ipa->endpoint_count) ipa_endpoint_teardown_one(&ipa->endpoint[endpoint_id]); - } - ipa->set_up = 0; +} + +void ipa_endpoint_deconfig(struct ipa *ipa) +{ + ipa->available_count = 0; + bitmap_free(ipa->available); + ipa->available = NULL; } int ipa_endpoint_config(struct ipa *ipa) { struct device *dev = &ipa->pdev->dev; - const struct ipa_reg *reg; - u32 initialized; + const struct reg *reg; + u32 endpoint_id; + u32 hw_limit; + u32 tx_count; + u32 rx_count; u32 rx_base; - u32 rx_mask; - u32 tx_mask; - int ret = 0; - u32 max; + u32 limit; u32 val; - /* Prior to IPAv3.5, the FLAVOR_0 register was not supported. + /* Prior to IPA v3.5, the FLAVOR_0 register was not supported. * Furthermore, the endpoints were not grouped such that TX * endpoint numbers started with 0 and RX endpoints had numbers * higher than all TX endpoints, so we can't do the simple @@ -1861,61 +2004,86 @@ int ipa_endpoint_config(struct ipa *ipa) * assume the configuration is valid. */ if (ipa->version < IPA_VERSION_3_5) { - ipa->available = ~0; + ipa->available = bitmap_zalloc(IPA_ENDPOINT_MAX, GFP_KERNEL); + if (!ipa->available) + return -ENOMEM; + ipa->available_count = IPA_ENDPOINT_MAX; + + bitmap_set(ipa->available, 0, IPA_ENDPOINT_MAX); + return 0; } /* Find out about the endpoints supplied by the hardware, and ensure - * the highest one doesn't exceed the number we support. + * the highest one doesn't exceed the number supported by software. */ reg = ipa_reg(ipa, FLAVOR_0); - val = ioread32(ipa->reg_virt + ipa_reg_offset(reg)); - - /* Our RX is an IPA producer */ - rx_base = ipa_reg_decode(reg, PROD_LOWEST, val); - max = rx_base + ipa_reg_decode(reg, MAX_PROD_PIPES, val); - if (max > IPA_ENDPOINT_MAX) { - dev_err(dev, "too many endpoints (%u > %u)\n", - max, IPA_ENDPOINT_MAX); + val = ioread32(ipa->reg_virt + reg_offset(reg)); + + /* Our RX is an IPA producer; our TX is an IPA consumer. */ + tx_count = reg_decode(reg, MAX_CONS_PIPES, val); + rx_count = reg_decode(reg, MAX_PROD_PIPES, val); + rx_base = reg_decode(reg, PROD_LOWEST, val); + + limit = rx_base + rx_count; + if (limit > IPA_ENDPOINT_MAX) { + dev_err(dev, "too many endpoints, %u > %u\n", + limit, IPA_ENDPOINT_MAX); return -EINVAL; } - rx_mask = GENMASK(max - 1, rx_base); - /* Our TX is an IPA consumer */ - max = ipa_reg_decode(reg, MAX_CONS_PIPES, val); - tx_mask = GENMASK(max - 1, 0); + /* Until IPA v5.0, the max endpoint ID was 32 */ + hw_limit = ipa->version < IPA_VERSION_5_0 ? 32 : U8_MAX + 1; + if (limit > hw_limit) { + dev_err(dev, "unexpected endpoint count, %u > %u\n", + limit, hw_limit); + return -EINVAL; + } - ipa->available = rx_mask | tx_mask; + /* Allocate and initialize the available endpoint bitmap */ + ipa->available = bitmap_zalloc(limit, GFP_KERNEL); + if (!ipa->available) + return -ENOMEM; + ipa->available_count = limit; - /* Check for initialized endpoints not supported by the hardware */ - if (ipa->initialized & ~ipa->available) { - dev_err(dev, "unavailable endpoint id(s) 0x%08x\n", - ipa->initialized & ~ipa->available); - ret = -EINVAL; /* Report other errors too */ - } + /* Mark all supported RX and TX endpoints as available */ + bitmap_set(ipa->available, 0, tx_count); + bitmap_set(ipa->available, rx_base, rx_count); - initialized = ipa->initialized; - while (initialized) { - u32 endpoint_id = __ffs(initialized); + for_each_set_bit(endpoint_id, ipa->defined, ipa->endpoint_count) { struct ipa_endpoint *endpoint; - initialized ^= BIT(endpoint_id); + if (endpoint_id >= limit) { + dev_err(dev, "invalid endpoint id, %u > %u\n", + endpoint_id, limit - 1); + goto err_free_bitmap; + } + + if (!test_bit(endpoint_id, ipa->available)) { + dev_err(dev, "unavailable endpoint id %u\n", + endpoint_id); + goto err_free_bitmap; + } /* Make sure it's pointing in the right direction */ endpoint = &ipa->endpoint[endpoint_id]; - if ((endpoint_id < rx_base) != endpoint->toward_ipa) { - dev_err(dev, "endpoint id %u wrong direction\n", - endpoint_id); - ret = -EINVAL; + if (endpoint->toward_ipa) { + if (endpoint_id < tx_count) + continue; + } else if (endpoint_id >= rx_base) { + continue; } + + dev_err(dev, "endpoint id %u wrong direction\n", endpoint_id); + goto err_free_bitmap; } - return ret; -} + return 0; -void ipa_endpoint_deconfig(struct ipa *ipa) -{ - ipa->available = 0; /* Nothing more to do */ +err_free_bitmap: + ipa_endpoint_deconfig(ipa); + + return -EINVAL; } static void ipa_endpoint_init_one(struct ipa *ipa, enum ipa_endpoint_name name, @@ -1936,46 +2104,64 @@ static void ipa_endpoint_init_one(struct ipa *ipa, enum ipa_endpoint_name name, endpoint->toward_ipa = data->toward_ipa; endpoint->config = data->endpoint.config; - ipa->initialized |= BIT(endpoint->endpoint_id); + __set_bit(endpoint->endpoint_id, ipa->defined); } static void ipa_endpoint_exit_one(struct ipa_endpoint *endpoint) { - endpoint->ipa->initialized &= ~BIT(endpoint->endpoint_id); + __clear_bit(endpoint->endpoint_id, endpoint->ipa->defined); memset(endpoint, 0, sizeof(*endpoint)); } void ipa_endpoint_exit(struct ipa *ipa) { - u32 initialized = ipa->initialized; - - while (initialized) { - u32 endpoint_id = __fls(initialized); + u32 endpoint_id; - initialized ^= BIT(endpoint_id); + ipa->filtered = 0; + for_each_set_bit(endpoint_id, ipa->defined, ipa->endpoint_count) ipa_endpoint_exit_one(&ipa->endpoint[endpoint_id]); - } + + bitmap_free(ipa->enabled); + ipa->enabled = NULL; + bitmap_free(ipa->set_up); + ipa->set_up = NULL; + bitmap_free(ipa->defined); + ipa->defined = NULL; + memset(ipa->name_map, 0, sizeof(ipa->name_map)); memset(ipa->channel_map, 0, sizeof(ipa->channel_map)); } /* Returns a bitmask of endpoints that support filtering, or 0 on error */ -u32 ipa_endpoint_init(struct ipa *ipa, u32 count, +int ipa_endpoint_init(struct ipa *ipa, u32 count, const struct ipa_gsi_endpoint_data *data) { enum ipa_endpoint_name name; - u32 filter_map; + u32 filtered; BUILD_BUG_ON(!IPA_REPLENISH_BATCH); - if (!ipa_endpoint_data_valid(ipa, count, data)) - return 0; /* Error */ + /* Number of endpoints is one more than the maximum ID */ + ipa->endpoint_count = ipa_endpoint_max(ipa, count, data) + 1; + if (!ipa->endpoint_count) + return -EINVAL; + + /* Initialize endpoint state bitmaps */ + ipa->defined = bitmap_zalloc(ipa->endpoint_count, GFP_KERNEL); + if (!ipa->defined) + return -ENOMEM; + + ipa->set_up = bitmap_zalloc(ipa->endpoint_count, GFP_KERNEL); + if (!ipa->set_up) + goto err_free_defined; - ipa->initialized = 0; + ipa->enabled = bitmap_zalloc(ipa->endpoint_count, GFP_KERNEL); + if (!ipa->enabled) + goto err_free_set_up; - filter_map = 0; + filtered = 0; for (name = 0; name < count; name++, data++) { if (ipa_gsi_endpoint_data_empty(data)) continue; /* Skip over empty slots */ @@ -1983,18 +2169,28 @@ u32 ipa_endpoint_init(struct ipa *ipa, u32 count, ipa_endpoint_init_one(ipa, name, data); if (data->endpoint.filter_support) - filter_map |= BIT(data->endpoint_id); + filtered |= BIT(data->endpoint_id); if (data->ee_id == GSI_EE_MODEM && data->toward_ipa) ipa->modem_tx_count++; } - if (!ipa_filter_map_valid(ipa, filter_map)) - goto err_endpoint_exit; + /* Make sure the set of filtered endpoints is valid */ + if (!ipa_filtered_valid(ipa, filtered)) { + ipa_endpoint_exit(ipa); - return filter_map; /* Non-zero bitmask */ + return -EINVAL; + } + + ipa->filtered = filtered; -err_endpoint_exit: - ipa_endpoint_exit(ipa); + return 0; + +err_free_set_up: + bitmap_free(ipa->set_up); + ipa->set_up = NULL; +err_free_defined: + bitmap_free(ipa->defined); + ipa->defined = NULL; - return 0; /* Error */ + return -ENOMEM; } diff --git a/drivers/net/ipa/ipa_endpoint.h b/drivers/net/ipa/ipa_endpoint.h index d8dfa24f5214..3ad2e802040a 100644 --- a/drivers/net/ipa/ipa_endpoint.h +++ b/drivers/net/ipa/ipa_endpoint.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. - * Copyright (C) 2019-2022 Linaro Ltd. + * Copyright (C) 2019-2023 Linaro Ltd. */ #ifndef _IPA_ENDPOINT_H_ #define _IPA_ENDPOINT_H_ @@ -38,7 +38,7 @@ enum ipa_endpoint_name { IPA_ENDPOINT_COUNT, /* Number of names (not an index) */ }; -#define IPA_ENDPOINT_MAX 32 /* Max supported by driver */ +#define IPA_ENDPOINT_MAX 36 /* Max supported by driver */ /** * struct ipa_endpoint_tx - Endpoint configuration for TX endpoints @@ -195,7 +195,7 @@ void ipa_endpoint_deconfig(struct ipa *ipa); void ipa_endpoint_default_route_set(struct ipa *ipa, u32 endpoint_id); void ipa_endpoint_default_route_clear(struct ipa *ipa); -u32 ipa_endpoint_init(struct ipa *ipa, u32 count, +int ipa_endpoint_init(struct ipa *ipa, u32 count, const struct ipa_gsi_endpoint_data *data); void ipa_endpoint_exit(struct ipa *ipa); diff --git a/drivers/net/ipa/ipa_interrupt.c b/drivers/net/ipa/ipa_interrupt.c index c269432f9c2e..4bc05948f772 100644 --- a/drivers/net/ipa/ipa_interrupt.c +++ b/drivers/net/ipa/ipa_interrupt.c @@ -22,10 +22,13 @@ #include <linux/types.h> #include <linux/interrupt.h> #include <linux/pm_runtime.h> +#include <linux/pm_wakeirq.h> #include "ipa.h" #include "ipa_reg.h" #include "ipa_endpoint.h" +#include "ipa_power.h" +#include "ipa_uc.h" #include "ipa_interrupt.h" /** @@ -33,47 +36,47 @@ * @ipa: IPA pointer * @irq: Linux IRQ number used for IPA interrupts * @enabled: Mask indicating which interrupts are enabled - * @handler: Array of handlers indexed by IPA interrupt ID */ struct ipa_interrupt { struct ipa *ipa; u32 irq; u32 enabled; - ipa_irq_handler_t handler[IPA_IRQ_COUNT]; }; -/* Returns true if the interrupt type is associated with the microcontroller */ -static bool ipa_interrupt_uc(struct ipa_interrupt *interrupt, u32 irq_id) -{ - return irq_id == IPA_IRQ_UC_0 || irq_id == IPA_IRQ_UC_1; -} - /* Process a particular interrupt type that has been received */ static void ipa_interrupt_process(struct ipa_interrupt *interrupt, u32 irq_id) { - bool uc_irq = ipa_interrupt_uc(interrupt, irq_id); struct ipa *ipa = interrupt->ipa; - const struct ipa_reg *reg; + const struct reg *reg; u32 mask = BIT(irq_id); u32 offset; - /* For microcontroller interrupts, clear the interrupt right away, - * "to avoid clearing unhandled interrupts." - */ reg = ipa_reg(ipa, IPA_IRQ_CLR); - offset = ipa_reg_offset(reg); - if (uc_irq) + offset = reg_offset(reg); + + switch (irq_id) { + case IPA_IRQ_UC_0: + case IPA_IRQ_UC_1: + /* For microcontroller interrupts, clear the interrupt right + * away, "to avoid clearing unhandled interrupts." + */ iowrite32(mask, ipa->reg_virt + offset); - - if (irq_id < IPA_IRQ_COUNT && interrupt->handler[irq_id]) - interrupt->handler[irq_id](interrupt->ipa, irq_id); - - /* Clearing the SUSPEND_TX interrupt also clears the register - * that tells us which suspended endpoint(s) caused the interrupt, - * so defer clearing until after the handler has been called. - */ - if (!uc_irq) + ipa_uc_interrupt_handler(ipa, irq_id); + break; + + case IPA_IRQ_TX_SUSPEND: + /* Clearing the SUSPEND_TX interrupt also clears the + * register that tells us which suspended endpoint(s) + * caused the interrupt, so defer clearing until after + * the handler has been called. + */ + ipa_power_suspend_handler(ipa, irq_id); + fallthrough; + + default: /* Silently ignore (and clear) any other condition */ iowrite32(mask, ipa->reg_virt + offset); + break; + } } /* IPA IRQ handler is threaded */ @@ -82,7 +85,7 @@ static irqreturn_t ipa_isr_thread(int irq, void *dev_id) struct ipa_interrupt *interrupt = dev_id; struct ipa *ipa = interrupt->ipa; u32 enabled = interrupt->enabled; - const struct ipa_reg *reg; + const struct reg *reg; struct device *dev; u32 pending; u32 offset; @@ -99,7 +102,7 @@ static irqreturn_t ipa_isr_thread(int irq, void *dev_id) * only the enabled ones. */ reg = ipa_reg(ipa, IPA_IRQ_STTS); - offset = ipa_reg_offset(reg); + offset = reg_offset(reg); pending = ioread32(ipa->reg_virt + offset); while ((mask = pending & enabled)) { do { @@ -117,8 +120,7 @@ static irqreturn_t ipa_isr_thread(int irq, void *dev_id) dev_dbg(dev, "clearing disabled IPA interrupts 0x%08x\n", pending); reg = ipa_reg(ipa, IPA_IRQ_CLR); - offset = ipa_reg_offset(reg); - iowrite32(pending, ipa->reg_virt + offset); + iowrite32(pending, ipa->reg_virt + reg_offset(reg)); } out_power_put: pm_runtime_mark_last_busy(dev); @@ -127,29 +129,65 @@ out_power_put: return IRQ_HANDLED; } +static void ipa_interrupt_enabled_update(struct ipa *ipa) +{ + const struct reg *reg = ipa_reg(ipa, IPA_IRQ_EN); + + iowrite32(ipa->interrupt->enabled, ipa->reg_virt + reg_offset(reg)); +} + +/* Enable an IPA interrupt type */ +void ipa_interrupt_enable(struct ipa *ipa, enum ipa_irq_id ipa_irq) +{ + /* Update the IPA interrupt mask to enable it */ + ipa->interrupt->enabled |= BIT(ipa_irq); + ipa_interrupt_enabled_update(ipa); +} + +/* Disable an IPA interrupt type */ +void ipa_interrupt_disable(struct ipa *ipa, enum ipa_irq_id ipa_irq) +{ + /* Update the IPA interrupt mask to disable it */ + ipa->interrupt->enabled &= ~BIT(ipa_irq); + ipa_interrupt_enabled_update(ipa); +} + +void ipa_interrupt_irq_disable(struct ipa *ipa) +{ + disable_irq(ipa->interrupt->irq); +} + +void ipa_interrupt_irq_enable(struct ipa *ipa) +{ + enable_irq(ipa->interrupt->irq); +} + /* Common function used to enable/disable TX_SUSPEND for an endpoint */ static void ipa_interrupt_suspend_control(struct ipa_interrupt *interrupt, u32 endpoint_id, bool enable) { struct ipa *ipa = interrupt->ipa; - u32 mask = BIT(endpoint_id); - const struct ipa_reg *reg; + u32 mask = BIT(endpoint_id % 32); + u32 unit = endpoint_id / 32; + const struct reg *reg; u32 offset; u32 val; - WARN_ON(!(mask & ipa->available)); + WARN_ON(!test_bit(endpoint_id, ipa->available)); /* IPA version 3.0 does not support TX_SUSPEND interrupt control */ if (ipa->version == IPA_VERSION_3_0) return; reg = ipa_reg(ipa, IRQ_SUSPEND_EN); - offset = ipa_reg_offset(reg); + offset = reg_n_offset(reg, unit); val = ioread32(ipa->reg_virt + offset); + if (enable) val |= mask; else val &= ~mask; + iowrite32(val, ipa->reg_virt + offset); } @@ -171,18 +209,24 @@ ipa_interrupt_suspend_disable(struct ipa_interrupt *interrupt, u32 endpoint_id) void ipa_interrupt_suspend_clear_all(struct ipa_interrupt *interrupt) { struct ipa *ipa = interrupt->ipa; - const struct ipa_reg *reg; - u32 val; + u32 unit_count; + u32 unit; - reg = ipa_reg(ipa, IRQ_SUSPEND_INFO); - val = ioread32(ipa->reg_virt + ipa_reg_offset(reg)); + unit_count = roundup(ipa->endpoint_count, 32); + for (unit = 0; unit < unit_count; unit++) { + const struct reg *reg; + u32 val; - /* SUSPEND interrupt status isn't cleared on IPA version 3.0 */ - if (ipa->version == IPA_VERSION_3_0) - return; + reg = ipa_reg(ipa, IRQ_SUSPEND_INFO); + val = ioread32(ipa->reg_virt + reg_n_offset(reg, unit)); - reg = ipa_reg(ipa, IRQ_SUSPEND_CLR); - iowrite32(val, ipa->reg_virt + ipa_reg_offset(reg)); + /* SUSPEND interrupt status isn't cleared on IPA version 3.0 */ + if (ipa->version == IPA_VERSION_3_0) + continue; + + reg = ipa_reg(ipa, IRQ_SUSPEND_CLR); + iowrite32(val, ipa->reg_virt + reg_n_offset(reg, unit)); + } } /* Simulate arrival of an IPA TX_SUSPEND interrupt */ @@ -191,50 +235,12 @@ void ipa_interrupt_simulate_suspend(struct ipa_interrupt *interrupt) ipa_interrupt_process(interrupt, IPA_IRQ_TX_SUSPEND); } -/* Add a handler for an IPA interrupt */ -void ipa_interrupt_add(struct ipa_interrupt *interrupt, - enum ipa_irq_id ipa_irq, ipa_irq_handler_t handler) -{ - struct ipa *ipa = interrupt->ipa; - const struct ipa_reg *reg; - - if (WARN_ON(ipa_irq >= IPA_IRQ_COUNT)) - return; - - interrupt->handler[ipa_irq] = handler; - - /* Update the IPA interrupt mask to enable it */ - interrupt->enabled |= BIT(ipa_irq); - - reg = ipa_reg(ipa, IPA_IRQ_EN); - iowrite32(interrupt->enabled, ipa->reg_virt + ipa_reg_offset(reg)); -} - -/* Remove the handler for an IPA interrupt type */ -void -ipa_interrupt_remove(struct ipa_interrupt *interrupt, enum ipa_irq_id ipa_irq) -{ - struct ipa *ipa = interrupt->ipa; - const struct ipa_reg *reg; - - if (WARN_ON(ipa_irq >= IPA_IRQ_COUNT)) - return; - - /* Update the IPA interrupt mask to disable it */ - interrupt->enabled &= ~BIT(ipa_irq); - - reg = ipa_reg(ipa, IPA_IRQ_EN); - iowrite32(interrupt->enabled, ipa->reg_virt + ipa_reg_offset(reg)); - - interrupt->handler[ipa_irq] = NULL; -} - /* Configure the IPA interrupt framework */ struct ipa_interrupt *ipa_interrupt_config(struct ipa *ipa) { struct device *dev = &ipa->pdev->dev; struct ipa_interrupt *interrupt; - const struct ipa_reg *reg; + const struct reg *reg; unsigned int irq; int ret; @@ -254,7 +260,7 @@ struct ipa_interrupt *ipa_interrupt_config(struct ipa *ipa) /* Start with all IPA interrupts disabled */ reg = ipa_reg(ipa, IPA_IRQ_EN); - iowrite32(0, ipa->reg_virt + ipa_reg_offset(reg)); + iowrite32(0, ipa->reg_virt + reg_offset(reg)); ret = request_threaded_irq(irq, NULL, ipa_isr_thread, IRQF_ONESHOT, "ipa", interrupt); @@ -263,9 +269,9 @@ struct ipa_interrupt *ipa_interrupt_config(struct ipa *ipa) goto err_kfree; } - ret = enable_irq_wake(irq); + ret = dev_pm_set_wake_irq(dev, irq); if (ret) { - dev_err(dev, "error %d enabling wakeup for \"ipa\" IRQ\n", ret); + dev_err(dev, "error %d registering \"ipa\" IRQ as wakeirq\n", ret); goto err_free_irq; } @@ -283,11 +289,8 @@ err_kfree: void ipa_interrupt_deconfig(struct ipa_interrupt *interrupt) { struct device *dev = &interrupt->ipa->pdev->dev; - int ret; - ret = disable_irq_wake(interrupt->irq); - if (ret) - dev_err(dev, "error %d disabling \"ipa\" IRQ wakeup\n", ret); + dev_pm_clear_wake_irq(dev); free_irq(interrupt->irq, interrupt); kfree(interrupt); } diff --git a/drivers/net/ipa/ipa_interrupt.h b/drivers/net/ipa/ipa_interrupt.h index f31fd9965fdc..12e3e798ccb3 100644 --- a/drivers/net/ipa/ipa_interrupt.h +++ b/drivers/net/ipa/ipa_interrupt.h @@ -11,39 +11,7 @@ struct ipa; struct ipa_interrupt; - -/** - * typedef ipa_irq_handler_t - IPA interrupt handler function type - * @ipa: IPA pointer - * @irq_id: interrupt type - * - * Callback function registered by ipa_interrupt_add() to handle a specific - * IPA interrupt type - */ -typedef void (*ipa_irq_handler_t)(struct ipa *ipa, enum ipa_irq_id irq_id); - -/** - * ipa_interrupt_add() - Register a handler for an IPA interrupt type - * @interrupt: IPA interrupt structure - * @irq_id: IPA interrupt type - * @handler: Handler function for the interrupt - * - * Add a handler for an IPA interrupt and enable it. IPA interrupt - * handlers are run in threaded interrupt context, so are allowed to - * block. - */ -void ipa_interrupt_add(struct ipa_interrupt *interrupt, enum ipa_irq_id irq_id, - ipa_irq_handler_t handler); - -/** - * ipa_interrupt_remove() - Remove the handler for an IPA interrupt type - * @interrupt: IPA interrupt structure - * @irq_id: IPA interrupt type - * - * Remove an IPA interrupt handler and disable it. - */ -void ipa_interrupt_remove(struct ipa_interrupt *interrupt, - enum ipa_irq_id irq_id); +enum ipa_irq_id; /** * ipa_interrupt_suspend_enable - Enable TX_SUSPEND for an endpoint @@ -86,6 +54,36 @@ void ipa_interrupt_suspend_clear_all(struct ipa_interrupt *interrupt); void ipa_interrupt_simulate_suspend(struct ipa_interrupt *interrupt); /** + * ipa_interrupt_enable() - Enable an IPA interrupt type + * @ipa: IPA pointer + * @ipa_irq: IPA interrupt ID + */ +void ipa_interrupt_enable(struct ipa *ipa, enum ipa_irq_id ipa_irq); + +/** + * ipa_interrupt_disable() - Disable an IPA interrupt type + * @ipa: IPA pointer + * @ipa_irq: IPA interrupt ID + */ +void ipa_interrupt_disable(struct ipa *ipa, enum ipa_irq_id ipa_irq); + +/** + * ipa_interrupt_irq_enable() - Enable IPA interrupts + * @ipa: IPA pointer + * + * This enables the IPA interrupt line + */ +void ipa_interrupt_irq_enable(struct ipa *ipa); + +/** + * ipa_interrupt_irq_disable() - Disable IPA interrupts + * @ipa: IPA pointer + * + * This disables the IPA interrupt line + */ +void ipa_interrupt_irq_disable(struct ipa *ipa); + +/** * ipa_interrupt_config() - Configure the IPA interrupt framework * @ipa: IPA pointer * diff --git a/drivers/net/ipa/ipa_main.c b/drivers/net/ipa/ipa_main.c index 49537fccf6ad..6cb7bf96a626 100644 --- a/drivers/net/ipa/ipa_main.c +++ b/drivers/net/ipa/ipa_main.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. - * Copyright (C) 2018-2022 Linaro Ltd. + * Copyright (C) 2018-2023 Linaro Ltd. */ #include <linux/types.h> @@ -82,6 +82,23 @@ #define IPA_XO_CLOCK_DIVIDER 192 /* 1 is subtracted where used */ /** + * enum ipa_firmware_loader: How GSI firmware gets loaded + * + * @IPA_LOADER_DEFER: System not ready; try again later + * @IPA_LOADER_SELF: AP loads GSI firmware + * @IPA_LOADER_MODEM: Modem loads GSI firmware, signals when done + * @IPA_LOADER_SKIP: Neither AP nor modem need to load GSI firmware + * @IPA_LOADER_INVALID: GSI firmware loader specification is invalid + */ +enum ipa_firmware_loader { + IPA_LOADER_DEFER, + IPA_LOADER_SELF, + IPA_LOADER_MODEM, + IPA_LOADER_SKIP, + IPA_LOADER_INVALID, +}; + +/** * ipa_setup() - Set up IPA hardware * @ipa: IPA pointer * @@ -186,7 +203,7 @@ static void ipa_teardown(struct ipa *ipa) static void ipa_hardware_config_bcr(struct ipa *ipa, const struct ipa_data *data) { - const struct ipa_reg *reg; + const struct reg *reg; u32 val; /* IPA v4.5+ has no backward compatibility register */ @@ -195,13 +212,13 @@ ipa_hardware_config_bcr(struct ipa *ipa, const struct ipa_data *data) reg = ipa_reg(ipa, IPA_BCR); val = data->backward_compat; - iowrite32(val, ipa->reg_virt + ipa_reg_offset(reg)); + iowrite32(val, ipa->reg_virt + reg_offset(reg)); } static void ipa_hardware_config_tx(struct ipa *ipa) { enum ipa_version version = ipa->version; - const struct ipa_reg *reg; + const struct reg *reg; u32 offset; u32 val; @@ -210,11 +227,11 @@ static void ipa_hardware_config_tx(struct ipa *ipa) /* Disable PA mask to allow HOLB drop */ reg = ipa_reg(ipa, IPA_TX_CFG); - offset = ipa_reg_offset(reg); + offset = reg_offset(reg); val = ioread32(ipa->reg_virt + offset); - val &= ~ipa_reg_bit(reg, PA_MASK_EN); + val &= ~reg_bit(reg, PA_MASK_EN); iowrite32(val, ipa->reg_virt + offset); } @@ -222,7 +239,7 @@ static void ipa_hardware_config_tx(struct ipa *ipa) static void ipa_hardware_config_clkon(struct ipa *ipa) { enum ipa_version version = ipa->version; - const struct ipa_reg *reg; + const struct reg *reg; u32 val; if (version >= IPA_VERSION_4_5) @@ -235,20 +252,20 @@ static void ipa_hardware_config_clkon(struct ipa *ipa) reg = ipa_reg(ipa, CLKON_CFG); if (version == IPA_VERSION_3_1) { /* Disable MISC clock gating */ - val = ipa_reg_bit(reg, CLKON_MISC); + val = reg_bit(reg, CLKON_MISC); } else { /* IPA v4.0+ */ /* Enable open global clocks in the CLKON configuration */ - val = ipa_reg_bit(reg, CLKON_GLOBAL); - val |= ipa_reg_bit(reg, GLOBAL_2X_CLK); + val = reg_bit(reg, CLKON_GLOBAL); + val |= reg_bit(reg, GLOBAL_2X_CLK); } - iowrite32(val, ipa->reg_virt + ipa_reg_offset(reg)); + iowrite32(val, ipa->reg_virt + reg_offset(reg)); } /* Configure bus access behavior for IPA components */ static void ipa_hardware_config_comp(struct ipa *ipa) { - const struct ipa_reg *reg; + const struct reg *reg; u32 offset; u32 val; @@ -257,21 +274,22 @@ static void ipa_hardware_config_comp(struct ipa *ipa) return; reg = ipa_reg(ipa, COMP_CFG); - offset = ipa_reg_offset(reg); + offset = reg_offset(reg); + val = ioread32(ipa->reg_virt + offset); if (ipa->version == IPA_VERSION_4_0) { - val &= ~ipa_reg_bit(reg, IPA_QMB_SELECT_CONS_EN); - val &= ~ipa_reg_bit(reg, IPA_QMB_SELECT_PROD_EN); - val &= ~ipa_reg_bit(reg, IPA_QMB_SELECT_GLOBAL_EN); + val &= ~reg_bit(reg, IPA_QMB_SELECT_CONS_EN); + val &= ~reg_bit(reg, IPA_QMB_SELECT_PROD_EN); + val &= ~reg_bit(reg, IPA_QMB_SELECT_GLOBAL_EN); } else if (ipa->version < IPA_VERSION_4_5) { - val |= ipa_reg_bit(reg, GSI_MULTI_AXI_MASTERS_DIS); + val |= reg_bit(reg, GSI_MULTI_AXI_MASTERS_DIS); } else { /* For IPA v4.5 FULL_FLUSH_WAIT_RS_CLOSURE_EN is 0 */ } - val |= ipa_reg_bit(reg, GSI_MULTI_INORDER_RD_DIS); - val |= ipa_reg_bit(reg, GSI_MULTI_INORDER_WR_DIS); + val |= reg_bit(reg, GSI_MULTI_INORDER_RD_DIS); + val |= reg_bit(reg, GSI_MULTI_INORDER_WR_DIS); iowrite32(val, ipa->reg_virt + offset); } @@ -282,7 +300,7 @@ ipa_hardware_config_qsb(struct ipa *ipa, const struct ipa_data *data) { const struct ipa_qsb_data *data0; const struct ipa_qsb_data *data1; - const struct ipa_reg *reg; + const struct reg *reg; u32 val; /* QMB 0 represents DDR; QMB 1 (if present) represents PCIe */ @@ -293,29 +311,27 @@ ipa_hardware_config_qsb(struct ipa *ipa, const struct ipa_data *data) /* Max outstanding write accesses for QSB masters */ reg = ipa_reg(ipa, QSB_MAX_WRITES); - val = ipa_reg_encode(reg, GEN_QMB_0_MAX_WRITES, data0->max_writes); + val = reg_encode(reg, GEN_QMB_0_MAX_WRITES, data0->max_writes); if (data->qsb_count > 1) - val |= ipa_reg_encode(reg, GEN_QMB_1_MAX_WRITES, - data1->max_writes); + val |= reg_encode(reg, GEN_QMB_1_MAX_WRITES, data1->max_writes); - iowrite32(val, ipa->reg_virt + ipa_reg_offset(reg)); + iowrite32(val, ipa->reg_virt + reg_offset(reg)); /* Max outstanding read accesses for QSB masters */ reg = ipa_reg(ipa, QSB_MAX_READS); - val = ipa_reg_encode(reg, GEN_QMB_0_MAX_READS, data0->max_reads); + val = reg_encode(reg, GEN_QMB_0_MAX_READS, data0->max_reads); if (ipa->version >= IPA_VERSION_4_0) - val |= ipa_reg_encode(reg, GEN_QMB_0_MAX_READS_BEATS, - data0->max_reads_beats); + val |= reg_encode(reg, GEN_QMB_0_MAX_READS_BEATS, + data0->max_reads_beats); if (data->qsb_count > 1) { - val = ipa_reg_encode(reg, GEN_QMB_1_MAX_READS, - data1->max_reads); + val = reg_encode(reg, GEN_QMB_1_MAX_READS, data1->max_reads); if (ipa->version >= IPA_VERSION_4_0) - val |= ipa_reg_encode(reg, GEN_QMB_1_MAX_READS_BEATS, - data1->max_reads_beats); + val |= reg_encode(reg, GEN_QMB_1_MAX_READS_BEATS, + data1->max_reads_beats); } - iowrite32(val, ipa->reg_virt + ipa_reg_offset(reg)); + iowrite32(val, ipa->reg_virt + reg_offset(reg)); } /* The internal inactivity timer clock is used for the aggregation timer */ @@ -351,41 +367,47 @@ static __always_inline u32 ipa_aggr_granularity_val(u32 usec) */ static void ipa_qtime_config(struct ipa *ipa) { - const struct ipa_reg *reg; + const struct reg *reg; u32 offset; u32 val; /* Timer clock divider must be disabled when we change the rate */ reg = ipa_reg(ipa, TIMERS_XO_CLK_DIV_CFG); - iowrite32(0, ipa->reg_virt + ipa_reg_offset(reg)); + iowrite32(0, ipa->reg_virt + reg_offset(reg)); reg = ipa_reg(ipa, QTIME_TIMESTAMP_CFG); /* Set DPL time stamp resolution to use Qtime (instead of 1 msec) */ - val = ipa_reg_encode(reg, DPL_TIMESTAMP_LSB, DPL_TIMESTAMP_SHIFT); - val |= ipa_reg_bit(reg, DPL_TIMESTAMP_SEL); + val = reg_encode(reg, DPL_TIMESTAMP_LSB, DPL_TIMESTAMP_SHIFT); + val |= reg_bit(reg, DPL_TIMESTAMP_SEL); /* Configure tag and NAT Qtime timestamp resolution as well */ - val = ipa_reg_encode(reg, TAG_TIMESTAMP_LSB, TAG_TIMESTAMP_SHIFT); - val = ipa_reg_encode(reg, NAT_TIMESTAMP_LSB, NAT_TIMESTAMP_SHIFT); + val = reg_encode(reg, TAG_TIMESTAMP_LSB, TAG_TIMESTAMP_SHIFT); + val = reg_encode(reg, NAT_TIMESTAMP_LSB, NAT_TIMESTAMP_SHIFT); - iowrite32(val, ipa->reg_virt + ipa_reg_offset(reg)); + iowrite32(val, ipa->reg_virt + reg_offset(reg)); /* Set granularity of pulse generators used for other timers */ reg = ipa_reg(ipa, TIMERS_PULSE_GRAN_CFG); - val = ipa_reg_encode(reg, PULSE_GRAN_0, IPA_GRAN_100_US); - val |= ipa_reg_encode(reg, PULSE_GRAN_1, IPA_GRAN_1_MS); - val |= ipa_reg_encode(reg, PULSE_GRAN_2, IPA_GRAN_1_MS); + val = reg_encode(reg, PULSE_GRAN_0, IPA_GRAN_100_US); + val |= reg_encode(reg, PULSE_GRAN_1, IPA_GRAN_1_MS); + if (ipa->version >= IPA_VERSION_5_0) { + val |= reg_encode(reg, PULSE_GRAN_2, IPA_GRAN_10_MS); + val |= reg_encode(reg, PULSE_GRAN_3, IPA_GRAN_10_MS); + } else { + val |= reg_encode(reg, PULSE_GRAN_2, IPA_GRAN_1_MS); + } - iowrite32(val, ipa->reg_virt + ipa_reg_offset(reg)); + iowrite32(val, ipa->reg_virt + reg_offset(reg)); /* Actual divider is 1 more than value supplied here */ reg = ipa_reg(ipa, TIMERS_XO_CLK_DIV_CFG); - offset = ipa_reg_offset(reg); - val = ipa_reg_encode(reg, DIV_VALUE, IPA_XO_CLOCK_DIVIDER - 1); + offset = reg_offset(reg); + + val = reg_encode(reg, DIV_VALUE, IPA_XO_CLOCK_DIVIDER - 1); iowrite32(val, ipa->reg_virt + offset); /* Divider value is set; re-enable the common timer clock divider */ - val |= ipa_reg_bit(reg, DIV_ENABLE); + val |= reg_bit(reg, DIV_ENABLE); iowrite32(val, ipa->reg_virt + offset); } @@ -394,13 +416,13 @@ static void ipa_qtime_config(struct ipa *ipa) static void ipa_hardware_config_counter(struct ipa *ipa) { u32 granularity = ipa_aggr_granularity_val(IPA_AGGR_GRANULARITY); - const struct ipa_reg *reg; + const struct reg *reg; u32 val; reg = ipa_reg(ipa, COUNTER_CFG); /* If defined, EOT_COAL_GRANULARITY is 0 */ - val = ipa_reg_encode(reg, AGGR_GRANULARITY, granularity); - iowrite32(val, ipa->reg_virt + ipa_reg_offset(reg)); + val = reg_encode(reg, AGGR_GRANULARITY, granularity); + iowrite32(val, ipa->reg_virt + reg_offset(reg)); } static void ipa_hardware_config_timing(struct ipa *ipa) @@ -413,8 +435,13 @@ static void ipa_hardware_config_timing(struct ipa *ipa) static void ipa_hardware_config_hashing(struct ipa *ipa) { - const struct ipa_reg *reg; + const struct reg *reg; + /* Other than IPA v4.2, all versions enable "hashing". Starting + * with IPA v5.0, the filter and router tables are implemented + * differently, but the default configuration enables this feature + * (now referred to as "cacheing"), so there's nothing to do here. + */ if (ipa->version != IPA_VERSION_4_2) return; @@ -424,26 +451,26 @@ static void ipa_hardware_config_hashing(struct ipa *ipa) /* IPV6_ROUTER_HASH, IPV6_FILTER_HASH, IPV4_ROUTER_HASH, * IPV4_FILTER_HASH are all zero. */ - iowrite32(0, ipa->reg_virt + ipa_reg_offset(reg)); + iowrite32(0, ipa->reg_virt + reg_offset(reg)); } static void ipa_idle_indication_cfg(struct ipa *ipa, u32 enter_idle_debounce_thresh, bool const_non_idle_enable) { - const struct ipa_reg *reg; + const struct reg *reg; u32 val; if (ipa->version < IPA_VERSION_3_5_1) return; reg = ipa_reg(ipa, IDLE_INDICATION_CFG); - val = ipa_reg_encode(reg, ENTER_IDLE_DEBOUNCE_THRESH, - enter_idle_debounce_thresh); + val = reg_encode(reg, ENTER_IDLE_DEBOUNCE_THRESH, + enter_idle_debounce_thresh); if (const_non_idle_enable) - val |= ipa_reg_bit(reg, CONST_NON_IDLE_ENABLE); + val |= reg_bit(reg, CONST_NON_IDLE_ENABLE); - iowrite32(val, ipa->reg_virt + ipa_reg_offset(reg)); + iowrite32(val, ipa->reg_virt + reg_offset(reg)); } /** @@ -646,6 +673,10 @@ static const struct of_device_id ipa_match[] = { .data = &ipa_data_v4_5, }, { + .compatible = "qcom,sm6350-ipa", + .data = &ipa_data_v4_7, + }, + { .compatible = "qcom,sm8350-ipa", .data = &ipa_data_v4_9, }, @@ -696,6 +727,50 @@ static void ipa_validate_build(void) BUILD_BUG_ON(!ipa_aggr_granularity_val(IPA_AGGR_GRANULARITY)); } +static enum ipa_firmware_loader ipa_firmware_loader(struct device *dev) +{ + bool modem_init; + const char *str; + int ret; + + /* Look up the old and new properties by name */ + modem_init = of_property_read_bool(dev->of_node, "modem-init"); + ret = of_property_read_string(dev->of_node, "qcom,gsi-loader", &str); + + /* If the new property doesn't exist, it's legacy behavior */ + if (ret == -EINVAL) { + if (modem_init) + return IPA_LOADER_MODEM; + goto out_self; + } + + /* Any other error on the new property means it's poorly defined */ + if (ret) + return IPA_LOADER_INVALID; + + /* New property value exists; if old one does too, that's invalid */ + if (modem_init) + return IPA_LOADER_INVALID; + + /* Modem loads GSI firmware for "modem" */ + if (!strcmp(str, "modem")) + return IPA_LOADER_MODEM; + + /* No GSI firmware load is needed for "skip" */ + if (!strcmp(str, "skip")) + return IPA_LOADER_SKIP; + + /* Any value other than "self" is an error */ + if (strcmp(str, "self")) + return IPA_LOADER_INVALID; +out_self: + /* We need Trust Zone to load firmware; make sure it's available */ + if (qcom_scm_is_available()) + return IPA_LOADER_SELF; + + return IPA_LOADER_DEFER; +} + /** * ipa_probe() - IPA platform driver probe function * @pdev: Platform device pointer @@ -722,9 +797,9 @@ static void ipa_validate_build(void) static int ipa_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; + enum ipa_firmware_loader loader; const struct ipa_data *data; struct ipa_power *power; - bool modem_init; struct ipa *ipa; int ret; @@ -742,11 +817,16 @@ static int ipa_probe(struct platform_device *pdev) return -EINVAL; } - /* If we need Trust Zone, make sure it's available */ - modem_init = of_property_read_bool(dev->of_node, "modem-init"); - if (!modem_init) - if (!qcom_scm_is_available()) - return -EPROBE_DEFER; + if (!data->modem_route_count) { + dev_err(dev, "modem_route_count cannot be zero\n"); + return -EINVAL; + } + + loader = ipa_firmware_loader(dev); + if (loader == IPA_LOADER_INVALID) + return -EINVAL; + if (loader == IPA_LOADER_DEFER) + return -EPROBE_DEFER; /* The clock and interconnects might not be ready when we're * probed, so might return -EPROBE_DEFER. @@ -766,6 +846,7 @@ static int ipa_probe(struct platform_device *pdev) dev_set_drvdata(dev, ipa); ipa->power = power; ipa->version = data->version; + ipa->modem_route_count = data->modem_route_count; init_completion(&ipa->completion); ret = ipa_reg_init(ipa); @@ -782,18 +863,15 @@ static int ipa_probe(struct platform_device *pdev) goto err_mem_exit; /* Result is a non-zero mask of endpoints that support filtering */ - ipa->filter_map = ipa_endpoint_init(ipa, data->endpoint_count, - data->endpoint_data); - if (!ipa->filter_map) { - ret = -EINVAL; + ret = ipa_endpoint_init(ipa, data->endpoint_count, data->endpoint_data); + if (ret) goto err_gsi_exit; - } ret = ipa_table_init(ipa); if (ret) goto err_endpoint_exit; - ret = ipa_smp2p_init(ipa, modem_init); + ret = ipa_smp2p_init(ipa, loader == IPA_LOADER_MODEM); if (ret) goto err_table_exit; @@ -808,20 +886,20 @@ static int ipa_probe(struct platform_device *pdev) dev_info(dev, "IPA driver initialized"); - /* If the modem is doing early initialization, it will trigger a - * call to ipa_setup() when it has finished. In that case we're - * done here. + /* If the modem is loading GSI firmware, it will trigger a call to + * ipa_setup() when it has finished. In that case we're done here. */ - if (modem_init) + if (loader == IPA_LOADER_MODEM) goto done; - /* Otherwise we need to load the firmware and have Trust Zone validate - * and install it. If that succeeds we can proceed with setup. - */ - ret = ipa_firmware_load(dev); - if (ret) - goto err_deconfig; + if (loader == IPA_LOADER_SELF) { + /* The AP is loading GSI firmware; do so now */ + ret = ipa_firmware_load(dev); + if (ret) + goto err_deconfig; + } /* Otherwise loader == IPA_LOADER_SKIP */ + /* GSI firmware is loaded; proceed to setup */ ret = ipa_setup(ipa); if (ret) goto err_deconfig; diff --git a/drivers/net/ipa/ipa_mem.c b/drivers/net/ipa/ipa_mem.c index f84c6830495a..85096d1efe5b 100644 --- a/drivers/net/ipa/ipa_mem.c +++ b/drivers/net/ipa/ipa_mem.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. - * Copyright (C) 2019-2022 Linaro Ltd. + * Copyright (C) 2019-2023 Linaro Ltd. */ #include <linux/types.h> @@ -75,7 +75,7 @@ ipa_mem_zero_region_add(struct gsi_trans *trans, enum ipa_mem_id mem_id) int ipa_mem_setup(struct ipa *ipa) { dma_addr_t addr = ipa->zero_addr; - const struct ipa_reg *reg; + const struct reg *reg; const struct ipa_mem *mem; struct gsi_trans *trans; u32 offset; @@ -115,8 +115,8 @@ int ipa_mem_setup(struct ipa *ipa) offset = ipa->mem_offset + mem->offset; reg = ipa_reg(ipa, LOCAL_PKT_PROC_CNTXT); - val = ipa_reg_encode(reg, IPA_BASE_ADDR, offset); - iowrite32(val, ipa->reg_virt + ipa_reg_offset(reg)); + val = reg_encode(reg, IPA_BASE_ADDR, offset); + iowrite32(val, ipa->reg_virt + reg_offset(reg)); return 0; } @@ -163,6 +163,12 @@ static bool ipa_mem_id_valid(struct ipa *ipa, enum ipa_mem_id mem_id) return false; break; + case IPA_MEM_AP_V4_FILTER: + case IPA_MEM_AP_V6_FILTER: + if (version != IPA_VERSION_5_0) + return false; + break; + case IPA_MEM_NAT_TABLE: case IPA_MEM_STATS_FILTER_ROUTE: if (version < IPA_VERSION_4_5) @@ -198,9 +204,12 @@ static bool ipa_mem_id_required(struct ipa *ipa, enum ipa_mem_id mem_id) case IPA_MEM_PDN_CONFIG: case IPA_MEM_STATS_QUOTA_MODEM: - case IPA_MEM_STATS_TETHERING: return ipa->version >= IPA_VERSION_4_0; + case IPA_MEM_STATS_TETHERING: + return ipa->version >= IPA_VERSION_4_0 && + ipa->version != IPA_VERSION_5_0; + default: return false; /* Anything else is optional */ } @@ -309,8 +318,8 @@ static bool ipa_mem_size_valid(struct ipa *ipa) int ipa_mem_config(struct ipa *ipa) { struct device *dev = &ipa->pdev->dev; - const struct ipa_reg *reg; const struct ipa_mem *mem; + const struct reg *reg; dma_addr_t addr; u32 mem_size; void *virt; @@ -319,13 +328,13 @@ int ipa_mem_config(struct ipa *ipa) /* Check the advertised location and size of the shared memory area */ reg = ipa_reg(ipa, SHARED_MEM_SIZE); - val = ioread32(ipa->reg_virt + ipa_reg_offset(reg)); + val = ioread32(ipa->reg_virt + reg_offset(reg)); /* The fields in the register are in 8 byte units */ - ipa->mem_offset = 8 * ipa_reg_decode(reg, MEM_BADDR, val); + ipa->mem_offset = 8 * reg_decode(reg, MEM_BADDR, val); /* Make sure the end is within the region's mapped space */ - mem_size = 8 * ipa_reg_decode(reg, MEM_SIZE, val); + mem_size = 8 * reg_decode(reg, MEM_SIZE, val); /* If the sizes don't match, issue a warning */ if (ipa->mem_offset + mem_size < ipa->mem_size) { @@ -366,14 +375,6 @@ int ipa_mem_config(struct ipa *ipa) while (--canary_count); } - /* Make sure filter and route table memory regions are valid */ - if (!ipa_table_valid(ipa)) - goto err_dma_free; - - /* Validate memory-related properties relevant to immediate commands */ - if (!ipa_cmd_data_valid(ipa)) - goto err_dma_free; - /* Verify the microcontroller ring alignment (if defined) */ mem = ipa_mem_find(ipa, IPA_MEM_UC_EVENT_RING); if (mem && mem->offset % 1024) { @@ -625,6 +626,12 @@ int ipa_mem_init(struct ipa *ipa, const struct ipa_mem_data *mem_data) ipa->mem_count = mem_data->local_count; ipa->mem = mem_data->local; + /* Check the route and filter table memory regions */ + if (!ipa_table_mem_valid(ipa, false)) + return -EINVAL; + if (!ipa_table_mem_valid(ipa, true)) + return -EINVAL; + ret = dma_set_mask_and_coherent(&ipa->pdev->dev, DMA_BIT_MASK(64)); if (ret) { dev_err(dev, "error %d setting DMA mask\n", ret); diff --git a/drivers/net/ipa/ipa_mem.h b/drivers/net/ipa/ipa_mem.h index 570bfdd99bff..868e9c20e8c4 100644 --- a/drivers/net/ipa/ipa_mem.h +++ b/drivers/net/ipa/ipa_mem.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. - * Copyright (C) 2019-2021 Linaro Ltd. + * Copyright (C) 2019-2023 Linaro Ltd. */ #ifndef _IPA_MEM_H_ #define _IPA_MEM_H_ @@ -62,13 +62,15 @@ enum ipa_mem_id { IPA_MEM_PDN_CONFIG, /* 0/2 canaries (IPA v4.0+) */ IPA_MEM_STATS_QUOTA_MODEM, /* 2/4 canaries (IPA v4.0+) */ IPA_MEM_STATS_QUOTA_AP, /* 0 canaries, optional (IPA v4.0+) */ - IPA_MEM_STATS_TETHERING, /* 0 canaries (IPA v4.0+) */ + IPA_MEM_STATS_TETHERING, /* 0 canaries, optional (IPA v4.0+) */ IPA_MEM_STATS_DROP, /* 0 canaries, optional (IPA v4.0+) */ - /* The next 5 filter and route statistics regions are optional */ + /* The next 7 filter and route statistics regions are optional */ IPA_MEM_STATS_V4_FILTER, /* 0 canaries (IPA v4.0-v4.2) */ IPA_MEM_STATS_V6_FILTER, /* 0 canaries (IPA v4.0-v4.2) */ IPA_MEM_STATS_V4_ROUTE, /* 0 canaries (IPA v4.0-v4.2) */ IPA_MEM_STATS_V6_ROUTE, /* 0 canaries (IPA v4.0-v4.2) */ + IPA_MEM_AP_V4_FILTER, /* 2 canaries (IPA v5.0) */ + IPA_MEM_AP_V6_FILTER, /* 0 canaries (IPA v5.0) */ IPA_MEM_STATS_FILTER_ROUTE, /* 0 canaries (IPA v4.5+) */ IPA_MEM_NAT_TABLE, /* 4 canaries, optional (IPA v4.5+) */ IPA_MEM_END_MARKER, /* 1 canary (not a real region) */ diff --git a/drivers/net/ipa/ipa_power.c b/drivers/net/ipa/ipa_power.c index 8420f93128a2..921eecf3eff6 100644 --- a/drivers/net/ipa/ipa_power.c +++ b/drivers/net/ipa/ipa_power.c @@ -181,6 +181,17 @@ static int ipa_suspend(struct device *dev) __set_bit(IPA_POWER_FLAG_SYSTEM, ipa->power->flags); + /* Increment the disable depth to ensure that the IRQ won't + * be re-enabled until the matching _enable call in + * ipa_resume(). We do this to ensure that the interrupt + * handler won't run whilst PM runtime is disabled. + * + * Note that disabling the IRQ is NOT the same as disabling + * irq wake. If wakeup is enabled for the IPA then the IRQ + * will still cause the system to wake up, see irq_set_irq_wake(). + */ + ipa_interrupt_irq_disable(ipa); + return pm_runtime_force_suspend(dev); } @@ -193,6 +204,12 @@ static int ipa_resume(struct device *dev) __clear_bit(IPA_POWER_FLAG_SYSTEM, ipa->power->flags); + /* Now that PM runtime is enabled again it's safe + * to turn the IRQ back on and process any data + * that was received during suspend. + */ + ipa_interrupt_irq_enable(ipa); + return ret; } @@ -202,17 +219,7 @@ u32 ipa_core_clock_rate(struct ipa *ipa) return ipa->power ? (u32)clk_get_rate(ipa->power->core) : 0; } -/** - * ipa_suspend_handler() - Handle the suspend IPA interrupt - * @ipa: IPA pointer - * @irq_id: IPA interrupt type (unused) - * - * If an RX endpoint is suspended, and the IPA has a packet destined for - * that endpoint, the IPA generates a SUSPEND interrupt to inform the AP - * that it should resume the endpoint. If we get one of these interrupts - * we just wake up the system. - */ -static void ipa_suspend_handler(struct ipa *ipa, enum ipa_irq_id irq_id) +void ipa_power_suspend_handler(struct ipa *ipa, enum ipa_irq_id irq_id) { /* To handle an IPA interrupt we will have resumed the hardware * just to handle the interrupt, so we're done. If we are in a @@ -335,12 +342,11 @@ int ipa_power_setup(struct ipa *ipa) { int ret; - ipa_interrupt_add(ipa->interrupt, IPA_IRQ_TX_SUSPEND, - ipa_suspend_handler); + ipa_interrupt_enable(ipa, IPA_IRQ_TX_SUSPEND); ret = device_init_wakeup(&ipa->pdev->dev, true); if (ret) - ipa_interrupt_remove(ipa->interrupt, IPA_IRQ_TX_SUSPEND); + ipa_interrupt_disable(ipa, IPA_IRQ_TX_SUSPEND); return ret; } @@ -348,7 +354,7 @@ int ipa_power_setup(struct ipa *ipa) void ipa_power_teardown(struct ipa *ipa) { (void)device_init_wakeup(&ipa->pdev->dev, false); - ipa_interrupt_remove(ipa->interrupt, IPA_IRQ_TX_SUSPEND); + ipa_interrupt_disable(ipa, IPA_IRQ_TX_SUSPEND); } /* Initialize IPA power management */ diff --git a/drivers/net/ipa/ipa_power.h b/drivers/net/ipa/ipa_power.h index 896f052e51a1..3a4c59ea1222 100644 --- a/drivers/net/ipa/ipa_power.h +++ b/drivers/net/ipa/ipa_power.h @@ -10,6 +10,7 @@ struct device; struct ipa; struct ipa_power_data; +enum ipa_irq_id; /* IPA device power management function block */ extern const struct dev_pm_ops ipa_pm_ops; @@ -48,6 +49,17 @@ void ipa_power_modem_queue_active(struct ipa *ipa); void ipa_power_retention(struct ipa *ipa, bool enable); /** + * ipa_power_suspend_handler() - Handler for SUSPEND IPA interrupts + * @ipa: IPA pointer + * @irq_id: IPA interrupt ID (unused) + * + * If an RX endpoint is suspended, and the IPA has a packet destined for + * that endpoint, the IPA generates a SUSPEND interrupt to inform the AP + * that it should resume the endpoint. + */ +void ipa_power_suspend_handler(struct ipa *ipa, enum ipa_irq_id irq_id); + +/** * ipa_power_setup() - Set up IPA power management * @ipa: IPA pointer * diff --git a/drivers/net/ipa/ipa_qmi.c b/drivers/net/ipa/ipa_qmi.c index 8295fd4b70d1..f70f0a1d1cda 100644 --- a/drivers/net/ipa/ipa_qmi.c +++ b/drivers/net/ipa/ipa_qmi.c @@ -284,6 +284,7 @@ static const struct ipa_init_modem_driver_req * init_modem_driver_req(struct ipa_qmi *ipa_qmi) { struct ipa *ipa = container_of(ipa_qmi, struct ipa, qmi); + u32 modem_route_count = ipa->modem_route_count; static struct ipa_init_modem_driver_req req; const struct ipa_mem *mem; @@ -308,12 +309,12 @@ init_modem_driver_req(struct ipa_qmi *ipa_qmi) mem = ipa_mem_find(ipa, IPA_MEM_V4_ROUTE); req.v4_route_tbl_info_valid = 1; req.v4_route_tbl_info.start = ipa->mem_offset + mem->offset; - req.v4_route_tbl_info.end = IPA_ROUTE_MODEM_COUNT - 1; + req.v4_route_tbl_info.end = modem_route_count - 1; mem = ipa_mem_find(ipa, IPA_MEM_V6_ROUTE); req.v6_route_tbl_info_valid = 1; req.v6_route_tbl_info.start = ipa->mem_offset + mem->offset; - req.v6_route_tbl_info.end = IPA_ROUTE_MODEM_COUNT - 1; + req.v6_route_tbl_info.end = modem_route_count - 1; mem = ipa_mem_find(ipa, IPA_MEM_V4_FILTER); req.v4_filter_tbl_start_valid = 1; @@ -352,7 +353,7 @@ init_modem_driver_req(struct ipa_qmi *ipa_qmi) req.v4_hash_route_tbl_info_valid = 1; req.v4_hash_route_tbl_info.start = ipa->mem_offset + mem->offset; - req.v4_hash_route_tbl_info.end = IPA_ROUTE_MODEM_COUNT - 1; + req.v4_hash_route_tbl_info.end = modem_route_count - 1; } mem = ipa_mem_find(ipa, IPA_MEM_V6_ROUTE_HASHED); @@ -360,7 +361,7 @@ init_modem_driver_req(struct ipa_qmi *ipa_qmi) req.v6_hash_route_tbl_info_valid = 1; req.v6_hash_route_tbl_info.start = ipa->mem_offset + mem->offset; - req.v6_hash_route_tbl_info.end = IPA_ROUTE_MODEM_COUNT - 1; + req.v6_hash_route_tbl_info.end = modem_route_count - 1; } mem = ipa_mem_find(ipa, IPA_MEM_V4_FILTER_HASHED); diff --git a/drivers/net/ipa/ipa_qmi_msg.c b/drivers/net/ipa/ipa_qmi_msg.c index 97c0befe8d86..894f99517233 100644 --- a/drivers/net/ipa/ipa_qmi_msg.c +++ b/drivers/net/ipa/ipa_qmi_msg.c @@ -9,7 +9,7 @@ #include "ipa_qmi_msg.h" /* QMI message structure definition for struct ipa_indication_register_req */ -struct qmi_elem_info ipa_indication_register_req_ei[] = { +const struct qmi_elem_info ipa_indication_register_req_ei[] = { { .data_type = QMI_OPT_FLAG, .elem_len = 1, @@ -116,7 +116,7 @@ struct qmi_elem_info ipa_indication_register_req_ei[] = { }; /* QMI message structure definition for struct ipa_indication_register_rsp */ -struct qmi_elem_info ipa_indication_register_rsp_ei[] = { +const struct qmi_elem_info ipa_indication_register_rsp_ei[] = { { .data_type = QMI_STRUCT, .elem_len = 1, @@ -134,7 +134,7 @@ struct qmi_elem_info ipa_indication_register_rsp_ei[] = { }; /* QMI message structure definition for struct ipa_driver_init_complete_req */ -struct qmi_elem_info ipa_driver_init_complete_req_ei[] = { +const struct qmi_elem_info ipa_driver_init_complete_req_ei[] = { { .data_type = QMI_UNSIGNED_1_BYTE, .elem_len = 1, @@ -151,7 +151,7 @@ struct qmi_elem_info ipa_driver_init_complete_req_ei[] = { }; /* QMI message structure definition for struct ipa_driver_init_complete_rsp */ -struct qmi_elem_info ipa_driver_init_complete_rsp_ei[] = { +const struct qmi_elem_info ipa_driver_init_complete_rsp_ei[] = { { .data_type = QMI_STRUCT, .elem_len = 1, @@ -169,7 +169,7 @@ struct qmi_elem_info ipa_driver_init_complete_rsp_ei[] = { }; /* QMI message structure definition for struct ipa_init_complete_ind */ -struct qmi_elem_info ipa_init_complete_ind_ei[] = { +const struct qmi_elem_info ipa_init_complete_ind_ei[] = { { .data_type = QMI_STRUCT, .elem_len = 1, @@ -187,7 +187,7 @@ struct qmi_elem_info ipa_init_complete_ind_ei[] = { }; /* QMI message structure definition for struct ipa_mem_bounds */ -struct qmi_elem_info ipa_mem_bounds_ei[] = { +const struct qmi_elem_info ipa_mem_bounds_ei[] = { { .data_type = QMI_UNSIGNED_4_BYTE, .elem_len = 1, @@ -208,7 +208,7 @@ struct qmi_elem_info ipa_mem_bounds_ei[] = { }; /* QMI message structure definition for struct ipa_mem_array */ -struct qmi_elem_info ipa_mem_array_ei[] = { +const struct qmi_elem_info ipa_mem_array_ei[] = { { .data_type = QMI_UNSIGNED_4_BYTE, .elem_len = 1, @@ -229,7 +229,7 @@ struct qmi_elem_info ipa_mem_array_ei[] = { }; /* QMI message structure definition for struct ipa_mem_range */ -struct qmi_elem_info ipa_mem_range_ei[] = { +const struct qmi_elem_info ipa_mem_range_ei[] = { { .data_type = QMI_UNSIGNED_4_BYTE, .elem_len = 1, @@ -250,7 +250,7 @@ struct qmi_elem_info ipa_mem_range_ei[] = { }; /* QMI message structure definition for struct ipa_init_modem_driver_req */ -struct qmi_elem_info ipa_init_modem_driver_req_ei[] = { +const struct qmi_elem_info ipa_init_modem_driver_req_ei[] = { { .data_type = QMI_OPT_FLAG, .elem_len = 1, @@ -645,7 +645,7 @@ struct qmi_elem_info ipa_init_modem_driver_req_ei[] = { }; /* QMI message structure definition for struct ipa_init_modem_driver_rsp */ -struct qmi_elem_info ipa_init_modem_driver_rsp_ei[] = { +const struct qmi_elem_info ipa_init_modem_driver_rsp_ei[] = { { .data_type = QMI_STRUCT, .elem_len = 1, diff --git a/drivers/net/ipa/ipa_qmi_msg.h b/drivers/net/ipa/ipa_qmi_msg.h index e29663965f43..b73503552c4d 100644 --- a/drivers/net/ipa/ipa_qmi_msg.h +++ b/drivers/net/ipa/ipa_qmi_msg.h @@ -247,15 +247,15 @@ struct ipa_init_modem_driver_rsp { }; /* Message structure definitions defined in "ipa_qmi_msg.c" */ -extern struct qmi_elem_info ipa_indication_register_req_ei[]; -extern struct qmi_elem_info ipa_indication_register_rsp_ei[]; -extern struct qmi_elem_info ipa_driver_init_complete_req_ei[]; -extern struct qmi_elem_info ipa_driver_init_complete_rsp_ei[]; -extern struct qmi_elem_info ipa_init_complete_ind_ei[]; -extern struct qmi_elem_info ipa_mem_bounds_ei[]; -extern struct qmi_elem_info ipa_mem_array_ei[]; -extern struct qmi_elem_info ipa_mem_range_ei[]; -extern struct qmi_elem_info ipa_init_modem_driver_req_ei[]; -extern struct qmi_elem_info ipa_init_modem_driver_rsp_ei[]; +extern const struct qmi_elem_info ipa_indication_register_req_ei[]; +extern const struct qmi_elem_info ipa_indication_register_rsp_ei[]; +extern const struct qmi_elem_info ipa_driver_init_complete_req_ei[]; +extern const struct qmi_elem_info ipa_driver_init_complete_rsp_ei[]; +extern const struct qmi_elem_info ipa_init_complete_ind_ei[]; +extern const struct qmi_elem_info ipa_mem_bounds_ei[]; +extern const struct qmi_elem_info ipa_mem_array_ei[]; +extern const struct qmi_elem_info ipa_mem_range_ei[]; +extern const struct qmi_elem_info ipa_init_modem_driver_req_ei[]; +extern const struct qmi_elem_info ipa_init_modem_driver_rsp_ei[]; #endif /* !_IPA_QMI_MSG_H_ */ diff --git a/drivers/net/ipa/ipa_reg.c b/drivers/net/ipa/ipa_reg.c index 22f067741d9b..735fa6591609 100644 --- a/drivers/net/ipa/ipa_reg.c +++ b/drivers/net/ipa/ipa_reg.c @@ -9,73 +9,96 @@ #include "ipa.h" #include "ipa_reg.h" -/* Is this register valid and defined for the current IPA version? */ -static bool ipa_reg_valid(struct ipa *ipa, enum ipa_reg_id reg_id) +/* Is this register ID valid for the current IPA version? */ +static bool ipa_reg_id_valid(struct ipa *ipa, enum ipa_reg_id reg_id) { enum ipa_version version = ipa->version; - bool valid; - - /* Check for bogus (out of range) register IDs */ - if ((u32)reg_id >= ipa->regs->reg_count) - return false; switch (reg_id) { case IPA_BCR: case COUNTER_CFG: - valid = version < IPA_VERSION_4_5; - break; + return version < IPA_VERSION_4_5; case IPA_TX_CFG: case FLAVOR_0: case IDLE_INDICATION_CFG: - valid = version >= IPA_VERSION_3_5; - break; + return version >= IPA_VERSION_3_5; case QTIME_TIMESTAMP_CFG: case TIMERS_XO_CLK_DIV_CFG: case TIMERS_PULSE_GRAN_CFG: - valid = version >= IPA_VERSION_4_5; - break; + return version >= IPA_VERSION_4_5; case SRC_RSRC_GRP_45_RSRC_TYPE: case DST_RSRC_GRP_45_RSRC_TYPE: - valid = version <= IPA_VERSION_3_1 || - version == IPA_VERSION_4_5; - break; + return version <= IPA_VERSION_3_1 || + version == IPA_VERSION_4_5; case SRC_RSRC_GRP_67_RSRC_TYPE: case DST_RSRC_GRP_67_RSRC_TYPE: - valid = version <= IPA_VERSION_3_1; - break; + return version <= IPA_VERSION_3_1; case ENDP_FILTER_ROUTER_HSH_CFG: - valid = version != IPA_VERSION_4_2; - break; + return version != IPA_VERSION_4_2; case IRQ_SUSPEND_EN: case IRQ_SUSPEND_CLR: - valid = version >= IPA_VERSION_3_1; - break; + return version >= IPA_VERSION_3_1; + + case COMP_CFG: + case CLKON_CFG: + case ROUTE: + case SHARED_MEM_SIZE: + case QSB_MAX_WRITES: + case QSB_MAX_READS: + case FILT_ROUT_HASH_EN: + case FILT_ROUT_CACHE_CFG: + case FILT_ROUT_HASH_FLUSH: + case FILT_ROUT_CACHE_FLUSH: + case STATE_AGGR_ACTIVE: + case LOCAL_PKT_PROC_CNTXT: + case AGGR_FORCE_CLOSE: + case SRC_RSRC_GRP_01_RSRC_TYPE: + case SRC_RSRC_GRP_23_RSRC_TYPE: + case DST_RSRC_GRP_01_RSRC_TYPE: + case DST_RSRC_GRP_23_RSRC_TYPE: + case ENDP_INIT_CTRL: + case ENDP_INIT_CFG: + case ENDP_INIT_NAT: + case ENDP_INIT_HDR: + case ENDP_INIT_HDR_EXT: + case ENDP_INIT_HDR_METADATA_MASK: + case ENDP_INIT_MODE: + case ENDP_INIT_AGGR: + case ENDP_INIT_HOL_BLOCK_EN: + case ENDP_INIT_HOL_BLOCK_TIMER: + case ENDP_INIT_DEAGGR: + case ENDP_INIT_RSRC_GRP: + case ENDP_INIT_SEQ: + case ENDP_STATUS: + case ENDP_FILTER_CACHE_CFG: + case ENDP_ROUTER_CACHE_CFG: + case IPA_IRQ_STTS: + case IPA_IRQ_EN: + case IPA_IRQ_CLR: + case IPA_IRQ_UC: + case IRQ_SUSPEND_INFO: + return true; /* These should be defined for all versions */ default: - valid = true; /* Others should be defined for all versions */ - break; + return false; } - - /* To be valid, it must be defined */ - - return valid && ipa->regs->reg[reg_id]; } -const struct ipa_reg *ipa_reg(struct ipa *ipa, enum ipa_reg_id reg_id) +const struct reg *ipa_reg(struct ipa *ipa, enum ipa_reg_id reg_id) { - if (WARN_ON(!ipa_reg_valid(ipa, reg_id))) + if (WARN(!ipa_reg_id_valid(ipa, reg_id), "invalid reg %u\n", reg_id)) return NULL; - return ipa->regs->reg[reg_id]; + return reg(ipa->regs, reg_id); } -static const struct ipa_regs *ipa_regs(enum ipa_version version) +static const struct regs *ipa_regs(enum ipa_version version) { switch (version) { case IPA_VERSION_3_1: @@ -86,6 +109,8 @@ static const struct ipa_regs *ipa_regs(enum ipa_version version) return &ipa_regs_v4_2; case IPA_VERSION_4_5: return &ipa_regs_v4_5; + case IPA_VERSION_4_7: + return &ipa_regs_v4_7; case IPA_VERSION_4_9: return &ipa_regs_v4_9; case IPA_VERSION_4_11: @@ -98,7 +123,7 @@ static const struct ipa_regs *ipa_regs(enum ipa_version version) int ipa_reg_init(struct ipa *ipa) { struct device *dev = &ipa->pdev->dev; - const struct ipa_regs *regs; + const struct regs *regs; struct resource *res; regs = ipa_regs(ipa->version); @@ -121,7 +146,6 @@ int ipa_reg_init(struct ipa *ipa) dev_err(dev, "unable to remap \"ipa-reg\" memory\n"); return -ENOMEM; } - ipa->reg_addr = res->start; ipa->regs = regs; return 0; diff --git a/drivers/net/ipa/ipa_reg.h b/drivers/net/ipa/ipa_reg.h index 7bf70f70f63f..28aa1351dd48 100644 --- a/drivers/net/ipa/ipa_reg.h +++ b/drivers/net/ipa/ipa_reg.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. - * Copyright (C) 2018-2022 Linaro Ltd. + * Copyright (C) 2018-2023 Linaro Ltd. */ #ifndef _IPA_REG_H_ #define _IPA_REG_H_ @@ -10,6 +10,7 @@ #include <linux/bug.h> #include "ipa_version.h" +#include "reg.h" struct ipa; @@ -35,7 +36,7 @@ struct ipa; * by register ID. Each entry in the array specifies the base offset and * (for parameterized registers) a non-zero stride value. Not all versions * of IPA define all registers. The offset for a register is returned by - * ipa_reg_offset() when the register's ipa_reg structure is supplied; + * reg_offset() when the register's ipa_reg structure is supplied; * zero is returned for an undefined register (this should never happen). * * Some registers encode multiple fields within them. Each field in @@ -44,9 +45,9 @@ struct ipa; * an array of field masks, indexed by field ID. Two functions are * used to access register fields; both take an ipa_reg structure as * argument. To encode a value to be represented in a register field, - * the value and field ID are passed to ipa_reg_encode(). To extract + * the value and field ID are passed to reg_encode(). To extract * a value encoded in a register field, the field ID is passed to - * ipa_reg_decode(). In addition, for single-bit fields, ipa_reg_bit() + * reg_decode(). In addition, for single-bit fields, reg_bit() * can be used to either encode the bit value, or to generate a mask * used to extract the bit value. */ @@ -59,8 +60,10 @@ enum ipa_reg_id { SHARED_MEM_SIZE, QSB_MAX_WRITES, QSB_MAX_READS, - FILT_ROUT_HASH_EN, - FILT_ROUT_HASH_FLUSH, + FILT_ROUT_HASH_EN, /* Not IPA v5.0+ */ + FILT_ROUT_CACHE_CFG, /* IPA v5.0+ */ + FILT_ROUT_HASH_FLUSH, /* Not IPA v5.0+ */ + FILT_ROUT_CACHE_FLUSH, /* IPA v5.0+ */ STATE_AGGR_ACTIVE, IPA_BCR, /* Not IPA v4.5+ */ LOCAL_PKT_PROC_CNTXT, @@ -95,7 +98,9 @@ enum ipa_reg_id { ENDP_INIT_SEQ, /* TX only */ ENDP_STATUS, ENDP_FILTER_ROUTER_HSH_CFG, /* Not IPA v4.2 */ - /* The IRQ registers are only used for GSI_EE_AP */ + ENDP_FILTER_CACHE_CFG, /* IPA v5.0+ */ + ENDP_ROUTER_CACHE_CFG, /* IPA v5.0+ */ + /* The IRQ registers that follow are only used for GSI_EE_AP */ IPA_IRQ_STTS, IPA_IRQ_EN, IPA_IRQ_CLR, @@ -106,56 +111,6 @@ enum ipa_reg_id { IPA_REG_ID_COUNT, /* Last; not an ID */ }; -/** - * struct ipa_reg - An IPA register descriptor - * @offset: Register offset relative to base of the "ipa-reg" memory - * @stride: Distance between two instances, if parameterized - * @fcount: Number of entries in the @fmask array - * @fmask: Array of mask values defining position and width of fields - * @name: Upper-case name of the IPA register - */ -struct ipa_reg { - u32 offset; - u32 stride; - u32 fcount; - const u32 *fmask; /* BIT(nr) or GENMASK(h, l) */ - const char *name; -}; - -/* Helper macro for defining "simple" (non-parameterized) registers */ -#define IPA_REG(__NAME, __reg_id, __offset) \ - IPA_REG_STRIDE(__NAME, __reg_id, __offset, 0) - -/* Helper macro for defining parameterized registers, specifying stride */ -#define IPA_REG_STRIDE(__NAME, __reg_id, __offset, __stride) \ - static const struct ipa_reg ipa_reg_ ## __reg_id = { \ - .name = #__NAME, \ - .offset = __offset, \ - .stride = __stride, \ - } - -#define IPA_REG_FIELDS(__NAME, __name, __offset) \ - IPA_REG_STRIDE_FIELDS(__NAME, __name, __offset, 0) - -#define IPA_REG_STRIDE_FIELDS(__NAME, __name, __offset, __stride) \ - static const struct ipa_reg ipa_reg_ ## __name = { \ - .name = #__NAME, \ - .offset = __offset, \ - .stride = __stride, \ - .fcount = ARRAY_SIZE(ipa_reg_ ## __name ## _fmask), \ - .fmask = ipa_reg_ ## __name ## _fmask, \ - } - -/** - * struct ipa_regs - Description of registers supported by hardware - * @reg_count: Number of registers in the @reg[] array - * @reg: Array of register descriptors - */ -struct ipa_regs { - u32 reg_count; - const struct ipa_reg **reg; -}; - /* COMP_CFG register */ enum ipa_reg_comp_cfg_field_id { COMP_CFG_ENABLE, /* Not IPA v4.0+ */ @@ -251,14 +206,28 @@ enum ipa_reg_qsb_max_reads_field_id { GEN_QMB_1_MAX_READS_BEATS, /* IPA v4.0+ */ }; +/* FILT_ROUT_CACHE_CFG register */ +enum ipa_reg_filt_rout_cache_cfg_field_id { + ROUTER_CACHE_EN, + FILTER_CACHE_EN, + LOW_PRI_HASH_HIT_DISABLE, + LRU_EVICTION_THRESHOLD, +}; + /* FILT_ROUT_HASH_EN and FILT_ROUT_HASH_FLUSH registers */ -enum ipa_reg_rout_hash_field_id { +enum ipa_reg_filt_rout_hash_field_id { IPV6_ROUTER_HASH, IPV6_FILTER_HASH, IPV4_ROUTER_HASH, IPV4_FILTER_HASH, }; +/* FILT_ROUT_CACHE_FLUSH register */ +enum ipa_reg_filt_rout_cache_field_id { + ROUTER_CACHE, + FILTER_CACHE, +}; + /* BCR register */ enum ipa_bcr_compat { BCR_CMDQ_L_LACK_ONE_ENTRY = 0x0, /* Not IPA v4.2+ */ @@ -298,6 +267,7 @@ enum ipa_reg_ipa_tx_cfg_field_id { DUAL_TX_ENABLE, /* v4.5+ */ SSPND_PA_NO_START_STATE, /* v4,2+, not v4.5 */ SSPND_PA_NO_BQ_STATE, /* v4.2 only */ + HOLB_STICKY_DROP_EN, /* v5.0+ */ }; /* FLAVOR_0 register */ @@ -333,6 +303,7 @@ enum ipa_reg_timers_pulse_gran_cfg_field_id { PULSE_GRAN_0, PULSE_GRAN_1, PULSE_GRAN_2, + PULSE_GRAN_3, }; /* Values for IPA_GRAN_x fields of TIMERS_PULSE_GRAN_CFG */ @@ -382,11 +353,11 @@ enum ipa_reg_endp_init_nat_field_id { NAT_EN, }; -/** enum ipa_nat_en - ENDP_INIT_NAT register NAT_EN field value */ -enum ipa_nat_en { - IPA_NAT_BYPASS = 0x0, - IPA_NAT_SRC = 0x1, - IPA_NAT_DST = 0x2, +/** enum ipa_nat_type - ENDP_INIT_NAT register NAT_EN field value */ +enum ipa_nat_type { + IPA_NAT_TYPE_BYPASS = 0, + IPA_NAT_TYPE_SRC = 1, + IPA_NAT_TYPE_DST = 2, }; /* ENDP_INIT_HDR register */ @@ -415,6 +386,8 @@ enum ipa_reg_endp_init_hdr_ext_field_id { HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB, /* v4.5+ */ HDR_OFST_PKT_SIZE_MSB, /* v4.5+ */ HDR_ADDITIONAL_CONST_LEN_MSB, /* v4.5+ */ + HDR_BYTES_TO_REMOVE_VALID, /* v5.0+ */ + HDR_BYTES_TO_REMOVE, /* v5.0+ */ }; /* ENDP_INIT_MODE register */ @@ -573,6 +546,17 @@ enum ipa_reg_endp_filter_router_hsh_cfg_field_id { ROUTER_HASH_MSK_ALL, /* Bitwise OR of the above 6 fields */ }; +/* ENDP_FILTER_CACHE_CFG and ENDP_ROUTER_CACHE_CFG registers */ +enum ipa_reg_endp_cache_cfg_field_id { + CACHE_MSK_SRC_ID, + CACHE_MSK_SRC_IP, + CACHE_MSK_DST_IP, + CACHE_MSK_SRC_PORT, + CACHE_MSK_DST_PORT, + CACHE_MSK_PROTOCOL, + CACHE_MSK_METADATA, +}; + /* IPA_IRQ_STTS, IPA_IRQ_EN, and IPA_IRQ_CLR registers */ /** * enum ipa_irq_id - Bit positions representing type of IPA IRQ @@ -654,78 +638,15 @@ enum ipa_reg_ipa_irq_uc_field_id { UC_INTR, }; -extern const struct ipa_regs ipa_regs_v3_1; -extern const struct ipa_regs ipa_regs_v3_5_1; -extern const struct ipa_regs ipa_regs_v4_2; -extern const struct ipa_regs ipa_regs_v4_5; -extern const struct ipa_regs ipa_regs_v4_9; -extern const struct ipa_regs ipa_regs_v4_11; - -/* Return the field mask for a field in a register */ -static inline u32 ipa_reg_fmask(const struct ipa_reg *reg, u32 field_id) -{ - if (!reg || WARN_ON(field_id >= reg->fcount)) - return 0; - - return reg->fmask[field_id]; -} - -/* Return the mask for a single-bit field in a register */ -static inline u32 ipa_reg_bit(const struct ipa_reg *reg, u32 field_id) -{ - u32 fmask = ipa_reg_fmask(reg, field_id); - - WARN_ON(!is_power_of_2(fmask)); - - return fmask; -} - -/* Encode a value into the given field of a register */ -static inline u32 -ipa_reg_encode(const struct ipa_reg *reg, u32 field_id, u32 val) -{ - u32 fmask = ipa_reg_fmask(reg, field_id); - - if (!fmask) - return 0; - - val <<= __ffs(fmask); - if (WARN_ON(val & ~fmask)) - return 0; - - return val; -} - -/* Given a register value, decode (extract) the value in the given field */ -static inline u32 -ipa_reg_decode(const struct ipa_reg *reg, u32 field_id, u32 val) -{ - u32 fmask = ipa_reg_fmask(reg, field_id); - - return fmask ? (val & fmask) >> __ffs(fmask) : 0; -} - -/* Return the maximum value representable by the given field; always 2^n - 1 */ -static inline u32 ipa_reg_field_max(const struct ipa_reg *reg, u32 field_id) -{ - u32 fmask = ipa_reg_fmask(reg, field_id); - - return fmask ? fmask >> __ffs(fmask) : 0; -} - -const struct ipa_reg *ipa_reg(struct ipa *ipa, enum ipa_reg_id reg_id); - -/* Returns 0 for NULL reg; warning will have already been issued */ -static inline u32 ipa_reg_offset(const struct ipa_reg *reg) -{ - return reg ? reg->offset : 0; -} +extern const struct regs ipa_regs_v3_1; +extern const struct regs ipa_regs_v3_5_1; +extern const struct regs ipa_regs_v4_2; +extern const struct regs ipa_regs_v4_5; +extern const struct regs ipa_regs_v4_7; +extern const struct regs ipa_regs_v4_9; +extern const struct regs ipa_regs_v4_11; -/* Returns 0 for NULL reg; warning will have already been issued */ -static inline u32 ipa_reg_n_offset(const struct ipa_reg *reg, u32 n) -{ - return reg ? reg->offset + n * reg->stride : 0; -} +const struct reg *ipa_reg(struct ipa *ipa, enum ipa_reg_id reg_id); int ipa_reg_init(struct ipa *ipa); void ipa_reg_exit(struct ipa *ipa); diff --git a/drivers/net/ipa/ipa_resource.c b/drivers/net/ipa/ipa_resource.c index a257f0e5e361..82c88a744d10 100644 --- a/drivers/net/ipa/ipa_resource.c +++ b/drivers/net/ipa/ipa_resource.c @@ -70,20 +70,20 @@ static bool ipa_resource_limits_valid(struct ipa *ipa, static void ipa_resource_config_common(struct ipa *ipa, u32 resource_type, - const struct ipa_reg *reg, + const struct reg *reg, const struct ipa_resource_limits *xlimits, const struct ipa_resource_limits *ylimits) { u32 val; - val = ipa_reg_encode(reg, X_MIN_LIM, xlimits->min); - val |= ipa_reg_encode(reg, X_MAX_LIM, xlimits->max); + val = reg_encode(reg, X_MIN_LIM, xlimits->min); + val |= reg_encode(reg, X_MAX_LIM, xlimits->max); if (ylimits) { - val |= ipa_reg_encode(reg, Y_MIN_LIM, ylimits->min); - val |= ipa_reg_encode(reg, Y_MAX_LIM, ylimits->max); + val |= reg_encode(reg, Y_MIN_LIM, ylimits->min); + val |= reg_encode(reg, Y_MAX_LIM, ylimits->max); } - iowrite32(val, ipa->reg_virt + ipa_reg_n_offset(reg, resource_type)); + iowrite32(val, ipa->reg_virt + reg_n_offset(reg, resource_type)); } static void ipa_resource_config_src(struct ipa *ipa, u32 resource_type, @@ -92,7 +92,7 @@ static void ipa_resource_config_src(struct ipa *ipa, u32 resource_type, u32 group_count = data->rsrc_group_src_count; const struct ipa_resource_limits *ylimits; const struct ipa_resource *resource; - const struct ipa_reg *reg; + const struct reg *reg; resource = &data->resource_src[resource_type]; @@ -129,7 +129,7 @@ static void ipa_resource_config_dst(struct ipa *ipa, u32 resource_type, u32 group_count = data->rsrc_group_dst_count; const struct ipa_resource_limits *ylimits; const struct ipa_resource *resource; - const struct ipa_reg *reg; + const struct reg *reg; resource = &data->resource_dst[resource_type]; diff --git a/drivers/net/ipa/ipa_sysfs.c b/drivers/net/ipa/ipa_sysfs.c index 5cbc15a971f9..14bd2f903045 100644 --- a/drivers/net/ipa/ipa_sysfs.c +++ b/drivers/net/ipa/ipa_sysfs.c @@ -46,7 +46,7 @@ version_show(struct device *dev, struct device_attribute *attr, char *buf) { struct ipa *ipa = dev_get_drvdata(dev); - return scnprintf(buf, PAGE_SIZE, "%s\n", ipa_version_string(ipa)); + return sysfs_emit(buf, "%s\n", ipa_version_string(ipa)); } static DEVICE_ATTR_RO(version); @@ -70,7 +70,7 @@ static ssize_t rx_offload_show(struct device *dev, { struct ipa *ipa = dev_get_drvdata(dev); - return scnprintf(buf, PAGE_SIZE, "%s\n", ipa_offload_string(ipa)); + return sysfs_emit(buf, "%s\n", ipa_offload_string(ipa)); } static DEVICE_ATTR_RO(rx_offload); @@ -80,7 +80,7 @@ static ssize_t tx_offload_show(struct device *dev, { struct ipa *ipa = dev_get_drvdata(dev); - return scnprintf(buf, PAGE_SIZE, "%s\n", ipa_offload_string(ipa)); + return sysfs_emit(buf, "%s\n", ipa_offload_string(ipa)); } static DEVICE_ATTR_RO(tx_offload); diff --git a/drivers/net/ipa/ipa_table.c b/drivers/net/ipa/ipa_table.c index 510ff2dc8999..f0529c31d0b6 100644 --- a/drivers/net/ipa/ipa_table.c +++ b/drivers/net/ipa/ipa_table.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. - * Copyright (C) 2018-2022 Linaro Ltd. + * Copyright (C) 2018-2023 Linaro Ltd. */ #include <linux/types.h> @@ -32,8 +32,8 @@ * endian 64-bit "slot" that holds the address of a rule definition. (The * size of these slots is 64 bits regardless of the host DMA address size.) * - * Separate tables (both filter and route) used for IPv4 and IPv6. There - * are normally another set of "hashed" filter and route tables, which are + * Separate tables (both filter and route) are used for IPv4 and IPv6. There + * is normally another set of "hashed" filter and route tables, which are * used with a hash of message metadata. Hashed operation is not supported * by all IPA hardware (IPA v4.2 doesn't support hashed tables). * @@ -51,19 +51,32 @@ * Each filter rule is associated with an AP or modem TX endpoint, though * not all TX endpoints support filtering. The first 64-bit slot in a * filter table is a bitmap indicating which endpoints have entries in - * the table. The low-order bit (bit 0) in this bitmap represents a - * special global filter, which applies to all traffic. This is not - * used in the current code. Bit 1, if set, indicates that there is an - * entry (i.e. slot containing a system address referring to a rule) for - * endpoint 0 in the table. Bit 3, if set, indicates there is an entry - * for endpoint 2, and so on. Space is set aside in IPA local memory to - * hold as many filter table entries as might be required, but typically - * they are not all used. + * the table. Each set bit in this bitmap indicates the presence of the + * address of a filter rule in the memory following the bitmap. Until IPA + * v5.0, the low-order bit (bit 0) in this bitmap represents a special + * global filter, which applies to all traffic. Otherwise the position of + * each set bit represents an endpoint for which a filter rule is defined. + * + * The global rule is not used in current code, and support for it is + * removed starting at IPA v5.0. For IPA v5.0+, the endpoint bitmap + * position defines the endpoint ID--i.e. if bit 1 is set in the endpoint + * bitmap, endpoint 1 has a filter rule. Older versions of IPA represent + * the presence of a filter rule for endpoint X by bit (X + 1) being set. + * I.e., bit 1 set indicates the presence of a filter rule for endpoint 0, + * and bit 3 set means there is a filter rule present for endpoint 2. + * + * Each filter table entry has the address of a set of equations that + * implement a filter rule. So following the endpoint bitmap there + * will be such an address/entry for each endpoint with a set bit in + * the bitmap. * * The AP initializes all entries in a filter table to refer to a "zero" - * entry. Once initialized the modem and AP update the entries for - * endpoints they "own" directly. Currently the AP does not use the - * IPA filtering functionality. + * rule. Once initialized, the modem and AP update the entries for + * endpoints they "own" directly. Currently the AP does not use the IPA + * filtering functionality. + * + * This diagram shows an example of a filter table with an endpoint + * bitmap as defined prior to IPA v5.0. * * IPA Filter Table * ---------------------- @@ -106,12 +119,6 @@ * ---------------------- */ -/* Assignment of route table entries to the modem and AP */ -#define IPA_ROUTE_MODEM_MIN 0 -#define IPA_ROUTE_AP_MIN IPA_ROUTE_MODEM_COUNT -#define IPA_ROUTE_AP_COUNT \ - (IPA_ROUTE_COUNT_MAX - IPA_ROUTE_MODEM_COUNT) - /* Filter or route rules consist of a set of 32-bit values followed by a * 32-bit all-zero rule list terminator. The "zero rule" is simply an * all-zero rule followed by the list terminator. @@ -135,85 +142,40 @@ static void ipa_table_validate_build(void) * assumes that it can be written using a pointer to __le64. */ BUILD_BUG_ON(IPA_ZERO_RULE_SIZE != sizeof(__le64)); - - /* Impose a practical limit on the number of routes */ - BUILD_BUG_ON(IPA_ROUTE_COUNT_MAX > 32); - /* The modem must be allotted at least one route table entry */ - BUILD_BUG_ON(!IPA_ROUTE_MODEM_COUNT); - /* But it can't have more than what is available */ - BUILD_BUG_ON(IPA_ROUTE_MODEM_COUNT > IPA_ROUTE_COUNT_MAX); - } -static bool -ipa_table_valid_one(struct ipa *ipa, enum ipa_mem_id mem_id, bool route) +static const struct ipa_mem * +ipa_table_mem(struct ipa *ipa, bool filter, bool hashed, bool ipv6) { - const struct ipa_mem *mem = ipa_mem_find(ipa, mem_id); - struct device *dev = &ipa->pdev->dev; - u32 size; - - if (route) - size = IPA_ROUTE_COUNT_MAX * sizeof(__le64); - else - size = (1 + IPA_FILTER_COUNT_MAX) * sizeof(__le64); - - if (!ipa_cmd_table_valid(ipa, mem, route)) - return false; - - /* mem->size >= size is sufficient, but we'll demand more */ - if (mem->size == size) - return true; - - /* Hashed table regions can be zero size if hashing is not supported */ - if (ipa_table_hash_support(ipa) && !mem->size) - return true; - - dev_err(dev, "%s table region %u size 0x%02x, expected 0x%02x\n", - route ? "route" : "filter", mem_id, mem->size, size); - - return false; + enum ipa_mem_id mem_id; + + mem_id = filter ? hashed ? ipv6 ? IPA_MEM_V6_FILTER_HASHED + : IPA_MEM_V4_FILTER_HASHED + : ipv6 ? IPA_MEM_V6_FILTER + : IPA_MEM_V4_FILTER + : hashed ? ipv6 ? IPA_MEM_V6_ROUTE_HASHED + : IPA_MEM_V4_ROUTE_HASHED + : ipv6 ? IPA_MEM_V6_ROUTE + : IPA_MEM_V4_ROUTE; + + return ipa_mem_find(ipa, mem_id); } -/* Verify the filter and route table memory regions are the expected size */ -bool ipa_table_valid(struct ipa *ipa) -{ - bool valid; - - valid = ipa_table_valid_one(ipa, IPA_MEM_V4_FILTER, false); - valid = valid && ipa_table_valid_one(ipa, IPA_MEM_V6_FILTER, false); - valid = valid && ipa_table_valid_one(ipa, IPA_MEM_V4_ROUTE, true); - valid = valid && ipa_table_valid_one(ipa, IPA_MEM_V6_ROUTE, true); - - if (!ipa_table_hash_support(ipa)) - return valid; - - valid = valid && ipa_table_valid_one(ipa, IPA_MEM_V4_FILTER_HASHED, - false); - valid = valid && ipa_table_valid_one(ipa, IPA_MEM_V6_FILTER_HASHED, - false); - valid = valid && ipa_table_valid_one(ipa, IPA_MEM_V4_ROUTE_HASHED, - true); - valid = valid && ipa_table_valid_one(ipa, IPA_MEM_V6_ROUTE_HASHED, - true); - - return valid; -} - -bool ipa_filter_map_valid(struct ipa *ipa, u32 filter_map) +bool ipa_filtered_valid(struct ipa *ipa, u64 filtered) { struct device *dev = &ipa->pdev->dev; u32 count; - if (!filter_map) { + if (!filtered) { dev_err(dev, "at least one filtering endpoint is required\n"); return false; } - count = hweight32(filter_map); - if (count > IPA_FILTER_COUNT_MAX) { - dev_err(dev, "too many filtering endpoints (%u, max %u)\n", - count, IPA_FILTER_COUNT_MAX); + count = hweight64(filtered); + if (count > ipa->filter_count) { + dev_err(dev, "too many filtering endpoints (%u > %u)\n", + count, ipa->filter_count); return false; } @@ -229,7 +191,7 @@ static dma_addr_t ipa_table_addr(struct ipa *ipa, bool filter_mask, u16 count) if (!count) return 0; - WARN_ON(count > max_t(u32, IPA_FILTER_COUNT_MAX, IPA_ROUTE_COUNT_MAX)); + WARN_ON(count > max_t(u32, ipa->filter_count, ipa->route_count)); /* Skip over the zero rule and possibly the filter mask */ skip = filter_mask ? 1 : 2; @@ -238,16 +200,17 @@ static dma_addr_t ipa_table_addr(struct ipa *ipa, bool filter_mask, u16 count) } static void ipa_table_reset_add(struct gsi_trans *trans, bool filter, - u16 first, u16 count, enum ipa_mem_id mem_id) + bool hashed, bool ipv6, u16 first, u16 count) { struct ipa *ipa = container_of(trans->gsi, struct ipa, gsi); - const struct ipa_mem *mem = ipa_mem_find(ipa, mem_id); + const struct ipa_mem *mem; dma_addr_t addr; u32 offset; u16 size; - /* Nothing to do if the table memory region is empty */ - if (!mem->size) + /* Nothing to do if the memory region is doesn't exist or is empty */ + mem = ipa_table_mem(ipa, filter, hashed, ipv6); + if (!mem || !mem->size) return; if (filter) @@ -265,14 +228,13 @@ static void ipa_table_reset_add(struct gsi_trans *trans, bool filter, * for the IPv4 and IPv6 non-hashed and hashed filter tables. */ static int -ipa_filter_reset_table(struct ipa *ipa, enum ipa_mem_id mem_id, bool modem) +ipa_filter_reset_table(struct ipa *ipa, bool hashed, bool ipv6, bool modem) { - u32 ep_mask = ipa->filter_map; - u32 count = hweight32(ep_mask); + u64 ep_mask = ipa->filtered; struct gsi_trans *trans; enum gsi_ee_id ee_id; - trans = ipa_cmd_trans_alloc(ipa, count); + trans = ipa_cmd_trans_alloc(ipa, hweight64(ep_mask)); if (!trans) { dev_err(&ipa->pdev->dev, "no transaction for %s filter reset\n", @@ -291,7 +253,7 @@ ipa_filter_reset_table(struct ipa *ipa, enum ipa_mem_id mem_id, bool modem) if (endpoint->ee_id != ee_id) continue; - ipa_table_reset_add(trans, true, endpoint_id, 1, mem_id); + ipa_table_reset_add(trans, true, hashed, ipv6, endpoint_id, 1); } gsi_trans_commit_wait(trans); @@ -307,18 +269,18 @@ static int ipa_filter_reset(struct ipa *ipa, bool modem) { int ret; - ret = ipa_filter_reset_table(ipa, IPA_MEM_V4_FILTER, modem); + ret = ipa_filter_reset_table(ipa, false, false, modem); if (ret) return ret; - ret = ipa_filter_reset_table(ipa, IPA_MEM_V4_FILTER_HASHED, modem); + ret = ipa_filter_reset_table(ipa, true, false, modem); if (ret) return ret; - ret = ipa_filter_reset_table(ipa, IPA_MEM_V6_FILTER, modem); + ret = ipa_filter_reset_table(ipa, false, true, modem); if (ret) return ret; - ret = ipa_filter_reset_table(ipa, IPA_MEM_V6_FILTER_HASHED, modem); + ret = ipa_filter_reset_table(ipa, true, true, modem); return ret; } @@ -329,6 +291,7 @@ static int ipa_filter_reset(struct ipa *ipa, bool modem) * */ static int ipa_route_reset(struct ipa *ipa, bool modem) { + u32 modem_route_count = ipa->modem_route_count; struct gsi_trans *trans; u16 first; u16 count; @@ -342,20 +305,18 @@ static int ipa_route_reset(struct ipa *ipa, bool modem) } if (modem) { - first = IPA_ROUTE_MODEM_MIN; - count = IPA_ROUTE_MODEM_COUNT; + first = 0; + count = modem_route_count; } else { - first = IPA_ROUTE_AP_MIN; - count = IPA_ROUTE_AP_COUNT; + first = modem_route_count; + count = ipa->route_count - modem_route_count; } - ipa_table_reset_add(trans, false, first, count, IPA_MEM_V4_ROUTE); - ipa_table_reset_add(trans, false, first, count, - IPA_MEM_V4_ROUTE_HASHED); + ipa_table_reset_add(trans, false, false, false, first, count); + ipa_table_reset_add(trans, false, true, false, first, count); - ipa_table_reset_add(trans, false, first, count, IPA_MEM_V6_ROUTE); - ipa_table_reset_add(trans, false, first, count, - IPA_MEM_V6_ROUTE_HASHED); + ipa_table_reset_add(trans, false, false, true, first, count); + ipa_table_reset_add(trans, false, true, true, first, count); gsi_trans_commit_wait(trans); @@ -384,9 +345,8 @@ void ipa_table_reset(struct ipa *ipa, bool modem) int ipa_table_hash_flush(struct ipa *ipa) { - const struct ipa_reg *reg; struct gsi_trans *trans; - u32 offset; + const struct reg *reg; u32 val; if (!ipa_table_hash_support(ipa)) @@ -398,31 +358,37 @@ int ipa_table_hash_flush(struct ipa *ipa) return -EBUSY; } - reg = ipa_reg(ipa, FILT_ROUT_HASH_FLUSH); - offset = ipa_reg_offset(reg); + if (ipa->version < IPA_VERSION_5_0) { + reg = ipa_reg(ipa, FILT_ROUT_HASH_FLUSH); - val = ipa_reg_bit(reg, IPV6_ROUTER_HASH); - val |= ipa_reg_bit(reg, IPV6_FILTER_HASH); - val |= ipa_reg_bit(reg, IPV4_ROUTER_HASH); - val |= ipa_reg_bit(reg, IPV4_FILTER_HASH); + val = reg_bit(reg, IPV6_ROUTER_HASH); + val |= reg_bit(reg, IPV6_FILTER_HASH); + val |= reg_bit(reg, IPV4_ROUTER_HASH); + val |= reg_bit(reg, IPV4_FILTER_HASH); + } else { + reg = ipa_reg(ipa, FILT_ROUT_CACHE_FLUSH); - ipa_cmd_register_write_add(trans, offset, val, val, false); + /* IPA v5.0+ uses a unified cache (both IPv4 and IPv6) */ + val = reg_bit(reg, ROUTER_CACHE); + val |= reg_bit(reg, FILTER_CACHE); + } + + ipa_cmd_register_write_add(trans, reg_offset(reg), val, val, false); gsi_trans_commit_wait(trans); return 0; } -static void ipa_table_init_add(struct gsi_trans *trans, bool filter, - enum ipa_cmd_opcode opcode, - enum ipa_mem_id mem_id, - enum ipa_mem_id hash_mem_id) +static void ipa_table_init_add(struct gsi_trans *trans, bool filter, bool ipv6) { struct ipa *ipa = container_of(trans->gsi, struct ipa, gsi); - const struct ipa_mem *hash_mem = ipa_mem_find(ipa, hash_mem_id); - const struct ipa_mem *mem = ipa_mem_find(ipa, mem_id); + const struct ipa_mem *hash_mem; + enum ipa_cmd_opcode opcode; + const struct ipa_mem *mem; dma_addr_t hash_addr; dma_addr_t addr; + u32 hash_offset; u32 zero_offset; u16 hash_count; u32 zero_size; @@ -430,6 +396,16 @@ static void ipa_table_init_add(struct gsi_trans *trans, bool filter, u16 count; u16 size; + opcode = filter ? ipv6 ? IPA_CMD_IP_V6_FILTER_INIT + : IPA_CMD_IP_V4_FILTER_INIT + : ipv6 ? IPA_CMD_IP_V6_ROUTING_INIT + : IPA_CMD_IP_V4_ROUTING_INIT; + + /* The non-hashed region will exist (see ipa_table_mem_valid()) */ + mem = ipa_table_mem(ipa, filter, false, ipv6); + hash_mem = ipa_table_mem(ipa, filter, true, ipv6); + hash_offset = hash_mem ? hash_mem->offset : 0; + /* Compute the number of table entries to initialize */ if (filter) { /* The number of filtering endpoints determines number of @@ -437,14 +413,14 @@ static void ipa_table_init_add(struct gsi_trans *trans, bool filter, * to hold the bitmap itself. The size of the hashed filter * table is either the same as the non-hashed one, or zero. */ - count = 1 + hweight32(ipa->filter_map); - hash_count = hash_mem->size ? count : 0; + count = 1 + hweight64(ipa->filtered); + hash_count = hash_mem && hash_mem->size ? count : 0; } else { /* The size of a route table region determines the number * of entries it has. */ count = mem->size / sizeof(__le64); - hash_count = hash_mem->size / sizeof(__le64); + hash_count = hash_mem ? hash_mem->size / sizeof(__le64) : 0; } size = count * sizeof(__le64); hash_size = hash_count * sizeof(__le64); @@ -453,7 +429,7 @@ static void ipa_table_init_add(struct gsi_trans *trans, bool filter, hash_addr = ipa_table_addr(ipa, filter, hash_count); ipa_cmd_table_init_add(trans, opcode, size, mem->offset, addr, - hash_size, hash_mem->offset, hash_addr); + hash_size, hash_offset, hash_addr); if (!filter) return; @@ -466,7 +442,7 @@ static void ipa_table_init_add(struct gsi_trans *trans, bool filter, return; /* Zero the unused space in the hashed filter table */ - zero_offset = hash_mem->offset + hash_size; + zero_offset = hash_offset + hash_size; zero_size = hash_mem->size - hash_size; ipa_cmd_dma_shared_mem_add(trans, zero_offset, zero_size, ipa->zero_addr, true); @@ -495,17 +471,10 @@ int ipa_table_setup(struct ipa *ipa) return -EBUSY; } - ipa_table_init_add(trans, false, IPA_CMD_IP_V4_ROUTING_INIT, - IPA_MEM_V4_ROUTE, IPA_MEM_V4_ROUTE_HASHED); - - ipa_table_init_add(trans, false, IPA_CMD_IP_V6_ROUTING_INIT, - IPA_MEM_V6_ROUTE, IPA_MEM_V6_ROUTE_HASHED); - - ipa_table_init_add(trans, true, IPA_CMD_IP_V4_FILTER_INIT, - IPA_MEM_V4_FILTER, IPA_MEM_V4_FILTER_HASHED); - - ipa_table_init_add(trans, true, IPA_CMD_IP_V6_FILTER_INIT, - IPA_MEM_V6_FILTER, IPA_MEM_V6_FILTER_HASHED); + ipa_table_init_add(trans, false, false); + ipa_table_init_add(trans, false, true); + ipa_table_init_add(trans, true, false); + ipa_table_init_add(trans, true, true); gsi_trans_commit_wait(trans); @@ -523,17 +492,26 @@ static void ipa_filter_tuple_zero(struct ipa_endpoint *endpoint) { u32 endpoint_id = endpoint->endpoint_id; struct ipa *ipa = endpoint->ipa; - const struct ipa_reg *reg; + const struct reg *reg; u32 offset; u32 val; - reg = ipa_reg(ipa, ENDP_FILTER_ROUTER_HSH_CFG); + if (ipa->version < IPA_VERSION_5_0) { + reg = ipa_reg(ipa, ENDP_FILTER_ROUTER_HSH_CFG); - offset = ipa_reg_n_offset(reg, endpoint_id); - val = ioread32(endpoint->ipa->reg_virt + offset); + offset = reg_n_offset(reg, endpoint_id); + val = ioread32(endpoint->ipa->reg_virt + offset); - /* Zero all filter-related fields, preserving the rest */ - val &= ~ipa_reg_fmask(reg, FILTER_HASH_MSK_ALL); + /* Zero all filter-related fields, preserving the rest */ + val &= ~reg_fmask(reg, FILTER_HASH_MSK_ALL); + } else { + /* IPA v5.0 separates filter and router cache configuration */ + reg = ipa_reg(ipa, ENDP_FILTER_CACHE_CFG); + offset = reg_n_offset(reg, endpoint_id); + + /* Zero all filter-related fields */ + val = 0; + } iowrite32(val, endpoint->ipa->reg_virt + offset); } @@ -542,7 +520,7 @@ static void ipa_filter_tuple_zero(struct ipa_endpoint *endpoint) static void ipa_filter_config(struct ipa *ipa, bool modem) { enum gsi_ee_id ee_id = modem ? GSI_EE_MODEM : GSI_EE_AP; - u32 ep_mask = ipa->filter_map; + u64 ep_mask = ipa->filtered; if (!ipa_table_hash_support(ipa)) return; @@ -559,10 +537,9 @@ static void ipa_filter_config(struct ipa *ipa, bool modem) } } -static bool ipa_route_id_modem(u32 route_id) +static bool ipa_route_id_modem(struct ipa *ipa, u32 route_id) { - return route_id >= IPA_ROUTE_MODEM_MIN && - route_id <= IPA_ROUTE_MODEM_MIN + IPA_ROUTE_MODEM_COUNT - 1; + return route_id < ipa->modem_route_count; } /** @@ -574,17 +551,26 @@ static bool ipa_route_id_modem(u32 route_id) */ static void ipa_route_tuple_zero(struct ipa *ipa, u32 route_id) { - const struct ipa_reg *reg; + const struct reg *reg; u32 offset; u32 val; - reg = ipa_reg(ipa, ENDP_FILTER_ROUTER_HSH_CFG); - offset = ipa_reg_n_offset(reg, route_id); + if (ipa->version < IPA_VERSION_5_0) { + reg = ipa_reg(ipa, ENDP_FILTER_ROUTER_HSH_CFG); + offset = reg_n_offset(reg, route_id); - val = ioread32(ipa->reg_virt + offset); + val = ioread32(ipa->reg_virt + offset); - /* Zero all route-related fields, preserving the rest */ - val &= ~ipa_reg_fmask(reg, ROUTER_HASH_MSK_ALL); + /* Zero all route-related fields, preserving the rest */ + val &= ~reg_fmask(reg, ROUTER_HASH_MSK_ALL); + } else { + /* IPA v5.0 separates filter and router cache configuration */ + reg = ipa_reg(ipa, ENDP_ROUTER_CACHE_CFG); + offset = reg_n_offset(reg, route_id); + + /* Zero all route-related fields */ + val = 0; + } iowrite32(val, ipa->reg_virt + offset); } @@ -597,8 +583,8 @@ static void ipa_route_config(struct ipa *ipa, bool modem) if (!ipa_table_hash_support(ipa)) return; - for (route_id = 0; route_id < IPA_ROUTE_COUNT_MAX; route_id++) - if (ipa_route_id_modem(route_id) == modem) + for (route_id = 0; route_id < ipa->route_count; route_id++) + if (ipa_route_id_modem(ipa, route_id) == modem) ipa_route_tuple_zero(ipa, route_id); } @@ -611,14 +597,94 @@ void ipa_table_config(struct ipa *ipa) ipa_route_config(ipa, true); } -/* - * Initialize a coherent DMA allocation containing initialized filter and +/* Verify the sizes of all IPA table filter or routing table memory regions + * are valid. If valid, this records the size of the routing table. + */ +bool ipa_table_mem_valid(struct ipa *ipa, bool filter) +{ + bool hash_support = ipa_table_hash_support(ipa); + const struct ipa_mem *mem_hashed; + const struct ipa_mem *mem_ipv4; + const struct ipa_mem *mem_ipv6; + u32 count; + + /* IPv4 and IPv6 non-hashed tables are expected to be defined and + * have the same size. Both must have at least two entries (and + * would normally have more than that). + */ + mem_ipv4 = ipa_table_mem(ipa, filter, false, false); + if (!mem_ipv4) + return false; + + mem_ipv6 = ipa_table_mem(ipa, filter, false, true); + if (!mem_ipv6) + return false; + + if (mem_ipv4->size != mem_ipv6->size) + return false; + + /* Compute and record the number of entries for each table type */ + count = mem_ipv4->size / sizeof(__le64); + if (count < 2) + return false; + if (filter) + ipa->filter_count = count - 1; /* Filter map in first entry */ + else + ipa->route_count = count; + + /* Table offset and size must fit in TABLE_INIT command fields */ + if (!ipa_cmd_table_init_valid(ipa, mem_ipv4, !filter)) + return false; + + /* Make sure the regions are big enough */ + if (filter) { + /* Filter tables must able to hold the endpoint bitmap plus + * an entry for each endpoint that supports filtering + */ + if (count < 1 + hweight64(ipa->filtered)) + return false; + } else { + /* Routing tables must be able to hold all modem entries, + * plus at least one entry for the AP. + */ + if (count < ipa->modem_route_count + 1) + return false; + } + + /* If hashing is supported, hashed tables are expected to be defined, + * and have the same size as non-hashed tables. If hashing is not + * supported, hashed tables are expected to have zero size (or not + * be defined). + */ + mem_hashed = ipa_table_mem(ipa, filter, true, false); + if (hash_support) { + if (!mem_hashed || mem_hashed->size != mem_ipv4->size) + return false; + } else { + if (mem_hashed && mem_hashed->size) + return false; + } + + /* Same check for IPv6 tables */ + mem_hashed = ipa_table_mem(ipa, filter, true, true); + if (hash_support) { + if (!mem_hashed || mem_hashed->size != mem_ipv6->size) + return false; + } else { + if (mem_hashed && mem_hashed->size) + return false; + } + + return true; +} + +/* Initialize a coherent DMA allocation containing initialized filter and * route table data. This is used when initializing or resetting the IPA * filter or route table. * * The first entry in a filter table contains a bitmap indicating which * endpoints contain entries in the table. In addition to that first entry, - * there are at most IPA_FILTER_COUNT_MAX entries that follow. Filter table + * there is a fixed maximum number of entries that follow. Filter table * entries are 64 bits wide, and (other than the bitmap) contain the DMA * address of a filter rule. A "zero rule" indicates no filtering, and * consists of 64 bits of zeroes. When a filter table is initialized (or @@ -629,12 +695,6 @@ void ipa_table_config(struct ipa *ipa) * when a route table is initialized or reset, its entries are made to refer * to the zero rule. The zero rule is shared for route and filter tables. * - * Note that the IPA hardware requires a filter or route rule address to be - * aligned on a 128 byte boundary. The coherent DMA buffer we allocate here - * has a minimum alignment, and we place the zero rule at the base of that - * allocated space. In ipa_table_init() we verify the minimum DMA allocation - * meets our requirement. - * * +-------------------+ * --> | zero rule | * / |-------------------| @@ -642,8 +702,8 @@ void ipa_table_config(struct ipa *ipa) * |\ |-------------------| * | ---- zero rule address | \ * |\ |-------------------| | - * | ---- zero rule address | | IPA_FILTER_COUNT_MAX - * | |-------------------| > or IPA_ROUTE_COUNT_MAX, + * | ---- zero rule address | | Max IPA filter count + * | |-------------------| > or IPA route count, * | ... | whichever is greater * \ |-------------------| | * ---- zero rule address | / @@ -651,15 +711,17 @@ void ipa_table_config(struct ipa *ipa) */ int ipa_table_init(struct ipa *ipa) { - u32 count = max_t(u32, IPA_FILTER_COUNT_MAX, IPA_ROUTE_COUNT_MAX); struct device *dev = &ipa->pdev->dev; dma_addr_t addr; __le64 le_addr; __le64 *virt; size_t size; + u32 count; ipa_table_validate_build(); + count = max_t(u32, ipa->filter_count, ipa->route_count); + /* The IPA hardware requires route and filter table rules to be * aligned on a 128-byte boundary. We put the "zero rule" at the * base of the table area allocated here. The DMA address returned @@ -677,12 +739,16 @@ int ipa_table_init(struct ipa *ipa) /* First slot is the zero rule */ *virt++ = 0; - /* Next is the filter table bitmap. The "soft" bitmap value - * must be converted to the hardware representation by shifting - * it left one position. (Bit 0 repesents global filtering, - * which is possible but not used.) + /* Next is the filter table bitmap. The "soft" bitmap value might + * need to be converted to the hardware representation by shifting + * it left one position. Prior to IPA v5.0, bit 0 repesents global + * filtering, which is possible but not used. IPA v5.0+ eliminated + * that option, so there's no shifting required. */ - *virt++ = cpu_to_le64((u64)ipa->filter_map << 1); + if (ipa->version < IPA_VERSION_5_0) + *virt++ = cpu_to_le64(ipa->filtered << 1); + else + *virt++ = cpu_to_le64(ipa->filtered); /* All the rest contain the DMA address of the zero rule */ le_addr = cpu_to_le64(addr); @@ -694,7 +760,7 @@ int ipa_table_init(struct ipa *ipa) void ipa_table_exit(struct ipa *ipa) { - u32 count = max_t(u32, 1 + IPA_FILTER_COUNT_MAX, IPA_ROUTE_COUNT_MAX); + u32 count = max_t(u32, 1 + ipa->filter_count, ipa->route_count); struct device *dev = &ipa->pdev->dev; size_t size; diff --git a/drivers/net/ipa/ipa_table.h b/drivers/net/ipa/ipa_table.h index 395189f75d78..7cc951904bb4 100644 --- a/drivers/net/ipa/ipa_table.h +++ b/drivers/net/ipa/ipa_table.h @@ -10,31 +10,14 @@ struct ipa; -/* The maximum number of filter table entries (IPv4, IPv6; hashed or not) */ -#define IPA_FILTER_COUNT_MAX 14 - -/* The number of route table entries allotted to the modem */ -#define IPA_ROUTE_MODEM_COUNT 8 - -/* The maximum number of route table entries (IPv4, IPv6; hashed or not) */ -#define IPA_ROUTE_COUNT_MAX 15 - /** - * ipa_table_valid() - Validate route and filter table memory regions + * ipa_filtered_valid() - Validate a filter table endpoint bitmap * @ipa: IPA pointer + * @filtered: Filter table endpoint bitmap to check * * Return: true if all regions are valid, false otherwise */ -bool ipa_table_valid(struct ipa *ipa); - -/** - * ipa_filter_map_valid() - Validate a filter table endpoint bitmap - * @ipa: IPA pointer - * @filter_mask: Filter table endpoint bitmap to check - * - * Return: true if all regions are valid, false otherwise - */ -bool ipa_filter_map_valid(struct ipa *ipa, u32 filter_mask); +bool ipa_filtered_valid(struct ipa *ipa, u64 filtered); /** * ipa_table_hash_support() - Return true if hashed tables are supported @@ -86,4 +69,11 @@ int ipa_table_init(struct ipa *ipa); */ void ipa_table_exit(struct ipa *ipa); +/** + * ipa_table_mem_valid() - Validate sizes of table memory regions + * @ipa: IPA pointer + * @filter: Whether to check filter or routing tables + */ +bool ipa_table_mem_valid(struct ipa *ipa, bool filter); + #endif /* _IPA_TABLE_H_ */ diff --git a/drivers/net/ipa/ipa_uc.c b/drivers/net/ipa/ipa_uc.c index f0ee47281015..7eaa0b4ebed9 100644 --- a/drivers/net/ipa/ipa_uc.c +++ b/drivers/net/ipa/ipa_uc.c @@ -124,7 +124,7 @@ static struct ipa_uc_mem_area *ipa_uc_shared(struct ipa *ipa) } /* Microcontroller event IPA interrupt handler */ -static void ipa_uc_event_handler(struct ipa *ipa, enum ipa_irq_id irq_id) +static void ipa_uc_event_handler(struct ipa *ipa) { struct ipa_uc_mem_area *shared = ipa_uc_shared(ipa); struct device *dev = &ipa->pdev->dev; @@ -138,7 +138,7 @@ static void ipa_uc_event_handler(struct ipa *ipa, enum ipa_irq_id irq_id) } /* Microcontroller response IPA interrupt handler */ -static void ipa_uc_response_hdlr(struct ipa *ipa, enum ipa_irq_id irq_id) +static void ipa_uc_response_hdlr(struct ipa *ipa) { struct ipa_uc_mem_area *shared = ipa_uc_shared(ipa); struct device *dev = &ipa->pdev->dev; @@ -170,13 +170,22 @@ static void ipa_uc_response_hdlr(struct ipa *ipa, enum ipa_irq_id irq_id) } } +void ipa_uc_interrupt_handler(struct ipa *ipa, enum ipa_irq_id irq_id) +{ + /* Silently ignore anything unrecognized */ + if (irq_id == IPA_IRQ_UC_0) + ipa_uc_event_handler(ipa); + else if (irq_id == IPA_IRQ_UC_1) + ipa_uc_response_hdlr(ipa); +} + /* Configure the IPA microcontroller subsystem */ void ipa_uc_config(struct ipa *ipa) { ipa->uc_powered = false; ipa->uc_loaded = false; - ipa_interrupt_add(ipa->interrupt, IPA_IRQ_UC_0, ipa_uc_event_handler); - ipa_interrupt_add(ipa->interrupt, IPA_IRQ_UC_1, ipa_uc_response_hdlr); + ipa_interrupt_enable(ipa, IPA_IRQ_UC_0); + ipa_interrupt_enable(ipa, IPA_IRQ_UC_1); } /* Inverse of ipa_uc_config() */ @@ -184,8 +193,8 @@ void ipa_uc_deconfig(struct ipa *ipa) { struct device *dev = &ipa->pdev->dev; - ipa_interrupt_remove(ipa->interrupt, IPA_IRQ_UC_1); - ipa_interrupt_remove(ipa->interrupt, IPA_IRQ_UC_0); + ipa_interrupt_disable(ipa, IPA_IRQ_UC_1); + ipa_interrupt_disable(ipa, IPA_IRQ_UC_0); if (ipa->uc_loaded) ipa_power_retention(ipa, false); @@ -222,7 +231,7 @@ void ipa_uc_power(struct ipa *ipa) static void send_uc_command(struct ipa *ipa, u32 command, u32 command_param) { struct ipa_uc_mem_area *shared = ipa_uc_shared(ipa); - const struct ipa_reg *reg; + const struct reg *reg; u32 val; /* Fill in the command data */ @@ -234,9 +243,9 @@ static void send_uc_command(struct ipa *ipa, u32 command, u32 command_param) /* Use an interrupt to tell the microcontroller the command is ready */ reg = ipa_reg(ipa, IPA_IRQ_UC); - val = ipa_reg_bit(reg, UC_INTR); + val = reg_bit(reg, UC_INTR); - iowrite32(val, ipa->reg_virt + ipa_reg_offset(reg)); + iowrite32(val, ipa->reg_virt + reg_offset(reg)); } /* Tell the microcontroller the AP is shutting down */ diff --git a/drivers/net/ipa/ipa_uc.h b/drivers/net/ipa/ipa_uc.h index 8514096e6f36..85aa0df818c2 100644 --- a/drivers/net/ipa/ipa_uc.h +++ b/drivers/net/ipa/ipa_uc.h @@ -7,6 +7,14 @@ #define _IPA_UC_H_ struct ipa; +enum ipa_irq_id; + +/** + * ipa_uc_interrupt_handler() - Handler for microcontroller IPA interrupts + * @ipa: IPA pointer + * @irq_id: IPA interrupt ID + */ +void ipa_uc_interrupt_handler(struct ipa *ipa, enum ipa_irq_id irq_id); /** * ipa_uc_config() - Configure the IPA microcontroller subsystem diff --git a/drivers/net/ipa/ipa_version.h b/drivers/net/ipa/ipa_version.h index 7870e0cc3d7c..06e75b8ece7e 100644 --- a/drivers/net/ipa/ipa_version.h +++ b/drivers/net/ipa/ipa_version.h @@ -9,7 +9,7 @@ /** * enum ipa_version * @IPA_VERSION_3_0: IPA version 3.0/GSI version 1.0 - * @IPA_VERSION_3_1: IPA version 3.1/GSI version 1.1 + * @IPA_VERSION_3_1: IPA version 3.1/GSI version 1.0 * @IPA_VERSION_3_5: IPA version 3.5/GSI version 1.2 * @IPA_VERSION_3_5_1: IPA version 3.5.1/GSI version 1.3 * @IPA_VERSION_4_0: IPA version 4.0/GSI version 2.0 @@ -19,6 +19,9 @@ * @IPA_VERSION_4_7: IPA version 4.7/GSI version 2.7 * @IPA_VERSION_4_9: IPA version 4.9/GSI version 2.9 * @IPA_VERSION_4_11: IPA version 4.11/GSI version 2.11 (2.1.1) + * @IPA_VERSION_5_0: IPA version 5.0/GSI version 3.0 + * @IPA_VERSION_5_1: IPA version 5.1/GSI version 3.0 + * @IPA_VERSION_5_5: IPA version 5.5/GSI version 5.5 * @IPA_VERSION_COUNT: Number of defined IPA versions * * Defines the version of IPA (and GSI) hardware present on the platform. @@ -36,6 +39,9 @@ enum ipa_version { IPA_VERSION_4_7, IPA_VERSION_4_9, IPA_VERSION_4_11, + IPA_VERSION_5_0, + IPA_VERSION_5_1, + IPA_VERSION_5_5, IPA_VERSION_COUNT, /* Last; not a version */ }; @@ -46,8 +52,10 @@ static inline bool ipa_version_supported(enum ipa_version version) case IPA_VERSION_3_5_1: case IPA_VERSION_4_2: case IPA_VERSION_4_5: + case IPA_VERSION_4_7: case IPA_VERSION_4_9: case IPA_VERSION_4_11: + case IPA_VERSION_5_0: return true; default: return false; diff --git a/drivers/net/ipa/reg.h b/drivers/net/ipa/reg.h new file mode 100644 index 000000000000..57b457f39b6e --- /dev/null +++ b/drivers/net/ipa/reg.h @@ -0,0 +1,133 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +/* *Copyright (C) 2022-2023 Linaro Ltd. */ + +#ifndef _REG_H_ +#define _REG_H_ + +#include <linux/types.h> +#include <linux/bits.h> + +/** + * struct reg - A register descriptor + * @offset: Register offset relative to base of register memory + * @stride: Distance between two instances, if parameterized + * @fcount: Number of entries in the @fmask array + * @fmask: Array of mask values defining position and width of fields + * @name: Upper-case name of the register + */ +struct reg { + u32 offset; + u32 stride; + u32 fcount; + const u32 *fmask; /* BIT(nr) or GENMASK(h, l) */ + const char *name; +}; + +/* Helper macro for defining "simple" (non-parameterized) registers */ +#define REG(__NAME, __reg_id, __offset) \ + REG_STRIDE(__NAME, __reg_id, __offset, 0) + +/* Helper macro for defining parameterized registers, specifying stride */ +#define REG_STRIDE(__NAME, __reg_id, __offset, __stride) \ + static const struct reg reg_ ## __reg_id = { \ + .name = #__NAME, \ + .offset = __offset, \ + .stride = __stride, \ + } + +#define REG_FIELDS(__NAME, __name, __offset) \ + REG_STRIDE_FIELDS(__NAME, __name, __offset, 0) + +#define REG_STRIDE_FIELDS(__NAME, __name, __offset, __stride) \ + static const struct reg reg_ ## __name = { \ + .name = #__NAME, \ + .offset = __offset, \ + .stride = __stride, \ + .fcount = ARRAY_SIZE(reg_ ## __name ## _fmask), \ + .fmask = reg_ ## __name ## _fmask, \ + } + +/** + * struct regs - Description of registers supported by hardware + * @reg_count: Number of registers in the @reg[] array + * @reg: Array of register descriptors + */ +struct regs { + u32 reg_count; + const struct reg **reg; +}; + +static inline const struct reg *reg(const struct regs *regs, u32 reg_id) +{ + if (WARN(reg_id >= regs->reg_count, + "reg out of range (%u > %u)\n", reg_id, regs->reg_count - 1)) + return NULL; + + return regs->reg[reg_id]; +} + +/* Return the field mask for a field in a register, or 0 on error */ +static inline u32 reg_fmask(const struct reg *reg, u32 field_id) +{ + if (!reg || WARN_ON(field_id >= reg->fcount)) + return 0; + + return reg->fmask[field_id]; +} + +/* Return the mask for a single-bit field in a register, or 0 on error */ +static inline u32 reg_bit(const struct reg *reg, u32 field_id) +{ + u32 fmask = reg_fmask(reg, field_id); + + if (WARN_ON(!is_power_of_2(fmask))) + return 0; + + return fmask; +} + +/* Return the maximum value representable by the given field; always 2^n - 1 */ +static inline u32 reg_field_max(const struct reg *reg, u32 field_id) +{ + u32 fmask = reg_fmask(reg, field_id); + + return fmask ? fmask >> __ffs(fmask) : 0; +} + +/* Encode a value into the given field of a register */ +static inline u32 reg_encode(const struct reg *reg, u32 field_id, u32 val) +{ + u32 fmask = reg_fmask(reg, field_id); + + if (!fmask) + return 0; + + val <<= __ffs(fmask); + if (WARN_ON(val & ~fmask)) + return 0; + + return val; +} + +/* Given a register value, decode (extract) the value in the given field */ +static inline u32 reg_decode(const struct reg *reg, u32 field_id, u32 val) +{ + u32 fmask = reg_fmask(reg, field_id); + + return fmask ? (val & fmask) >> __ffs(fmask) : 0; +} + +/* Returns 0 for NULL reg; warning should have already been issued */ +static inline u32 reg_offset(const struct reg *reg) +{ + return reg ? reg->offset : 0; +} + +/* Returns 0 for NULL reg; warning should have already been issued */ +static inline u32 reg_n_offset(const struct reg *reg, u32 n) +{ + return reg ? reg->offset + n * reg->stride : 0; +} + +#endif /* _REG_H_ */ diff --git a/drivers/net/ipa/reg/gsi_reg-v3.1.c b/drivers/net/ipa/reg/gsi_reg-v3.1.c new file mode 100644 index 000000000000..e036805a7882 --- /dev/null +++ b/drivers/net/ipa/reg/gsi_reg-v3.1.c @@ -0,0 +1,291 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* Copyright (C) 2023 Linaro Ltd. */ + +#include <linux/types.h> + +#include "../gsi.h" +#include "../reg.h" +#include "../gsi_reg.h" + +REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk, + 0x0000c020 + 0x1000 * GSI_EE_AP); + +REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk, + 0x0000c024 + 0x1000 * GSI_EE_AP); + +static const u32 reg_ch_c_cntxt_0_fmask[] = { + [CHTYPE_PROTOCOL] = GENMASK(2, 0), + [CHTYPE_DIR] = BIT(3), + [CH_EE] = GENMASK(7, 4), + [CHID] = GENMASK(12, 8), + /* Bit 13 reserved */ + [ERINDEX] = GENMASK(18, 14), + /* Bit 19 reserved */ + [CHSTATE] = GENMASK(23, 20), + [ELEMENT_SIZE] = GENMASK(31, 24), +}; + +REG_STRIDE_FIELDS(CH_C_CNTXT_0, ch_c_cntxt_0, + 0x0001c000 + 0x4000 * GSI_EE_AP, 0x80); + +static const u32 reg_ch_c_cntxt_1_fmask[] = { + [CH_R_LENGTH] = GENMASK(15, 0), + /* Bits 16-31 reserved */ +}; + +REG_STRIDE_FIELDS(CH_C_CNTXT_1, ch_c_cntxt_1, + 0x0001c004 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x0001c008 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0001c00c + 0x4000 * GSI_EE_AP, 0x80); + +static const u32 reg_ch_c_qos_fmask[] = { + [WRR_WEIGHT] = GENMASK(3, 0), + /* Bits 4-7 reserved */ + [MAX_PREFETCH] = BIT(8), + [USE_DB_ENG] = BIT(9), + /* Bits 10-31 reserved */ +}; + +REG_STRIDE_FIELDS(CH_C_QOS, ch_c_qos, 0x0001c05c + 0x4000 * GSI_EE_AP, 0x80); + +static const u32 reg_error_log_fmask[] = { + [ERR_ARG3] = GENMASK(3, 0), + [ERR_ARG2] = GENMASK(7, 4), + [ERR_ARG1] = GENMASK(11, 8), + [ERR_CODE] = GENMASK(15, 12), + /* Bits 16-18 reserved */ + [ERR_VIRT_IDX] = GENMASK(23, 19), + [ERR_TYPE] = GENMASK(27, 24), + [ERR_EE] = GENMASK(31, 28), +}; + +REG_STRIDE(CH_C_SCRATCH_0, ch_c_scratch_0, + 0x0001c060 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(CH_C_SCRATCH_1, ch_c_scratch_1, + 0x0001c064 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(CH_C_SCRATCH_2, ch_c_scratch_2, + 0x0001c068 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(CH_C_SCRATCH_3, ch_c_scratch_3, + 0x0001c06c + 0x4000 * GSI_EE_AP, 0x80); + +static const u32 reg_ev_ch_e_cntxt_0_fmask[] = { + [EV_CHTYPE] = GENMASK(3, 0), + [EV_EE] = GENMASK(7, 4), + [EV_EVCHID] = GENMASK(15, 8), + [EV_INTYPE] = BIT(16), + /* Bits 17-19 reserved */ + [EV_CHSTATE] = GENMASK(23, 20), + [EV_ELEMENT_SIZE] = GENMASK(31, 24), +}; + +REG_STRIDE_FIELDS(EV_CH_E_CNTXT_0, ev_ch_e_cntxt_0, + 0x0001d000 + 0x4000 * GSI_EE_AP, 0x80); + +static const u32 reg_ev_ch_e_cntxt_1_fmask[] = { + [R_LENGTH] = GENMASK(15, 0), +}; + +REG_STRIDE_FIELDS(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1, + 0x0001d004 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_CNTXT_2, ev_ch_e_cntxt_2, + 0x0001d008 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_CNTXT_3, ev_ch_e_cntxt_3, + 0x0001d00c + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_CNTXT_4, ev_ch_e_cntxt_4, + 0x0001d010 + 0x4000 * GSI_EE_AP, 0x80); + +static const u32 reg_ev_ch_e_cntxt_8_fmask[] = { + [EV_MODT] = GENMASK(15, 0), + [EV_MODC] = GENMASK(23, 16), + [EV_MOD_CNT] = GENMASK(31, 24), +}; + +REG_STRIDE_FIELDS(EV_CH_E_CNTXT_8, ev_ch_e_cntxt_8, + 0x0001d020 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_CNTXT_9, ev_ch_e_cntxt_9, + 0x0001d024 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_CNTXT_10, ev_ch_e_cntxt_10, + 0x0001d028 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_CNTXT_11, ev_ch_e_cntxt_11, + 0x0001d02c + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_CNTXT_12, ev_ch_e_cntxt_12, + 0x0001d030 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_CNTXT_13, ev_ch_e_cntxt_13, + 0x0001d034 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_SCRATCH_0, ev_ch_e_scratch_0, + 0x0001d048 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_SCRATCH_1, ev_ch_e_scratch_1, + 0x0001d04c + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(CH_C_DOORBELL_0, ch_c_doorbell_0, + 0x0001e000 + 0x4000 * GSI_EE_AP, 0x08); + +REG_STRIDE(EV_CH_E_DOORBELL_0, ev_ch_e_doorbell_0, + 0x0001e100 + 0x4000 * GSI_EE_AP, 0x08); + +static const u32 reg_gsi_status_fmask[] = { + [ENABLED] = BIT(0), + /* Bits 1-31 reserved */ +}; + +REG_FIELDS(GSI_STATUS, gsi_status, 0x0001f000 + 0x4000 * GSI_EE_AP); + +static const u32 reg_ch_cmd_fmask[] = { + [CH_CHID] = GENMASK(7, 0), + /* Bits 8-23 reserved */ + [CH_OPCODE] = GENMASK(31, 24), +}; + +REG_FIELDS(CH_CMD, ch_cmd, 0x0001f008 + 0x4000 * GSI_EE_AP); + +static const u32 reg_ev_ch_cmd_fmask[] = { + [EV_CHID] = GENMASK(7, 0), + /* Bits 8-23 reserved */ + [EV_OPCODE] = GENMASK(31, 24), +}; + +REG_FIELDS(EV_CH_CMD, ev_ch_cmd, 0x0001f010 + 0x4000 * GSI_EE_AP); + +static const u32 reg_generic_cmd_fmask[] = { + [GENERIC_OPCODE] = GENMASK(4, 0), + [GENERIC_CHID] = GENMASK(9, 5), + [GENERIC_EE] = GENMASK(13, 10), + /* Bits 14-31 reserved */ +}; + +REG_FIELDS(GENERIC_CMD, generic_cmd, 0x0001f018 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x0001f080 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x0001f088 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x0001f090 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x0001f094 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk, + 0x0001f098 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk, + 0x0001f09c + 0x4000 * GSI_EE_AP); + +REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr, + 0x0001f0a0 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr, + 0x0001f0a4 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_SRC_IEOB_IRQ, cntxt_src_ieob_irq, 0x0001f0b0 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_SRC_IEOB_IRQ_MSK, cntxt_src_ieob_irq_msk, + 0x0001f0b8 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_SRC_IEOB_IRQ_CLR, cntxt_src_ieob_irq_clr, + 0x0001f0c0 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_GLOB_IRQ_STTS, cntxt_glob_irq_stts, 0x0001f100 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_GLOB_IRQ_EN, cntxt_glob_irq_en, 0x0001f108 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_GLOB_IRQ_CLR, cntxt_glob_irq_clr, 0x0001f110 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_GSI_IRQ_STTS, cntxt_gsi_irq_stts, 0x0001f118 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_GSI_IRQ_EN, cntxt_gsi_irq_en, 0x0001f120 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_GSI_IRQ_CLR, cntxt_gsi_irq_clr, 0x0001f128 + 0x4000 * GSI_EE_AP); + +static const u32 reg_cntxt_intset_fmask[] = { + [INTYPE] = BIT(0) + /* Bits 1-31 reserved */ +}; + +REG_FIELDS(CNTXT_INTSET, cntxt_intset, 0x0001f180 + 0x4000 * GSI_EE_AP); + +REG_FIELDS(ERROR_LOG, error_log, 0x0001f200 + 0x4000 * GSI_EE_AP); + +REG(ERROR_LOG_CLR, error_log_clr, 0x0001f210 + 0x4000 * GSI_EE_AP); + +static const u32 reg_cntxt_scratch_0_fmask[] = { + [INTER_EE_RESULT] = GENMASK(2, 0), + /* Bits 3-4 reserved */ + [GENERIC_EE_RESULT] = GENMASK(7, 5), + /* Bits 8-31 reserved */ +}; + +REG_FIELDS(CNTXT_SCRATCH_0, cntxt_scratch_0, 0x0001f400 + 0x4000 * GSI_EE_AP); + +static const struct reg *reg_array[] = { + [INTER_EE_SRC_CH_IRQ_MSK] = ®_inter_ee_src_ch_irq_msk, + [INTER_EE_SRC_EV_CH_IRQ_MSK] = ®_inter_ee_src_ev_ch_irq_msk, + [CH_C_CNTXT_0] = ®_ch_c_cntxt_0, + [CH_C_CNTXT_1] = ®_ch_c_cntxt_1, + [CH_C_CNTXT_2] = ®_ch_c_cntxt_2, + [CH_C_CNTXT_3] = ®_ch_c_cntxt_3, + [CH_C_QOS] = ®_ch_c_qos, + [CH_C_SCRATCH_0] = ®_ch_c_scratch_0, + [CH_C_SCRATCH_1] = ®_ch_c_scratch_1, + [CH_C_SCRATCH_2] = ®_ch_c_scratch_2, + [CH_C_SCRATCH_3] = ®_ch_c_scratch_3, + [EV_CH_E_CNTXT_0] = ®_ev_ch_e_cntxt_0, + [EV_CH_E_CNTXT_1] = ®_ev_ch_e_cntxt_1, + [EV_CH_E_CNTXT_2] = ®_ev_ch_e_cntxt_2, + [EV_CH_E_CNTXT_3] = ®_ev_ch_e_cntxt_3, + [EV_CH_E_CNTXT_4] = ®_ev_ch_e_cntxt_4, + [EV_CH_E_CNTXT_8] = ®_ev_ch_e_cntxt_8, + [EV_CH_E_CNTXT_9] = ®_ev_ch_e_cntxt_9, + [EV_CH_E_CNTXT_10] = ®_ev_ch_e_cntxt_10, + [EV_CH_E_CNTXT_11] = ®_ev_ch_e_cntxt_11, + [EV_CH_E_CNTXT_12] = ®_ev_ch_e_cntxt_12, + [EV_CH_E_CNTXT_13] = ®_ev_ch_e_cntxt_13, + [EV_CH_E_SCRATCH_0] = ®_ev_ch_e_scratch_0, + [EV_CH_E_SCRATCH_1] = ®_ev_ch_e_scratch_1, + [CH_C_DOORBELL_0] = ®_ch_c_doorbell_0, + [EV_CH_E_DOORBELL_0] = ®_ev_ch_e_doorbell_0, + [GSI_STATUS] = ®_gsi_status, + [CH_CMD] = ®_ch_cmd, + [EV_CH_CMD] = ®_ev_ch_cmd, + [GENERIC_CMD] = ®_generic_cmd, + [CNTXT_TYPE_IRQ] = ®_cntxt_type_irq, + [CNTXT_TYPE_IRQ_MSK] = ®_cntxt_type_irq_msk, + [CNTXT_SRC_CH_IRQ] = ®_cntxt_src_ch_irq, + [CNTXT_SRC_EV_CH_IRQ] = ®_cntxt_src_ev_ch_irq, + [CNTXT_SRC_CH_IRQ_MSK] = ®_cntxt_src_ch_irq_msk, + [CNTXT_SRC_EV_CH_IRQ_MSK] = ®_cntxt_src_ev_ch_irq_msk, + [CNTXT_SRC_CH_IRQ_CLR] = ®_cntxt_src_ch_irq_clr, + [CNTXT_SRC_EV_CH_IRQ_CLR] = ®_cntxt_src_ev_ch_irq_clr, + [CNTXT_SRC_IEOB_IRQ] = ®_cntxt_src_ieob_irq, + [CNTXT_SRC_IEOB_IRQ_MSK] = ®_cntxt_src_ieob_irq_msk, + [CNTXT_SRC_IEOB_IRQ_CLR] = ®_cntxt_src_ieob_irq_clr, + [CNTXT_GLOB_IRQ_STTS] = ®_cntxt_glob_irq_stts, + [CNTXT_GLOB_IRQ_EN] = ®_cntxt_glob_irq_en, + [CNTXT_GLOB_IRQ_CLR] = ®_cntxt_glob_irq_clr, + [CNTXT_GSI_IRQ_STTS] = ®_cntxt_gsi_irq_stts, + [CNTXT_GSI_IRQ_EN] = ®_cntxt_gsi_irq_en, + [CNTXT_GSI_IRQ_CLR] = ®_cntxt_gsi_irq_clr, + [CNTXT_INTSET] = ®_cntxt_intset, + [ERROR_LOG] = ®_error_log, + [ERROR_LOG_CLR] = ®_error_log_clr, + [CNTXT_SCRATCH_0] = ®_cntxt_scratch_0, +}; + +const struct regs gsi_regs_v3_1 = { + .reg_count = ARRAY_SIZE(reg_array), + .reg = reg_array, +}; diff --git a/drivers/net/ipa/reg/gsi_reg-v3.5.1.c b/drivers/net/ipa/reg/gsi_reg-v3.5.1.c new file mode 100644 index 000000000000..8c3ab3a5288e --- /dev/null +++ b/drivers/net/ipa/reg/gsi_reg-v3.5.1.c @@ -0,0 +1,303 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* Copyright (C) 2023 Linaro Ltd. */ + +#include <linux/types.h> + +#include "../gsi.h" +#include "../reg.h" +#include "../gsi_reg.h" + +REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk, + 0x0000c020 + 0x1000 * GSI_EE_AP); + +REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk, + 0x0000c024 + 0x1000 * GSI_EE_AP); + +static const u32 reg_ch_c_cntxt_0_fmask[] = { + [CHTYPE_PROTOCOL] = GENMASK(2, 0), + [CHTYPE_DIR] = BIT(3), + [CH_EE] = GENMASK(7, 4), + [CHID] = GENMASK(12, 8), + /* Bit 13 reserved */ + [ERINDEX] = GENMASK(18, 14), + /* Bit 19 reserved */ + [CHSTATE] = GENMASK(23, 20), + [ELEMENT_SIZE] = GENMASK(31, 24), +}; + +REG_STRIDE_FIELDS(CH_C_CNTXT_0, ch_c_cntxt_0, + 0x0001c000 + 0x4000 * GSI_EE_AP, 0x80); + +static const u32 reg_ch_c_cntxt_1_fmask[] = { + [CH_R_LENGTH] = GENMASK(15, 0), + /* Bits 16-31 reserved */ +}; + +REG_STRIDE_FIELDS(CH_C_CNTXT_1, ch_c_cntxt_1, + 0x0001c004 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x0001c008 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0001c00c + 0x4000 * GSI_EE_AP, 0x80); + +static const u32 reg_ch_c_qos_fmask[] = { + [WRR_WEIGHT] = GENMASK(3, 0), + /* Bits 4-7 reserved */ + [MAX_PREFETCH] = BIT(8), + [USE_DB_ENG] = BIT(9), + /* Bits 10-31 reserved */ +}; + +REG_STRIDE_FIELDS(CH_C_QOS, ch_c_qos, 0x0001c05c + 0x4000 * GSI_EE_AP, 0x80); + +static const u32 reg_error_log_fmask[] = { + [ERR_ARG3] = GENMASK(3, 0), + [ERR_ARG2] = GENMASK(7, 4), + [ERR_ARG1] = GENMASK(11, 8), + [ERR_CODE] = GENMASK(15, 12), + /* Bits 16-18 reserved */ + [ERR_VIRT_IDX] = GENMASK(23, 19), + [ERR_TYPE] = GENMASK(27, 24), + [ERR_EE] = GENMASK(31, 28), +}; + +REG_STRIDE(CH_C_SCRATCH_0, ch_c_scratch_0, + 0x0001c060 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(CH_C_SCRATCH_1, ch_c_scratch_1, + 0x0001c064 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(CH_C_SCRATCH_2, ch_c_scratch_2, + 0x0001c068 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(CH_C_SCRATCH_3, ch_c_scratch_3, + 0x0001c06c + 0x4000 * GSI_EE_AP, 0x80); + +static const u32 reg_ev_ch_e_cntxt_0_fmask[] = { + [EV_CHTYPE] = GENMASK(3, 0), + [EV_EE] = GENMASK(7, 4), + [EV_EVCHID] = GENMASK(15, 8), + [EV_INTYPE] = BIT(16), + /* Bits 17-19 reserved */ + [EV_CHSTATE] = GENMASK(23, 20), + [EV_ELEMENT_SIZE] = GENMASK(31, 24), +}; + +REG_STRIDE_FIELDS(EV_CH_E_CNTXT_0, ev_ch_e_cntxt_0, + 0x0001d000 + 0x4000 * GSI_EE_AP, 0x80); + +static const u32 reg_ev_ch_e_cntxt_1_fmask[] = { + [R_LENGTH] = GENMASK(15, 0), +}; + +REG_STRIDE_FIELDS(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1, + 0x0001d004 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_CNTXT_2, ev_ch_e_cntxt_2, + 0x0001d008 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_CNTXT_3, ev_ch_e_cntxt_3, + 0x0001d00c + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_CNTXT_4, ev_ch_e_cntxt_4, + 0x0001d010 + 0x4000 * GSI_EE_AP, 0x80); + +static const u32 reg_ev_ch_e_cntxt_8_fmask[] = { + [EV_MODT] = GENMASK(15, 0), + [EV_MODC] = GENMASK(23, 16), + [EV_MOD_CNT] = GENMASK(31, 24), +}; + +REG_STRIDE_FIELDS(EV_CH_E_CNTXT_8, ev_ch_e_cntxt_8, + 0x0001d020 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_CNTXT_9, ev_ch_e_cntxt_9, + 0x0001d024 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_CNTXT_10, ev_ch_e_cntxt_10, + 0x0001d028 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_CNTXT_11, ev_ch_e_cntxt_11, + 0x0001d02c + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_CNTXT_12, ev_ch_e_cntxt_12, + 0x0001d030 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_CNTXT_13, ev_ch_e_cntxt_13, + 0x0001d034 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_SCRATCH_0, ev_ch_e_scratch_0, + 0x0001d048 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_SCRATCH_1, ev_ch_e_scratch_1, + 0x0001d04c + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(CH_C_DOORBELL_0, ch_c_doorbell_0, + 0x0001e000 + 0x4000 * GSI_EE_AP, 0x08); + +REG_STRIDE(EV_CH_E_DOORBELL_0, ev_ch_e_doorbell_0, + 0x0001e100 + 0x4000 * GSI_EE_AP, 0x08); + +static const u32 reg_gsi_status_fmask[] = { + [ENABLED] = BIT(0), + /* Bits 1-31 reserved */ +}; + +REG_FIELDS(GSI_STATUS, gsi_status, 0x0001f000 + 0x4000 * GSI_EE_AP); + +static const u32 reg_ch_cmd_fmask[] = { + [CH_CHID] = GENMASK(7, 0), + /* Bits 8-23 reserved */ + [CH_OPCODE] = GENMASK(31, 24), +}; + +REG_FIELDS(CH_CMD, ch_cmd, 0x0001f008 + 0x4000 * GSI_EE_AP); + +static const u32 reg_ev_ch_cmd_fmask[] = { + [EV_CHID] = GENMASK(7, 0), + /* Bits 8-23 reserved */ + [EV_OPCODE] = GENMASK(31, 24), +}; + +REG_FIELDS(EV_CH_CMD, ev_ch_cmd, 0x0001f010 + 0x4000 * GSI_EE_AP); + +static const u32 reg_generic_cmd_fmask[] = { + [GENERIC_OPCODE] = GENMASK(4, 0), + [GENERIC_CHID] = GENMASK(9, 5), + [GENERIC_EE] = GENMASK(13, 10), + /* Bits 14-31 reserved */ +}; + +REG_FIELDS(GENERIC_CMD, generic_cmd, 0x0001f018 + 0x4000 * GSI_EE_AP); + +static const u32 reg_hw_param_2_fmask[] = { + [IRAM_SIZE] = GENMASK(2, 0), + [NUM_CH_PER_EE] = GENMASK(7, 3), + [NUM_EV_PER_EE] = GENMASK(12, 8), + [GSI_CH_PEND_TRANSLATE] = BIT(13), + [GSI_CH_FULL_LOGIC] = BIT(14), + /* Bits 15-31 reserved */ +}; + +REG_FIELDS(HW_PARAM_2, hw_param_2, 0x0001f040 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x0001f080 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x0001f088 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x0001f090 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x0001f094 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk, + 0x0001f098 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk, + 0x0001f09c + 0x4000 * GSI_EE_AP); + +REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr, + 0x0001f0a0 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr, + 0x0001f0a4 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_SRC_IEOB_IRQ, cntxt_src_ieob_irq, 0x0001f0b0 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_SRC_IEOB_IRQ_MSK, cntxt_src_ieob_irq_msk, + 0x0001f0b8 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_SRC_IEOB_IRQ_CLR, cntxt_src_ieob_irq_clr, + 0x0001f0c0 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_GLOB_IRQ_STTS, cntxt_glob_irq_stts, 0x0001f100 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_GLOB_IRQ_EN, cntxt_glob_irq_en, 0x0001f108 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_GLOB_IRQ_CLR, cntxt_glob_irq_clr, 0x0001f110 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_GSI_IRQ_STTS, cntxt_gsi_irq_stts, 0x0001f118 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_GSI_IRQ_EN, cntxt_gsi_irq_en, 0x0001f120 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_GSI_IRQ_CLR, cntxt_gsi_irq_clr, 0x0001f128 + 0x4000 * GSI_EE_AP); + +static const u32 reg_cntxt_intset_fmask[] = { + [INTYPE] = BIT(0) + /* Bits 1-31 reserved */ +}; + +REG_FIELDS(CNTXT_INTSET, cntxt_intset, 0x0001f180 + 0x4000 * GSI_EE_AP); + +REG_FIELDS(ERROR_LOG, error_log, 0x0001f200 + 0x4000 * GSI_EE_AP); + +REG(ERROR_LOG_CLR, error_log_clr, 0x0001f210 + 0x4000 * GSI_EE_AP); + +static const u32 reg_cntxt_scratch_0_fmask[] = { + [INTER_EE_RESULT] = GENMASK(2, 0), + /* Bits 3-4 reserved */ + [GENERIC_EE_RESULT] = GENMASK(7, 5), + /* Bits 8-31 reserved */ +}; + +REG_FIELDS(CNTXT_SCRATCH_0, cntxt_scratch_0, 0x0001f400 + 0x4000 * GSI_EE_AP); + +static const struct reg *reg_array[] = { + [INTER_EE_SRC_CH_IRQ_MSK] = ®_inter_ee_src_ch_irq_msk, + [INTER_EE_SRC_EV_CH_IRQ_MSK] = ®_inter_ee_src_ev_ch_irq_msk, + [CH_C_CNTXT_0] = ®_ch_c_cntxt_0, + [CH_C_CNTXT_1] = ®_ch_c_cntxt_1, + [CH_C_CNTXT_2] = ®_ch_c_cntxt_2, + [CH_C_CNTXT_3] = ®_ch_c_cntxt_3, + [CH_C_QOS] = ®_ch_c_qos, + [CH_C_SCRATCH_0] = ®_ch_c_scratch_0, + [CH_C_SCRATCH_1] = ®_ch_c_scratch_1, + [CH_C_SCRATCH_2] = ®_ch_c_scratch_2, + [CH_C_SCRATCH_3] = ®_ch_c_scratch_3, + [EV_CH_E_CNTXT_0] = ®_ev_ch_e_cntxt_0, + [EV_CH_E_CNTXT_1] = ®_ev_ch_e_cntxt_1, + [EV_CH_E_CNTXT_2] = ®_ev_ch_e_cntxt_2, + [EV_CH_E_CNTXT_3] = ®_ev_ch_e_cntxt_3, + [EV_CH_E_CNTXT_4] = ®_ev_ch_e_cntxt_4, + [EV_CH_E_CNTXT_8] = ®_ev_ch_e_cntxt_8, + [EV_CH_E_CNTXT_9] = ®_ev_ch_e_cntxt_9, + [EV_CH_E_CNTXT_10] = ®_ev_ch_e_cntxt_10, + [EV_CH_E_CNTXT_11] = ®_ev_ch_e_cntxt_11, + [EV_CH_E_CNTXT_12] = ®_ev_ch_e_cntxt_12, + [EV_CH_E_CNTXT_13] = ®_ev_ch_e_cntxt_13, + [EV_CH_E_SCRATCH_0] = ®_ev_ch_e_scratch_0, + [EV_CH_E_SCRATCH_1] = ®_ev_ch_e_scratch_1, + [CH_C_DOORBELL_0] = ®_ch_c_doorbell_0, + [EV_CH_E_DOORBELL_0] = ®_ev_ch_e_doorbell_0, + [GSI_STATUS] = ®_gsi_status, + [CH_CMD] = ®_ch_cmd, + [EV_CH_CMD] = ®_ev_ch_cmd, + [GENERIC_CMD] = ®_generic_cmd, + [HW_PARAM_2] = ®_hw_param_2, + [CNTXT_TYPE_IRQ] = ®_cntxt_type_irq, + [CNTXT_TYPE_IRQ_MSK] = ®_cntxt_type_irq_msk, + [CNTXT_SRC_CH_IRQ] = ®_cntxt_src_ch_irq, + [CNTXT_SRC_EV_CH_IRQ] = ®_cntxt_src_ev_ch_irq, + [CNTXT_SRC_CH_IRQ_MSK] = ®_cntxt_src_ch_irq_msk, + [CNTXT_SRC_EV_CH_IRQ_MSK] = ®_cntxt_src_ev_ch_irq_msk, + [CNTXT_SRC_CH_IRQ_CLR] = ®_cntxt_src_ch_irq_clr, + [CNTXT_SRC_EV_CH_IRQ_CLR] = ®_cntxt_src_ev_ch_irq_clr, + [CNTXT_SRC_IEOB_IRQ] = ®_cntxt_src_ieob_irq, + [CNTXT_SRC_IEOB_IRQ_MSK] = ®_cntxt_src_ieob_irq_msk, + [CNTXT_SRC_IEOB_IRQ_CLR] = ®_cntxt_src_ieob_irq_clr, + [CNTXT_GLOB_IRQ_STTS] = ®_cntxt_glob_irq_stts, + [CNTXT_GLOB_IRQ_EN] = ®_cntxt_glob_irq_en, + [CNTXT_GLOB_IRQ_CLR] = ®_cntxt_glob_irq_clr, + [CNTXT_GSI_IRQ_STTS] = ®_cntxt_gsi_irq_stts, + [CNTXT_GSI_IRQ_EN] = ®_cntxt_gsi_irq_en, + [CNTXT_GSI_IRQ_CLR] = ®_cntxt_gsi_irq_clr, + [CNTXT_INTSET] = ®_cntxt_intset, + [ERROR_LOG] = ®_error_log, + [ERROR_LOG_CLR] = ®_error_log_clr, + [CNTXT_SCRATCH_0] = ®_cntxt_scratch_0, +}; + +const struct regs gsi_regs_v3_5_1 = { + .reg_count = ARRAY_SIZE(reg_array), + .reg = reg_array, +}; diff --git a/drivers/net/ipa/reg/gsi_reg-v4.0.c b/drivers/net/ipa/reg/gsi_reg-v4.0.c new file mode 100644 index 000000000000..7cc7a21d07f9 --- /dev/null +++ b/drivers/net/ipa/reg/gsi_reg-v4.0.c @@ -0,0 +1,308 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* Copyright (C) 2023 Linaro Ltd. */ + +#include <linux/types.h> + +#include "../gsi.h" +#include "../reg.h" +#include "../gsi_reg.h" + +REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk, + 0x0000c020 + 0x1000 * GSI_EE_AP); + +REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk, + 0x0000c024 + 0x1000 * GSI_EE_AP); + +static const u32 reg_ch_c_cntxt_0_fmask[] = { + [CHTYPE_PROTOCOL] = GENMASK(2, 0), + [CHTYPE_DIR] = BIT(3), + [CH_EE] = GENMASK(7, 4), + [CHID] = GENMASK(12, 8), + /* Bit 13 reserved */ + [ERINDEX] = GENMASK(18, 14), + /* Bit 19 reserved */ + [CHSTATE] = GENMASK(23, 20), + [ELEMENT_SIZE] = GENMASK(31, 24), +}; + +REG_STRIDE_FIELDS(CH_C_CNTXT_0, ch_c_cntxt_0, + 0x0001c000 + 0x4000 * GSI_EE_AP, 0x80); + +static const u32 reg_ch_c_cntxt_1_fmask[] = { + [CH_R_LENGTH] = GENMASK(15, 0), + /* Bits 16-31 reserved */ +}; + +REG_STRIDE_FIELDS(CH_C_CNTXT_1, ch_c_cntxt_1, + 0x0001c004 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x0001c008 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0001c00c + 0x4000 * GSI_EE_AP, 0x80); + +static const u32 reg_ch_c_qos_fmask[] = { + [WRR_WEIGHT] = GENMASK(3, 0), + /* Bits 4-7 reserved */ + [MAX_PREFETCH] = BIT(8), + [USE_DB_ENG] = BIT(9), + [USE_ESCAPE_BUF_ONLY] = BIT(10), + /* Bits 11-31 reserved */ +}; + +REG_STRIDE_FIELDS(CH_C_QOS, ch_c_qos, 0x0001c05c + 0x4000 * GSI_EE_AP, 0x80); + +static const u32 reg_error_log_fmask[] = { + [ERR_ARG3] = GENMASK(3, 0), + [ERR_ARG2] = GENMASK(7, 4), + [ERR_ARG1] = GENMASK(11, 8), + [ERR_CODE] = GENMASK(15, 12), + /* Bits 16-18 reserved */ + [ERR_VIRT_IDX] = GENMASK(23, 19), + [ERR_TYPE] = GENMASK(27, 24), + [ERR_EE] = GENMASK(31, 28), +}; + +REG_STRIDE(CH_C_SCRATCH_0, ch_c_scratch_0, + 0x0001c060 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(CH_C_SCRATCH_1, ch_c_scratch_1, + 0x0001c064 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(CH_C_SCRATCH_2, ch_c_scratch_2, + 0x0001c068 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(CH_C_SCRATCH_3, ch_c_scratch_3, + 0x0001c06c + 0x4000 * GSI_EE_AP, 0x80); + +static const u32 reg_ev_ch_e_cntxt_0_fmask[] = { + [EV_CHTYPE] = GENMASK(3, 0), + [EV_EE] = GENMASK(7, 4), + [EV_EVCHID] = GENMASK(15, 8), + [EV_INTYPE] = BIT(16), + /* Bits 17-19 reserved */ + [EV_CHSTATE] = GENMASK(23, 20), + [EV_ELEMENT_SIZE] = GENMASK(31, 24), +}; + +REG_STRIDE_FIELDS(EV_CH_E_CNTXT_0, ev_ch_e_cntxt_0, + 0x0001d000 + 0x4000 * GSI_EE_AP, 0x80); + +static const u32 reg_ev_ch_e_cntxt_1_fmask[] = { + [R_LENGTH] = GENMASK(15, 0), +}; + +REG_STRIDE_FIELDS(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1, + 0x0001d004 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_CNTXT_2, ev_ch_e_cntxt_2, + 0x0001d008 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_CNTXT_3, ev_ch_e_cntxt_3, + 0x0001d00c + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_CNTXT_4, ev_ch_e_cntxt_4, + 0x0001d010 + 0x4000 * GSI_EE_AP, 0x80); + +static const u32 reg_ev_ch_e_cntxt_8_fmask[] = { + [EV_MODT] = GENMASK(15, 0), + [EV_MODC] = GENMASK(23, 16), + [EV_MOD_CNT] = GENMASK(31, 24), +}; + +REG_STRIDE_FIELDS(EV_CH_E_CNTXT_8, ev_ch_e_cntxt_8, + 0x0001d020 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_CNTXT_9, ev_ch_e_cntxt_9, + 0x0001d024 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_CNTXT_10, ev_ch_e_cntxt_10, + 0x0001d028 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_CNTXT_11, ev_ch_e_cntxt_11, + 0x0001d02c + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_CNTXT_12, ev_ch_e_cntxt_12, + 0x0001d030 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_CNTXT_13, ev_ch_e_cntxt_13, + 0x0001d034 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_SCRATCH_0, ev_ch_e_scratch_0, + 0x0001d048 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_SCRATCH_1, ev_ch_e_scratch_1, + 0x0001d04c + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(CH_C_DOORBELL_0, ch_c_doorbell_0, + 0x0001e000 + 0x4000 * GSI_EE_AP, 0x08); + +REG_STRIDE(EV_CH_E_DOORBELL_0, ev_ch_e_doorbell_0, + 0x0001e100 + 0x4000 * GSI_EE_AP, 0x08); + +static const u32 reg_gsi_status_fmask[] = { + [ENABLED] = BIT(0), + /* Bits 1-31 reserved */ +}; + +REG_FIELDS(GSI_STATUS, gsi_status, 0x0001f000 + 0x4000 * GSI_EE_AP); + +static const u32 reg_ch_cmd_fmask[] = { + [CH_CHID] = GENMASK(7, 0), + /* Bits 8-23 reserved */ + [CH_OPCODE] = GENMASK(31, 24), +}; + +REG_FIELDS(CH_CMD, ch_cmd, 0x0001f008 + 0x4000 * GSI_EE_AP); + +static const u32 reg_ev_ch_cmd_fmask[] = { + [EV_CHID] = GENMASK(7, 0), + /* Bits 8-23 reserved */ + [EV_OPCODE] = GENMASK(31, 24), +}; + +REG_FIELDS(EV_CH_CMD, ev_ch_cmd, 0x0001f010 + 0x4000 * GSI_EE_AP); + +static const u32 reg_generic_cmd_fmask[] = { + [GENERIC_OPCODE] = GENMASK(4, 0), + [GENERIC_CHID] = GENMASK(9, 5), + [GENERIC_EE] = GENMASK(13, 10), + /* Bits 14-31 reserved */ +}; + +REG_FIELDS(GENERIC_CMD, generic_cmd, 0x0001f018 + 0x4000 * GSI_EE_AP); + +static const u32 reg_hw_param_2_fmask[] = { + [IRAM_SIZE] = GENMASK(2, 0), + [NUM_CH_PER_EE] = GENMASK(7, 3), + [NUM_EV_PER_EE] = GENMASK(12, 8), + [GSI_CH_PEND_TRANSLATE] = BIT(13), + [GSI_CH_FULL_LOGIC] = BIT(14), + [GSI_USE_SDMA] = BIT(15), + [GSI_SDMA_N_INT] = GENMASK(18, 16), + [GSI_SDMA_MAX_BURST] = GENMASK(26, 19), + [GSI_SDMA_N_IOVEC] = GENMASK(29, 27), + /* Bits 30-31 reserved */ +}; + +REG_FIELDS(HW_PARAM_2, hw_param_2, 0x0001f040 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x0001f080 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x0001f088 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x0001f090 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x0001f094 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk, + 0x0001f098 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk, + 0x0001f09c + 0x4000 * GSI_EE_AP); + +REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr, + 0x0001f0a0 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr, + 0x0001f0a4 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_SRC_IEOB_IRQ, cntxt_src_ieob_irq, 0x0001f0b0 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_SRC_IEOB_IRQ_MSK, cntxt_src_ieob_irq_msk, + 0x0001f0b8 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_SRC_IEOB_IRQ_CLR, cntxt_src_ieob_irq_clr, + 0x0001f0c0 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_GLOB_IRQ_STTS, cntxt_glob_irq_stts, 0x0001f100 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_GLOB_IRQ_EN, cntxt_glob_irq_en, 0x0001f108 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_GLOB_IRQ_CLR, cntxt_glob_irq_clr, 0x0001f110 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_GSI_IRQ_STTS, cntxt_gsi_irq_stts, 0x0001f118 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_GSI_IRQ_EN, cntxt_gsi_irq_en, 0x0001f120 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_GSI_IRQ_CLR, cntxt_gsi_irq_clr, 0x0001f128 + 0x4000 * GSI_EE_AP); + +static const u32 reg_cntxt_intset_fmask[] = { + [INTYPE] = BIT(0) + /* Bits 1-31 reserved */ +}; + +REG_FIELDS(CNTXT_INTSET, cntxt_intset, 0x0001f180 + 0x4000 * GSI_EE_AP); + +REG_FIELDS(ERROR_LOG, error_log, 0x0001f200 + 0x4000 * GSI_EE_AP); + +REG(ERROR_LOG_CLR, error_log_clr, 0x0001f210 + 0x4000 * GSI_EE_AP); + +static const u32 reg_cntxt_scratch_0_fmask[] = { + [INTER_EE_RESULT] = GENMASK(2, 0), + /* Bits 3-4 reserved */ + [GENERIC_EE_RESULT] = GENMASK(7, 5), + /* Bits 8-31 reserved */ +}; + +REG_FIELDS(CNTXT_SCRATCH_0, cntxt_scratch_0, 0x0001f400 + 0x4000 * GSI_EE_AP); + +static const struct reg *reg_array[] = { + [INTER_EE_SRC_CH_IRQ_MSK] = ®_inter_ee_src_ch_irq_msk, + [INTER_EE_SRC_EV_CH_IRQ_MSK] = ®_inter_ee_src_ev_ch_irq_msk, + [CH_C_CNTXT_0] = ®_ch_c_cntxt_0, + [CH_C_CNTXT_1] = ®_ch_c_cntxt_1, + [CH_C_CNTXT_2] = ®_ch_c_cntxt_2, + [CH_C_CNTXT_3] = ®_ch_c_cntxt_3, + [CH_C_QOS] = ®_ch_c_qos, + [CH_C_SCRATCH_0] = ®_ch_c_scratch_0, + [CH_C_SCRATCH_1] = ®_ch_c_scratch_1, + [CH_C_SCRATCH_2] = ®_ch_c_scratch_2, + [CH_C_SCRATCH_3] = ®_ch_c_scratch_3, + [EV_CH_E_CNTXT_0] = ®_ev_ch_e_cntxt_0, + [EV_CH_E_CNTXT_1] = ®_ev_ch_e_cntxt_1, + [EV_CH_E_CNTXT_2] = ®_ev_ch_e_cntxt_2, + [EV_CH_E_CNTXT_3] = ®_ev_ch_e_cntxt_3, + [EV_CH_E_CNTXT_4] = ®_ev_ch_e_cntxt_4, + [EV_CH_E_CNTXT_8] = ®_ev_ch_e_cntxt_8, + [EV_CH_E_CNTXT_9] = ®_ev_ch_e_cntxt_9, + [EV_CH_E_CNTXT_10] = ®_ev_ch_e_cntxt_10, + [EV_CH_E_CNTXT_11] = ®_ev_ch_e_cntxt_11, + [EV_CH_E_CNTXT_12] = ®_ev_ch_e_cntxt_12, + [EV_CH_E_CNTXT_13] = ®_ev_ch_e_cntxt_13, + [EV_CH_E_SCRATCH_0] = ®_ev_ch_e_scratch_0, + [EV_CH_E_SCRATCH_1] = ®_ev_ch_e_scratch_1, + [CH_C_DOORBELL_0] = ®_ch_c_doorbell_0, + [EV_CH_E_DOORBELL_0] = ®_ev_ch_e_doorbell_0, + [GSI_STATUS] = ®_gsi_status, + [CH_CMD] = ®_ch_cmd, + [EV_CH_CMD] = ®_ev_ch_cmd, + [GENERIC_CMD] = ®_generic_cmd, + [HW_PARAM_2] = ®_hw_param_2, + [CNTXT_TYPE_IRQ] = ®_cntxt_type_irq, + [CNTXT_TYPE_IRQ_MSK] = ®_cntxt_type_irq_msk, + [CNTXT_SRC_CH_IRQ] = ®_cntxt_src_ch_irq, + [CNTXT_SRC_EV_CH_IRQ] = ®_cntxt_src_ev_ch_irq, + [CNTXT_SRC_CH_IRQ_MSK] = ®_cntxt_src_ch_irq_msk, + [CNTXT_SRC_EV_CH_IRQ_MSK] = ®_cntxt_src_ev_ch_irq_msk, + [CNTXT_SRC_CH_IRQ_CLR] = ®_cntxt_src_ch_irq_clr, + [CNTXT_SRC_EV_CH_IRQ_CLR] = ®_cntxt_src_ev_ch_irq_clr, + [CNTXT_SRC_IEOB_IRQ] = ®_cntxt_src_ieob_irq, + [CNTXT_SRC_IEOB_IRQ_MSK] = ®_cntxt_src_ieob_irq_msk, + [CNTXT_SRC_IEOB_IRQ_CLR] = ®_cntxt_src_ieob_irq_clr, + [CNTXT_GLOB_IRQ_STTS] = ®_cntxt_glob_irq_stts, + [CNTXT_GLOB_IRQ_EN] = ®_cntxt_glob_irq_en, + [CNTXT_GLOB_IRQ_CLR] = ®_cntxt_glob_irq_clr, + [CNTXT_GSI_IRQ_STTS] = ®_cntxt_gsi_irq_stts, + [CNTXT_GSI_IRQ_EN] = ®_cntxt_gsi_irq_en, + [CNTXT_GSI_IRQ_CLR] = ®_cntxt_gsi_irq_clr, + [CNTXT_INTSET] = ®_cntxt_intset, + [ERROR_LOG] = ®_error_log, + [ERROR_LOG_CLR] = ®_error_log_clr, + [CNTXT_SCRATCH_0] = ®_cntxt_scratch_0, +}; + +const struct regs gsi_regs_v4_0 = { + .reg_count = ARRAY_SIZE(reg_array), + .reg = reg_array, +}; diff --git a/drivers/net/ipa/reg/gsi_reg-v4.11.c b/drivers/net/ipa/reg/gsi_reg-v4.11.c new file mode 100644 index 000000000000..01696519032f --- /dev/null +++ b/drivers/net/ipa/reg/gsi_reg-v4.11.c @@ -0,0 +1,313 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* Copyright (C) 2023 Linaro Ltd. */ + +#include <linux/types.h> + +#include "../gsi.h" +#include "../reg.h" +#include "../gsi_reg.h" + +REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk, + 0x0000c020 + 0x1000 * GSI_EE_AP); + +REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk, + 0x0000c024 + 0x1000 * GSI_EE_AP); + +static const u32 reg_ch_c_cntxt_0_fmask[] = { + [CHTYPE_PROTOCOL] = GENMASK(2, 0), + [CHTYPE_DIR] = BIT(3), + [CH_EE] = GENMASK(7, 4), + [CHID] = GENMASK(12, 8), + [CHTYPE_PROTOCOL_MSB] = BIT(13), + [ERINDEX] = GENMASK(18, 14), + /* Bit 19 reserved */ + [CHSTATE] = GENMASK(23, 20), + [ELEMENT_SIZE] = GENMASK(31, 24), +}; + +REG_STRIDE_FIELDS(CH_C_CNTXT_0, ch_c_cntxt_0, + 0x0000f000 + 0x4000 * GSI_EE_AP, 0x80); + +static const u32 reg_ch_c_cntxt_1_fmask[] = { + [CH_R_LENGTH] = GENMASK(19, 0), + /* Bits 20-31 reserved */ +}; + +REG_STRIDE_FIELDS(CH_C_CNTXT_1, ch_c_cntxt_1, + 0x0000f004 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x0000f008 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0000f00c + 0x4000 * GSI_EE_AP, 0x80); + +static const u32 reg_ch_c_qos_fmask[] = { + [WRR_WEIGHT] = GENMASK(3, 0), + /* Bits 4-7 reserved */ + [MAX_PREFETCH] = BIT(8), + [USE_DB_ENG] = BIT(9), + [PREFETCH_MODE] = GENMASK(13, 10), + /* Bits 14-15 reserved */ + [EMPTY_LVL_THRSHOLD] = GENMASK(23, 16), + [DB_IN_BYTES] = BIT(24), + /* Bits 25-31 reserved */ +}; + +REG_STRIDE_FIELDS(CH_C_QOS, ch_c_qos, 0x0000f05c + 0x4000 * GSI_EE_AP, 0x80); + +static const u32 reg_error_log_fmask[] = { + [ERR_ARG3] = GENMASK(3, 0), + [ERR_ARG2] = GENMASK(7, 4), + [ERR_ARG1] = GENMASK(11, 8), + [ERR_CODE] = GENMASK(15, 12), + /* Bits 16-18 reserved */ + [ERR_VIRT_IDX] = GENMASK(23, 19), + [ERR_TYPE] = GENMASK(27, 24), + [ERR_EE] = GENMASK(31, 28), +}; + +REG_STRIDE(CH_C_SCRATCH_0, ch_c_scratch_0, + 0x0000f060 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(CH_C_SCRATCH_1, ch_c_scratch_1, + 0x0000f064 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(CH_C_SCRATCH_2, ch_c_scratch_2, + 0x0000f068 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(CH_C_SCRATCH_3, ch_c_scratch_3, + 0x0000f06c + 0x4000 * GSI_EE_AP, 0x80); + +static const u32 reg_ev_ch_e_cntxt_0_fmask[] = { + [EV_CHTYPE] = GENMASK(3, 0), + [EV_EE] = GENMASK(7, 4), + [EV_EVCHID] = GENMASK(15, 8), + [EV_INTYPE] = BIT(16), + /* Bits 17-19 reserved */ + [EV_CHSTATE] = GENMASK(23, 20), + [EV_ELEMENT_SIZE] = GENMASK(31, 24), +}; + +REG_STRIDE_FIELDS(EV_CH_E_CNTXT_0, ev_ch_e_cntxt_0, + 0x00010000 + 0x4000 * GSI_EE_AP, 0x80); + +static const u32 reg_ev_ch_e_cntxt_1_fmask[] = { + [R_LENGTH] = GENMASK(19, 0), +}; + +REG_STRIDE_FIELDS(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1, + 0x00010004 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_CNTXT_2, ev_ch_e_cntxt_2, + 0x00010008 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_CNTXT_3, ev_ch_e_cntxt_3, + 0x0001000c + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_CNTXT_4, ev_ch_e_cntxt_4, + 0x00010010 + 0x4000 * GSI_EE_AP, 0x80); + +static const u32 reg_ev_ch_e_cntxt_8_fmask[] = { + [EV_MODT] = GENMASK(15, 0), + [EV_MODC] = GENMASK(23, 16), + [EV_MOD_CNT] = GENMASK(31, 24), +}; + +REG_STRIDE_FIELDS(EV_CH_E_CNTXT_8, ev_ch_e_cntxt_8, + 0x00010020 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_CNTXT_9, ev_ch_e_cntxt_9, + 0x00010024 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_CNTXT_10, ev_ch_e_cntxt_10, + 0x00010028 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_CNTXT_11, ev_ch_e_cntxt_11, + 0x0001002c + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_CNTXT_12, ev_ch_e_cntxt_12, + 0x00010030 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_CNTXT_13, ev_ch_e_cntxt_13, + 0x00010034 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_SCRATCH_0, ev_ch_e_scratch_0, + 0x00010048 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_SCRATCH_1, ev_ch_e_scratch_1, + 0x0001004c + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(CH_C_DOORBELL_0, ch_c_doorbell_0, + 0x00011000 + 0x4000 * GSI_EE_AP, 0x08); + +REG_STRIDE(EV_CH_E_DOORBELL_0, ev_ch_e_doorbell_0, + 0x00011100 + 0x4000 * GSI_EE_AP, 0x08); + +static const u32 reg_gsi_status_fmask[] = { + [ENABLED] = BIT(0), + /* Bits 1-31 reserved */ +}; + +REG_FIELDS(GSI_STATUS, gsi_status, 0x00012000 + 0x4000 * GSI_EE_AP); + +static const u32 reg_ch_cmd_fmask[] = { + [CH_CHID] = GENMASK(7, 0), + /* Bits 8-23 reserved */ + [CH_OPCODE] = GENMASK(31, 24), +}; + +REG_FIELDS(CH_CMD, ch_cmd, 0x00012008 + 0x4000 * GSI_EE_AP); + +static const u32 reg_ev_ch_cmd_fmask[] = { + [EV_CHID] = GENMASK(7, 0), + /* Bits 8-23 reserved */ + [EV_OPCODE] = GENMASK(31, 24), +}; + +REG_FIELDS(EV_CH_CMD, ev_ch_cmd, 0x00012010 + 0x4000 * GSI_EE_AP); + +static const u32 reg_generic_cmd_fmask[] = { + [GENERIC_OPCODE] = GENMASK(4, 0), + [GENERIC_CHID] = GENMASK(9, 5), + [GENERIC_EE] = GENMASK(13, 10), + /* Bits 14-23 reserved */ + [GENERIC_PARAMS] = GENMASK(31, 24), +}; + +REG_FIELDS(GENERIC_CMD, generic_cmd, 0x00012018 + 0x4000 * GSI_EE_AP); + +static const u32 reg_hw_param_2_fmask[] = { + [IRAM_SIZE] = GENMASK(2, 0), + [NUM_CH_PER_EE] = GENMASK(7, 3), + [NUM_EV_PER_EE] = GENMASK(12, 8), + [GSI_CH_PEND_TRANSLATE] = BIT(13), + [GSI_CH_FULL_LOGIC] = BIT(14), + [GSI_USE_SDMA] = BIT(15), + [GSI_SDMA_N_INT] = GENMASK(18, 16), + [GSI_SDMA_MAX_BURST] = GENMASK(26, 19), + [GSI_SDMA_N_IOVEC] = GENMASK(29, 27), + [GSI_USE_RD_WR_ENG] = BIT(30), + [GSI_USE_INTER_EE] = BIT(31), +}; + +REG_FIELDS(HW_PARAM_2, hw_param_2, 0x00012040 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x00012080 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x00012088 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x00012090 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x00012094 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk, + 0x00012098 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk, + 0x0001209c + 0x4000 * GSI_EE_AP); + +REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr, + 0x000120a0 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr, + 0x000120a4 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_SRC_IEOB_IRQ, cntxt_src_ieob_irq, 0x000120b0 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_SRC_IEOB_IRQ_MSK, cntxt_src_ieob_irq_msk, + 0x000120b8 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_SRC_IEOB_IRQ_CLR, cntxt_src_ieob_irq_clr, + 0x000120c0 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_GLOB_IRQ_STTS, cntxt_glob_irq_stts, 0x00012100 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_GLOB_IRQ_EN, cntxt_glob_irq_en, 0x00012108 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_GLOB_IRQ_CLR, cntxt_glob_irq_clr, 0x00012110 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_GSI_IRQ_STTS, cntxt_gsi_irq_stts, 0x00012118 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_GSI_IRQ_EN, cntxt_gsi_irq_en, 0x00012120 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_GSI_IRQ_CLR, cntxt_gsi_irq_clr, 0x00012128 + 0x4000 * GSI_EE_AP); + +static const u32 reg_cntxt_intset_fmask[] = { + [INTYPE] = BIT(0) + /* Bits 1-31 reserved */ +}; + +REG_FIELDS(CNTXT_INTSET, cntxt_intset, 0x00012180 + 0x4000 * GSI_EE_AP); + +REG_FIELDS(ERROR_LOG, error_log, 0x00012200 + 0x4000 * GSI_EE_AP); + +REG(ERROR_LOG_CLR, error_log_clr, 0x00012210 + 0x4000 * GSI_EE_AP); + +static const u32 reg_cntxt_scratch_0_fmask[] = { + [INTER_EE_RESULT] = GENMASK(2, 0), + /* Bits 3-4 reserved */ + [GENERIC_EE_RESULT] = GENMASK(7, 5), + /* Bits 8-31 reserved */ +}; + +REG_FIELDS(CNTXT_SCRATCH_0, cntxt_scratch_0, 0x00012400 + 0x4000 * GSI_EE_AP); + +static const struct reg *reg_array[] = { + [INTER_EE_SRC_CH_IRQ_MSK] = ®_inter_ee_src_ch_irq_msk, + [INTER_EE_SRC_EV_CH_IRQ_MSK] = ®_inter_ee_src_ev_ch_irq_msk, + [CH_C_CNTXT_0] = ®_ch_c_cntxt_0, + [CH_C_CNTXT_1] = ®_ch_c_cntxt_1, + [CH_C_CNTXT_2] = ®_ch_c_cntxt_2, + [CH_C_CNTXT_3] = ®_ch_c_cntxt_3, + [CH_C_QOS] = ®_ch_c_qos, + [CH_C_SCRATCH_0] = ®_ch_c_scratch_0, + [CH_C_SCRATCH_1] = ®_ch_c_scratch_1, + [CH_C_SCRATCH_2] = ®_ch_c_scratch_2, + [CH_C_SCRATCH_3] = ®_ch_c_scratch_3, + [EV_CH_E_CNTXT_0] = ®_ev_ch_e_cntxt_0, + [EV_CH_E_CNTXT_1] = ®_ev_ch_e_cntxt_1, + [EV_CH_E_CNTXT_2] = ®_ev_ch_e_cntxt_2, + [EV_CH_E_CNTXT_3] = ®_ev_ch_e_cntxt_3, + [EV_CH_E_CNTXT_4] = ®_ev_ch_e_cntxt_4, + [EV_CH_E_CNTXT_8] = ®_ev_ch_e_cntxt_8, + [EV_CH_E_CNTXT_9] = ®_ev_ch_e_cntxt_9, + [EV_CH_E_CNTXT_10] = ®_ev_ch_e_cntxt_10, + [EV_CH_E_CNTXT_11] = ®_ev_ch_e_cntxt_11, + [EV_CH_E_CNTXT_12] = ®_ev_ch_e_cntxt_12, + [EV_CH_E_CNTXT_13] = ®_ev_ch_e_cntxt_13, + [EV_CH_E_SCRATCH_0] = ®_ev_ch_e_scratch_0, + [EV_CH_E_SCRATCH_1] = ®_ev_ch_e_scratch_1, + [CH_C_DOORBELL_0] = ®_ch_c_doorbell_0, + [EV_CH_E_DOORBELL_0] = ®_ev_ch_e_doorbell_0, + [GSI_STATUS] = ®_gsi_status, + [CH_CMD] = ®_ch_cmd, + [EV_CH_CMD] = ®_ev_ch_cmd, + [GENERIC_CMD] = ®_generic_cmd, + [HW_PARAM_2] = ®_hw_param_2, + [CNTXT_TYPE_IRQ] = ®_cntxt_type_irq, + [CNTXT_TYPE_IRQ_MSK] = ®_cntxt_type_irq_msk, + [CNTXT_SRC_CH_IRQ] = ®_cntxt_src_ch_irq, + [CNTXT_SRC_EV_CH_IRQ] = ®_cntxt_src_ev_ch_irq, + [CNTXT_SRC_CH_IRQ_MSK] = ®_cntxt_src_ch_irq_msk, + [CNTXT_SRC_EV_CH_IRQ_MSK] = ®_cntxt_src_ev_ch_irq_msk, + [CNTXT_SRC_CH_IRQ_CLR] = ®_cntxt_src_ch_irq_clr, + [CNTXT_SRC_EV_CH_IRQ_CLR] = ®_cntxt_src_ev_ch_irq_clr, + [CNTXT_SRC_IEOB_IRQ] = ®_cntxt_src_ieob_irq, + [CNTXT_SRC_IEOB_IRQ_MSK] = ®_cntxt_src_ieob_irq_msk, + [CNTXT_SRC_IEOB_IRQ_CLR] = ®_cntxt_src_ieob_irq_clr, + [CNTXT_GLOB_IRQ_STTS] = ®_cntxt_glob_irq_stts, + [CNTXT_GLOB_IRQ_EN] = ®_cntxt_glob_irq_en, + [CNTXT_GLOB_IRQ_CLR] = ®_cntxt_glob_irq_clr, + [CNTXT_GSI_IRQ_STTS] = ®_cntxt_gsi_irq_stts, + [CNTXT_GSI_IRQ_EN] = ®_cntxt_gsi_irq_en, + [CNTXT_GSI_IRQ_CLR] = ®_cntxt_gsi_irq_clr, + [CNTXT_INTSET] = ®_cntxt_intset, + [ERROR_LOG] = ®_error_log, + [ERROR_LOG_CLR] = ®_error_log_clr, + [CNTXT_SCRATCH_0] = ®_cntxt_scratch_0, +}; + +const struct regs gsi_regs_v4_11 = { + .reg_count = ARRAY_SIZE(reg_array), + .reg = reg_array, +}; diff --git a/drivers/net/ipa/reg/gsi_reg-v4.5.c b/drivers/net/ipa/reg/gsi_reg-v4.5.c new file mode 100644 index 000000000000..648b51b88d4e --- /dev/null +++ b/drivers/net/ipa/reg/gsi_reg-v4.5.c @@ -0,0 +1,311 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* Copyright (C) 2023 Linaro Ltd. */ + +#include <linux/types.h> + +#include "../gsi.h" +#include "../reg.h" +#include "../gsi_reg.h" + +REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk, + 0x0000c020 + 0x1000 * GSI_EE_AP); + +REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk, + 0x0000c024 + 0x1000 * GSI_EE_AP); + +static const u32 reg_ch_c_cntxt_0_fmask[] = { + [CHTYPE_PROTOCOL] = GENMASK(2, 0), + [CHTYPE_DIR] = BIT(3), + [CH_EE] = GENMASK(7, 4), + [CHID] = GENMASK(12, 8), + [CHTYPE_PROTOCOL_MSB] = BIT(13), + [ERINDEX] = GENMASK(18, 14), + /* Bit 19 reserved */ + [CHSTATE] = GENMASK(23, 20), + [ELEMENT_SIZE] = GENMASK(31, 24), +}; + +REG_STRIDE_FIELDS(CH_C_CNTXT_0, ch_c_cntxt_0, + 0x0000f000 + 0x4000 * GSI_EE_AP, 0x80); + +static const u32 reg_ch_c_cntxt_1_fmask[] = { + [CH_R_LENGTH] = GENMASK(15, 0), + /* Bits 16-31 reserved */ +}; + +REG_STRIDE_FIELDS(CH_C_CNTXT_1, ch_c_cntxt_1, + 0x0000f004 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x0000f008 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0000f00c + 0x4000 * GSI_EE_AP, 0x80); + +static const u32 reg_ch_c_qos_fmask[] = { + [WRR_WEIGHT] = GENMASK(3, 0), + /* Bits 4-7 reserved */ + [MAX_PREFETCH] = BIT(8), + [USE_DB_ENG] = BIT(9), + [PREFETCH_MODE] = GENMASK(13, 10), + /* Bits 14-15 reserved */ + [EMPTY_LVL_THRSHOLD] = GENMASK(23, 16), + /* Bits 24-31 reserved */ +}; + +REG_STRIDE_FIELDS(CH_C_QOS, ch_c_qos, 0x0000f05c + 0x4000 * GSI_EE_AP, 0x80); + +static const u32 reg_error_log_fmask[] = { + [ERR_ARG3] = GENMASK(3, 0), + [ERR_ARG2] = GENMASK(7, 4), + [ERR_ARG1] = GENMASK(11, 8), + [ERR_CODE] = GENMASK(15, 12), + /* Bits 16-18 reserved */ + [ERR_VIRT_IDX] = GENMASK(23, 19), + [ERR_TYPE] = GENMASK(27, 24), + [ERR_EE] = GENMASK(31, 28), +}; + +REG_STRIDE(CH_C_SCRATCH_0, ch_c_scratch_0, + 0x0000f060 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(CH_C_SCRATCH_1, ch_c_scratch_1, + 0x0000f064 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(CH_C_SCRATCH_2, ch_c_scratch_2, + 0x0000f068 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(CH_C_SCRATCH_3, ch_c_scratch_3, + 0x0000f06c + 0x4000 * GSI_EE_AP, 0x80); + +static const u32 reg_ev_ch_e_cntxt_0_fmask[] = { + [EV_CHTYPE] = GENMASK(3, 0), + [EV_EE] = GENMASK(7, 4), + [EV_EVCHID] = GENMASK(15, 8), + [EV_INTYPE] = BIT(16), + /* Bits 17-19 reserved */ + [EV_CHSTATE] = GENMASK(23, 20), + [EV_ELEMENT_SIZE] = GENMASK(31, 24), +}; + +REG_STRIDE_FIELDS(EV_CH_E_CNTXT_0, ev_ch_e_cntxt_0, + 0x00010000 + 0x4000 * GSI_EE_AP, 0x80); + +static const u32 reg_ev_ch_e_cntxt_1_fmask[] = { + [R_LENGTH] = GENMASK(15, 0), +}; + +REG_STRIDE_FIELDS(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1, + 0x00010004 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_CNTXT_2, ev_ch_e_cntxt_2, + 0x00010008 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_CNTXT_3, ev_ch_e_cntxt_3, + 0x0001000c + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_CNTXT_4, ev_ch_e_cntxt_4, + 0x00010010 + 0x4000 * GSI_EE_AP, 0x80); + +static const u32 reg_ev_ch_e_cntxt_8_fmask[] = { + [EV_MODT] = GENMASK(15, 0), + [EV_MODC] = GENMASK(23, 16), + [EV_MOD_CNT] = GENMASK(31, 24), +}; + +REG_STRIDE_FIELDS(EV_CH_E_CNTXT_8, ev_ch_e_cntxt_8, + 0x00010020 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_CNTXT_9, ev_ch_e_cntxt_9, + 0x00010024 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_CNTXT_10, ev_ch_e_cntxt_10, + 0x00010028 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_CNTXT_11, ev_ch_e_cntxt_11, + 0x0001002c + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_CNTXT_12, ev_ch_e_cntxt_12, + 0x00010030 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_CNTXT_13, ev_ch_e_cntxt_13, + 0x00010034 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_SCRATCH_0, ev_ch_e_scratch_0, + 0x00010048 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_SCRATCH_1, ev_ch_e_scratch_1, + 0x0001004c + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(CH_C_DOORBELL_0, ch_c_doorbell_0, + 0x0001e000 + 0x4000 * GSI_EE_AP, 0x08); + +REG_STRIDE(EV_CH_E_DOORBELL_0, ev_ch_e_doorbell_0, + 0x0001e100 + 0x4000 * GSI_EE_AP, 0x08); + +static const u32 reg_gsi_status_fmask[] = { + [ENABLED] = BIT(0), + /* Bits 1-31 reserved */ +}; + +REG_FIELDS(GSI_STATUS, gsi_status, 0x0001f000 + 0x4000 * GSI_EE_AP); + +static const u32 reg_ch_cmd_fmask[] = { + [CH_CHID] = GENMASK(7, 0), + /* Bits 8-23 reserved */ + [CH_OPCODE] = GENMASK(31, 24), +}; + +REG_FIELDS(CH_CMD, ch_cmd, 0x0001f008 + 0x4000 * GSI_EE_AP); + +static const u32 reg_ev_ch_cmd_fmask[] = { + [EV_CHID] = GENMASK(7, 0), + /* Bits 8-23 reserved */ + [EV_OPCODE] = GENMASK(31, 24), +}; + +REG_FIELDS(EV_CH_CMD, ev_ch_cmd, 0x0001f010 + 0x4000 * GSI_EE_AP); + +static const u32 reg_generic_cmd_fmask[] = { + [GENERIC_OPCODE] = GENMASK(4, 0), + [GENERIC_CHID] = GENMASK(9, 5), + [GENERIC_EE] = GENMASK(13, 10), + /* Bits 14-31 reserved */ +}; + +REG_FIELDS(GENERIC_CMD, generic_cmd, 0x0001f018 + 0x4000 * GSI_EE_AP); + +static const u32 reg_hw_param_2_fmask[] = { + [IRAM_SIZE] = GENMASK(2, 0), + [NUM_CH_PER_EE] = GENMASK(7, 3), + [NUM_EV_PER_EE] = GENMASK(12, 8), + [GSI_CH_PEND_TRANSLATE] = BIT(13), + [GSI_CH_FULL_LOGIC] = BIT(14), + [GSI_USE_SDMA] = BIT(15), + [GSI_SDMA_N_INT] = GENMASK(18, 16), + [GSI_SDMA_MAX_BURST] = GENMASK(26, 19), + [GSI_SDMA_N_IOVEC] = GENMASK(29, 27), + [GSI_USE_RD_WR_ENG] = BIT(30), + [GSI_USE_INTER_EE] = BIT(31), +}; + +REG_FIELDS(HW_PARAM_2, hw_param_2, 0x0001f040 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x0001f080 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x0001f088 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x0001f090 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x0001f094 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk, + 0x0001f098 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk, + 0x0001f09c + 0x4000 * GSI_EE_AP); + +REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr, + 0x0001f0a0 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr, + 0x0001f0a4 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_SRC_IEOB_IRQ, cntxt_src_ieob_irq, 0x0001f0b0 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_SRC_IEOB_IRQ_MSK, cntxt_src_ieob_irq_msk, + 0x0001f0b8 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_SRC_IEOB_IRQ_CLR, cntxt_src_ieob_irq_clr, + 0x0001f0c0 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_GLOB_IRQ_STTS, cntxt_glob_irq_stts, 0x0001f100 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_GLOB_IRQ_EN, cntxt_glob_irq_en, 0x0001f108 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_GLOB_IRQ_CLR, cntxt_glob_irq_clr, 0x0001f110 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_GSI_IRQ_STTS, cntxt_gsi_irq_stts, 0x0001f118 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_GSI_IRQ_EN, cntxt_gsi_irq_en, 0x0001f120 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_GSI_IRQ_CLR, cntxt_gsi_irq_clr, 0x0001f128 + 0x4000 * GSI_EE_AP); + +static const u32 reg_cntxt_intset_fmask[] = { + [INTYPE] = BIT(0) + /* Bits 1-31 reserved */ +}; + +REG_FIELDS(CNTXT_INTSET, cntxt_intset, 0x0001f180 + 0x4000 * GSI_EE_AP); + +REG_FIELDS(ERROR_LOG, error_log, 0x0001f200 + 0x4000 * GSI_EE_AP); + +REG(ERROR_LOG_CLR, error_log_clr, 0x0001f210 + 0x4000 * GSI_EE_AP); + +static const u32 reg_cntxt_scratch_0_fmask[] = { + [INTER_EE_RESULT] = GENMASK(2, 0), + /* Bits 3-4 reserved */ + [GENERIC_EE_RESULT] = GENMASK(7, 5), + /* Bits 8-31 reserved */ +}; + +REG_FIELDS(CNTXT_SCRATCH_0, cntxt_scratch_0, 0x0001f400 + 0x4000 * GSI_EE_AP); + +static const struct reg *reg_array[] = { + [INTER_EE_SRC_CH_IRQ_MSK] = ®_inter_ee_src_ch_irq_msk, + [INTER_EE_SRC_EV_CH_IRQ_MSK] = ®_inter_ee_src_ev_ch_irq_msk, + [CH_C_CNTXT_0] = ®_ch_c_cntxt_0, + [CH_C_CNTXT_1] = ®_ch_c_cntxt_1, + [CH_C_CNTXT_2] = ®_ch_c_cntxt_2, + [CH_C_CNTXT_3] = ®_ch_c_cntxt_3, + [CH_C_QOS] = ®_ch_c_qos, + [CH_C_SCRATCH_0] = ®_ch_c_scratch_0, + [CH_C_SCRATCH_1] = ®_ch_c_scratch_1, + [CH_C_SCRATCH_2] = ®_ch_c_scratch_2, + [CH_C_SCRATCH_3] = ®_ch_c_scratch_3, + [EV_CH_E_CNTXT_0] = ®_ev_ch_e_cntxt_0, + [EV_CH_E_CNTXT_1] = ®_ev_ch_e_cntxt_1, + [EV_CH_E_CNTXT_2] = ®_ev_ch_e_cntxt_2, + [EV_CH_E_CNTXT_3] = ®_ev_ch_e_cntxt_3, + [EV_CH_E_CNTXT_4] = ®_ev_ch_e_cntxt_4, + [EV_CH_E_CNTXT_8] = ®_ev_ch_e_cntxt_8, + [EV_CH_E_CNTXT_9] = ®_ev_ch_e_cntxt_9, + [EV_CH_E_CNTXT_10] = ®_ev_ch_e_cntxt_10, + [EV_CH_E_CNTXT_11] = ®_ev_ch_e_cntxt_11, + [EV_CH_E_CNTXT_12] = ®_ev_ch_e_cntxt_12, + [EV_CH_E_CNTXT_13] = ®_ev_ch_e_cntxt_13, + [EV_CH_E_SCRATCH_0] = ®_ev_ch_e_scratch_0, + [EV_CH_E_SCRATCH_1] = ®_ev_ch_e_scratch_1, + [CH_C_DOORBELL_0] = ®_ch_c_doorbell_0, + [EV_CH_E_DOORBELL_0] = ®_ev_ch_e_doorbell_0, + [GSI_STATUS] = ®_gsi_status, + [CH_CMD] = ®_ch_cmd, + [EV_CH_CMD] = ®_ev_ch_cmd, + [GENERIC_CMD] = ®_generic_cmd, + [HW_PARAM_2] = ®_hw_param_2, + [CNTXT_TYPE_IRQ] = ®_cntxt_type_irq, + [CNTXT_TYPE_IRQ_MSK] = ®_cntxt_type_irq_msk, + [CNTXT_SRC_CH_IRQ] = ®_cntxt_src_ch_irq, + [CNTXT_SRC_EV_CH_IRQ] = ®_cntxt_src_ev_ch_irq, + [CNTXT_SRC_CH_IRQ_MSK] = ®_cntxt_src_ch_irq_msk, + [CNTXT_SRC_EV_CH_IRQ_MSK] = ®_cntxt_src_ev_ch_irq_msk, + [CNTXT_SRC_CH_IRQ_CLR] = ®_cntxt_src_ch_irq_clr, + [CNTXT_SRC_EV_CH_IRQ_CLR] = ®_cntxt_src_ev_ch_irq_clr, + [CNTXT_SRC_IEOB_IRQ] = ®_cntxt_src_ieob_irq, + [CNTXT_SRC_IEOB_IRQ_MSK] = ®_cntxt_src_ieob_irq_msk, + [CNTXT_SRC_IEOB_IRQ_CLR] = ®_cntxt_src_ieob_irq_clr, + [CNTXT_GLOB_IRQ_STTS] = ®_cntxt_glob_irq_stts, + [CNTXT_GLOB_IRQ_EN] = ®_cntxt_glob_irq_en, + [CNTXT_GLOB_IRQ_CLR] = ®_cntxt_glob_irq_clr, + [CNTXT_GSI_IRQ_STTS] = ®_cntxt_gsi_irq_stts, + [CNTXT_GSI_IRQ_EN] = ®_cntxt_gsi_irq_en, + [CNTXT_GSI_IRQ_CLR] = ®_cntxt_gsi_irq_clr, + [CNTXT_INTSET] = ®_cntxt_intset, + [ERROR_LOG] = ®_error_log, + [ERROR_LOG_CLR] = ®_error_log_clr, + [CNTXT_SCRATCH_0] = ®_cntxt_scratch_0, +}; + +const struct regs gsi_regs_v4_5 = { + .reg_count = ARRAY_SIZE(reg_array), + .reg = reg_array, +}; diff --git a/drivers/net/ipa/reg/gsi_reg-v4.9.c b/drivers/net/ipa/reg/gsi_reg-v4.9.c new file mode 100644 index 000000000000..4bf45d264d6b --- /dev/null +++ b/drivers/net/ipa/reg/gsi_reg-v4.9.c @@ -0,0 +1,312 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* Copyright (C) 2023 Linaro Ltd. */ + +#include <linux/types.h> + +#include "../gsi.h" +#include "../reg.h" +#include "../gsi_reg.h" + +REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk, + 0x0000c020 + 0x1000 * GSI_EE_AP); + +REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk, + 0x0000c024 + 0x1000 * GSI_EE_AP); + +static const u32 reg_ch_c_cntxt_0_fmask[] = { + [CHTYPE_PROTOCOL] = GENMASK(2, 0), + [CHTYPE_DIR] = BIT(3), + [CH_EE] = GENMASK(7, 4), + [CHID] = GENMASK(12, 8), + [CHTYPE_PROTOCOL_MSB] = BIT(13), + [ERINDEX] = GENMASK(18, 14), + /* Bit 19 reserved */ + [CHSTATE] = GENMASK(23, 20), + [ELEMENT_SIZE] = GENMASK(31, 24), +}; + +REG_STRIDE_FIELDS(CH_C_CNTXT_0, ch_c_cntxt_0, + 0x0001c000 + 0x4000 * GSI_EE_AP, 0x80); + +static const u32 reg_ch_c_cntxt_1_fmask[] = { + [CH_R_LENGTH] = GENMASK(19, 0), + /* Bits 20-31 reserved */ +}; + +REG_STRIDE_FIELDS(CH_C_CNTXT_1, ch_c_cntxt_1, + 0x0001c004 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x0001c008 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0001c00c + 0x4000 * GSI_EE_AP, 0x80); + +static const u32 reg_ch_c_qos_fmask[] = { + [WRR_WEIGHT] = GENMASK(3, 0), + /* Bits 4-7 reserved */ + [MAX_PREFETCH] = BIT(8), + [USE_DB_ENG] = BIT(9), + [PREFETCH_MODE] = GENMASK(13, 10), + /* Bits 14-15 reserved */ + [EMPTY_LVL_THRSHOLD] = GENMASK(23, 16), + [DB_IN_BYTES] = BIT(24), + /* Bits 25-31 reserved */ +}; + +REG_STRIDE_FIELDS(CH_C_QOS, ch_c_qos, 0x0001c05c + 0x4000 * GSI_EE_AP, 0x80); + +static const u32 reg_error_log_fmask[] = { + [ERR_ARG3] = GENMASK(3, 0), + [ERR_ARG2] = GENMASK(7, 4), + [ERR_ARG1] = GENMASK(11, 8), + [ERR_CODE] = GENMASK(15, 12), + /* Bits 16-18 reserved */ + [ERR_VIRT_IDX] = GENMASK(23, 19), + [ERR_TYPE] = GENMASK(27, 24), + [ERR_EE] = GENMASK(31, 28), +}; + +REG_STRIDE(CH_C_SCRATCH_0, ch_c_scratch_0, + 0x0001c060 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(CH_C_SCRATCH_1, ch_c_scratch_1, + 0x0001c064 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(CH_C_SCRATCH_2, ch_c_scratch_2, + 0x0001c068 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(CH_C_SCRATCH_3, ch_c_scratch_3, + 0x0001c06c + 0x4000 * GSI_EE_AP, 0x80); + +static const u32 reg_ev_ch_e_cntxt_0_fmask[] = { + [EV_CHTYPE] = GENMASK(3, 0), + [EV_EE] = GENMASK(7, 4), + [EV_EVCHID] = GENMASK(15, 8), + [EV_INTYPE] = BIT(16), + /* Bits 17-19 reserved */ + [EV_CHSTATE] = GENMASK(23, 20), + [EV_ELEMENT_SIZE] = GENMASK(31, 24), +}; + +REG_STRIDE_FIELDS(EV_CH_E_CNTXT_0, ev_ch_e_cntxt_0, + 0x0001d000 + 0x4000 * GSI_EE_AP, 0x80); + +static const u32 reg_ev_ch_e_cntxt_1_fmask[] = { + [R_LENGTH] = GENMASK(15, 0), +}; + +REG_STRIDE_FIELDS(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1, + 0x0001d004 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_CNTXT_2, ev_ch_e_cntxt_2, + 0x0001d008 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_CNTXT_3, ev_ch_e_cntxt_3, + 0x0001d00c + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_CNTXT_4, ev_ch_e_cntxt_4, + 0x0001d010 + 0x4000 * GSI_EE_AP, 0x80); + +static const u32 reg_ev_ch_e_cntxt_8_fmask[] = { + [EV_MODT] = GENMASK(15, 0), + [EV_MODC] = GENMASK(23, 16), + [EV_MOD_CNT] = GENMASK(31, 24), +}; + +REG_STRIDE_FIELDS(EV_CH_E_CNTXT_8, ev_ch_e_cntxt_8, + 0x0001d020 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_CNTXT_9, ev_ch_e_cntxt_9, + 0x0001d024 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_CNTXT_10, ev_ch_e_cntxt_10, + 0x0001d028 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_CNTXT_11, ev_ch_e_cntxt_11, + 0x0001d02c + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_CNTXT_12, ev_ch_e_cntxt_12, + 0x0001d030 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_CNTXT_13, ev_ch_e_cntxt_13, + 0x0001d034 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_SCRATCH_0, ev_ch_e_scratch_0, + 0x0001d048 + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(EV_CH_E_SCRATCH_1, ev_ch_e_scratch_1, + 0x0001d04c + 0x4000 * GSI_EE_AP, 0x80); + +REG_STRIDE(CH_C_DOORBELL_0, ch_c_doorbell_0, + 0x00011000 + 0x4000 * GSI_EE_AP, 0x08); + +REG_STRIDE(EV_CH_E_DOORBELL_0, ev_ch_e_doorbell_0, + 0x00011100 + 0x4000 * GSI_EE_AP, 0x08); + +static const u32 reg_gsi_status_fmask[] = { + [ENABLED] = BIT(0), + /* Bits 1-31 reserved */ +}; + +REG_FIELDS(GSI_STATUS, gsi_status, 0x00012000 + 0x4000 * GSI_EE_AP); + +static const u32 reg_ch_cmd_fmask[] = { + [CH_CHID] = GENMASK(7, 0), + /* Bits 8-23 reserved */ + [CH_OPCODE] = GENMASK(31, 24), +}; + +REG_FIELDS(CH_CMD, ch_cmd, 0x00012008 + 0x4000 * GSI_EE_AP); + +static const u32 reg_ev_ch_cmd_fmask[] = { + [EV_CHID] = GENMASK(7, 0), + /* Bits 8-23 reserved */ + [EV_OPCODE] = GENMASK(31, 24), +}; + +REG_FIELDS(EV_CH_CMD, ev_ch_cmd, 0x00012010 + 0x4000 * GSI_EE_AP); + +static const u32 reg_generic_cmd_fmask[] = { + [GENERIC_OPCODE] = GENMASK(4, 0), + [GENERIC_CHID] = GENMASK(9, 5), + [GENERIC_EE] = GENMASK(13, 10), + /* Bits 14-31 reserved */ +}; + +REG_FIELDS(GENERIC_CMD, generic_cmd, 0x00012018 + 0x4000 * GSI_EE_AP); + +static const u32 reg_hw_param_2_fmask[] = { + [IRAM_SIZE] = GENMASK(2, 0), + [NUM_CH_PER_EE] = GENMASK(7, 3), + [NUM_EV_PER_EE] = GENMASK(12, 8), + [GSI_CH_PEND_TRANSLATE] = BIT(13), + [GSI_CH_FULL_LOGIC] = BIT(14), + [GSI_USE_SDMA] = BIT(15), + [GSI_SDMA_N_INT] = GENMASK(18, 16), + [GSI_SDMA_MAX_BURST] = GENMASK(26, 19), + [GSI_SDMA_N_IOVEC] = GENMASK(29, 27), + [GSI_USE_RD_WR_ENG] = BIT(30), + [GSI_USE_INTER_EE] = BIT(31), +}; + +REG_FIELDS(HW_PARAM_2, hw_param_2, 0x00012040 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x00012080 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x00012088 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x00012090 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x00012094 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk, + 0x00012098 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk, + 0x0001209c + 0x4000 * GSI_EE_AP); + +REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr, + 0x000120a0 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr, + 0x000120a4 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_SRC_IEOB_IRQ, cntxt_src_ieob_irq, 0x000120b0 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_SRC_IEOB_IRQ_MSK, cntxt_src_ieob_irq_msk, + 0x000120b8 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_SRC_IEOB_IRQ_CLR, cntxt_src_ieob_irq_clr, + 0x000120c0 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_GLOB_IRQ_STTS, cntxt_glob_irq_stts, 0x00012100 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_GLOB_IRQ_EN, cntxt_glob_irq_en, 0x00012108 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_GLOB_IRQ_CLR, cntxt_glob_irq_clr, 0x00012110 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_GSI_IRQ_STTS, cntxt_gsi_irq_stts, 0x00012118 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_GSI_IRQ_EN, cntxt_gsi_irq_en, 0x00012120 + 0x4000 * GSI_EE_AP); + +REG(CNTXT_GSI_IRQ_CLR, cntxt_gsi_irq_clr, 0x00012128 + 0x4000 * GSI_EE_AP); + +static const u32 reg_cntxt_intset_fmask[] = { + [INTYPE] = BIT(0) + /* Bits 1-31 reserved */ +}; + +REG_FIELDS(CNTXT_INTSET, cntxt_intset, 0x00012180 + 0x4000 * GSI_EE_AP); + +REG_FIELDS(ERROR_LOG, error_log, 0x00012200 + 0x4000 * GSI_EE_AP); + +REG(ERROR_LOG_CLR, error_log_clr, 0x00012210 + 0x4000 * GSI_EE_AP); + +static const u32 reg_cntxt_scratch_0_fmask[] = { + [INTER_EE_RESULT] = GENMASK(2, 0), + /* Bits 3-4 reserved */ + [GENERIC_EE_RESULT] = GENMASK(7, 5), + /* Bits 8-31 reserved */ +}; + +REG_FIELDS(CNTXT_SCRATCH_0, cntxt_scratch_0, 0x00012400 + 0x4000 * GSI_EE_AP); + +static const struct reg *reg_array[] = { + [INTER_EE_SRC_CH_IRQ_MSK] = ®_inter_ee_src_ch_irq_msk, + [INTER_EE_SRC_EV_CH_IRQ_MSK] = ®_inter_ee_src_ev_ch_irq_msk, + [CH_C_CNTXT_0] = ®_ch_c_cntxt_0, + [CH_C_CNTXT_1] = ®_ch_c_cntxt_1, + [CH_C_CNTXT_2] = ®_ch_c_cntxt_2, + [CH_C_CNTXT_3] = ®_ch_c_cntxt_3, + [CH_C_QOS] = ®_ch_c_qos, + [CH_C_SCRATCH_0] = ®_ch_c_scratch_0, + [CH_C_SCRATCH_1] = ®_ch_c_scratch_1, + [CH_C_SCRATCH_2] = ®_ch_c_scratch_2, + [CH_C_SCRATCH_3] = ®_ch_c_scratch_3, + [EV_CH_E_CNTXT_0] = ®_ev_ch_e_cntxt_0, + [EV_CH_E_CNTXT_1] = ®_ev_ch_e_cntxt_1, + [EV_CH_E_CNTXT_2] = ®_ev_ch_e_cntxt_2, + [EV_CH_E_CNTXT_3] = ®_ev_ch_e_cntxt_3, + [EV_CH_E_CNTXT_4] = ®_ev_ch_e_cntxt_4, + [EV_CH_E_CNTXT_8] = ®_ev_ch_e_cntxt_8, + [EV_CH_E_CNTXT_9] = ®_ev_ch_e_cntxt_9, + [EV_CH_E_CNTXT_10] = ®_ev_ch_e_cntxt_10, + [EV_CH_E_CNTXT_11] = ®_ev_ch_e_cntxt_11, + [EV_CH_E_CNTXT_12] = ®_ev_ch_e_cntxt_12, + [EV_CH_E_CNTXT_13] = ®_ev_ch_e_cntxt_13, + [EV_CH_E_SCRATCH_0] = ®_ev_ch_e_scratch_0, + [EV_CH_E_SCRATCH_1] = ®_ev_ch_e_scratch_1, + [CH_C_DOORBELL_0] = ®_ch_c_doorbell_0, + [EV_CH_E_DOORBELL_0] = ®_ev_ch_e_doorbell_0, + [GSI_STATUS] = ®_gsi_status, + [CH_CMD] = ®_ch_cmd, + [EV_CH_CMD] = ®_ev_ch_cmd, + [GENERIC_CMD] = ®_generic_cmd, + [HW_PARAM_2] = ®_hw_param_2, + [CNTXT_TYPE_IRQ] = ®_cntxt_type_irq, + [CNTXT_TYPE_IRQ_MSK] = ®_cntxt_type_irq_msk, + [CNTXT_SRC_CH_IRQ] = ®_cntxt_src_ch_irq, + [CNTXT_SRC_EV_CH_IRQ] = ®_cntxt_src_ev_ch_irq, + [CNTXT_SRC_CH_IRQ_MSK] = ®_cntxt_src_ch_irq_msk, + [CNTXT_SRC_EV_CH_IRQ_MSK] = ®_cntxt_src_ev_ch_irq_msk, + [CNTXT_SRC_CH_IRQ_CLR] = ®_cntxt_src_ch_irq_clr, + [CNTXT_SRC_EV_CH_IRQ_CLR] = ®_cntxt_src_ev_ch_irq_clr, + [CNTXT_SRC_IEOB_IRQ] = ®_cntxt_src_ieob_irq, + [CNTXT_SRC_IEOB_IRQ_MSK] = ®_cntxt_src_ieob_irq_msk, + [CNTXT_SRC_IEOB_IRQ_CLR] = ®_cntxt_src_ieob_irq_clr, + [CNTXT_GLOB_IRQ_STTS] = ®_cntxt_glob_irq_stts, + [CNTXT_GLOB_IRQ_EN] = ®_cntxt_glob_irq_en, + [CNTXT_GLOB_IRQ_CLR] = ®_cntxt_glob_irq_clr, + [CNTXT_GSI_IRQ_STTS] = ®_cntxt_gsi_irq_stts, + [CNTXT_GSI_IRQ_EN] = ®_cntxt_gsi_irq_en, + [CNTXT_GSI_IRQ_CLR] = ®_cntxt_gsi_irq_clr, + [CNTXT_INTSET] = ®_cntxt_intset, + [ERROR_LOG] = ®_error_log, + [ERROR_LOG_CLR] = ®_error_log_clr, + [CNTXT_SCRATCH_0] = ®_cntxt_scratch_0, +}; + +const struct regs gsi_regs_v4_9 = { + .reg_count = ARRAY_SIZE(reg_array), + .reg = reg_array, +}; diff --git a/drivers/net/ipa/reg/ipa_reg-v3.1.c b/drivers/net/ipa/reg/ipa_reg-v3.1.c index 0d002c3c38a2..648dbfe1fce3 100644 --- a/drivers/net/ipa/reg/ipa_reg-v3.1.c +++ b/drivers/net/ipa/reg/ipa_reg-v3.1.c @@ -7,7 +7,7 @@ #include "../ipa.h" #include "../ipa_reg.h" -static const u32 ipa_reg_comp_cfg_fmask[] = { +static const u32 reg_comp_cfg_fmask[] = { [COMP_CFG_ENABLE] = BIT(0), [GSI_SNOC_BYPASS_DIS] = BIT(1), [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2), @@ -16,9 +16,9 @@ static const u32 ipa_reg_comp_cfg_fmask[] = { /* Bits 5-31 reserved */ }; -IPA_REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c); +REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c); -static const u32 ipa_reg_clkon_cfg_fmask[] = { +static const u32 reg_clkon_cfg_fmask[] = { [CLKON_RX] = BIT(0), [CLKON_PROC] = BIT(1), [TX_WRAPPER] = BIT(2), @@ -39,9 +39,9 @@ static const u32 ipa_reg_clkon_cfg_fmask[] = { /* Bits 17-31 reserved */ }; -IPA_REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044); +REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044); -static const u32 ipa_reg_route_fmask[] = { +static const u32 reg_route_fmask[] = { [ROUTE_DIS] = BIT(0), [ROUTE_DEF_PIPE] = GENMASK(5, 1), [ROUTE_DEF_HDR_TABLE] = BIT(6), @@ -52,31 +52,31 @@ static const u32 ipa_reg_route_fmask[] = { /* Bits 25-31 reserved */ }; -IPA_REG_FIELDS(ROUTE, route, 0x00000048); +REG_FIELDS(ROUTE, route, 0x00000048); -static const u32 ipa_reg_shared_mem_size_fmask[] = { +static const u32 reg_shared_mem_size_fmask[] = { [MEM_SIZE] = GENMASK(15, 0), [MEM_BADDR] = GENMASK(31, 16), }; -IPA_REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054); +REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054); -static const u32 ipa_reg_qsb_max_writes_fmask[] = { +static const u32 reg_qsb_max_writes_fmask[] = { [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0), [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4), /* Bits 8-31 reserved */ }; -IPA_REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074); +REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074); -static const u32 ipa_reg_qsb_max_reads_fmask[] = { +static const u32 reg_qsb_max_reads_fmask[] = { [GEN_QMB_0_MAX_READS] = GENMASK(3, 0), [GEN_QMB_1_MAX_READS] = GENMASK(7, 4), }; -IPA_REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078); +REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078); -static const u32 ipa_reg_filt_rout_hash_en_fmask[] = { +static const u32 reg_filt_rout_hash_en_fmask[] = { [IPV6_ROUTER_HASH] = BIT(0), /* Bits 1-3 reserved */ [IPV6_FILTER_HASH] = BIT(4), @@ -87,9 +87,9 @@ static const u32 ipa_reg_filt_rout_hash_en_fmask[] = { /* Bits 13-31 reserved */ }; -IPA_REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x000008c); +REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x000008c); -static const u32 ipa_reg_filt_rout_hash_flush_fmask[] = { +static const u32 reg_filt_rout_hash_flush_fmask[] = { [IPV6_ROUTER_HASH] = BIT(0), /* Bits 1-3 reserved */ [IPV6_FILTER_HASH] = BIT(4), @@ -100,121 +100,121 @@ static const u32 ipa_reg_filt_rout_hash_flush_fmask[] = { /* Bits 13-31 reserved */ }; -IPA_REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x0000090); +REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x0000090); /* Valid bits defined by ipa->available */ -IPA_REG(STATE_AGGR_ACTIVE, state_aggr_active, 0x0000010c); +REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x0000010c, 0x0004); -IPA_REG(IPA_BCR, ipa_bcr, 0x000001d0); +REG(IPA_BCR, ipa_bcr, 0x000001d0); -static const u32 ipa_reg_local_pkt_proc_cntxt_fmask[] = { +static const u32 reg_local_pkt_proc_cntxt_fmask[] = { [IPA_BASE_ADDR] = GENMASK(16, 0), /* Bits 17-31 reserved */ }; /* Offset must be a multiple of 8 */ -IPA_REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8); +REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8); /* Valid bits defined by ipa->available */ -IPA_REG(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec); +REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004); -static const u32 ipa_reg_counter_cfg_fmask[] = { +static const u32 reg_counter_cfg_fmask[] = { [EOT_COAL_GRANULARITY] = GENMASK(3, 0), [AGGR_GRANULARITY] = GENMASK(8, 4), /* Bits 5-31 reserved */ }; -IPA_REG_FIELDS(COUNTER_CFG, counter_cfg, 0x000001f0); +REG_FIELDS(COUNTER_CFG, counter_cfg, 0x000001f0); -static const u32 ipa_reg_src_rsrc_grp_01_rsrc_type_fmask[] = { +static const u32 reg_src_rsrc_grp_01_rsrc_type_fmask[] = { [X_MIN_LIM] = GENMASK(7, 0), [X_MAX_LIM] = GENMASK(15, 8), [Y_MIN_LIM] = GENMASK(23, 16), [Y_MAX_LIM] = GENMASK(31, 24), }; -IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type, - 0x00000400, 0x0020); +REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type, + 0x00000400, 0x0020); -static const u32 ipa_reg_src_rsrc_grp_23_rsrc_type_fmask[] = { +static const u32 reg_src_rsrc_grp_23_rsrc_type_fmask[] = { [X_MIN_LIM] = GENMASK(7, 0), [X_MAX_LIM] = GENMASK(15, 8), [Y_MIN_LIM] = GENMASK(23, 16), [Y_MAX_LIM] = GENMASK(31, 24), }; -IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type, - 0x00000404, 0x0020); +REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type, + 0x00000404, 0x0020); -static const u32 ipa_reg_src_rsrc_grp_45_rsrc_type_fmask[] = { +static const u32 reg_src_rsrc_grp_45_rsrc_type_fmask[] = { [X_MIN_LIM] = GENMASK(7, 0), [X_MAX_LIM] = GENMASK(15, 8), [Y_MIN_LIM] = GENMASK(23, 16), [Y_MAX_LIM] = GENMASK(31, 24), }; -IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_45_RSRC_TYPE, src_rsrc_grp_45_rsrc_type, - 0x00000408, 0x0020); +REG_STRIDE_FIELDS(SRC_RSRC_GRP_45_RSRC_TYPE, src_rsrc_grp_45_rsrc_type, + 0x00000408, 0x0020); -static const u32 ipa_reg_src_rsrc_grp_67_rsrc_type_fmask[] = { +static const u32 reg_src_rsrc_grp_67_rsrc_type_fmask[] = { [X_MIN_LIM] = GENMASK(7, 0), [X_MAX_LIM] = GENMASK(15, 8), [Y_MIN_LIM] = GENMASK(23, 16), [Y_MAX_LIM] = GENMASK(31, 24), }; -IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_67_RSRC_TYPE, src_rsrc_grp_67_rsrc_type, - 0x0000040c, 0x0020); +REG_STRIDE_FIELDS(SRC_RSRC_GRP_67_RSRC_TYPE, src_rsrc_grp_67_rsrc_type, + 0x0000040c, 0x0020); -static const u32 ipa_reg_dst_rsrc_grp_01_rsrc_type_fmask[] = { +static const u32 reg_dst_rsrc_grp_01_rsrc_type_fmask[] = { [X_MIN_LIM] = GENMASK(7, 0), [X_MAX_LIM] = GENMASK(15, 8), [Y_MIN_LIM] = GENMASK(23, 16), [Y_MAX_LIM] = GENMASK(31, 24), }; -IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type, - 0x00000500, 0x0020); +REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type, + 0x00000500, 0x0020); -static const u32 ipa_reg_dst_rsrc_grp_23_rsrc_type_fmask[] = { +static const u32 reg_dst_rsrc_grp_23_rsrc_type_fmask[] = { [X_MIN_LIM] = GENMASK(7, 0), [X_MAX_LIM] = GENMASK(15, 8), [Y_MIN_LIM] = GENMASK(23, 16), [Y_MAX_LIM] = GENMASK(31, 24), }; -IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type, - 0x00000504, 0x0020); +REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type, + 0x00000504, 0x0020); -static const u32 ipa_reg_dst_rsrc_grp_45_rsrc_type_fmask[] = { +static const u32 reg_dst_rsrc_grp_45_rsrc_type_fmask[] = { [X_MIN_LIM] = GENMASK(7, 0), [X_MAX_LIM] = GENMASK(15, 8), [Y_MIN_LIM] = GENMASK(23, 16), [Y_MAX_LIM] = GENMASK(31, 24), }; -IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_45_RSRC_TYPE, dst_rsrc_grp_45_rsrc_type, - 0x00000508, 0x0020); +REG_STRIDE_FIELDS(DST_RSRC_GRP_45_RSRC_TYPE, dst_rsrc_grp_45_rsrc_type, + 0x00000508, 0x0020); -static const u32 ipa_reg_dst_rsrc_grp_67_rsrc_type_fmask[] = { +static const u32 reg_dst_rsrc_grp_67_rsrc_type_fmask[] = { [X_MIN_LIM] = GENMASK(7, 0), [X_MAX_LIM] = GENMASK(15, 8), [Y_MIN_LIM] = GENMASK(23, 16), [Y_MAX_LIM] = GENMASK(31, 24), }; -IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_67_RSRC_TYPE, dst_rsrc_grp_67_rsrc_type, - 0x0000050c, 0x0020); +REG_STRIDE_FIELDS(DST_RSRC_GRP_67_RSRC_TYPE, dst_rsrc_grp_67_rsrc_type, + 0x0000050c, 0x0020); -static const u32 ipa_reg_endp_init_ctrl_fmask[] = { +static const u32 reg_endp_init_ctrl_fmask[] = { [ENDP_SUSPEND] = BIT(0), [ENDP_DELAY] = BIT(1), /* Bits 2-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_CTRL, endp_init_ctrl, 0x00000800, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_CTRL, endp_init_ctrl, 0x00000800, 0x0070); -static const u32 ipa_reg_endp_init_cfg_fmask[] = { +static const u32 reg_endp_init_cfg_fmask[] = { [FRAG_OFFLOAD_EN] = BIT(0), [CS_OFFLOAD_EN] = GENMASK(2, 1), [CS_METADATA_HDR_OFFSET] = GENMASK(6, 3), @@ -223,16 +223,16 @@ static const u32 ipa_reg_endp_init_cfg_fmask[] = { /* Bits 9-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070); -static const u32 ipa_reg_endp_init_nat_fmask[] = { +static const u32 reg_endp_init_nat_fmask[] = { [NAT_EN] = GENMASK(1, 0), /* Bits 2-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070); -static const u32 ipa_reg_endp_init_hdr_fmask[] = { +static const u32 reg_endp_init_hdr_fmask[] = { [HDR_LEN] = GENMASK(5, 0), [HDR_OFST_METADATA_VALID] = BIT(6), [HDR_OFST_METADATA] = GENMASK(12, 7), @@ -245,9 +245,9 @@ static const u32 ipa_reg_endp_init_hdr_fmask[] = { /* Bits 29-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070); -static const u32 ipa_reg_endp_init_hdr_ext_fmask[] = { +static const u32 reg_endp_init_hdr_ext_fmask[] = { [HDR_ENDIANNESS] = BIT(0), [HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1), [HDR_TOTAL_LEN_OR_PAD] = BIT(2), @@ -257,12 +257,12 @@ static const u32 ipa_reg_endp_init_hdr_ext_fmask[] = { /* Bits 14-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070); -IPA_REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask, - 0x00000818, 0x0070); +REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask, + 0x00000818, 0x0070); -static const u32 ipa_reg_endp_init_mode_fmask[] = { +static const u32 reg_endp_init_mode_fmask[] = { [ENDP_MODE] = GENMASK(2, 0), /* Bit 3 reserved */ [DEST_PIPE_INDEX] = GENMASK(8, 4), @@ -274,9 +274,9 @@ static const u32 ipa_reg_endp_init_mode_fmask[] = { /* Bit 31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070); -static const u32 ipa_reg_endp_init_aggr_fmask[] = { +static const u32 reg_endp_init_aggr_fmask[] = { [AGGR_EN] = GENMASK(1, 0), [AGGR_TYPE] = GENMASK(4, 2), [BYTE_LIMIT] = GENMASK(9, 5), @@ -289,25 +289,25 @@ static const u32 ipa_reg_endp_init_aggr_fmask[] = { /* Bits 25-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070); -static const u32 ipa_reg_endp_init_hol_block_en_fmask[] = { +static const u32 reg_endp_init_hol_block_en_fmask[] = { [HOL_BLOCK_EN] = BIT(0), /* Bits 1-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en, - 0x0000082c, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en, + 0x0000082c, 0x0070); /* Entire register is a tick count */ -static const u32 ipa_reg_endp_init_hol_block_timer_fmask[] = { +static const u32 reg_endp_init_hol_block_timer_fmask[] = { [TIMER_BASE_VALUE] = GENMASK(31, 0), }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer, - 0x00000830, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer, + 0x00000830, 0x0070); -static const u32 ipa_reg_endp_init_deaggr_fmask[] = { +static const u32 reg_endp_init_deaggr_fmask[] = { [DEAGGR_HDR_LEN] = GENMASK(5, 0), [SYSPIPE_ERR_DETECTION] = BIT(6), [PACKET_OFFSET_VALID] = BIT(7), @@ -317,25 +317,24 @@ static const u32 ipa_reg_endp_init_deaggr_fmask[] = { [MAX_PACKET_LEN] = GENMASK(31, 16), }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070); -static const u32 ipa_reg_endp_init_rsrc_grp_fmask[] = { +static const u32 reg_endp_init_rsrc_grp_fmask[] = { [ENDP_RSRC_GRP] = GENMASK(2, 0), /* Bits 3-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, - 0x00000838, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00000838, 0x0070); -static const u32 ipa_reg_endp_init_seq_fmask[] = { +static const u32 reg_endp_init_seq_fmask[] = { [SEQ_TYPE] = GENMASK(7, 0), [SEQ_REP_TYPE] = GENMASK(15, 8), /* Bits 16-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070); -static const u32 ipa_reg_endp_status_fmask[] = { +static const u32 reg_endp_status_fmask[] = { [STATUS_EN] = BIT(0), [STATUS_ENDP] = GENMASK(5, 1), /* Bits 6-7 reserved */ @@ -343,9 +342,9 @@ static const u32 ipa_reg_endp_status_fmask[] = { /* Bits 9-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070); +REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070); -static const u32 ipa_reg_endp_filter_router_hsh_cfg_fmask[] = { +static const u32 reg_endp_filter_router_hsh_cfg_fmask[] = { [FILTER_HASH_MSK_SRC_ID] = BIT(0), [FILTER_HASH_MSK_SRC_IP] = BIT(1), [FILTER_HASH_MSK_DST_IP] = BIT(2), @@ -366,81 +365,84 @@ static const u32 ipa_reg_endp_filter_router_hsh_cfg_fmask[] = { /* Bits 23-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg, - 0x0000085c, 0x0070); +REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg, + 0x0000085c, 0x0070); /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ -IPA_REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP); +REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP); /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ -IPA_REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP); +REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP); /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ -IPA_REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP); +REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP); -static const u32 ipa_reg_ipa_irq_uc_fmask[] = { +static const u32 reg_ipa_irq_uc_fmask[] = { [UC_INTR] = BIT(0), /* Bits 1-31 reserved */ }; -IPA_REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000301c + 0x1000 * GSI_EE_AP); +REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000301c + 0x1000 * GSI_EE_AP); /* Valid bits defined by ipa->available */ -IPA_REG(IRQ_SUSPEND_INFO, irq_suspend_info, 0x00003030 + 0x1000 * GSI_EE_AP); +REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info, + 0x00003030 + 0x1000 * GSI_EE_AP, 0x0004); /* Valid bits defined by ipa->available */ -IPA_REG(IRQ_SUSPEND_EN, irq_suspend_en, 0x00003034 + 0x1000 * GSI_EE_AP); +REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en, + 0x00003034 + 0x1000 * GSI_EE_AP, 0x0004); /* Valid bits defined by ipa->available */ -IPA_REG(IRQ_SUSPEND_CLR, irq_suspend_clr, 0x00003038 + 0x1000 * GSI_EE_AP); - -static const struct ipa_reg *ipa_reg_array[] = { - [COMP_CFG] = &ipa_reg_comp_cfg, - [CLKON_CFG] = &ipa_reg_clkon_cfg, - [ROUTE] = &ipa_reg_route, - [SHARED_MEM_SIZE] = &ipa_reg_shared_mem_size, - [QSB_MAX_WRITES] = &ipa_reg_qsb_max_writes, - [QSB_MAX_READS] = &ipa_reg_qsb_max_reads, - [FILT_ROUT_HASH_EN] = &ipa_reg_filt_rout_hash_en, - [FILT_ROUT_HASH_FLUSH] = &ipa_reg_filt_rout_hash_flush, - [STATE_AGGR_ACTIVE] = &ipa_reg_state_aggr_active, - [IPA_BCR] = &ipa_reg_ipa_bcr, - [LOCAL_PKT_PROC_CNTXT] = &ipa_reg_local_pkt_proc_cntxt, - [AGGR_FORCE_CLOSE] = &ipa_reg_aggr_force_close, - [COUNTER_CFG] = &ipa_reg_counter_cfg, - [SRC_RSRC_GRP_01_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_01_rsrc_type, - [SRC_RSRC_GRP_23_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_23_rsrc_type, - [SRC_RSRC_GRP_45_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_45_rsrc_type, - [SRC_RSRC_GRP_67_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_67_rsrc_type, - [DST_RSRC_GRP_01_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_01_rsrc_type, - [DST_RSRC_GRP_23_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_23_rsrc_type, - [DST_RSRC_GRP_45_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_45_rsrc_type, - [DST_RSRC_GRP_67_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_67_rsrc_type, - [ENDP_INIT_CTRL] = &ipa_reg_endp_init_ctrl, - [ENDP_INIT_CFG] = &ipa_reg_endp_init_cfg, - [ENDP_INIT_NAT] = &ipa_reg_endp_init_nat, - [ENDP_INIT_HDR] = &ipa_reg_endp_init_hdr, - [ENDP_INIT_HDR_EXT] = &ipa_reg_endp_init_hdr_ext, - [ENDP_INIT_HDR_METADATA_MASK] = &ipa_reg_endp_init_hdr_metadata_mask, - [ENDP_INIT_MODE] = &ipa_reg_endp_init_mode, - [ENDP_INIT_AGGR] = &ipa_reg_endp_init_aggr, - [ENDP_INIT_HOL_BLOCK_EN] = &ipa_reg_endp_init_hol_block_en, - [ENDP_INIT_HOL_BLOCK_TIMER] = &ipa_reg_endp_init_hol_block_timer, - [ENDP_INIT_DEAGGR] = &ipa_reg_endp_init_deaggr, - [ENDP_INIT_RSRC_GRP] = &ipa_reg_endp_init_rsrc_grp, - [ENDP_INIT_SEQ] = &ipa_reg_endp_init_seq, - [ENDP_STATUS] = &ipa_reg_endp_status, - [ENDP_FILTER_ROUTER_HSH_CFG] = &ipa_reg_endp_filter_router_hsh_cfg, - [IPA_IRQ_STTS] = &ipa_reg_ipa_irq_stts, - [IPA_IRQ_EN] = &ipa_reg_ipa_irq_en, - [IPA_IRQ_CLR] = &ipa_reg_ipa_irq_clr, - [IPA_IRQ_UC] = &ipa_reg_ipa_irq_uc, - [IRQ_SUSPEND_INFO] = &ipa_reg_irq_suspend_info, - [IRQ_SUSPEND_EN] = &ipa_reg_irq_suspend_en, - [IRQ_SUSPEND_CLR] = &ipa_reg_irq_suspend_clr, -}; - -const struct ipa_regs ipa_regs_v3_1 = { - .reg_count = ARRAY_SIZE(ipa_reg_array), - .reg = ipa_reg_array, +REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr, + 0x00003038 + 0x1000 * GSI_EE_AP, 0x0004); + +static const struct reg *reg_array[] = { + [COMP_CFG] = ®_comp_cfg, + [CLKON_CFG] = ®_clkon_cfg, + [ROUTE] = ®_route, + [SHARED_MEM_SIZE] = ®_shared_mem_size, + [QSB_MAX_WRITES] = ®_qsb_max_writes, + [QSB_MAX_READS] = ®_qsb_max_reads, + [FILT_ROUT_HASH_EN] = ®_filt_rout_hash_en, + [FILT_ROUT_HASH_FLUSH] = ®_filt_rout_hash_flush, + [STATE_AGGR_ACTIVE] = ®_state_aggr_active, + [IPA_BCR] = ®_ipa_bcr, + [LOCAL_PKT_PROC_CNTXT] = ®_local_pkt_proc_cntxt, + [AGGR_FORCE_CLOSE] = ®_aggr_force_close, + [COUNTER_CFG] = ®_counter_cfg, + [SRC_RSRC_GRP_01_RSRC_TYPE] = ®_src_rsrc_grp_01_rsrc_type, + [SRC_RSRC_GRP_23_RSRC_TYPE] = ®_src_rsrc_grp_23_rsrc_type, + [SRC_RSRC_GRP_45_RSRC_TYPE] = ®_src_rsrc_grp_45_rsrc_type, + [SRC_RSRC_GRP_67_RSRC_TYPE] = ®_src_rsrc_grp_67_rsrc_type, + [DST_RSRC_GRP_01_RSRC_TYPE] = ®_dst_rsrc_grp_01_rsrc_type, + [DST_RSRC_GRP_23_RSRC_TYPE] = ®_dst_rsrc_grp_23_rsrc_type, + [DST_RSRC_GRP_45_RSRC_TYPE] = ®_dst_rsrc_grp_45_rsrc_type, + [DST_RSRC_GRP_67_RSRC_TYPE] = ®_dst_rsrc_grp_67_rsrc_type, + [ENDP_INIT_CTRL] = ®_endp_init_ctrl, + [ENDP_INIT_CFG] = ®_endp_init_cfg, + [ENDP_INIT_NAT] = ®_endp_init_nat, + [ENDP_INIT_HDR] = ®_endp_init_hdr, + [ENDP_INIT_HDR_EXT] = ®_endp_init_hdr_ext, + [ENDP_INIT_HDR_METADATA_MASK] = ®_endp_init_hdr_metadata_mask, + [ENDP_INIT_MODE] = ®_endp_init_mode, + [ENDP_INIT_AGGR] = ®_endp_init_aggr, + [ENDP_INIT_HOL_BLOCK_EN] = ®_endp_init_hol_block_en, + [ENDP_INIT_HOL_BLOCK_TIMER] = ®_endp_init_hol_block_timer, + [ENDP_INIT_DEAGGR] = ®_endp_init_deaggr, + [ENDP_INIT_RSRC_GRP] = ®_endp_init_rsrc_grp, + [ENDP_INIT_SEQ] = ®_endp_init_seq, + [ENDP_STATUS] = ®_endp_status, + [ENDP_FILTER_ROUTER_HSH_CFG] = ®_endp_filter_router_hsh_cfg, + [IPA_IRQ_STTS] = ®_ipa_irq_stts, + [IPA_IRQ_EN] = ®_ipa_irq_en, + [IPA_IRQ_CLR] = ®_ipa_irq_clr, + [IPA_IRQ_UC] = ®_ipa_irq_uc, + [IRQ_SUSPEND_INFO] = ®_irq_suspend_info, + [IRQ_SUSPEND_EN] = ®_irq_suspend_en, + [IRQ_SUSPEND_CLR] = ®_irq_suspend_clr, +}; + +const struct regs ipa_regs_v3_1 = { + .reg_count = ARRAY_SIZE(reg_array), + .reg = reg_array, }; diff --git a/drivers/net/ipa/reg/ipa_reg-v3.5.1.c b/drivers/net/ipa/reg/ipa_reg-v3.5.1.c index 6e2f939b18f1..78b1bf60cd02 100644 --- a/drivers/net/ipa/reg/ipa_reg-v3.5.1.c +++ b/drivers/net/ipa/reg/ipa_reg-v3.5.1.c @@ -7,7 +7,7 @@ #include "../ipa.h" #include "../ipa_reg.h" -static const u32 ipa_reg_comp_cfg_fmask[] = { +static const u32 reg_comp_cfg_fmask[] = { [COMP_CFG_ENABLE] = BIT(0), [GSI_SNOC_BYPASS_DIS] = BIT(1), [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2), @@ -16,9 +16,9 @@ static const u32 ipa_reg_comp_cfg_fmask[] = { /* Bits 5-31 reserved */ }; -IPA_REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c); +REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c); -static const u32 ipa_reg_clkon_cfg_fmask[] = { +static const u32 reg_clkon_cfg_fmask[] = { [CLKON_RX] = BIT(0), [CLKON_PROC] = BIT(1), [TX_WRAPPER] = BIT(2), @@ -44,9 +44,9 @@ static const u32 ipa_reg_clkon_cfg_fmask[] = { /* Bits 22-31 reserved */ }; -IPA_REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044); +REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044); -static const u32 ipa_reg_route_fmask[] = { +static const u32 reg_route_fmask[] = { [ROUTE_DIS] = BIT(0), [ROUTE_DEF_PIPE] = GENMASK(5, 1), [ROUTE_DEF_HDR_TABLE] = BIT(6), @@ -57,31 +57,31 @@ static const u32 ipa_reg_route_fmask[] = { /* Bits 25-31 reserved */ }; -IPA_REG_FIELDS(ROUTE, route, 0x00000048); +REG_FIELDS(ROUTE, route, 0x00000048); -static const u32 ipa_reg_shared_mem_size_fmask[] = { +static const u32 reg_shared_mem_size_fmask[] = { [MEM_SIZE] = GENMASK(15, 0), [MEM_BADDR] = GENMASK(31, 16), }; -IPA_REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054); +REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054); -static const u32 ipa_reg_qsb_max_writes_fmask[] = { +static const u32 reg_qsb_max_writes_fmask[] = { [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0), [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4), /* Bits 8-31 reserved */ }; -IPA_REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074); +REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074); -static const u32 ipa_reg_qsb_max_reads_fmask[] = { +static const u32 reg_qsb_max_reads_fmask[] = { [GEN_QMB_0_MAX_READS] = GENMASK(3, 0), [GEN_QMB_1_MAX_READS] = GENMASK(7, 4), }; -IPA_REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078); +REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078); -static const u32 ipa_reg_filt_rout_hash_en_fmask[] = { +static const u32 reg_filt_rout_hash_en_fmask[] = { [IPV6_ROUTER_HASH] = BIT(0), /* Bits 1-3 reserved */ [IPV6_FILTER_HASH] = BIT(4), @@ -92,9 +92,9 @@ static const u32 ipa_reg_filt_rout_hash_en_fmask[] = { /* Bits 13-31 reserved */ }; -IPA_REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x000008c); +REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x000008c); -static const u32 ipa_reg_filt_rout_hash_flush_fmask[] = { +static const u32 reg_filt_rout_hash_flush_fmask[] = { [IPV6_ROUTER_HASH] = BIT(0), /* Bits 1-3 reserved */ [IPV6_FILTER_HASH] = BIT(4), @@ -105,42 +105,42 @@ static const u32 ipa_reg_filt_rout_hash_flush_fmask[] = { /* Bits 13-31 reserved */ }; -IPA_REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x0000090); +REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x0000090); /* Valid bits defined by ipa->available */ -IPA_REG(STATE_AGGR_ACTIVE, state_aggr_active, 0x0000010c); +REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x0000010c, 0x0004); -IPA_REG(IPA_BCR, ipa_bcr, 0x000001d0); +REG(IPA_BCR, ipa_bcr, 0x000001d0); -static const u32 ipa_reg_local_pkt_proc_cntxt_fmask[] = { +static const u32 reg_local_pkt_proc_cntxt_fmask[] = { [IPA_BASE_ADDR] = GENMASK(16, 0), /* Bits 17-31 reserved */ }; /* Offset must be a multiple of 8 */ -IPA_REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8); +REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8); /* Valid bits defined by ipa->available */ -IPA_REG(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec); +REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004); -static const u32 ipa_reg_counter_cfg_fmask[] = { +static const u32 reg_counter_cfg_fmask[] = { /* Bits 0-3 reserved */ [AGGR_GRANULARITY] = GENMASK(8, 4), /* Bits 5-31 reserved */ }; -IPA_REG_FIELDS(COUNTER_CFG, counter_cfg, 0x000001f0); +REG_FIELDS(COUNTER_CFG, counter_cfg, 0x000001f0); -static const u32 ipa_reg_ipa_tx_cfg_fmask[] = { +static const u32 reg_ipa_tx_cfg_fmask[] = { [TX0_PREFETCH_DISABLE] = BIT(0), [TX1_PREFETCH_DISABLE] = BIT(1), [PREFETCH_ALMOST_EMPTY_SIZE] = GENMASK(4, 2), /* Bits 5-31 reserved */ }; -IPA_REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc); +REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc); -static const u32 ipa_reg_flavor_0_fmask[] = { +static const u32 reg_flavor_0_fmask[] = { [MAX_PIPES] = GENMASK(3, 0), /* Bits 4-7 reserved */ [MAX_CONS_PIPES] = GENMASK(12, 8), @@ -151,17 +151,17 @@ static const u32 ipa_reg_flavor_0_fmask[] = { /* Bits 28-31 reserved */ }; -IPA_REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210); +REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210); -static const u32 ipa_reg_idle_indication_cfg_fmask[] = { +static const u32 reg_idle_indication_cfg_fmask[] = { [ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0), [CONST_NON_IDLE_ENABLE] = BIT(16), /* Bits 17-31 reserved */ }; -IPA_REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000220); +REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000220); -static const u32 ipa_reg_src_rsrc_grp_01_rsrc_type_fmask[] = { +static const u32 reg_src_rsrc_grp_01_rsrc_type_fmask[] = { [X_MIN_LIM] = GENMASK(5, 0), /* Bits 6-7 reserved */ [X_MAX_LIM] = GENMASK(13, 8), @@ -172,10 +172,10 @@ static const u32 ipa_reg_src_rsrc_grp_01_rsrc_type_fmask[] = { /* Bits 30-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type, - 0x00000400, 0x0020); +REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type, + 0x00000400, 0x0020); -static const u32 ipa_reg_src_rsrc_grp_23_rsrc_type_fmask[] = { +static const u32 reg_src_rsrc_grp_23_rsrc_type_fmask[] = { [X_MIN_LIM] = GENMASK(5, 0), /* Bits 6-7 reserved */ [X_MAX_LIM] = GENMASK(13, 8), @@ -186,10 +186,10 @@ static const u32 ipa_reg_src_rsrc_grp_23_rsrc_type_fmask[] = { /* Bits 30-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type, - 0x00000404, 0x0020); +REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type, + 0x00000404, 0x0020); -static const u32 ipa_reg_dst_rsrc_grp_01_rsrc_type_fmask[] = { +static const u32 reg_dst_rsrc_grp_01_rsrc_type_fmask[] = { [X_MIN_LIM] = GENMASK(5, 0), /* Bits 6-7 reserved */ [X_MAX_LIM] = GENMASK(13, 8), @@ -200,10 +200,10 @@ static const u32 ipa_reg_dst_rsrc_grp_01_rsrc_type_fmask[] = { /* Bits 30-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type, - 0x00000500, 0x0020); +REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type, + 0x00000500, 0x0020); -static const u32 ipa_reg_dst_rsrc_grp_23_rsrc_type_fmask[] = { +static const u32 reg_dst_rsrc_grp_23_rsrc_type_fmask[] = { [X_MIN_LIM] = GENMASK(5, 0), /* Bits 6-7 reserved */ [X_MAX_LIM] = GENMASK(13, 8), @@ -214,18 +214,18 @@ static const u32 ipa_reg_dst_rsrc_grp_23_rsrc_type_fmask[] = { /* Bits 30-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type, - 0x00000504, 0x0020); +REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type, + 0x00000504, 0x0020); -static const u32 ipa_reg_endp_init_ctrl_fmask[] = { +static const u32 reg_endp_init_ctrl_fmask[] = { [ENDP_SUSPEND] = BIT(0), [ENDP_DELAY] = BIT(1), /* Bits 2-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_CTRL, endp_init_ctrl, 0x00000800, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_CTRL, endp_init_ctrl, 0x00000800, 0x0070); -static const u32 ipa_reg_endp_init_cfg_fmask[] = { +static const u32 reg_endp_init_cfg_fmask[] = { [FRAG_OFFLOAD_EN] = BIT(0), [CS_OFFLOAD_EN] = GENMASK(2, 1), [CS_METADATA_HDR_OFFSET] = GENMASK(6, 3), @@ -234,16 +234,16 @@ static const u32 ipa_reg_endp_init_cfg_fmask[] = { /* Bits 9-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070); -static const u32 ipa_reg_endp_init_nat_fmask[] = { +static const u32 reg_endp_init_nat_fmask[] = { [NAT_EN] = GENMASK(1, 0), /* Bits 2-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070); -static const u32 ipa_reg_endp_init_hdr_fmask[] = { +static const u32 reg_endp_init_hdr_fmask[] = { [HDR_LEN] = GENMASK(5, 0), [HDR_OFST_METADATA_VALID] = BIT(6), [HDR_OFST_METADATA] = GENMASK(12, 7), @@ -256,9 +256,9 @@ static const u32 ipa_reg_endp_init_hdr_fmask[] = { /* Bits 29-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070); -static const u32 ipa_reg_endp_init_hdr_ext_fmask[] = { +static const u32 reg_endp_init_hdr_ext_fmask[] = { [HDR_ENDIANNESS] = BIT(0), [HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1), [HDR_TOTAL_LEN_OR_PAD] = BIT(2), @@ -268,12 +268,12 @@ static const u32 ipa_reg_endp_init_hdr_ext_fmask[] = { /* Bits 14-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070); -IPA_REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask, - 0x00000818, 0x0070); +REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask, + 0x00000818, 0x0070); -static const u32 ipa_reg_endp_init_mode_fmask[] = { +static const u32 reg_endp_init_mode_fmask[] = { [ENDP_MODE] = GENMASK(2, 0), /* Bit 3 reserved */ [DEST_PIPE_INDEX] = GENMASK(8, 4), @@ -285,9 +285,9 @@ static const u32 ipa_reg_endp_init_mode_fmask[] = { /* Bit 31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070); -static const u32 ipa_reg_endp_init_aggr_fmask[] = { +static const u32 reg_endp_init_aggr_fmask[] = { [AGGR_EN] = GENMASK(1, 0), [AGGR_TYPE] = GENMASK(4, 2), [BYTE_LIMIT] = GENMASK(9, 5), @@ -300,25 +300,25 @@ static const u32 ipa_reg_endp_init_aggr_fmask[] = { /* Bits 25-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070); -static const u32 ipa_reg_endp_init_hol_block_en_fmask[] = { +static const u32 reg_endp_init_hol_block_en_fmask[] = { [HOL_BLOCK_EN] = BIT(0), /* Bits 1-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en, - 0x0000082c, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en, + 0x0000082c, 0x0070); /* Entire register is a tick count */ -static const u32 ipa_reg_endp_init_hol_block_timer_fmask[] = { +static const u32 reg_endp_init_hol_block_timer_fmask[] = { [TIMER_BASE_VALUE] = GENMASK(31, 0), }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer, - 0x00000830, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer, + 0x00000830, 0x0070); -static const u32 ipa_reg_endp_init_deaggr_fmask[] = { +static const u32 reg_endp_init_deaggr_fmask[] = { [DEAGGR_HDR_LEN] = GENMASK(5, 0), [SYSPIPE_ERR_DETECTION] = BIT(6), [PACKET_OFFSET_VALID] = BIT(7), @@ -328,25 +328,24 @@ static const u32 ipa_reg_endp_init_deaggr_fmask[] = { [MAX_PACKET_LEN] = GENMASK(31, 16), }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070); -static const u32 ipa_reg_endp_init_rsrc_grp_fmask[] = { +static const u32 reg_endp_init_rsrc_grp_fmask[] = { [ENDP_RSRC_GRP] = GENMASK(1, 0), /* Bits 2-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, - 0x00000838, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00000838, 0x0070); -static const u32 ipa_reg_endp_init_seq_fmask[] = { +static const u32 reg_endp_init_seq_fmask[] = { [SEQ_TYPE] = GENMASK(7, 0), [SEQ_REP_TYPE] = GENMASK(15, 8), /* Bits 16-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070); -static const u32 ipa_reg_endp_status_fmask[] = { +static const u32 reg_endp_status_fmask[] = { [STATUS_EN] = BIT(0), [STATUS_ENDP] = GENMASK(5, 1), /* Bits 6-7 reserved */ @@ -354,9 +353,9 @@ static const u32 ipa_reg_endp_status_fmask[] = { /* Bits 9-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070); +REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070); -static const u32 ipa_reg_endp_filter_router_hsh_cfg_fmask[] = { +static const u32 reg_endp_filter_router_hsh_cfg_fmask[] = { [FILTER_HASH_MSK_SRC_ID] = BIT(0), [FILTER_HASH_MSK_SRC_IP] = BIT(1), [FILTER_HASH_MSK_DST_IP] = BIT(2), @@ -377,80 +376,83 @@ static const u32 ipa_reg_endp_filter_router_hsh_cfg_fmask[] = { /* Bits 23-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg, - 0x0000085c, 0x0070); +REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg, + 0x0000085c, 0x0070); /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ -IPA_REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP); +REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP); /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ -IPA_REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP); +REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP); /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ -IPA_REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP); +REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP); -static const u32 ipa_reg_ipa_irq_uc_fmask[] = { +static const u32 reg_ipa_irq_uc_fmask[] = { [UC_INTR] = BIT(0), /* Bits 1-31 reserved */ }; -IPA_REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000301c + 0x1000 * GSI_EE_AP); +REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000301c + 0x1000 * GSI_EE_AP); /* Valid bits defined by ipa->available */ -IPA_REG(IRQ_SUSPEND_INFO, irq_suspend_info, 0x00003030 + 0x1000 * GSI_EE_AP); +REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info, + 0x00003030 + 0x1000 * GSI_EE_AP, 0x0004); /* Valid bits defined by ipa->available */ -IPA_REG(IRQ_SUSPEND_EN, irq_suspend_en, 0x00003034 + 0x1000 * GSI_EE_AP); +REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en, + 0x00003034 + 0x1000 * GSI_EE_AP, 0x0004); /* Valid bits defined by ipa->available */ -IPA_REG(IRQ_SUSPEND_CLR, irq_suspend_clr, 0x00003038 + 0x1000 * GSI_EE_AP); - -static const struct ipa_reg *ipa_reg_array[] = { - [COMP_CFG] = &ipa_reg_comp_cfg, - [CLKON_CFG] = &ipa_reg_clkon_cfg, - [ROUTE] = &ipa_reg_route, - [SHARED_MEM_SIZE] = &ipa_reg_shared_mem_size, - [QSB_MAX_WRITES] = &ipa_reg_qsb_max_writes, - [QSB_MAX_READS] = &ipa_reg_qsb_max_reads, - [FILT_ROUT_HASH_EN] = &ipa_reg_filt_rout_hash_en, - [FILT_ROUT_HASH_FLUSH] = &ipa_reg_filt_rout_hash_flush, - [STATE_AGGR_ACTIVE] = &ipa_reg_state_aggr_active, - [IPA_BCR] = &ipa_reg_ipa_bcr, - [LOCAL_PKT_PROC_CNTXT] = &ipa_reg_local_pkt_proc_cntxt, - [AGGR_FORCE_CLOSE] = &ipa_reg_aggr_force_close, - [COUNTER_CFG] = &ipa_reg_counter_cfg, - [IPA_TX_CFG] = &ipa_reg_ipa_tx_cfg, - [FLAVOR_0] = &ipa_reg_flavor_0, - [IDLE_INDICATION_CFG] = &ipa_reg_idle_indication_cfg, - [SRC_RSRC_GRP_01_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_01_rsrc_type, - [SRC_RSRC_GRP_23_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_23_rsrc_type, - [DST_RSRC_GRP_01_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_01_rsrc_type, - [DST_RSRC_GRP_23_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_23_rsrc_type, - [ENDP_INIT_CTRL] = &ipa_reg_endp_init_ctrl, - [ENDP_INIT_CFG] = &ipa_reg_endp_init_cfg, - [ENDP_INIT_NAT] = &ipa_reg_endp_init_nat, - [ENDP_INIT_HDR] = &ipa_reg_endp_init_hdr, - [ENDP_INIT_HDR_EXT] = &ipa_reg_endp_init_hdr_ext, - [ENDP_INIT_HDR_METADATA_MASK] = &ipa_reg_endp_init_hdr_metadata_mask, - [ENDP_INIT_MODE] = &ipa_reg_endp_init_mode, - [ENDP_INIT_AGGR] = &ipa_reg_endp_init_aggr, - [ENDP_INIT_HOL_BLOCK_EN] = &ipa_reg_endp_init_hol_block_en, - [ENDP_INIT_HOL_BLOCK_TIMER] = &ipa_reg_endp_init_hol_block_timer, - [ENDP_INIT_DEAGGR] = &ipa_reg_endp_init_deaggr, - [ENDP_INIT_RSRC_GRP] = &ipa_reg_endp_init_rsrc_grp, - [ENDP_INIT_SEQ] = &ipa_reg_endp_init_seq, - [ENDP_STATUS] = &ipa_reg_endp_status, - [ENDP_FILTER_ROUTER_HSH_CFG] = &ipa_reg_endp_filter_router_hsh_cfg, - [IPA_IRQ_STTS] = &ipa_reg_ipa_irq_stts, - [IPA_IRQ_EN] = &ipa_reg_ipa_irq_en, - [IPA_IRQ_CLR] = &ipa_reg_ipa_irq_clr, - [IPA_IRQ_UC] = &ipa_reg_ipa_irq_uc, - [IRQ_SUSPEND_INFO] = &ipa_reg_irq_suspend_info, - [IRQ_SUSPEND_EN] = &ipa_reg_irq_suspend_en, - [IRQ_SUSPEND_CLR] = &ipa_reg_irq_suspend_clr, -}; - -const struct ipa_regs ipa_regs_v3_5_1 = { - .reg_count = ARRAY_SIZE(ipa_reg_array), - .reg = ipa_reg_array, +REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr, + 0x00003038 + 0x1000 * GSI_EE_AP, 0x0004); + +static const struct reg *reg_array[] = { + [COMP_CFG] = ®_comp_cfg, + [CLKON_CFG] = ®_clkon_cfg, + [ROUTE] = ®_route, + [SHARED_MEM_SIZE] = ®_shared_mem_size, + [QSB_MAX_WRITES] = ®_qsb_max_writes, + [QSB_MAX_READS] = ®_qsb_max_reads, + [FILT_ROUT_HASH_EN] = ®_filt_rout_hash_en, + [FILT_ROUT_HASH_FLUSH] = ®_filt_rout_hash_flush, + [STATE_AGGR_ACTIVE] = ®_state_aggr_active, + [IPA_BCR] = ®_ipa_bcr, + [LOCAL_PKT_PROC_CNTXT] = ®_local_pkt_proc_cntxt, + [AGGR_FORCE_CLOSE] = ®_aggr_force_close, + [COUNTER_CFG] = ®_counter_cfg, + [IPA_TX_CFG] = ®_ipa_tx_cfg, + [FLAVOR_0] = ®_flavor_0, + [IDLE_INDICATION_CFG] = ®_idle_indication_cfg, + [SRC_RSRC_GRP_01_RSRC_TYPE] = ®_src_rsrc_grp_01_rsrc_type, + [SRC_RSRC_GRP_23_RSRC_TYPE] = ®_src_rsrc_grp_23_rsrc_type, + [DST_RSRC_GRP_01_RSRC_TYPE] = ®_dst_rsrc_grp_01_rsrc_type, + [DST_RSRC_GRP_23_RSRC_TYPE] = ®_dst_rsrc_grp_23_rsrc_type, + [ENDP_INIT_CTRL] = ®_endp_init_ctrl, + [ENDP_INIT_CFG] = ®_endp_init_cfg, + [ENDP_INIT_NAT] = ®_endp_init_nat, + [ENDP_INIT_HDR] = ®_endp_init_hdr, + [ENDP_INIT_HDR_EXT] = ®_endp_init_hdr_ext, + [ENDP_INIT_HDR_METADATA_MASK] = ®_endp_init_hdr_metadata_mask, + [ENDP_INIT_MODE] = ®_endp_init_mode, + [ENDP_INIT_AGGR] = ®_endp_init_aggr, + [ENDP_INIT_HOL_BLOCK_EN] = ®_endp_init_hol_block_en, + [ENDP_INIT_HOL_BLOCK_TIMER] = ®_endp_init_hol_block_timer, + [ENDP_INIT_DEAGGR] = ®_endp_init_deaggr, + [ENDP_INIT_RSRC_GRP] = ®_endp_init_rsrc_grp, + [ENDP_INIT_SEQ] = ®_endp_init_seq, + [ENDP_STATUS] = ®_endp_status, + [ENDP_FILTER_ROUTER_HSH_CFG] = ®_endp_filter_router_hsh_cfg, + [IPA_IRQ_STTS] = ®_ipa_irq_stts, + [IPA_IRQ_EN] = ®_ipa_irq_en, + [IPA_IRQ_CLR] = ®_ipa_irq_clr, + [IPA_IRQ_UC] = ®_ipa_irq_uc, + [IRQ_SUSPEND_INFO] = ®_irq_suspend_info, + [IRQ_SUSPEND_EN] = ®_irq_suspend_en, + [IRQ_SUSPEND_CLR] = ®_irq_suspend_clr, +}; + +const struct regs ipa_regs_v3_5_1 = { + .reg_count = ARRAY_SIZE(reg_array), + .reg = reg_array, }; diff --git a/drivers/net/ipa/reg/ipa_reg-v4.11.c b/drivers/net/ipa/reg/ipa_reg-v4.11.c index 8fd36569bb9f..29e71cce4a84 100644 --- a/drivers/net/ipa/reg/ipa_reg-v4.11.c +++ b/drivers/net/ipa/reg/ipa_reg-v4.11.c @@ -7,7 +7,7 @@ #include "../ipa.h" #include "../ipa_reg.h" -static const u32 ipa_reg_comp_cfg_fmask[] = { +static const u32 reg_comp_cfg_fmask[] = { [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0), [GSI_SNOC_BYPASS_DIS] = BIT(1), [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2), @@ -36,9 +36,9 @@ static const u32 ipa_reg_comp_cfg_fmask[] = { [GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31), }; -IPA_REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c); +REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c); -static const u32 ipa_reg_clkon_cfg_fmask[] = { +static const u32 reg_clkon_cfg_fmask[] = { [CLKON_RX] = BIT(0), [CLKON_PROC] = BIT(1), [TX_WRAPPER] = BIT(2), @@ -73,9 +73,9 @@ static const u32 ipa_reg_clkon_cfg_fmask[] = { [DRBIP] = BIT(31), }; -IPA_REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044); +REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044); -static const u32 ipa_reg_route_fmask[] = { +static const u32 reg_route_fmask[] = { [ROUTE_DIS] = BIT(0), [ROUTE_DEF_PIPE] = GENMASK(5, 1), [ROUTE_DEF_HDR_TABLE] = BIT(6), @@ -86,24 +86,24 @@ static const u32 ipa_reg_route_fmask[] = { /* Bits 25-31 reserved */ }; -IPA_REG_FIELDS(ROUTE, route, 0x00000048); +REG_FIELDS(ROUTE, route, 0x00000048); -static const u32 ipa_reg_shared_mem_size_fmask[] = { +static const u32 reg_shared_mem_size_fmask[] = { [MEM_SIZE] = GENMASK(15, 0), [MEM_BADDR] = GENMASK(31, 16), }; -IPA_REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054); +REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054); -static const u32 ipa_reg_qsb_max_writes_fmask[] = { +static const u32 reg_qsb_max_writes_fmask[] = { [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0), [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4), /* Bits 8-31 reserved */ }; -IPA_REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074); +REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074); -static const u32 ipa_reg_qsb_max_reads_fmask[] = { +static const u32 reg_qsb_max_reads_fmask[] = { [GEN_QMB_0_MAX_READS] = GENMASK(3, 0), [GEN_QMB_1_MAX_READS] = GENMASK(7, 4), /* Bits 8-15 reserved */ @@ -111,9 +111,9 @@ static const u32 ipa_reg_qsb_max_reads_fmask[] = { [GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24), }; -IPA_REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078); +REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078); -static const u32 ipa_reg_filt_rout_hash_en_fmask[] = { +static const u32 reg_filt_rout_hash_en_fmask[] = { [IPV6_ROUTER_HASH] = BIT(0), /* Bits 1-3 reserved */ [IPV6_FILTER_HASH] = BIT(4), @@ -124,9 +124,9 @@ static const u32 ipa_reg_filt_rout_hash_en_fmask[] = { /* Bits 13-31 reserved */ }; -IPA_REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x0000148); +REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x0000148); -static const u32 ipa_reg_filt_rout_hash_flush_fmask[] = { +static const u32 reg_filt_rout_hash_flush_fmask[] = { [IPV6_ROUTER_HASH] = BIT(0), /* Bits 1-3 reserved */ [IPV6_FILTER_HASH] = BIT(4), @@ -137,23 +137,23 @@ static const u32 ipa_reg_filt_rout_hash_flush_fmask[] = { /* Bits 13-31 reserved */ }; -IPA_REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c); +REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c); /* Valid bits defined by ipa->available */ -IPA_REG(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4); +REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4, 0x0004); -static const u32 ipa_reg_local_pkt_proc_cntxt_fmask[] = { +static const u32 reg_local_pkt_proc_cntxt_fmask[] = { [IPA_BASE_ADDR] = GENMASK(17, 0), /* Bits 18-31 reserved */ }; /* Offset must be a multiple of 8 */ -IPA_REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8); +REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8); /* Valid bits defined by ipa->available */ -IPA_REG(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec); +REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004); -static const u32 ipa_reg_ipa_tx_cfg_fmask[] = { +static const u32 reg_ipa_tx_cfg_fmask[] = { /* Bits 0-1 reserved */ [PREFETCH_ALMOST_EMPTY_SIZE_TX0] = GENMASK(5, 2), [DMAW_SCND_OUTSD_PRED_THRESHOLD] = GENMASK(9, 6), @@ -166,9 +166,9 @@ static const u32 ipa_reg_ipa_tx_cfg_fmask[] = { /* Bits 19-31 reserved */ }; -IPA_REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc); +REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc); -static const u32 ipa_reg_flavor_0_fmask[] = { +static const u32 reg_flavor_0_fmask[] = { [MAX_PIPES] = GENMASK(4, 0), /* Bits 5-7 reserved */ [MAX_CONS_PIPES] = GENMASK(12, 8), @@ -179,17 +179,17 @@ static const u32 ipa_reg_flavor_0_fmask[] = { /* Bits 28-31 reserved */ }; -IPA_REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210); +REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210); -static const u32 ipa_reg_idle_indication_cfg_fmask[] = { +static const u32 reg_idle_indication_cfg_fmask[] = { [ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0), [CONST_NON_IDLE_ENABLE] = BIT(16), /* Bits 17-31 reserved */ }; -IPA_REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000240); +REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000240); -static const u32 ipa_reg_qtime_timestamp_cfg_fmask[] = { +static const u32 reg_qtime_timestamp_cfg_fmask[] = { [DPL_TIMESTAMP_LSB] = GENMASK(4, 0), /* Bits 5-6 reserved */ [DPL_TIMESTAMP_SEL] = BIT(7), @@ -199,26 +199,26 @@ static const u32 ipa_reg_qtime_timestamp_cfg_fmask[] = { /* Bits 21-31 reserved */ }; -IPA_REG_FIELDS(QTIME_TIMESTAMP_CFG, qtime_timestamp_cfg, 0x0000024c); +REG_FIELDS(QTIME_TIMESTAMP_CFG, qtime_timestamp_cfg, 0x0000024c); -static const u32 ipa_reg_timers_xo_clk_div_cfg_fmask[] = { +static const u32 reg_timers_xo_clk_div_cfg_fmask[] = { [DIV_VALUE] = GENMASK(8, 0), /* Bits 9-30 reserved */ [DIV_ENABLE] = BIT(31), }; -IPA_REG_FIELDS(TIMERS_XO_CLK_DIV_CFG, timers_xo_clk_div_cfg, 0x00000250); +REG_FIELDS(TIMERS_XO_CLK_DIV_CFG, timers_xo_clk_div_cfg, 0x00000250); -static const u32 ipa_reg_timers_pulse_gran_cfg_fmask[] = { +static const u32 reg_timers_pulse_gran_cfg_fmask[] = { [PULSE_GRAN_0] = GENMASK(2, 0), [PULSE_GRAN_1] = GENMASK(5, 3), [PULSE_GRAN_2] = GENMASK(8, 6), /* Bits 9-31 reserved */ }; -IPA_REG_FIELDS(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x00000254); +REG_FIELDS(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x00000254); -static const u32 ipa_reg_src_rsrc_grp_01_rsrc_type_fmask[] = { +static const u32 reg_src_rsrc_grp_01_rsrc_type_fmask[] = { [X_MIN_LIM] = GENMASK(5, 0), /* Bits 6-7 reserved */ [X_MAX_LIM] = GENMASK(13, 8), @@ -229,10 +229,10 @@ static const u32 ipa_reg_src_rsrc_grp_01_rsrc_type_fmask[] = { /* Bits 30-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type, - 0x00000400, 0x0020); +REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type, + 0x00000400, 0x0020); -static const u32 ipa_reg_src_rsrc_grp_23_rsrc_type_fmask[] = { +static const u32 reg_src_rsrc_grp_23_rsrc_type_fmask[] = { [X_MIN_LIM] = GENMASK(5, 0), /* Bits 6-7 reserved */ [X_MAX_LIM] = GENMASK(13, 8), @@ -243,10 +243,10 @@ static const u32 ipa_reg_src_rsrc_grp_23_rsrc_type_fmask[] = { /* Bits 30-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type, - 0x00000404, 0x0020); +REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type, + 0x00000404, 0x0020); -static const u32 ipa_reg_dst_rsrc_grp_01_rsrc_type_fmask[] = { +static const u32 reg_dst_rsrc_grp_01_rsrc_type_fmask[] = { [X_MIN_LIM] = GENMASK(5, 0), /* Bits 6-7 reserved */ [X_MAX_LIM] = GENMASK(13, 8), @@ -257,10 +257,10 @@ static const u32 ipa_reg_dst_rsrc_grp_01_rsrc_type_fmask[] = { /* Bits 30-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type, - 0x00000500, 0x0020); +REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type, + 0x00000500, 0x0020); -static const u32 ipa_reg_dst_rsrc_grp_23_rsrc_type_fmask[] = { +static const u32 reg_dst_rsrc_grp_23_rsrc_type_fmask[] = { [X_MIN_LIM] = GENMASK(5, 0), /* Bits 6-7 reserved */ [X_MAX_LIM] = GENMASK(13, 8), @@ -271,10 +271,10 @@ static const u32 ipa_reg_dst_rsrc_grp_23_rsrc_type_fmask[] = { /* Bits 30-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type, - 0x00000504, 0x0020); +REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type, + 0x00000504, 0x0020); -static const u32 ipa_reg_endp_init_cfg_fmask[] = { +static const u32 reg_endp_init_cfg_fmask[] = { [FRAG_OFFLOAD_EN] = BIT(0), [CS_OFFLOAD_EN] = GENMASK(2, 1), [CS_METADATA_HDR_OFFSET] = GENMASK(6, 3), @@ -283,16 +283,16 @@ static const u32 ipa_reg_endp_init_cfg_fmask[] = { /* Bits 9-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070); -static const u32 ipa_reg_endp_init_nat_fmask[] = { +static const u32 reg_endp_init_nat_fmask[] = { [NAT_EN] = GENMASK(1, 0), /* Bits 2-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070); -static const u32 ipa_reg_endp_init_hdr_fmask[] = { +static const u32 reg_endp_init_hdr_fmask[] = { [HDR_LEN] = GENMASK(5, 0), [HDR_OFST_METADATA_VALID] = BIT(6), [HDR_OFST_METADATA] = GENMASK(12, 7), @@ -305,9 +305,9 @@ static const u32 ipa_reg_endp_init_hdr_fmask[] = { [HDR_OFST_METADATA_MSB] = GENMASK(31, 30), }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070); -static const u32 ipa_reg_endp_init_hdr_ext_fmask[] = { +static const u32 reg_endp_init_hdr_ext_fmask[] = { [HDR_ENDIANNESS] = BIT(0), [HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1), [HDR_TOTAL_LEN_OR_PAD] = BIT(2), @@ -321,12 +321,12 @@ static const u32 ipa_reg_endp_init_hdr_ext_fmask[] = { /* Bits 22-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070); -IPA_REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask, - 0x00000818, 0x0070); +REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask, + 0x00000818, 0x0070); -static const u32 ipa_reg_endp_init_mode_fmask[] = { +static const u32 reg_endp_init_mode_fmask[] = { [ENDP_MODE] = GENMASK(2, 0), [DCPH_ENABLE] = BIT(3), [DEST_PIPE_INDEX] = GENMASK(8, 4), @@ -338,9 +338,9 @@ static const u32 ipa_reg_endp_init_mode_fmask[] = { /* Bit 31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070); -static const u32 ipa_reg_endp_init_aggr_fmask[] = { +static const u32 reg_endp_init_aggr_fmask[] = { [AGGR_EN] = GENMASK(1, 0), [AGGR_TYPE] = GENMASK(4, 2), [BYTE_LIMIT] = GENMASK(10, 5), @@ -355,27 +355,27 @@ static const u32 ipa_reg_endp_init_aggr_fmask[] = { /* Bits 28-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070); -static const u32 ipa_reg_endp_init_hol_block_en_fmask[] = { +static const u32 reg_endp_init_hol_block_en_fmask[] = { [HOL_BLOCK_EN] = BIT(0), /* Bits 1-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en, - 0x0000082c, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en, + 0x0000082c, 0x0070); -static const u32 ipa_reg_endp_init_hol_block_timer_fmask[] = { +static const u32 reg_endp_init_hol_block_timer_fmask[] = { [TIMER_LIMIT] = GENMASK(4, 0), /* Bits 5-7 reserved */ [TIMER_GRAN_SEL] = BIT(8), /* Bits 9-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer, - 0x00000830, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer, + 0x00000830, 0x0070); -static const u32 ipa_reg_endp_init_deaggr_fmask[] = { +static const u32 reg_endp_init_deaggr_fmask[] = { [DEAGGR_HDR_LEN] = GENMASK(5, 0), [SYSPIPE_ERR_DETECTION] = BIT(6), [PACKET_OFFSET_VALID] = BIT(7), @@ -385,24 +385,23 @@ static const u32 ipa_reg_endp_init_deaggr_fmask[] = { [MAX_PACKET_LEN] = GENMASK(31, 16), }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070); -static const u32 ipa_reg_endp_init_rsrc_grp_fmask[] = { +static const u32 reg_endp_init_rsrc_grp_fmask[] = { [ENDP_RSRC_GRP] = GENMASK(1, 0), /* Bits 2-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, - 0x00000838, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00000838, 0x0070); -static const u32 ipa_reg_endp_init_seq_fmask[] = { +static const u32 reg_endp_init_seq_fmask[] = { [SEQ_TYPE] = GENMASK(7, 0), /* Bits 8-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070); -static const u32 ipa_reg_endp_status_fmask[] = { +static const u32 reg_endp_status_fmask[] = { [STATUS_EN] = BIT(0), [STATUS_ENDP] = GENMASK(5, 1), /* Bits 6-8 reserved */ @@ -410,9 +409,9 @@ static const u32 ipa_reg_endp_status_fmask[] = { /* Bits 10-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070); +REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070); -static const u32 ipa_reg_endp_filter_router_hsh_cfg_fmask[] = { +static const u32 reg_endp_filter_router_hsh_cfg_fmask[] = { [FILTER_HASH_MSK_SRC_ID] = BIT(0), [FILTER_HASH_MSK_SRC_IP] = BIT(1), [FILTER_HASH_MSK_DST_IP] = BIT(2), @@ -433,80 +432,83 @@ static const u32 ipa_reg_endp_filter_router_hsh_cfg_fmask[] = { /* Bits 23-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg, - 0x0000085c, 0x0070); +REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg, + 0x0000085c, 0x0070); /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ -IPA_REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00004008 + 0x1000 * GSI_EE_AP); +REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00004008 + 0x1000 * GSI_EE_AP); /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ -IPA_REG(IPA_IRQ_EN, ipa_irq_en, 0x0000400c + 0x1000 * GSI_EE_AP); +REG(IPA_IRQ_EN, ipa_irq_en, 0x0000400c + 0x1000 * GSI_EE_AP); /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ -IPA_REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00004010 + 0x1000 * GSI_EE_AP); +REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00004010 + 0x1000 * GSI_EE_AP); -static const u32 ipa_reg_ipa_irq_uc_fmask[] = { +static const u32 reg_ipa_irq_uc_fmask[] = { [UC_INTR] = BIT(0), /* Bits 1-31 reserved */ }; -IPA_REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000401c + 0x1000 * GSI_EE_AP); +REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000401c + 0x1000 * GSI_EE_AP); /* Valid bits defined by ipa->available */ -IPA_REG(IRQ_SUSPEND_INFO, irq_suspend_info, 0x00004030 + 0x1000 * GSI_EE_AP); +REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info, + 0x00004030 + 0x1000 * GSI_EE_AP, 0x0004); /* Valid bits defined by ipa->available */ -IPA_REG(IRQ_SUSPEND_EN, irq_suspend_en, 0x00004034 + 0x1000 * GSI_EE_AP); +REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en, + 0x00004034 + 0x1000 * GSI_EE_AP, 0x0004); /* Valid bits defined by ipa->available */ -IPA_REG(IRQ_SUSPEND_CLR, irq_suspend_clr, 0x00004038 + 0x1000 * GSI_EE_AP); - -static const struct ipa_reg *ipa_reg_array[] = { - [COMP_CFG] = &ipa_reg_comp_cfg, - [CLKON_CFG] = &ipa_reg_clkon_cfg, - [ROUTE] = &ipa_reg_route, - [SHARED_MEM_SIZE] = &ipa_reg_shared_mem_size, - [QSB_MAX_WRITES] = &ipa_reg_qsb_max_writes, - [QSB_MAX_READS] = &ipa_reg_qsb_max_reads, - [FILT_ROUT_HASH_EN] = &ipa_reg_filt_rout_hash_en, - [FILT_ROUT_HASH_FLUSH] = &ipa_reg_filt_rout_hash_flush, - [STATE_AGGR_ACTIVE] = &ipa_reg_state_aggr_active, - [LOCAL_PKT_PROC_CNTXT] = &ipa_reg_local_pkt_proc_cntxt, - [AGGR_FORCE_CLOSE] = &ipa_reg_aggr_force_close, - [IPA_TX_CFG] = &ipa_reg_ipa_tx_cfg, - [FLAVOR_0] = &ipa_reg_flavor_0, - [IDLE_INDICATION_CFG] = &ipa_reg_idle_indication_cfg, - [QTIME_TIMESTAMP_CFG] = &ipa_reg_qtime_timestamp_cfg, - [TIMERS_XO_CLK_DIV_CFG] = &ipa_reg_timers_xo_clk_div_cfg, - [TIMERS_PULSE_GRAN_CFG] = &ipa_reg_timers_pulse_gran_cfg, - [SRC_RSRC_GRP_01_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_01_rsrc_type, - [SRC_RSRC_GRP_23_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_23_rsrc_type, - [DST_RSRC_GRP_01_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_01_rsrc_type, - [DST_RSRC_GRP_23_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_23_rsrc_type, - [ENDP_INIT_CFG] = &ipa_reg_endp_init_cfg, - [ENDP_INIT_NAT] = &ipa_reg_endp_init_nat, - [ENDP_INIT_HDR] = &ipa_reg_endp_init_hdr, - [ENDP_INIT_HDR_EXT] = &ipa_reg_endp_init_hdr_ext, - [ENDP_INIT_HDR_METADATA_MASK] = &ipa_reg_endp_init_hdr_metadata_mask, - [ENDP_INIT_MODE] = &ipa_reg_endp_init_mode, - [ENDP_INIT_AGGR] = &ipa_reg_endp_init_aggr, - [ENDP_INIT_HOL_BLOCK_EN] = &ipa_reg_endp_init_hol_block_en, - [ENDP_INIT_HOL_BLOCK_TIMER] = &ipa_reg_endp_init_hol_block_timer, - [ENDP_INIT_DEAGGR] = &ipa_reg_endp_init_deaggr, - [ENDP_INIT_RSRC_GRP] = &ipa_reg_endp_init_rsrc_grp, - [ENDP_INIT_SEQ] = &ipa_reg_endp_init_seq, - [ENDP_STATUS] = &ipa_reg_endp_status, - [ENDP_FILTER_ROUTER_HSH_CFG] = &ipa_reg_endp_filter_router_hsh_cfg, - [IPA_IRQ_STTS] = &ipa_reg_ipa_irq_stts, - [IPA_IRQ_EN] = &ipa_reg_ipa_irq_en, - [IPA_IRQ_CLR] = &ipa_reg_ipa_irq_clr, - [IPA_IRQ_UC] = &ipa_reg_ipa_irq_uc, - [IRQ_SUSPEND_INFO] = &ipa_reg_irq_suspend_info, - [IRQ_SUSPEND_EN] = &ipa_reg_irq_suspend_en, - [IRQ_SUSPEND_CLR] = &ipa_reg_irq_suspend_clr, -}; - -const struct ipa_regs ipa_regs_v4_11 = { - .reg_count = ARRAY_SIZE(ipa_reg_array), - .reg = ipa_reg_array, +REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr, + 0x00004038 + 0x1000 * GSI_EE_AP, 0x0004); + +static const struct reg *reg_array[] = { + [COMP_CFG] = ®_comp_cfg, + [CLKON_CFG] = ®_clkon_cfg, + [ROUTE] = ®_route, + [SHARED_MEM_SIZE] = ®_shared_mem_size, + [QSB_MAX_WRITES] = ®_qsb_max_writes, + [QSB_MAX_READS] = ®_qsb_max_reads, + [FILT_ROUT_HASH_EN] = ®_filt_rout_hash_en, + [FILT_ROUT_HASH_FLUSH] = ®_filt_rout_hash_flush, + [STATE_AGGR_ACTIVE] = ®_state_aggr_active, + [LOCAL_PKT_PROC_CNTXT] = ®_local_pkt_proc_cntxt, + [AGGR_FORCE_CLOSE] = ®_aggr_force_close, + [IPA_TX_CFG] = ®_ipa_tx_cfg, + [FLAVOR_0] = ®_flavor_0, + [IDLE_INDICATION_CFG] = ®_idle_indication_cfg, + [QTIME_TIMESTAMP_CFG] = ®_qtime_timestamp_cfg, + [TIMERS_XO_CLK_DIV_CFG] = ®_timers_xo_clk_div_cfg, + [TIMERS_PULSE_GRAN_CFG] = ®_timers_pulse_gran_cfg, + [SRC_RSRC_GRP_01_RSRC_TYPE] = ®_src_rsrc_grp_01_rsrc_type, + [SRC_RSRC_GRP_23_RSRC_TYPE] = ®_src_rsrc_grp_23_rsrc_type, + [DST_RSRC_GRP_01_RSRC_TYPE] = ®_dst_rsrc_grp_01_rsrc_type, + [DST_RSRC_GRP_23_RSRC_TYPE] = ®_dst_rsrc_grp_23_rsrc_type, + [ENDP_INIT_CFG] = ®_endp_init_cfg, + [ENDP_INIT_NAT] = ®_endp_init_nat, + [ENDP_INIT_HDR] = ®_endp_init_hdr, + [ENDP_INIT_HDR_EXT] = ®_endp_init_hdr_ext, + [ENDP_INIT_HDR_METADATA_MASK] = ®_endp_init_hdr_metadata_mask, + [ENDP_INIT_MODE] = ®_endp_init_mode, + [ENDP_INIT_AGGR] = ®_endp_init_aggr, + [ENDP_INIT_HOL_BLOCK_EN] = ®_endp_init_hol_block_en, + [ENDP_INIT_HOL_BLOCK_TIMER] = ®_endp_init_hol_block_timer, + [ENDP_INIT_DEAGGR] = ®_endp_init_deaggr, + [ENDP_INIT_RSRC_GRP] = ®_endp_init_rsrc_grp, + [ENDP_INIT_SEQ] = ®_endp_init_seq, + [ENDP_STATUS] = ®_endp_status, + [ENDP_FILTER_ROUTER_HSH_CFG] = ®_endp_filter_router_hsh_cfg, + [IPA_IRQ_STTS] = ®_ipa_irq_stts, + [IPA_IRQ_EN] = ®_ipa_irq_en, + [IPA_IRQ_CLR] = ®_ipa_irq_clr, + [IPA_IRQ_UC] = ®_ipa_irq_uc, + [IRQ_SUSPEND_INFO] = ®_irq_suspend_info, + [IRQ_SUSPEND_EN] = ®_irq_suspend_en, + [IRQ_SUSPEND_CLR] = ®_irq_suspend_clr, +}; + +const struct regs ipa_regs_v4_11 = { + .reg_count = ARRAY_SIZE(reg_array), + .reg = reg_array, }; diff --git a/drivers/net/ipa/reg/ipa_reg-v4.2.c b/drivers/net/ipa/reg/ipa_reg-v4.2.c index f8e78e1907c8..bb7cf488144d 100644 --- a/drivers/net/ipa/reg/ipa_reg-v4.2.c +++ b/drivers/net/ipa/reg/ipa_reg-v4.2.c @@ -7,7 +7,7 @@ #include "../ipa.h" #include "../ipa_reg.h" -static const u32 ipa_reg_comp_cfg_fmask[] = { +static const u32 reg_comp_cfg_fmask[] = { /* Bit 0 reserved */ [GSI_SNOC_BYPASS_DIS] = BIT(1), [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2), @@ -29,9 +29,9 @@ static const u32 ipa_reg_comp_cfg_fmask[] = { /* Bits 21-31 reserved */ }; -IPA_REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c); +REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c); -static const u32 ipa_reg_clkon_cfg_fmask[] = { +static const u32 reg_clkon_cfg_fmask[] = { [CLKON_RX] = BIT(0), [CLKON_PROC] = BIT(1), [TX_WRAPPER] = BIT(2), @@ -65,9 +65,9 @@ static const u32 ipa_reg_clkon_cfg_fmask[] = { /* Bits 30-31 reserved */ }; -IPA_REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044); +REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044); -static const u32 ipa_reg_route_fmask[] = { +static const u32 reg_route_fmask[] = { [ROUTE_DIS] = BIT(0), [ROUTE_DEF_PIPE] = GENMASK(5, 1), [ROUTE_DEF_HDR_TABLE] = BIT(6), @@ -78,24 +78,24 @@ static const u32 ipa_reg_route_fmask[] = { /* Bits 25-31 reserved */ }; -IPA_REG_FIELDS(ROUTE, route, 0x00000048); +REG_FIELDS(ROUTE, route, 0x00000048); -static const u32 ipa_reg_shared_mem_size_fmask[] = { +static const u32 reg_shared_mem_size_fmask[] = { [MEM_SIZE] = GENMASK(15, 0), [MEM_BADDR] = GENMASK(31, 16), }; -IPA_REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054); +REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054); -static const u32 ipa_reg_qsb_max_writes_fmask[] = { +static const u32 reg_qsb_max_writes_fmask[] = { [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0), [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4), /* Bits 8-31 reserved */ }; -IPA_REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074); +REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074); -static const u32 ipa_reg_qsb_max_reads_fmask[] = { +static const u32 reg_qsb_max_reads_fmask[] = { [GEN_QMB_0_MAX_READS] = GENMASK(3, 0), [GEN_QMB_1_MAX_READS] = GENMASK(7, 4), /* Bits 8-15 reserved */ @@ -103,9 +103,9 @@ static const u32 ipa_reg_qsb_max_reads_fmask[] = { [GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24), }; -IPA_REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078); +REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078); -static const u32 ipa_reg_filt_rout_hash_en_fmask[] = { +static const u32 reg_filt_rout_hash_en_fmask[] = { [IPV6_ROUTER_HASH] = BIT(0), /* Bits 1-3 reserved */ [IPV6_FILTER_HASH] = BIT(4), @@ -116,9 +116,9 @@ static const u32 ipa_reg_filt_rout_hash_en_fmask[] = { /* Bits 13-31 reserved */ }; -IPA_REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x0000148); +REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x0000148); -static const u32 ipa_reg_filt_rout_hash_flush_fmask[] = { +static const u32 reg_filt_rout_hash_flush_fmask[] = { [IPV6_ROUTER_HASH] = BIT(0), /* Bits 1-3 reserved */ [IPV6_FILTER_HASH] = BIT(4), @@ -129,33 +129,33 @@ static const u32 ipa_reg_filt_rout_hash_flush_fmask[] = { /* Bits 13-31 reserved */ }; -IPA_REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c); +REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c); /* Valid bits defined by ipa->available */ -IPA_REG(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4); +REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4, 0x0004); -IPA_REG(IPA_BCR, ipa_bcr, 0x000001d0); +REG(IPA_BCR, ipa_bcr, 0x000001d0); -static const u32 ipa_reg_local_pkt_proc_cntxt_fmask[] = { +static const u32 reg_local_pkt_proc_cntxt_fmask[] = { [IPA_BASE_ADDR] = GENMASK(16, 0), /* Bits 17-31 reserved */ }; /* Offset must be a multiple of 8 */ -IPA_REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8); +REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8); /* Valid bits defined by ipa->available */ -IPA_REG(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec); +REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004); -static const u32 ipa_reg_counter_cfg_fmask[] = { +static const u32 reg_counter_cfg_fmask[] = { /* Bits 0-3 reserved */ [AGGR_GRANULARITY] = GENMASK(8, 4), /* Bits 9-31 reserved */ }; -IPA_REG_FIELDS(COUNTER_CFG, counter_cfg, 0x000001f0); +REG_FIELDS(COUNTER_CFG, counter_cfg, 0x000001f0); -static const u32 ipa_reg_ipa_tx_cfg_fmask[] = { +static const u32 reg_ipa_tx_cfg_fmask[] = { /* Bits 0-1 reserved */ [PREFETCH_ALMOST_EMPTY_SIZE_TX0] = GENMASK(5, 2), [DMAW_SCND_OUTSD_PRED_THRESHOLD] = GENMASK(9, 6), @@ -169,9 +169,9 @@ static const u32 ipa_reg_ipa_tx_cfg_fmask[] = { /* Bits 20-31 reserved */ }; -IPA_REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc); +REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc); -static const u32 ipa_reg_flavor_0_fmask[] = { +static const u32 reg_flavor_0_fmask[] = { [MAX_PIPES] = GENMASK(3, 0), /* Bits 4-7 reserved */ [MAX_CONS_PIPES] = GENMASK(12, 8), @@ -182,17 +182,17 @@ static const u32 ipa_reg_flavor_0_fmask[] = { /* Bits 28-31 reserved */ }; -IPA_REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210); +REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210); -static const u32 ipa_reg_idle_indication_cfg_fmask[] = { +static const u32 reg_idle_indication_cfg_fmask[] = { [ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0), [CONST_NON_IDLE_ENABLE] = BIT(16), /* Bits 17-31 reserved */ }; -IPA_REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000240); +REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000240); -static const u32 ipa_reg_src_rsrc_grp_01_rsrc_type_fmask[] = { +static const u32 reg_src_rsrc_grp_01_rsrc_type_fmask[] = { [X_MIN_LIM] = GENMASK(5, 0), /* Bits 6-7 reserved */ [X_MAX_LIM] = GENMASK(13, 8), @@ -203,10 +203,10 @@ static const u32 ipa_reg_src_rsrc_grp_01_rsrc_type_fmask[] = { /* Bits 30-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type, - 0x00000400, 0x0020); +REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type, + 0x00000400, 0x0020); -static const u32 ipa_reg_src_rsrc_grp_23_rsrc_type_fmask[] = { +static const u32 reg_src_rsrc_grp_23_rsrc_type_fmask[] = { [X_MIN_LIM] = GENMASK(5, 0), /* Bits 6-7 reserved */ [X_MAX_LIM] = GENMASK(13, 8), @@ -217,10 +217,10 @@ static const u32 ipa_reg_src_rsrc_grp_23_rsrc_type_fmask[] = { /* Bits 30-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type, - 0x00000404, 0x0020); +REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type, + 0x00000404, 0x0020); -static const u32 ipa_reg_dst_rsrc_grp_01_rsrc_type_fmask[] = { +static const u32 reg_dst_rsrc_grp_01_rsrc_type_fmask[] = { [X_MIN_LIM] = GENMASK(5, 0), /* Bits 6-7 reserved */ [X_MAX_LIM] = GENMASK(13, 8), @@ -231,10 +231,10 @@ static const u32 ipa_reg_dst_rsrc_grp_01_rsrc_type_fmask[] = { /* Bits 30-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type, - 0x00000500, 0x0020); +REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type, + 0x00000500, 0x0020); -static const u32 ipa_reg_dst_rsrc_grp_23_rsrc_type_fmask[] = { +static const u32 reg_dst_rsrc_grp_23_rsrc_type_fmask[] = { [X_MIN_LIM] = GENMASK(5, 0), /* Bits 6-7 reserved */ [X_MAX_LIM] = GENMASK(13, 8), @@ -245,10 +245,10 @@ static const u32 ipa_reg_dst_rsrc_grp_23_rsrc_type_fmask[] = { /* Bits 30-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type, - 0x00000504, 0x0020); +REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type, + 0x00000504, 0x0020); -static const u32 ipa_reg_endp_init_cfg_fmask[] = { +static const u32 reg_endp_init_cfg_fmask[] = { [FRAG_OFFLOAD_EN] = BIT(0), [CS_OFFLOAD_EN] = GENMASK(2, 1), [CS_METADATA_HDR_OFFSET] = GENMASK(6, 3), @@ -257,16 +257,16 @@ static const u32 ipa_reg_endp_init_cfg_fmask[] = { /* Bits 9-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070); -static const u32 ipa_reg_endp_init_nat_fmask[] = { +static const u32 reg_endp_init_nat_fmask[] = { [NAT_EN] = GENMASK(1, 0), /* Bits 2-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070); -static const u32 ipa_reg_endp_init_hdr_fmask[] = { +static const u32 reg_endp_init_hdr_fmask[] = { [HDR_LEN] = GENMASK(5, 0), [HDR_OFST_METADATA_VALID] = BIT(6), [HDR_OFST_METADATA] = GENMASK(12, 7), @@ -279,9 +279,9 @@ static const u32 ipa_reg_endp_init_hdr_fmask[] = { /* Bits 29-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070); -static const u32 ipa_reg_endp_init_hdr_ext_fmask[] = { +static const u32 reg_endp_init_hdr_ext_fmask[] = { [HDR_ENDIANNESS] = BIT(0), [HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1), [HDR_TOTAL_LEN_OR_PAD] = BIT(2), @@ -291,12 +291,12 @@ static const u32 ipa_reg_endp_init_hdr_ext_fmask[] = { /* Bits 14-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070); -IPA_REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask, - 0x00000818, 0x0070); +REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask, + 0x00000818, 0x0070); -static const u32 ipa_reg_endp_init_mode_fmask[] = { +static const u32 reg_endp_init_mode_fmask[] = { [ENDP_MODE] = GENMASK(2, 0), /* Bit 3 reserved */ [DEST_PIPE_INDEX] = GENMASK(8, 4), @@ -308,9 +308,9 @@ static const u32 ipa_reg_endp_init_mode_fmask[] = { /* Bit 31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070); -static const u32 ipa_reg_endp_init_aggr_fmask[] = { +static const u32 reg_endp_init_aggr_fmask[] = { [AGGR_EN] = GENMASK(1, 0), [AGGR_TYPE] = GENMASK(4, 2), [BYTE_LIMIT] = GENMASK(9, 5), @@ -323,27 +323,27 @@ static const u32 ipa_reg_endp_init_aggr_fmask[] = { /* Bits 25-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070); -static const u32 ipa_reg_endp_init_hol_block_en_fmask[] = { +static const u32 reg_endp_init_hol_block_en_fmask[] = { [HOL_BLOCK_EN] = BIT(0), /* Bits 1-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en, - 0x0000082c, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en, + 0x0000082c, 0x0070); -static const u32 ipa_reg_endp_init_hol_block_timer_fmask[] = { +static const u32 reg_endp_init_hol_block_timer_fmask[] = { [TIMER_BASE_VALUE] = GENMASK(4, 0), /* Bits 5-7 reserved */ [TIMER_SCALE] = GENMASK(12, 8), /* Bits 9-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer, - 0x00000830, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer, + 0x00000830, 0x0070); -static const u32 ipa_reg_endp_init_deaggr_fmask[] = { +static const u32 reg_endp_init_deaggr_fmask[] = { [DEAGGR_HDR_LEN] = GENMASK(5, 0), [SYSPIPE_ERR_DETECTION] = BIT(6), [PACKET_OFFSET_VALID] = BIT(7), @@ -353,25 +353,24 @@ static const u32 ipa_reg_endp_init_deaggr_fmask[] = { [MAX_PACKET_LEN] = GENMASK(31, 16), }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070); -static const u32 ipa_reg_endp_init_rsrc_grp_fmask[] = { +static const u32 reg_endp_init_rsrc_grp_fmask[] = { [ENDP_RSRC_GRP] = BIT(0), /* Bits 1-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, - 0x00000838, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00000838, 0x0070); -static const u32 ipa_reg_endp_init_seq_fmask[] = { +static const u32 reg_endp_init_seq_fmask[] = { [SEQ_TYPE] = GENMASK(7, 0), [SEQ_REP_TYPE] = GENMASK(15, 8), /* Bits 16-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070); -static const u32 ipa_reg_endp_status_fmask[] = { +static const u32 reg_endp_status_fmask[] = { [STATUS_EN] = BIT(0), [STATUS_ENDP] = GENMASK(5, 1), /* Bits 6-7 reserved */ @@ -380,77 +379,80 @@ static const u32 ipa_reg_endp_status_fmask[] = { /* Bits 10-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070); +REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070); /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ -IPA_REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP); +REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP); /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ -IPA_REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP); +REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP); /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ -IPA_REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP); +REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP); -static const u32 ipa_reg_ipa_irq_uc_fmask[] = { +static const u32 reg_ipa_irq_uc_fmask[] = { [UC_INTR] = BIT(0), /* Bits 1-31 reserved */ }; -IPA_REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000301c + 0x1000 * GSI_EE_AP); +REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000301c + 0x1000 * GSI_EE_AP); /* Valid bits defined by ipa->available */ -IPA_REG(IRQ_SUSPEND_INFO, irq_suspend_info, 0x00003030 + 0x1000 * GSI_EE_AP); +REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info, + 0x00003030 + 0x1000 * GSI_EE_AP, 0x0004); /* Valid bits defined by ipa->available */ -IPA_REG(IRQ_SUSPEND_EN, irq_suspend_en, 0x00003034 + 0x1000 * GSI_EE_AP); +REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en, + 0x00003034 + 0x1000 * GSI_EE_AP, 0x0004); /* Valid bits defined by ipa->available */ -IPA_REG(IRQ_SUSPEND_CLR, irq_suspend_clr, 0x00003038 + 0x1000 * GSI_EE_AP); - -static const struct ipa_reg *ipa_reg_array[] = { - [COMP_CFG] = &ipa_reg_comp_cfg, - [CLKON_CFG] = &ipa_reg_clkon_cfg, - [ROUTE] = &ipa_reg_route, - [SHARED_MEM_SIZE] = &ipa_reg_shared_mem_size, - [QSB_MAX_WRITES] = &ipa_reg_qsb_max_writes, - [QSB_MAX_READS] = &ipa_reg_qsb_max_reads, - [FILT_ROUT_HASH_EN] = &ipa_reg_filt_rout_hash_en, - [FILT_ROUT_HASH_FLUSH] = &ipa_reg_filt_rout_hash_flush, - [STATE_AGGR_ACTIVE] = &ipa_reg_state_aggr_active, - [IPA_BCR] = &ipa_reg_ipa_bcr, - [LOCAL_PKT_PROC_CNTXT] = &ipa_reg_local_pkt_proc_cntxt, - [AGGR_FORCE_CLOSE] = &ipa_reg_aggr_force_close, - [COUNTER_CFG] = &ipa_reg_counter_cfg, - [IPA_TX_CFG] = &ipa_reg_ipa_tx_cfg, - [FLAVOR_0] = &ipa_reg_flavor_0, - [IDLE_INDICATION_CFG] = &ipa_reg_idle_indication_cfg, - [SRC_RSRC_GRP_01_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_01_rsrc_type, - [SRC_RSRC_GRP_23_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_23_rsrc_type, - [DST_RSRC_GRP_01_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_01_rsrc_type, - [DST_RSRC_GRP_23_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_23_rsrc_type, - [ENDP_INIT_CFG] = &ipa_reg_endp_init_cfg, - [ENDP_INIT_NAT] = &ipa_reg_endp_init_nat, - [ENDP_INIT_HDR] = &ipa_reg_endp_init_hdr, - [ENDP_INIT_HDR_EXT] = &ipa_reg_endp_init_hdr_ext, - [ENDP_INIT_HDR_METADATA_MASK] = &ipa_reg_endp_init_hdr_metadata_mask, - [ENDP_INIT_MODE] = &ipa_reg_endp_init_mode, - [ENDP_INIT_AGGR] = &ipa_reg_endp_init_aggr, - [ENDP_INIT_HOL_BLOCK_EN] = &ipa_reg_endp_init_hol_block_en, - [ENDP_INIT_HOL_BLOCK_TIMER] = &ipa_reg_endp_init_hol_block_timer, - [ENDP_INIT_DEAGGR] = &ipa_reg_endp_init_deaggr, - [ENDP_INIT_RSRC_GRP] = &ipa_reg_endp_init_rsrc_grp, - [ENDP_INIT_SEQ] = &ipa_reg_endp_init_seq, - [ENDP_STATUS] = &ipa_reg_endp_status, - [IPA_IRQ_STTS] = &ipa_reg_ipa_irq_stts, - [IPA_IRQ_EN] = &ipa_reg_ipa_irq_en, - [IPA_IRQ_CLR] = &ipa_reg_ipa_irq_clr, - [IPA_IRQ_UC] = &ipa_reg_ipa_irq_uc, - [IRQ_SUSPEND_INFO] = &ipa_reg_irq_suspend_info, - [IRQ_SUSPEND_EN] = &ipa_reg_irq_suspend_en, - [IRQ_SUSPEND_CLR] = &ipa_reg_irq_suspend_clr, -}; - -const struct ipa_regs ipa_regs_v4_2 = { - .reg_count = ARRAY_SIZE(ipa_reg_array), - .reg = ipa_reg_array, +REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr, + 0x00003038 + 0x1000 * GSI_EE_AP, 0x0004); + +static const struct reg *reg_array[] = { + [COMP_CFG] = ®_comp_cfg, + [CLKON_CFG] = ®_clkon_cfg, + [ROUTE] = ®_route, + [SHARED_MEM_SIZE] = ®_shared_mem_size, + [QSB_MAX_WRITES] = ®_qsb_max_writes, + [QSB_MAX_READS] = ®_qsb_max_reads, + [FILT_ROUT_HASH_EN] = ®_filt_rout_hash_en, + [FILT_ROUT_HASH_FLUSH] = ®_filt_rout_hash_flush, + [STATE_AGGR_ACTIVE] = ®_state_aggr_active, + [IPA_BCR] = ®_ipa_bcr, + [LOCAL_PKT_PROC_CNTXT] = ®_local_pkt_proc_cntxt, + [AGGR_FORCE_CLOSE] = ®_aggr_force_close, + [COUNTER_CFG] = ®_counter_cfg, + [IPA_TX_CFG] = ®_ipa_tx_cfg, + [FLAVOR_0] = ®_flavor_0, + [IDLE_INDICATION_CFG] = ®_idle_indication_cfg, + [SRC_RSRC_GRP_01_RSRC_TYPE] = ®_src_rsrc_grp_01_rsrc_type, + [SRC_RSRC_GRP_23_RSRC_TYPE] = ®_src_rsrc_grp_23_rsrc_type, + [DST_RSRC_GRP_01_RSRC_TYPE] = ®_dst_rsrc_grp_01_rsrc_type, + [DST_RSRC_GRP_23_RSRC_TYPE] = ®_dst_rsrc_grp_23_rsrc_type, + [ENDP_INIT_CFG] = ®_endp_init_cfg, + [ENDP_INIT_NAT] = ®_endp_init_nat, + [ENDP_INIT_HDR] = ®_endp_init_hdr, + [ENDP_INIT_HDR_EXT] = ®_endp_init_hdr_ext, + [ENDP_INIT_HDR_METADATA_MASK] = ®_endp_init_hdr_metadata_mask, + [ENDP_INIT_MODE] = ®_endp_init_mode, + [ENDP_INIT_AGGR] = ®_endp_init_aggr, + [ENDP_INIT_HOL_BLOCK_EN] = ®_endp_init_hol_block_en, + [ENDP_INIT_HOL_BLOCK_TIMER] = ®_endp_init_hol_block_timer, + [ENDP_INIT_DEAGGR] = ®_endp_init_deaggr, + [ENDP_INIT_RSRC_GRP] = ®_endp_init_rsrc_grp, + [ENDP_INIT_SEQ] = ®_endp_init_seq, + [ENDP_STATUS] = ®_endp_status, + [IPA_IRQ_STTS] = ®_ipa_irq_stts, + [IPA_IRQ_EN] = ®_ipa_irq_en, + [IPA_IRQ_CLR] = ®_ipa_irq_clr, + [IPA_IRQ_UC] = ®_ipa_irq_uc, + [IRQ_SUSPEND_INFO] = ®_irq_suspend_info, + [IRQ_SUSPEND_EN] = ®_irq_suspend_en, + [IRQ_SUSPEND_CLR] = ®_irq_suspend_clr, +}; + +const struct regs ipa_regs_v4_2 = { + .reg_count = ARRAY_SIZE(reg_array), + .reg = reg_array, }; diff --git a/drivers/net/ipa/reg/ipa_reg-v4.5.c b/drivers/net/ipa/reg/ipa_reg-v4.5.c index d32b805abb11..1c58f78851c2 100644 --- a/drivers/net/ipa/reg/ipa_reg-v4.5.c +++ b/drivers/net/ipa/reg/ipa_reg-v4.5.c @@ -7,7 +7,7 @@ #include "../ipa.h" #include "../ipa_reg.h" -static const u32 ipa_reg_comp_cfg_fmask[] = { +static const u32 reg_comp_cfg_fmask[] = { /* Bit 0 reserved */ [GSI_SNOC_BYPASS_DIS] = BIT(1), [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2), @@ -30,9 +30,9 @@ static const u32 ipa_reg_comp_cfg_fmask[] = { /* Bits 22-31 reserved */ }; -IPA_REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c); +REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c); -static const u32 ipa_reg_clkon_cfg_fmask[] = { +static const u32 reg_clkon_cfg_fmask[] = { [CLKON_RX] = BIT(0), [CLKON_PROC] = BIT(1), [TX_WRAPPER] = BIT(2), @@ -67,9 +67,9 @@ static const u32 ipa_reg_clkon_cfg_fmask[] = { /* Bit 31 reserved */ }; -IPA_REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044); +REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044); -static const u32 ipa_reg_route_fmask[] = { +static const u32 reg_route_fmask[] = { [ROUTE_DIS] = BIT(0), [ROUTE_DEF_PIPE] = GENMASK(5, 1), [ROUTE_DEF_HDR_TABLE] = BIT(6), @@ -80,24 +80,24 @@ static const u32 ipa_reg_route_fmask[] = { /* Bits 25-31 reserved */ }; -IPA_REG_FIELDS(ROUTE, route, 0x00000048); +REG_FIELDS(ROUTE, route, 0x00000048); -static const u32 ipa_reg_shared_mem_size_fmask[] = { +static const u32 reg_shared_mem_size_fmask[] = { [MEM_SIZE] = GENMASK(15, 0), [MEM_BADDR] = GENMASK(31, 16), }; -IPA_REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054); +REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054); -static const u32 ipa_reg_qsb_max_writes_fmask[] = { +static const u32 reg_qsb_max_writes_fmask[] = { [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0), [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4), /* Bits 8-31 reserved */ }; -IPA_REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074); +REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074); -static const u32 ipa_reg_qsb_max_reads_fmask[] = { +static const u32 reg_qsb_max_reads_fmask[] = { [GEN_QMB_0_MAX_READS] = GENMASK(3, 0), [GEN_QMB_1_MAX_READS] = GENMASK(7, 4), /* Bits 8-15 reserved */ @@ -105,9 +105,9 @@ static const u32 ipa_reg_qsb_max_reads_fmask[] = { [GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24), }; -IPA_REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078); +REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078); -static const u32 ipa_reg_filt_rout_hash_en_fmask[] = { +static const u32 reg_filt_rout_hash_en_fmask[] = { [IPV6_ROUTER_HASH] = BIT(0), /* Bits 1-3 reserved */ [IPV6_FILTER_HASH] = BIT(4), @@ -118,9 +118,9 @@ static const u32 ipa_reg_filt_rout_hash_en_fmask[] = { /* Bits 13-31 reserved */ }; -IPA_REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x0000148); +REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x0000148); -static const u32 ipa_reg_filt_rout_hash_flush_fmask[] = { +static const u32 reg_filt_rout_hash_flush_fmask[] = { [IPV6_ROUTER_HASH] = BIT(0), /* Bits 1-3 reserved */ [IPV6_FILTER_HASH] = BIT(4), @@ -131,23 +131,23 @@ static const u32 ipa_reg_filt_rout_hash_flush_fmask[] = { /* Bits 13-31 reserved */ }; -IPA_REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c); +REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c); /* Valid bits defined by ipa->available */ -IPA_REG(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4); +REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4, 0x0004); -static const u32 ipa_reg_local_pkt_proc_cntxt_fmask[] = { +static const u32 reg_local_pkt_proc_cntxt_fmask[] = { [IPA_BASE_ADDR] = GENMASK(17, 0), /* Bits 18-31 reserved */ }; /* Offset must be a multiple of 8 */ -IPA_REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8); +REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8); /* Valid bits defined by ipa->available */ -IPA_REG(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec); +REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004); -static const u32 ipa_reg_ipa_tx_cfg_fmask[] = { +static const u32 reg_ipa_tx_cfg_fmask[] = { /* Bits 0-1 reserved */ [PREFETCH_ALMOST_EMPTY_SIZE_TX0] = GENMASK(5, 2), [DMAW_SCND_OUTSD_PRED_THRESHOLD] = GENMASK(9, 6), @@ -159,9 +159,9 @@ static const u32 ipa_reg_ipa_tx_cfg_fmask[] = { /* Bits 18-31 reserved */ }; -IPA_REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc); +REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc); -static const u32 ipa_reg_flavor_0_fmask[] = { +static const u32 reg_flavor_0_fmask[] = { [MAX_PIPES] = GENMASK(3, 0), /* Bits 4-7 reserved */ [MAX_CONS_PIPES] = GENMASK(12, 8), @@ -172,17 +172,17 @@ static const u32 ipa_reg_flavor_0_fmask[] = { /* Bits 28-31 reserved */ }; -IPA_REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210); +REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210); -static const u32 ipa_reg_idle_indication_cfg_fmask[] = { +static const u32 reg_idle_indication_cfg_fmask[] = { [ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0), [CONST_NON_IDLE_ENABLE] = BIT(16), /* Bits 17-31 reserved */ }; -IPA_REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000240); +REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000240); -static const u32 ipa_reg_qtime_timestamp_cfg_fmask[] = { +static const u32 reg_qtime_timestamp_cfg_fmask[] = { [DPL_TIMESTAMP_LSB] = GENMASK(4, 0), /* Bits 5-6 reserved */ [DPL_TIMESTAMP_SEL] = BIT(7), @@ -192,25 +192,25 @@ static const u32 ipa_reg_qtime_timestamp_cfg_fmask[] = { /* Bits 21-31 reserved */ }; -IPA_REG_FIELDS(QTIME_TIMESTAMP_CFG, qtime_timestamp_cfg, 0x0000024c); +REG_FIELDS(QTIME_TIMESTAMP_CFG, qtime_timestamp_cfg, 0x0000024c); -static const u32 ipa_reg_timers_xo_clk_div_cfg_fmask[] = { +static const u32 reg_timers_xo_clk_div_cfg_fmask[] = { [DIV_VALUE] = GENMASK(8, 0), /* Bits 9-30 reserved */ [DIV_ENABLE] = BIT(31), }; -IPA_REG_FIELDS(TIMERS_XO_CLK_DIV_CFG, timers_xo_clk_div_cfg, 0x00000250); +REG_FIELDS(TIMERS_XO_CLK_DIV_CFG, timers_xo_clk_div_cfg, 0x00000250); -static const u32 ipa_reg_timers_pulse_gran_cfg_fmask[] = { +static const u32 reg_timers_pulse_gran_cfg_fmask[] = { [PULSE_GRAN_0] = GENMASK(2, 0), [PULSE_GRAN_1] = GENMASK(5, 3), [PULSE_GRAN_2] = GENMASK(8, 6), }; -IPA_REG_FIELDS(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x00000254); +REG_FIELDS(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x00000254); -static const u32 ipa_reg_src_rsrc_grp_01_rsrc_type_fmask[] = { +static const u32 reg_src_rsrc_grp_01_rsrc_type_fmask[] = { [X_MIN_LIM] = GENMASK(5, 0), /* Bits 6-7 reserved */ [X_MAX_LIM] = GENMASK(13, 8), @@ -221,10 +221,10 @@ static const u32 ipa_reg_src_rsrc_grp_01_rsrc_type_fmask[] = { /* Bits 30-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type, - 0x00000400, 0x0020); +REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type, + 0x00000400, 0x0020); -static const u32 ipa_reg_src_rsrc_grp_23_rsrc_type_fmask[] = { +static const u32 reg_src_rsrc_grp_23_rsrc_type_fmask[] = { [X_MIN_LIM] = GENMASK(5, 0), /* Bits 6-7 reserved */ [X_MAX_LIM] = GENMASK(13, 8), @@ -235,10 +235,10 @@ static const u32 ipa_reg_src_rsrc_grp_23_rsrc_type_fmask[] = { /* Bits 30-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type, - 0x00000404, 0x0020); +REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type, + 0x00000404, 0x0020); -static const u32 ipa_reg_src_rsrc_grp_45_rsrc_type_fmask[] = { +static const u32 reg_src_rsrc_grp_45_rsrc_type_fmask[] = { [X_MIN_LIM] = GENMASK(5, 0), /* Bits 6-7 reserved */ [X_MAX_LIM] = GENMASK(13, 8), @@ -249,10 +249,10 @@ static const u32 ipa_reg_src_rsrc_grp_45_rsrc_type_fmask[] = { /* Bits 30-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_45_RSRC_TYPE, src_rsrc_grp_45_rsrc_type, - 0x00000408, 0x0020); +REG_STRIDE_FIELDS(SRC_RSRC_GRP_45_RSRC_TYPE, src_rsrc_grp_45_rsrc_type, + 0x00000408, 0x0020); -static const u32 ipa_reg_dst_rsrc_grp_01_rsrc_type_fmask[] = { +static const u32 reg_dst_rsrc_grp_01_rsrc_type_fmask[] = { [X_MIN_LIM] = GENMASK(5, 0), /* Bits 6-7 reserved */ [X_MAX_LIM] = GENMASK(13, 8), @@ -263,10 +263,10 @@ static const u32 ipa_reg_dst_rsrc_grp_01_rsrc_type_fmask[] = { /* Bits 30-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type, - 0x00000500, 0x0020); +REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type, + 0x00000500, 0x0020); -static const u32 ipa_reg_dst_rsrc_grp_23_rsrc_type_fmask[] = { +static const u32 reg_dst_rsrc_grp_23_rsrc_type_fmask[] = { [X_MIN_LIM] = GENMASK(5, 0), /* Bits 6-7 reserved */ [X_MAX_LIM] = GENMASK(13, 8), @@ -277,10 +277,10 @@ static const u32 ipa_reg_dst_rsrc_grp_23_rsrc_type_fmask[] = { /* Bits 30-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type, - 0x00000504, 0x0020); +REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type, + 0x00000504, 0x0020); -static const u32 ipa_reg_dst_rsrc_grp_45_rsrc_type_fmask[] = { +static const u32 reg_dst_rsrc_grp_45_rsrc_type_fmask[] = { [X_MIN_LIM] = GENMASK(5, 0), /* Bits 6-7 reserved */ [X_MAX_LIM] = GENMASK(13, 8), @@ -291,10 +291,10 @@ static const u32 ipa_reg_dst_rsrc_grp_45_rsrc_type_fmask[] = { /* Bits 30-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_45_RSRC_TYPE, dst_rsrc_grp_45_rsrc_type, - 0x00000508, 0x0020); +REG_STRIDE_FIELDS(DST_RSRC_GRP_45_RSRC_TYPE, dst_rsrc_grp_45_rsrc_type, + 0x00000508, 0x0020); -static const u32 ipa_reg_endp_init_cfg_fmask[] = { +static const u32 reg_endp_init_cfg_fmask[] = { [FRAG_OFFLOAD_EN] = BIT(0), [CS_OFFLOAD_EN] = GENMASK(2, 1), [CS_METADATA_HDR_OFFSET] = GENMASK(6, 3), @@ -303,16 +303,16 @@ static const u32 ipa_reg_endp_init_cfg_fmask[] = { /* Bits 9-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070); -static const u32 ipa_reg_endp_init_nat_fmask[] = { +static const u32 reg_endp_init_nat_fmask[] = { [NAT_EN] = GENMASK(1, 0), /* Bits 2-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070); -static const u32 ipa_reg_endp_init_hdr_fmask[] = { +static const u32 reg_endp_init_hdr_fmask[] = { [HDR_LEN] = GENMASK(5, 0), [HDR_OFST_METADATA_VALID] = BIT(6), [HDR_OFST_METADATA] = GENMASK(12, 7), @@ -325,9 +325,9 @@ static const u32 ipa_reg_endp_init_hdr_fmask[] = { [HDR_OFST_METADATA_MSB] = GENMASK(31, 30), }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070); -static const u32 ipa_reg_endp_init_hdr_ext_fmask[] = { +static const u32 reg_endp_init_hdr_ext_fmask[] = { [HDR_ENDIANNESS] = BIT(0), [HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1), [HDR_TOTAL_LEN_OR_PAD] = BIT(2), @@ -341,12 +341,12 @@ static const u32 ipa_reg_endp_init_hdr_ext_fmask[] = { /* Bits 22-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070); -IPA_REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask, - 0x00000818, 0x0070); +REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask, + 0x00000818, 0x0070); -static const u32 ipa_reg_endp_init_mode_fmask[] = { +static const u32 reg_endp_init_mode_fmask[] = { [ENDP_MODE] = GENMASK(2, 0), [DCPH_ENABLE] = BIT(3), [DEST_PIPE_INDEX] = GENMASK(8, 4), @@ -357,9 +357,9 @@ static const u32 ipa_reg_endp_init_mode_fmask[] = { /* Bits 30-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070); -static const u32 ipa_reg_endp_init_aggr_fmask[] = { +static const u32 reg_endp_init_aggr_fmask[] = { [AGGR_EN] = GENMASK(1, 0), [AGGR_TYPE] = GENMASK(4, 2), [BYTE_LIMIT] = GENMASK(10, 5), @@ -374,27 +374,27 @@ static const u32 ipa_reg_endp_init_aggr_fmask[] = { /* Bits 28-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070); -static const u32 ipa_reg_endp_init_hol_block_en_fmask[] = { +static const u32 reg_endp_init_hol_block_en_fmask[] = { [HOL_BLOCK_EN] = BIT(0), /* Bits 1-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en, - 0x0000082c, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en, + 0x0000082c, 0x0070); -static const u32 ipa_reg_endp_init_hol_block_timer_fmask[] = { +static const u32 reg_endp_init_hol_block_timer_fmask[] = { [TIMER_LIMIT] = GENMASK(4, 0), /* Bits 5-7 reserved */ [TIMER_GRAN_SEL] = BIT(8), /* Bits 9-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer, - 0x00000830, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer, + 0x00000830, 0x0070); -static const u32 ipa_reg_endp_init_deaggr_fmask[] = { +static const u32 reg_endp_init_deaggr_fmask[] = { [DEAGGR_HDR_LEN] = GENMASK(5, 0), [SYSPIPE_ERR_DETECTION] = BIT(6), [PACKET_OFFSET_VALID] = BIT(7), @@ -404,24 +404,23 @@ static const u32 ipa_reg_endp_init_deaggr_fmask[] = { [MAX_PACKET_LEN] = GENMASK(31, 16), }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070); -static const u32 ipa_reg_endp_init_rsrc_grp_fmask[] = { +static const u32 reg_endp_init_rsrc_grp_fmask[] = { [ENDP_RSRC_GRP] = GENMASK(2, 0), /* Bits 3-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, - 0x00000838, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00000838, 0x0070); -static const u32 ipa_reg_endp_init_seq_fmask[] = { +static const u32 reg_endp_init_seq_fmask[] = { [SEQ_TYPE] = GENMASK(7, 0), /* Bits 8-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070); -static const u32 ipa_reg_endp_status_fmask[] = { +static const u32 reg_endp_status_fmask[] = { [STATUS_EN] = BIT(0), [STATUS_ENDP] = GENMASK(5, 1), /* Bits 6-8 reserved */ @@ -429,9 +428,9 @@ static const u32 ipa_reg_endp_status_fmask[] = { /* Bits 10-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070); +REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070); -static const u32 ipa_reg_endp_filter_router_hsh_cfg_fmask[] = { +static const u32 reg_endp_filter_router_hsh_cfg_fmask[] = { [FILTER_HASH_MSK_SRC_ID] = BIT(0), [FILTER_HASH_MSK_SRC_IP] = BIT(1), [FILTER_HASH_MSK_DST_IP] = BIT(2), @@ -452,82 +451,85 @@ static const u32 ipa_reg_endp_filter_router_hsh_cfg_fmask[] = { /* Bits 23-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg, - 0x0000085c, 0x0070); +REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg, + 0x0000085c, 0x0070); /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ -IPA_REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP); +REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP); /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ -IPA_REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP); +REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP); /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ -IPA_REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP); +REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP); -static const u32 ipa_reg_ipa_irq_uc_fmask[] = { +static const u32 reg_ipa_irq_uc_fmask[] = { [UC_INTR] = BIT(0), /* Bits 1-31 reserved */ }; -IPA_REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000301c + 0x1000 * GSI_EE_AP); +REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000301c + 0x1000 * GSI_EE_AP); /* Valid bits defined by ipa->available */ -IPA_REG(IRQ_SUSPEND_INFO, irq_suspend_info, 0x00003030 + 0x1000 * GSI_EE_AP); +REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info, + 0x00003030 + 0x1000 * GSI_EE_AP, 0x0004); /* Valid bits defined by ipa->available */ -IPA_REG(IRQ_SUSPEND_EN, irq_suspend_en, 0x00003034 + 0x1000 * GSI_EE_AP); +REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en, + 0x00003034 + 0x1000 * GSI_EE_AP, 0x0004); /* Valid bits defined by ipa->available */ -IPA_REG(IRQ_SUSPEND_CLR, irq_suspend_clr, 0x00003038 + 0x1000 * GSI_EE_AP); - -static const struct ipa_reg *ipa_reg_array[] = { - [COMP_CFG] = &ipa_reg_comp_cfg, - [CLKON_CFG] = &ipa_reg_clkon_cfg, - [ROUTE] = &ipa_reg_route, - [SHARED_MEM_SIZE] = &ipa_reg_shared_mem_size, - [QSB_MAX_WRITES] = &ipa_reg_qsb_max_writes, - [QSB_MAX_READS] = &ipa_reg_qsb_max_reads, - [FILT_ROUT_HASH_EN] = &ipa_reg_filt_rout_hash_en, - [FILT_ROUT_HASH_FLUSH] = &ipa_reg_filt_rout_hash_flush, - [STATE_AGGR_ACTIVE] = &ipa_reg_state_aggr_active, - [LOCAL_PKT_PROC_CNTXT] = &ipa_reg_local_pkt_proc_cntxt, - [AGGR_FORCE_CLOSE] = &ipa_reg_aggr_force_close, - [IPA_TX_CFG] = &ipa_reg_ipa_tx_cfg, - [FLAVOR_0] = &ipa_reg_flavor_0, - [IDLE_INDICATION_CFG] = &ipa_reg_idle_indication_cfg, - [QTIME_TIMESTAMP_CFG] = &ipa_reg_qtime_timestamp_cfg, - [TIMERS_XO_CLK_DIV_CFG] = &ipa_reg_timers_xo_clk_div_cfg, - [TIMERS_PULSE_GRAN_CFG] = &ipa_reg_timers_pulse_gran_cfg, - [SRC_RSRC_GRP_01_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_01_rsrc_type, - [SRC_RSRC_GRP_23_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_23_rsrc_type, - [SRC_RSRC_GRP_45_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_45_rsrc_type, - [DST_RSRC_GRP_01_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_01_rsrc_type, - [DST_RSRC_GRP_23_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_23_rsrc_type, - [DST_RSRC_GRP_45_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_45_rsrc_type, - [ENDP_INIT_CFG] = &ipa_reg_endp_init_cfg, - [ENDP_INIT_NAT] = &ipa_reg_endp_init_nat, - [ENDP_INIT_HDR] = &ipa_reg_endp_init_hdr, - [ENDP_INIT_HDR_EXT] = &ipa_reg_endp_init_hdr_ext, - [ENDP_INIT_HDR_METADATA_MASK] = &ipa_reg_endp_init_hdr_metadata_mask, - [ENDP_INIT_MODE] = &ipa_reg_endp_init_mode, - [ENDP_INIT_AGGR] = &ipa_reg_endp_init_aggr, - [ENDP_INIT_HOL_BLOCK_EN] = &ipa_reg_endp_init_hol_block_en, - [ENDP_INIT_HOL_BLOCK_TIMER] = &ipa_reg_endp_init_hol_block_timer, - [ENDP_INIT_DEAGGR] = &ipa_reg_endp_init_deaggr, - [ENDP_INIT_RSRC_GRP] = &ipa_reg_endp_init_rsrc_grp, - [ENDP_INIT_SEQ] = &ipa_reg_endp_init_seq, - [ENDP_STATUS] = &ipa_reg_endp_status, - [ENDP_FILTER_ROUTER_HSH_CFG] = &ipa_reg_endp_filter_router_hsh_cfg, - [IPA_IRQ_STTS] = &ipa_reg_ipa_irq_stts, - [IPA_IRQ_EN] = &ipa_reg_ipa_irq_en, - [IPA_IRQ_CLR] = &ipa_reg_ipa_irq_clr, - [IPA_IRQ_UC] = &ipa_reg_ipa_irq_uc, - [IRQ_SUSPEND_INFO] = &ipa_reg_irq_suspend_info, - [IRQ_SUSPEND_EN] = &ipa_reg_irq_suspend_en, - [IRQ_SUSPEND_CLR] = &ipa_reg_irq_suspend_clr, -}; - -const struct ipa_regs ipa_regs_v4_5 = { - .reg_count = ARRAY_SIZE(ipa_reg_array), - .reg = ipa_reg_array, +REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr, + 0x00003038 + 0x1000 * GSI_EE_AP, 0x0004); + +static const struct reg *reg_array[] = { + [COMP_CFG] = ®_comp_cfg, + [CLKON_CFG] = ®_clkon_cfg, + [ROUTE] = ®_route, + [SHARED_MEM_SIZE] = ®_shared_mem_size, + [QSB_MAX_WRITES] = ®_qsb_max_writes, + [QSB_MAX_READS] = ®_qsb_max_reads, + [FILT_ROUT_HASH_EN] = ®_filt_rout_hash_en, + [FILT_ROUT_HASH_FLUSH] = ®_filt_rout_hash_flush, + [STATE_AGGR_ACTIVE] = ®_state_aggr_active, + [LOCAL_PKT_PROC_CNTXT] = ®_local_pkt_proc_cntxt, + [AGGR_FORCE_CLOSE] = ®_aggr_force_close, + [IPA_TX_CFG] = ®_ipa_tx_cfg, + [FLAVOR_0] = ®_flavor_0, + [IDLE_INDICATION_CFG] = ®_idle_indication_cfg, + [QTIME_TIMESTAMP_CFG] = ®_qtime_timestamp_cfg, + [TIMERS_XO_CLK_DIV_CFG] = ®_timers_xo_clk_div_cfg, + [TIMERS_PULSE_GRAN_CFG] = ®_timers_pulse_gran_cfg, + [SRC_RSRC_GRP_01_RSRC_TYPE] = ®_src_rsrc_grp_01_rsrc_type, + [SRC_RSRC_GRP_23_RSRC_TYPE] = ®_src_rsrc_grp_23_rsrc_type, + [SRC_RSRC_GRP_45_RSRC_TYPE] = ®_src_rsrc_grp_45_rsrc_type, + [DST_RSRC_GRP_01_RSRC_TYPE] = ®_dst_rsrc_grp_01_rsrc_type, + [DST_RSRC_GRP_23_RSRC_TYPE] = ®_dst_rsrc_grp_23_rsrc_type, + [DST_RSRC_GRP_45_RSRC_TYPE] = ®_dst_rsrc_grp_45_rsrc_type, + [ENDP_INIT_CFG] = ®_endp_init_cfg, + [ENDP_INIT_NAT] = ®_endp_init_nat, + [ENDP_INIT_HDR] = ®_endp_init_hdr, + [ENDP_INIT_HDR_EXT] = ®_endp_init_hdr_ext, + [ENDP_INIT_HDR_METADATA_MASK] = ®_endp_init_hdr_metadata_mask, + [ENDP_INIT_MODE] = ®_endp_init_mode, + [ENDP_INIT_AGGR] = ®_endp_init_aggr, + [ENDP_INIT_HOL_BLOCK_EN] = ®_endp_init_hol_block_en, + [ENDP_INIT_HOL_BLOCK_TIMER] = ®_endp_init_hol_block_timer, + [ENDP_INIT_DEAGGR] = ®_endp_init_deaggr, + [ENDP_INIT_RSRC_GRP] = ®_endp_init_rsrc_grp, + [ENDP_INIT_SEQ] = ®_endp_init_seq, + [ENDP_STATUS] = ®_endp_status, + [ENDP_FILTER_ROUTER_HSH_CFG] = ®_endp_filter_router_hsh_cfg, + [IPA_IRQ_STTS] = ®_ipa_irq_stts, + [IPA_IRQ_EN] = ®_ipa_irq_en, + [IPA_IRQ_CLR] = ®_ipa_irq_clr, + [IPA_IRQ_UC] = ®_ipa_irq_uc, + [IRQ_SUSPEND_INFO] = ®_irq_suspend_info, + [IRQ_SUSPEND_EN] = ®_irq_suspend_en, + [IRQ_SUSPEND_CLR] = ®_irq_suspend_clr, +}; + +const struct regs ipa_regs_v4_5 = { + .reg_count = ARRAY_SIZE(reg_array), + .reg = reg_array, }; diff --git a/drivers/net/ipa/reg/ipa_reg-v4.7.c b/drivers/net/ipa/reg/ipa_reg-v4.7.c new file mode 100644 index 000000000000..731824fce1d4 --- /dev/null +++ b/drivers/net/ipa/reg/ipa_reg-v4.7.c @@ -0,0 +1,506 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* Copyright (C) 2022 Linaro Ltd. */ + +#include <linux/types.h> + +#include "../ipa.h" +#include "../ipa_reg.h" + +static const u32 reg_comp_cfg_fmask[] = { + [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0), + [GSI_SNOC_BYPASS_DIS] = BIT(1), + [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2), + [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3), + /* Bit 4 reserved */ + [IPA_QMB_SELECT_CONS_EN] = BIT(5), + [IPA_QMB_SELECT_PROD_EN] = BIT(6), + [GSI_MULTI_INORDER_RD_DIS] = BIT(7), + [GSI_MULTI_INORDER_WR_DIS] = BIT(8), + [GEN_QMB_0_MULTI_INORDER_RD_DIS] = BIT(9), + [GEN_QMB_1_MULTI_INORDER_RD_DIS] = BIT(10), + [GEN_QMB_0_MULTI_INORDER_WR_DIS] = BIT(11), + [GEN_QMB_1_MULTI_INORDER_WR_DIS] = BIT(12), + [GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS] = BIT(13), + [GSI_SNOC_CNOC_LOOP_PROT_DISABLE] = BIT(14), + [GSI_MULTI_AXI_MASTERS_DIS] = BIT(15), + [IPA_QMB_SELECT_GLOBAL_EN] = BIT(16), + [ATOMIC_FETCHER_ARB_LOCK_DIS] = GENMASK(20, 17), + [FULL_FLUSH_WAIT_RS_CLOSURE_EN] = BIT(21), + /* Bits 22-31 reserved */ +}; + +REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c); + +static const u32 reg_clkon_cfg_fmask[] = { + [CLKON_RX] = BIT(0), + [CLKON_PROC] = BIT(1), + [TX_WRAPPER] = BIT(2), + [CLKON_MISC] = BIT(3), + [RAM_ARB] = BIT(4), + [FTCH_HPS] = BIT(5), + [FTCH_DPS] = BIT(6), + [CLKON_HPS] = BIT(7), + [CLKON_DPS] = BIT(8), + [RX_HPS_CMDQS] = BIT(9), + [HPS_DPS_CMDQS] = BIT(10), + [DPS_TX_CMDQS] = BIT(11), + [RSRC_MNGR] = BIT(12), + [CTX_HANDLER] = BIT(13), + [ACK_MNGR] = BIT(14), + [D_DCPH] = BIT(15), + [H_DCPH] = BIT(16), + [CLKON_DCMP] = BIT(17), + [NTF_TX_CMDQS] = BIT(18), + [CLKON_TX_0] = BIT(19), + [CLKON_TX_1] = BIT(20), + [CLKON_FNR] = BIT(21), + [QSB2AXI_CMDQ_L] = BIT(22), + [AGGR_WRAPPER] = BIT(23), + [RAM_SLAVEWAY] = BIT(24), + [CLKON_QMB] = BIT(25), + [WEIGHT_ARB] = BIT(26), + [GSI_IF] = BIT(27), + [CLKON_GLOBAL] = BIT(28), + [GLOBAL_2X_CLK] = BIT(29), + [DPL_FIFO] = BIT(30), + [DRBIP] = BIT(31), +}; + +REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044); + +static const u32 reg_route_fmask[] = { + [ROUTE_DIS] = BIT(0), + [ROUTE_DEF_PIPE] = GENMASK(5, 1), + [ROUTE_DEF_HDR_TABLE] = BIT(6), + [ROUTE_DEF_HDR_OFST] = GENMASK(16, 7), + [ROUTE_FRAG_DEF_PIPE] = GENMASK(21, 17), + /* Bits 22-23 reserved */ + [ROUTE_DEF_RETAIN_HDR] = BIT(24), + /* Bits 25-31 reserved */ +}; + +REG_FIELDS(ROUTE, route, 0x00000048); + +static const u32 reg_shared_mem_size_fmask[] = { + [MEM_SIZE] = GENMASK(15, 0), + [MEM_BADDR] = GENMASK(31, 16), +}; + +REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054); + +static const u32 reg_qsb_max_writes_fmask[] = { + [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0), + [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4), + /* Bits 8-31 reserved */ +}; + +REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074); + +static const u32 reg_qsb_max_reads_fmask[] = { + [GEN_QMB_0_MAX_READS] = GENMASK(3, 0), + [GEN_QMB_1_MAX_READS] = GENMASK(7, 4), + /* Bits 8-15 reserved */ + [GEN_QMB_0_MAX_READS_BEATS] = GENMASK(23, 16), + [GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24), +}; + +REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078); + +static const u32 reg_filt_rout_hash_en_fmask[] = { + [IPV6_ROUTER_HASH] = BIT(0), + /* Bits 1-3 reserved */ + [IPV6_FILTER_HASH] = BIT(4), + /* Bits 5-7 reserved */ + [IPV4_ROUTER_HASH] = BIT(8), + /* Bits 9-11 reserved */ + [IPV4_FILTER_HASH] = BIT(12), + /* Bits 13-31 reserved */ +}; + +REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x0000148); + +static const u32 reg_filt_rout_hash_flush_fmask[] = { + [IPV6_ROUTER_HASH] = BIT(0), + /* Bits 1-3 reserved */ + [IPV6_FILTER_HASH] = BIT(4), + /* Bits 5-7 reserved */ + [IPV4_ROUTER_HASH] = BIT(8), + /* Bits 9-11 reserved */ + [IPV4_FILTER_HASH] = BIT(12), + /* Bits 13-31 reserved */ +}; + +REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c); + +/* Valid bits defined by ipa->available */ +REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4, 0x0004); + +static const u32 reg_local_pkt_proc_cntxt_fmask[] = { + [IPA_BASE_ADDR] = GENMASK(17, 0), + /* Bits 18-31 reserved */ +}; + +/* Offset must be a multiple of 8 */ +REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8); + +/* Valid bits defined by ipa->available */ +REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004); + +static const u32 reg_ipa_tx_cfg_fmask[] = { + /* Bits 0-1 reserved */ + [PREFETCH_ALMOST_EMPTY_SIZE_TX0] = GENMASK(5, 2), + [DMAW_SCND_OUTSD_PRED_THRESHOLD] = GENMASK(9, 6), + [DMAW_SCND_OUTSD_PRED_EN] = BIT(10), + [DMAW_MAX_BEATS_256_DIS] = BIT(11), + [PA_MASK_EN] = BIT(12), + [PREFETCH_ALMOST_EMPTY_SIZE_TX1] = GENMASK(16, 13), + [DUAL_TX_ENABLE] = BIT(17), + [SSPND_PA_NO_START_STATE] = BIT(18), + /* Bits 19-31 reserved */ +}; + +REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc); + +static const u32 reg_flavor_0_fmask[] = { + [MAX_PIPES] = GENMASK(3, 0), + /* Bits 4-7 reserved */ + [MAX_CONS_PIPES] = GENMASK(12, 8), + /* Bits 13-15 reserved */ + [MAX_PROD_PIPES] = GENMASK(20, 16), + /* Bits 21-23 reserved */ + [PROD_LOWEST] = GENMASK(27, 24), + /* Bits 28-31 reserved */ +}; + +REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210); + +static const u32 reg_idle_indication_cfg_fmask[] = { + [ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0), + [CONST_NON_IDLE_ENABLE] = BIT(16), + /* Bits 17-31 reserved */ +}; + +REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000240); + +static const u32 reg_qtime_timestamp_cfg_fmask[] = { + [DPL_TIMESTAMP_LSB] = GENMASK(4, 0), + /* Bits 5-6 reserved */ + [DPL_TIMESTAMP_SEL] = BIT(7), + [TAG_TIMESTAMP_LSB] = GENMASK(12, 8), + /* Bits 13-15 reserved */ + [NAT_TIMESTAMP_LSB] = GENMASK(20, 16), + /* Bits 21-31 reserved */ +}; + +REG_FIELDS(QTIME_TIMESTAMP_CFG, qtime_timestamp_cfg, 0x0000024c); + +static const u32 reg_timers_xo_clk_div_cfg_fmask[] = { + [DIV_VALUE] = GENMASK(8, 0), + /* Bits 9-30 reserved */ + [DIV_ENABLE] = BIT(31), +}; + +REG_FIELDS(TIMERS_XO_CLK_DIV_CFG, timers_xo_clk_div_cfg, 0x00000250); + +static const u32 reg_timers_pulse_gran_cfg_fmask[] = { + [PULSE_GRAN_0] = GENMASK(2, 0), + [PULSE_GRAN_1] = GENMASK(5, 3), + [PULSE_GRAN_2] = GENMASK(8, 6), +}; + +REG_FIELDS(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x00000254); + +static const u32 reg_src_rsrc_grp_01_rsrc_type_fmask[] = { + [X_MIN_LIM] = GENMASK(5, 0), + /* Bits 6-7 reserved */ + [X_MAX_LIM] = GENMASK(13, 8), + /* Bits 14-15 reserved */ + [Y_MIN_LIM] = GENMASK(21, 16), + /* Bits 22-23 reserved */ + [Y_MAX_LIM] = GENMASK(29, 24), + /* Bits 30-31 reserved */ +}; + +REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type, + 0x00000400, 0x0020); + +static const u32 reg_src_rsrc_grp_23_rsrc_type_fmask[] = { + [X_MIN_LIM] = GENMASK(5, 0), + /* Bits 6-7 reserved */ + [X_MAX_LIM] = GENMASK(13, 8), + /* Bits 14-15 reserved */ + [Y_MIN_LIM] = GENMASK(21, 16), + /* Bits 22-23 reserved */ + [Y_MAX_LIM] = GENMASK(29, 24), + /* Bits 30-31 reserved */ +}; + +REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type, + 0x00000404, 0x0020); + +static const u32 reg_dst_rsrc_grp_01_rsrc_type_fmask[] = { + [X_MIN_LIM] = GENMASK(5, 0), + /* Bits 6-7 reserved */ + [X_MAX_LIM] = GENMASK(13, 8), + /* Bits 14-15 reserved */ + [Y_MIN_LIM] = GENMASK(21, 16), + /* Bits 22-23 reserved */ + [Y_MAX_LIM] = GENMASK(29, 24), + /* Bits 30-31 reserved */ +}; + +REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type, + 0x00000500, 0x0020); + +static const u32 reg_dst_rsrc_grp_23_rsrc_type_fmask[] = { + [X_MIN_LIM] = GENMASK(5, 0), + /* Bits 6-7 reserved */ + [X_MAX_LIM] = GENMASK(13, 8), + /* Bits 14-15 reserved */ + [Y_MIN_LIM] = GENMASK(21, 16), + /* Bits 22-23 reserved */ + [Y_MAX_LIM] = GENMASK(29, 24), + /* Bits 30-31 reserved */ +}; + +REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type, + 0x00000504, 0x0020); + +static const u32 reg_endp_init_cfg_fmask[] = { + [FRAG_OFFLOAD_EN] = BIT(0), + [CS_OFFLOAD_EN] = GENMASK(2, 1), + [CS_METADATA_HDR_OFFSET] = GENMASK(6, 3), + /* Bit 7 reserved */ + [CS_GEN_QMB_MASTER_SEL] = BIT(8), + /* Bits 9-31 reserved */ +}; + +REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070); + +static const u32 reg_endp_init_nat_fmask[] = { + [NAT_EN] = GENMASK(1, 0), + /* Bits 2-31 reserved */ +}; + +REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070); + +static const u32 reg_endp_init_hdr_fmask[] = { + [HDR_LEN] = GENMASK(5, 0), + [HDR_OFST_METADATA_VALID] = BIT(6), + [HDR_OFST_METADATA] = GENMASK(12, 7), + [HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13), + [HDR_OFST_PKT_SIZE_VALID] = BIT(19), + [HDR_OFST_PKT_SIZE] = GENMASK(25, 20), + [HDR_A5_MUX] = BIT(26), + [HDR_LEN_INC_DEAGG_HDR] = BIT(27), + [HDR_LEN_MSB] = GENMASK(29, 28), + [HDR_OFST_METADATA_MSB] = GENMASK(31, 30), +}; + +REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070); + +static const u32 reg_endp_init_hdr_ext_fmask[] = { + [HDR_ENDIANNESS] = BIT(0), + [HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1), + [HDR_TOTAL_LEN_OR_PAD] = BIT(2), + [HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3), + [HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4), + [HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10), + /* Bits 14-15 reserved */ + [HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB] = GENMASK(17, 16), + [HDR_OFST_PKT_SIZE_MSB] = GENMASK(19, 18), + [HDR_ADDITIONAL_CONST_LEN_MSB] = GENMASK(21, 20), + /* Bits 22-31 reserved */ +}; + +REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070); + +REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask, + 0x00000818, 0x0070); + +static const u32 reg_endp_init_mode_fmask[] = { + [ENDP_MODE] = GENMASK(2, 0), + [DCPH_ENABLE] = BIT(3), + [DEST_PIPE_INDEX] = GENMASK(8, 4), + /* Bits 9-11 reserved */ + [BYTE_THRESHOLD] = GENMASK(27, 12), + [PIPE_REPLICATION_EN] = BIT(28), + [PAD_EN] = BIT(29), + /* Bits 30-31 reserved */ +}; + +REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070); + +static const u32 reg_endp_init_aggr_fmask[] = { + [AGGR_EN] = GENMASK(1, 0), + [AGGR_TYPE] = GENMASK(4, 2), + [BYTE_LIMIT] = GENMASK(10, 5), + /* Bit 11 reserved */ + [TIME_LIMIT] = GENMASK(16, 12), + [PKT_LIMIT] = GENMASK(22, 17), + [SW_EOF_ACTIVE] = BIT(23), + [FORCE_CLOSE] = BIT(24), + /* Bit 25 reserved */ + [HARD_BYTE_LIMIT_EN] = BIT(26), + [AGGR_GRAN_SEL] = BIT(27), + /* Bits 28-31 reserved */ +}; + +REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070); + +static const u32 reg_endp_init_hol_block_en_fmask[] = { + [HOL_BLOCK_EN] = BIT(0), + /* Bits 1-31 reserved */ +}; + +REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en, + 0x0000082c, 0x0070); + +static const u32 reg_endp_init_hol_block_timer_fmask[] = { + [TIMER_LIMIT] = GENMASK(4, 0), + /* Bits 5-7 reserved */ + [TIMER_GRAN_SEL] = BIT(8), + /* Bits 9-31 reserved */ +}; + +REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer, + 0x00000830, 0x0070); + +static const u32 reg_endp_init_deaggr_fmask[] = { + [DEAGGR_HDR_LEN] = GENMASK(5, 0), + [SYSPIPE_ERR_DETECTION] = BIT(6), + [PACKET_OFFSET_VALID] = BIT(7), + [PACKET_OFFSET_LOCATION] = GENMASK(13, 8), + [IGNORE_MIN_PKT_ERR] = BIT(14), + /* Bit 15 reserved */ + [MAX_PACKET_LEN] = GENMASK(31, 16), +}; + +REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070); + +static const u32 reg_endp_init_rsrc_grp_fmask[] = { + [ENDP_RSRC_GRP] = BIT(0), + /* Bits 1-31 reserved */ +}; + +REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00000838, 0x0070); + +static const u32 reg_endp_init_seq_fmask[] = { + [SEQ_TYPE] = GENMASK(7, 0), + /* Bits 8-31 reserved */ +}; + +REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070); + +static const u32 reg_endp_status_fmask[] = { + [STATUS_EN] = BIT(0), + [STATUS_ENDP] = GENMASK(5, 1), + /* Bits 6-8 reserved */ + [STATUS_PKT_SUPPRESS] = BIT(9), + /* Bits 10-31 reserved */ +}; + +REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070); + +static const u32 reg_endp_filter_router_hsh_cfg_fmask[] = { + [FILTER_HASH_MSK_SRC_ID] = BIT(0), + [FILTER_HASH_MSK_SRC_IP] = BIT(1), + [FILTER_HASH_MSK_DST_IP] = BIT(2), + [FILTER_HASH_MSK_SRC_PORT] = BIT(3), + [FILTER_HASH_MSK_DST_PORT] = BIT(4), + [FILTER_HASH_MSK_PROTOCOL] = BIT(5), + [FILTER_HASH_MSK_METADATA] = BIT(6), + [FILTER_HASH_MSK_ALL] = GENMASK(6, 0), + /* Bits 7-15 reserved */ + [ROUTER_HASH_MSK_SRC_ID] = BIT(16), + [ROUTER_HASH_MSK_SRC_IP] = BIT(17), + [ROUTER_HASH_MSK_DST_IP] = BIT(18), + [ROUTER_HASH_MSK_SRC_PORT] = BIT(19), + [ROUTER_HASH_MSK_DST_PORT] = BIT(20), + [ROUTER_HASH_MSK_PROTOCOL] = BIT(21), + [ROUTER_HASH_MSK_METADATA] = BIT(22), + [ROUTER_HASH_MSK_ALL] = GENMASK(22, 16), + /* Bits 23-31 reserved */ +}; + +REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg, + 0x0000085c, 0x0070); + +/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ +REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP); + +/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ +REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP); + +/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ +REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP); + +static const u32 reg_ipa_irq_uc_fmask[] = { + [UC_INTR] = BIT(0), + /* Bits 1-31 reserved */ +}; + +REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000301c + 0x1000 * GSI_EE_AP); + +/* Valid bits defined by ipa->available */ +REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info, + 0x00003030 + 0x1000 * GSI_EE_AP, 0x0004); + +/* Valid bits defined by ipa->available */ +REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en, + 0x00003034 + 0x1000 * GSI_EE_AP, 0x0004); + +/* Valid bits defined by ipa->available */ +REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr, + 0x00003038 + 0x1000 * GSI_EE_AP, 0x0004); + +static const struct reg *reg_array[] = { + [COMP_CFG] = ®_comp_cfg, + [CLKON_CFG] = ®_clkon_cfg, + [ROUTE] = ®_route, + [SHARED_MEM_SIZE] = ®_shared_mem_size, + [QSB_MAX_WRITES] = ®_qsb_max_writes, + [QSB_MAX_READS] = ®_qsb_max_reads, + [FILT_ROUT_HASH_EN] = ®_filt_rout_hash_en, + [FILT_ROUT_HASH_FLUSH] = ®_filt_rout_hash_flush, + [STATE_AGGR_ACTIVE] = ®_state_aggr_active, + [LOCAL_PKT_PROC_CNTXT] = ®_local_pkt_proc_cntxt, + [AGGR_FORCE_CLOSE] = ®_aggr_force_close, + [IPA_TX_CFG] = ®_ipa_tx_cfg, + [FLAVOR_0] = ®_flavor_0, + [IDLE_INDICATION_CFG] = ®_idle_indication_cfg, + [QTIME_TIMESTAMP_CFG] = ®_qtime_timestamp_cfg, + [TIMERS_XO_CLK_DIV_CFG] = ®_timers_xo_clk_div_cfg, + [TIMERS_PULSE_GRAN_CFG] = ®_timers_pulse_gran_cfg, + [SRC_RSRC_GRP_01_RSRC_TYPE] = ®_src_rsrc_grp_01_rsrc_type, + [SRC_RSRC_GRP_23_RSRC_TYPE] = ®_src_rsrc_grp_23_rsrc_type, + [DST_RSRC_GRP_01_RSRC_TYPE] = ®_dst_rsrc_grp_01_rsrc_type, + [DST_RSRC_GRP_23_RSRC_TYPE] = ®_dst_rsrc_grp_23_rsrc_type, + [ENDP_INIT_CFG] = ®_endp_init_cfg, + [ENDP_INIT_NAT] = ®_endp_init_nat, + [ENDP_INIT_HDR] = ®_endp_init_hdr, + [ENDP_INIT_HDR_EXT] = ®_endp_init_hdr_ext, + [ENDP_INIT_HDR_METADATA_MASK] = ®_endp_init_hdr_metadata_mask, + [ENDP_INIT_MODE] = ®_endp_init_mode, + [ENDP_INIT_AGGR] = ®_endp_init_aggr, + [ENDP_INIT_HOL_BLOCK_EN] = ®_endp_init_hol_block_en, + [ENDP_INIT_HOL_BLOCK_TIMER] = ®_endp_init_hol_block_timer, + [ENDP_INIT_DEAGGR] = ®_endp_init_deaggr, + [ENDP_INIT_RSRC_GRP] = ®_endp_init_rsrc_grp, + [ENDP_INIT_SEQ] = ®_endp_init_seq, + [ENDP_STATUS] = ®_endp_status, + [ENDP_FILTER_ROUTER_HSH_CFG] = ®_endp_filter_router_hsh_cfg, + [IPA_IRQ_STTS] = ®_ipa_irq_stts, + [IPA_IRQ_EN] = ®_ipa_irq_en, + [IPA_IRQ_CLR] = ®_ipa_irq_clr, + [IPA_IRQ_UC] = ®_ipa_irq_uc, + [IRQ_SUSPEND_INFO] = ®_irq_suspend_info, + [IRQ_SUSPEND_EN] = ®_irq_suspend_en, + [IRQ_SUSPEND_CLR] = ®_irq_suspend_clr, +}; + +const struct regs ipa_regs_v4_7 = { + .reg_count = ARRAY_SIZE(reg_array), + .reg = reg_array, +}; diff --git a/drivers/net/ipa/reg/ipa_reg-v4.9.c b/drivers/net/ipa/reg/ipa_reg-v4.9.c index eabbc5451937..01f87b5290e0 100644 --- a/drivers/net/ipa/reg/ipa_reg-v4.9.c +++ b/drivers/net/ipa/reg/ipa_reg-v4.9.c @@ -7,7 +7,7 @@ #include "../ipa.h" #include "../ipa_reg.h" -static const u32 ipa_reg_comp_cfg_fmask[] = { +static const u32 reg_comp_cfg_fmask[] = { [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0), [GSI_SNOC_BYPASS_DIS] = BIT(1), [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2), @@ -35,9 +35,9 @@ static const u32 ipa_reg_comp_cfg_fmask[] = { [GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31), }; -IPA_REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c); +REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c); -static const u32 ipa_reg_clkon_cfg_fmask[] = { +static const u32 reg_clkon_cfg_fmask[] = { [CLKON_RX] = BIT(0), [CLKON_PROC] = BIT(1), [TX_WRAPPER] = BIT(2), @@ -72,9 +72,9 @@ static const u32 ipa_reg_clkon_cfg_fmask[] = { [DRBIP] = BIT(31), }; -IPA_REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044); +REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044); -static const u32 ipa_reg_route_fmask[] = { +static const u32 reg_route_fmask[] = { [ROUTE_DIS] = BIT(0), [ROUTE_DEF_PIPE] = GENMASK(5, 1), [ROUTE_DEF_HDR_TABLE] = BIT(6), @@ -85,24 +85,24 @@ static const u32 ipa_reg_route_fmask[] = { /* Bits 25-31 reserved */ }; -IPA_REG_FIELDS(ROUTE, route, 0x00000048); +REG_FIELDS(ROUTE, route, 0x00000048); -static const u32 ipa_reg_shared_mem_size_fmask[] = { +static const u32 reg_shared_mem_size_fmask[] = { [MEM_SIZE] = GENMASK(15, 0), [MEM_BADDR] = GENMASK(31, 16), }; -IPA_REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054); +REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054); -static const u32 ipa_reg_qsb_max_writes_fmask[] = { +static const u32 reg_qsb_max_writes_fmask[] = { [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0), [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4), /* Bits 8-31 reserved */ }; -IPA_REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074); +REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074); -static const u32 ipa_reg_qsb_max_reads_fmask[] = { +static const u32 reg_qsb_max_reads_fmask[] = { [GEN_QMB_0_MAX_READS] = GENMASK(3, 0), [GEN_QMB_1_MAX_READS] = GENMASK(7, 4), /* Bits 8-15 reserved */ @@ -110,9 +110,9 @@ static const u32 ipa_reg_qsb_max_reads_fmask[] = { [GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24), }; -IPA_REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078); +REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078); -static const u32 ipa_reg_filt_rout_hash_en_fmask[] = { +static const u32 reg_filt_rout_hash_en_fmask[] = { [IPV6_ROUTER_HASH] = BIT(0), /* Bits 1-3 reserved */ [IPV6_FILTER_HASH] = BIT(4), @@ -123,9 +123,9 @@ static const u32 ipa_reg_filt_rout_hash_en_fmask[] = { /* Bits 13-31 reserved */ }; -IPA_REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x0000148); +REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x0000148); -static const u32 ipa_reg_filt_rout_hash_flush_fmask[] = { +static const u32 reg_filt_rout_hash_flush_fmask[] = { [IPV6_ROUTER_HASH] = BIT(0), /* Bits 1-3 reserved */ [IPV6_FILTER_HASH] = BIT(4), @@ -136,23 +136,23 @@ static const u32 ipa_reg_filt_rout_hash_flush_fmask[] = { /* Bits 13-31 reserved */ }; -IPA_REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c); +REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c); /* Valid bits defined by ipa->available */ -IPA_REG(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4); +REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4, 0x0004); -static const u32 ipa_reg_local_pkt_proc_cntxt_fmask[] = { +static const u32 reg_local_pkt_proc_cntxt_fmask[] = { [IPA_BASE_ADDR] = GENMASK(17, 0), /* Bits 18-31 reserved */ }; /* Offset must be a multiple of 8 */ -IPA_REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8); +REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8); /* Valid bits defined by ipa->available */ -IPA_REG(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec); +REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004); -static const u32 ipa_reg_ipa_tx_cfg_fmask[] = { +static const u32 reg_ipa_tx_cfg_fmask[] = { /* Bits 0-1 reserved */ [PREFETCH_ALMOST_EMPTY_SIZE_TX0] = GENMASK(5, 2), [DMAW_SCND_OUTSD_PRED_THRESHOLD] = GENMASK(9, 6), @@ -165,9 +165,9 @@ static const u32 ipa_reg_ipa_tx_cfg_fmask[] = { /* Bits 19-31 reserved */ }; -IPA_REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc); +REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc); -static const u32 ipa_reg_flavor_0_fmask[] = { +static const u32 reg_flavor_0_fmask[] = { [MAX_PIPES] = GENMASK(3, 0), /* Bits 4-7 reserved */ [MAX_CONS_PIPES] = GENMASK(12, 8), @@ -178,17 +178,17 @@ static const u32 ipa_reg_flavor_0_fmask[] = { /* Bits 28-31 reserved */ }; -IPA_REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210); +REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210); -static const u32 ipa_reg_idle_indication_cfg_fmask[] = { +static const u32 reg_idle_indication_cfg_fmask[] = { [ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0), [CONST_NON_IDLE_ENABLE] = BIT(16), /* Bits 17-31 reserved */ }; -IPA_REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000240); +REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000240); -static const u32 ipa_reg_qtime_timestamp_cfg_fmask[] = { +static const u32 reg_qtime_timestamp_cfg_fmask[] = { [DPL_TIMESTAMP_LSB] = GENMASK(4, 0), /* Bits 5-6 reserved */ [DPL_TIMESTAMP_SEL] = BIT(7), @@ -198,25 +198,25 @@ static const u32 ipa_reg_qtime_timestamp_cfg_fmask[] = { /* Bits 21-31 reserved */ }; -IPA_REG_FIELDS(QTIME_TIMESTAMP_CFG, qtime_timestamp_cfg, 0x0000024c); +REG_FIELDS(QTIME_TIMESTAMP_CFG, qtime_timestamp_cfg, 0x0000024c); -static const u32 ipa_reg_timers_xo_clk_div_cfg_fmask[] = { +static const u32 reg_timers_xo_clk_div_cfg_fmask[] = { [DIV_VALUE] = GENMASK(8, 0), /* Bits 9-30 reserved */ [DIV_ENABLE] = BIT(31), }; -IPA_REG_FIELDS(TIMERS_XO_CLK_DIV_CFG, timers_xo_clk_div_cfg, 0x00000250); +REG_FIELDS(TIMERS_XO_CLK_DIV_CFG, timers_xo_clk_div_cfg, 0x00000250); -static const u32 ipa_reg_timers_pulse_gran_cfg_fmask[] = { +static const u32 reg_timers_pulse_gran_cfg_fmask[] = { [PULSE_GRAN_0] = GENMASK(2, 0), [PULSE_GRAN_1] = GENMASK(5, 3), [PULSE_GRAN_2] = GENMASK(8, 6), }; -IPA_REG_FIELDS(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x00000254); +REG_FIELDS(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x00000254); -static const u32 ipa_reg_src_rsrc_grp_01_rsrc_type_fmask[] = { +static const u32 reg_src_rsrc_grp_01_rsrc_type_fmask[] = { [X_MIN_LIM] = GENMASK(5, 0), /* Bits 6-7 reserved */ [X_MAX_LIM] = GENMASK(13, 8), @@ -227,10 +227,10 @@ static const u32 ipa_reg_src_rsrc_grp_01_rsrc_type_fmask[] = { /* Bits 30-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type, - 0x00000400, 0x0020); +REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type, + 0x00000400, 0x0020); -static const u32 ipa_reg_src_rsrc_grp_23_rsrc_type_fmask[] = { +static const u32 reg_src_rsrc_grp_23_rsrc_type_fmask[] = { [X_MIN_LIM] = GENMASK(5, 0), /* Bits 6-7 reserved */ [X_MAX_LIM] = GENMASK(13, 8), @@ -241,10 +241,10 @@ static const u32 ipa_reg_src_rsrc_grp_23_rsrc_type_fmask[] = { /* Bits 30-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type, - 0x00000404, 0x0020); +REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type, + 0x00000404, 0x0020); -static const u32 ipa_reg_dst_rsrc_grp_01_rsrc_type_fmask[] = { +static const u32 reg_dst_rsrc_grp_01_rsrc_type_fmask[] = { [X_MIN_LIM] = GENMASK(5, 0), /* Bits 6-7 reserved */ [X_MAX_LIM] = GENMASK(13, 8), @@ -255,10 +255,10 @@ static const u32 ipa_reg_dst_rsrc_grp_01_rsrc_type_fmask[] = { /* Bits 30-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type, - 0x00000500, 0x0020); +REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type, + 0x00000500, 0x0020); -static const u32 ipa_reg_dst_rsrc_grp_23_rsrc_type_fmask[] = { +static const u32 reg_dst_rsrc_grp_23_rsrc_type_fmask[] = { [X_MIN_LIM] = GENMASK(5, 0), /* Bits 6-7 reserved */ [X_MAX_LIM] = GENMASK(13, 8), @@ -269,10 +269,10 @@ static const u32 ipa_reg_dst_rsrc_grp_23_rsrc_type_fmask[] = { /* Bits 30-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type, - 0x00000504, 0x0020); +REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type, + 0x00000504, 0x0020); -static const u32 ipa_reg_endp_init_cfg_fmask[] = { +static const u32 reg_endp_init_cfg_fmask[] = { [FRAG_OFFLOAD_EN] = BIT(0), [CS_OFFLOAD_EN] = GENMASK(2, 1), [CS_METADATA_HDR_OFFSET] = GENMASK(6, 3), @@ -281,16 +281,16 @@ static const u32 ipa_reg_endp_init_cfg_fmask[] = { /* Bits 9-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070); -static const u32 ipa_reg_endp_init_nat_fmask[] = { +static const u32 reg_endp_init_nat_fmask[] = { [NAT_EN] = GENMASK(1, 0), /* Bits 2-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070); -static const u32 ipa_reg_endp_init_hdr_fmask[] = { +static const u32 reg_endp_init_hdr_fmask[] = { [HDR_LEN] = GENMASK(5, 0), [HDR_OFST_METADATA_VALID] = BIT(6), [HDR_OFST_METADATA] = GENMASK(12, 7), @@ -302,9 +302,9 @@ static const u32 ipa_reg_endp_init_hdr_fmask[] = { [HDR_OFST_METADATA_MSB] = GENMASK(31, 30), }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070); -static const u32 ipa_reg_endp_init_hdr_ext_fmask[] = { +static const u32 reg_endp_init_hdr_ext_fmask[] = { [HDR_ENDIANNESS] = BIT(0), [HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1), [HDR_TOTAL_LEN_OR_PAD] = BIT(2), @@ -318,12 +318,12 @@ static const u32 ipa_reg_endp_init_hdr_ext_fmask[] = { /* Bits 22-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070); -IPA_REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask, - 0x00000818, 0x0070); +REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask, + 0x00000818, 0x0070); -static const u32 ipa_reg_endp_init_mode_fmask[] = { +static const u32 reg_endp_init_mode_fmask[] = { [ENDP_MODE] = GENMASK(2, 0), [DCPH_ENABLE] = BIT(3), [DEST_PIPE_INDEX] = GENMASK(8, 4), @@ -335,9 +335,9 @@ static const u32 ipa_reg_endp_init_mode_fmask[] = { /* Bit 31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070); -static const u32 ipa_reg_endp_init_aggr_fmask[] = { +static const u32 reg_endp_init_aggr_fmask[] = { [AGGR_EN] = GENMASK(1, 0), [AGGR_TYPE] = GENMASK(4, 2), [BYTE_LIMIT] = GENMASK(10, 5), @@ -352,27 +352,27 @@ static const u32 ipa_reg_endp_init_aggr_fmask[] = { /* Bits 28-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070); -static const u32 ipa_reg_endp_init_hol_block_en_fmask[] = { +static const u32 reg_endp_init_hol_block_en_fmask[] = { [HOL_BLOCK_EN] = BIT(0), /* Bits 1-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en, - 0x0000082c, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en, + 0x0000082c, 0x0070); -static const u32 ipa_reg_endp_init_hol_block_timer_fmask[] = { +static const u32 reg_endp_init_hol_block_timer_fmask[] = { [TIMER_LIMIT] = GENMASK(4, 0), /* Bits 5-7 reserved */ [TIMER_GRAN_SEL] = BIT(8), /* Bits 9-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer, - 0x00000830, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer, + 0x00000830, 0x0070); -static const u32 ipa_reg_endp_init_deaggr_fmask[] = { +static const u32 reg_endp_init_deaggr_fmask[] = { [DEAGGR_HDR_LEN] = GENMASK(5, 0), [SYSPIPE_ERR_DETECTION] = BIT(6), [PACKET_OFFSET_VALID] = BIT(7), @@ -382,24 +382,23 @@ static const u32 ipa_reg_endp_init_deaggr_fmask[] = { [MAX_PACKET_LEN] = GENMASK(31, 16), }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070); -static const u32 ipa_reg_endp_init_rsrc_grp_fmask[] = { +static const u32 reg_endp_init_rsrc_grp_fmask[] = { [ENDP_RSRC_GRP] = GENMASK(1, 0), /* Bits 2-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, - 0x00000838, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00000838, 0x0070); -static const u32 ipa_reg_endp_init_seq_fmask[] = { +static const u32 reg_endp_init_seq_fmask[] = { [SEQ_TYPE] = GENMASK(7, 0), /* Bits 8-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070); -static const u32 ipa_reg_endp_status_fmask[] = { +static const u32 reg_endp_status_fmask[] = { [STATUS_EN] = BIT(0), [STATUS_ENDP] = GENMASK(5, 1), /* Bits 6-8 reserved */ @@ -407,9 +406,9 @@ static const u32 ipa_reg_endp_status_fmask[] = { /* Bits 10-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070); +REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070); -static const u32 ipa_reg_endp_filter_router_hsh_cfg_fmask[] = { +static const u32 reg_endp_filter_router_hsh_cfg_fmask[] = { [FILTER_HASH_MSK_SRC_ID] = BIT(0), [FILTER_HASH_MSK_SRC_IP] = BIT(1), [FILTER_HASH_MSK_DST_IP] = BIT(2), @@ -430,80 +429,83 @@ static const u32 ipa_reg_endp_filter_router_hsh_cfg_fmask[] = { /* Bits 23-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg, - 0x0000085c, 0x0070); +REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg, + 0x0000085c, 0x0070); /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ -IPA_REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00004008 + 0x1000 * GSI_EE_AP); +REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00004008 + 0x1000 * GSI_EE_AP); /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ -IPA_REG(IPA_IRQ_EN, ipa_irq_en, 0x0000400c + 0x1000 * GSI_EE_AP); +REG(IPA_IRQ_EN, ipa_irq_en, 0x0000400c + 0x1000 * GSI_EE_AP); /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ -IPA_REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00004010 + 0x1000 * GSI_EE_AP); +REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00004010 + 0x1000 * GSI_EE_AP); -static const u32 ipa_reg_ipa_irq_uc_fmask[] = { +static const u32 reg_ipa_irq_uc_fmask[] = { [UC_INTR] = BIT(0), /* Bits 1-31 reserved */ }; -IPA_REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000401c + 0x1000 * GSI_EE_AP); +REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000401c + 0x1000 * GSI_EE_AP); /* Valid bits defined by ipa->available */ -IPA_REG(IRQ_SUSPEND_INFO, irq_suspend_info, 0x00004030 + 0x1000 * GSI_EE_AP); +REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info, + 0x00004030 + 0x1000 * GSI_EE_AP, 0x0004); /* Valid bits defined by ipa->available */ -IPA_REG(IRQ_SUSPEND_EN, irq_suspend_en, 0x00004034 + 0x1000 * GSI_EE_AP); +REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en, + 0x00004034 + 0x1000 * GSI_EE_AP, 0x0004); /* Valid bits defined by ipa->available */ -IPA_REG(IRQ_SUSPEND_CLR, irq_suspend_clr, 0x00004038 + 0x1000 * GSI_EE_AP); - -static const struct ipa_reg *ipa_reg_array[] = { - [COMP_CFG] = &ipa_reg_comp_cfg, - [CLKON_CFG] = &ipa_reg_clkon_cfg, - [ROUTE] = &ipa_reg_route, - [SHARED_MEM_SIZE] = &ipa_reg_shared_mem_size, - [QSB_MAX_WRITES] = &ipa_reg_qsb_max_writes, - [QSB_MAX_READS] = &ipa_reg_qsb_max_reads, - [FILT_ROUT_HASH_EN] = &ipa_reg_filt_rout_hash_en, - [FILT_ROUT_HASH_FLUSH] = &ipa_reg_filt_rout_hash_flush, - [STATE_AGGR_ACTIVE] = &ipa_reg_state_aggr_active, - [LOCAL_PKT_PROC_CNTXT] = &ipa_reg_local_pkt_proc_cntxt, - [AGGR_FORCE_CLOSE] = &ipa_reg_aggr_force_close, - [IPA_TX_CFG] = &ipa_reg_ipa_tx_cfg, - [FLAVOR_0] = &ipa_reg_flavor_0, - [IDLE_INDICATION_CFG] = &ipa_reg_idle_indication_cfg, - [QTIME_TIMESTAMP_CFG] = &ipa_reg_qtime_timestamp_cfg, - [TIMERS_XO_CLK_DIV_CFG] = &ipa_reg_timers_xo_clk_div_cfg, - [TIMERS_PULSE_GRAN_CFG] = &ipa_reg_timers_pulse_gran_cfg, - [SRC_RSRC_GRP_01_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_01_rsrc_type, - [SRC_RSRC_GRP_23_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_23_rsrc_type, - [DST_RSRC_GRP_01_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_01_rsrc_type, - [DST_RSRC_GRP_23_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_23_rsrc_type, - [ENDP_INIT_CFG] = &ipa_reg_endp_init_cfg, - [ENDP_INIT_NAT] = &ipa_reg_endp_init_nat, - [ENDP_INIT_HDR] = &ipa_reg_endp_init_hdr, - [ENDP_INIT_HDR_EXT] = &ipa_reg_endp_init_hdr_ext, - [ENDP_INIT_HDR_METADATA_MASK] = &ipa_reg_endp_init_hdr_metadata_mask, - [ENDP_INIT_MODE] = &ipa_reg_endp_init_mode, - [ENDP_INIT_AGGR] = &ipa_reg_endp_init_aggr, - [ENDP_INIT_HOL_BLOCK_EN] = &ipa_reg_endp_init_hol_block_en, - [ENDP_INIT_HOL_BLOCK_TIMER] = &ipa_reg_endp_init_hol_block_timer, - [ENDP_INIT_DEAGGR] = &ipa_reg_endp_init_deaggr, - [ENDP_INIT_RSRC_GRP] = &ipa_reg_endp_init_rsrc_grp, - [ENDP_INIT_SEQ] = &ipa_reg_endp_init_seq, - [ENDP_STATUS] = &ipa_reg_endp_status, - [ENDP_FILTER_ROUTER_HSH_CFG] = &ipa_reg_endp_filter_router_hsh_cfg, - [IPA_IRQ_STTS] = &ipa_reg_ipa_irq_stts, - [IPA_IRQ_EN] = &ipa_reg_ipa_irq_en, - [IPA_IRQ_CLR] = &ipa_reg_ipa_irq_clr, - [IPA_IRQ_UC] = &ipa_reg_ipa_irq_uc, - [IRQ_SUSPEND_INFO] = &ipa_reg_irq_suspend_info, - [IRQ_SUSPEND_EN] = &ipa_reg_irq_suspend_en, - [IRQ_SUSPEND_CLR] = &ipa_reg_irq_suspend_clr, -}; - -const struct ipa_regs ipa_regs_v4_9 = { - .reg_count = ARRAY_SIZE(ipa_reg_array), - .reg = ipa_reg_array, +REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr, + 0x00004038 + 0x1000 * GSI_EE_AP, 0x0004); + +static const struct reg *reg_array[] = { + [COMP_CFG] = ®_comp_cfg, + [CLKON_CFG] = ®_clkon_cfg, + [ROUTE] = ®_route, + [SHARED_MEM_SIZE] = ®_shared_mem_size, + [QSB_MAX_WRITES] = ®_qsb_max_writes, + [QSB_MAX_READS] = ®_qsb_max_reads, + [FILT_ROUT_HASH_EN] = ®_filt_rout_hash_en, + [FILT_ROUT_HASH_FLUSH] = ®_filt_rout_hash_flush, + [STATE_AGGR_ACTIVE] = ®_state_aggr_active, + [LOCAL_PKT_PROC_CNTXT] = ®_local_pkt_proc_cntxt, + [AGGR_FORCE_CLOSE] = ®_aggr_force_close, + [IPA_TX_CFG] = ®_ipa_tx_cfg, + [FLAVOR_0] = ®_flavor_0, + [IDLE_INDICATION_CFG] = ®_idle_indication_cfg, + [QTIME_TIMESTAMP_CFG] = ®_qtime_timestamp_cfg, + [TIMERS_XO_CLK_DIV_CFG] = ®_timers_xo_clk_div_cfg, + [TIMERS_PULSE_GRAN_CFG] = ®_timers_pulse_gran_cfg, + [SRC_RSRC_GRP_01_RSRC_TYPE] = ®_src_rsrc_grp_01_rsrc_type, + [SRC_RSRC_GRP_23_RSRC_TYPE] = ®_src_rsrc_grp_23_rsrc_type, + [DST_RSRC_GRP_01_RSRC_TYPE] = ®_dst_rsrc_grp_01_rsrc_type, + [DST_RSRC_GRP_23_RSRC_TYPE] = ®_dst_rsrc_grp_23_rsrc_type, + [ENDP_INIT_CFG] = ®_endp_init_cfg, + [ENDP_INIT_NAT] = ®_endp_init_nat, + [ENDP_INIT_HDR] = ®_endp_init_hdr, + [ENDP_INIT_HDR_EXT] = ®_endp_init_hdr_ext, + [ENDP_INIT_HDR_METADATA_MASK] = ®_endp_init_hdr_metadata_mask, + [ENDP_INIT_MODE] = ®_endp_init_mode, + [ENDP_INIT_AGGR] = ®_endp_init_aggr, + [ENDP_INIT_HOL_BLOCK_EN] = ®_endp_init_hol_block_en, + [ENDP_INIT_HOL_BLOCK_TIMER] = ®_endp_init_hol_block_timer, + [ENDP_INIT_DEAGGR] = ®_endp_init_deaggr, + [ENDP_INIT_RSRC_GRP] = ®_endp_init_rsrc_grp, + [ENDP_INIT_SEQ] = ®_endp_init_seq, + [ENDP_STATUS] = ®_endp_status, + [ENDP_FILTER_ROUTER_HSH_CFG] = ®_endp_filter_router_hsh_cfg, + [IPA_IRQ_STTS] = ®_ipa_irq_stts, + [IPA_IRQ_EN] = ®_ipa_irq_en, + [IPA_IRQ_CLR] = ®_ipa_irq_clr, + [IPA_IRQ_UC] = ®_ipa_irq_uc, + [IRQ_SUSPEND_INFO] = ®_irq_suspend_info, + [IRQ_SUSPEND_EN] = ®_irq_suspend_en, + [IRQ_SUSPEND_CLR] = ®_irq_suspend_clr, +}; + +const struct regs ipa_regs_v4_9 = { + .reg_count = ARRAY_SIZE(reg_array), + .reg = reg_array, }; |