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-rw-r--r--drivers/memory/brcmstb_dpfe.c3
-rw-r--r--drivers/memory/da8xx-ddrctl.c1
-rw-r--r--drivers/memory/fsl_ifc.c2
-rw-r--r--drivers/memory/jz4780-nemc.c1
-rw-r--r--drivers/memory/pl353-smc.c1
-rw-r--r--drivers/memory/renesas-rpc-if.c1
-rw-r--r--drivers/memory/samsung/exynos5422-dmc.c2
-rw-r--r--drivers/memory/stm32-fmc2-ebi.c2
-rw-r--r--drivers/memory/tegra/mc.c2
-rw-r--r--drivers/memory/tegra/tegra124.c2
-rw-r--r--drivers/memory/tegra/tegra186-emc.c136
-rw-r--r--drivers/memory/tegra/tegra186.c3
-rw-r--r--drivers/memory/tegra/tegra20.c3
-rw-r--r--drivers/memory/tegra/tegra210-emc-core.c4
-rw-r--r--drivers/memory/tegra/tegra234.c610
-rw-r--r--drivers/memory/tegra/tegra30-emc.c2
-rw-r--r--drivers/memory/tegra/tegra30.c2
17 files changed, 459 insertions, 318 deletions
diff --git a/drivers/memory/brcmstb_dpfe.c b/drivers/memory/brcmstb_dpfe.c
index 9339f80b21c5..a7ab3d377206 100644
--- a/drivers/memory/brcmstb_dpfe.c
+++ b/drivers/memory/brcmstb_dpfe.c
@@ -32,8 +32,7 @@
#include <linux/firmware.h>
#include <linux/io.h>
#include <linux/module.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
#include <linux/platform_device.h>
#define DRVNAME "brcmstb-dpfe"
diff --git a/drivers/memory/da8xx-ddrctl.c b/drivers/memory/da8xx-ddrctl.c
index 0ef8cc878b95..2bf34da85d22 100644
--- a/drivers/memory/da8xx-ddrctl.c
+++ b/drivers/memory/da8xx-ddrctl.c
@@ -10,7 +10,6 @@
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/io.h>
diff --git a/drivers/memory/fsl_ifc.c b/drivers/memory/fsl_ifc.c
index 9e8d8e9c5ad8..2509e5152036 100644
--- a/drivers/memory/fsl_ifc.c
+++ b/drivers/memory/fsl_ifc.c
@@ -15,7 +15,7 @@
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/of.h>
-#include <linux/of_device.h>
+#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/fsl_ifc.h>
#include <linux/irqdomain.h>
diff --git a/drivers/memory/jz4780-nemc.c b/drivers/memory/jz4780-nemc.c
index 555f7ac3b7dd..e5a93e7da15f 100644
--- a/drivers/memory/jz4780-nemc.c
+++ b/drivers/memory/jz4780-nemc.c
@@ -12,7 +12,6 @@
#include <linux/math64.h>
#include <linux/of.h>
#include <linux/of_address.h>
-#include <linux/of_device.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
diff --git a/drivers/memory/pl353-smc.c b/drivers/memory/pl353-smc.c
index d39ee7d06665..48540817e046 100644
--- a/drivers/memory/pl353-smc.c
+++ b/drivers/memory/pl353-smc.c
@@ -10,6 +10,7 @@
#include <linux/clk.h>
#include <linux/kernel.h>
#include <linux/module.h>
+#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/amba/bus.h>
diff --git a/drivers/memory/renesas-rpc-if.c b/drivers/memory/renesas-rpc-if.c
index 75fcba45ec1b..9695b2d3ae59 100644
--- a/drivers/memory/renesas-rpc-if.c
+++ b/drivers/memory/renesas-rpc-if.c
@@ -13,7 +13,6 @@
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <linux/regmap.h>
#include <linux/reset.h>
diff --git a/drivers/memory/samsung/exynos5422-dmc.c b/drivers/memory/samsung/exynos5422-dmc.c
index c491cd549644..6d019dbd721c 100644
--- a/drivers/memory/samsung/exynos5422-dmc.c
+++ b/drivers/memory/samsung/exynos5422-dmc.c
@@ -13,7 +13,7 @@
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
#include <linux/pm_opp.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
diff --git a/drivers/memory/stm32-fmc2-ebi.c b/drivers/memory/stm32-fmc2-ebi.c
index ffec26a99313..9015e8277dc8 100644
--- a/drivers/memory/stm32-fmc2-ebi.c
+++ b/drivers/memory/stm32-fmc2-ebi.c
@@ -7,8 +7,10 @@
#include <linux/clk.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
+#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/pinctrl/consumer.h>
+#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/reset.h>
diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c
index deb6e65b59af..67d6e70b4eab 100644
--- a/drivers/memory/tegra/mc.c
+++ b/drivers/memory/tegra/mc.c
@@ -11,7 +11,7 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/of_device.h>
+#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/sort.h>
diff --git a/drivers/memory/tegra/tegra124.c b/drivers/memory/tegra/tegra124.c
index d780a84241fe..470b7dbab2c2 100644
--- a/drivers/memory/tegra/tegra124.c
+++ b/drivers/memory/tegra/tegra124.c
@@ -4,7 +4,7 @@
*/
#include <linux/of.h>
-#include <linux/of_device.h>
+#include <linux/device.h>
#include <linux/slab.h>
#include <dt-bindings/memory/tegra124-mc.h>
diff --git a/drivers/memory/tegra/tegra186-emc.c b/drivers/memory/tegra/tegra186-emc.c
index 6ad8a4023dd7..4007f4e16d74 100644
--- a/drivers/memory/tegra/tegra186-emc.c
+++ b/drivers/memory/tegra/tegra186-emc.c
@@ -155,6 +155,73 @@ DEFINE_DEBUGFS_ATTRIBUTE(tegra186_emc_debug_max_rate_fops,
tegra186_emc_debug_max_rate_get,
tegra186_emc_debug_max_rate_set, "%llu\n");
+static int tegra186_emc_get_emc_dvfs_latency(struct tegra186_emc *emc)
+{
+ struct mrq_emc_dvfs_latency_response response;
+ struct tegra_bpmp_message msg;
+ unsigned int i;
+ int err;
+
+ memset(&msg, 0, sizeof(msg));
+ msg.mrq = MRQ_EMC_DVFS_LATENCY;
+ msg.tx.data = NULL;
+ msg.tx.size = 0;
+ msg.rx.data = &response;
+ msg.rx.size = sizeof(response);
+
+ err = tegra_bpmp_transfer(emc->bpmp, &msg);
+ if (err < 0) {
+ dev_err(emc->dev, "failed to EMC DVFS pairs: %d\n", err);
+ return err;
+ }
+ if (msg.rx.ret < 0) {
+ dev_err(emc->dev, "EMC DVFS MRQ failed: %d (BPMP error code)\n", msg.rx.ret);
+ return -EINVAL;
+ }
+
+ emc->debugfs.min_rate = ULONG_MAX;
+ emc->debugfs.max_rate = 0;
+
+ emc->num_dvfs = response.num_pairs;
+
+ emc->dvfs = devm_kmalloc_array(emc->dev, emc->num_dvfs, sizeof(*emc->dvfs), GFP_KERNEL);
+ if (!emc->dvfs)
+ return -ENOMEM;
+
+ dev_dbg(emc->dev, "%u DVFS pairs:\n", emc->num_dvfs);
+
+ for (i = 0; i < emc->num_dvfs; i++) {
+ emc->dvfs[i].rate = response.pairs[i].freq * 1000;
+ emc->dvfs[i].latency = response.pairs[i].latency;
+
+ if (emc->dvfs[i].rate < emc->debugfs.min_rate)
+ emc->debugfs.min_rate = emc->dvfs[i].rate;
+
+ if (emc->dvfs[i].rate > emc->debugfs.max_rate)
+ emc->debugfs.max_rate = emc->dvfs[i].rate;
+
+ dev_dbg(emc->dev, " %2u: %lu Hz -> %lu us\n", i,
+ emc->dvfs[i].rate, emc->dvfs[i].latency);
+ }
+
+ err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate, emc->debugfs.max_rate);
+ if (err < 0) {
+ dev_err(emc->dev, "failed to set rate range [%lu-%lu] for %pC\n",
+ emc->debugfs.min_rate, emc->debugfs.max_rate, emc->clk);
+ return err;
+ }
+
+ emc->debugfs.root = debugfs_create_dir("emc", NULL);
+ debugfs_create_file("available_rates", 0444, emc->debugfs.root, emc,
+ &tegra186_emc_debug_available_rates_fops);
+ debugfs_create_file("min_rate", 0644, emc->debugfs.root, emc,
+ &tegra186_emc_debug_min_rate_fops);
+ debugfs_create_file("max_rate", 0644, emc->debugfs.root, emc,
+ &tegra186_emc_debug_max_rate_fops);
+
+ return 0;
+}
+
/*
* tegra_emc_icc_set_bw() - Set BW api for EMC provider
* @src: ICC node for External Memory Controller (EMC)
@@ -251,10 +318,7 @@ err_msg:
static int tegra186_emc_probe(struct platform_device *pdev)
{
struct tegra_mc *mc = dev_get_drvdata(pdev->dev.parent);
- struct mrq_emc_dvfs_latency_response response;
- struct tegra_bpmp_message msg;
struct tegra186_emc *emc;
- unsigned int i;
int err;
emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL);
@@ -275,70 +339,12 @@ static int tegra186_emc_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, emc);
emc->dev = &pdev->dev;
- memset(&msg, 0, sizeof(msg));
- msg.mrq = MRQ_EMC_DVFS_LATENCY;
- msg.tx.data = NULL;
- msg.tx.size = 0;
- msg.rx.data = &response;
- msg.rx.size = sizeof(response);
-
- err = tegra_bpmp_transfer(emc->bpmp, &msg);
- if (err < 0) {
- dev_err(&pdev->dev, "failed to EMC DVFS pairs: %d\n", err);
- goto put_bpmp;
- }
- if (msg.rx.ret < 0) {
- err = -EINVAL;
- dev_err(&pdev->dev, "EMC DVFS MRQ failed: %d (BPMP error code)\n", msg.rx.ret);
- goto put_bpmp;
- }
-
- emc->debugfs.min_rate = ULONG_MAX;
- emc->debugfs.max_rate = 0;
-
- emc->num_dvfs = response.num_pairs;
-
- emc->dvfs = devm_kmalloc_array(&pdev->dev, emc->num_dvfs,
- sizeof(*emc->dvfs), GFP_KERNEL);
- if (!emc->dvfs) {
- err = -ENOMEM;
- goto put_bpmp;
- }
-
- dev_dbg(&pdev->dev, "%u DVFS pairs:\n", emc->num_dvfs);
-
- for (i = 0; i < emc->num_dvfs; i++) {
- emc->dvfs[i].rate = response.pairs[i].freq * 1000;
- emc->dvfs[i].latency = response.pairs[i].latency;
-
- if (emc->dvfs[i].rate < emc->debugfs.min_rate)
- emc->debugfs.min_rate = emc->dvfs[i].rate;
-
- if (emc->dvfs[i].rate > emc->debugfs.max_rate)
- emc->debugfs.max_rate = emc->dvfs[i].rate;
-
- dev_dbg(&pdev->dev, " %2u: %lu Hz -> %lu us\n", i,
- emc->dvfs[i].rate, emc->dvfs[i].latency);
- }
-
- err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate,
- emc->debugfs.max_rate);
- if (err < 0) {
- dev_err(&pdev->dev,
- "failed to set rate range [%lu-%lu] for %pC\n",
- emc->debugfs.min_rate, emc->debugfs.max_rate,
- emc->clk);
- goto put_bpmp;
+ if (tegra_bpmp_mrq_is_supported(emc->bpmp, MRQ_EMC_DVFS_LATENCY)) {
+ err = tegra186_emc_get_emc_dvfs_latency(emc);
+ if (err)
+ goto put_bpmp;
}
- emc->debugfs.root = debugfs_create_dir("emc", NULL);
- debugfs_create_file("available_rates", S_IRUGO, emc->debugfs.root,
- emc, &tegra186_emc_debug_available_rates_fops);
- debugfs_create_file("min_rate", S_IRUGO | S_IWUSR, emc->debugfs.root,
- emc, &tegra186_emc_debug_min_rate_fops);
- debugfs_create_file("max_rate", S_IRUGO | S_IWUSR, emc->debugfs.root,
- emc, &tegra186_emc_debug_max_rate_fops);
-
if (mc && mc->soc->icc_ops) {
if (tegra_bpmp_mrq_is_supported(emc->bpmp, MRQ_BWMGR_INT)) {
mc->bwmgr_mrq_supported = true;
diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra186.c
index 7bb73f06fad3..533f85a4b2bd 100644
--- a/drivers/memory/tegra/tegra186.c
+++ b/drivers/memory/tegra/tegra186.c
@@ -7,7 +7,8 @@
#include <linux/iommu.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <soc/tegra/mc.h>
diff --git a/drivers/memory/tegra/tegra20.c b/drivers/memory/tegra/tegra20.c
index fcd7738fcb53..544bfd216a22 100644
--- a/drivers/memory/tegra/tegra20.c
+++ b/drivers/memory/tegra/tegra20.c
@@ -5,8 +5,9 @@
#include <linux/bitfield.h>
#include <linux/delay.h>
+#include <linux/device.h>
#include <linux/mutex.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
#include <linux/slab.h>
#include <linux/string.h>
diff --git a/drivers/memory/tegra/tegra210-emc-core.c b/drivers/memory/tegra/tegra210-emc-core.c
index ae5f982f861b..3300bde47c13 100644
--- a/drivers/memory/tegra/tegra210-emc-core.c
+++ b/drivers/memory/tegra/tegra210-emc-core.c
@@ -9,10 +9,10 @@
#include <linux/debugfs.h>
#include <linux/delay.h>
#include <linux/kernel.h>
+#include <linux/mod_devicetable.h>
#include <linux/module.h>
-#include <linux/of_address.h>
-#include <linux/of_platform.h>
#include <linux/of_reserved_mem.h>
+#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/thermal.h>
#include <soc/tegra/fuse.h>
diff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra234.c
index 8fb83b39f5f5..9e5b5dbd9c8d 100644
--- a/drivers/memory/tegra/tegra234.c
+++ b/drivers/memory/tegra/tegra234.c
@@ -12,6 +12,10 @@
#include <soc/tegra/bpmp.h>
#include "mc.h"
+/*
+ * MC Client entries are sorted in the increasing order of the
+ * override and security register offsets.
+ */
static const struct tegra_mc_client tegra234_mc_clients[] = {
{
.id = TEGRA234_MEMORY_CLIENT_HDAR,
@@ -26,6 +30,130 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
},
},
}, {
+ .id = TEGRA234_MEMORY_CLIENT_NVENCSRD,
+ .name = "nvencsrd",
+ .bpmp_id = TEGRA_ICC_BPMP_NVENC,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_NVENC,
+ .regs = {
+ .sid = {
+ .override = 0xe0,
+ .security = 0xe4,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_PCIE6AR,
+ .name = "pcie6ar",
+ .bpmp_id = TEGRA_ICC_BPMP_PCIE_6,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_PCIE6,
+ .regs = {
+ .sid = {
+ .override = 0x140,
+ .security = 0x144,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_PCIE6AW,
+ .name = "pcie6aw",
+ .bpmp_id = TEGRA_ICC_BPMP_PCIE_6,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_PCIE6,
+ .regs = {
+ .sid = {
+ .override = 0x148,
+ .security = 0x14c,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_PCIE7AR,
+ .name = "pcie7ar",
+ .bpmp_id = TEGRA_ICC_BPMP_PCIE_7,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_PCIE7,
+ .regs = {
+ .sid = {
+ .override = 0x150,
+ .security = 0x154,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_NVENCSWR,
+ .name = "nvencswr",
+ .bpmp_id = TEGRA_ICC_BPMP_NVENC,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_NVENC,
+ .regs = {
+ .sid = {
+ .override = 0x158,
+ .security = 0x15c,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_DLA0RDB,
+ .name = "dla0rdb",
+ .sid = TEGRA234_SID_NVDLA0,
+ .regs = {
+ .sid = {
+ .override = 0x160,
+ .security = 0x164,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_DLA0RDB1,
+ .name = "dla0rdb1",
+ .sid = TEGRA234_SID_NVDLA0,
+ .regs = {
+ .sid = {
+ .override = 0x168,
+ .security = 0x16c,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_DLA0WRB,
+ .name = "dla0wrb",
+ .sid = TEGRA234_SID_NVDLA0,
+ .regs = {
+ .sid = {
+ .override = 0x170,
+ .security = 0x174,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_DLA1RDB,
+ .name = "dla0rdb",
+ .sid = TEGRA234_SID_NVDLA1,
+ .regs = {
+ .sid = {
+ .override = 0x178,
+ .security = 0x17c,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_PCIE7AW,
+ .name = "pcie7aw",
+ .bpmp_id = TEGRA_ICC_BPMP_PCIE_7,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_PCIE7,
+ .regs = {
+ .sid = {
+ .override = 0x180,
+ .security = 0x184,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_PCIE8AR,
+ .name = "pcie8ar",
+ .bpmp_id = TEGRA_ICC_BPMP_PCIE_8,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_PCIE8,
+ .regs = {
+ .sid = {
+ .override = 0x190,
+ .security = 0x194,
+ },
+ },
+ }, {
.id = TEGRA234_MEMORY_CLIENT_HDAW,
.name = "hdaw",
.bpmp_id = TEGRA_ICC_BPMP_HDA,
@@ -38,6 +166,102 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
},
},
}, {
+ .id = TEGRA234_MEMORY_CLIENT_PCIE8AW,
+ .name = "pcie8aw",
+ .bpmp_id = TEGRA_ICC_BPMP_PCIE_8,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_PCIE8,
+ .regs = {
+ .sid = {
+ .override = 0x1d8,
+ .security = 0x1dc,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_PCIE9AR,
+ .name = "pcie9ar",
+ .bpmp_id = TEGRA_ICC_BPMP_PCIE_9,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_PCIE9,
+ .regs = {
+ .sid = {
+ .override = 0x1e0,
+ .security = 0x1e4,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_PCIE6AR1,
+ .name = "pcie6ar1",
+ .bpmp_id = TEGRA_ICC_BPMP_PCIE_6,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_PCIE6,
+ .regs = {
+ .sid = {
+ .override = 0x1e8,
+ .security = 0x1ec,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_PCIE9AW,
+ .name = "pcie9aw",
+ .bpmp_id = TEGRA_ICC_BPMP_PCIE_9,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_PCIE9,
+ .regs = {
+ .sid = {
+ .override = 0x1f0,
+ .security = 0x1f4,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_PCIE10AR,
+ .name = "pcie10ar",
+ .bpmp_id = TEGRA_ICC_BPMP_PCIE_10,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_PCIE10,
+ .regs = {
+ .sid = {
+ .override = 0x1f8,
+ .security = 0x1fc,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_PCIE10AW,
+ .name = "pcie10aw",
+ .bpmp_id = TEGRA_ICC_BPMP_PCIE_10,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_PCIE10,
+ .regs = {
+ .sid = {
+ .override = 0x200,
+ .security = 0x204,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_PCIE10AR1,
+ .name = "pcie10ar1",
+ .bpmp_id = TEGRA_ICC_BPMP_PCIE_10,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_PCIE10,
+ .regs = {
+ .sid = {
+ .override = 0x240,
+ .security = 0x244,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_PCIE7AR1,
+ .name = "pcie7ar1",
+ .bpmp_id = TEGRA_ICC_BPMP_PCIE_7,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_PCIE7,
+ .regs = {
+ .sid = {
+ .override = 0x248,
+ .security = 0x24c,
+ },
+ },
+ }, {
.id = TEGRA234_MEMORY_CLIENT_MGBEARD,
.name = "mgbeard",
.bpmp_id = TEGRA_ICC_BPMP_EQOS,
@@ -158,6 +382,50 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
},
},
}, {
+ .id = TEGRA234_MEMORY_CLIENT_VICSRD,
+ .name = "vicsrd",
+ .bpmp_id = TEGRA_ICC_BPMP_VIC,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_VIC,
+ .regs = {
+ .sid = {
+ .override = 0x360,
+ .security = 0x364,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_VICSWR,
+ .name = "vicswr",
+ .bpmp_id = TEGRA_ICC_BPMP_VIC,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_VIC,
+ .regs = {
+ .sid = {
+ .override = 0x368,
+ .security = 0x36c,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_DLA1RDB1,
+ .name = "dla0rdb1",
+ .sid = TEGRA234_SID_NVDLA1,
+ .regs = {
+ .sid = {
+ .override = 0x370,
+ .security = 0x374,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_DLA1WRB,
+ .name = "dla0wrb",
+ .sid = TEGRA234_SID_NVDLA1,
+ .regs = {
+ .sid = {
+ .override = 0x378,
+ .security = 0x37c,
+ },
+ },
+ }, {
.id = TEGRA234_MEMORY_CLIENT_VI2W,
.name = "vi2w",
.bpmp_id = TEGRA_ICC_BPMP_VI2,
@@ -182,15 +450,27 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
},
},
}, {
- .id = TEGRA234_MEMORY_CLIENT_VI2FALW,
- .name = "vi2falw",
- .bpmp_id = TEGRA_ICC_BPMP_VI2FAL,
- .type = TEGRA_ICC_ISO_VIFAL,
- .sid = TEGRA234_SID_ISO_VI2FALC,
+ .id = TEGRA234_MEMORY_CLIENT_NVDECSRD,
+ .name = "nvdecsrd",
+ .bpmp_id = TEGRA_ICC_BPMP_NVDEC,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_NVDEC,
.regs = {
.sid = {
- .override = 0x3e0,
- .security = 0x3e4,
+ .override = 0x3c0,
+ .security = 0x3c4,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_NVDECSWR,
+ .name = "nvdecswr",
+ .bpmp_id = TEGRA_ICC_BPMP_NVDEC,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_NVDEC,
+ .regs = {
+ .sid = {
+ .override = 0x3c8,
+ .security = 0x3cc,
},
},
}, {
@@ -218,27 +498,51 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
},
},
}, {
- .id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR,
- .name = "nvdisplayr",
- .bpmp_id = TEGRA_ICC_BPMP_DISPLAY,
- .type = TEGRA_ICC_ISO_DISPLAY,
- .sid = TEGRA234_SID_ISO_NVDISPLAY,
+ .id = TEGRA234_MEMORY_CLIENT_VI2FALW,
+ .name = "vi2falw",
+ .bpmp_id = TEGRA_ICC_BPMP_VI2FAL,
+ .type = TEGRA_ICC_ISO_VIFAL,
+ .sid = TEGRA234_SID_ISO_VI2FALC,
.regs = {
.sid = {
- .override = 0x490,
- .security = 0x494,
+ .override = 0x3e0,
+ .security = 0x3e4,
},
},
}, {
- .id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR1,
- .name = "nvdisplayr1",
+ .id = TEGRA234_MEMORY_CLIENT_NVJPGSRD,
+ .name = "nvjpgsrd",
+ .bpmp_id = TEGRA_ICC_BPMP_NVJPG_0,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_NVJPG,
+ .regs = {
+ .sid = {
+ .override = 0x3f0,
+ .security = 0x3f4,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_NVJPGSWR,
+ .name = "nvjpgswr",
+ .bpmp_id = TEGRA_ICC_BPMP_NVJPG_0,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_NVJPG,
+ .regs = {
+ .sid = {
+ .override = 0x3f8,
+ .security = 0x3fc,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR,
+ .name = "nvdisplayr",
.bpmp_id = TEGRA_ICC_BPMP_DISPLAY,
.type = TEGRA_ICC_ISO_DISPLAY,
.sid = TEGRA234_SID_ISO_NVDISPLAY,
.regs = {
.sid = {
- .override = 0x508,
- .security = 0x50c,
+ .override = 0x490,
+ .security = 0x494,
},
},
}, {
@@ -306,6 +610,18 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
},
},
}, {
+ .id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR1,
+ .name = "nvdisplayr1",
+ .bpmp_id = TEGRA_ICC_BPMP_DISPLAY,
+ .type = TEGRA_ICC_ISO_DISPLAY,
+ .sid = TEGRA234_SID_ISO_NVDISPLAY,
+ .regs = {
+ .sid = {
+ .override = 0x508,
+ .security = 0x50c,
+ },
+ },
+ }, {
.id = TEGRA234_MEMORY_CLIENT_DLA0RDA,
.name = "dla0rda",
.sid = TEGRA234_SID_NVDLA0,
@@ -336,26 +652,6 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
},
},
}, {
- .id = TEGRA234_MEMORY_CLIENT_DLA0RDB,
- .name = "dla0rdb",
- .sid = TEGRA234_SID_NVDLA0,
- .regs = {
- .sid = {
- .override = 0x160,
- .security = 0x164,
- },
- },
- }, {
- .id = TEGRA234_MEMORY_CLIENT_DLA0RDA1,
- .name = "dla0rda1",
- .sid = TEGRA234_SID_NVDLA0,
- .regs = {
- .sid = {
- .override = 0x748,
- .security = 0x74c,
- },
- },
- }, {
.id = TEGRA234_MEMORY_CLIENT_DLA0FALWRB,
.name = "dla0falwrb",
.sid = TEGRA234_SID_NVDLA0,
@@ -366,26 +662,6 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
},
},
}, {
- .id = TEGRA234_MEMORY_CLIENT_DLA0RDB1,
- .name = "dla0rdb1",
- .sid = TEGRA234_SID_NVDLA0,
- .regs = {
- .sid = {
- .override = 0x168,
- .security = 0x16c,
- },
- },
- }, {
- .id = TEGRA234_MEMORY_CLIENT_DLA0WRB,
- .name = "dla0wrb",
- .sid = TEGRA234_SID_NVDLA0,
- .regs = {
- .sid = {
- .override = 0x170,
- .security = 0x174,
- },
- },
- }, {
.id = TEGRA234_MEMORY_CLIENT_DLA1RDA,
.name = "dla0rda",
.sid = TEGRA234_SID_NVDLA1,
@@ -416,26 +692,6 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
},
},
}, {
- .id = TEGRA234_MEMORY_CLIENT_DLA1RDB,
- .name = "dla0rdb",
- .sid = TEGRA234_SID_NVDLA1,
- .regs = {
- .sid = {
- .override = 0x178,
- .security = 0x17c,
- },
- },
- }, {
- .id = TEGRA234_MEMORY_CLIENT_DLA1RDA1,
- .name = "dla0rda1",
- .sid = TEGRA234_SID_NVDLA1,
- .regs = {
- .sid = {
- .override = 0x750,
- .security = 0x754,
- },
- },
- }, {
.id = TEGRA234_MEMORY_CLIENT_DLA1FALWRB,
.name = "dla0falwrb",
.sid = TEGRA234_SID_NVDLA1,
@@ -446,26 +702,6 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
},
},
}, {
- .id = TEGRA234_MEMORY_CLIENT_DLA1RDB1,
- .name = "dla0rdb1",
- .sid = TEGRA234_SID_NVDLA1,
- .regs = {
- .sid = {
- .override = 0x370,
- .security = 0x374,
- },
- },
- }, {
- .id = TEGRA234_MEMORY_CLIENT_DLA1WRB,
- .name = "dla0wrb",
- .sid = TEGRA234_SID_NVDLA1,
- .regs = {
- .sid = {
- .override = 0x378,
- .security = 0x37c,
- },
- },
- }, {
.id = TEGRA234_MEMORY_CLIENT_PCIE0R,
.name = "pcie0r",
.bpmp_id = TEGRA_ICC_BPMP_PCIE_0,
@@ -610,171 +846,59 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
},
},
}, {
- .id = TEGRA234_MEMORY_CLIENT_PCIE5R1,
- .name = "pcie5r1",
- .bpmp_id = TEGRA_ICC_BPMP_PCIE_5,
- .type = TEGRA_ICC_NISO,
- .sid = TEGRA234_SID_PCIE5,
- .regs = {
- .sid = {
- .override = 0x778,
- .security = 0x77c,
- },
- },
- }, {
- .id = TEGRA234_MEMORY_CLIENT_PCIE6AR,
- .name = "pcie6ar",
- .bpmp_id = TEGRA_ICC_BPMP_PCIE_6,
- .type = TEGRA_ICC_NISO,
- .sid = TEGRA234_SID_PCIE6,
- .regs = {
- .sid = {
- .override = 0x140,
- .security = 0x144,
- },
- },
- }, {
- .id = TEGRA234_MEMORY_CLIENT_PCIE6AW,
- .name = "pcie6aw",
- .bpmp_id = TEGRA_ICC_BPMP_PCIE_6,
- .type = TEGRA_ICC_NISO,
- .sid = TEGRA234_SID_PCIE6,
- .regs = {
- .sid = {
- .override = 0x148,
- .security = 0x14c,
- },
- },
- }, {
- .id = TEGRA234_MEMORY_CLIENT_PCIE6AR1,
- .name = "pcie6ar1",
- .bpmp_id = TEGRA_ICC_BPMP_PCIE_6,
- .type = TEGRA_ICC_NISO,
- .sid = TEGRA234_SID_PCIE6,
- .regs = {
- .sid = {
- .override = 0x1e8,
- .security = 0x1ec,
- },
- },
- }, {
- .id = TEGRA234_MEMORY_CLIENT_PCIE7AR,
- .name = "pcie7ar",
- .bpmp_id = TEGRA_ICC_BPMP_PCIE_7,
- .type = TEGRA_ICC_NISO,
- .sid = TEGRA234_SID_PCIE7,
- .regs = {
- .sid = {
- .override = 0x150,
- .security = 0x154,
- },
- },
- }, {
- .id = TEGRA234_MEMORY_CLIENT_PCIE7AW,
- .name = "pcie7aw",
- .bpmp_id = TEGRA_ICC_BPMP_PCIE_7,
- .type = TEGRA_ICC_NISO,
- .sid = TEGRA234_SID_PCIE7,
- .regs = {
- .sid = {
- .override = 0x180,
- .security = 0x184,
- },
- },
- }, {
- .id = TEGRA234_MEMORY_CLIENT_PCIE7AR1,
- .name = "pcie7ar1",
- .bpmp_id = TEGRA_ICC_BPMP_PCIE_7,
- .type = TEGRA_ICC_NISO,
- .sid = TEGRA234_SID_PCIE7,
- .regs = {
- .sid = {
- .override = 0x248,
- .security = 0x24c,
- },
- },
- }, {
- .id = TEGRA234_MEMORY_CLIENT_PCIE8AR,
- .name = "pcie8ar",
- .bpmp_id = TEGRA_ICC_BPMP_PCIE_8,
- .type = TEGRA_ICC_NISO,
- .sid = TEGRA234_SID_PCIE8,
- .regs = {
- .sid = {
- .override = 0x190,
- .security = 0x194,
- },
- },
- }, {
- .id = TEGRA234_MEMORY_CLIENT_PCIE8AW,
- .name = "pcie8aw",
- .bpmp_id = TEGRA_ICC_BPMP_PCIE_8,
- .type = TEGRA_ICC_NISO,
- .sid = TEGRA234_SID_PCIE8,
- .regs = {
- .sid = {
- .override = 0x1d8,
- .security = 0x1dc,
- },
- },
- }, {
- .id = TEGRA234_MEMORY_CLIENT_PCIE9AR,
- .name = "pcie9ar",
- .bpmp_id = TEGRA_ICC_BPMP_PCIE_9,
- .type = TEGRA_ICC_NISO,
- .sid = TEGRA234_SID_PCIE9,
+ .id = TEGRA234_MEMORY_CLIENT_DLA0RDA1,
+ .name = "dla0rda1",
+ .sid = TEGRA234_SID_NVDLA0,
.regs = {
.sid = {
- .override = 0x1e0,
- .security = 0x1e4,
+ .override = 0x748,
+ .security = 0x74c,
},
},
}, {
- .id = TEGRA234_MEMORY_CLIENT_PCIE9AW,
- .name = "pcie9aw",
- .bpmp_id = TEGRA_ICC_BPMP_PCIE_9,
- .type = TEGRA_ICC_NISO,
- .sid = TEGRA234_SID_PCIE9,
+ .id = TEGRA234_MEMORY_CLIENT_DLA1RDA1,
+ .name = "dla0rda1",
+ .sid = TEGRA234_SID_NVDLA1,
.regs = {
.sid = {
- .override = 0x1f0,
- .security = 0x1f4,
+ .override = 0x750,
+ .security = 0x754,
},
},
}, {
- .id = TEGRA234_MEMORY_CLIENT_PCIE10AR,
- .name = "pcie10ar",
- .bpmp_id = TEGRA_ICC_BPMP_PCIE_10,
+ .id = TEGRA234_MEMORY_CLIENT_PCIE5R1,
+ .name = "pcie5r1",
+ .bpmp_id = TEGRA_ICC_BPMP_PCIE_5,
.type = TEGRA_ICC_NISO,
- .sid = TEGRA234_SID_PCIE10,
+ .sid = TEGRA234_SID_PCIE5,
.regs = {
.sid = {
- .override = 0x1f8,
- .security = 0x1fc,
+ .override = 0x778,
+ .security = 0x77c,
},
},
}, {
- .id = TEGRA234_MEMORY_CLIENT_PCIE10AW,
- .name = "pcie10aw",
- .bpmp_id = TEGRA_ICC_BPMP_PCIE_10,
+ .id = TEGRA234_MEMORY_CLIENT_NVJPG1SRD,
+ .name = "nvjpg1srd",
+ .bpmp_id = TEGRA_ICC_BPMP_NVJPG_1,
.type = TEGRA_ICC_NISO,
- .sid = TEGRA234_SID_PCIE10,
+ .sid = TEGRA234_SID_NVJPG1,
.regs = {
.sid = {
- .override = 0x200,
- .security = 0x204,
+ .override = 0x918,
+ .security = 0x91c,
},
},
}, {
- .id = TEGRA234_MEMORY_CLIENT_PCIE10AR1,
- .name = "pcie10ar1",
- .bpmp_id = TEGRA_ICC_BPMP_PCIE_10,
+ .id = TEGRA234_MEMORY_CLIENT_NVJPG1SWR,
+ .name = "nvjpg1swr",
+ .bpmp_id = TEGRA_ICC_BPMP_NVJPG_1,
.type = TEGRA_ICC_NISO,
- .sid = TEGRA234_SID_PCIE10,
+ .sid = TEGRA234_SID_NVJPG1,
.regs = {
.sid = {
- .override = 0x240,
- .security = 0x244,
+ .override = 0x920,
+ .security = 0x924,
},
},
}, {
@@ -792,6 +916,16 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
.name = "sw_cluster2",
.bpmp_id = TEGRA_ICC_BPMP_CPU_CLUSTER2,
.type = TEGRA_ICC_NISO,
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_NVL1R,
+ .name = "nvl1r",
+ .bpmp_id = TEGRA_ICC_BPMP_GPU,
+ .type = TEGRA_ICC_NISO,
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_NVL1W,
+ .name = "nvl1w",
+ .bpmp_id = TEGRA_ICC_BPMP_GPU,
+ .type = TEGRA_ICC_NISO,
},
};
diff --git a/drivers/memory/tegra/tegra30-emc.c b/drivers/memory/tegra/tegra30-emc.c
index c91e9b7e2e01..9eae25c57ec6 100644
--- a/drivers/memory/tegra/tegra30-emc.c
+++ b/drivers/memory/tegra/tegra30-emc.c
@@ -22,7 +22,7 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mutex.h>
-#include <linux/of_platform.h>
+#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_opp.h>
#include <linux/slab.h>
diff --git a/drivers/memory/tegra/tegra30.c b/drivers/memory/tegra/tegra30.c
index 84316357513d..06f8b35e0a14 100644
--- a/drivers/memory/tegra/tegra30.c
+++ b/drivers/memory/tegra/tegra30.c
@@ -3,8 +3,8 @@
* Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
*/
+#include <linux/device.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <linux/slab.h>
#include <dt-bindings/memory/tegra30-mc.h>
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