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-rw-r--r--drivers/irqchip/irq-ativic32.c31
-rw-r--r--drivers/irqchip/irq-gic-v3.c4
-rw-r--r--drivers/irqchip/irq-orion.c22
-rw-r--r--drivers/irqchip/irq-tb10x.c18
-rw-r--r--drivers/irqchip/irq-xtensa-mx.c10
-rw-r--r--drivers/irqchip/irq-xtensa-pic.c8
6 files changed, 62 insertions, 31 deletions
diff --git a/drivers/irqchip/irq-ativic32.c b/drivers/irqchip/irq-ativic32.c
index f69a8588521c..85cf6e0e0e52 100644
--- a/drivers/irqchip/irq-ativic32.c
+++ b/drivers/irqchip/irq-ativic32.c
@@ -10,6 +10,8 @@
#include <linux/irqchip.h>
#include <nds32_intrinsic.h>
+unsigned long wake_mask;
+
static void ativic32_ack_irq(struct irq_data *data)
{
__nds32__mtsr_dsb(BIT(data->hwirq), NDS32_SR_INT_PEND2);
@@ -27,11 +29,40 @@ static void ativic32_unmask_irq(struct irq_data *data)
__nds32__mtsr_dsb(int_mask2 | (BIT(data->hwirq)), NDS32_SR_INT_MASK2);
}
+static int nointc_set_wake(struct irq_data *data, unsigned int on)
+{
+ unsigned long int_mask = __nds32__mfsr(NDS32_SR_INT_MASK);
+ static unsigned long irq_orig_bit;
+ u32 bit = 1 << data->hwirq;
+
+ if (on) {
+ if (int_mask & bit)
+ __assign_bit(data->hwirq, &irq_orig_bit, true);
+ else
+ __assign_bit(data->hwirq, &irq_orig_bit, false);
+
+ __assign_bit(data->hwirq, &int_mask, true);
+ __assign_bit(data->hwirq, &wake_mask, true);
+
+ } else {
+ if (!(irq_orig_bit & bit))
+ __assign_bit(data->hwirq, &int_mask, false);
+
+ __assign_bit(data->hwirq, &wake_mask, false);
+ __assign_bit(data->hwirq, &irq_orig_bit, false);
+ }
+
+ __nds32__mtsr_dsb(int_mask, NDS32_SR_INT_MASK);
+
+ return 0;
+}
+
static struct irq_chip ativic32_chip = {
.name = "ativic32",
.irq_ack = ativic32_ack_irq,
.irq_mask = ativic32_mask_irq,
.irq_unmask = ativic32_unmask_irq,
+ .irq_set_wake = nointc_set_wake,
};
static unsigned int __initdata nivic_map[6] = { 6, 2, 10, 16, 24, 32 };
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index d3d4f65b377b..0868a9d81c3c 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -1199,8 +1199,8 @@ static void __init gic_populate_ppi_partitions(struct device_node *gic_node)
part->partition_id = of_node_to_fwnode(child_part);
- pr_info("GIC: PPI partition %s[%d] { ",
- child_part->name, part_idx);
+ pr_info("GIC: PPI partition %pOFn[%d] { ",
+ child_part, part_idx);
n = of_property_count_elems_of_size(child_part, "affinity",
sizeof(u32));
diff --git a/drivers/irqchip/irq-orion.c b/drivers/irqchip/irq-orion.c
index be4c5a8c9659..c4b5ffb61954 100644
--- a/drivers/irqchip/irq-orion.c
+++ b/drivers/irqchip/irq-orion.c
@@ -64,14 +64,14 @@ static int __init orion_irq_init(struct device_node *np,
num_chips * ORION_IRQS_PER_CHIP,
&irq_generic_chip_ops, NULL);
if (!orion_irq_domain)
- panic("%s: unable to add irq domain\n", np->name);
+ panic("%pOFn: unable to add irq domain\n", np);
ret = irq_alloc_domain_generic_chips(orion_irq_domain,
- ORION_IRQS_PER_CHIP, 1, np->name,
+ ORION_IRQS_PER_CHIP, 1, np->full_name,
handle_level_irq, clr, 0,
IRQ_GC_INIT_MASK_CACHE);
if (ret)
- panic("%s: unable to alloc irq domain gc\n", np->name);
+ panic("%pOFn: unable to alloc irq domain gc\n", np);
for (n = 0, base = 0; n < num_chips; n++, base += ORION_IRQS_PER_CHIP) {
struct irq_chip_generic *gc =
@@ -80,12 +80,12 @@ static int __init orion_irq_init(struct device_node *np,
of_address_to_resource(np, n, &r);
if (!request_mem_region(r.start, resource_size(&r), np->name))
- panic("%s: unable to request mem region %d",
- np->name, n);
+ panic("%pOFn: unable to request mem region %d",
+ np, n);
gc->reg_base = ioremap(r.start, resource_size(&r));
if (!gc->reg_base)
- panic("%s: unable to map resource %d", np->name, n);
+ panic("%pOFn: unable to map resource %d", np, n);
gc->chip_types[0].regs.mask = ORION_IRQ_MASK;
gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
@@ -150,20 +150,20 @@ static int __init orion_bridge_irq_init(struct device_node *np,
domain = irq_domain_add_linear(np, nrirqs,
&irq_generic_chip_ops, NULL);
if (!domain) {
- pr_err("%s: unable to add irq domain\n", np->name);
+ pr_err("%pOFn: unable to add irq domain\n", np);
return -ENOMEM;
}
ret = irq_alloc_domain_generic_chips(domain, nrirqs, 1, np->name,
handle_edge_irq, clr, 0, IRQ_GC_INIT_MASK_CACHE);
if (ret) {
- pr_err("%s: unable to alloc irq domain gc\n", np->name);
+ pr_err("%pOFn: unable to alloc irq domain gc\n", np);
return ret;
}
ret = of_address_to_resource(np, 0, &r);
if (ret) {
- pr_err("%s: unable to get resource\n", np->name);
+ pr_err("%pOFn: unable to get resource\n", np);
return ret;
}
@@ -175,14 +175,14 @@ static int __init orion_bridge_irq_init(struct device_node *np,
/* Map the parent interrupt for the chained handler */
irq = irq_of_parse_and_map(np, 0);
if (irq <= 0) {
- pr_err("%s: unable to parse irq\n", np->name);
+ pr_err("%pOFn: unable to parse irq\n", np);
return -EINVAL;
}
gc = irq_get_domain_generic_chip(domain, 0);
gc->reg_base = ioremap(r.start, resource_size(&r));
if (!gc->reg_base) {
- pr_err("%s: unable to map resource\n", np->name);
+ pr_err("%pOFn: unable to map resource\n", np);
return -ENOMEM;
}
diff --git a/drivers/irqchip/irq-tb10x.c b/drivers/irqchip/irq-tb10x.c
index 848d782a2a3b..7e6708099a7b 100644
--- a/drivers/irqchip/irq-tb10x.c
+++ b/drivers/irqchip/irq-tb10x.c
@@ -115,21 +115,21 @@ static int __init of_tb10x_init_irq(struct device_node *ictl,
void __iomem *reg_base;
if (of_address_to_resource(ictl, 0, &mem)) {
- pr_err("%s: No registers declared in DeviceTree.\n",
- ictl->name);
+ pr_err("%pOFn: No registers declared in DeviceTree.\n",
+ ictl);
return -EINVAL;
}
if (!request_mem_region(mem.start, resource_size(&mem),
- ictl->name)) {
- pr_err("%s: Request mem region failed.\n", ictl->name);
+ ictl->full_name)) {
+ pr_err("%pOFn: Request mem region failed.\n", ictl);
return -EBUSY;
}
reg_base = ioremap(mem.start, resource_size(&mem));
if (!reg_base) {
ret = -EBUSY;
- pr_err("%s: ioremap failed.\n", ictl->name);
+ pr_err("%pOFn: ioremap failed.\n", ictl);
goto ioremap_fail;
}
@@ -137,8 +137,8 @@ static int __init of_tb10x_init_irq(struct device_node *ictl,
&irq_generic_chip_ops, NULL);
if (!domain) {
ret = -ENOMEM;
- pr_err("%s: Could not register interrupt domain.\n",
- ictl->name);
+ pr_err("%pOFn: Could not register interrupt domain.\n",
+ ictl);
goto irq_domain_add_fail;
}
@@ -147,8 +147,8 @@ static int __init of_tb10x_init_irq(struct device_node *ictl,
IRQ_NOREQUEST, IRQ_NOPROBE,
IRQ_GC_INIT_MASK_CACHE);
if (ret) {
- pr_err("%s: Could not allocate generic interrupt chip.\n",
- ictl->name);
+ pr_err("%pOFn: Could not allocate generic interrupt chip.\n",
+ ictl);
goto gc_alloc_fail;
}
diff --git a/drivers/irqchip/irq-xtensa-mx.c b/drivers/irqchip/irq-xtensa-mx.c
index e539500752d4..5385f5768345 100644
--- a/drivers/irqchip/irq-xtensa-mx.c
+++ b/drivers/irqchip/irq-xtensa-mx.c
@@ -62,7 +62,7 @@ void secondary_init_irq(void)
__this_cpu_write(cached_irq_mask,
XCHAL_INTTYPE_MASK_EXTERN_EDGE |
XCHAL_INTTYPE_MASK_EXTERN_LEVEL);
- set_sr(XCHAL_INTTYPE_MASK_EXTERN_EDGE |
+ xtensa_set_sr(XCHAL_INTTYPE_MASK_EXTERN_EDGE |
XCHAL_INTTYPE_MASK_EXTERN_LEVEL, intenable);
}
@@ -77,7 +77,7 @@ static void xtensa_mx_irq_mask(struct irq_data *d)
} else {
mask = __this_cpu_read(cached_irq_mask) & ~mask;
__this_cpu_write(cached_irq_mask, mask);
- set_sr(mask, intenable);
+ xtensa_set_sr(mask, intenable);
}
}
@@ -92,7 +92,7 @@ static void xtensa_mx_irq_unmask(struct irq_data *d)
} else {
mask |= __this_cpu_read(cached_irq_mask);
__this_cpu_write(cached_irq_mask, mask);
- set_sr(mask, intenable);
+ xtensa_set_sr(mask, intenable);
}
}
@@ -108,12 +108,12 @@ static void xtensa_mx_irq_disable(struct irq_data *d)
static void xtensa_mx_irq_ack(struct irq_data *d)
{
- set_sr(1 << d->hwirq, intclear);
+ xtensa_set_sr(1 << d->hwirq, intclear);
}
static int xtensa_mx_irq_retrigger(struct irq_data *d)
{
- set_sr(1 << d->hwirq, intset);
+ xtensa_set_sr(1 << d->hwirq, intset);
return 1;
}
diff --git a/drivers/irqchip/irq-xtensa-pic.c b/drivers/irqchip/irq-xtensa-pic.c
index 000cb5462bcf..c200234dd2c9 100644
--- a/drivers/irqchip/irq-xtensa-pic.c
+++ b/drivers/irqchip/irq-xtensa-pic.c
@@ -44,13 +44,13 @@ static const struct irq_domain_ops xtensa_irq_domain_ops = {
static void xtensa_irq_mask(struct irq_data *d)
{
cached_irq_mask &= ~(1 << d->hwirq);
- set_sr(cached_irq_mask, intenable);
+ xtensa_set_sr(cached_irq_mask, intenable);
}
static void xtensa_irq_unmask(struct irq_data *d)
{
cached_irq_mask |= 1 << d->hwirq;
- set_sr(cached_irq_mask, intenable);
+ xtensa_set_sr(cached_irq_mask, intenable);
}
static void xtensa_irq_enable(struct irq_data *d)
@@ -65,12 +65,12 @@ static void xtensa_irq_disable(struct irq_data *d)
static void xtensa_irq_ack(struct irq_data *d)
{
- set_sr(1 << d->hwirq, intclear);
+ xtensa_set_sr(1 << d->hwirq, intclear);
}
static int xtensa_irq_retrigger(struct irq_data *d)
{
- set_sr(1 << d->hwirq, intset);
+ xtensa_set_sr(1 << d->hwirq, intset);
return 1;
}
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