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path: root/drivers/i3c/master/mipi-i3c-hci/hci_quirks.c
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Diffstat (limited to 'drivers/i3c/master/mipi-i3c-hci/hci_quirks.c')
-rw-r--r--drivers/i3c/master/mipi-i3c-hci/hci_quirks.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/i3c/master/mipi-i3c-hci/hci_quirks.c b/drivers/i3c/master/mipi-i3c-hci/hci_quirks.c
index e8ea4d101f66..3b9c6e76c536 100644
--- a/drivers/i3c/master/mipi-i3c-hci/hci_quirks.c
+++ b/drivers/i3c/master/mipi-i3c-hci/hci_quirks.c
@@ -20,6 +20,8 @@
#define AMD_SCL_I3C_OD_TIMING 0x00cf00cf
#define AMD_SCL_I3C_PP_TIMING 0x00160016
+#define QUEUE_THLD_CTRL 0xD0
+
void amd_set_od_pp_timing(struct i3c_hci *hci)
{
u32 data;
@@ -31,3 +33,12 @@ void amd_set_od_pp_timing(struct i3c_hci *hci)
data |= W0_MASK(18, 16);
reg_write(HCI_SDA_HOLD_SWITCH_DLY_TIMING, data);
}
+
+void amd_set_resp_buf_thld(struct i3c_hci *hci)
+{
+ u32 data;
+
+ data = reg_read(QUEUE_THLD_CTRL);
+ data = data & ~W0_MASK(15, 8);
+ reg_write(QUEUE_THLD_CTRL, data);
+}