diff options
Diffstat (limited to 'drivers/gpu/drm/rockchip')
30 files changed, 1729 insertions, 814 deletions
diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig index 1e75196f9659..6f4222f8beeb 100644 --- a/drivers/gpu/drm/rockchip/Kconfig +++ b/drivers/gpu/drm/rockchip/Kconfig @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only config DRM_ROCKCHIP tristate "DRM Support for Rockchip" depends on DRM && ROCKCHIP_IOMMU @@ -77,4 +78,12 @@ config ROCKCHIP_RGB Some Rockchip CRTCs, like rv1108, can directly output parallel and serial RGB format to panel or connect to a conversion chip. say Y to enable its driver. + +config ROCKCHIP_RK3066_HDMI + bool "Rockchip specific extensions for RK3066 HDMI" + depends on DRM_ROCKCHIP + help + This selects support for Rockchip SoC specific extensions + for the RK3066 HDMI driver. If you want to enable + HDMI on RK3066 based SoC, you should select this option. endif diff --git a/drivers/gpu/drm/rockchip/Makefile b/drivers/gpu/drm/rockchip/Makefile index f6fc9d5dd0ad..17a9e7eb2130 100644 --- a/drivers/gpu/drm/rockchip/Makefile +++ b/drivers/gpu/drm/rockchip/Makefile @@ -4,8 +4,7 @@ # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o \ - rockchip_drm_gem.o rockchip_drm_psr.o \ - rockchip_drm_vop.o rockchip_vop_reg.o + rockchip_drm_gem.o rockchip_drm_vop.o rockchip_vop_reg.o rockchipdrm-$(CONFIG_DRM_FBDEV_EMULATION) += rockchip_drm_fbdev.o rockchipdrm-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o @@ -15,5 +14,6 @@ rockchipdrm-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi-rockchip.o rockchipdrm-$(CONFIG_ROCKCHIP_INNO_HDMI) += inno_hdmi.o rockchipdrm-$(CONFIG_ROCKCHIP_LVDS) += rockchip_lvds.o rockchipdrm-$(CONFIG_ROCKCHIP_RGB) += rockchip_rgb.o +rockchipdrm-$(CONFIG_ROCKCHIP_RK3066_HDMI) += rk3066_hdmi.o obj-$(CONFIG_DRM_ROCKCHIP) += rockchipdrm.o diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c index bc4423624209..f38f5e113c6b 100644 --- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c +++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Rockchip SoC DP (Display Port) interface driver. * @@ -5,11 +6,6 @@ * Author: Andy Yan <[email protected]> * Yakir Yang <[email protected]> * Jeff Chen <[email protected]> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. */ #include <linux/component.h> @@ -20,19 +16,18 @@ #include <linux/reset.h> #include <linux/clk.h> -#include <drm/drmP.h> -#include <drm/drm_dp_helper.h> -#include <drm/drm_of.h> -#include <drm/drm_panel.h> -#include <drm/drm_probe_helper.h> - #include <video/of_videomode.h> #include <video/videomode.h> +#include <drm/drm_atomic.h> +#include <drm/drm_atomic_helper.h> #include <drm/bridge/analogix_dp.h> +#include <drm/drm_dp_helper.h> +#include <drm/drm_of.h> +#include <drm/drm_panel.h> +#include <drm/drm_probe_helper.h> #include "rockchip_drm_drv.h" -#include "rockchip_drm_psr.h" #include "rockchip_drm_vop.h" #define RK3288_GRF_SOC_CON6 0x25c @@ -77,29 +72,6 @@ struct rockchip_dp_device { struct analogix_dp_plat_data plat_data; }; -static int analogix_dp_psr_set(struct drm_encoder *encoder, bool enabled) -{ - struct rockchip_dp_device *dp = to_dp(encoder); - int ret; - - if (!analogix_dp_psr_enabled(dp->adp)) - return 0; - - DRM_DEV_DEBUG(dp->dev, "%s PSR...\n", enabled ? "Entry" : "Exit"); - - ret = rockchip_drm_wait_vact_end(dp->encoder.crtc, - PSR_WAIT_LINE_FLAG_TIMEOUT_MS); - if (ret) { - DRM_DEV_ERROR(dp->dev, "line flag interrupt did not arrive\n"); - return -ETIMEDOUT; - } - - if (enabled) - return analogix_dp_enable_psr(dp->adp); - else - return analogix_dp_disable_psr(dp->adp); -} - static int rockchip_dp_pre_init(struct rockchip_dp_device *dp) { reset_control_assert(dp->rst); @@ -130,21 +102,9 @@ static int rockchip_dp_poweron_start(struct analogix_dp_plat_data *plat_data) return ret; } -static int rockchip_dp_poweron_end(struct analogix_dp_plat_data *plat_data) -{ - struct rockchip_dp_device *dp = to_dp(plat_data); - - return rockchip_drm_psr_inhibit_put(&dp->encoder); -} - static int rockchip_dp_powerdown(struct analogix_dp_plat_data *plat_data) { struct rockchip_dp_device *dp = to_dp(plat_data); - int ret; - - ret = rockchip_drm_psr_inhibit_get(&dp->encoder); - if (ret != 0) - return ret; clk_disable_unprepare(dp->pclk); @@ -184,12 +144,42 @@ static void rockchip_dp_drm_encoder_mode_set(struct drm_encoder *encoder, /* do nothing */ } -static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder) +static +struct drm_crtc *rockchip_dp_drm_get_new_crtc(struct drm_encoder *encoder, + struct drm_atomic_state *state) +{ + struct drm_connector *connector; + struct drm_connector_state *conn_state; + + connector = drm_atomic_get_new_connector_for_encoder(state, encoder); + if (!connector) + return NULL; + + conn_state = drm_atomic_get_new_connector_state(state, connector); + if (!conn_state) + return NULL; + + return conn_state->crtc; +} + +static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder, + struct drm_atomic_state *state) { struct rockchip_dp_device *dp = to_dp(encoder); + struct drm_crtc *crtc; + struct drm_crtc_state *old_crtc_state; int ret; u32 val; + crtc = rockchip_dp_drm_get_new_crtc(encoder, state); + if (!crtc) + return; + + old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc); + /* Coming back from self refresh, nothing to do */ + if (old_crtc_state && old_crtc_state->self_refresh_active) + return; + ret = drm_of_encoder_active_endpoint_id(dp->dev->of_node, encoder); if (ret < 0) return; @@ -214,9 +204,27 @@ static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder) clk_disable_unprepare(dp->grfclk); } -static void rockchip_dp_drm_encoder_nop(struct drm_encoder *encoder) +static void rockchip_dp_drm_encoder_disable(struct drm_encoder *encoder, + struct drm_atomic_state *state) { - /* do nothing */ + struct rockchip_dp_device *dp = to_dp(encoder); + struct drm_crtc *crtc; + struct drm_crtc_state *new_crtc_state = NULL; + int ret; + + crtc = rockchip_dp_drm_get_new_crtc(encoder, state); + /* No crtc means we're doing a full shutdown */ + if (!crtc) + return; + + new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc); + /* If we're not entering self-refresh, no need to wait for vact */ + if (!new_crtc_state || !new_crtc_state->self_refresh_active) + return; + + ret = rockchip_drm_wait_vact_end(crtc, PSR_WAIT_LINE_FLAG_TIMEOUT_MS); + if (ret) + DRM_DEV_ERROR(dp->dev, "line flag irq timed out\n"); } static int @@ -245,8 +253,8 @@ rockchip_dp_drm_encoder_atomic_check(struct drm_encoder *encoder, static struct drm_encoder_helper_funcs rockchip_dp_encoder_helper_funcs = { .mode_fixup = rockchip_dp_drm_encoder_mode_fixup, .mode_set = rockchip_dp_drm_encoder_mode_set, - .enable = rockchip_dp_drm_encoder_enable, - .disable = rockchip_dp_drm_encoder_nop, + .atomic_enable = rockchip_dp_drm_encoder_enable, + .atomic_disable = rockchip_dp_drm_encoder_disable, .atomic_check = rockchip_dp_drm_encoder_atomic_check, }; @@ -338,23 +346,16 @@ static int rockchip_dp_bind(struct device *dev, struct device *master, dp->plat_data.dev_type = dp->data->chip_type; dp->plat_data.power_on_start = rockchip_dp_poweron_start; - dp->plat_data.power_on_end = rockchip_dp_poweron_end; dp->plat_data.power_off = rockchip_dp_powerdown; dp->plat_data.get_modes = rockchip_dp_get_modes; - ret = rockchip_drm_psr_register(&dp->encoder, analogix_dp_psr_set); - if (ret < 0) - goto err_cleanup_encoder; - dp->adp = analogix_dp_bind(dev, dp->drm_dev, &dp->plat_data); if (IS_ERR(dp->adp)) { ret = PTR_ERR(dp->adp); - goto err_unreg_psr; + goto err_cleanup_encoder; } return 0; -err_unreg_psr: - rockchip_drm_psr_unregister(&dp->encoder); err_cleanup_encoder: dp->encoder.funcs->destroy(&dp->encoder); return ret; @@ -366,7 +367,6 @@ static void rockchip_dp_unbind(struct device *dev, struct device *master, struct rockchip_dp_device *dp = dev_get_drvdata(dev); analogix_dp_unbind(dp->adp); - rockchip_drm_psr_unregister(&dp->encoder); dp->encoder.funcs->destroy(&dp->encoder); dp->adp = ERR_PTR(-ENODEV); @@ -436,7 +436,7 @@ static int rockchip_dp_resume(struct device *dev) static const struct dev_pm_ops rockchip_dp_pm_ops = { #ifdef CONFIG_PM_SLEEP - .suspend = rockchip_dp_suspend, + .suspend_late = rockchip_dp_suspend, .resume_early = rockchip_dp_resume, #endif }; diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.c b/drivers/gpu/drm/rockchip/cdn-dp-core.c index f7b9d45aa1d6..eed594bd38d3 100644 --- a/drivers/gpu/drm/rockchip/cdn-dp-core.c +++ b/drivers/gpu/drm/rockchip/cdn-dp-core.c @@ -1,35 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd * Author: Chris Zhong <[email protected]> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ -#include <drm/drmP.h> -#include <drm/drm_atomic_helper.h> -#include <drm/drm_dp_helper.h> -#include <drm/drm_edid.h> -#include <drm/drm_of.h> -#include <drm/drm_probe_helper.h> - #include <linux/clk.h> #include <linux/component.h> #include <linux/extcon.h> #include <linux/firmware.h> -#include <linux/regmap.h> -#include <linux/reset.h> #include <linux/mfd/syscon.h> #include <linux/phy/phy.h> +#include <linux/regmap.h> +#include <linux/reset.h> #include <sound/hdmi-codec.h> +#include <drm/drm_atomic_helper.h> +#include <drm/drm_dp_helper.h> +#include <drm/drm_edid.h> +#include <drm/drm_of.h> +#include <drm/drm_probe_helper.h> + #include "cdn-dp-core.h" #include "cdn-dp-reg.h" #include "rockchip_drm_vop.h" @@ -486,8 +477,8 @@ static int cdn_dp_disable(struct cdn_dp_device *dp) cdn_dp_set_firmware_active(dp, false); cdn_dp_clk_disable(dp); dp->active = false; - dp->link.rate = 0; - dp->link.num_lanes = 0; + dp->max_lanes = 0; + dp->max_rate = 0; if (!dp->connected) { kfree(dp->edid); dp->edid = NULL; @@ -579,7 +570,7 @@ static bool cdn_dp_check_link_status(struct cdn_dp_device *dp) struct cdn_dp_port *port = cdn_dp_connected_port(dp); u8 sink_lanes = drm_dp_max_lane_count(dp->dpcd); - if (!port || !dp->link.rate || !dp->link.num_lanes) + if (!port || !dp->max_rate || !dp->max_lanes) return false; if (cdn_dp_dpcd_read(dp, DP_LANE0_1_STATUS, link_status, @@ -961,8 +952,8 @@ static void cdn_dp_pd_event_work(struct work_struct *work) /* Enabled and connected with a sink, re-train if requested */ } else if (!cdn_dp_check_link_status(dp)) { - unsigned int rate = dp->link.rate; - unsigned int lanes = dp->link.num_lanes; + unsigned int rate = dp->max_rate; + unsigned int lanes = dp->max_lanes; struct drm_display_mode *mode = &dp->mode; DRM_DEV_INFO(dp->dev, "Connected with sink. Re-train link\n"); @@ -975,7 +966,7 @@ static void cdn_dp_pd_event_work(struct work_struct *work) /* If training result is changed, update the video config */ if (mode->clock && - (rate != dp->link.rate || lanes != dp->link.num_lanes)) { + (rate != dp->max_rate || lanes != dp->max_lanes)) { ret = cdn_dp_config_video(dp); if (ret) { dp->connected = false; diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.h b/drivers/gpu/drm/rockchip/cdn-dp-core.h index 48fef95cb3c6..83c4586665b4 100644 --- a/drivers/gpu/drm/rockchip/cdn-dp-core.h +++ b/drivers/gpu/drm/rockchip/cdn-dp-core.h @@ -1,24 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2016 Chris Zhong <[email protected]> * Copyright (C) 2016 ROCKCHIP, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #ifndef _CDN_DP_CORE_H #define _CDN_DP_CORE_H -#include <drm/drmP.h> #include <drm/drm_dp_helper.h> #include <drm/drm_panel.h> #include <drm/drm_probe_helper.h> + #include "rockchip_drm_drv.h" #define MAX_PHY 2 @@ -100,9 +92,10 @@ struct cdn_dp_device { struct reset_control *core_rst; struct audio_info audio_info; struct video_info video_info; - struct drm_dp_link link; struct cdn_dp_port *port[MAX_PHY]; u8 ports; + u8 max_lanes; + u8 max_rate; u8 lanes; int active_port; diff --git a/drivers/gpu/drm/rockchip/cdn-dp-reg.c b/drivers/gpu/drm/rockchip/cdn-dp-reg.c index 6c8b14fb1d2f..7361c07cb4a7 100644 --- a/drivers/gpu/drm/rockchip/cdn-dp-reg.c +++ b/drivers/gpu/drm/rockchip/cdn-dp-reg.c @@ -1,15 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd * Author: Chris Zhong <[email protected]> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include <linux/clk.h> @@ -543,8 +535,8 @@ static int cdn_dp_get_training_status(struct cdn_dp_device *dp) if (ret) goto err_get_training_status; - dp->link.rate = status[0]; - dp->link.num_lanes = status[1]; + dp->max_rate = drm_dp_bw_code_to_link_rate(status[0]); + dp->max_lanes = status[1]; err_get_training_status: if (ret) @@ -568,8 +560,8 @@ int cdn_dp_train_link(struct cdn_dp_device *dp) return ret; } - DRM_DEV_DEBUG_KMS(dp->dev, "rate:0x%x, lanes:%d\n", dp->link.rate, - dp->link.num_lanes); + DRM_DEV_DEBUG_KMS(dp->dev, "rate:0x%x, lanes:%d\n", dp->max_rate, + dp->max_lanes); return ret; } @@ -647,7 +639,7 @@ int cdn_dp_config_video(struct cdn_dp_device *dp) bit_per_pix = (video->color_fmt == YCBCR_4_2_2) ? (video->color_depth * 2) : (video->color_depth * 3); - link_rate = drm_dp_bw_code_to_link_rate(dp->link.rate) / 1000; + link_rate = dp->max_rate / 1000; ret = cdn_dp_reg_write(dp, BND_HSYNC2VSYNC, VIF_BYPASS_INTERLACE); if (ret) @@ -667,14 +659,13 @@ int cdn_dp_config_video(struct cdn_dp_device *dp) do { tu_size_reg += 2; symbol = tu_size_reg * mode->clock * bit_per_pix; - do_div(symbol, dp->link.num_lanes * link_rate * 8); + do_div(symbol, dp->max_lanes * link_rate * 8); rem = do_div(symbol, 1000); if (tu_size_reg > 64) { ret = -EINVAL; DRM_DEV_ERROR(dp->dev, "tu error, clk:%d, lanes:%d, rate:%d\n", - mode->clock, dp->link.num_lanes, - link_rate); + mode->clock, dp->max_lanes, link_rate); goto err_config_video; } } while ((symbol <= 1) || (tu_size_reg - symbol < 4) || @@ -688,7 +679,7 @@ int cdn_dp_config_video(struct cdn_dp_device *dp) /* set the FIFO Buffer size */ val = div_u64(mode->clock * (symbol + 1), 1000) + link_rate; - val /= (dp->link.num_lanes * link_rate); + val /= (dp->max_lanes * link_rate); val = div_u64(8 * (symbol + 1), bit_per_pix) - val; val += 2; ret = cdn_dp_reg_write(dp, DP_VC_TABLE(15), val); @@ -841,7 +832,7 @@ static void cdn_dp_audio_config_i2s(struct cdn_dp_device *dp, u32 val; if (audio->channels == 2) { - if (dp->link.num_lanes == 1) + if (dp->max_lanes == 1) sub_pckt_num = 2; else sub_pckt_num = 4; diff --git a/drivers/gpu/drm/rockchip/cdn-dp-reg.h b/drivers/gpu/drm/rockchip/cdn-dp-reg.h index c4bbb4a83319..441248b7a79e 100644 --- a/drivers/gpu/drm/rockchip/cdn-dp-reg.h +++ b/drivers/gpu/drm/rockchip/cdn-dp-reg.h @@ -1,15 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd * Author: Chris Zhong <[email protected]> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #ifndef _CDN_DP_REG_H diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c index ef8486e5e2cd..bc073ec5c183 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c @@ -6,10 +6,6 @@ * Nickey Yang <[email protected]> */ -#include <drm/drmP.h> -#include <drm/drm_mipi_dsi.h> -#include <drm/bridge/dw_mipi_dsi.h> -#include <drm/drm_of.h> #include <linux/clk.h> #include <linux/iopoll.h> #include <linux/math64.h> @@ -18,8 +14,13 @@ #include <linux/of_device.h> #include <linux/pm_runtime.h> #include <linux/regmap.h> + #include <video/mipi_display.h> +#include <drm/bridge/dw_mipi_dsi.h> +#include <drm/drm_mipi_dsi.h> +#include <drm/drm_of.h> + #include "rockchip_drm_drv.h" #include "rockchip_drm_vop.h" diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c index 4cdc9f86c2e5..7f56d8c3491d 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -1,10 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. */ #include <linux/clk.h> @@ -14,15 +10,22 @@ #include <linux/phy/phy.h> #include <linux/regmap.h> -#include <drm/drm_of.h> -#include <drm/drmP.h> +#include <drm/bridge/dw_hdmi.h> #include <drm/drm_edid.h> +#include <drm/drm_of.h> #include <drm/drm_probe_helper.h> -#include <drm/bridge/dw_hdmi.h> #include "rockchip_drm_drv.h" #include "rockchip_drm_vop.h" +#define RK3228_GRF_SOC_CON2 0x0408 +#define RK3228_HDMI_SDAIN_MSK BIT(14) +#define RK3228_HDMI_SCLIN_MSK BIT(13) +#define RK3228_GRF_SOC_CON6 0x0418 +#define RK3228_HDMI_HPD_VSEL BIT(6) +#define RK3228_HDMI_SDA_VSEL BIT(5) +#define RK3228_HDMI_SCL_VSEL BIT(4) + #define RK3288_GRF_SOC_CON6 0x025C #define RK3288_HDMI_LCDC_SEL BIT(4) #define RK3328_GRF_SOC_CON2 0x0408 @@ -325,6 +328,25 @@ static void dw_hdmi_rockchip_genphy_disable(struct dw_hdmi *dw_hdmi, void *data) phy_power_off(hdmi->phy); } +static void dw_hdmi_rk3228_setup_hpd(struct dw_hdmi *dw_hdmi, void *data) +{ + struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; + + dw_hdmi_phy_setup_hpd(dw_hdmi, data); + + regmap_write(hdmi->regmap, + RK3228_GRF_SOC_CON6, + HIWORD_UPDATE(RK3228_HDMI_HPD_VSEL | RK3228_HDMI_SDA_VSEL | + RK3228_HDMI_SCL_VSEL, + RK3228_HDMI_HPD_VSEL | RK3228_HDMI_SDA_VSEL | + RK3228_HDMI_SCL_VSEL)); + + regmap_write(hdmi->regmap, + RK3228_GRF_SOC_CON2, + HIWORD_UPDATE(RK3228_HDMI_SDAIN_MSK | RK3228_HDMI_SCLIN_MSK, + RK3228_HDMI_SDAIN_MSK | RK3228_HDMI_SCLIN_MSK)); +} + static enum drm_connector_status dw_hdmi_rk3328_read_hpd(struct dw_hdmi *dw_hdmi, void *data) { @@ -370,6 +392,29 @@ static void dw_hdmi_rk3328_setup_hpd(struct dw_hdmi *dw_hdmi, void *data) RK3328_HDMI_HPD_IOE)); } +static const struct dw_hdmi_phy_ops rk3228_hdmi_phy_ops = { + .init = dw_hdmi_rockchip_genphy_init, + .disable = dw_hdmi_rockchip_genphy_disable, + .read_hpd = dw_hdmi_phy_read_hpd, + .update_hpd = dw_hdmi_phy_update_hpd, + .setup_hpd = dw_hdmi_rk3228_setup_hpd, +}; + +static struct rockchip_hdmi_chip_data rk3228_chip_data = { + .lcdsel_grf_reg = -1, +}; + +static const struct dw_hdmi_plat_data rk3228_hdmi_drv_data = { + .mode_valid = dw_hdmi_rockchip_mode_valid, + .mpll_cfg = rockchip_mpll_cfg, + .cur_ctr = rockchip_cur_ctr, + .phy_config = rockchip_phy_config, + .phy_data = &rk3228_chip_data, + .phy_ops = &rk3228_hdmi_phy_ops, + .phy_name = "inno_dw_hdmi_phy2", + .phy_force_vendor = true, +}; + static struct rockchip_hdmi_chip_data rk3288_chip_data = { .lcdsel_grf_reg = RK3288_GRF_SOC_CON6, .lcdsel_big = HIWORD_UPDATE(0, RK3288_HDMI_LCDC_SEL), @@ -405,6 +450,7 @@ static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = { .phy_ops = &rk3328_hdmi_phy_ops, .phy_name = "inno_dw_hdmi_phy2", .phy_force_vendor = true, + .use_drm_infoframe = true, }; static struct rockchip_hdmi_chip_data rk3399_chip_data = { @@ -419,9 +465,13 @@ static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = { .cur_ctr = rockchip_cur_ctr, .phy_config = rockchip_phy_config, .phy_data = &rk3399_chip_data, + .use_drm_infoframe = true, }; static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = { + { .compatible = "rockchip,rk3228-dw-hdmi", + .data = &rk3228_hdmi_drv_data + }, { .compatible = "rockchip,rk3288-dw-hdmi", .data = &rk3288_hdmi_drv_data }, @@ -542,11 +592,25 @@ static int dw_hdmi_rockchip_remove(struct platform_device *pdev) return 0; } +static int __maybe_unused dw_hdmi_rockchip_resume(struct device *dev) +{ + struct rockchip_hdmi *hdmi = dev_get_drvdata(dev); + + dw_hdmi_resume(hdmi->hdmi); + + return 0; +} + +static const struct dev_pm_ops dw_hdmi_rockchip_pm = { + SET_SYSTEM_SLEEP_PM_OPS(NULL, dw_hdmi_rockchip_resume) +}; + struct platform_driver dw_hdmi_rockchip_pltfm_driver = { .probe = dw_hdmi_rockchip_probe, .remove = dw_hdmi_rockchip_remove, .driver = { .name = "dwhdmi-rockchip", + .pm = &dw_hdmi_rockchip_pm, .of_match_table = dw_hdmi_rockchip_dt_ids, }, }; diff --git a/drivers/gpu/drm/rockchip/inno_hdmi.c b/drivers/gpu/drm/rockchip/inno_hdmi.c index ce1545862b6c..ed344a795b4d 100644 --- a/drivers/gpu/drm/rockchip/inno_hdmi.c +++ b/drivers/gpu/drm/rockchip/inno_hdmi.c @@ -1,16 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd * Zheng Yang <[email protected]> * Yakir Yang <[email protected]> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include <linux/irq.h> @@ -23,10 +15,9 @@ #include <linux/mutex.h> #include <linux/of_device.h> -#include <drm/drm_of.h> -#include <drm/drmP.h> #include <drm/drm_atomic_helper.h> #include <drm/drm_edid.h> +#include <drm/drm_of.h> #include <drm/drm_probe_helper.h> #include "rockchip_drm_drv.h" diff --git a/drivers/gpu/drm/rockchip/inno_hdmi.h b/drivers/gpu/drm/rockchip/inno_hdmi.h index aa7c415f8cc1..93245b55f967 100644 --- a/drivers/gpu/drm/rockchip/inno_hdmi.h +++ b/drivers/gpu/drm/rockchip/inno_hdmi.h @@ -1,16 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd * Zheng Yang <[email protected]> * Yakir Yang <[email protected]> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #ifndef __INNO_HDMI_H__ diff --git a/drivers/gpu/drm/rockchip/rk3066_hdmi.c b/drivers/gpu/drm/rockchip/rk3066_hdmi.c new file mode 100644 index 000000000000..cdb401f4283d --- /dev/null +++ b/drivers/gpu/drm/rockchip/rk3066_hdmi.c @@ -0,0 +1,870 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd + * Zheng Yang <[email protected]> + */ + +#include <drm/drm_of.h> +#include <drm/drm_probe_helper.h> + +#include <linux/clk.h> +#include <linux/mfd/syscon.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> + +#include "rk3066_hdmi.h" + +#include "rockchip_drm_drv.h" +#include "rockchip_drm_vop.h" + +#define DEFAULT_PLLA_RATE 30000000 + +struct hdmi_data_info { + int vic; /* The CEA Video ID (VIC) of the current drm display mode. */ + bool sink_is_hdmi; + unsigned int enc_out_format; + unsigned int colorimetry; +}; + +struct rk3066_hdmi_i2c { + struct i2c_adapter adap; + + u8 ddc_addr; + u8 segment_addr; + u8 stat; + + struct mutex i2c_lock; /* For i2c operation. */ + struct completion cmpltn; +}; + +struct rk3066_hdmi { + struct device *dev; + struct drm_device *drm_dev; + struct regmap *grf_regmap; + int irq; + struct clk *hclk; + void __iomem *regs; + + struct drm_connector connector; + struct drm_encoder encoder; + + struct rk3066_hdmi_i2c *i2c; + struct i2c_adapter *ddc; + + unsigned int tmdsclk; + + struct hdmi_data_info hdmi_data; + struct drm_display_mode previous_mode; +}; + +#define to_rk3066_hdmi(x) container_of(x, struct rk3066_hdmi, x) + +static inline u8 hdmi_readb(struct rk3066_hdmi *hdmi, u16 offset) +{ + return readl_relaxed(hdmi->regs + offset); +} + +static inline void hdmi_writeb(struct rk3066_hdmi *hdmi, u16 offset, u32 val) +{ + writel_relaxed(val, hdmi->regs + offset); +} + +static inline void hdmi_modb(struct rk3066_hdmi *hdmi, u16 offset, + u32 msk, u32 val) +{ + u8 temp = hdmi_readb(hdmi, offset) & ~msk; + + temp |= val & msk; + hdmi_writeb(hdmi, offset, temp); +} + +static void rk3066_hdmi_i2c_init(struct rk3066_hdmi *hdmi) +{ + int ddc_bus_freq; + + ddc_bus_freq = (hdmi->tmdsclk >> 2) / HDMI_SCL_RATE; + + hdmi_writeb(hdmi, HDMI_DDC_BUS_FREQ_L, ddc_bus_freq & 0xFF); + hdmi_writeb(hdmi, HDMI_DDC_BUS_FREQ_H, (ddc_bus_freq >> 8) & 0xFF); + + /* Clear the EDID interrupt flag and mute the interrupt. */ + hdmi_modb(hdmi, HDMI_INTR_MASK1, HDMI_INTR_EDID_MASK, 0); + hdmi_writeb(hdmi, HDMI_INTR_STATUS1, HDMI_INTR_EDID_MASK); +} + +static inline u8 rk3066_hdmi_get_power_mode(struct rk3066_hdmi *hdmi) +{ + return hdmi_readb(hdmi, HDMI_SYS_CTRL) & HDMI_SYS_POWER_MODE_MASK; +} + +static void rk3066_hdmi_set_power_mode(struct rk3066_hdmi *hdmi, int mode) +{ + u8 current_mode, next_mode; + u8 i = 0; + + current_mode = rk3066_hdmi_get_power_mode(hdmi); + + DRM_DEV_DEBUG(hdmi->dev, "mode :%d\n", mode); + DRM_DEV_DEBUG(hdmi->dev, "current_mode :%d\n", current_mode); + + if (current_mode == mode) + return; + + do { + if (current_mode > mode) { + next_mode = current_mode / 2; + } else { + if (current_mode < HDMI_SYS_POWER_MODE_A) + next_mode = HDMI_SYS_POWER_MODE_A; + else + next_mode = current_mode * 2; + } + + DRM_DEV_DEBUG(hdmi->dev, "%d: next_mode :%d\n", i, next_mode); + + if (next_mode != HDMI_SYS_POWER_MODE_D) { + hdmi_modb(hdmi, HDMI_SYS_CTRL, + HDMI_SYS_POWER_MODE_MASK, next_mode); + } else { + hdmi_writeb(hdmi, HDMI_SYS_CTRL, + HDMI_SYS_POWER_MODE_D | + HDMI_SYS_PLL_RESET_MASK); + usleep_range(90, 100); + hdmi_writeb(hdmi, HDMI_SYS_CTRL, + HDMI_SYS_POWER_MODE_D | + HDMI_SYS_PLLB_RESET); + usleep_range(90, 100); + hdmi_writeb(hdmi, HDMI_SYS_CTRL, + HDMI_SYS_POWER_MODE_D); + } + current_mode = next_mode; + i = i + 1; + } while ((next_mode != mode) && (i < 5)); + + /* + * When the IP controller isn't configured with accurate video timing, + * DDC_CLK should be equal to the PLLA frequency, which is 30MHz, + * so we need to init the TMDS rate to the PCLK rate and reconfigure + * the DDC clock. + */ + if (mode < HDMI_SYS_POWER_MODE_D) + hdmi->tmdsclk = DEFAULT_PLLA_RATE; +} + +static int +rk3066_hdmi_upload_frame(struct rk3066_hdmi *hdmi, int setup_rc, + union hdmi_infoframe *frame, u32 frame_index, + u32 mask, u32 disable, u32 enable) +{ + if (mask) + hdmi_modb(hdmi, HDMI_CP_AUTO_SEND_CTRL, mask, disable); + + hdmi_writeb(hdmi, HDMI_CP_BUF_INDEX, frame_index); + + if (setup_rc >= 0) { + u8 packed_frame[HDMI_MAXIMUM_INFO_FRAME_SIZE]; + ssize_t rc, i; + + rc = hdmi_infoframe_pack(frame, packed_frame, + sizeof(packed_frame)); + if (rc < 0) + return rc; + + for (i = 0; i < rc; i++) + hdmi_writeb(hdmi, HDMI_CP_BUF_ACC_HB0 + i * 4, + packed_frame[i]); + + if (mask) + hdmi_modb(hdmi, HDMI_CP_AUTO_SEND_CTRL, mask, enable); + } + + return setup_rc; +} + +static int rk3066_hdmi_config_avi(struct rk3066_hdmi *hdmi, + struct drm_display_mode *mode) +{ + union hdmi_infoframe frame; + int rc; + + rc = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, + &hdmi->connector, mode); + + if (hdmi->hdmi_data.enc_out_format == HDMI_COLORSPACE_YUV444) + frame.avi.colorspace = HDMI_COLORSPACE_YUV444; + else if (hdmi->hdmi_data.enc_out_format == HDMI_COLORSPACE_YUV422) + frame.avi.colorspace = HDMI_COLORSPACE_YUV422; + else + frame.avi.colorspace = HDMI_COLORSPACE_RGB; + + frame.avi.colorimetry = hdmi->hdmi_data.colorimetry; + frame.avi.scan_mode = HDMI_SCAN_MODE_NONE; + + return rk3066_hdmi_upload_frame(hdmi, rc, &frame, + HDMI_INFOFRAME_AVI, 0, 0, 0); +} + +static int rk3066_hdmi_config_video_timing(struct rk3066_hdmi *hdmi, + struct drm_display_mode *mode) +{ + int value, vsync_offset; + + /* Set the details for the external polarity and interlace mode. */ + value = HDMI_EXT_VIDEO_SET_EN; + value |= mode->flags & DRM_MODE_FLAG_PHSYNC ? + HDMI_VIDEO_HSYNC_ACTIVE_HIGH : HDMI_VIDEO_HSYNC_ACTIVE_LOW; + value |= mode->flags & DRM_MODE_FLAG_PVSYNC ? + HDMI_VIDEO_VSYNC_ACTIVE_HIGH : HDMI_VIDEO_VSYNC_ACTIVE_LOW; + value |= mode->flags & DRM_MODE_FLAG_INTERLACE ? + HDMI_VIDEO_MODE_INTERLACE : HDMI_VIDEO_MODE_PROGRESSIVE; + + if (hdmi->hdmi_data.vic == 2 || hdmi->hdmi_data.vic == 3) + vsync_offset = 6; + else + vsync_offset = 0; + + value |= vsync_offset << HDMI_VIDEO_VSYNC_OFFSET_SHIFT; + hdmi_writeb(hdmi, HDMI_EXT_VIDEO_PARA, value); + + /* Set the details for the external video timing. */ + value = mode->htotal; + hdmi_writeb(hdmi, HDMI_EXT_HTOTAL_L, value & 0xFF); + hdmi_writeb(hdmi, HDMI_EXT_HTOTAL_H, (value >> 8) & 0xFF); + + value = mode->htotal - mode->hdisplay; + hdmi_writeb(hdmi, HDMI_EXT_HBLANK_L, value & 0xFF); + hdmi_writeb(hdmi, HDMI_EXT_HBLANK_H, (value >> 8) & 0xFF); + + value = mode->htotal - mode->hsync_start; + hdmi_writeb(hdmi, HDMI_EXT_HDELAY_L, value & 0xFF); + hdmi_writeb(hdmi, HDMI_EXT_HDELAY_H, (value >> 8) & 0xFF); + + value = mode->hsync_end - mode->hsync_start; + hdmi_writeb(hdmi, HDMI_EXT_HDURATION_L, value & 0xFF); + hdmi_writeb(hdmi, HDMI_EXT_HDURATION_H, (value >> 8) & 0xFF); + + value = mode->vtotal; + hdmi_writeb(hdmi, HDMI_EXT_VTOTAL_L, value & 0xFF); + hdmi_writeb(hdmi, HDMI_EXT_VTOTAL_H, (value >> 8) & 0xFF); + + value = mode->vtotal - mode->vdisplay; + hdmi_writeb(hdmi, HDMI_EXT_VBLANK_L, value & 0xFF); + + value = mode->vtotal - mode->vsync_start + vsync_offset; + hdmi_writeb(hdmi, HDMI_EXT_VDELAY, value & 0xFF); + + value = mode->vsync_end - mode->vsync_start; + hdmi_writeb(hdmi, HDMI_EXT_VDURATION, value & 0xFF); + + return 0; +} + +static void +rk3066_hdmi_phy_write(struct rk3066_hdmi *hdmi, u16 offset, u8 value) +{ + hdmi_writeb(hdmi, offset, value); + hdmi_modb(hdmi, HDMI_SYS_CTRL, + HDMI_SYS_PLL_RESET_MASK, HDMI_SYS_PLL_RESET); + usleep_range(90, 100); + hdmi_modb(hdmi, HDMI_SYS_CTRL, HDMI_SYS_PLL_RESET_MASK, 0); + usleep_range(900, 1000); +} + +static void rk3066_hdmi_config_phy(struct rk3066_hdmi *hdmi) +{ + /* TMDS uses the same frequency as dclk. */ + hdmi_writeb(hdmi, HDMI_DEEP_COLOR_MODE, 0x22); + + /* + * The semi-public documentation does not describe the hdmi registers + * used by the function rk3066_hdmi_phy_write(), so we keep using + * these magic values for now. + */ + if (hdmi->tmdsclk > 100000000) { + rk3066_hdmi_phy_write(hdmi, 0x158, 0x0E); + rk3066_hdmi_phy_write(hdmi, 0x15c, 0x00); + rk3066_hdmi_phy_write(hdmi, 0x160, 0x60); + rk3066_hdmi_phy_write(hdmi, 0x164, 0x00); + rk3066_hdmi_phy_write(hdmi, 0x168, 0xDA); + rk3066_hdmi_phy_write(hdmi, 0x16c, 0xA1); + rk3066_hdmi_phy_write(hdmi, 0x170, 0x0e); + rk3066_hdmi_phy_write(hdmi, 0x174, 0x22); + rk3066_hdmi_phy_write(hdmi, 0x178, 0x00); + } else if (hdmi->tmdsclk > 50000000) { + rk3066_hdmi_phy_write(hdmi, 0x158, 0x06); + rk3066_hdmi_phy_write(hdmi, 0x15c, 0x00); + rk3066_hdmi_phy_write(hdmi, 0x160, 0x60); + rk3066_hdmi_phy_write(hdmi, 0x164, 0x00); + rk3066_hdmi_phy_write(hdmi, 0x168, 0xCA); + rk3066_hdmi_phy_write(hdmi, 0x16c, 0xA3); + rk3066_hdmi_phy_write(hdmi, 0x170, 0x0e); + rk3066_hdmi_phy_write(hdmi, 0x174, 0x20); + rk3066_hdmi_phy_write(hdmi, 0x178, 0x00); + } else { + rk3066_hdmi_phy_write(hdmi, 0x158, 0x02); + rk3066_hdmi_phy_write(hdmi, 0x15c, 0x00); + rk3066_hdmi_phy_write(hdmi, 0x160, 0x60); + rk3066_hdmi_phy_write(hdmi, 0x164, 0x00); + rk3066_hdmi_phy_write(hdmi, 0x168, 0xC2); + rk3066_hdmi_phy_write(hdmi, 0x16c, 0xA2); + rk3066_hdmi_phy_write(hdmi, 0x170, 0x0e); + rk3066_hdmi_phy_write(hdmi, 0x174, 0x20); + rk3066_hdmi_phy_write(hdmi, 0x178, 0x00); + } +} + +static int rk3066_hdmi_setup(struct rk3066_hdmi *hdmi, + struct drm_display_mode *mode) +{ + hdmi->hdmi_data.vic = drm_match_cea_mode(mode); + hdmi->hdmi_data.enc_out_format = HDMI_COLORSPACE_RGB; + + if (hdmi->hdmi_data.vic == 6 || hdmi->hdmi_data.vic == 7 || + hdmi->hdmi_data.vic == 21 || hdmi->hdmi_data.vic == 22 || + hdmi->hdmi_data.vic == 2 || hdmi->hdmi_data.vic == 3 || + hdmi->hdmi_data.vic == 17 || hdmi->hdmi_data.vic == 18) + hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601; + else + hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709; + + hdmi->tmdsclk = mode->clock * 1000; + + /* Mute video and audio output. */ + hdmi_modb(hdmi, HDMI_VIDEO_CTRL2, HDMI_VIDEO_AUDIO_DISABLE_MASK, + HDMI_AUDIO_DISABLE | HDMI_VIDEO_DISABLE); + + /* Set power state to mode B. */ + if (rk3066_hdmi_get_power_mode(hdmi) != HDMI_SYS_POWER_MODE_B) + rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_B); + + /* Input video mode is RGB 24 bit. Use external data enable signal. */ + hdmi_modb(hdmi, HDMI_AV_CTRL1, + HDMI_VIDEO_DE_MASK, HDMI_VIDEO_EXTERNAL_DE); + hdmi_writeb(hdmi, HDMI_VIDEO_CTRL1, + HDMI_VIDEO_OUTPUT_RGB444 | + HDMI_VIDEO_INPUT_DATA_DEPTH_8BIT | + HDMI_VIDEO_INPUT_COLOR_RGB); + hdmi_writeb(hdmi, HDMI_DEEP_COLOR_MODE, 0x20); + + rk3066_hdmi_config_video_timing(hdmi, mode); + + if (hdmi->hdmi_data.sink_is_hdmi) { + hdmi_modb(hdmi, HDMI_HDCP_CTRL, HDMI_VIDEO_MODE_MASK, + HDMI_VIDEO_MODE_HDMI); + rk3066_hdmi_config_avi(hdmi, mode); + } else { + hdmi_modb(hdmi, HDMI_HDCP_CTRL, HDMI_VIDEO_MODE_MASK, 0); + } + + rk3066_hdmi_config_phy(hdmi); + + rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_E); + + /* + * When the IP controller is configured with accurate video + * timing, the TMDS clock source should be switched to + * DCLK_LCDC, so we need to init the TMDS rate to the pixel mode + * clock rate and reconfigure the DDC clock. + */ + rk3066_hdmi_i2c_init(hdmi); + + /* Unmute video output. */ + hdmi_modb(hdmi, HDMI_VIDEO_CTRL2, + HDMI_VIDEO_AUDIO_DISABLE_MASK, HDMI_AUDIO_DISABLE); + return 0; +} + +static void +rk3066_hdmi_encoder_mode_set(struct drm_encoder *encoder, + struct drm_display_mode *mode, + struct drm_display_mode *adj_mode) +{ + struct rk3066_hdmi *hdmi = to_rk3066_hdmi(encoder); + + /* Store the display mode for plugin/DPMS poweron events. */ + memcpy(&hdmi->previous_mode, adj_mode, sizeof(hdmi->previous_mode)); +} + +static void rk3066_hdmi_encoder_enable(struct drm_encoder *encoder) +{ + struct rk3066_hdmi *hdmi = to_rk3066_hdmi(encoder); + int mux, val; + + mux = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder); + if (mux) + val = (HDMI_VIDEO_SEL << 16) | HDMI_VIDEO_SEL; + else + val = HDMI_VIDEO_SEL << 16; + + regmap_write(hdmi->grf_regmap, GRF_SOC_CON0, val); + + DRM_DEV_DEBUG(hdmi->dev, "hdmi encoder enable select: vop%s\n", + (mux) ? "1" : "0"); + + rk3066_hdmi_setup(hdmi, &hdmi->previous_mode); +} + +static void rk3066_hdmi_encoder_disable(struct drm_encoder *encoder) +{ + struct rk3066_hdmi *hdmi = to_rk3066_hdmi(encoder); + + DRM_DEV_DEBUG(hdmi->dev, "hdmi encoder disable\n"); + + if (rk3066_hdmi_get_power_mode(hdmi) == HDMI_SYS_POWER_MODE_E) { + hdmi_writeb(hdmi, HDMI_VIDEO_CTRL2, + HDMI_VIDEO_AUDIO_DISABLE_MASK); + hdmi_modb(hdmi, HDMI_VIDEO_CTRL2, + HDMI_AUDIO_CP_LOGIC_RESET_MASK, + HDMI_AUDIO_CP_LOGIC_RESET); + usleep_range(500, 510); + } + rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_A); +} + +static bool +rk3066_hdmi_encoder_mode_fixup(struct drm_encoder *encoder, + const struct drm_display_mode *mode, + struct drm_display_mode *adj_mode) +{ + return true; +} + +static int +rk3066_hdmi_encoder_atomic_check(struct drm_encoder *encoder, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); + + s->output_mode = ROCKCHIP_OUT_MODE_P888; + s->output_type = DRM_MODE_CONNECTOR_HDMIA; + + return 0; +} + +static const +struct drm_encoder_helper_funcs rk3066_hdmi_encoder_helper_funcs = { + .enable = rk3066_hdmi_encoder_enable, + .disable = rk3066_hdmi_encoder_disable, + .mode_fixup = rk3066_hdmi_encoder_mode_fixup, + .mode_set = rk3066_hdmi_encoder_mode_set, + .atomic_check = rk3066_hdmi_encoder_atomic_check, +}; + +static const struct drm_encoder_funcs rk3066_hdmi_encoder_funcs = { + .destroy = drm_encoder_cleanup, +}; + +static enum drm_connector_status +rk3066_hdmi_connector_detect(struct drm_connector *connector, bool force) +{ + struct rk3066_hdmi *hdmi = to_rk3066_hdmi(connector); + + return (hdmi_readb(hdmi, HDMI_HPG_MENS_STA) & HDMI_HPG_IN_STATUS_HIGH) ? + connector_status_connected : connector_status_disconnected; +} + +static int rk3066_hdmi_connector_get_modes(struct drm_connector *connector) +{ + struct rk3066_hdmi *hdmi = to_rk3066_hdmi(connector); + struct edid *edid; + int ret = 0; + + if (!hdmi->ddc) + return 0; + + edid = drm_get_edid(connector, hdmi->ddc); + if (edid) { + hdmi->hdmi_data.sink_is_hdmi = drm_detect_hdmi_monitor(edid); + drm_connector_update_edid_property(connector, edid); + ret = drm_add_edid_modes(connector, edid); + kfree(edid); + } + + return ret; +} + +static enum drm_mode_status +rk3066_hdmi_connector_mode_valid(struct drm_connector *connector, + struct drm_display_mode *mode) +{ + u32 vic = drm_match_cea_mode(mode); + + if (vic > 1) + return MODE_OK; + else + return MODE_BAD; +} + +static struct drm_encoder * +rk3066_hdmi_connector_best_encoder(struct drm_connector *connector) +{ + struct rk3066_hdmi *hdmi = to_rk3066_hdmi(connector); + + return &hdmi->encoder; +} + +static int +rk3066_hdmi_probe_single_connector_modes(struct drm_connector *connector, + uint32_t maxX, uint32_t maxY) +{ + if (maxX > 1920) + maxX = 1920; + if (maxY > 1080) + maxY = 1080; + + return drm_helper_probe_single_connector_modes(connector, maxX, maxY); +} + +static void rk3066_hdmi_connector_destroy(struct drm_connector *connector) +{ + drm_connector_unregister(connector); + drm_connector_cleanup(connector); +} + +static const struct drm_connector_funcs rk3066_hdmi_connector_funcs = { + .fill_modes = rk3066_hdmi_probe_single_connector_modes, + .detect = rk3066_hdmi_connector_detect, + .destroy = rk3066_hdmi_connector_destroy, + .reset = drm_atomic_helper_connector_reset, + .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, +}; + +static const +struct drm_connector_helper_funcs rk3066_hdmi_connector_helper_funcs = { + .get_modes = rk3066_hdmi_connector_get_modes, + .mode_valid = rk3066_hdmi_connector_mode_valid, + .best_encoder = rk3066_hdmi_connector_best_encoder, +}; + +static int +rk3066_hdmi_register(struct drm_device *drm, struct rk3066_hdmi *hdmi) +{ + struct drm_encoder *encoder = &hdmi->encoder; + struct device *dev = hdmi->dev; + + encoder->possible_crtcs = + drm_of_find_possible_crtcs(drm, dev->of_node); + + /* + * If we failed to find the CRTC(s) which this encoder is + * supposed to be connected to, it's because the CRTC has + * not been registered yet. Defer probing, and hope that + * the required CRTC is added later. + */ + if (encoder->possible_crtcs == 0) + return -EPROBE_DEFER; + + drm_encoder_helper_add(encoder, &rk3066_hdmi_encoder_helper_funcs); + drm_encoder_init(drm, encoder, &rk3066_hdmi_encoder_funcs, + DRM_MODE_ENCODER_TMDS, NULL); + + hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD; + + drm_connector_helper_add(&hdmi->connector, + &rk3066_hdmi_connector_helper_funcs); + drm_connector_init(drm, &hdmi->connector, + &rk3066_hdmi_connector_funcs, + DRM_MODE_CONNECTOR_HDMIA); + + drm_connector_attach_encoder(&hdmi->connector, encoder); + + return 0; +} + +static irqreturn_t rk3066_hdmi_hardirq(int irq, void *dev_id) +{ + struct rk3066_hdmi *hdmi = dev_id; + irqreturn_t ret = IRQ_NONE; + u8 interrupt; + + if (rk3066_hdmi_get_power_mode(hdmi) == HDMI_SYS_POWER_MODE_A) + hdmi_writeb(hdmi, HDMI_SYS_CTRL, HDMI_SYS_POWER_MODE_B); + + interrupt = hdmi_readb(hdmi, HDMI_INTR_STATUS1); + if (interrupt) + hdmi_writeb(hdmi, HDMI_INTR_STATUS1, interrupt); + + if (interrupt & HDMI_INTR_EDID_MASK) { + hdmi->i2c->stat = interrupt; + complete(&hdmi->i2c->cmpltn); + } + + if (interrupt & (HDMI_INTR_HOTPLUG | HDMI_INTR_MSENS)) + ret = IRQ_WAKE_THREAD; + + return ret; +} + +static irqreturn_t rk3066_hdmi_irq(int irq, void *dev_id) +{ + struct rk3066_hdmi *hdmi = dev_id; + + drm_helper_hpd_irq_event(hdmi->connector.dev); + + return IRQ_HANDLED; +} + +static int rk3066_hdmi_i2c_read(struct rk3066_hdmi *hdmi, struct i2c_msg *msgs) +{ + int length = msgs->len; + u8 *buf = msgs->buf; + int ret; + + ret = wait_for_completion_timeout(&hdmi->i2c->cmpltn, HZ / 10); + if (!ret || hdmi->i2c->stat & HDMI_INTR_EDID_ERR) + return -EAGAIN; + + while (length--) + *buf++ = hdmi_readb(hdmi, HDMI_DDC_READ_FIFO_ADDR); + + return 0; +} + +static int rk3066_hdmi_i2c_write(struct rk3066_hdmi *hdmi, struct i2c_msg *msgs) +{ + /* + * The DDC module only supports read EDID message, so + * we assume that each word write to this i2c adapter + * should be the offset of the EDID word address. + */ + if (msgs->len != 1 || + (msgs->addr != DDC_ADDR && msgs->addr != DDC_SEGMENT_ADDR)) + return -EINVAL; + + reinit_completion(&hdmi->i2c->cmpltn); + + if (msgs->addr == DDC_SEGMENT_ADDR) + hdmi->i2c->segment_addr = msgs->buf[0]; + if (msgs->addr == DDC_ADDR) + hdmi->i2c->ddc_addr = msgs->buf[0]; + + /* Set edid word address 0x00/0x80. */ + hdmi_writeb(hdmi, HDMI_EDID_WORD_ADDR, hdmi->i2c->ddc_addr); + + /* Set edid segment pointer. */ + hdmi_writeb(hdmi, HDMI_EDID_SEGMENT_POINTER, hdmi->i2c->segment_addr); + + return 0; +} + +static int rk3066_hdmi_i2c_xfer(struct i2c_adapter *adap, + struct i2c_msg *msgs, int num) +{ + struct rk3066_hdmi *hdmi = i2c_get_adapdata(adap); + struct rk3066_hdmi_i2c *i2c = hdmi->i2c; + int i, ret = 0; + + mutex_lock(&i2c->i2c_lock); + + rk3066_hdmi_i2c_init(hdmi); + + /* Unmute HDMI EDID interrupt. */ + hdmi_modb(hdmi, HDMI_INTR_MASK1, + HDMI_INTR_EDID_MASK, HDMI_INTR_EDID_MASK); + i2c->stat = 0; + + for (i = 0; i < num; i++) { + DRM_DEV_DEBUG(hdmi->dev, + "xfer: num: %d/%d, len: %d, flags: %#x\n", + i + 1, num, msgs[i].len, msgs[i].flags); + + if (msgs[i].flags & I2C_M_RD) + ret = rk3066_hdmi_i2c_read(hdmi, &msgs[i]); + else + ret = rk3066_hdmi_i2c_write(hdmi, &msgs[i]); + + if (ret < 0) + break; + } + + if (!ret) + ret = num; + + /* Mute HDMI EDID interrupt. */ + hdmi_modb(hdmi, HDMI_INTR_MASK1, HDMI_INTR_EDID_MASK, 0); + + mutex_unlock(&i2c->i2c_lock); + + return ret; +} + +static u32 rk3066_hdmi_i2c_func(struct i2c_adapter *adapter) +{ + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; +} + +static const struct i2c_algorithm rk3066_hdmi_algorithm = { + .master_xfer = rk3066_hdmi_i2c_xfer, + .functionality = rk3066_hdmi_i2c_func, +}; + +static struct i2c_adapter *rk3066_hdmi_i2c_adapter(struct rk3066_hdmi *hdmi) +{ + struct i2c_adapter *adap; + struct rk3066_hdmi_i2c *i2c; + int ret; + + i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL); + if (!i2c) + return ERR_PTR(-ENOMEM); + + mutex_init(&i2c->i2c_lock); + init_completion(&i2c->cmpltn); + + adap = &i2c->adap; + adap->class = I2C_CLASS_DDC; + adap->owner = THIS_MODULE; + adap->dev.parent = hdmi->dev; + adap->dev.of_node = hdmi->dev->of_node; + adap->algo = &rk3066_hdmi_algorithm; + strlcpy(adap->name, "RK3066 HDMI", sizeof(adap->name)); + i2c_set_adapdata(adap, hdmi); + + ret = i2c_add_adapter(adap); + if (ret) { + DRM_DEV_ERROR(hdmi->dev, "cannot add %s I2C adapter\n", + adap->name); + devm_kfree(hdmi->dev, i2c); + return ERR_PTR(ret); + } + + hdmi->i2c = i2c; + + DRM_DEV_DEBUG(hdmi->dev, "registered %s I2C bus driver\n", adap->name); + + return adap; +} + +static int rk3066_hdmi_bind(struct device *dev, struct device *master, + void *data) +{ + struct platform_device *pdev = to_platform_device(dev); + struct drm_device *drm = data; + struct rk3066_hdmi *hdmi; + int irq; + int ret; + + hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); + if (!hdmi) + return -ENOMEM; + + hdmi->dev = dev; + hdmi->drm_dev = drm; + hdmi->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(hdmi->regs)) + return PTR_ERR(hdmi->regs); + + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + hdmi->hclk = devm_clk_get(dev, "hclk"); + if (IS_ERR(hdmi->hclk)) { + DRM_DEV_ERROR(dev, "unable to get HDMI hclk clock\n"); + return PTR_ERR(hdmi->hclk); + } + + ret = clk_prepare_enable(hdmi->hclk); + if (ret) { + DRM_DEV_ERROR(dev, "cannot enable HDMI hclk clock: %d\n", ret); + return ret; + } + + hdmi->grf_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, + "rockchip,grf"); + if (IS_ERR(hdmi->grf_regmap)) { + DRM_DEV_ERROR(dev, "unable to get rockchip,grf\n"); + ret = PTR_ERR(hdmi->grf_regmap); + goto err_disable_hclk; + } + + /* internal hclk = hdmi_hclk / 25 */ + hdmi_writeb(hdmi, HDMI_INTERNAL_CLK_DIVIDER, 25); + + hdmi->ddc = rk3066_hdmi_i2c_adapter(hdmi); + if (IS_ERR(hdmi->ddc)) { + ret = PTR_ERR(hdmi->ddc); + hdmi->ddc = NULL; + goto err_disable_hclk; + } + + rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_B); + usleep_range(999, 1000); + hdmi_writeb(hdmi, HDMI_INTR_MASK1, HDMI_INTR_HOTPLUG); + hdmi_writeb(hdmi, HDMI_INTR_MASK2, 0); + hdmi_writeb(hdmi, HDMI_INTR_MASK3, 0); + hdmi_writeb(hdmi, HDMI_INTR_MASK4, 0); + rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_A); + + ret = rk3066_hdmi_register(drm, hdmi); + if (ret) + goto err_disable_i2c; + + dev_set_drvdata(dev, hdmi); + + ret = devm_request_threaded_irq(dev, irq, rk3066_hdmi_hardirq, + rk3066_hdmi_irq, IRQF_SHARED, + dev_name(dev), hdmi); + if (ret) { + DRM_DEV_ERROR(dev, "failed to request hdmi irq: %d\n", ret); + goto err_cleanup_hdmi; + } + + return 0; + +err_cleanup_hdmi: + hdmi->connector.funcs->destroy(&hdmi->connector); + hdmi->encoder.funcs->destroy(&hdmi->encoder); +err_disable_i2c: + i2c_put_adapter(hdmi->ddc); +err_disable_hclk: + clk_disable_unprepare(hdmi->hclk); + + return ret; +} + +static void rk3066_hdmi_unbind(struct device *dev, struct device *master, + void *data) +{ + struct rk3066_hdmi *hdmi = dev_get_drvdata(dev); + + hdmi->connector.funcs->destroy(&hdmi->connector); + hdmi->encoder.funcs->destroy(&hdmi->encoder); + + i2c_put_adapter(hdmi->ddc); + clk_disable_unprepare(hdmi->hclk); +} + +static const struct component_ops rk3066_hdmi_ops = { + .bind = rk3066_hdmi_bind, + .unbind = rk3066_hdmi_unbind, +}; + +static int rk3066_hdmi_probe(struct platform_device *pdev) +{ + return component_add(&pdev->dev, &rk3066_hdmi_ops); +} + +static int rk3066_hdmi_remove(struct platform_device *pdev) +{ + component_del(&pdev->dev, &rk3066_hdmi_ops); + + return 0; +} + +static const struct of_device_id rk3066_hdmi_dt_ids[] = { + { .compatible = "rockchip,rk3066-hdmi" }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, rk3066_hdmi_dt_ids); + +struct platform_driver rk3066_hdmi_driver = { + .probe = rk3066_hdmi_probe, + .remove = rk3066_hdmi_remove, + .driver = { + .name = "rockchip-rk3066-hdmi", + .of_match_table = rk3066_hdmi_dt_ids, + }, +}; diff --git a/drivers/gpu/drm/rockchip/rk3066_hdmi.h b/drivers/gpu/drm/rockchip/rk3066_hdmi.h new file mode 100644 index 000000000000..39a31c62a428 --- /dev/null +++ b/drivers/gpu/drm/rockchip/rk3066_hdmi.h @@ -0,0 +1,229 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd + * Zheng Yang <[email protected]> + */ + +#ifndef __RK3066_HDMI_H__ +#define __RK3066_HDMI_H__ + +#define GRF_SOC_CON0 0x150 +#define HDMI_VIDEO_SEL BIT(14) + +#define DDC_SEGMENT_ADDR 0x30 +#define HDMI_SCL_RATE (50 * 1000) +#define HDMI_MAXIMUM_INFO_FRAME_SIZE 0x11 + +#define N_32K 0x1000 +#define N_441K 0x1880 +#define N_882K 0x3100 +#define N_1764K 0x6200 +#define N_48K 0x1800 +#define N_96K 0x3000 +#define N_192K 0x6000 + +#define HDMI_SYS_CTRL 0x000 +#define HDMI_LR_SWAP_N3 0x004 +#define HDMI_N2 0x008 +#define HDMI_N1 0x00c +#define HDMI_SPDIF_FS_CTS_INT3 0x010 +#define HDMI_CTS_INT2 0x014 +#define HDMI_CTS_INT1 0x018 +#define HDMI_CTS_EXT3 0x01c +#define HDMI_CTS_EXT2 0x020 +#define HDMI_CTS_EXT1 0x024 +#define HDMI_AUDIO_CTRL1 0x028 +#define HDMI_AUDIO_CTRL2 0x02c +#define HDMI_I2S_AUDIO_CTRL 0x030 +#define HDMI_I2S_SWAP 0x040 +#define HDMI_AUDIO_STA_BIT_CTRL1 0x044 +#define HDMI_AUDIO_STA_BIT_CTRL2 0x048 +#define HDMI_AUDIO_SRC_NUM_AND_LENGTH 0x050 +#define HDMI_AV_CTRL1 0x054 +#define HDMI_VIDEO_CTRL1 0x058 +#define HDMI_DEEP_COLOR_MODE 0x05c + +#define HDMI_EXT_VIDEO_PARA 0x0c0 +#define HDMI_EXT_HTOTAL_L 0x0c4 +#define HDMI_EXT_HTOTAL_H 0x0c8 +#define HDMI_EXT_HBLANK_L 0x0cc +#define HDMI_EXT_HBLANK_H 0x0d0 +#define HDMI_EXT_HDELAY_L 0x0d4 +#define HDMI_EXT_HDELAY_H 0x0d8 +#define HDMI_EXT_HDURATION_L 0x0dc +#define HDMI_EXT_HDURATION_H 0x0e0 +#define HDMI_EXT_VTOTAL_L 0x0e4 +#define HDMI_EXT_VTOTAL_H 0x0e8 +#define HDMI_AV_CTRL2 0x0ec +#define HDMI_EXT_VBLANK_L 0x0f4 +#define HDMI_EXT_VBLANK_H 0x10c +#define HDMI_EXT_VDELAY 0x0f8 +#define HDMI_EXT_VDURATION 0x0fc + +#define HDMI_CP_MANU_SEND_CTRL 0x100 +#define HDMI_CP_AUTO_SEND_CTRL 0x104 +#define HDMI_AUTO_CHECKSUM_OPT 0x108 + +#define HDMI_VIDEO_CTRL2 0x114 + +#define HDMI_PHY_OPTION 0x144 + +#define HDMI_CP_BUF_INDEX 0x17c +#define HDMI_CP_BUF_ACC_HB0 0x180 +#define HDMI_CP_BUF_ACC_HB1 0x184 +#define HDMI_CP_BUF_ACC_HB2 0x188 +#define HDMI_CP_BUF_ACC_PB0 0x18c + +#define HDMI_DDC_READ_FIFO_ADDR 0x200 +#define HDMI_DDC_BUS_FREQ_L 0x204 +#define HDMI_DDC_BUS_FREQ_H 0x208 +#define HDMI_DDC_BUS_CTRL 0x2dc +#define HDMI_DDC_I2C_LEN 0x278 +#define HDMI_DDC_I2C_OFFSET 0x280 +#define HDMI_DDC_I2C_CTRL 0x284 +#define HDMI_DDC_I2C_READ_BUF0 0x288 +#define HDMI_DDC_I2C_READ_BUF1 0x28c +#define HDMI_DDC_I2C_READ_BUF2 0x290 +#define HDMI_DDC_I2C_READ_BUF3 0x294 +#define HDMI_DDC_I2C_WRITE_BUF0 0x298 +#define HDMI_DDC_I2C_WRITE_BUF1 0x29c +#define HDMI_DDC_I2C_WRITE_BUF2 0x2a0 +#define HDMI_DDC_I2C_WRITE_BUF3 0x2a4 +#define HDMI_DDC_I2C_WRITE_BUF4 0x2ac +#define HDMI_DDC_I2C_WRITE_BUF5 0x2b0 +#define HDMI_DDC_I2C_WRITE_BUF6 0x2b4 + +#define HDMI_INTR_MASK1 0x248 +#define HDMI_INTR_MASK2 0x24c +#define HDMI_INTR_STATUS1 0x250 +#define HDMI_INTR_STATUS2 0x254 +#define HDMI_INTR_MASK3 0x258 +#define HDMI_INTR_MASK4 0x25c +#define HDMI_INTR_STATUS3 0x260 +#define HDMI_INTR_STATUS4 0x264 + +#define HDMI_HDCP_CTRL 0x2bc + +#define HDMI_EDID_SEGMENT_POINTER 0x310 +#define HDMI_EDID_WORD_ADDR 0x314 +#define HDMI_EDID_FIFO_ADDR 0x318 + +#define HDMI_HPG_MENS_STA 0x37c + +#define HDMI_INTERNAL_CLK_DIVIDER 0x800 + +enum { + /* HDMI_SYS_CTRL */ + HDMI_SYS_POWER_MODE_MASK = 0xf0, + HDMI_SYS_POWER_MODE_A = 0x10, + HDMI_SYS_POWER_MODE_B = 0x20, + HDMI_SYS_POWER_MODE_D = 0x40, + HDMI_SYS_POWER_MODE_E = 0x80, + HDMI_SYS_PLL_RESET_MASK = 0x0c, + HDMI_SYS_PLL_RESET = 0x0c, + HDMI_SYS_PLLB_RESET = 0x08, + + /* HDMI_LR_SWAP_N3 */ + HDMI_AUDIO_LR_SWAP_MASK = 0xf0, + HDMI_AUDIO_LR_SWAP_SUBPACKET0 = 0x10, + HDMI_AUDIO_LR_SWAP_SUBPACKET1 = 0x20, + HDMI_AUDIO_LR_SWAP_SUBPACKET2 = 0x40, + HDMI_AUDIO_LR_SWAP_SUBPACKET3 = 0x80, + HDMI_AUDIO_N_19_16_MASK = 0x0f, + + /* HDMI_AUDIO_CTRL1 */ + HDMI_AUDIO_EXTERNAL_CTS = BIT(7), + HDMI_AUDIO_INPUT_IIS = 0, + HDMI_AUDIO_INPUT_SPDIF = 0x08, + HDMI_AUDIO_INPUT_MCLK_ACTIVE = 0x04, + HDMI_AUDIO_INPUT_MCLK_DEACTIVE = 0, + HDMI_AUDIO_INPUT_MCLK_RATE_128X = 0, + HDMI_AUDIO_INPUT_MCLK_RATE_256X = 1, + HDMI_AUDIO_INPUT_MCLK_RATE_384X = 2, + HDMI_AUDIO_INPUT_MCLK_RATE_512X = 3, + + /* HDMI_I2S_AUDIO_CTRL */ + HDMI_AUDIO_I2S_FORMAT_STANDARD = 0, + HDMI_AUDIO_I2S_CHANNEL_1_2 = 0x04, + HDMI_AUDIO_I2S_CHANNEL_3_4 = 0x0c, + HDMI_AUDIO_I2S_CHANNEL_5_6 = 0x1c, + HDMI_AUDIO_I2S_CHANNEL_7_8 = 0x3c, + + /* HDMI_AV_CTRL1 */ + HDMI_AUDIO_SAMPLE_FRE_MASK = 0xf0, + HDMI_AUDIO_SAMPLE_FRE_32000 = 0x30, + HDMI_AUDIO_SAMPLE_FRE_44100 = 0, + HDMI_AUDIO_SAMPLE_FRE_48000 = 0x20, + HDMI_AUDIO_SAMPLE_FRE_88200 = 0x80, + HDMI_AUDIO_SAMPLE_FRE_96000 = 0xa0, + HDMI_AUDIO_SAMPLE_FRE_176400 = 0xc0, + HDMI_AUDIO_SAMPLE_FRE_192000 = 0xe0, + HDMI_AUDIO_SAMPLE_FRE_768000 = 0x90, + + HDMI_VIDEO_INPUT_FORMAT_MASK = 0x0e, + HDMI_VIDEO_INPUT_RGB_YCBCR444 = 0, + HDMI_VIDEO_INPUT_YCBCR422 = 0x02, + HDMI_VIDEO_DE_MASK = 0x1, + HDMI_VIDEO_INTERNAL_DE = 0, + HDMI_VIDEO_EXTERNAL_DE = 0x01, + + /* HDMI_VIDEO_CTRL1 */ + HDMI_VIDEO_OUTPUT_FORMAT_MASK = 0xc0, + HDMI_VIDEO_OUTPUT_RGB444 = 0, + HDMI_VIDEO_OUTPUT_YCBCR444 = 0x40, + HDMI_VIDEO_OUTPUT_YCBCR422 = 0x80, + HDMI_VIDEO_INPUT_DATA_DEPTH_MASK = 0x30, + HDMI_VIDEO_INPUT_DATA_DEPTH_12BIT = 0, + HDMI_VIDEO_INPUT_DATA_DEPTH_10BIT = 0x10, + HDMI_VIDEO_INPUT_DATA_DEPTH_8BIT = 0x30, + HDMI_VIDEO_INPUT_COLOR_MASK = 1, + HDMI_VIDEO_INPUT_COLOR_RGB = 0, + HDMI_VIDEO_INPUT_COLOR_YCBCR = 1, + + /* HDMI_EXT_VIDEO_PARA */ + HDMI_VIDEO_VSYNC_OFFSET_SHIFT = 4, + HDMI_VIDEO_VSYNC_ACTIVE_HIGH = BIT(3), + HDMI_VIDEO_VSYNC_ACTIVE_LOW = 0, + HDMI_VIDEO_HSYNC_ACTIVE_HIGH = BIT(2), + HDMI_VIDEO_HSYNC_ACTIVE_LOW = 0, + HDMI_VIDEO_MODE_INTERLACE = BIT(1), + HDMI_VIDEO_MODE_PROGRESSIVE = 0, + HDMI_EXT_VIDEO_SET_EN = BIT(0), + + /* HDMI_CP_AUTO_SEND_CTRL */ + + /* HDMI_VIDEO_CTRL2 */ + HDMI_VIDEO_AV_MUTE_MASK = 0xc0, + HDMI_VIDEO_CLR_AV_MUTE = BIT(7), + HDMI_VIDEO_SET_AV_MUTE = BIT(6), + HDMI_AUDIO_CP_LOGIC_RESET_MASK = BIT(2), + HDMI_AUDIO_CP_LOGIC_RESET = BIT(2), + HDMI_VIDEO_AUDIO_DISABLE_MASK = 0x3, + HDMI_AUDIO_DISABLE = BIT(1), + HDMI_VIDEO_DISABLE = BIT(0), + + /* HDMI_CP_BUF_INDEX */ + HDMI_INFOFRAME_VSI = 0x05, + HDMI_INFOFRAME_AVI = 0x06, + HDMI_INFOFRAME_AAI = 0x08, + + /* HDMI_INTR_MASK1 */ + /* HDMI_INTR_STATUS1 */ + HDMI_INTR_HOTPLUG = BIT(7), + HDMI_INTR_MSENS = BIT(6), + HDMI_INTR_VSYNC = BIT(5), + HDMI_INTR_AUDIO_FIFO_FULL = BIT(4), + HDMI_INTR_EDID_MASK = 0x6, + HDMI_INTR_EDID_READY = BIT(2), + HDMI_INTR_EDID_ERR = BIT(1), + + /* HDMI_HDCP_CTRL */ + HDMI_VIDEO_MODE_MASK = BIT(1), + HDMI_VIDEO_MODE_HDMI = BIT(1), + + /* HDMI_HPG_MENS_STA */ + HDMI_HPG_IN_STATUS_HIGH = BIT(7), + HDMI_MSENS_IN_STATUS_HIGH = BIT(6), +}; + +#endif /* __RK3066_HDMI_H__ */ diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c index d7fa17f12769..20ecb1508a22 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c @@ -1,24 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd * Author:Mark Yao <[email protected]> * * based on exynos_drm_drv.c - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ -#include <drm/drmP.h> -#include <drm/drm_fb_helper.h> -#include <drm/drm_gem_cma_helper.h> -#include <drm/drm_of.h> -#include <drm/drm_probe_helper.h> #include <linux/dma-mapping.h> #include <linux/dma-iommu.h> #include <linux/pm_runtime.h> @@ -29,6 +16,13 @@ #include <linux/console.h> #include <linux/iommu.h> +#include <drm/drm_drv.h> +#include <drm/drm_fb_helper.h> +#include <drm/drm_gem_cma_helper.h> +#include <drm/drm_of.h> +#include <drm/drm_probe_helper.h> +#include <drm/drm_vblank.h> + #include "rockchip_drm_drv.h" #include "rockchip_drm_fb.h" #include "rockchip_drm_fbdev.h" @@ -220,16 +214,13 @@ static const struct file_operations rockchip_drm_driver_fops = { }; static struct drm_driver rockchip_drm_driver = { - .driver_features = DRIVER_MODESET | DRIVER_GEM | - DRIVER_PRIME | DRIVER_ATOMIC, + .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC, .lastclose = drm_fb_helper_lastclose, .gem_vm_ops = &drm_gem_cma_vm_ops, .gem_free_object_unlocked = rockchip_gem_free_object, .dumb_create = rockchip_gem_dumb_create, .prime_handle_to_fd = drm_gem_prime_handle_to_fd, .prime_fd_to_handle = drm_gem_prime_fd_to_handle, - .gem_prime_import = drm_gem_prime_import, - .gem_prime_export = drm_gem_prime_export, .gem_prime_get_sg_table = rockchip_gem_prime_get_sg_table, .gem_prime_import_sg_table = rockchip_gem_prime_import_sg_table, .gem_prime_vmap = rockchip_gem_prime_vmap, @@ -338,8 +329,7 @@ static struct component_match *rockchip_drm_match_add(struct device *dev) struct device *p = NULL, *d; do { - d = bus_find_device(&platform_bus_type, p, &drv->driver, - (void *)platform_bus_type.match); + d = platform_find_device_by_driver(p, &drv->driver); put_device(p); p = d; @@ -448,6 +438,14 @@ static int rockchip_drm_platform_remove(struct platform_device *pdev) return 0; } +static void rockchip_drm_platform_shutdown(struct platform_device *pdev) +{ + struct drm_device *drm = platform_get_drvdata(pdev); + + if (drm) + drm_atomic_helper_shutdown(drm); +} + static const struct of_device_id rockchip_drm_dt_ids[] = { { .compatible = "rockchip,display-subsystem", }, { /* sentinel */ }, @@ -457,6 +455,7 @@ MODULE_DEVICE_TABLE(of, rockchip_drm_dt_ids); static struct platform_driver rockchip_drm_platform_driver = { .probe = rockchip_drm_platform_probe, .remove = rockchip_drm_platform_remove, + .shutdown = rockchip_drm_platform_shutdown, .driver = { .name = "rockchip-drm", .of_match_table = rockchip_drm_dt_ids, @@ -486,6 +485,8 @@ static int __init rockchip_drm_init(void) ADD_ROCKCHIP_SUB_DRIVER(dw_mipi_dsi_rockchip_driver, CONFIG_ROCKCHIP_DW_MIPI_DSI); ADD_ROCKCHIP_SUB_DRIVER(inno_hdmi_driver, CONFIG_ROCKCHIP_INNO_HDMI); + ADD_ROCKCHIP_SUB_DRIVER(rk3066_hdmi_driver, + CONFIG_ROCKCHIP_RK3066_HDMI); ret = platform_register_drivers(rockchip_sub_drivers, num_rockchip_sub_drivers); diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h index ce48568ec8a0..c5b06048124e 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h @@ -1,17 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd * Author:Mark Yao <[email protected]> * * based on exynos_drm_drv.h - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #ifndef _ROCKCHIP_DRM_DRV_H @@ -73,4 +65,5 @@ extern struct platform_driver inno_hdmi_driver; extern struct platform_driver rockchip_dp_driver; extern struct platform_driver rockchip_lvds_driver; extern struct platform_driver vop_platform_driver; +extern struct platform_driver rk3066_hdmi_driver; #endif /* _ROCKCHIP_DRM_DRV_H_ */ diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_fb.c b/drivers/gpu/drm/rockchip/rockchip_drm_fb.c index 97438bbbe389..ca01234c037c 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_fb.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_fb.c @@ -1,44 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd * Author:Mark Yao <[email protected]> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include <linux/kernel.h> + #include <drm/drm.h> -#include <drm/drmP.h> #include <drm/drm_atomic.h> +#include <drm/drm_damage_helper.h> #include <drm/drm_fb_helper.h> +#include <drm/drm_fourcc.h> #include <drm/drm_gem_framebuffer_helper.h> #include <drm/drm_probe_helper.h> #include "rockchip_drm_drv.h" #include "rockchip_drm_fb.h" #include "rockchip_drm_gem.h" -#include "rockchip_drm_psr.h" - -static int rockchip_drm_fb_dirty(struct drm_framebuffer *fb, - struct drm_file *file, - unsigned int flags, unsigned int color, - struct drm_clip_rect *clips, - unsigned int num_clips) -{ - rockchip_drm_psr_flush_all(fb->dev); - return 0; -} static const struct drm_framebuffer_funcs rockchip_drm_fb_funcs = { .destroy = drm_gem_fb_destroy, .create_handle = drm_gem_fb_create_handle, - .dirty = rockchip_drm_fb_dirty, + .dirty = drm_atomic_helper_dirtyfb, }; static struct drm_framebuffer * @@ -74,23 +57,18 @@ static struct drm_framebuffer * rockchip_user_fb_create(struct drm_device *dev, struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd) { + const struct drm_format_info *info = drm_get_format_info(dev, + mode_cmd); struct drm_framebuffer *fb; struct drm_gem_object *objs[ROCKCHIP_MAX_FB_BUFFER]; struct drm_gem_object *obj; - unsigned int hsub; - unsigned int vsub; - int num_planes; + int num_planes = min_t(int, info->num_planes, ROCKCHIP_MAX_FB_BUFFER); int ret; int i; - hsub = drm_format_horz_chroma_subsampling(mode_cmd->pixel_format); - vsub = drm_format_vert_chroma_subsampling(mode_cmd->pixel_format); - num_planes = min(drm_format_num_planes(mode_cmd->pixel_format), - ROCKCHIP_MAX_FB_BUFFER); - for (i = 0; i < num_planes; i++) { - unsigned int width = mode_cmd->width / (i ? hsub : 1); - unsigned int height = mode_cmd->height / (i ? vsub : 1); + unsigned int width = mode_cmd->width / (i ? info->hsub : 1); + unsigned int height = mode_cmd->height / (i ? info->vsub : 1); unsigned int min_size; obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[i]); @@ -103,7 +81,7 @@ rockchip_user_fb_create(struct drm_device *dev, struct drm_file *file_priv, min_size = (height - 1) * mode_cmd->pitches[i] + mode_cmd->offsets[i] + - width * drm_format_plane_cpp(mode_cmd->pixel_format, i); + width * info->cpp[i]; if (obj->size < min_size) { drm_gem_object_put_unlocked(obj); @@ -127,31 +105,8 @@ err_gem_object_unreference: return ERR_PTR(ret); } -static void -rockchip_atomic_helper_commit_tail_rpm(struct drm_atomic_state *old_state) -{ - struct drm_device *dev = old_state->dev; - - rockchip_drm_psr_inhibit_get_state(old_state); - - drm_atomic_helper_commit_modeset_disables(dev, old_state); - - drm_atomic_helper_commit_modeset_enables(dev, old_state); - - drm_atomic_helper_commit_planes(dev, old_state, - DRM_PLANE_COMMIT_ACTIVE_ONLY); - - rockchip_drm_psr_inhibit_put_state(old_state); - - drm_atomic_helper_commit_hw_done(old_state); - - drm_atomic_helper_wait_for_vblanks(dev, old_state); - - drm_atomic_helper_cleanup_planes(dev, old_state); -} - static const struct drm_mode_config_helper_funcs rockchip_mode_config_helpers = { - .atomic_commit_tail = rockchip_atomic_helper_commit_tail_rpm, + .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm, }; static const struct drm_mode_config_funcs rockchip_drm_mode_config_funcs = { diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_fb.h b/drivers/gpu/drm/rockchip/rockchip_drm_fb.h index f1265cb1aee8..1a696521096d 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_fb.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_fb.h @@ -1,15 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd * Author:Mark Yao <[email protected]> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #ifndef _ROCKCHIP_DRM_FB_H diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c b/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c index 8ce68bd508be..02be6c5ff857 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c @@ -1,20 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd * Author:Mark Yao <[email protected]> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include <drm/drm.h> -#include <drm/drmP.h> #include <drm/drm_fb_helper.h> +#include <drm/drm_fourcc.h> #include <drm/drm_probe_helper.h> #include "rockchip_drm_drv.h" @@ -90,12 +82,10 @@ static int rockchip_drm_fbdev_create(struct drm_fb_helper *helper, goto out; } - fbi->par = helper; fbi->fbops = &rockchip_drm_fbdev_ops; fb = helper->fb; - drm_fb_helper_fill_fix(fbi, fb->pitches[0], fb->format->depth); - drm_fb_helper_fill_var(fbi, helper, sizes->fb_width, sizes->fb_height); + drm_fb_helper_fill_info(fbi, helper, sizes); offset = fbi->var.xoffset * bytes_per_pixel; offset += fbi->var.yoffset * fb->pitches[0]; @@ -110,8 +100,6 @@ static int rockchip_drm_fbdev_create(struct drm_fb_helper *helper, rk_obj->kvaddr, offset, size); - fbi->skip_vt_switch = true; - return 0; out: diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.h b/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.h index 73718c5f5bbf..5fb7ac2371a8 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.h @@ -1,15 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd * Author:Mark Yao <[email protected]> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #ifndef _ROCKCHIP_DRM_FBDEV_H diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c index a8db758d523e..7582d0e6a60a 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c @@ -1,25 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd * Author:Mark Yao <[email protected]> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ +#include <linux/dma-buf.h> +#include <linux/iommu.h> + #include <drm/drm.h> -#include <drm/drmP.h> #include <drm/drm_gem.h> +#include <drm/drm_prime.h> #include <drm/drm_vma_manager.h> -#include <linux/dma-buf.h> -#include <linux/iommu.h> - #include "rockchip_drm_drv.h" #include "rockchip_drm_gem.h" @@ -221,26 +213,13 @@ static int rockchip_drm_gem_object_mmap_iommu(struct drm_gem_object *obj, struct vm_area_struct *vma) { struct rockchip_gem_object *rk_obj = to_rockchip_obj(obj); - unsigned int i, count = obj->size >> PAGE_SHIFT; + unsigned int count = obj->size >> PAGE_SHIFT; unsigned long user_count = vma_pages(vma); - unsigned long uaddr = vma->vm_start; - unsigned long offset = vma->vm_pgoff; - unsigned long end = user_count + offset; - int ret; if (user_count == 0) return -ENXIO; - if (end > count) - return -ENXIO; - - for (i = offset; i < end; i++) { - ret = vm_insert_page(vma, uaddr, rk_obj->pages[i]); - if (ret) - return ret; - uaddr += PAGE_SIZE; - } - return 0; + return vm_map_pages(vma, rk_obj->pages, count); } static int rockchip_drm_gem_object_mmap_dma(struct drm_gem_object *obj, @@ -315,7 +294,7 @@ static void rockchip_gem_release_object(struct rockchip_gem_object *rk_obj) kfree(rk_obj); } -struct rockchip_gem_object * +static struct rockchip_gem_object * rockchip_gem_alloc_object(struct drm_device *drm, unsigned int size) { struct rockchip_gem_object *rk_obj; diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_gem.h b/drivers/gpu/drm/rockchip/rockchip_drm_gem.h index d41fa65219d2..7ffc541bea07 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_gem.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_gem.h @@ -1,15 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd * Author:Mark Yao <[email protected]> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #ifndef _ROCKCHIP_DRM_GEM_H diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_psr.c b/drivers/gpu/drm/rockchip/rockchip_drm_psr.c deleted file mode 100644 index a0c8bd235b67..000000000000 --- a/drivers/gpu/drm/rockchip/rockchip_drm_psr.c +++ /dev/null @@ -1,290 +0,0 @@ -/* - * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd - * Author: Yakir Yang <[email protected]> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <drm/drmP.h> -#include <drm/drm_atomic.h> -#include <drm/drm_probe_helper.h> - -#include "rockchip_drm_drv.h" -#include "rockchip_drm_psr.h" - -#define PSR_FLUSH_TIMEOUT_MS 100 - -struct psr_drv { - struct list_head list; - struct drm_encoder *encoder; - - struct mutex lock; - int inhibit_count; - bool enabled; - - struct delayed_work flush_work; - - int (*set)(struct drm_encoder *encoder, bool enable); -}; - -static struct psr_drv *find_psr_by_encoder(struct drm_encoder *encoder) -{ - struct rockchip_drm_private *drm_drv = encoder->dev->dev_private; - struct psr_drv *psr; - - mutex_lock(&drm_drv->psr_list_lock); - list_for_each_entry(psr, &drm_drv->psr_list, list) { - if (psr->encoder == encoder) - goto out; - } - psr = ERR_PTR(-ENODEV); - -out: - mutex_unlock(&drm_drv->psr_list_lock); - return psr; -} - -static int psr_set_state_locked(struct psr_drv *psr, bool enable) -{ - int ret; - - if (psr->inhibit_count > 0) - return -EINVAL; - - if (enable == psr->enabled) - return 0; - - ret = psr->set(psr->encoder, enable); - if (ret) - return ret; - - psr->enabled = enable; - return 0; -} - -static void psr_flush_handler(struct work_struct *work) -{ - struct psr_drv *psr = container_of(to_delayed_work(work), - struct psr_drv, flush_work); - - mutex_lock(&psr->lock); - psr_set_state_locked(psr, true); - mutex_unlock(&psr->lock); -} - -/** - * rockchip_drm_psr_inhibit_put - release PSR inhibit on given encoder - * @encoder: encoder to obtain the PSR encoder - * - * Decrements PSR inhibit count on given encoder. Should be called only - * for a PSR inhibit count increment done before. If PSR inhibit counter - * reaches zero, PSR flush work is scheduled to make the hardware enter - * PSR mode in PSR_FLUSH_TIMEOUT_MS. - * - * Returns: - * Zero on success, negative errno on failure. - */ -int rockchip_drm_psr_inhibit_put(struct drm_encoder *encoder) -{ - struct psr_drv *psr = find_psr_by_encoder(encoder); - - if (IS_ERR(psr)) - return PTR_ERR(psr); - - mutex_lock(&psr->lock); - --psr->inhibit_count; - WARN_ON(psr->inhibit_count < 0); - if (!psr->inhibit_count) - mod_delayed_work(system_wq, &psr->flush_work, - PSR_FLUSH_TIMEOUT_MS); - mutex_unlock(&psr->lock); - - return 0; -} -EXPORT_SYMBOL(rockchip_drm_psr_inhibit_put); - -void rockchip_drm_psr_inhibit_get_state(struct drm_atomic_state *state) -{ - struct drm_crtc *crtc; - struct drm_crtc_state *crtc_state; - struct drm_encoder *encoder; - u32 encoder_mask = 0; - int i; - - for_each_old_crtc_in_state(state, crtc, crtc_state, i) { - encoder_mask |= crtc_state->encoder_mask; - encoder_mask |= crtc->state->encoder_mask; - } - - drm_for_each_encoder_mask(encoder, state->dev, encoder_mask) - rockchip_drm_psr_inhibit_get(encoder); -} -EXPORT_SYMBOL(rockchip_drm_psr_inhibit_get_state); - -void rockchip_drm_psr_inhibit_put_state(struct drm_atomic_state *state) -{ - struct drm_crtc *crtc; - struct drm_crtc_state *crtc_state; - struct drm_encoder *encoder; - u32 encoder_mask = 0; - int i; - - for_each_old_crtc_in_state(state, crtc, crtc_state, i) { - encoder_mask |= crtc_state->encoder_mask; - encoder_mask |= crtc->state->encoder_mask; - } - - drm_for_each_encoder_mask(encoder, state->dev, encoder_mask) - rockchip_drm_psr_inhibit_put(encoder); -} -EXPORT_SYMBOL(rockchip_drm_psr_inhibit_put_state); - -/** - * rockchip_drm_psr_inhibit_get - acquire PSR inhibit on given encoder - * @encoder: encoder to obtain the PSR encoder - * - * Increments PSR inhibit count on given encoder. This function guarantees - * that after it returns PSR is turned off on given encoder and no PSR-related - * hardware state change occurs at least until a matching call to - * rockchip_drm_psr_inhibit_put() is done. - * - * Returns: - * Zero on success, negative errno on failure. - */ -int rockchip_drm_psr_inhibit_get(struct drm_encoder *encoder) -{ - struct psr_drv *psr = find_psr_by_encoder(encoder); - - if (IS_ERR(psr)) - return PTR_ERR(psr); - - mutex_lock(&psr->lock); - psr_set_state_locked(psr, false); - ++psr->inhibit_count; - mutex_unlock(&psr->lock); - cancel_delayed_work_sync(&psr->flush_work); - - return 0; -} -EXPORT_SYMBOL(rockchip_drm_psr_inhibit_get); - -static void rockchip_drm_do_flush(struct psr_drv *psr) -{ - cancel_delayed_work_sync(&psr->flush_work); - - mutex_lock(&psr->lock); - if (!psr_set_state_locked(psr, false)) - mod_delayed_work(system_wq, &psr->flush_work, - PSR_FLUSH_TIMEOUT_MS); - mutex_unlock(&psr->lock); -} - -/** - * rockchip_drm_psr_flush_all - force to flush all registered PSR encoders - * @dev: drm device - * - * Disable the PSR function for all registered encoders, and then enable the - * PSR function back after PSR_FLUSH_TIMEOUT. If encoder PSR state have been - * changed during flush time, then keep the state no change after flush - * timeout. - * - * Returns: - * Zero on success, negative errno on failure. - */ -void rockchip_drm_psr_flush_all(struct drm_device *dev) -{ - struct rockchip_drm_private *drm_drv = dev->dev_private; - struct psr_drv *psr; - - mutex_lock(&drm_drv->psr_list_lock); - list_for_each_entry(psr, &drm_drv->psr_list, list) - rockchip_drm_do_flush(psr); - mutex_unlock(&drm_drv->psr_list_lock); -} -EXPORT_SYMBOL(rockchip_drm_psr_flush_all); - -/** - * rockchip_drm_psr_register - register encoder to psr driver - * @encoder: encoder that obtain the PSR function - * @psr_set: call back to set PSR state - * - * The function returns with PSR inhibit counter initialized with one - * and the caller (typically encoder driver) needs to call - * rockchip_drm_psr_inhibit_put() when it becomes ready to accept PSR - * enable request. - * - * Returns: - * Zero on success, negative errno on failure. - */ -int rockchip_drm_psr_register(struct drm_encoder *encoder, - int (*psr_set)(struct drm_encoder *, bool enable)) -{ - struct rockchip_drm_private *drm_drv; - struct psr_drv *psr; - - if (!encoder || !psr_set) - return -EINVAL; - - drm_drv = encoder->dev->dev_private; - - psr = kzalloc(sizeof(struct psr_drv), GFP_KERNEL); - if (!psr) - return -ENOMEM; - - INIT_DELAYED_WORK(&psr->flush_work, psr_flush_handler); - mutex_init(&psr->lock); - - psr->inhibit_count = 1; - psr->enabled = false; - psr->encoder = encoder; - psr->set = psr_set; - - mutex_lock(&drm_drv->psr_list_lock); - list_add_tail(&psr->list, &drm_drv->psr_list); - mutex_unlock(&drm_drv->psr_list_lock); - - return 0; -} -EXPORT_SYMBOL(rockchip_drm_psr_register); - -/** - * rockchip_drm_psr_unregister - unregister encoder to psr driver - * @encoder: encoder that obtain the PSR function - * @psr_set: call back to set PSR state - * - * It is expected that the PSR inhibit counter is 1 when this function is - * called, which corresponds to a state when related encoder has been - * disconnected from any CRTCs and its driver called - * rockchip_drm_psr_inhibit_get() to stop the PSR logic. - * - * Returns: - * Zero on success, negative errno on failure. - */ -void rockchip_drm_psr_unregister(struct drm_encoder *encoder) -{ - struct rockchip_drm_private *drm_drv = encoder->dev->dev_private; - struct psr_drv *psr, *n; - - mutex_lock(&drm_drv->psr_list_lock); - list_for_each_entry_safe(psr, n, &drm_drv->psr_list, list) { - if (psr->encoder == encoder) { - /* - * Any other value would mean that the encoder - * is still in use. - */ - WARN_ON(psr->inhibit_count != 1); - - list_del(&psr->list); - kfree(psr); - } - } - mutex_unlock(&drm_drv->psr_list_lock); -} -EXPORT_SYMBOL(rockchip_drm_psr_unregister); diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_psr.h b/drivers/gpu/drm/rockchip/rockchip_drm_psr.h deleted file mode 100644 index 25350ba3237b..000000000000 --- a/drivers/gpu/drm/rockchip/rockchip_drm_psr.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd - * Author: Yakir Yang <[email protected]> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __ROCKCHIP_DRM_PSR___ -#define __ROCKCHIP_DRM_PSR___ - -void rockchip_drm_psr_flush_all(struct drm_device *dev); - -int rockchip_drm_psr_inhibit_put(struct drm_encoder *encoder); -int rockchip_drm_psr_inhibit_get(struct drm_encoder *encoder); - -void rockchip_drm_psr_inhibit_get_state(struct drm_atomic_state *state); -void rockchip_drm_psr_inhibit_put_state(struct drm_atomic_state *state); - -int rockchip_drm_psr_register(struct drm_encoder *encoder, - int (*psr_set)(struct drm_encoder *, bool enable)); -void rockchip_drm_psr_unregister(struct drm_encoder *encoder); - -#endif /* __ROCKCHIP_DRM_PSR__ */ diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index 0d4ade9d4722..d04b3492bdac 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -1,48 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd * Author:Mark Yao <[email protected]> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ +#include <linux/clk.h> +#include <linux/component.h> +#include <linux/delay.h> +#include <linux/iopoll.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/overflow.h> +#include <linux/platform_device.h> +#include <linux/pm_runtime.h> +#include <linux/reset.h> + #include <drm/drm.h> -#include <drm/drmP.h> #include <drm/drm_atomic.h> #include <drm/drm_atomic_uapi.h> #include <drm/drm_crtc.h> #include <drm/drm_flip_work.h> +#include <drm/drm_fourcc.h> #include <drm/drm_gem_framebuffer_helper.h> #include <drm/drm_plane_helper.h> #include <drm/drm_probe_helper.h> +#include <drm/drm_self_refresh_helper.h> +#include <drm/drm_vblank.h> + #ifdef CONFIG_DRM_ANALOGIX_DP #include <drm/bridge/analogix_dp.h> #endif -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/platform_device.h> -#include <linux/clk.h> -#include <linux/iopoll.h> -#include <linux/of.h> -#include <linux/of_device.h> -#include <linux/pm_runtime.h> -#include <linux/component.h> -#include <linux/overflow.h> - -#include <linux/reset.h> -#include <linux/delay.h> - #include "rockchip_drm_drv.h" #include "rockchip_drm_gem.h" #include "rockchip_drm_fb.h" -#include "rockchip_drm_psr.h" #include "rockchip_drm_vop.h" #include "rockchip_rgb.h" @@ -87,7 +80,7 @@ vop_get_intr_type(vop, &vop->data->intr->name, type) #define VOP_WIN_GET(vop, win, name) \ - vop_read_reg(vop, win->offset, win->phy->name) + vop_read_reg(vop, win->base, &win->phy->name) #define VOP_WIN_HAS_REG(win, name) \ (!!(win->phy->name.mask)) @@ -132,6 +125,7 @@ struct vop { bool is_enabled; struct completion dsp_hold_completion; + unsigned int win_enabled; /* protected by dev->event_lock */ struct drm_pending_vblank_event *event; @@ -145,6 +139,7 @@ struct vop { uint32_t *regsbak; void __iomem *regs; + void __iomem *lut_regs; /* physical map length of vop register */ uint32_t len; @@ -315,24 +310,19 @@ static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, uint32_t src_w, uint32_t src_h, uint32_t dst_w, - uint32_t dst_h, uint32_t pixel_format) + uint32_t dst_h, const struct drm_format_info *info) { uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; uint16_t cbcr_hor_scl_mode = SCALE_NONE; uint16_t cbcr_ver_scl_mode = SCALE_NONE; - int hsub = drm_format_horz_chroma_subsampling(pixel_format); - int vsub = drm_format_vert_chroma_subsampling(pixel_format); - const struct drm_format_info *info; bool is_yuv = false; - uint16_t cbcr_src_w = src_w / hsub; - uint16_t cbcr_src_h = src_h / vsub; + uint16_t cbcr_src_w = src_w / info->hsub; + uint16_t cbcr_src_h = src_h / info->vsub; uint16_t vsu_mode; uint16_t lb_mode; uint32_t val; int vskiplines; - info = drm_format_info(pixel_format); - if (info->is_yuv) is_yuv = true; @@ -541,8 +531,10 @@ static void vop_core_clks_disable(struct vop *vop) clk_disable(vop->hclk); } -static void vop_win_disable(struct vop *vop, const struct vop_win_data *win) +static void vop_win_disable(struct vop *vop, const struct vop_win *vop_win) { + const struct vop_win_data *win = vop_win->data; + if (win->phy->scl && win->phy->scl->ext) { VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE); VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE); @@ -551,9 +543,10 @@ static void vop_win_disable(struct vop *vop, const struct vop_win_data *win) } VOP_WIN_SET(vop, win, enable, 0); + vop->win_enabled &= ~BIT(VOP_WIN_TO_INDEX(vop_win)); } -static int vop_enable(struct drm_crtc *crtc) +static int vop_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state) { struct vop *vop = to_vop(crtc); int ret, i; @@ -593,12 +586,17 @@ static int vop_enable(struct drm_crtc *crtc) * We need to make sure that all windows are disabled before we * enable the crtc. Otherwise we might try to scan from a destroyed * buffer later. + * + * In the case of enable-after-PSR, we don't need to worry about this + * case since the buffer is guaranteed to be valid and disabling the + * window will result in screen glitches on PSR exit. */ - for (i = 0; i < vop->data->win_size; i++) { - struct vop_win *vop_win = &vop->win[i]; - const struct vop_win_data *win = vop_win->data; + if (!old_state || !old_state->self_refresh_active) { + for (i = 0; i < vop->data->win_size; i++) { + struct vop_win *vop_win = &vop->win[i]; - vop_win_disable(vop, win); + vop_win_disable(vop, vop_win); + } } spin_unlock(&vop->reg_lock); @@ -628,6 +626,25 @@ err_put_pm_runtime: return ret; } +static void rockchip_drm_set_win_enabled(struct drm_crtc *crtc, bool enabled) +{ + struct vop *vop = to_vop(crtc); + int i; + + spin_lock(&vop->reg_lock); + + for (i = 0; i < vop->data->win_size; i++) { + struct vop_win *vop_win = &vop->win[i]; + const struct vop_win_data *win = vop_win->data; + + VOP_WIN_SET(vop, win, enable, + enabled && (vop->win_enabled & BIT(i))); + } + vop_cfg_done(vop); + + spin_unlock(&vop->reg_lock); +} + static void vop_crtc_atomic_disable(struct drm_crtc *crtc, struct drm_crtc_state *old_state) { @@ -635,9 +652,16 @@ static void vop_crtc_atomic_disable(struct drm_crtc *crtc, WARN_ON(vop->event); + if (crtc->state->self_refresh_active) + rockchip_drm_set_win_enabled(crtc, false); + mutex_lock(&vop->vop_lock); + drm_crtc_vblank_off(crtc); + if (crtc->state->self_refresh_active) + goto out; + /* * Vop standby will take effect at end of current frame, * if dsp hold valid irq happen, it means standby complete. @@ -668,6 +692,8 @@ static void vop_crtc_atomic_disable(struct drm_crtc *crtc, clk_disable(vop->dclk); vop_core_clks_disable(vop); pm_runtime_put(vop->dev); + +out: mutex_unlock(&vop->vop_lock); if (crtc->state->event && !crtc->state->active) { @@ -739,7 +765,6 @@ static void vop_plane_atomic_disable(struct drm_plane *plane, struct drm_plane_state *old_state) { struct vop_win *vop_win = to_vop_win(plane); - const struct vop_win_data *win = vop_win->data; struct vop *vop = to_vop(old_state->crtc); if (!old_state->crtc) @@ -747,7 +772,7 @@ static void vop_plane_atomic_disable(struct drm_plane *plane, spin_lock(&vop->reg_lock); - vop_win_disable(vop, win); + vop_win_disable(vop, vop_win); spin_unlock(&vop->reg_lock); } @@ -831,8 +856,8 @@ static void vop_plane_atomic_update(struct drm_plane *plane, (state->rotation & DRM_MODE_REFLECT_X) ? 1 : 0); if (is_yuv) { - int hsub = drm_format_horz_chroma_subsampling(fb->format->format); - int vsub = drm_format_vert_chroma_subsampling(fb->format->format); + int hsub = fb->format->hsub; + int vsub = fb->format->vsub; int bpp = fb->format->cpp[1]; uv_obj = fb->obj[1]; @@ -856,7 +881,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, if (win->phy->scl) scl_vop_cal_scl_fac(vop, win, actual_w, actual_h, drm_rect_width(dest), drm_rect_height(dest), - fb->format->format); + fb->format); VOP_WIN_SET(vop, win, act_info, act_info); VOP_WIN_SET(vop, win, dsp_info, dsp_info); @@ -886,6 +911,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, } VOP_WIN_SET(vop, win, enable, 1); + vop->win_enabled |= BIT(win_index); spin_unlock(&vop->reg_lock); } @@ -924,40 +950,39 @@ static void vop_plane_atomic_async_update(struct drm_plane *plane, struct drm_plane_state *new_state) { struct vop *vop = to_vop(plane->state->crtc); - struct drm_plane_state *plane_state; - - plane_state = plane->funcs->atomic_duplicate_state(plane); - plane_state->crtc_x = new_state->crtc_x; - plane_state->crtc_y = new_state->crtc_y; - plane_state->crtc_h = new_state->crtc_h; - plane_state->crtc_w = new_state->crtc_w; - plane_state->src_x = new_state->src_x; - plane_state->src_y = new_state->src_y; - plane_state->src_h = new_state->src_h; - plane_state->src_w = new_state->src_w; - - if (plane_state->fb != new_state->fb) - drm_atomic_set_fb_for_plane(plane_state, new_state->fb); - - swap(plane_state, plane->state); - - if (plane->state->fb && plane->state->fb != new_state->fb) { - drm_framebuffer_get(plane->state->fb); - WARN_ON(drm_crtc_vblank_get(plane->state->crtc) != 0); - drm_flip_work_queue(&vop->fb_unref_work, plane->state->fb); - set_bit(VOP_PENDING_FB_UNREF, &vop->pending); - } + struct drm_framebuffer *old_fb = plane->state->fb; + + plane->state->crtc_x = new_state->crtc_x; + plane->state->crtc_y = new_state->crtc_y; + plane->state->crtc_h = new_state->crtc_h; + plane->state->crtc_w = new_state->crtc_w; + plane->state->src_x = new_state->src_x; + plane->state->src_y = new_state->src_y; + plane->state->src_h = new_state->src_h; + plane->state->src_w = new_state->src_w; + swap(plane->state->fb, new_state->fb); if (vop->is_enabled) { - rockchip_drm_psr_inhibit_get_state(new_state->state); vop_plane_atomic_update(plane, plane->state); spin_lock(&vop->reg_lock); vop_cfg_done(vop); spin_unlock(&vop->reg_lock); - rockchip_drm_psr_inhibit_put_state(new_state->state); - } - plane->funcs->atomic_destroy_state(plane, plane_state); + /* + * A scanout can still be occurring, so we can't drop the + * reference to the old framebuffer. To solve this we get a + * reference to old_fb and set a worker to release it later. + * FIXME: if we perform 500 async_update calls before the + * vblank, then we can have 500 different framebuffers waiting + * to be released. + */ + if (old_fb && plane->state->fb != old_fb) { + drm_framebuffer_get(old_fb); + WARN_ON(drm_crtc_vblank_get(plane->state->crtc) != 0); + drm_flip_work_queue(&vop->fb_unref_work, old_fb); + set_bit(VOP_PENDING_FB_UNREF, &vop->pending); + } + } } static const struct drm_plane_helper_funcs plane_helper_funcs = { @@ -1016,13 +1041,118 @@ static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, struct drm_display_mode *adjusted_mode) { struct vop *vop = to_vop(crtc); + unsigned long rate; - adjusted_mode->clock = - clk_round_rate(vop->dclk, mode->clock * 1000) / 1000; + /* + * Clock craziness. + * + * Key points: + * + * - DRM works in in kHz. + * - Clock framework works in Hz. + * - Rockchip's clock driver picks the clock rate that is the + * same _OR LOWER_ than the one requested. + * + * Action plan: + * + * 1. When DRM gives us a mode, we should add 999 Hz to it. That way + * if the clock we need is 60000001 Hz (~60 MHz) and DRM tells us to + * make 60000 kHz then the clock framework will actually give us + * the right clock. + * + * NOTE: if the PLL (maybe through a divider) could actually make + * a clock rate 999 Hz higher instead of the one we want then this + * could be a problem. Unfortunately there's not much we can do + * since it's baked into DRM to use kHz. It shouldn't matter in + * practice since Rockchip PLLs are controlled by tables and + * even if there is a divider in the middle I wouldn't expect PLL + * rates in the table that are just a few kHz different. + * + * 2. Get the clock framework to round the rate for us to tell us + * what it will actually make. + * + * 3. Store the rounded up rate so that we don't need to worry about + * this in the actual clk_set_rate(). + */ + rate = clk_round_rate(vop->dclk, adjusted_mode->clock * 1000 + 999); + adjusted_mode->clock = DIV_ROUND_UP(rate, 1000); return true; } +static bool vop_dsp_lut_is_enabled(struct vop *vop) +{ + return vop_read_reg(vop, 0, &vop->data->common->dsp_lut_en); +} + +static void vop_crtc_write_gamma_lut(struct vop *vop, struct drm_crtc *crtc) +{ + struct drm_color_lut *lut = crtc->state->gamma_lut->data; + unsigned int i; + + for (i = 0; i < crtc->gamma_size; i++) { + u32 word; + + word = (drm_color_lut_extract(lut[i].red, 10) << 20) | + (drm_color_lut_extract(lut[i].green, 10) << 10) | + drm_color_lut_extract(lut[i].blue, 10); + writel(word, vop->lut_regs + i * 4); + } +} + +static void vop_crtc_gamma_set(struct vop *vop, struct drm_crtc *crtc, + struct drm_crtc_state *old_state) +{ + struct drm_crtc_state *state = crtc->state; + unsigned int idle; + int ret; + + if (!vop->lut_regs) + return; + /* + * To disable gamma (gamma_lut is null) or to write + * an update to the LUT, clear dsp_lut_en. + */ + spin_lock(&vop->reg_lock); + VOP_REG_SET(vop, common, dsp_lut_en, 0); + vop_cfg_done(vop); + spin_unlock(&vop->reg_lock); + + /* + * In order to write the LUT to the internal memory, + * we need to first make sure the dsp_lut_en bit is cleared. + */ + ret = readx_poll_timeout(vop_dsp_lut_is_enabled, vop, + idle, !idle, 5, 30 * 1000); + if (ret) { + DRM_DEV_ERROR(vop->dev, "display LUT RAM enable timeout!\n"); + return; + } + + if (!state->gamma_lut) + return; + + spin_lock(&vop->reg_lock); + vop_crtc_write_gamma_lut(vop, crtc); + VOP_REG_SET(vop, common, dsp_lut_en, 1); + vop_cfg_done(vop); + spin_unlock(&vop->reg_lock); +} + +static void vop_crtc_atomic_begin(struct drm_crtc *crtc, + struct drm_crtc_state *old_crtc_state) +{ + struct vop *vop = to_vop(crtc); + + /* + * Only update GAMMA if the 'active' flag is not changed, + * otherwise it's updated by .atomic_enable. + */ + if (crtc->state->color_mgmt_changed && + !crtc->state->active_changed) + vop_crtc_gamma_set(vop, crtc, old_crtc_state); +} + static void vop_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state) { @@ -1041,21 +1171,34 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; u16 vact_end = vact_st + vdisplay; uint32_t pin_pol, val; + int dither_bpc = s->output_bpc ? s->output_bpc : 10; int ret; + if (old_state && old_state->self_refresh_active) { + drm_crtc_vblank_on(crtc); + rockchip_drm_set_win_enabled(crtc, true); + return; + } + + /* + * If we have a GAMMA LUT in the state, then let's make sure + * it's updated. We might be coming out of suspend, + * which means the LUT internal memory needs to be re-written. + */ + if (crtc->state->gamma_lut) + vop_crtc_gamma_set(vop, crtc, old_state); + mutex_lock(&vop->vop_lock); WARN_ON(vop->event); - ret = vop_enable(crtc); + ret = vop_enable(crtc, old_state); if (ret) { mutex_unlock(&vop->vop_lock); DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret); return; } - - pin_pol = BIT(DCLK_INVERT); - pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ? + pin_pol = (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ? BIT(HSYNC_POSITIVE) : 0; pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ? BIT(VSYNC_POSITIVE) : 0; @@ -1064,25 +1207,29 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, switch (s->output_type) { case DRM_MODE_CONNECTOR_LVDS: - VOP_REG_SET(vop, output, rgb_en, 1); + VOP_REG_SET(vop, output, rgb_dclk_pol, 1); VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol); + VOP_REG_SET(vop, output, rgb_en, 1); break; case DRM_MODE_CONNECTOR_eDP: + VOP_REG_SET(vop, output, edp_dclk_pol, 1); VOP_REG_SET(vop, output, edp_pin_pol, pin_pol); VOP_REG_SET(vop, output, edp_en, 1); break; case DRM_MODE_CONNECTOR_HDMIA: + VOP_REG_SET(vop, output, hdmi_dclk_pol, 1); VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol); VOP_REG_SET(vop, output, hdmi_en, 1); break; case DRM_MODE_CONNECTOR_DSI: + VOP_REG_SET(vop, output, mipi_dclk_pol, 1); VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol); VOP_REG_SET(vop, output, mipi_en, 1); VOP_REG_SET(vop, output, mipi_dual_channel_en, !!(s->output_flags & ROCKCHIP_OUTPUT_DSI_DUAL)); break; case DRM_MODE_CONNECTOR_DisplayPort: - pin_pol &= ~BIT(DCLK_INVERT); + VOP_REG_SET(vop, output, dp_dclk_pol, 0); VOP_REG_SET(vop, output, dp_pin_pol, pin_pol); VOP_REG_SET(vop, output, dp_en, 1); break; @@ -1098,11 +1245,19 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)) s->output_mode = ROCKCHIP_OUT_MODE_P888; - if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && s->output_bpc == 8) + if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8) VOP_REG_SET(vop, common, pre_dither_down, 1); else VOP_REG_SET(vop, common, pre_dither_down, 0); + if (dither_bpc == 6) { + VOP_REG_SET(vop, common, dither_down_sel, DITHER_DOWN_ALLEGRO); + VOP_REG_SET(vop, common, dither_down_mode, RGB888_TO_RGB666); + VOP_REG_SET(vop, common, dither_down_en, 1); + } else { + VOP_REG_SET(vop, common, dither_down_en, 0); + } + VOP_REG_SET(vop, common, out_mode, s->output_mode); VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len); @@ -1151,6 +1306,26 @@ static void vop_wait_for_irq_handler(struct vop *vop) synchronize_irq(vop->irq); } +static int vop_crtc_atomic_check(struct drm_crtc *crtc, + struct drm_crtc_state *crtc_state) +{ + struct vop *vop = to_vop(crtc); + + if (vop->lut_regs && crtc_state->color_mgmt_changed && + crtc_state->gamma_lut) { + unsigned int len; + + len = drm_color_lut_size(crtc_state->gamma_lut); + if (len != crtc->gamma_size) { + DRM_DEBUG_KMS("Invalid LUT size; got %d, expected %d\n", + len, crtc->gamma_size); + return -EINVAL; + } + } + + return 0; +} + static void vop_crtc_atomic_flush(struct drm_crtc *crtc, struct drm_crtc_state *old_crtc_state) { @@ -1203,6 +1378,8 @@ static void vop_crtc_atomic_flush(struct drm_crtc *crtc, static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { .mode_fixup = vop_crtc_mode_fixup, + .atomic_check = vop_crtc_atomic_check, + .atomic_begin = vop_crtc_atomic_begin, .atomic_flush = vop_crtc_atomic_flush, .atomic_enable = vop_crtc_atomic_enable, .atomic_disable = vop_crtc_atomic_disable, @@ -1213,17 +1390,6 @@ static void vop_crtc_destroy(struct drm_crtc *crtc) drm_crtc_cleanup(crtc); } -static void vop_crtc_reset(struct drm_crtc *crtc) -{ - if (crtc->state) - __drm_atomic_helper_crtc_destroy_state(crtc->state); - kfree(crtc->state); - - crtc->state = kzalloc(sizeof(struct rockchip_crtc_state), GFP_KERNEL); - if (crtc->state) - crtc->state->crtc = crtc; -} - static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) { struct rockchip_crtc_state *rockchip_state; @@ -1245,6 +1411,17 @@ static void vop_crtc_destroy_state(struct drm_crtc *crtc, kfree(s); } +static void vop_crtc_reset(struct drm_crtc *crtc) +{ + struct rockchip_crtc_state *crtc_state = + kzalloc(sizeof(*crtc_state), GFP_KERNEL); + + if (crtc->state) + vop_crtc_destroy_state(crtc, crtc->state); + + __drm_atomic_helper_crtc_reset(crtc, &crtc_state->base); +} + #ifdef CONFIG_DRM_ANALOGIX_DP static struct drm_connector *vop_get_edp_connector(struct vop *vop) { @@ -1321,6 +1498,7 @@ static const struct drm_crtc_funcs vop_crtc_funcs = { .disable_vblank = vop_crtc_disable_vblank, .set_crc_source = vop_crtc_set_crc_source, .verify_crc_source = vop_crtc_verify_crc_source, + .gamma_set = drm_atomic_helper_legacy_gamma_set, }; static void vop_fb_unref_worker(struct drm_flip_work *work, void *val) @@ -1478,6 +1656,10 @@ static int vop_create_crtc(struct vop *vop) goto err_cleanup_planes; drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs); + if (vop->lut_regs) { + drm_mode_crtc_set_gamma_size(crtc, vop_data->lut_size); + drm_crtc_enable_color_mgmt(crtc, 0, false, vop_data->lut_size); + } /* * Create drm_planes for overlay windows with possible_crtcs restricted @@ -1521,6 +1703,12 @@ static int vop_create_crtc(struct vop *vop) init_completion(&vop->line_flag_completion); crtc->port = port; + ret = drm_self_refresh_helper_init(crtc); + if (ret) + DRM_DEV_DEBUG_KMS(vop->dev, + "Failed to init %s with SR helpers %d, ignoring\n", + crtc->name, ret); + return 0; err_cleanup_crtc: @@ -1538,6 +1726,8 @@ static void vop_destroy_crtc(struct vop *vop) struct drm_device *drm_dev = vop->drm_dev; struct drm_plane *plane, *tmp; + drm_self_refresh_helper_cleanup(crtc); + of_node_put(crtc->port); /* @@ -1562,7 +1752,6 @@ static void vop_destroy_crtc(struct vop *vop) static int vop_initial(struct vop *vop) { - const struct vop_data *vop_data = vop->data; struct reset_control *ahb_rst; int i, ret; @@ -1629,12 +1818,13 @@ static int vop_initial(struct vop *vop) VOP_REG_SET(vop, misc, global_regdone_en, 1); VOP_REG_SET(vop, common, dsp_blank, 0); - for (i = 0; i < vop_data->win_size; i++) { - const struct vop_win_data *win = &vop_data->win[i]; + for (i = 0; i < vop->data->win_size; i++) { + struct vop_win *vop_win = &vop->win[i]; + const struct vop_win_data *win = vop_win->data; int channel = i * 2 + 1; VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel); - vop_win_disable(vop, win); + vop_win_disable(vop, vop_win); VOP_WIN_SET(vop, win, gate, 1); } @@ -1774,6 +1964,17 @@ static int vop_bind(struct device *dev, struct device *master, void *data) if (IS_ERR(vop->regs)) return PTR_ERR(vop->regs); + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (res) { + if (!vop_data->lut_size) { + DRM_DEV_ERROR(dev, "no gamma LUT size defined\n"); + return -EINVAL; + } + vop->lut_regs = devm_ioremap_resource(dev, res); + if (IS_ERR(vop->lut_regs)) + return PTR_ERR(vop->lut_regs); + } + vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL); if (!vop->regsbak) return -ENOMEM; diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h index 04ed401d2325..0b3d18c457b2 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h @@ -1,15 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd * Author:Mark Yao <[email protected]> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #ifndef _ROCKCHIP_DRM_VOP_H @@ -54,10 +46,15 @@ struct vop_modeset { struct vop_output { struct vop_reg pin_pol; struct vop_reg dp_pin_pol; + struct vop_reg dp_dclk_pol; struct vop_reg edp_pin_pol; + struct vop_reg edp_dclk_pol; struct vop_reg hdmi_pin_pol; + struct vop_reg hdmi_dclk_pol; struct vop_reg mipi_pin_pol; + struct vop_reg mipi_dclk_pol; struct vop_reg rgb_pin_pol; + struct vop_reg rgb_dclk_pol; struct vop_reg dp_en; struct vop_reg edp_en; struct vop_reg hdmi_en; @@ -71,8 +68,11 @@ struct vop_common { struct vop_reg dsp_blank; struct vop_reg data_blank; struct vop_reg pre_dither_down; - struct vop_reg dither_down; + struct vop_reg dither_down_sel; + struct vop_reg dither_down_mode; + struct vop_reg dither_down_en; struct vop_reg dither_up; + struct vop_reg dsp_lut_en; struct vop_reg gate_en; struct vop_reg mmu_en; struct vop_reg out_mode; @@ -176,6 +176,7 @@ struct vop_data { const struct vop_win_yuv2yuv_data *win_yuv2yuv; const struct vop_win_data *win; unsigned int win_size; + unsigned int lut_size; #define VOP_FEATURE_OUTPUT_RGB10 BIT(0) #define VOP_FEATURE_INTERNAL_RGB BIT(1) @@ -287,11 +288,20 @@ enum scale_down_mode { SCALE_DOWN_AVG = 0x1 }; +enum dither_down_mode { + RGB888_TO_RGB565 = 0x0, + RGB888_TO_RGB666 = 0x1 +}; + +enum dither_down_mode_sel { + DITHER_DOWN_ALLEGRO = 0x0, + DITHER_DOWN_FRC = 0x1 +}; + enum vop_pol { HSYNC_POSITIVE = 0, VSYNC_POSITIVE = 1, - DEN_NEGATIVE = 2, - DCLK_INVERT = 3 + DEN_NEGATIVE = 2 }; #define FRAC_16_16(mult, div) (((mult) << 16) / (div)) diff --git a/drivers/gpu/drm/rockchip/rockchip_lvds.c b/drivers/gpu/drm/rockchip/rockchip_lvds.c index e52dd5a8529e..8a4c9af0ba73 100644 --- a/drivers/gpu/drm/rockchip/rockchip_lvds.c +++ b/drivers/gpu/drm/rockchip/rockchip_lvds.c @@ -1,34 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd * Author: * Mark Yao <[email protected]> * Sandy Huang <[email protected]> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ -#include <drm/drmP.h> -#include <drm/drm_atomic_helper.h> -#include <drm/drm_dp_helper.h> -#include <drm/drm_panel.h> -#include <drm/drm_of.h> -#include <drm/drm_probe_helper.h> - -#include <linux/component.h> #include <linux/clk.h> +#include <linux/component.h> #include <linux/mfd/syscon.h> #include <linux/of_graph.h> #include <linux/pinctrl/devinfo.h> +#include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/regmap.h> #include <linux/reset.h> +#include <drm/drm_atomic_helper.h> +#include <drm/drm_bridge.h> + +#include <drm/drm_dp_helper.h> +#include <drm/drm_of.h> +#include <drm/drm_panel.h> +#include <drm/drm_probe_helper.h> #include "rockchip_drm_drv.h" #include "rockchip_drm_vop.h" diff --git a/drivers/gpu/drm/rockchip/rockchip_lvds.h b/drivers/gpu/drm/rockchip/rockchip_lvds.h index 15810b737809..029bad8e1a14 100644 --- a/drivers/gpu/drm/rockchip/rockchip_lvds.h +++ b/drivers/gpu/drm/rockchip/rockchip_lvds.h @@ -1,17 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd * Author: * Sandy Huang <[email protected]> * Mark Yao <[email protected]> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #ifndef _ROCKCHIP_LVDS_ diff --git a/drivers/gpu/drm/rockchip/rockchip_rgb.c b/drivers/gpu/drm/rockchip/rockchip_rgb.c index ce4d82d293e4..ae730275a34f 100644 --- a/drivers/gpu/drm/rockchip/rockchip_rgb.c +++ b/drivers/gpu/drm/rockchip/rockchip_rgb.c @@ -5,16 +5,16 @@ * Sandy Huang <[email protected]> */ -#include <drm/drmP.h> +#include <linux/component.h> +#include <linux/of_graph.h> + #include <drm/drm_atomic_helper.h> +#include <drm/drm_bridge.h> #include <drm/drm_dp_helper.h> -#include <drm/drm_panel.h> #include <drm/drm_of.h> +#include <drm/drm_panel.h> #include <drm/drm_probe_helper.h> -#include <linux/component.h> -#include <linux/of_graph.h> - #include "rockchip_drm_drv.h" #include "rockchip_drm_vop.h" @@ -136,7 +136,8 @@ struct rockchip_rgb *rockchip_rgb_init(struct device *dev, drm_encoder_helper_add(encoder, &rockchip_rgb_encoder_helper_funcs); if (panel) { - bridge = drm_panel_bridge_add(panel, DRM_MODE_CONNECTOR_LVDS); + bridge = drm_panel_bridge_add_typed(panel, + DRM_MODE_CONNECTOR_LVDS); if (IS_ERR(bridge)) return ERR_CAST(bridge); } diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c index bd76328c0fdb..7a9d979c8d5d 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -1,24 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd * Author:Mark Yao <[email protected]> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ -#include <drm/drmP.h> - -#include <linux/kernel.h> #include <linux/component.h> +#include <linux/mod_devicetable.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include <drm/drm_fourcc.h> +#include <drm/drm_plane.h> +#include <drm/drm_print.h> #include "rockchip_drm_vop.h" #include "rockchip_vop_reg.h" +#include "rockchip_drm_drv.h" #define _VOP_REG(off, _mask, _shift, _write_mask, _relaxed) \ { \ @@ -137,6 +135,9 @@ static const struct vop_common rk3036_common = { .standby = VOP_REG_SYNC(RK3036_SYS_CTRL, 0x1, 30), .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), .dsp_blank = VOP_REG(RK3036_DSP_CTRL1, 0x1, 24), + .dither_down_sel = VOP_REG(RK3036_DSP_CTRL0, 0x1, 27), + .dither_down_en = VOP_REG(RK3036_DSP_CTRL0, 0x1, 11), + .dither_down_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 10), .cfg_done = VOP_REG_SYNC(RK3036_REG_CFG_DONE, 0x1, 0), }; @@ -200,6 +201,9 @@ static const struct vop_common px30_common = { .standby = VOP_REG_SYNC(PX30_SYS_CTRL2, 0x1, 1), .out_mode = VOP_REG(PX30_DSP_CTRL2, 0xf, 16), .dsp_blank = VOP_REG(PX30_DSP_CTRL2, 0x1, 14), + .dither_down_en = VOP_REG(PX30_DSP_CTRL2, 0x1, 8), + .dither_down_sel = VOP_REG(PX30_DSP_CTRL2, 0x1, 7), + .dither_down_mode = VOP_REG(PX30_DSP_CTRL2, 0x1, 6), .cfg_done = VOP_REG_SYNC(PX30_REG_CFG_DONE, 0x1, 0), }; @@ -211,9 +215,11 @@ static const struct vop_modeset px30_modeset = { }; static const struct vop_output px30_output = { - .rgb_pin_pol = VOP_REG(PX30_DSP_CTRL0, 0xf, 1), - .mipi_pin_pol = VOP_REG(PX30_DSP_CTRL0, 0xf, 25), + .rgb_dclk_pol = VOP_REG(PX30_DSP_CTRL0, 0x1, 1), + .rgb_pin_pol = VOP_REG(PX30_DSP_CTRL0, 0x7, 2), .rgb_en = VOP_REG(PX30_DSP_CTRL0, 0x1, 0), + .mipi_dclk_pol = VOP_REG(PX30_DSP_CTRL0, 0x1, 25), + .mipi_pin_pol = VOP_REG(PX30_DSP_CTRL0, 0x7, 26), .mipi_en = VOP_REG(PX30_DSP_CTRL0, 0x1, 24), }; @@ -365,6 +371,8 @@ static const struct vop_common rk3066_common = { .standby = VOP_REG(RK3066_SYS_CTRL0, 0x1, 1), .out_mode = VOP_REG(RK3066_DSP_CTRL0, 0xf, 0), .cfg_done = VOP_REG(RK3066_REG_CFG_DONE, 0x1, 0), + .dither_down_en = VOP_REG(RK3066_DSP_CTRL0, 0x1, 11), + .dither_down_mode = VOP_REG(RK3066_DSP_CTRL0, 0x1, 10), .dsp_blank = VOP_REG(RK3066_DSP_CTRL1, 0x1, 24), }; @@ -458,6 +466,9 @@ static const struct vop_common rk3188_common = { .standby = VOP_REG(RK3188_SYS_CTRL, 0x1, 30), .out_mode = VOP_REG(RK3188_DSP_CTRL0, 0xf, 0), .cfg_done = VOP_REG(RK3188_REG_CFG_DONE, 0x1, 0), + .dither_down_sel = VOP_REG(RK3188_DSP_CTRL0, 0x1, 27), + .dither_down_en = VOP_REG(RK3188_DSP_CTRL0, 0x1, 11), + .dither_down_mode = VOP_REG(RK3188_DSP_CTRL0, 0x1, 10), .dsp_blank = VOP_REG(RK3188_DSP_CTRL1, 0x3, 24), }; @@ -585,9 +596,12 @@ static const struct vop_common rk3288_common = { .standby = VOP_REG_SYNC(RK3288_SYS_CTRL, 0x1, 22), .gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23), .mmu_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 20), + .dither_down_sel = VOP_REG(RK3288_DSP_CTRL1, 0x1, 4), + .dither_down_mode = VOP_REG(RK3288_DSP_CTRL1, 0x1, 3), + .dither_down_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 2), .pre_dither_down = VOP_REG(RK3288_DSP_CTRL1, 0x1, 1), - .dither_down = VOP_REG(RK3288_DSP_CTRL1, 0xf, 1), .dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6), + .dsp_lut_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 0), .data_blank = VOP_REG(RK3288_DSP_CTRL0, 0x1, 19), .dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18), .out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0), @@ -636,6 +650,7 @@ static const struct vop_data rk3288_vop = { .output = &rk3288_output, .win = rk3288_vop_win_data, .win_size = ARRAY_SIZE(rk3288_vop_win_data), + .lut_size = 1024, }; static const int rk3368_vop_intrs[] = { @@ -707,10 +722,14 @@ static const struct vop_win_data rk3368_vop_win_data[] = { }; static const struct vop_output rk3368_output = { - .rgb_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 16), - .hdmi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 20), - .edp_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 24), - .mipi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 28), + .rgb_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 19), + .hdmi_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 23), + .edp_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 27), + .mipi_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 31), + .rgb_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 16), + .hdmi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 20), + .edp_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 24), + .mipi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 28), .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12), .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13), .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14), @@ -754,11 +773,16 @@ static const struct vop_data rk3366_vop = { }; static const struct vop_output rk3399_output = { - .dp_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 16), - .rgb_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 16), - .hdmi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 20), - .edp_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 24), - .mipi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 28), + .dp_dclk_pol = VOP_REG(RK3399_DSP_CTRL1, 0x1, 19), + .rgb_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 19), + .hdmi_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 23), + .edp_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 27), + .mipi_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 31), + .dp_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0x7, 16), + .rgb_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 16), + .hdmi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 20), + .edp_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 24), + .mipi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 28), .dp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 11), .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12), .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13), @@ -862,14 +886,18 @@ static const struct vop_modeset rk3328_modeset = { }; static const struct vop_output rk3328_output = { + .rgb_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 19), + .hdmi_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 23), + .edp_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 27), + .mipi_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 31), .rgb_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 12), .hdmi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 13), .edp_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 14), .mipi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 15), - .rgb_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 16), - .hdmi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 20), - .edp_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 24), - .mipi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 28), + .rgb_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 16), + .hdmi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 20), + .edp_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 24), + .mipi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 28), }; static const struct vop_misc rk3328_misc = { @@ -878,7 +906,10 @@ static const struct vop_misc rk3328_misc = { static const struct vop_common rk3328_common = { .standby = VOP_REG_SYNC(RK3328_SYS_CTRL, 0x1, 22), - .dither_down = VOP_REG(RK3328_DSP_CTRL1, 0xf, 1), + .dither_down_sel = VOP_REG(RK3328_DSP_CTRL1, 0x1, 4), + .dither_down_mode = VOP_REG(RK3328_DSP_CTRL1, 0x1, 3), + .dither_down_en = VOP_REG(RK3328_DSP_CTRL1, 0x1, 2), + .pre_dither_down = VOP_REG(RK3328_DSP_CTRL1, 0x1, 1), .dither_up = VOP_REG(RK3328_DSP_CTRL1, 0x1, 6), .dsp_blank = VOP_REG(RK3328_DSP_CTRL0, 0x3, 18), .out_mode = VOP_REG(RK3328_DSP_CTRL0, 0xf, 0), diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h index d837d4a7df4a..6e9fa5815d4d 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h @@ -1,15 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd * Author:Mark Yao <[email protected]> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #ifndef _ROCKCHIP_VOP_REG_H |