diff options
Diffstat (limited to 'drivers/gpu/drm/msm/dsi/dsi_host.c')
| -rw-r--r-- | drivers/gpu/drm/msm/dsi/dsi_host.c | 46 | 
1 files changed, 33 insertions, 13 deletions
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 458cec82ae13..11ae5b8444c3 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -505,7 +505,7 @@ int msm_dsi_runtime_resume(struct device *dev)  	return dsi_bus_clk_enable(msm_host);  } -int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host) +int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host)  {  	int ret; @@ -515,13 +515,13 @@ int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host)  	ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate);  	if (ret) {  		pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret); -		goto error; +		return ret;  	}  	ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate);  	if (ret) {  		pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret); -		goto error; +		return ret;  	}  	if (msm_host->byte_intf_clk) { @@ -530,10 +530,18 @@ int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host)  		if (ret) {  			pr_err("%s: Failed to set rate byte intf clk, %d\n",  			       __func__, ret); -			goto error; +			return ret;  		}  	} +	return 0; +} + + +int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host) +{ +	int ret; +  	ret = clk_prepare_enable(msm_host->esc_clk);  	if (ret) {  		pr_err("%s: Failed to enable dsi esc clk\n", __func__); @@ -573,7 +581,7 @@ error:  	return ret;  } -int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host) +int dsi_link_clk_set_rate_v2(struct msm_dsi_host *msm_host)  {  	int ret; @@ -584,27 +592,34 @@ int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host)  	ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate);  	if (ret) {  		pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret); -		goto error; +		return ret;  	}  	ret = clk_set_rate(msm_host->esc_clk, msm_host->esc_clk_rate);  	if (ret) {  		pr_err("%s: Failed to set rate esc clk, %d\n", __func__, ret); -		goto error; +		return ret;  	}  	ret = clk_set_rate(msm_host->src_clk, msm_host->src_clk_rate);  	if (ret) {  		pr_err("%s: Failed to set rate src clk, %d\n", __func__, ret); -		goto error; +		return ret;  	}  	ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate);  	if (ret) {  		pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret); -		goto error; +		return ret;  	} +	return 0; +} + +int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host) +{ +	int ret; +  	ret = clk_prepare_enable(msm_host->byte_clk);  	if (ret) {  		pr_err("%s: Failed to enable dsi byte clk\n", __func__); @@ -818,7 +833,7 @@ static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable,  	u32 flags = msm_host->mode_flags;  	enum mipi_dsi_pixel_format mipi_fmt = msm_host->format;  	const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; -	u32 data = 0; +	u32 data = 0, lane_ctrl = 0;  	if (!enable) {  		dsi_write(msm_host, REG_DSI_CTRL, 0); @@ -906,9 +921,11 @@ static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable,  	dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL,  		  DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(msm_host->dlane_swap)); -	if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) +	if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) { +		lane_ctrl = dsi_read(msm_host, REG_DSI_LANE_CTRL);  		dsi_write(msm_host, REG_DSI_LANE_CTRL, -			DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST); +			lane_ctrl | DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST); +	}  	data |= DSI_CTRL_ENABLE; @@ -1996,6 +2013,7 @@ int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host,  	 * mdp clock need to be enabled to receive dsi interrupt  	 */  	pm_runtime_get_sync(&msm_host->pdev->dev); +	cfg_hnd->ops->link_clk_set_rate(msm_host);  	cfg_hnd->ops->link_clk_enable(msm_host);  	/* TODO: vote for bus bandwidth */ @@ -2344,7 +2362,9 @@ int msm_dsi_host_power_on(struct mipi_dsi_host *host,  	}  	pm_runtime_get_sync(&msm_host->pdev->dev); -	ret = cfg_hnd->ops->link_clk_enable(msm_host); +	ret = cfg_hnd->ops->link_clk_set_rate(msm_host); +	if (!ret) +		ret = cfg_hnd->ops->link_clk_enable(msm_host);  	if (ret) {  		pr_err("%s: failed to enable link clocks. ret=%d\n",  		       __func__, ret);  |