diff options
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 28 |
1 files changed, 13 insertions, 15 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index b2bab57cd113..5711cb701760 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -6685,22 +6685,20 @@ intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) static void compute_m_n(unsigned int m, unsigned int n, uint32_t *ret_m, uint32_t *ret_n, - bool reduce_m_n) + bool constant_n) { /* - * Reduce M/N as much as possible without loss in precision. Several DP - * dongles in particular seem to be fussy about too large *link* M/N - * values. The passed in values are more likely to have the least - * significant bits zero than M after rounding below, so do this first. + * Several DP dongles in particular seem to be fussy about + * too large link M/N values. Give N value as 0x8000 that + * should be acceptable by specific devices. 0x8000 is the + * specified fixed N value for asynchronous clock mode, + * which the devices expect also in synchronous clock mode. */ - if (reduce_m_n) { - while ((m & 1) == 0 && (n & 1) == 0) { - m >>= 1; - n >>= 1; - } - } + if (constant_n) + *ret_n = 0x8000; + else + *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); - *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); *ret_m = div_u64((uint64_t) m * *ret_n, n); intel_reduce_m_n_ratio(ret_m, ret_n); } @@ -6709,18 +6707,18 @@ void intel_link_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock, int link_clock, struct intel_link_m_n *m_n, - bool reduce_m_n) + bool constant_n) { m_n->tu = 64; compute_m_n(bits_per_pixel * pixel_clock, link_clock * nlanes * 8, &m_n->gmch_m, &m_n->gmch_n, - reduce_m_n); + constant_n); compute_m_n(pixel_clock, link_clock, &m_n->link_m, &m_n->link_n, - reduce_m_n); + constant_n); } static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |