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path: root/drivers/gpu/drm/i915/i915_pci.c
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Diffstat (limited to 'drivers/gpu/drm/i915/i915_pci.c')
-rw-r--r--drivers/gpu/drm/i915/i915_pci.c94
1 files changed, 69 insertions, 25 deletions
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 261294df535c..acf688b698c3 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -22,12 +22,14 @@
*
*/
+#include <drm/drm_color_mgmt.h>
#include <drm/drm_drv.h>
#include <drm/i915_pciids.h>
#include "i915_driver.h"
#include "i915_drv.h"
#include "i915_pci.h"
+#include "i915_reg.h"
#define PLATFORM(x) .platform = (x)
#define GEN(x) \
@@ -214,13 +216,13 @@ static const struct intel_device_info i845g_info = {
static const struct intel_device_info i85x_info = {
I830_FEATURES,
PLATFORM(INTEL_I85X),
- .display.has_fbc = 1,
+ .display.fbc_mask = BIT(INTEL_FBC_A),
};
static const struct intel_device_info i865g_info = {
I845_FEATURES,
PLATFORM(INTEL_I865G),
- .display.has_fbc = 1,
+ .display.fbc_mask = BIT(INTEL_FBC_A),
};
#define GEN3_FEATURES \
@@ -258,7 +260,7 @@ static const struct intel_device_info i915gm_info = {
.display.has_overlay = 1,
.display.overlay_needs_physical = 1,
.display.supports_tv = 1,
- .display.has_fbc = 1,
+ .display.fbc_mask = BIT(INTEL_FBC_A),
.hws_needs_physical = 1,
.unfenced_needs_alignment = 1,
};
@@ -283,7 +285,7 @@ static const struct intel_device_info i945gm_info = {
.display.has_overlay = 1,
.display.overlay_needs_physical = 1,
.display.supports_tv = 1,
- .display.has_fbc = 1,
+ .display.fbc_mask = BIT(INTEL_FBC_A),
.hws_needs_physical = 1,
.unfenced_needs_alignment = 1,
};
@@ -342,7 +344,7 @@ static const struct intel_device_info i965gm_info = {
GEN4_FEATURES,
PLATFORM(INTEL_I965GM),
.is_mobile = 1,
- .display.has_fbc = 1,
+ .display.fbc_mask = BIT(INTEL_FBC_A),
.display.has_overlay = 1,
.display.supports_tv = 1,
.hws_needs_physical = 1,
@@ -360,7 +362,7 @@ static const struct intel_device_info gm45_info = {
GEN4_FEATURES,
PLATFORM(INTEL_GM45),
.is_mobile = 1,
- .display.has_fbc = 1,
+ .display.fbc_mask = BIT(INTEL_FBC_A),
.display.supports_tv = 1,
.platform_engine_mask = BIT(RCS0) | BIT(VCS0),
.gpu_reset_clobbers_display = false,
@@ -393,7 +395,7 @@ static const struct intel_device_info ilk_m_info = {
PLATFORM(INTEL_IRONLAKE),
.is_mobile = 1,
.has_rps = true,
- .display.has_fbc = 1,
+ .display.fbc_mask = BIT(INTEL_FBC_A),
};
#define GEN6_FEATURES \
@@ -401,7 +403,7 @@ static const struct intel_device_info ilk_m_info = {
.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
.display.has_hotplug = 1, \
- .display.has_fbc = 1, \
+ .display.fbc_mask = BIT(INTEL_FBC_A), \
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
.has_coherent_ggtt = true, \
.has_llc = 1, \
@@ -452,7 +454,7 @@ static const struct intel_device_info snb_m_gt2_info = {
.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \
.display.has_hotplug = 1, \
- .display.has_fbc = 1, \
+ .display.fbc_mask = BIT(INTEL_FBC_A), \
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
.has_coherent_ggtt = true, \
.has_llc = 1, \
@@ -693,7 +695,7 @@ static const struct intel_device_info skl_gt4_info = {
.has_64bit_reloc = 1, \
.display.has_ddi = 1, \
.display.has_fpga_dbg = 1, \
- .display.has_fbc = 1, \
+ .display.fbc_mask = BIT(INTEL_FBC_A), \
.display.has_hdcp = 1, \
.display.has_psr = 1, \
.display.has_psr_hw_tracking = 1, \
@@ -899,7 +901,8 @@ static const struct intel_device_info rkl_info = {
.has_llc = 0, \
.has_pxp = 0, \
.has_snoop = 1, \
- .is_dgfx = 1
+ .is_dgfx = 1, \
+ .has_heci_gscfi = 1
static const struct intel_device_info dg1_info = {
GEN12_FEATURES,
@@ -948,7 +951,7 @@ static const struct intel_device_info adl_s_info = {
.display.has_dp_mst = 1, \
.display.has_dsb = 1, \
.display.has_dsc = 1, \
- .display.has_fbc = 1, \
+ .display.fbc_mask = BIT(INTEL_FBC_A), \
.display.has_fpga_dbg = 1, \
.display.has_hdcp = 1, \
.display.has_hotplug = 1, \
@@ -1003,6 +1006,7 @@ static const struct intel_device_info adl_p_info = {
XE_HP_PAGE_SIZES, \
.dma_mask_size = 46, \
.has_64bit_reloc = 1, \
+ .has_flat_ccs = 1, \
.has_global_mocs = 1, \
.has_gt_uc = 1, \
.has_llc = 1, \
@@ -1028,31 +1032,68 @@ static const struct intel_device_info xehpsdv_info = {
PLATFORM(INTEL_XEHPSDV),
.display = { },
.has_64k_pages = 1,
+ .needs_compact_pt = 1,
.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) |
BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) |
BIT(VCS0) | BIT(VCS1) | BIT(VCS2) | BIT(VCS3) |
- BIT(VCS4) | BIT(VCS5) | BIT(VCS6) | BIT(VCS7),
+ BIT(VCS4) | BIT(VCS5) | BIT(VCS6) | BIT(VCS7) |
+ BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3),
.require_force_probe = 1,
};
-__maybe_unused
+#define DG2_FEATURES \
+ XE_HP_FEATURES, \
+ XE_HPM_FEATURES, \
+ DGFX_FEATURES, \
+ .graphics.rel = 55, \
+ .media.rel = 55, \
+ PLATFORM(INTEL_DG2), \
+ .has_4tile = 1, \
+ .has_64k_pages = 1, \
+ .has_guc_deprivilege = 1, \
+ .has_heci_pxp = 1, \
+ .needs_compact_pt = 1, \
+ .platform_engine_mask = \
+ BIT(RCS0) | BIT(BCS0) | \
+ BIT(VECS0) | BIT(VECS1) | \
+ BIT(VCS0) | BIT(VCS2) | \
+ BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3)
+
static const struct intel_device_info dg2_info = {
- XE_HP_FEATURES,
- XE_HPM_FEATURES,
+ DG2_FEATURES,
XE_LPD_FEATURES,
+ .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+ BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
+ .require_force_probe = 1,
+};
+
+__maybe_unused
+static const struct intel_device_info ats_m_info = {
+ DG2_FEATURES,
+ .display = { 0 },
+ .require_force_probe = 1,
+};
+
+#define XE_HPC_FEATURES \
+ XE_HP_FEATURES, \
+ .dma_mask_size = 52
+
+__maybe_unused
+static const struct intel_device_info pvc_info = {
+ XE_HPC_FEATURES,
+ XE_HPM_FEATURES,
DGFX_FEATURES,
- .graphics.rel = 55,
- .media.rel = 55,
- PLATFORM(INTEL_DG2),
- .has_64k_pages = 1,
+ .graphics.rel = 60,
+ .media.rel = 60,
+ PLATFORM(INTEL_PONTEVECCHIO),
+ .display = { 0 },
+ .has_flat_ccs = 0,
.platform_engine_mask =
- BIT(RCS0) | BIT(BCS0) |
- BIT(VECS0) | BIT(VECS1) |
- BIT(VCS0) | BIT(VCS2),
+ BIT(BCS0) |
+ BIT(VCS0) |
+ BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3),
.require_force_probe = 1,
- .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
- BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
};
#undef PLATFORM
@@ -1131,8 +1172,11 @@ static const struct pci_device_id pciidlist[] = {
INTEL_RKL_IDS(&rkl_info),
INTEL_ADLS_IDS(&adl_s_info),
INTEL_ADLP_IDS(&adl_p_info),
+ INTEL_ADLN_IDS(&adl_p_info),
INTEL_DG1_IDS(&dg1_info),
INTEL_RPLS_IDS(&adl_s_info),
+ INTEL_RPLP_IDS(&adl_p_info),
+ INTEL_DG2_IDS(&dg2_info),
{0, 0, 0}
};
MODULE_DEVICE_TABLE(pci, pciidlist);
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