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path: root/drivers/gpu/drm/i915/display/intel_display.c
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Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/display/intel_display.c823
1 files changed, 466 insertions, 357 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 273323f30ae2..7bc4f3de691e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -54,6 +54,7 @@
#include "i915_reg.h"
#include "i915_utils.h"
#include "i9xx_plane.h"
+#include "i9xx_plane_regs.h"
#include "i9xx_wm.h"
#include "intel_atomic.h"
#include "intel_atomic_plane.h"
@@ -65,6 +66,8 @@
#include "intel_crt.h"
#include "intel_crtc.h"
#include "intel_crtc_state_dump.h"
+#include "intel_cursor_regs.h"
+#include "intel_cx0_phy.h"
#include "intel_ddi.h"
#include "intel_de.h"
#include "intel_display_driver.h"
@@ -109,6 +112,7 @@
#include "intel_sdvo.h"
#include "intel_snps_phy.h"
#include "intel_tc.h"
+#include "intel_tdf.h"
#include "intel_tv.h"
#include "intel_vblank.h"
#include "intel_vdsc.h"
@@ -118,6 +122,7 @@
#include "intel_wm.h"
#include "skl_scaler.h"
#include "skl_universal_plane.h"
+#include "skl_universal_plane_regs.h"
#include "skl_watermark.h"
#include "vlv_dpio_phy_regs.h"
#include "vlv_dsi.h"
@@ -241,53 +246,53 @@ is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
is_trans_port_sync_slave(crtc_state);
}
-static enum pipe bigjoiner_master_pipe(const struct intel_crtc_state *crtc_state)
+static enum pipe joiner_primary_pipe(const struct intel_crtc_state *crtc_state)
{
- return ffs(crtc_state->bigjoiner_pipes) - 1;
+ return ffs(crtc_state->joiner_pipes) - 1;
}
-u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state)
+u8 intel_crtc_joiner_secondary_pipes(const struct intel_crtc_state *crtc_state)
{
- if (crtc_state->bigjoiner_pipes)
- return crtc_state->bigjoiner_pipes & ~BIT(bigjoiner_master_pipe(crtc_state));
+ if (crtc_state->joiner_pipes)
+ return crtc_state->joiner_pipes & ~BIT(joiner_primary_pipe(crtc_state));
else
return 0;
}
-bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state)
+bool intel_crtc_is_joiner_secondary(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- return crtc_state->bigjoiner_pipes &&
- crtc->pipe != bigjoiner_master_pipe(crtc_state);
+ return crtc_state->joiner_pipes &&
+ crtc->pipe != joiner_primary_pipe(crtc_state);
}
-bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state)
+bool intel_crtc_is_joiner_primary(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- return crtc_state->bigjoiner_pipes &&
- crtc->pipe == bigjoiner_master_pipe(crtc_state);
+ return crtc_state->joiner_pipes &&
+ crtc->pipe == joiner_primary_pipe(crtc_state);
}
-static int intel_bigjoiner_num_pipes(const struct intel_crtc_state *crtc_state)
+static int intel_joiner_num_pipes(const struct intel_crtc_state *crtc_state)
{
- return hweight8(crtc_state->bigjoiner_pipes);
+ return hweight8(crtc_state->joiner_pipes);
}
u8 intel_crtc_joined_pipe_mask(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- return BIT(crtc->pipe) | crtc_state->bigjoiner_pipes;
+ return BIT(crtc->pipe) | crtc_state->joiner_pipes;
}
-struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state)
+struct intel_crtc *intel_primary_crtc(const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
- if (intel_crtc_is_bigjoiner_slave(crtc_state))
- return intel_crtc_for_pipe(i915, bigjoiner_master_pipe(crtc_state));
+ if (intel_crtc_is_joiner_secondary(crtc_state))
+ return intel_crtc_for_pipe(i915, joiner_primary_pipe(crtc_state));
else
return to_intel_crtc(crtc_state->uapi.crtc);
}
@@ -302,7 +307,7 @@ intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
/* Wait for the Pipe State to go off */
- if (intel_de_wait_for_clear(dev_priv, TRANSCONF(cpu_transcoder),
+ if (intel_de_wait_for_clear(dev_priv, TRANSCONF(dev_priv, cpu_transcoder),
TRANSCONF_STATE_ENABLE, 100))
drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n");
} else {
@@ -324,7 +329,8 @@ void assert_transcoder(struct drm_i915_private *dev_priv,
power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
if (wakeref) {
- u32 val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder));
+ u32 val = intel_de_read(dev_priv,
+ TRANSCONF(dev_priv, cpu_transcoder));
cur_state = !!(val & TRANSCONF_ENABLE);
intel_display_power_put(dev_priv, power_domain, wakeref);
@@ -377,11 +383,11 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
fallthrough;
case PORT_B:
port_mask = DPLL_PORTB_READY_MASK;
- dpll_reg = DPLL(0);
+ dpll_reg = DPLL(dev_priv, 0);
break;
case PORT_C:
port_mask = DPLL_PORTC_READY_MASK;
- dpll_reg = DPLL(0);
+ dpll_reg = DPLL(dev_priv, 0);
expected_mask <<= 4;
break;
case PORT_D:
@@ -433,7 +439,7 @@ void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
/* Wa_22012358565:adl-p */
if (DISPLAY_VER(dev_priv) == 13)
- intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe),
+ intel_de_rmw(dev_priv, PIPE_ARB_CTL(dev_priv, pipe),
0, PIPE_ARB_USE_PROG_SLOTS);
if (DISPLAY_VER(dev_priv) >= 14) {
@@ -448,7 +454,7 @@ void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
clear, set);
}
- val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder));
+ val = intel_de_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder));
if (val & TRANSCONF_ENABLE) {
/* we keep both pipes enabled on 830 */
drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv));
@@ -463,9 +469,9 @@ void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
TRANSCONF_PIXEL_COUNT_SCALING_X4);
}
- intel_de_write(dev_priv, TRANSCONF(cpu_transcoder),
+ intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder),
val | TRANSCONF_ENABLE);
- intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
+ intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder));
/*
* Until the pipe starts PIPEDSL reads will return a stale value,
@@ -494,7 +500,7 @@ void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state)
*/
assert_planes_disabled(crtc);
- val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder));
+ val = intel_de_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder));
if ((val & TRANSCONF_ENABLE) == 0)
return;
@@ -514,7 +520,7 @@ void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state)
old_crtc_state->dsc.compression_enable)
val &= ~TRANSCONF_PIXEL_COUNT_SCALING_MASK;
- intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
+ intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), val);
if (DISPLAY_VER(dev_priv) >= 12)
intel_de_rmw(dev_priv, hsw_chicken_trans_reg(dev_priv, cpu_transcoder),
@@ -797,14 +803,14 @@ intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
const struct drm_connector_state *connector_state;
const struct drm_connector *connector;
struct intel_encoder *encoder = NULL;
- struct intel_crtc *master_crtc;
+ struct intel_crtc *primary_crtc;
int num_encoders = 0;
int i;
- master_crtc = intel_master_crtc(crtc_state);
+ primary_crtc = intel_primary_crtc(crtc_state);
for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
- if (connector_state->crtc != &master_crtc->base)
+ if (connector_state->crtc != &primary_crtc->base)
continue;
encoder = to_intel_encoder(connector_state->best_encoder);
@@ -813,7 +819,7 @@ intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
drm_WARN(state->base.dev, num_encoders != 1,
"%d encoders for pipe %c\n",
- num_encoders, pipe_name(master_crtc->pipe));
+ num_encoders, pipe_name(primary_crtc->pipe));
return encoder;
}
@@ -1000,6 +1006,13 @@ static bool vrr_params_changed(const struct intel_crtc_state *old_crtc_state,
old_crtc_state->vrr.pipeline_full != new_crtc_state->vrr.pipeline_full;
}
+static bool cmrr_params_changed(const struct intel_crtc_state *old_crtc_state,
+ const struct intel_crtc_state *new_crtc_state)
+{
+ return old_crtc_state->cmrr.cmrr_m != new_crtc_state->cmrr.cmrr_m ||
+ old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n;
+}
+
static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state,
const struct intel_crtc_state *new_crtc_state)
{
@@ -1140,7 +1153,7 @@ static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state,
int i;
for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
- if (plane->need_async_flip_disable_wa &&
+ if (plane->need_async_flip_toggle_wa &&
plane->pipe == crtc->pipe &&
disable_async_flip_planes & BIT(plane->id)) {
/*
@@ -1641,7 +1654,7 @@ static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_sta
intel_vrr_set_transcoder_timings(crtc_state);
if (cpu_transcoder != TRANSCODER_EDP)
- intel_de_write(dev_priv, TRANS_MULT(cpu_transcoder),
+ intel_de_write(dev_priv, TRANS_MULT(dev_priv, cpu_transcoder),
crtc_state->pixel_multiplier - 1);
hsw_set_frame_start_delay(crtc_state);
@@ -1856,16 +1869,17 @@ static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
* according to register description and PRM.
*/
drm_WARN_ON(&dev_priv->drm,
- intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE);
+ intel_de_read(dev_priv, PFIT_CONTROL(dev_priv)) & PFIT_ENABLE);
assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
- intel_de_write(dev_priv, PFIT_PGM_RATIOS,
+ intel_de_write(dev_priv, PFIT_PGM_RATIOS(dev_priv),
crtc_state->gmch_pfit.pgm_ratios);
- intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control);
+ intel_de_write(dev_priv, PFIT_CONTROL(dev_priv),
+ crtc_state->gmch_pfit.control);
/* Border color in case we don't scale up to the full screen. Black by
* default, change to something else for debugging. */
- intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0);
+ intel_de_write(dev_priv, BCLRPAT(dev_priv, crtc->pipe), 0);
}
/* Prefer intel_encoder_is_combo() */
@@ -1894,11 +1908,10 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
{
/*
- * DG2's "TC1", although TC-capable output, doesn't share the same flow
- * as other platforms on the display engine side and rather rely on the
- * SNPS PHY, that is programmed separately
+ * Discrete GPU phy's are not attached to FIA's to support TC
+ * subsystem Legacy or non-legacy, and only support native DP/HDMI
*/
- if (IS_DG2(dev_priv))
+ if (IS_DGFX(dev_priv))
return false;
if (DISPLAY_VER(dev_priv) >= 13)
@@ -2102,8 +2115,9 @@ static void valleyview_crtc_enable(struct intel_atomic_state *state,
intel_de_write(dev_priv, VLV_PIPE_MSA_MISC(pipe), 0);
if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
- intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY);
- intel_de_write(dev_priv, CHV_CANVAS(pipe), 0);
+ intel_de_write(dev_priv, CHV_BLEND(dev_priv, pipe),
+ CHV_BLEND_LEGACY);
+ intel_de_write(dev_priv, CHV_CANVAS(dev_priv, pipe), 0);
}
crtc->active = true;
@@ -2191,8 +2205,8 @@ static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder);
drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n",
- intel_de_read(dev_priv, PFIT_CONTROL));
- intel_de_write(dev_priv, PFIT_CONTROL, 0);
+ intel_de_read(dev_priv, PFIT_CONTROL(dev_priv)));
+ intel_de_write(dev_priv, PFIT_CONTROL(dev_priv), 0);
}
static void i9xx_crtc_disable(struct intel_atomic_state *state,
@@ -2314,10 +2328,10 @@ static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
ilk_pipe_pixel_rate(crtc_state);
}
-static void intel_bigjoiner_adjust_timings(const struct intel_crtc_state *crtc_state,
- struct drm_display_mode *mode)
+static void intel_joiner_adjust_timings(const struct intel_crtc_state *crtc_state,
+ struct drm_display_mode *mode)
{
- int num_pipes = intel_bigjoiner_num_pipes(crtc_state);
+ int num_pipes = intel_joiner_num_pipes(crtc_state);
if (num_pipes < 2)
return;
@@ -2381,11 +2395,11 @@ static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state
drm_mode_copy(mode, pipe_mode);
intel_mode_from_crtc_timings(mode, mode);
mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) *
- (intel_bigjoiner_num_pipes(crtc_state) ?: 1);
+ (intel_joiner_num_pipes(crtc_state) ?: 1);
mode->vdisplay = drm_rect_height(&crtc_state->pipe_src);
- /* Derive per-pipe timings in case bigjoiner is used */
- intel_bigjoiner_adjust_timings(crtc_state, pipe_mode);
+ /* Derive per-pipe timings in case joiner is used */
+ intel_joiner_adjust_timings(crtc_state, pipe_mode);
intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
intel_crtc_compute_pixel_rate(crtc_state);
@@ -2399,9 +2413,9 @@ void intel_encoder_get_config(struct intel_encoder *encoder,
intel_crtc_readout_derived_state(crtc_state);
}
-static void intel_bigjoiner_compute_pipe_src(struct intel_crtc_state *crtc_state)
+static void intel_joiner_compute_pipe_src(struct intel_crtc_state *crtc_state)
{
- int num_pipes = intel_bigjoiner_num_pipes(crtc_state);
+ int num_pipes = intel_joiner_num_pipes(crtc_state);
int width, height;
if (num_pipes < 2)
@@ -2419,7 +2433,7 @@ static int intel_crtc_compute_pipe_src(struct intel_crtc_state *crtc_state)
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
- intel_bigjoiner_compute_pipe_src(crtc_state);
+ intel_joiner_compute_pipe_src(crtc_state);
/*
* Pipe horizontal size must be even in:
@@ -2464,8 +2478,8 @@ static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state)
/* Expand MSO per-segment transcoder timings to full */
intel_splitter_adjust_timings(crtc_state, pipe_mode);
- /* Derive per-pipe timings in case bigjoiner is used */
- intel_bigjoiner_adjust_timings(crtc_state, pipe_mode);
+ /* Derive per-pipe timings in case joiner is used */
+ intel_joiner_adjust_timings(crtc_state, pipe_mode);
intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
if (DISPLAY_VER(i915) < 4) {
@@ -2634,8 +2648,10 @@ void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
if (DISPLAY_VER(dev_priv) >= 5)
intel_set_m_n(dev_priv, m_n,
- PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder),
- PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
+ PIPE_DATA_M1(dev_priv, transcoder),
+ PIPE_DATA_N1(dev_priv, transcoder),
+ PIPE_LINK_M1(dev_priv, transcoder),
+ PIPE_LINK_N1(dev_priv, transcoder));
else
intel_set_m_n(dev_priv, m_n,
PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
@@ -2652,8 +2668,10 @@ void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
return;
intel_set_m_n(dev_priv, m_n,
- PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder),
- PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
+ PIPE_DATA_M2(dev_priv, transcoder),
+ PIPE_DATA_N2(dev_priv, transcoder),
+ PIPE_LINK_M2(dev_priv, transcoder),
+ PIPE_LINK_N2(dev_priv, transcoder));
}
static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
@@ -2692,7 +2710,8 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
* TRANS_SET_CONTEXT_LATENCY to configure the pipe vblank start.
*/
if (DISPLAY_VER(dev_priv) >= 13) {
- intel_de_write(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder),
+ intel_de_write(dev_priv,
+ TRANS_SET_CONTEXT_LATENCY(dev_priv, cpu_transcoder),
crtc_vblank_start - crtc_vdisplay);
/*
@@ -2703,26 +2722,27 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
}
if (DISPLAY_VER(dev_priv) >= 4)
- intel_de_write(dev_priv, TRANS_VSYNCSHIFT(cpu_transcoder),
+ intel_de_write(dev_priv,
+ TRANS_VSYNCSHIFT(dev_priv, cpu_transcoder),
vsyncshift);
- intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder),
+ intel_de_write(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder),
HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
HTOTAL(adjusted_mode->crtc_htotal - 1));
- intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder),
+ intel_de_write(dev_priv, TRANS_HBLANK(dev_priv, cpu_transcoder),
HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
HBLANK_END(adjusted_mode->crtc_hblank_end - 1));
- intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder),
+ intel_de_write(dev_priv, TRANS_HSYNC(dev_priv, cpu_transcoder),
HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
- intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
+ intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder),
VACTIVE(crtc_vdisplay - 1) |
VTOTAL(crtc_vtotal - 1));
- intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
+ intel_de_write(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder),
VBLANK_START(crtc_vblank_start - 1) |
VBLANK_END(crtc_vblank_end - 1));
- intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder),
+ intel_de_write(dev_priv, TRANS_VSYNC(dev_priv, cpu_transcoder),
VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
VSYNC_END(adjusted_mode->crtc_vsync_end - 1));
@@ -2732,7 +2752,7 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
* bits. */
if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
(pipe == PIPE_B || pipe == PIPE_C))
- intel_de_write(dev_priv, TRANS_VTOTAL(pipe),
+ intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, pipe),
VACTIVE(crtc_vdisplay - 1) |
VTOTAL(crtc_vtotal - 1));
}
@@ -2756,14 +2776,14 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc
* The hardware actually ignores TRANS_VBLANK.VBLANK_END in DP mode.
* But let's write it anyway to keep the state checker happy.
*/
- intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
+ intel_de_write(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder),
VBLANK_START(crtc_vblank_start - 1) |
VBLANK_END(crtc_vblank_end - 1));
/*
* The double buffer latch point for TRANS_VTOTAL
* is the transcoder's undelayed vblank.
*/
- intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
+ intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder),
VACTIVE(crtc_vdisplay - 1) |
VTOTAL(crtc_vtotal - 1));
}
@@ -2779,7 +2799,7 @@ static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
/* pipesrc controls the size that is scaled from, which should
* always be the user's requested size.
*/
- intel_de_write(dev_priv, PIPESRC(pipe),
+ intel_de_write(dev_priv, PIPESRC(dev_priv, pipe),
PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1));
}
@@ -2793,9 +2813,11 @@ static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
if (DISPLAY_VER(dev_priv) >= 9 ||
IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
- return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK_HSW;
+ return intel_de_read(dev_priv,
+ TRANSCONF(dev_priv, cpu_transcoder)) & TRANSCONF_INTERLACE_MASK_HSW;
else
- return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK;
+ return intel_de_read(dev_priv,
+ TRANSCONF(dev_priv, cpu_transcoder)) & TRANSCONF_INTERLACE_MASK;
}
static void intel_get_transcoder_timings(struct intel_crtc *crtc,
@@ -2807,31 +2829,33 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
u32 tmp;
- tmp = intel_de_read(dev_priv, TRANS_HTOTAL(cpu_transcoder));
+ tmp = intel_de_read(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder));
adjusted_mode->crtc_hdisplay = REG_FIELD_GET(HACTIVE_MASK, tmp) + 1;
adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1;
if (!transcoder_is_dsi(cpu_transcoder)) {
- tmp = intel_de_read(dev_priv, TRANS_HBLANK(cpu_transcoder));
+ tmp = intel_de_read(dev_priv,
+ TRANS_HBLANK(dev_priv, cpu_transcoder));
adjusted_mode->crtc_hblank_start = REG_FIELD_GET(HBLANK_START_MASK, tmp) + 1;
adjusted_mode->crtc_hblank_end = REG_FIELD_GET(HBLANK_END_MASK, tmp) + 1;
}
- tmp = intel_de_read(dev_priv, TRANS_HSYNC(cpu_transcoder));
+ tmp = intel_de_read(dev_priv, TRANS_HSYNC(dev_priv, cpu_transcoder));
adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp) + 1;
adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1;
- tmp = intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder));
+ tmp = intel_de_read(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder));
adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1;
adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1;
/* FIXME TGL+ DSI transcoders have this! */
if (!transcoder_is_dsi(cpu_transcoder)) {
- tmp = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder));
+ tmp = intel_de_read(dev_priv,
+ TRANS_VBLANK(dev_priv, cpu_transcoder));
adjusted_mode->crtc_vblank_start = REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1;
adjusted_mode->crtc_vblank_end = REG_FIELD_GET(VBLANK_END_MASK, tmp) + 1;
}
- tmp = intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder));
+ tmp = intel_de_read(dev_priv, TRANS_VSYNC(dev_priv, cpu_transcoder));
adjusted_mode->crtc_vsync_start = REG_FIELD_GET(VSYNC_START_MASK, tmp) + 1;
adjusted_mode->crtc_vsync_end = REG_FIELD_GET(VSYNC_END_MASK, tmp) + 1;
@@ -2844,24 +2868,25 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
if (DISPLAY_VER(dev_priv) >= 13 && !transcoder_is_dsi(cpu_transcoder))
adjusted_mode->crtc_vblank_start =
adjusted_mode->crtc_vdisplay +
- intel_de_read(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder));
+ intel_de_read(dev_priv,
+ TRANS_SET_CONTEXT_LATENCY(dev_priv, cpu_transcoder));
}
-static void intel_bigjoiner_adjust_pipe_src(struct intel_crtc_state *crtc_state)
+static void intel_joiner_adjust_pipe_src(struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- int num_pipes = intel_bigjoiner_num_pipes(crtc_state);
- enum pipe master_pipe, pipe = crtc->pipe;
+ int num_pipes = intel_joiner_num_pipes(crtc_state);
+ enum pipe primary_pipe, pipe = crtc->pipe;
int width;
if (num_pipes < 2)
return;
- master_pipe = bigjoiner_master_pipe(crtc_state);
+ primary_pipe = joiner_primary_pipe(crtc_state);
width = drm_rect_width(&crtc_state->pipe_src);
drm_rect_translate_to(&crtc_state->pipe_src,
- (pipe - master_pipe) * width, 0);
+ (pipe - primary_pipe) * width, 0);
}
static void intel_get_pipe_src_size(struct intel_crtc *crtc,
@@ -2871,13 +2896,13 @@ static void intel_get_pipe_src_size(struct intel_crtc *crtc,
struct drm_i915_private *dev_priv = to_i915(dev);
u32 tmp;
- tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe));
+ tmp = intel_de_read(dev_priv, PIPESRC(dev_priv, crtc->pipe));
drm_rect_init(&pipe_config->pipe_src, 0, 0,
REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1,
REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1);
- intel_bigjoiner_adjust_pipe_src(pipe_config);
+ intel_joiner_adjust_pipe_src(pipe_config);
}
void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
@@ -2944,8 +2969,8 @@ void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
- intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
- intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
+ intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), val);
+ intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder));
}
static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
@@ -2967,7 +2992,7 @@ static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state)
if (!i9xx_has_pfit(dev_priv))
return;
- tmp = intel_de_read(dev_priv, PFIT_CONTROL);
+ tmp = intel_de_read(dev_priv, PFIT_CONTROL(dev_priv));
if (!(tmp & PFIT_ENABLE))
return;
@@ -2982,7 +3007,7 @@ static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state)
crtc_state->gmch_pfit.control = tmp;
crtc_state->gmch_pfit.pgm_ratios =
- intel_de_read(dev_priv, PFIT_PGM_RATIOS);
+ intel_de_read(dev_priv, PFIT_PGM_RATIOS(dev_priv));
}
static enum intel_output_format
@@ -3027,7 +3052,8 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
ret = false;
- tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder));
+ tmp = intel_de_read(dev_priv,
+ TRANSCONF(dev_priv, pipe_config->cpu_transcoder));
if (!(tmp & TRANSCONF_ENABLE))
goto out;
@@ -3174,8 +3200,8 @@ void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
val |= TRANSCONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay);
- intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
- intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
+ intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), val);
+ intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder));
}
static void hsw_set_transconf(const struct intel_crtc_state *crtc_state)
@@ -3204,8 +3230,8 @@ static void hsw_set_transconf(const struct intel_crtc_state *crtc_state)
crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
val |= TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW;
- intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
- intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
+ intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), val);
+ intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder));
}
static void bdw_set_pipe_misc(const struct intel_crtc_state *crtc_state)
@@ -3324,8 +3350,10 @@ void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
if (DISPLAY_VER(dev_priv) >= 5)
intel_get_m_n(dev_priv, m_n,
- PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder),
- PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
+ PIPE_DATA_M1(dev_priv, transcoder),
+ PIPE_DATA_N1(dev_priv, transcoder),
+ PIPE_LINK_M1(dev_priv, transcoder),
+ PIPE_LINK_N1(dev_priv, transcoder));
else
intel_get_m_n(dev_priv, m_n,
PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
@@ -3342,8 +3370,10 @@ void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
return;
intel_get_m_n(dev_priv, m_n,
- PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder),
- PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
+ PIPE_DATA_M2(dev_priv, transcoder),
+ PIPE_DATA_N2(dev_priv, transcoder),
+ PIPE_LINK_M2(dev_priv, transcoder),
+ PIPE_LINK_N2(dev_priv, transcoder));
}
static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
@@ -3400,7 +3430,8 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc,
pipe_config->shared_dpll = NULL;
ret = false;
- tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder));
+ tmp = intel_de_read(dev_priv,
+ TRANSCONF(dev_priv, pipe_config->cpu_transcoder));
if (!(tmp & TRANSCONF_ENABLE))
goto out;
@@ -3461,7 +3492,7 @@ out:
return ret;
}
-static u8 bigjoiner_pipes(struct drm_i915_private *i915)
+static u8 joiner_pipes(struct drm_i915_private *i915)
{
u8 pipes;
@@ -3485,21 +3516,22 @@ static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv,
power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref)
- tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
+ tmp = intel_de_read(dev_priv,
+ TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder));
return tmp & TRANS_DDI_FUNC_ENABLE;
}
-static void enabled_bigjoiner_pipes(struct drm_i915_private *dev_priv,
- u8 *master_pipes, u8 *slave_pipes)
+static void enabled_joiner_pipes(struct drm_i915_private *dev_priv,
+ u8 *primary_pipes, u8 *secondary_pipes)
{
struct intel_crtc *crtc;
- *master_pipes = 0;
- *slave_pipes = 0;
+ *primary_pipes = 0;
+ *secondary_pipes = 0;
for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc,
- bigjoiner_pipes(dev_priv)) {
+ joiner_pipes(dev_priv)) {
enum intel_display_power_domain power_domain;
enum pipe pipe = crtc->pipe;
intel_wakeref_t wakeref;
@@ -3511,10 +3543,10 @@ static void enabled_bigjoiner_pipes(struct drm_i915_private *dev_priv,
if (!(tmp & BIG_JOINER_ENABLE))
continue;
- if (tmp & MASTER_BIG_JOINER_ENABLE)
- *master_pipes |= BIT(pipe);
+ if (tmp & PRIMARY_BIG_JOINER_ENABLE)
+ *primary_pipes |= BIT(pipe);
else
- *slave_pipes |= BIT(pipe);
+ *secondary_pipes |= BIT(pipe);
}
if (DISPLAY_VER(dev_priv) < 13)
@@ -3524,48 +3556,48 @@ static void enabled_bigjoiner_pipes(struct drm_i915_private *dev_priv,
with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) {
u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe));
- if (tmp & UNCOMPRESSED_JOINER_MASTER)
- *master_pipes |= BIT(pipe);
- if (tmp & UNCOMPRESSED_JOINER_SLAVE)
- *slave_pipes |= BIT(pipe);
+ if (tmp & UNCOMPRESSED_JOINER_PRIMARY)
+ *primary_pipes |= BIT(pipe);
+ if (tmp & UNCOMPRESSED_JOINER_SECONDARY)
+ *secondary_pipes |= BIT(pipe);
}
}
- /* Bigjoiner pipes should always be consecutive master and slave */
- drm_WARN(&dev_priv->drm, *slave_pipes != *master_pipes << 1,
- "Bigjoiner misconfigured (master pipes 0x%x, slave pipes 0x%x)\n",
- *master_pipes, *slave_pipes);
+ /* Joiner pipes should always be consecutive primary and secondary */
+ drm_WARN(&dev_priv->drm, *secondary_pipes != *primary_pipes << 1,
+ "Joiner misconfigured (primary pipes 0x%x, secondary pipes 0x%x)\n",
+ *primary_pipes, *secondary_pipes);
}
-static enum pipe get_bigjoiner_master_pipe(enum pipe pipe, u8 master_pipes, u8 slave_pipes)
+static enum pipe get_joiner_primary_pipe(enum pipe pipe, u8 primary_pipes, u8 secondary_pipes)
{
- if ((slave_pipes & BIT(pipe)) == 0)
+ if ((secondary_pipes & BIT(pipe)) == 0)
return pipe;
/* ignore everything above our pipe */
- master_pipes &= ~GENMASK(7, pipe);
+ primary_pipes &= ~GENMASK(7, pipe);
- /* highest remaining bit should be our master pipe */
- return fls(master_pipes) - 1;
+ /* highest remaining bit should be our primary pipe */
+ return fls(primary_pipes) - 1;
}
-static u8 get_bigjoiner_slave_pipes(enum pipe pipe, u8 master_pipes, u8 slave_pipes)
+static u8 get_joiner_secondary_pipes(enum pipe pipe, u8 primary_pipes, u8 secondary_pipes)
{
- enum pipe master_pipe, next_master_pipe;
+ enum pipe primary_pipe, next_primary_pipe;
- master_pipe = get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes);
+ primary_pipe = get_joiner_primary_pipe(pipe, primary_pipes, secondary_pipes);
- if ((master_pipes & BIT(master_pipe)) == 0)
+ if ((primary_pipes & BIT(primary_pipe)) == 0)
return 0;
- /* ignore our master pipe and everything below it */
- master_pipes &= ~GENMASK(master_pipe, 0);
+ /* ignore our primary pipe and everything below it */
+ primary_pipes &= ~GENMASK(primary_pipe, 0);
/* make sure a high bit is set for the ffs() */
- master_pipes |= BIT(7);
- /* lowest remaining bit should be the next master pipe */
- next_master_pipe = ffs(master_pipes) - 1;
+ primary_pipes |= BIT(7);
+ /* lowest remaining bit should be the next primary pipe */
+ next_primary_pipe = ffs(primary_pipes) - 1;
- return slave_pipes & GENMASK(next_master_pipe - 1, master_pipe);
+ return secondary_pipes & GENMASK(next_primary_pipe - 1, primary_pipe);
}
static u8 hsw_panel_transcoders(struct drm_i915_private *i915)
@@ -3584,7 +3616,7 @@ static u8 hsw_enabled_transcoders(struct intel_crtc *crtc)
struct drm_i915_private *dev_priv = to_i915(dev);
u8 panel_transcoder_mask = hsw_panel_transcoders(dev_priv);
enum transcoder cpu_transcoder;
- u8 master_pipes, slave_pipes;
+ u8 primary_pipes, secondary_pipes;
u8 enabled_transcoders = 0;
/*
@@ -3600,7 +3632,8 @@ static u8 hsw_enabled_transcoders(struct intel_crtc *crtc)
power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref)
- tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
+ tmp = intel_de_read(dev_priv,
+ TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder));
if (!(tmp & TRANS_DDI_FUNC_ENABLE))
continue;
@@ -3630,16 +3663,16 @@ static u8 hsw_enabled_transcoders(struct intel_crtc *crtc)
enabled_transcoders |= BIT(cpu_transcoder);
}
- /* single pipe or bigjoiner master */
+ /* single pipe or joiner primary */
cpu_transcoder = (enum transcoder) crtc->pipe;
if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder))
enabled_transcoders |= BIT(cpu_transcoder);
- /* bigjoiner slave -> consider the master pipe's transcoder as well */
- enabled_bigjoiner_pipes(dev_priv, &master_pipes, &slave_pipes);
- if (slave_pipes & BIT(crtc->pipe)) {
+ /* joiner secondary -> consider the primary pipe's transcoder as well */
+ enabled_joiner_pipes(dev_priv, &primary_pipes, &secondary_pipes);
+ if (secondary_pipes & BIT(crtc->pipe)) {
cpu_transcoder = (enum transcoder)
- get_bigjoiner_master_pipe(crtc->pipe, master_pipes, slave_pipes);
+ get_joiner_primary_pipe(crtc->pipe, primary_pipes, secondary_pipes);
if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder))
enabled_transcoders |= BIT(cpu_transcoder);
}
@@ -3707,13 +3740,15 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
return false;
if (hsw_panel_transcoders(dev_priv) & BIT(pipe_config->cpu_transcoder)) {
- tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
+ tmp = intel_de_read(dev_priv,
+ TRANS_DDI_FUNC_CTL(dev_priv, pipe_config->cpu_transcoder));
if ((tmp & TRANS_DDI_EDP_INPUT_MASK) == TRANS_DDI_EDP_INPUT_A_ONOFF)
pipe_config->pch_pfit.force_thru = true;
}
- tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder));
+ tmp = intel_de_read(dev_priv,
+ TRANSCONF(dev_priv, pipe_config->cpu_transcoder));
return tmp & TRANSCONF_ENABLE;
}
@@ -3764,21 +3799,21 @@ static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
return transcoder_is_dsi(pipe_config->cpu_transcoder);
}
-static void intel_bigjoiner_get_config(struct intel_crtc_state *crtc_state)
+static void intel_joiner_get_config(struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
- u8 master_pipes, slave_pipes;
+ u8 primary_pipes, secondary_pipes;
enum pipe pipe = crtc->pipe;
- enabled_bigjoiner_pipes(i915, &master_pipes, &slave_pipes);
+ enabled_joiner_pipes(i915, &primary_pipes, &secondary_pipes);
- if (((master_pipes | slave_pipes) & BIT(pipe)) == 0)
+ if (((primary_pipes | secondary_pipes) & BIT(pipe)) == 0)
return;
- crtc_state->bigjoiner_pipes =
- BIT(get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes)) |
- get_bigjoiner_slave_pipes(pipe, master_pipes, slave_pipes);
+ crtc_state->joiner_pipes =
+ BIT(get_joiner_primary_pipe(pipe, primary_pipes, secondary_pipes)) |
+ get_joiner_secondary_pipes(pipe, primary_pipes, secondary_pipes);
}
static bool hsw_get_pipe_config(struct intel_crtc *crtc,
@@ -3805,7 +3840,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
if (!active)
goto out;
- intel_bigjoiner_get_config(pipe_config);
+ intel_joiner_get_config(pipe_config);
intel_dsc_get_config(pipe_config);
if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
@@ -3819,7 +3854,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
if (IS_HASWELL(dev_priv)) {
u32 tmp = intel_de_read(dev_priv,
- TRANSCONF(pipe_config->cpu_transcoder));
+ TRANSCONF(dev_priv, pipe_config->cpu_transcoder));
if (tmp & TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW)
pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
@@ -3854,7 +3889,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
pipe_config->pixel_multiplier =
intel_de_read(dev_priv,
- TRANS_MULT(pipe_config->cpu_transcoder)) + 1;
+ TRANS_MULT(dev_priv, pipe_config->cpu_transcoder)) + 1;
} else {
pipe_config->pixel_multiplier = 1;
}
@@ -4030,11 +4065,12 @@ static int icl_add_linked_planes(struct intel_atomic_state *state)
return 0;
}
-static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
+static int icl_check_nv12_planes(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
struct intel_plane *plane, *linked;
struct intel_plane_state *plane_state;
int i;
@@ -4119,13 +4155,13 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
linked_state->uapi.dst = plane_state->uapi.dst;
if (icl_is_hdr_plane(dev_priv, plane->id)) {
- if (linked->id == PLANE_SPRITE5)
+ if (linked->id == PLANE_7)
plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL;
- else if (linked->id == PLANE_SPRITE4)
+ else if (linked->id == PLANE_6)
plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL;
- else if (linked->id == PLANE_SPRITE3)
+ else if (linked->id == PLANE_5)
plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL;
- else if (linked->id == PLANE_SPRITE2)
+ else if (linked->id == PLANE_4)
plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL;
else
MISSING_CASE(linked->id);
@@ -4135,17 +4171,6 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
return 0;
}
-static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
-{
- struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
- struct intel_atomic_state *state =
- to_intel_atomic_state(new_crtc_state->uapi.state);
- const struct intel_crtc_state *old_crtc_state =
- intel_atomic_get_old_crtc_state(state, crtc);
-
- return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
-}
-
static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
{
const struct drm_display_mode *pipe_mode =
@@ -4244,18 +4269,9 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
return ret;
}
- /*
- * May need to update pipe gamma enable bits
- * when C8 planes are getting enabled/disabled.
- */
- if (c8_planes_changed(crtc_state))
- crtc_state->uapi.color_mgmt_changed = true;
-
- if (intel_crtc_needs_color_update(crtc_state)) {
- ret = intel_color_check(crtc_state);
- if (ret)
- return ret;
- }
+ ret = intel_color_check(state, crtc);
+ if (ret)
+ return ret;
ret = intel_compute_pipe_wm(state, crtc);
if (ret) {
@@ -4464,7 +4480,7 @@ intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state,
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state));
+ WARN_ON(intel_crtc_is_joiner_secondary(crtc_state));
drm_property_replace_blob(&crtc_state->hw.degamma_lut,
crtc_state->uapi.degamma_lut);
@@ -4481,7 +4497,7 @@ intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state,
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state));
+ WARN_ON(intel_crtc_is_joiner_secondary(crtc_state));
crtc_state->hw.enable = crtc_state->uapi.enable;
crtc_state->hw.active = crtc_state->uapi.active;
@@ -4495,79 +4511,79 @@ intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state,
}
static void
-copy_bigjoiner_crtc_state_nomodeset(struct intel_atomic_state *state,
- struct intel_crtc *slave_crtc)
+copy_joiner_crtc_state_nomodeset(struct intel_atomic_state *state,
+ struct intel_crtc *secondary_crtc)
{
- struct intel_crtc_state *slave_crtc_state =
- intel_atomic_get_new_crtc_state(state, slave_crtc);
- struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state);
- const struct intel_crtc_state *master_crtc_state =
- intel_atomic_get_new_crtc_state(state, master_crtc);
+ struct intel_crtc_state *secondary_crtc_state =
+ intel_atomic_get_new_crtc_state(state, secondary_crtc);
+ struct intel_crtc *primary_crtc = intel_primary_crtc(secondary_crtc_state);
+ const struct intel_crtc_state *primary_crtc_state =
+ intel_atomic_get_new_crtc_state(state, primary_crtc);
- drm_property_replace_blob(&slave_crtc_state->hw.degamma_lut,
- master_crtc_state->hw.degamma_lut);
- drm_property_replace_blob(&slave_crtc_state->hw.gamma_lut,
- master_crtc_state->hw.gamma_lut);
- drm_property_replace_blob(&slave_crtc_state->hw.ctm,
- master_crtc_state->hw.ctm);
+ drm_property_replace_blob(&secondary_crtc_state->hw.degamma_lut,
+ primary_crtc_state->hw.degamma_lut);
+ drm_property_replace_blob(&secondary_crtc_state->hw.gamma_lut,
+ primary_crtc_state->hw.gamma_lut);
+ drm_property_replace_blob(&secondary_crtc_state->hw.ctm,
+ primary_crtc_state->hw.ctm);
- slave_crtc_state->uapi.color_mgmt_changed = master_crtc_state->uapi.color_mgmt_changed;
+ secondary_crtc_state->uapi.color_mgmt_changed = primary_crtc_state->uapi.color_mgmt_changed;
}
static int
-copy_bigjoiner_crtc_state_modeset(struct intel_atomic_state *state,
- struct intel_crtc *slave_crtc)
-{
- struct intel_crtc_state *slave_crtc_state =
- intel_atomic_get_new_crtc_state(state, slave_crtc);
- struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state);
- const struct intel_crtc_state *master_crtc_state =
- intel_atomic_get_new_crtc_state(state, master_crtc);
+copy_joiner_crtc_state_modeset(struct intel_atomic_state *state,
+ struct intel_crtc *secondary_crtc)
+{
+ struct intel_crtc_state *secondary_crtc_state =
+ intel_atomic_get_new_crtc_state(state, secondary_crtc);
+ struct intel_crtc *primary_crtc = intel_primary_crtc(secondary_crtc_state);
+ const struct intel_crtc_state *primary_crtc_state =
+ intel_atomic_get_new_crtc_state(state, primary_crtc);
struct intel_crtc_state *saved_state;
- WARN_ON(master_crtc_state->bigjoiner_pipes !=
- slave_crtc_state->bigjoiner_pipes);
+ WARN_ON(primary_crtc_state->joiner_pipes !=
+ secondary_crtc_state->joiner_pipes);
- saved_state = kmemdup(master_crtc_state, sizeof(*saved_state), GFP_KERNEL);
+ saved_state = kmemdup(primary_crtc_state, sizeof(*saved_state), GFP_KERNEL);
if (!saved_state)
return -ENOMEM;
/* preserve some things from the slave's original crtc state */
- saved_state->uapi = slave_crtc_state->uapi;
- saved_state->scaler_state = slave_crtc_state->scaler_state;
- saved_state->shared_dpll = slave_crtc_state->shared_dpll;
- saved_state->crc_enabled = slave_crtc_state->crc_enabled;
-
- intel_crtc_free_hw_state(slave_crtc_state);
- if (slave_crtc_state->dp_tunnel_ref.tunnel)
- drm_dp_tunnel_ref_put(&slave_crtc_state->dp_tunnel_ref);
- memcpy(slave_crtc_state, saved_state, sizeof(*slave_crtc_state));
+ saved_state->uapi = secondary_crtc_state->uapi;
+ saved_state->scaler_state = secondary_crtc_state->scaler_state;
+ saved_state->shared_dpll = secondary_crtc_state->shared_dpll;
+ saved_state->crc_enabled = secondary_crtc_state->crc_enabled;
+
+ intel_crtc_free_hw_state(secondary_crtc_state);
+ if (secondary_crtc_state->dp_tunnel_ref.tunnel)
+ drm_dp_tunnel_ref_put(&secondary_crtc_state->dp_tunnel_ref);
+ memcpy(secondary_crtc_state, saved_state, sizeof(*secondary_crtc_state));
kfree(saved_state);
/* Re-init hw state */
- memset(&slave_crtc_state->hw, 0, sizeof(slave_crtc_state->hw));
- slave_crtc_state->hw.enable = master_crtc_state->hw.enable;
- slave_crtc_state->hw.active = master_crtc_state->hw.active;
- drm_mode_copy(&slave_crtc_state->hw.mode,
- &master_crtc_state->hw.mode);
- drm_mode_copy(&slave_crtc_state->hw.pipe_mode,
- &master_crtc_state->hw.pipe_mode);
- drm_mode_copy(&slave_crtc_state->hw.adjusted_mode,
- &master_crtc_state->hw.adjusted_mode);
- slave_crtc_state->hw.scaling_filter = master_crtc_state->hw.scaling_filter;
-
- if (master_crtc_state->dp_tunnel_ref.tunnel)
- drm_dp_tunnel_ref_get(master_crtc_state->dp_tunnel_ref.tunnel,
- &slave_crtc_state->dp_tunnel_ref);
-
- copy_bigjoiner_crtc_state_nomodeset(state, slave_crtc);
-
- slave_crtc_state->uapi.mode_changed = master_crtc_state->uapi.mode_changed;
- slave_crtc_state->uapi.connectors_changed = master_crtc_state->uapi.connectors_changed;
- slave_crtc_state->uapi.active_changed = master_crtc_state->uapi.active_changed;
-
- WARN_ON(master_crtc_state->bigjoiner_pipes !=
- slave_crtc_state->bigjoiner_pipes);
+ memset(&secondary_crtc_state->hw, 0, sizeof(secondary_crtc_state->hw));
+ secondary_crtc_state->hw.enable = primary_crtc_state->hw.enable;
+ secondary_crtc_state->hw.active = primary_crtc_state->hw.active;
+ drm_mode_copy(&secondary_crtc_state->hw.mode,
+ &primary_crtc_state->hw.mode);
+ drm_mode_copy(&secondary_crtc_state->hw.pipe_mode,
+ &primary_crtc_state->hw.pipe_mode);
+ drm_mode_copy(&secondary_crtc_state->hw.adjusted_mode,
+ &primary_crtc_state->hw.adjusted_mode);
+ secondary_crtc_state->hw.scaling_filter = primary_crtc_state->hw.scaling_filter;
+
+ if (primary_crtc_state->dp_tunnel_ref.tunnel)
+ drm_dp_tunnel_ref_get(primary_crtc_state->dp_tunnel_ref.tunnel,
+ &secondary_crtc_state->dp_tunnel_ref);
+
+ copy_joiner_crtc_state_nomodeset(state, secondary_crtc);
+
+ secondary_crtc_state->uapi.mode_changed = primary_crtc_state->uapi.mode_changed;
+ secondary_crtc_state->uapi.connectors_changed = primary_crtc_state->uapi.connectors_changed;
+ secondary_crtc_state->uapi.active_changed = primary_crtc_state->uapi.active_changed;
+
+ WARN_ON(primary_crtc_state->joiner_pipes !=
+ secondary_crtc_state->joiner_pipes);
return 0;
}
@@ -5000,6 +5016,24 @@ pipe_config_pll_mismatch(struct drm_printer *p, bool fastset,
intel_dpll_dump_hw_state(i915, p, b);
}
+static void
+pipe_config_cx0pll_mismatch(struct drm_printer *p, bool fastset,
+ const struct intel_crtc *crtc,
+ const char *name,
+ const struct intel_cx0pll_state *a,
+ const struct intel_cx0pll_state *b)
+{
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ char *chipname = a->use_c10 ? "C10" : "C20";
+
+ pipe_config_mismatch(p, fastset, crtc, name, chipname);
+
+ drm_printf(p, "expected:\n");
+ intel_cx0pll_dump_hw_state(i915, a);
+ drm_printf(p, "found:\n");
+ intel_cx0pll_dump_hw_state(i915, b);
+}
+
bool
intel_pipe_config_compare(const struct intel_crtc_state *current_config,
const struct intel_crtc_state *pipe_config,
@@ -5051,6 +5085,16 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
} \
} while (0)
+#define PIPE_CONF_CHECK_LLI(name) do { \
+ if (current_config->name != pipe_config->name) { \
+ pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
+ "(expected %lli, found %lli)", \
+ current_config->name, \
+ pipe_config->name); \
+ ret = false; \
+ } \
+} while (0)
+
#define PIPE_CONF_CHECK_BOOL(name) do { \
if (current_config->name != pipe_config->name) { \
BUILD_BUG_ON_MSG(!__same_type(current_config->name, bool), \
@@ -5103,6 +5147,16 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
} \
} while (0)
+#define PIPE_CONF_CHECK_PLL_CX0(name) do { \
+ if (!intel_cx0pll_compare_hw_state(&current_config->name, \
+ &pipe_config->name)) { \
+ pipe_config_cx0pll_mismatch(&p, fastset, crtc, __stringify(name), \
+ &current_config->name, \
+ &pipe_config->name); \
+ ret = false; \
+ } \
+} while (0)
+
#define PIPE_CONF_CHECK_TIMINGS(name) do { \
PIPE_CONF_CHECK_I(name.crtc_hdisplay); \
PIPE_CONF_CHECK_I(name.crtc_htotal); \
@@ -5318,9 +5372,11 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
* Panel replay has to be enabled before link training. PSR doesn't have
* this requirement -> check these only if using panel replay
*/
- if (current_config->has_panel_replay || pipe_config->has_panel_replay) {
+ if (current_config->active_planes &&
+ (current_config->has_panel_replay ||
+ pipe_config->has_panel_replay)) {
PIPE_CONF_CHECK_BOOL(has_psr);
- PIPE_CONF_CHECK_BOOL(has_psr2);
+ PIPE_CONF_CHECK_BOOL(has_sel_update);
PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
PIPE_CONF_CHECK_BOOL(enable_psr2_su_region_et);
PIPE_CONF_CHECK_BOOL(has_panel_replay);
@@ -5335,6 +5391,10 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
if (dev_priv->display.dpll.mgr || HAS_GMCH(dev_priv))
PIPE_CONF_CHECK_PLL(dpll_hw_state);
+ /* FIXME convert MTL+ platforms over to dpll_mgr */
+ if (DISPLAY_VER(dev_priv) >= 14)
+ PIPE_CONF_CHECK_PLL_CX0(dpll_hw_state.cx0pll);
+
PIPE_CONF_CHECK_X(dsi_pll.ctrl);
PIPE_CONF_CHECK_X(dsi_pll.div);
@@ -5365,7 +5425,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
PIPE_CONF_CHECK_I(master_transcoder);
- PIPE_CONF_CHECK_X(bigjoiner_pipes);
+ PIPE_CONF_CHECK_X(joiner_pipes);
PIPE_CONF_CHECK_BOOL(dsc.config.block_pred_enable);
PIPE_CONF_CHECK_BOOL(dsc.config.convert_rgb);
@@ -5415,10 +5475,14 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_I(vrr.guardband);
PIPE_CONF_CHECK_I(vrr.vsync_start);
PIPE_CONF_CHECK_I(vrr.vsync_end);
+ PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
+ PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
+ PIPE_CONF_CHECK_BOOL(cmrr.enable);
}
#undef PIPE_CONF_CHECK_X
#undef PIPE_CONF_CHECK_I
+#undef PIPE_CONF_CHECK_LLI
#undef PIPE_CONF_CHECK_BOOL
#undef PIPE_CONF_CHECK_P
#undef PIPE_CONF_CHECK_FLAGS
@@ -5567,6 +5631,40 @@ int intel_modeset_all_pipes_late(struct intel_atomic_state *state,
return 0;
}
+int intel_modeset_commit_pipes(struct drm_i915_private *i915,
+ u8 pipe_mask,
+ struct drm_modeset_acquire_ctx *ctx)
+{
+ struct drm_atomic_state *state;
+ struct intel_crtc *crtc;
+ int ret;
+
+ state = drm_atomic_state_alloc(&i915->drm);
+ if (!state)
+ return -ENOMEM;
+
+ state->acquire_ctx = ctx;
+ to_intel_atomic_state(state)->internal = true;
+
+ for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, pipe_mask) {
+ struct intel_crtc_state *crtc_state =
+ intel_atomic_get_crtc_state(state, crtc);
+
+ if (IS_ERR(crtc_state)) {
+ ret = PTR_ERR(crtc_state);
+ goto out;
+ }
+
+ crtc_state->uapi.connectors_changed = true;
+ }
+
+ ret = drm_atomic_commit(state);
+out:
+ drm_atomic_state_put(state);
+
+ return ret;
+}
+
/*
* This implements the workaround described in the "notes" section of the mode
* set sequence documentation. When going from no pipes or single pipe to
@@ -5729,9 +5827,9 @@ static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv)
IS_IVYBRIDGE(dev_priv);
}
-static int intel_crtc_add_bigjoiner_planes(struct intel_atomic_state *state,
- struct intel_crtc *crtc,
- struct intel_crtc *other)
+static int intel_crtc_add_joiner_planes(struct intel_atomic_state *state,
+ struct intel_crtc *crtc,
+ struct intel_crtc *other)
{
const struct intel_plane_state __maybe_unused *plane_state;
struct intel_plane *plane;
@@ -5746,7 +5844,7 @@ static int intel_crtc_add_bigjoiner_planes(struct intel_atomic_state *state,
return intel_crtc_add_planes_to_state(state, other, plane_ids);
}
-static int intel_bigjoiner_add_affected_planes(struct intel_atomic_state *state)
+static int intel_joiner_add_affected_planes(struct intel_atomic_state *state)
{
struct drm_i915_private *i915 = to_i915(state->base.dev);
const struct intel_crtc_state *crtc_state;
@@ -5757,13 +5855,13 @@ static int intel_bigjoiner_add_affected_planes(struct intel_atomic_state *state)
struct intel_crtc *other;
for_each_intel_crtc_in_pipe_mask(&i915->drm, other,
- crtc_state->bigjoiner_pipes) {
+ crtc_state->joiner_pipes) {
int ret;
if (crtc == other)
continue;
- ret = intel_crtc_add_bigjoiner_planes(state, crtc, other);
+ ret = intel_crtc_add_joiner_planes(state, crtc, other);
if (ret)
return ret;
}
@@ -5785,7 +5883,7 @@ static int intel_atomic_check_planes(struct intel_atomic_state *state)
if (ret)
return ret;
- ret = intel_bigjoiner_add_affected_planes(state);
+ ret = intel_joiner_add_affected_planes(state);
if (ret)
return ret;
@@ -5803,7 +5901,7 @@ static int intel_atomic_check_planes(struct intel_atomic_state *state)
new_crtc_state, i) {
u8 old_active_planes, new_active_planes;
- ret = icl_check_nv12_planes(new_crtc_state);
+ ret = icl_check_nv12_planes(state, crtc);
if (ret)
return ret;
@@ -5885,70 +5983,70 @@ static bool intel_pipes_need_modeset(struct intel_atomic_state *state,
return false;
}
-static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state,
- struct intel_crtc *master_crtc)
+static int intel_atomic_check_joiner(struct intel_atomic_state *state,
+ struct intel_crtc *primary_crtc)
{
struct drm_i915_private *i915 = to_i915(state->base.dev);
- struct intel_crtc_state *master_crtc_state =
- intel_atomic_get_new_crtc_state(state, master_crtc);
- struct intel_crtc *slave_crtc;
+ struct intel_crtc_state *primary_crtc_state =
+ intel_atomic_get_new_crtc_state(state, primary_crtc);
+ struct intel_crtc *secondary_crtc;
- if (!master_crtc_state->bigjoiner_pipes)
+ if (!primary_crtc_state->joiner_pipes)
return 0;
/* sanity check */
if (drm_WARN_ON(&i915->drm,
- master_crtc->pipe != bigjoiner_master_pipe(master_crtc_state)))
+ primary_crtc->pipe != joiner_primary_pipe(primary_crtc_state)))
return -EINVAL;
- if (master_crtc_state->bigjoiner_pipes & ~bigjoiner_pipes(i915)) {
+ if (primary_crtc_state->joiner_pipes & ~joiner_pipes(i915)) {
drm_dbg_kms(&i915->drm,
- "[CRTC:%d:%s] Cannot act as big joiner master "
+ "[CRTC:%d:%s] Cannot act as joiner primary "
"(need 0x%x as pipes, only 0x%x possible)\n",
- master_crtc->base.base.id, master_crtc->base.name,
- master_crtc_state->bigjoiner_pipes, bigjoiner_pipes(i915));
+ primary_crtc->base.base.id, primary_crtc->base.name,
+ primary_crtc_state->joiner_pipes, joiner_pipes(i915));
return -EINVAL;
}
- for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc,
- intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) {
- struct intel_crtc_state *slave_crtc_state;
+ for_each_intel_crtc_in_pipe_mask(&i915->drm, secondary_crtc,
+ intel_crtc_joiner_secondary_pipes(primary_crtc_state)) {
+ struct intel_crtc_state *secondary_crtc_state;
int ret;
- slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave_crtc);
- if (IS_ERR(slave_crtc_state))
- return PTR_ERR(slave_crtc_state);
+ secondary_crtc_state = intel_atomic_get_crtc_state(&state->base, secondary_crtc);
+ if (IS_ERR(secondary_crtc_state))
+ return PTR_ERR(secondary_crtc_state);
- /* master being enabled, slave was already configured? */
- if (slave_crtc_state->uapi.enable) {
+ /* primary being enabled, secondary was already configured? */
+ if (secondary_crtc_state->uapi.enable) {
drm_dbg_kms(&i915->drm,
- "[CRTC:%d:%s] Slave is enabled as normal CRTC, but "
- "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n",
- slave_crtc->base.base.id, slave_crtc->base.name,
- master_crtc->base.base.id, master_crtc->base.name);
+ "[CRTC:%d:%s] secondary is enabled as normal CRTC, but "
+ "[CRTC:%d:%s] claiming this CRTC for joiner.\n",
+ secondary_crtc->base.base.id, secondary_crtc->base.name,
+ primary_crtc->base.base.id, primary_crtc->base.name);
return -EINVAL;
}
/*
- * The state copy logic assumes the master crtc gets processed
- * before the slave crtc during the main compute_config loop.
+ * The state copy logic assumes the primary crtc gets processed
+ * before the secondary crtc during the main compute_config loop.
* This works because the crtcs are created in pipe order,
- * and the hardware requires master pipe < slave pipe as well.
+ * and the hardware requires primary pipe < secondary pipe as well.
* Should that change we need to rethink the logic.
*/
- if (WARN_ON(drm_crtc_index(&master_crtc->base) >
- drm_crtc_index(&slave_crtc->base)))
+ if (WARN_ON(drm_crtc_index(&primary_crtc->base) >
+ drm_crtc_index(&secondary_crtc->base)))
return -EINVAL;
drm_dbg_kms(&i915->drm,
- "[CRTC:%d:%s] Used as slave for big joiner master [CRTC:%d:%s]\n",
- slave_crtc->base.base.id, slave_crtc->base.name,
- master_crtc->base.base.id, master_crtc->base.name);
+ "[CRTC:%d:%s] Used as secondary for joiner primary [CRTC:%d:%s]\n",
+ secondary_crtc->base.base.id, secondary_crtc->base.name,
+ primary_crtc->base.base.id, primary_crtc->base.name);
- slave_crtc_state->bigjoiner_pipes =
- master_crtc_state->bigjoiner_pipes;
+ secondary_crtc_state->joiner_pipes =
+ primary_crtc_state->joiner_pipes;
- ret = copy_bigjoiner_crtc_state_modeset(state, slave_crtc);
+ ret = copy_joiner_crtc_state_modeset(state, secondary_crtc);
if (ret)
return ret;
}
@@ -5956,25 +6054,25 @@ static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state,
return 0;
}
-static void kill_bigjoiner_slave(struct intel_atomic_state *state,
- struct intel_crtc *master_crtc)
+static void kill_joiner_secondaries(struct intel_atomic_state *state,
+ struct intel_crtc *primary_crtc)
{
struct drm_i915_private *i915 = to_i915(state->base.dev);
- struct intel_crtc_state *master_crtc_state =
- intel_atomic_get_new_crtc_state(state, master_crtc);
- struct intel_crtc *slave_crtc;
+ struct intel_crtc_state *primary_crtc_state =
+ intel_atomic_get_new_crtc_state(state, primary_crtc);
+ struct intel_crtc *secondary_crtc;
- for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc,
- intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) {
- struct intel_crtc_state *slave_crtc_state =
- intel_atomic_get_new_crtc_state(state, slave_crtc);
+ for_each_intel_crtc_in_pipe_mask(&i915->drm, secondary_crtc,
+ intel_crtc_joiner_secondary_pipes(primary_crtc_state)) {
+ struct intel_crtc_state *secondary_crtc_state =
+ intel_atomic_get_new_crtc_state(state, secondary_crtc);
- slave_crtc_state->bigjoiner_pipes = 0;
+ secondary_crtc_state->joiner_pipes = 0;
- intel_crtc_copy_uapi_to_hw_state_modeset(state, slave_crtc);
+ intel_crtc_copy_uapi_to_hw_state_modeset(state, secondary_crtc);
}
- master_crtc_state->bigjoiner_pipes = 0;
+ primary_crtc_state->joiner_pipes = 0;
}
/**
@@ -6024,12 +6122,12 @@ static int intel_async_flip_check_uapi(struct intel_atomic_state *state,
}
/*
- * FIXME: Bigjoiner+async flip is busted currently.
+ * FIXME: joiner+async flip is busted currently.
* Remove this check once the issues are fixed.
*/
- if (new_crtc_state->bigjoiner_pipes) {
+ if (new_crtc_state->joiner_pipes) {
drm_dbg_kms(&i915->drm,
- "[CRTC:%d:%s] async flip disallowed with bigjoiner\n",
+ "[CRTC:%d:%s] async flip disallowed with joiner\n",
crtc->base.base.id, crtc->base.name);
return -EINVAL;
}
@@ -6166,6 +6264,13 @@ static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct in
return -EINVAL;
}
+ /*
+ * We turn the first async flip request into a sync flip
+ * so that we can reconfigure the plane (eg. change modifier).
+ */
+ if (!new_crtc_state->do_async_flip)
+ continue;
+
if (old_plane_state->view.color_plane[0].mapping_stride !=
new_plane_state->view.color_plane[0].mapping_stride) {
drm_dbg_kms(&i915->drm,
@@ -6247,7 +6352,7 @@ static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct in
return 0;
}
-static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state)
+static int intel_joiner_add_affected_crtcs(struct intel_atomic_state *state)
{
struct drm_i915_private *i915 = to_i915(state->base.dev);
struct intel_crtc_state *crtc_state;
@@ -6257,9 +6362,9 @@ static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state)
int i;
for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
- affected_pipes |= crtc_state->bigjoiner_pipes;
+ affected_pipes |= crtc_state->joiner_pipes;
if (intel_crtc_needs_modeset(crtc_state))
- modeset_pipes |= crtc_state->bigjoiner_pipes;
+ modeset_pipes |= crtc_state->joiner_pipes;
}
for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, affected_pipes) {
@@ -6285,10 +6390,10 @@ static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state)
}
for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
- /* Kill old bigjoiner link, we may re-establish afterwards */
+ /* Kill old joiner link, we may re-establish afterwards */
if (intel_crtc_needs_modeset(crtc_state) &&
- intel_crtc_is_bigjoiner_master(crtc_state))
- kill_bigjoiner_slave(state, crtc);
+ intel_crtc_is_joiner_primary(crtc_state))
+ kill_joiner_secondaries(state, crtc);
}
return 0;
@@ -6306,7 +6411,7 @@ static int intel_atomic_check_config(struct intel_atomic_state *state,
*failed_pipe = INVALID_PIPE;
- ret = intel_bigjoiner_add_affected_crtcs(state);
+ ret = intel_joiner_add_affected_crtcs(state);
if (ret)
return ret;
@@ -6316,14 +6421,14 @@ static int intel_atomic_check_config(struct intel_atomic_state *state,
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
if (!intel_crtc_needs_modeset(new_crtc_state)) {
- if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
- copy_bigjoiner_crtc_state_nomodeset(state, crtc);
+ if (intel_crtc_is_joiner_secondary(new_crtc_state))
+ copy_joiner_crtc_state_nomodeset(state, crtc);
else
intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc);
continue;
}
- if (drm_WARN_ON(&i915->drm, intel_crtc_is_bigjoiner_slave(new_crtc_state)))
+ if (drm_WARN_ON(&i915->drm, intel_crtc_is_joiner_secondary(new_crtc_state)))
continue;
ret = intel_crtc_prepare_cleared_state(state, crtc);
@@ -6342,7 +6447,7 @@ static int intel_atomic_check_config(struct intel_atomic_state *state,
if (!intel_crtc_needs_modeset(new_crtc_state))
continue;
- if (drm_WARN_ON(&i915->drm, intel_crtc_is_bigjoiner_slave(new_crtc_state)))
+ if (drm_WARN_ON(&i915->drm, intel_crtc_is_joiner_secondary(new_crtc_state)))
continue;
if (!new_crtc_state->hw.enable)
@@ -6453,12 +6558,12 @@ int intel_atomic_check(struct drm_device *dev,
if (!intel_crtc_needs_modeset(new_crtc_state))
continue;
- if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) {
+ if (intel_crtc_is_joiner_secondary(new_crtc_state)) {
drm_WARN_ON(&dev_priv->drm, new_crtc_state->uapi.enable);
continue;
}
- ret = intel_atomic_check_bigjoiner(state, crtc);
+ ret = intel_atomic_check_joiner(state, crtc);
if (ret)
goto fail;
}
@@ -6468,7 +6573,7 @@ int intel_atomic_check(struct drm_device *dev,
if (!intel_crtc_needs_modeset(new_crtc_state))
continue;
- intel_bigjoiner_adjust_pipe_src(new_crtc_state);
+ intel_joiner_adjust_pipe_src(new_crtc_state);
intel_crtc_check_fastset(old_crtc_state, new_crtc_state);
}
@@ -6508,8 +6613,8 @@ int intel_atomic_check(struct drm_device *dev,
intel_crtc_flag_modeset(new_crtc_state);
}
- if (new_crtc_state->bigjoiner_pipes) {
- if (intel_pipes_need_modeset(state, new_crtc_state->bigjoiner_pipes))
+ if (new_crtc_state->joiner_pipes) {
+ if (intel_pipes_need_modeset(state, new_crtc_state->joiner_pipes))
intel_crtc_flag_modeset(new_crtc_state);
}
}
@@ -6800,7 +6905,8 @@ static void intel_pre_update_crtc(struct intel_atomic_state *state,
intel_crtc_needs_fastset(new_crtc_state))
icl_set_pipe_chicken(new_crtc_state);
- if (vrr_params_changed(old_crtc_state, new_crtc_state))
+ if (vrr_params_changed(old_crtc_state, new_crtc_state) ||
+ cmrr_params_changed(old_crtc_state, new_crtc_state))
intel_vrr_set_transcoder_timings(new_crtc_state);
}
@@ -6923,7 +7029,7 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state)
if ((disable_pipes & BIT(crtc->pipe)) == 0)
continue;
- if (intel_crtc_is_bigjoiner_slave(old_crtc_state))
+ if (intel_crtc_is_joiner_secondary(old_crtc_state))
continue;
/* In case of Transcoder port Sync master slave CRTCs can be
@@ -6945,7 +7051,7 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state)
if ((disable_pipes & BIT(crtc->pipe)) == 0)
continue;
- if (intel_crtc_is_bigjoiner_slave(old_crtc_state))
+ if (intel_crtc_is_joiner_secondary(old_crtc_state))
continue;
intel_old_crtc_state_disables(state, crtc);
@@ -7024,8 +7130,8 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
while (update_pipes) {
/*
- * Commit in reverse order to make bigjoiner master
- * send the uapi events after slaves are done.
+ * Commit in reverse order to make joiner primary
+ * send the uapi events after secondaries are done.
*/
for_each_oldnew_intel_crtc_in_state_reverse(state, crtc, old_crtc_state,
new_crtc_state, i) {
@@ -7070,7 +7176,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
if ((modeset_pipes & BIT(pipe)) == 0)
continue;
- if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
+ if (intel_crtc_is_joiner_secondary(new_crtc_state))
continue;
if (intel_dp_mst_is_slave_trans(new_crtc_state) ||
@@ -7084,7 +7190,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
/*
* Then we enable all remaining pipes that depend on other
- * pipes: MST slaves and port sync masters, big joiner master
+ * pipes: MST slaves and port sync masters
*/
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
enum pipe pipe = crtc->pipe;
@@ -7092,7 +7198,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
if ((modeset_pipes & BIT(pipe)) == 0)
continue;
- if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
+ if (intel_crtc_is_joiner_secondary(new_crtc_state))
continue;
modeset_pipes &= ~intel_crtc_joined_pipe_mask(new_crtc_state);
@@ -7113,8 +7219,8 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
}
/*
- * Commit in reverse order to make bigjoiner master
- * send the uapi events after slaves are done.
+ * Commit in reverse order to make joiner primary
+ * send the uapi events after secondaries are done.
*/
for_each_new_intel_crtc_in_state_reverse(state, crtc, new_crtc_state, i) {
enum pipe pipe = crtc->pipe;
@@ -7227,6 +7333,8 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
intel_atomic_commit_fence_wait(state);
+ intel_td_flush(dev_priv);
+
drm_atomic_helper_wait_for_dependencies(&state->base);
drm_dp_mst_atomic_wait_for_dependencies(&state->base);
intel_atomic_global_state_wait_for_dependencies(state);
@@ -7839,7 +7947,7 @@ static int max_dotclock(struct drm_i915_private *i915)
{
int max_dotclock = i915->display.cdclk.max_dotclk_freq;
- /* icl+ might use bigjoiner */
+ /* icl+ might use joiner */
if (DISPLAY_VER(i915) >= 11)
max_dotclock *= 2;
@@ -7964,7 +8072,7 @@ enum drm_mode_status intel_cpu_transcoder_mode_valid(struct drm_i915_private *de
enum drm_mode_status
intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
const struct drm_display_mode *mode,
- bool bigjoiner)
+ bool joiner)
{
int plane_width_max, plane_height_max;
@@ -7981,7 +8089,7 @@ intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
* too big for that.
*/
if (DISPLAY_VER(dev_priv) >= 11) {
- plane_width_max = 5120 << bigjoiner;
+ plane_width_max = 5120 << joiner;
plane_height_max = 4320;
} else {
plane_width_max = 5120;
@@ -8163,19 +8271,19 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
PLL_REF_INPUT_DREFCLK |
DPLL_VCO_ENABLE;
- intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder),
+ intel_de_write(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder),
HACTIVE(640 - 1) | HTOTAL(800 - 1));
- intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder),
+ intel_de_write(dev_priv, TRANS_HBLANK(dev_priv, cpu_transcoder),
HBLANK_START(640 - 1) | HBLANK_END(800 - 1));
- intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder),
+ intel_de_write(dev_priv, TRANS_HSYNC(dev_priv, cpu_transcoder),
HSYNC_START(656 - 1) | HSYNC_END(752 - 1));
- intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
+ intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder),
VACTIVE(480 - 1) | VTOTAL(525 - 1));
- intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
+ intel_de_write(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder),
VBLANK_START(480 - 1) | VBLANK_END(525 - 1));
- intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder),
+ intel_de_write(dev_priv, TRANS_VSYNC(dev_priv, cpu_transcoder),
VSYNC_START(490 - 1) | VSYNC_END(492 - 1));
- intel_de_write(dev_priv, PIPESRC(pipe),
+ intel_de_write(dev_priv, PIPESRC(dev_priv, pipe),
PIPESRC_WIDTH(640 - 1) | PIPESRC_HEIGHT(480 - 1));
intel_de_write(dev_priv, FP0(pipe), fp);
@@ -8186,11 +8294,12 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
* the P1/P2 dividers. Otherwise the DPLL will keep using the old
* dividers, even though the register value does change.
*/
- intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
- intel_de_write(dev_priv, DPLL(pipe), dpll);
+ intel_de_write(dev_priv, DPLL(dev_priv, pipe),
+ dpll & ~DPLL_VGA_MODE_DIS);
+ intel_de_write(dev_priv, DPLL(dev_priv, pipe), dpll);
/* Wait for the clocks to stabilize. */
- intel_de_posting_read(dev_priv, DPLL(pipe));
+ intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe));
udelay(150);
/* The pixel multiplier can only be updated once the
@@ -8198,17 +8307,17 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
*
* So write it again.
*/
- intel_de_write(dev_priv, DPLL(pipe), dpll);
+ intel_de_write(dev_priv, DPLL(dev_priv, pipe), dpll);
/* We do this three times for luck */
for (i = 0; i < 3 ; i++) {
- intel_de_write(dev_priv, DPLL(pipe), dpll);
- intel_de_posting_read(dev_priv, DPLL(pipe));
+ intel_de_write(dev_priv, DPLL(dev_priv, pipe), dpll);
+ intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe));
udelay(150); /* wait for warmup */
}
- intel_de_write(dev_priv, TRANSCONF(pipe), TRANSCONF_ENABLE);
- intel_de_posting_read(dev_priv, TRANSCONF(pipe));
+ intel_de_write(dev_priv, TRANSCONF(dev_priv, pipe), TRANSCONF_ENABLE);
+ intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, pipe));
intel_wait_for_pipe_scanline_moving(crtc);
}
@@ -8221,23 +8330,23 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
pipe_name(pipe));
drm_WARN_ON(&dev_priv->drm,
- intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & DISP_ENABLE);
+ intel_de_read(dev_priv, DSPCNTR(dev_priv, PLANE_A)) & DISP_ENABLE);
drm_WARN_ON(&dev_priv->drm,
- intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & DISP_ENABLE);
+ intel_de_read(dev_priv, DSPCNTR(dev_priv, PLANE_B)) & DISP_ENABLE);
drm_WARN_ON(&dev_priv->drm,
- intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DISP_ENABLE);
+ intel_de_read(dev_priv, DSPCNTR(dev_priv, PLANE_C)) & DISP_ENABLE);
drm_WARN_ON(&dev_priv->drm,
- intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE_MASK);
+ intel_de_read(dev_priv, CURCNTR(dev_priv, PIPE_A)) & MCURSOR_MODE_MASK);
drm_WARN_ON(&dev_priv->drm,
- intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE_MASK);
+ intel_de_read(dev_priv, CURCNTR(dev_priv, PIPE_B)) & MCURSOR_MODE_MASK);
- intel_de_write(dev_priv, TRANSCONF(pipe), 0);
- intel_de_posting_read(dev_priv, TRANSCONF(pipe));
+ intel_de_write(dev_priv, TRANSCONF(dev_priv, pipe), 0);
+ intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, pipe));
intel_wait_for_pipe_scanline_stopped(crtc);
- intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
- intel_de_posting_read(dev_priv, DPLL(pipe));
+ intel_de_write(dev_priv, DPLL(dev_priv, pipe), DPLL_VGA_MODE_DIS);
+ intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe));
}
void intel_hpd_poll_fini(struct drm_i915_private *i915)
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