diff options
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dc.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dc.h | 137 |
1 files changed, 72 insertions, 65 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 77ef9d1f9ea8..8e1e40083ec8 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -47,7 +47,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.177" +#define DC_VER "3.2.196" #define MAX_SURFACES 3 #define MAX_PLANES 6 @@ -162,6 +162,11 @@ struct dc_color_caps { struct mpc_color_caps mpc; }; +struct dc_dmub_caps { + bool psr; + bool mclk_sw; +}; + struct dc_caps { uint32_t max_streams; uint32_t max_links; @@ -196,12 +201,21 @@ struct dc_caps { unsigned int cursor_cache_size; struct dc_plane_cap planes[MAX_PLANES]; struct dc_color_caps color; + struct dc_dmub_caps dmub_caps; bool dp_hpo; - bool hdmi_frl_pcon_support; + bool dp_hdmi21_pcon_support; bool edp_dsc_support; bool vbios_lttpr_aware; bool vbios_lttpr_enable; uint32_t max_otg_num; + uint32_t max_cab_allocation_bytes; + uint32_t cache_line_size; + uint32_t cache_num_ways; + uint16_t subvp_fw_processing_delay_us; + uint16_t subvp_prefetch_end_to_mall_start_us; + uint16_t subvp_pstate_allow_width_us; + uint16_t subvp_vertical_int_margin_us; + bool seamless_odm; }; struct dc_bug_wa { @@ -222,7 +236,6 @@ struct dc_dcc_setting { unsigned int max_compressed_blk_size; unsigned int max_uncompressed_blk_size; bool independent_64b_blks; -#if defined(CONFIG_DRM_AMD_DC_DCN) //These bitfields to be used starting with DCN struct { uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN (the worst compression case) @@ -230,7 +243,6 @@ struct dc_dcc_setting { uint32_t dcc_256_128_128 : 1; //available starting with DCN uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN (the best compression case) } dcc_controls; -#endif }; struct dc_surface_dcc_cap { @@ -331,15 +343,15 @@ struct dc_config { bool disable_dmcu; bool enable_4to1MPC; bool enable_windowed_mpo_odm; - bool allow_edp_hotplug_detection; -#if defined(CONFIG_DRM_AMD_DC_DCN) + uint32_t allow_edp_hotplug_detection; bool clamp_min_dcfclk; -#endif uint64_t vblank_alignment_dto_params; uint8_t vblank_alignment_max_frame_time_diff; bool is_asymmetric_memory; bool is_single_rank_dimm; bool use_pipe_ctx_sync_logic; + bool ignore_dpref_ss; + bool enable_mipi_converter_optimization; }; enum visual_confirm { @@ -348,6 +360,8 @@ enum visual_confirm { VISUAL_CONFIRM_HDR = 2, VISUAL_CONFIRM_MPCTREE = 4, VISUAL_CONFIRM_PSR = 5, + VISUAL_CONFIRM_SWAPCHAIN = 6, + VISUAL_CONFIRM_FAMS = 7, VISUAL_CONFIRM_SWIZZLE = 9, }; @@ -358,6 +372,12 @@ enum dc_psr_power_opts { psr_power_opt_ds_disable_allow = 0x100, }; +enum dml_hostvm_override_opts { + DML_HOSTVM_NO_OVERRIDE = 0x0, + DML_HOSTVM_OVERRIDE_FALSE = 0x1, + DML_HOSTVM_OVERRIDE_TRUE = 0x2, +}; + enum dcc_option { DCC_ENABLE = 0, DCC_DISABLE = 1, @@ -388,14 +408,12 @@ enum dcn_pwr_state { DCN_PWR_STATE_LOW_POWER = 3, }; -#if defined(CONFIG_DRM_AMD_DC_DCN) enum dcn_zstate_support_state { DCN_ZSTATE_SUPPORT_UNKNOWN, DCN_ZSTATE_SUPPORT_ALLOW, DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY, DCN_ZSTATE_SUPPORT_DISALLOW, }; -#endif /* * For any clocks that may differ per pipe * only the max is stored in this structure @@ -413,16 +431,21 @@ struct dc_clocks { int phyclk_khz; int dramclk_khz; bool p_state_change_support; -#if defined(CONFIG_DRM_AMD_DC_DCN) enum dcn_zstate_support_state zstate_support; bool dtbclk_en; -#endif + int ref_dtbclk_khz; + bool fclk_p_state_change_support; enum dcn_pwr_state pwr_state; /* * Elements below are not compared for the purposes of * optimization required */ bool prev_p_state_change_support; + bool fclk_prev_p_state_change_support; + int num_ways; + bool fw_based_mclk_switching; + bool fw_based_mclk_switching_shut_down; + int prev_num_ways; enum dtm_pstate dtm_level; int max_supported_dppclk_khz; int max_supported_dispclk_khz; @@ -519,9 +542,8 @@ union dpia_debug_options { uint32_t force_non_lttpr:1; /* bit 1 */ uint32_t extend_aux_rd_interval:1; /* bit 2 */ uint32_t disable_mst_dsc_work_around:1; /* bit 3 */ - uint32_t hpd_delay_in_ms:12; /* bits 4-15 */ - uint32_t disable_force_tbt3_work_around:1; /* bit 16 */ - uint32_t reserved:15; + uint32_t enable_force_tbt3_work_around:1; /* bit 4 */ + uint32_t reserved:27; } bits; uint32_t raw; }; @@ -646,9 +668,7 @@ struct dc_debug_options { bool disable_pplib_clock_request; bool disable_clock_gate; bool disable_mem_low_power; -#if defined(CONFIG_DRM_AMD_DC_DCN) bool pstate_enabled; -#endif bool disable_dmcu; bool disable_psr; bool force_abm_enable; @@ -663,22 +683,18 @@ struct dc_debug_options { bool hdmi20_disable; bool skip_detection_link_training; uint32_t edid_read_retry_times; - bool remove_disconnect_edp; unsigned int force_odm_combine; //bit vector based on otg inst -#if defined(CONFIG_DRM_AMD_DC_DCN) + unsigned int seamless_boot_odm_combine; unsigned int force_odm_combine_4to1; //bit vector based on otg inst bool disable_z9_mpc; -#endif unsigned int force_fclk_khz; bool enable_tri_buf; bool dmub_offload_enabled; bool dmcub_emulation; -#if defined(CONFIG_DRM_AMD_DC_DCN) bool disable_idle_power_optimizations; unsigned int mall_size_override; unsigned int mall_additional_timer_percent; bool mall_error_as_fatal; -#endif bool dmub_command_table; /* for testing only */ struct dc_bw_validation_profile bw_val_profile; bool disable_fec; @@ -687,9 +703,7 @@ struct dc_debug_options { * watermarks are not affected. */ unsigned int force_min_dcfclk_mhz; -#if defined(CONFIG_DRM_AMD_DC_DCN) int dwb_fi_phase; -#endif bool disable_timing_sync; bool cm_in_bypass; int force_clock_mode;/*every mode change.*/ @@ -714,6 +728,7 @@ struct dc_debug_options { /* Enable dmub aux for legacy ddc */ bool enable_dmub_aux_for_legacy_ddc; + bool disable_fams; bool optimize_edp_link_rate; /* eDP ILR */ /* FEC/PSR1 sequence enable delay in 100us */ uint8_t fec_enable_delay_in100us; @@ -721,16 +736,25 @@ struct dc_debug_options { enum det_size crb_alloc_policy; int crb_alloc_policy_min_disp_count; bool disable_z10; -#if defined(CONFIG_DRM_AMD_DC_DCN) bool enable_z9_disable_interface; bool enable_sw_cntl_psr; union dpia_debug_options dpia_debug; -#endif - bool apply_vendor_specific_lttpr_wa; + bool disable_fixed_vs_aux_timeout_wa; + bool force_disable_subvp; + bool force_subvp_mclk_switch; + bool force_usr_allow; + /* uses value at boot and disables switch */ + bool disable_dtb_ref_clk_switch; + uint32_t fixed_vs_aux_delay_config_wa; bool extended_blank_optimization; union aux_wake_wa_options aux_wake_wa; - bool ignore_dpref_ss; + uint32_t mst_start_top_delay; uint8_t psr_power_use_phy_fsm; + enum dml_hostvm_override_opts dml_hostvm_override; + bool use_legacy_soc_bb_mechanism; + bool exit_idle_opt_for_cursor_updates; + bool enable_single_display_2to1_odm_policy; + bool enable_dp_dig_pixel_rate_div_policy; }; struct gpu_info_soc_bounding_box_v1_0; @@ -759,11 +783,9 @@ struct dc { /* Inputs into BW and WM calculations. */ struct bw_calcs_dceip *bw_dceip; struct bw_calcs_vbios *bw_vbios; -#ifdef CONFIG_DRM_AMD_DC_DCN struct dcn_soc_bounding_box *dcn_soc; struct dcn_ip_params *dcn_ip; struct display_mode_lib dml; -#endif /* HW functions */ struct hw_sequencer_funcs hwss; @@ -772,12 +794,8 @@ struct dc { /* Require to optimize clocks and bandwidth for added/removed planes */ bool optimized_required; bool wm_optimized_required; -#if defined(CONFIG_DRM_AMD_DC_DCN) bool idle_optimizations_allowed; -#endif -#if defined(CONFIG_DRM_AMD_DC_DCN) bool enable_c20_dtm_b0; -#endif /* Require to maintain clocks and bandwidth for UEFI enabled HW */ @@ -789,6 +807,9 @@ struct dc { const char *build_id; struct vm_helper *vm_helper; + + uint32_t *dcn_reg_offsets; + uint32_t *nbio_reg_offsets; }; enum frame_buffer_mode { @@ -827,9 +848,16 @@ struct dc_init_data { uint64_t log_mask; struct dpcd_vendor_signature vendor_signature; -#if defined(CONFIG_DRM_AMD_DC_DCN) bool force_smu_not_present; -#endif + /* + * IP offset for run time initializaion of register addresses + * + * DCN3.5+ will fail dc_create() if these fields are null for them. They are + * applicable starting with DCN32/321 and are not used for ASICs upstreamed + * before them. + */ + uint32_t *dcn_reg_offsets; + uint32_t *nbio_reg_offsets; }; struct dc_callback_init { @@ -1022,15 +1050,14 @@ struct dc_plane_state { struct dc_transfer_func *in_shaper_func; struct dc_transfer_func *blend_tf; -#if defined(CONFIG_DRM_AMD_DC_DCN) struct dc_transfer_func *gamcor_tf; -#endif enum surface_pixel_format format; enum dc_rotation_angle rotation; enum plane_stereo_format stereo_format; bool is_tiling_rotated; bool per_pixel_alpha; + bool pre_multiplied_alpha; bool global_alpha; int global_alpha_value; bool visible; @@ -1049,6 +1076,8 @@ struct dc_plane_state { /* HACK: Workaround for forcing full reprogramming under some conditions */ bool force_full_update; + bool is_phantom; // TODO: Change mall_stream_config into mall_plane_config instead + /* private to dc_surface.c */ enum dc_irq_source irq_source; struct kref refcount; @@ -1065,6 +1094,7 @@ struct dc_plane_info { bool horizontal_mirror; bool visible; bool per_pixel_alpha; + bool pre_multiplied_alpha; bool global_alpha; int global_alpha_value; bool input_csc_enabled; @@ -1121,18 +1151,6 @@ struct dc_transfer_func *dc_create_transfer_func(void); struct dc_3dlut *dc_create_3dlut_func(void); void dc_3dlut_func_release(struct dc_3dlut *lut); void dc_3dlut_func_retain(struct dc_3dlut *lut); -/* - * This structure holds a surface address. There could be multiple addresses - * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such - * as frame durations and DCC format can also be set. - */ -struct dc_flip_addrs { - struct dc_plane_address address; - unsigned int flip_timestamp_in_us; - bool flip_immediate; - /* TODO: add flip duration for FreeSync */ - bool triplebuffer_flips; -}; void dc_post_update_surfaces_to_stream( struct dc *dc); @@ -1173,13 +1191,11 @@ void dc_resource_state_construct( const struct dc *dc, struct dc_state *dst_ctx); -#if defined(CONFIG_DRM_AMD_DC_DCN) bool dc_acquire_release_mpc_3dlut( struct dc *dc, bool acquire, struct dc_stream_state *stream, struct dc_3dlut **lut, struct dc_transfer_func **shaper); -#endif void dc_resource_state_copy_construct( const struct dc_state *src_ctx, @@ -1249,6 +1265,7 @@ struct dpcd_caps { bool panel_mode_edp; bool dpcd_display_control_capable; bool ext_receiver_cap_field_present; + bool set_power_state_capable_edp; bool dynamic_backlight_capable_edp; union dpcd_fec_capability fec_cap; struct dpcd_dsc_capabilities dsc_caps; @@ -1310,10 +1327,8 @@ struct hdcp_caps { #include "dc_link.h" -#if defined(CONFIG_DRM_AMD_DC_DCN) uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); -#endif /******************************************************************************* * Sink Interfaces - A sink corresponds to a display output device ******************************************************************************/ @@ -1437,23 +1452,16 @@ bool dc_is_dmcu_initialized(struct dc *dc); enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); -#if defined(CONFIG_DRM_AMD_DC_DCN) bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane, struct dc_cursor_attributes *cursor_attr); void dc_allow_idle_optimizations(struct dc *dc, bool allow); -/* - * blank all streams, and set min and max memory clock to - * lowest and highest DPM level, respectively - */ +/* set min and max memory clock to lowest and highest DPM level, respectively */ void dc_unlock_memory_clock_frequency(struct dc *dc); -/* - * set min memory clock to the min required for current mode, - * max to maxDPM, and unblank streams - */ +/* set min memory clock to the min required for current mode, max to maxDPM */ void dc_lock_memory_clock_frequency(struct dc *dc); /* set soft max for memclk, to be used for AC/DC switching clock limitations */ @@ -1462,13 +1470,12 @@ void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable); /* cleanup on driver unload */ void dc_hardware_release(struct dc *dc); -#endif +/* disables fw based mclk switch */ +void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc); bool dc_set_psr_allow_active(struct dc *dc, bool enable); -#if defined(CONFIG_DRM_AMD_DC_DCN) void dc_z10_restore(const struct dc *dc); void dc_z10_save_init(struct dc *dc); -#endif bool dc_is_dmub_outbox_supported(struct dc *dc); bool dc_enable_dmub_notifications(struct dc *dc); |