diff options
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_object.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 36 | 
1 files changed, 22 insertions, 14 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index 940752488330..2c82b1d5a0d7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -472,7 +472,7 @@ static bool amdgpu_bo_validate_size(struct amdgpu_device *adev,  fail:  	DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size, -		  man->size << PAGE_SHIFT); +		  man->size);  	return false;  } @@ -567,6 +567,7 @@ int amdgpu_bo_create(struct amdgpu_device *adev,  		bp->domain;  	bo->allowed_domains = bo->preferred_domains;  	if (bp->type != ttm_bo_type_kernel && +	    !(bp->flags & AMDGPU_GEM_CREATE_DISCARDABLE) &&  	    bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)  		bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; @@ -612,9 +613,8 @@ int amdgpu_bo_create(struct amdgpu_device *adev,  		if (unlikely(r))  			goto fail_unreserve; -		amdgpu_bo_fence(bo, fence, false); -		dma_fence_put(bo->tbo.moving); -		bo->tbo.moving = dma_fence_get(fence); +		dma_resv_add_fence(bo->tbo.base.resv, fence, +				   DMA_RESV_USAGE_KERNEL);  		dma_fence_put(fence);  	}  	if (!bp->resv) @@ -761,6 +761,11 @@ int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr)  	if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)  		return -EPERM; +	r = dma_resv_wait_timeout(bo->tbo.base.resv, DMA_RESV_USAGE_KERNEL, +				  false, MAX_SCHEDULE_TIMEOUT); +	if (r < 0) +		return r; +  	kptr = amdgpu_bo_kptr(bo);  	if (kptr) {  		if (ptr) @@ -768,11 +773,6 @@ int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr)  		return 0;  	} -	r = dma_resv_wait_timeout(bo->tbo.base.resv, false, false, -				  MAX_SCHEDULE_TIMEOUT); -	if (r < 0) -		return r; -  	r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.resource->num_pages, &bo->kmap);  	if (r)  		return r; @@ -1019,7 +1019,9 @@ static const char *amdgpu_vram_names[] = {  	"DDR3",  	"DDR4",  	"GDDR6", -	"DDR5" +	"DDR5", +	"LPDDR4", +	"LPDDR5"  };  /** @@ -1390,11 +1392,17 @@ void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,  		     bool shared)  {  	struct dma_resv *resv = bo->tbo.base.resv; +	int r; -	if (shared) -		dma_resv_add_shared_fence(resv, fence); -	else -		dma_resv_add_excl_fence(resv, fence); +	r = dma_resv_reserve_fences(resv, 1); +	if (r) { +		/* As last resort on OOM we block for the fence */ +		dma_fence_wait(fence, false); +		return; +	} + +	dma_resv_add_fence(resv, fence, shared ? DMA_RESV_USAGE_READ : +			   DMA_RESV_USAGE_WRITE);  }  /**  |