diff options
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 22 | 
1 files changed, 11 insertions, 11 deletions
| diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h index e11051271f71..0bc837dab578 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h @@ -52,7 +52,6 @@ enum amdgpu_mes_priority_level {  #define AMDGPU_MES_PROC_CTX_SIZE 0x1000 /* one page area */  #define AMDGPU_MES_GANG_CTX_SIZE 0x1000 /* one page area */ -#define AMDGPU_MES_LOG_BUFFER_SIZE 0x4000 /* Maximu log buffer size for MES */  struct amdgpu_mes_funcs; @@ -83,8 +82,8 @@ struct amdgpu_mes {  	uint64_t                        default_process_quantum;  	uint64_t                        default_gang_quantum; -	struct amdgpu_ring              ring; -	spinlock_t                      ring_lock; +	struct amdgpu_ring              ring[AMDGPU_MAX_MES_PIPES]; +	spinlock_t                      ring_lock[AMDGPU_MAX_MES_PIPES];  	const struct firmware           *fw[AMDGPU_MAX_MES_PIPES]; @@ -113,12 +112,12 @@ struct amdgpu_mes {  	uint32_t                        gfx_hqd_mask[AMDGPU_MES_MAX_GFX_PIPES];  	uint32_t                        sdma_hqd_mask[AMDGPU_MES_MAX_SDMA_PIPES];  	uint32_t                        aggregated_doorbells[AMDGPU_MES_PRIORITY_NUM_LEVELS]; -	uint32_t                        sch_ctx_offs; -	uint64_t			sch_ctx_gpu_addr; -	uint64_t			*sch_ctx_ptr; -	uint32_t			query_status_fence_offs; -	uint64_t			query_status_fence_gpu_addr; -	uint64_t			*query_status_fence_ptr; +	uint32_t                        sch_ctx_offs[AMDGPU_MAX_MES_PIPES]; +	uint64_t			sch_ctx_gpu_addr[AMDGPU_MAX_MES_PIPES]; +	uint64_t			*sch_ctx_ptr[AMDGPU_MAX_MES_PIPES]; +	uint32_t			query_status_fence_offs[AMDGPU_MAX_MES_PIPES]; +	uint64_t			query_status_fence_gpu_addr[AMDGPU_MAX_MES_PIPES]; +	uint64_t			*query_status_fence_ptr[AMDGPU_MAX_MES_PIPES];  	uint32_t                        read_val_offs;  	uint64_t			read_val_gpu_addr;  	uint32_t			*read_val_ptr; @@ -135,8 +134,9 @@ struct amdgpu_mes {  	unsigned long			*doorbell_bitmap;  	/* MES event log buffer */ -	struct amdgpu_bo		*event_log_gpu_obj; -	uint64_t                        event_log_gpu_addr; +	uint32_t			event_log_size; +	struct amdgpu_bo	*event_log_gpu_obj; +	uint64_t			event_log_gpu_addr;  	void				*event_log_cpu_addr;  	/* ip specific functions */ |