diff options
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 40 | 
1 files changed, 30 insertions, 10 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c index 82e27bd4f038..f0f00466b59f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c @@ -1104,6 +1104,11 @@ int amdgpu_mes_ctx_alloc_meta_data(struct amdgpu_device *adev,  			    &ctx_data->meta_data_obj,  			    &ctx_data->meta_data_mc_addr,  			    &ctx_data->meta_data_ptr); +	if (r) { +		dev_warn(adev->dev, "(%d) create CTX bo failed\n", r); +		return r; +	} +  	if (!ctx_data->meta_data_obj)  		return -ENOMEM; @@ -1328,12 +1333,9 @@ int amdgpu_mes_self_test(struct amdgpu_device *adev)  	struct amdgpu_mes_ctx_data ctx_data = {0};  	struct amdgpu_ring *added_rings[AMDGPU_MES_CTX_MAX_RINGS] = { NULL };  	int gang_ids[3] = {0}; -	int queue_types[][2] = { { AMDGPU_RING_TYPE_GFX, -				   AMDGPU_MES_CTX_MAX_GFX_RINGS}, -				 { AMDGPU_RING_TYPE_COMPUTE, -				   AMDGPU_MES_CTX_MAX_COMPUTE_RINGS}, -				 { AMDGPU_RING_TYPE_SDMA, -				   AMDGPU_MES_CTX_MAX_SDMA_RINGS } }; +	int queue_types[][2] = { { AMDGPU_RING_TYPE_GFX, 1 }, +				 { AMDGPU_RING_TYPE_COMPUTE, 1 }, +				 { AMDGPU_RING_TYPE_SDMA, 1} };  	int i, r, pasid, k = 0;  	pasid = amdgpu_pasid_alloc(16); @@ -1432,13 +1434,31 @@ int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe)  	struct amdgpu_firmware_info *info;  	char ucode_prefix[30];  	char fw_name[40]; +	bool need_retry = false;  	int r; -	amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); -	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes%s.bin", -		ucode_prefix, -		pipe == AMDGPU_MES_SCHED_PIPE ? "" : "1"); +	amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, +				       sizeof(ucode_prefix)); +	if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(11, 0, 0)) { +		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes%s.bin", +			 ucode_prefix, +			 pipe == AMDGPU_MES_SCHED_PIPE ? "_2" : "1"); +		need_retry = true; +	} else { +		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes%s.bin", +			 ucode_prefix, +			 pipe == AMDGPU_MES_SCHED_PIPE ? "" : "1"); +	} +  	r = amdgpu_ucode_request(adev, &adev->mes.fw[pipe], fw_name); +	if (r && need_retry && pipe == AMDGPU_MES_SCHED_PIPE) { +		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes.bin", +			 ucode_prefix); +		DRM_INFO("try to fall back to %s\n", fw_name); +		r = amdgpu_ucode_request(adev, &adev->mes.fw[pipe], +					 fw_name); +	} +  	if (r)  		goto out;  |