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path: root/drivers/clk/renesas/rzg2l-cpg.c
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Diffstat (limited to 'drivers/clk/renesas/rzg2l-cpg.c')
-rw-r--r--drivers/clk/renesas/rzg2l-cpg.c71
1 files changed, 37 insertions, 34 deletions
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index 04b78064d4e0..88bf39e8c79c 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -339,8 +339,7 @@ static const struct clk_ops rzg3s_div_clk_ops = {
};
static struct clk * __init
-rzg3s_cpg_div_clk_register(const struct cpg_core_clk *core, struct clk **clks,
- void __iomem *base, struct rzg2l_cpg_priv *priv)
+rzg3s_cpg_div_clk_register(const struct cpg_core_clk *core, struct rzg2l_cpg_priv *priv)
{
struct div_hw_data *div_hw_data;
struct clk_init_data init = {};
@@ -351,7 +350,7 @@ rzg3s_cpg_div_clk_register(const struct cpg_core_clk *core, struct clk **clks,
u32 max = 0;
int ret;
- parent = clks[core->parent & 0xffff];
+ parent = priv->clks[core->parent];
if (IS_ERR(parent))
return ERR_CAST(parent);
@@ -400,16 +399,15 @@ rzg3s_cpg_div_clk_register(const struct cpg_core_clk *core, struct clk **clks,
static struct clk * __init
rzg2l_cpg_div_clk_register(const struct cpg_core_clk *core,
- struct clk **clks,
- void __iomem *base,
struct rzg2l_cpg_priv *priv)
{
+ void __iomem *base = priv->base;
struct device *dev = priv->dev;
const struct clk *parent;
const char *parent_name;
struct clk_hw *clk_hw;
- parent = clks[core->parent & 0xffff];
+ parent = priv->clks[core->parent];
if (IS_ERR(parent))
return ERR_CAST(parent);
@@ -440,7 +438,6 @@ rzg2l_cpg_div_clk_register(const struct cpg_core_clk *core,
static struct clk * __init
rzg2l_cpg_mux_clk_register(const struct cpg_core_clk *core,
- void __iomem *base,
struct rzg2l_cpg_priv *priv)
{
const struct clk_hw *clk_hw;
@@ -448,7 +445,7 @@ rzg2l_cpg_mux_clk_register(const struct cpg_core_clk *core,
clk_hw = devm_clk_hw_register_mux(priv->dev, core->name,
core->parent_names, core->num_parents,
core->flag,
- base + GET_REG_OFFSET(core->conf),
+ priv->base + GET_REG_OFFSET(core->conf),
GET_SHIFT(core->conf),
GET_WIDTH(core->conf),
core->mux_flags, &priv->rmw_lock);
@@ -508,7 +505,6 @@ static const struct clk_ops rzg2l_cpg_sd_clk_mux_ops = {
static struct clk * __init
rzg2l_cpg_sd_mux_clk_register(const struct cpg_core_clk *core,
- void __iomem *base,
struct rzg2l_cpg_priv *priv)
{
struct sd_mux_hw_data *sd_mux_hw_data;
@@ -652,7 +648,6 @@ static const struct clk_ops rzg2l_cpg_dsi_div_ops = {
static struct clk * __init
rzg2l_cpg_dsi_div_clk_register(const struct cpg_core_clk *core,
- struct clk **clks,
struct rzg2l_cpg_priv *priv)
{
struct dsi_div_hw_data *clk_hw_data;
@@ -662,7 +657,7 @@ rzg2l_cpg_dsi_div_clk_register(const struct cpg_core_clk *core,
struct clk_hw *clk_hw;
int ret;
- parent = clks[core->parent & 0xffff];
+ parent = priv->clks[core->parent];
if (IS_ERR(parent))
return ERR_CAST(parent);
@@ -900,7 +895,6 @@ static const struct clk_ops rzg2l_cpg_sipll5_ops = {
static struct clk * __init
rzg2l_cpg_sipll5_register(const struct cpg_core_clk *core,
- struct clk **clks,
struct rzg2l_cpg_priv *priv)
{
const struct clk *parent;
@@ -910,7 +904,7 @@ rzg2l_cpg_sipll5_register(const struct cpg_core_clk *core,
struct clk_hw *clk_hw;
int ret;
- parent = clks[core->parent & 0xffff];
+ parent = priv->clks[core->parent];
if (IS_ERR(parent))
return ERR_CAST(parent);
@@ -1013,8 +1007,6 @@ static const struct clk_ops rzg3s_cpg_pll_ops = {
static struct clk * __init
rzg2l_cpg_pll_clk_register(const struct cpg_core_clk *core,
- struct clk **clks,
- void __iomem *base,
struct rzg2l_cpg_priv *priv,
const struct clk_ops *ops)
{
@@ -1023,8 +1015,9 @@ rzg2l_cpg_pll_clk_register(const struct cpg_core_clk *core,
struct clk_init_data init;
const char *parent_name;
struct pll_clk *pll_clk;
+ int ret;
- parent = clks[core->parent & 0xffff];
+ parent = priv->clks[core->parent];
if (IS_ERR(parent))
return ERR_CAST(parent);
@@ -1041,11 +1034,15 @@ rzg2l_cpg_pll_clk_register(const struct cpg_core_clk *core,
pll_clk->hw.init = &init;
pll_clk->conf = core->conf;
- pll_clk->base = base;
+ pll_clk->base = priv->base;
pll_clk->priv = priv;
pll_clk->type = core->type;
- return clk_register(NULL, &pll_clk->hw);
+ ret = devm_clk_hw_register(dev, &pll_clk->hw);
+ if (ret)
+ return ERR_PTR(ret);
+
+ return pll_clk->hw.clk;
}
static struct clk
@@ -1102,6 +1099,7 @@ rzg2l_cpg_register_core_clk(const struct cpg_core_clk *core,
struct device *dev = priv->dev;
unsigned int id = core->id, div = core->div;
const char *parent_name;
+ struct clk_hw *clk_hw;
WARN_DEBUG(id >= priv->num_core_clks);
WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
@@ -1124,39 +1122,40 @@ rzg2l_cpg_register_core_clk(const struct cpg_core_clk *core,
}
parent_name = __clk_get_name(parent);
- clk = clk_register_fixed_factor(NULL, core->name,
- parent_name, CLK_SET_RATE_PARENT,
- core->mult, div);
+ clk_hw = devm_clk_hw_register_fixed_factor(dev, core->name, parent_name,
+ CLK_SET_RATE_PARENT,
+ core->mult, div);
+ if (IS_ERR(clk_hw))
+ clk = ERR_CAST(clk_hw);
+ else
+ clk = clk_hw->clk;
break;
case CLK_TYPE_SAM_PLL:
- clk = rzg2l_cpg_pll_clk_register(core, priv->clks, priv->base, priv,
- &rzg2l_cpg_pll_ops);
+ clk = rzg2l_cpg_pll_clk_register(core, priv, &rzg2l_cpg_pll_ops);
break;
case CLK_TYPE_G3S_PLL:
- clk = rzg2l_cpg_pll_clk_register(core, priv->clks, priv->base, priv,
- &rzg3s_cpg_pll_ops);
+ clk = rzg2l_cpg_pll_clk_register(core, priv, &rzg3s_cpg_pll_ops);
break;
case CLK_TYPE_SIPLL5:
- clk = rzg2l_cpg_sipll5_register(core, priv->clks, priv);
+ clk = rzg2l_cpg_sipll5_register(core, priv);
break;
case CLK_TYPE_DIV:
- clk = rzg2l_cpg_div_clk_register(core, priv->clks,
- priv->base, priv);
+ clk = rzg2l_cpg_div_clk_register(core, priv);
break;
case CLK_TYPE_G3S_DIV:
- clk = rzg3s_cpg_div_clk_register(core, priv->clks, priv->base, priv);
+ clk = rzg3s_cpg_div_clk_register(core, priv);
break;
case CLK_TYPE_MUX:
- clk = rzg2l_cpg_mux_clk_register(core, priv->base, priv);
+ clk = rzg2l_cpg_mux_clk_register(core, priv);
break;
case CLK_TYPE_SD_MUX:
- clk = rzg2l_cpg_sd_mux_clk_register(core, priv->base, priv);
+ clk = rzg2l_cpg_sd_mux_clk_register(core, priv);
break;
case CLK_TYPE_PLL5_4_MUX:
clk = rzg2l_cpg_pll5_4_mux_clk_register(core, priv);
break;
case CLK_TYPE_DSI_DIV:
- clk = rzg2l_cpg_dsi_div_clk_register(core, priv->clks, priv);
+ clk = rzg2l_cpg_dsi_div_clk_register(core, priv);
break;
default:
goto fail;
@@ -1337,6 +1336,7 @@ rzg2l_cpg_register_mod_clk(const struct rzg2l_mod_clk *mod,
struct clk *parent, *clk;
const char *parent_name;
unsigned int i;
+ int ret;
WARN_DEBUG(id < priv->num_core_clks);
WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks);
@@ -1380,10 +1380,13 @@ rzg2l_cpg_register_mod_clk(const struct rzg2l_mod_clk *mod,
clock->priv = priv;
clock->hw.init = &init;
- clk = clk_register(NULL, &clock->hw);
- if (IS_ERR(clk))
+ ret = devm_clk_hw_register(dev, &clock->hw);
+ if (ret) {
+ clk = ERR_PTR(ret);
goto fail;
+ }
+ clk = clock->hw.clk;
dev_dbg(dev, "Module clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
priv->clks[id] = clk;
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