diff options
Diffstat (limited to 'drivers/clk/imx/clk-composite-7ulp.c')
| -rw-r--r-- | drivers/clk/imx/clk-composite-7ulp.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/clk/imx/clk-composite-7ulp.c b/drivers/clk/imx/clk-composite-7ulp.c index 9ce8c630ee32..89106de16a3f 100644 --- a/drivers/clk/imx/clk-composite-7ulp.c +++ b/drivers/clk/imx/clk-composite-7ulp.c @@ -29,6 +29,7 @@ static int pcc_gate_enable(struct clk_hw *hw) { struct clk_gate *gate = to_clk_gate(hw); + unsigned long flags; u32 val; int ret; @@ -36,6 +37,7 @@ static int pcc_gate_enable(struct clk_hw *hw) if (ret) return ret; + spin_lock_irqsave(gate->lock, flags); /* * release the sw reset for peripherals associated with * with this pcc clock. @@ -44,6 +46,8 @@ static int pcc_gate_enable(struct clk_hw *hw) val |= SW_RST; writel(val, gate->reg); + spin_unlock_irqrestore(gate->lock, flags); + return 0; } @@ -84,6 +88,8 @@ static struct clk_hw *imx_ulp_clk_hw_composite(const char *name, mux->reg = reg; mux->shift = PCG_PCS_SHIFT; mux->mask = PCG_PCS_MASK; + if (has_swrst) + mux->lock = &imx_ccm_lock; } if (rate_present) { @@ -101,6 +107,8 @@ static struct clk_hw *imx_ulp_clk_hw_composite(const char *name, fd->nwidth = PCG_PCD_WIDTH; fd->nmask = PCG_PCD_MASK; fd->flags = CLK_FRAC_DIVIDER_ZERO_BASED; + if (has_swrst) + fd->lock = &imx_ccm_lock; } if (gate_present) { @@ -113,6 +121,8 @@ static struct clk_hw *imx_ulp_clk_hw_composite(const char *name, gate_hw = &gate->hw; gate->reg = reg; gate->bit_idx = PCG_CGC_SHIFT; + if (has_swrst) + gate->lock = &imx_ccm_lock; /* * make sure clock is gated during clock tree initialization, * the HW ONLY allow clock parent/rate changed with clock gated, |