diff options
Diffstat (limited to 'arch')
367 files changed, 34185 insertions, 13980 deletions
diff --git a/arch/arm/boot/dts/am335x-nano.dts b/arch/arm/boot/dts/am335x-nano.dts index b6f2567bd65a..c447aebd8d86 100644 --- a/arch/arm/boot/dts/am335x-nano.dts +++ b/arch/arm/boot/dts/am335x-nano.dts @@ -120,8 +120,8 @@ uart3_pins: uart3_pins { pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_INPUT_PULLUP, MUX_MODE6) /* lcd_data10.uart3_ctsn */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE6) /* lcd_data11.uart3_rtsn */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_INPUT_PULLUP, MUX_MODE7) /* lcd_data10.gpio2[16] */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE7) /* lcd_data11.gpio2[17] */ AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE1) /* spi0_cs1.uart3_rxd */ AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT, MUX_MODE1) /* ecap0_in_pwm0_out.uart3_txd */ >; @@ -129,8 +129,8 @@ uart4_pins: uart4_pins { pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_INPUT_PULLUP, MUX_MODE6) /* lcd_data12.uart4_ctsn */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE6) /* lcd_data13.uart4_rtsn */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_INPUT_PULLUP, MUX_MODE7) /* lcd_data12.gpio0[8] */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE7) /* lcd_data13.gpio0[9] */ AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT, MUX_MODE1) /* uart0_ctsn.uart4_rxd */ AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT, MUX_MODE1) /* uart0_rtsn.uart4_txd */ >; @@ -187,12 +187,22 @@ &uart3 { pinctrl-names = "default"; pinctrl-0 = <&uart3_pins>; + rts-gpio = <&gpio2 17 GPIO_ACTIVE_HIGH>; + rs485-rts-active-high; + rs485-rx-during-tx; + rs485-rts-delay = <1 1>; + linux,rs485-enabled-at-boot-time; status = "okay"; }; &uart4 { pinctrl-names = "default"; pinctrl-0 = <&uart4_pins>; + rts-gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>; + rs485-rts-active-high; + rs485-rx-during-tx; + rs485-rts-delay = <1 1>; + linux,rs485-enabled-at-boot-time; status = "okay"; }; @@ -220,6 +230,11 @@ reg = <0x24>; }; + temperature-sensor@48 { + compatible = "lm75"; + reg = <0x48>; + }; + eeprom@53 { compatible = "microchip,24c02", "atmel,24c02"; reg = <0x53>; @@ -403,8 +418,13 @@ pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; bus-width = <4>; - cd-gpios = <&gpio3 8 0>; - wp-gpios = <&gpio3 18 0>; + cd-debounce-delay-ms = <5>; + cd-gpios = <&gpio3 8 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; +}; + +&usb0 { + dr_mode = "host"; }; #include "tps65217.dtsi" diff --git a/arch/arm/boot/dts/am3874-iceboard.dts b/arch/arm/boot/dts/am3874-iceboard.dts index d039af879367..791478e81c5a 100644 --- a/arch/arm/boot/dts/am3874-iceboard.dts +++ b/arch/arm/boot/dts/am3874-iceboard.dts @@ -106,7 +106,7 @@ * "i2c-mux-idle-disconnect" is important. */ - pca9548@70 { + i2c-mux@70 { compatible = "nxp,pca9548"; reg = <0x70>; #address-cells = <1>; @@ -256,7 +256,7 @@ }; &i2c2 { - pca9548@71 { + i2c-mux@71 { compatible = "nxp,pca9548"; reg = <0x71>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/at91-gatwick.dts b/arch/arm/boot/dts/at91-gatwick.dts index 2c718cf84d7b..551300fd7746 100644 --- a/arch/arm/boot/dts/at91-gatwick.dts +++ b/arch/arm/boot/dts/at91-gatwick.dts @@ -31,37 +31,37 @@ leds { compatible = "gpio-leds"; - ethernet { + led-ethernet { label = "gatwick:yellow:ethernet"; gpios = <&pioA 10 GPIO_ACTIVE_LOW>; default-state = "off"; }; - wifi { + led-wifi { label = "gatwick:green:wifi"; gpios = <&pioA 28 GPIO_ACTIVE_LOW>; default-state = "off"; }; - ble { + led-ble { label = "gatwick:blue:ble"; gpios = <&pioA 22 GPIO_ACTIVE_LOW>; default-state = "off"; }; - lora { + led-lora { label = "gatwick:orange:lora"; gpios = <&pioA 26 GPIO_ACTIVE_LOW>; default-state = "off"; }; - blank { + led-blank { label = "gatwick:green:blank"; gpios = <&pioA 24 GPIO_ACTIVE_LOW>; default-state = "off"; }; - user { + led-user { label = "gatwick:yellow:user"; gpios = <&pioA 12 GPIO_ACTIVE_LOW>; default-state = "off"; diff --git a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts index 0dc6ca377b0c..52ddd0571f1c 100644 --- a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts +++ b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts @@ -498,17 +498,17 @@ pinctrl-0 = <&pinctrl_led_gpio_default>; status = "okay"; /* Conflict with pwm0. */ - red { + led-red { label = "red"; gpios = <&pioA PIN_PA10 GPIO_ACTIVE_HIGH>; }; - green { + led-green { label = "green"; gpios = <&pioA PIN_PB1 GPIO_ACTIVE_HIGH>; }; - blue { + led-blue { label = "blue"; gpios = <&pioA PIN_PA31 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; diff --git a/arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts b/arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts index b665ddc6b0de..e055b9e2fe34 100644 --- a/arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts +++ b/arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts @@ -46,17 +46,17 @@ pinctrl-0 = <&pinctrl_led_gpio_default>; status = "okay"; - red { + led-red { label = "red"; gpios = <&pioA PIN_PA6 GPIO_ACTIVE_HIGH>; }; - green { + led-green { label = "green"; gpios = <&pioA PIN_PA7 GPIO_ACTIVE_HIGH>; }; - blue { + led-blue { label = "blue"; gpios = <&pioA PIN_PA8 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; diff --git a/arch/arm/boot/dts/at91-sama5d2_icp.dts b/arch/arm/boot/dts/at91-sama5d2_icp.dts index dd1dec9d4e07..1346b8f2b259 100644 --- a/arch/arm/boot/dts/at91-sama5d2_icp.dts +++ b/arch/arm/boot/dts/at91-sama5d2_icp.dts @@ -62,17 +62,17 @@ pinctrl-0 = <&pinctrl_led_gpio_default>; status = "okay"; /* conflict with pwm0 */ - red { + led-red { label = "red"; gpios = <&pioA PIN_PB0 GPIO_ACTIVE_HIGH>; }; - green { + led-green { label = "green"; gpios = <&pioA PIN_PB1 GPIO_ACTIVE_HIGH>; }; - blue { + led-blue { label = "blue"; gpios = <&pioA PIN_PA31 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; diff --git a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts index 76a711b167b0..bf1c9ca72a9f 100644 --- a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts +++ b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts @@ -416,17 +416,17 @@ pinctrl-0 = <&pinctrl_led_gpio_default>; status = "okay"; - red { + led-red { label = "red"; gpios = <&pioA PIN_PB10 GPIO_ACTIVE_HIGH>; }; - green { + led-green { label = "green"; gpios = <&pioA PIN_PB8 GPIO_ACTIVE_HIGH>; }; - blue { + led-blue { label = "blue"; gpios = <&pioA PIN_PB6 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts index 85949c24b687..2d53c47d7cc8 100644 --- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts @@ -725,18 +725,18 @@ pinctrl-0 = <&pinctrl_led_gpio_default>; status = "okay"; /* conflict with pwm0 */ - red { + led-red { label = "red"; gpios = <&pioA PIN_PB6 GPIO_ACTIVE_LOW>; }; - green { + led-green { label = "green"; gpios = <&pioA PIN_PB5 GPIO_ACTIVE_LOW>; }; - blue { + led-blue { label = "blue"; gpios = <&pioA PIN_PB0 GPIO_ACTIVE_LOW>; linux,default-trigger = "heartbeat"; diff --git a/arch/arm/boot/dts/at91-sama5d3_xplained.dts b/arch/arm/boot/dts/at91-sama5d3_xplained.dts index 1f42a6a981bf..820033727088 100644 --- a/arch/arm/boot/dts/at91-sama5d3_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d3_xplained.dts @@ -392,13 +392,13 @@ pinctrl-0 = <&pinctrl_gpio_leds>; status = "okay"; - d2 { + led-d2 { label = "d2"; gpios = <&pioE 23 GPIO_ACTIVE_LOW>; /* PE23, conflicts with A23, CTS2 */ linux,default-trigger = "heartbeat"; }; - d3 { + led-d3 { label = "d3"; /* Conflict with EBI CS0, USART2 CTS. */ gpios = <&pioE 24 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts b/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts index 4d7cee569ff2..8adf567f2f0f 100644 --- a/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts +++ b/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts @@ -115,19 +115,19 @@ compatible = "gpio-leds"; status = "okay"; - user1 { + led-user1 { label = "user1"; gpios = <&pioD 28 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; - user2 { + led-user2 { label = "user2"; gpios = <&pioD 29 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; - user3 { + led-user3 { label = "user3"; gpios = <&pioD 30 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; diff --git a/arch/arm/boot/dts/at91-sama5d4_xplained.dts b/arch/arm/boot/dts/at91-sama5d4_xplained.dts index f122f302f8e0..95d701d13fef 100644 --- a/arch/arm/boot/dts/at91-sama5d4_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d4_xplained.dts @@ -262,13 +262,13 @@ pinctrl-0 = <&pinctrl_gpio_leds>; status = "okay"; - d8 { + led-d8 { label = "d8"; gpios = <&pioD 30 GPIO_ACTIVE_HIGH>; default-state = "on"; }; - d10 { + led-d10 { label = "d10"; gpios = <&pioE 15 GPIO_ACTIVE_LOW>; linux,default-trigger = "heartbeat"; diff --git a/arch/arm/boot/dts/at91-sama5d4ek.dts b/arch/arm/boot/dts/at91-sama5d4ek.dts index fce4e93c6bee..20ac775059ca 100644 --- a/arch/arm/boot/dts/at91-sama5d4ek.dts +++ b/arch/arm/boot/dts/at91-sama5d4ek.dts @@ -287,18 +287,18 @@ compatible = "gpio-leds"; status = "okay"; - d8 { + led-d8 { label = "d8"; /* PE28, conflicts with usart4 rts pin */ gpios = <&pioE 28 GPIO_ACTIVE_LOW>; }; - d9 { + led-d9 { label = "d9"; gpios = <&pioE 9 GPIO_ACTIVE_HIGH>; }; - d10 { + led-d10 { label = "d10"; gpios = <&pioE 8 GPIO_ACTIVE_LOW>; linux,default-trigger = "heartbeat"; diff --git a/arch/arm/boot/dts/at91-tse850-3.dts b/arch/arm/boot/dts/at91-tse850-3.dts index 7e5c598e7e68..b99a4fb44a36 100644 --- a/arch/arm/boot/dts/at91-tse850-3.dts +++ b/arch/arm/boot/dts/at91-tse850-3.dts @@ -106,35 +106,35 @@ leds { compatible = "gpio-leds"; - ch1-red { + led-ch1-red { label = "ch-1:red"; gpios = <&pioA 23 GPIO_ACTIVE_LOW>; }; - ch1-green { + led-ch1-green { label = "ch-1:green"; gpios = <&pioA 22 GPIO_ACTIVE_LOW>; }; - ch2-red { + led-ch2-red { label = "ch-2:red"; gpios = <&pioA 21 GPIO_ACTIVE_LOW>; }; - ch2-green { + led-ch2-green { label = "ch-2:green"; gpios = <&pioA 20 GPIO_ACTIVE_LOW>; }; - data-red { + led-data-red { label = "data:red"; gpios = <&pioA 19 GPIO_ACTIVE_LOW>; }; - data-green { + led-data-green { label = "data:green"; gpios = <&pioA 18 GPIO_ACTIVE_LOW>; }; - alarm-red { + led-alarm-red { label = "alarm:red"; gpios = <&pioA 17 GPIO_ACTIVE_LOW>; }; - alarm-green { + led-alarm-green { label = "alarm:green"; gpios = <&pioA 16 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/dove-cm-a510.dtsi b/arch/arm/boot/dts/dove-cm-a510.dtsi index 9b9dfbe07be4..0af9e9fda7d3 100644 --- a/arch/arm/boot/dts/dove-cm-a510.dtsi +++ b/arch/arm/boot/dts/dove-cm-a510.dtsi @@ -101,7 +101,7 @@ pinctrl-0 = <&pmx_nand_gpo>; pinctrl-names = "default"; - system { + led-system { label = "cm-a510:system:green"; gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; default-state = "keep"; diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts index 2639b9fe0ab4..c0e8d6bc4083 100644 --- a/arch/arm/boot/dts/dove-cubox.dts +++ b/arch/arm/boot/dts/dove-cubox.dts @@ -21,7 +21,7 @@ pinctrl-0 = <&pmx_gpio_18>; pinctrl-names = "default"; - power { + led-power { label = "Power"; gpios = <&gpio0 18 1>; default-state = "keep"; diff --git a/arch/arm/boot/dts/dove-d2plug.dts b/arch/arm/boot/dts/dove-d2plug.dts index a0e8996c2ffd..79ee2b32409d 100644 --- a/arch/arm/boot/dts/dove-d2plug.dts +++ b/arch/arm/boot/dts/dove-d2plug.dts @@ -21,17 +21,17 @@ pinctrl-0 = <&pmx_gpio_0 &pmx_gpio_1 &pmx_gpio_2>; pinctrl-names = "default"; - wlan-ap { + led-wlan-ap { label = "wlan-ap"; gpios = <&gpio0 0 1>; }; - wlan-act { + led-wlan-act { label = "wlan-act"; gpios = <&gpio0 1 1>; }; - bluetooth-act { + led-bluetooth-act { label = "bt-act"; gpios = <&gpio0 2 1>; }; diff --git a/arch/arm/boot/dts/dove-d3plug.dts b/arch/arm/boot/dts/dove-d3plug.dts index 1e81d1b97055..5aa5d4a7d51d 100644 --- a/arch/arm/boot/dts/dove-d3plug.dts +++ b/arch/arm/boot/dts/dove-d3plug.dts @@ -21,17 +21,17 @@ pinctrl-0 = <&pmx_gpio_0 &pmx_gpio_1 &pmx_gpio_2>; pinctrl-names = "default"; - wlan-act { + led-wlan-act { label = "wlan-act"; gpios = <&gpio0 0 1>; }; - wlan-ap { + led-wlan-ap { label = "wlan-ap"; gpios = <&gpio0 1 1>; }; - status { + led-status { label = "status"; gpios = <&gpio0 2 1>; }; diff --git a/arch/arm/boot/dts/gemini-dlink-dns-313.dts b/arch/arm/boot/dts/gemini-dlink-dns-313.dts index eba1c94ed7f7..138c47e1ac1b 100644 --- a/arch/arm/boot/dts/gemini-dlink-dns-313.dts +++ b/arch/arm/boot/dts/gemini-dlink-dns-313.dts @@ -80,6 +80,15 @@ #cooling-cells = <2>; }; + /* + * This is the type B USB connector on the device, + * a GPIO-controlled USB VBUS detect + */ + usb1_phy: phy { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + #phy-cells = <0>; + vbus-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; + }; /* Global Mixed-Mode Technology G751 mounted on GPIO I2C */ i2c { @@ -164,6 +173,8 @@ compatible = "cortina,gemini-flash", "jedec-flash"; status = "okay"; reg = <0x30000000 0x00080000>; + #address-cells = <1>; + #size-cells = <1>; /* * This "RedBoot" is the Storlink derivative. @@ -300,5 +311,13 @@ ide@63000000 { status = "okay"; }; + + usb@69000000 { + status = "okay"; + dr_mode = "peripheral"; + usb-phy = <&usb1_phy>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_default_pins>; + }; }; }; diff --git a/arch/arm/boot/dts/gemini-wbd111.dts b/arch/arm/boot/dts/gemini-wbd111.dts index de3c4416b0fb..3c88c59ab481 100644 --- a/arch/arm/boot/dts/gemini-wbd111.dts +++ b/arch/arm/boot/dts/gemini-wbd111.dts @@ -87,33 +87,10 @@ /* 8MB of flash */ reg = <0x30000000 0x00800000>; - partition@0 { - label = "RedBoot"; - reg = <0x00000000 0x00020000>; - read-only; - }; - partition@20000 { - label = "kernel"; - reg = <0x00020000 0x00100000>; - }; - partition@120000 { - label = "rootfs"; - reg = <0x00120000 0x006a0000>; - }; - partition@7c0000 { - label = "VCTL"; - reg = <0x007c0000 0x00010000>; - read-only; - }; - partition@7d0000 { - label = "cfg"; - reg = <0x007d0000 0x00010000>; - read-only; - }; - partition@7e0000 { - label = "FIS"; - reg = <0x007e0000 0x00010000>; - read-only; + partitions { + compatible = "redboot-fis"; + /* Eraseblock at 0x7e0000 */ + fis-index-block = <0x3f>; }; }; diff --git a/arch/arm/boot/dts/gemini-wbd222.dts b/arch/arm/boot/dts/gemini-wbd222.dts index e5ceaadbcc1a..ff72bbc4db3e 100644 --- a/arch/arm/boot/dts/gemini-wbd222.dts +++ b/arch/arm/boot/dts/gemini-wbd222.dts @@ -91,33 +91,10 @@ /* 8MB of flash */ reg = <0x30000000 0x00800000>; - partition@0 { - label = "RedBoot"; - reg = <0x00000000 0x00020000>; - read-only; - }; - partition@20000 { - label = "kernel"; - reg = <0x00020000 0x00100000>; - }; - partition@120000 { - label = "rootfs"; - reg = <0x00120000 0x006a0000>; - }; - partition@7c0000 { - label = "VCTL"; - reg = <0x007c0000 0x00010000>; - read-only; - }; - partition@7d0000 { - label = "cfg"; - reg = <0x007d0000 0x00010000>; - read-only; - }; - partition@7e0000 { - label = "FIS"; - reg = <0x007e0000 0x00010000>; - read-only; + partitions { + compatible = "redboot-fis"; + /* Eraseblock at 0x7e0000 */ + fis-index-block = <0x3f>; }; }; diff --git a/arch/arm/boot/dts/gemini.dtsi b/arch/arm/boot/dts/gemini.dtsi index e836bd0818d4..befe322bd7de 100644 --- a/arch/arm/boot/dts/gemini.dtsi +++ b/arch/arm/boot/dts/gemini.dtsi @@ -22,8 +22,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pflash_default_pins>; bank-width = <2>; - #address-cells = <1>; - #size-cells = <1>; status = "disabled"; }; @@ -441,7 +439,7 @@ }; usb0: usb@68000000 { - compatible = "cortina,gemini-usb", "faraday,fotg210"; + compatible = "cortina,gemini-usb", "faraday,fotg200"; reg = <0x68000000 0x1000>; interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; resets = <&syscon GEMINI_RESET_USB0>; @@ -457,12 +455,14 @@ */ pinctrl-names = "default"; pinctrl-0 = <&usb_default_pins>; + /* Default to host mode */ + dr_mode = "host"; syscon = <&syscon>; status = "disabled"; }; usb1: usb@69000000 { - compatible = "cortina,gemini-usb", "faraday,fotg210"; + compatible = "cortina,gemini-usb", "faraday,fotg200"; reg = <0x69000000 0x1000>; interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; resets = <&syscon GEMINI_RESET_USB1>; diff --git a/arch/arm/boot/dts/intel-ixp42x-welltech-epbx100.dts b/arch/arm/boot/dts/intel-ixp42x-welltech-epbx100.dts index f5846a50e4d4..b444003c10e1 100644 --- a/arch/arm/boot/dts/intel-ixp42x-welltech-epbx100.dts +++ b/arch/arm/boot/dts/intel-ixp42x-welltech-epbx100.dts @@ -76,5 +76,23 @@ }; }; }; + + /* LAN port */ + ethernet@c8009000 { + status = "ok"; + queue-rx = <&qmgr 3>; + queue-txready = <&qmgr 20>; + phy-mode = "rgmii"; + phy-handle = <&phy5>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy5: ethernet-phy@5 { + reg = <5>; + }; + }; + }; }; }; diff --git a/arch/arm/boot/dts/keystone-k2hk-evm.dts b/arch/arm/boot/dts/keystone-k2hk-evm.dts index 4a91f5ded402..4352397b4f52 100644 --- a/arch/arm/boot/dts/keystone-k2hk-evm.dts +++ b/arch/arm/boot/dts/keystone-k2hk-evm.dts @@ -28,22 +28,22 @@ leds { compatible = "gpio-leds"; - debug1_1 { + led-debug-1-1 { label = "keystone:green:debug1"; gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; /* 12 */ }; - debug1_2 { + led-debug-1-2 { label = "keystone:red:debug1"; gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; /* 13 */ }; - debug2 { + led-debug-2 { label = "keystone:blue:debug2"; gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; /* 14 */ }; - debug3 { + led-debug-3 { label = "keystone:blue:debug3"; gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; /* 15 */ }; diff --git a/arch/arm/boot/dts/omap3-gta04a5.dts b/arch/arm/boot/dts/omap3-gta04a5.dts index 0b5bd7388877..425081201fd4 100644 --- a/arch/arm/boot/dts/omap3-gta04a5.dts +++ b/arch/arm/boot/dts/omap3-gta04a5.dts @@ -75,6 +75,11 @@ >; }; + bno050_pins: pinmux-bno050-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2136, PIN_INPUT | MUX_MODE4) /* gpin113 */ + >; + }; }; /* @@ -115,17 +120,17 @@ /delete-node/ itg3200@68; /delete-node/ hmc5843@1e; - bmg160@69 { + gyrometer@69 { compatible = "bosch,bmg160"; reg = <0x69>; }; - bmc150@10 { + accelerometer@10 { compatible = "bosch,bmc150_accel"; reg = <0x10>; }; - bmc150@12 { + magnetometer@12 { compatible = "bosch,bmc150_magn"; reg = <0x12>; }; @@ -136,4 +141,12 @@ vdda-supply = <&vio>; vddd-supply = <&vio>; }; + + imu@29 { + compatible = "bosch,bno055"; + reg = <0x29>; + pinctrl-names = "default"; + pinctrl-0 = <&bno050_pins>; + /* interrupt at &gpio4 17 */ + }; }; diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index 6ba2e8f81973..f9f9eca0c56c 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -9,6 +9,7 @@ #include "omap34xx.dtsi" #include <dt-bindings/input/input.h> #include <dt-bindings/leds/common.h> +#include <dt-bindings/media/video-interfaces.h> /* * Default secure signed bootloader (Nokia X-Loader) does not enable L3 firewall @@ -194,7 +195,7 @@ csi_isp: endpoint { remote-endpoint = <&csi_cam1>; - bus-type = <3>; /* CCP2 */ + bus-type = <MEDIA_BUS_TYPE_CCP2>; clock-lanes = <1>; data-lanes = <0>; lane-polarity = <0 0>; @@ -767,56 +768,20 @@ clock-frequency = <400000>; - lis302dl: lis3lv02d@1d { - compatible = "st,lis3lv02d"; + accelerometer@1d { + compatible = "st,lis302dl"; reg = <0x1d>; - Vdd-supply = <&vaux1>; - Vdd_IO-supply = <&vio>; + vdd-supply = <&vaux1>; + vddio-supply = <&vio>; interrupt-parent = <&gpio6>; - interrupts = <21 20>; /* 181 and 180 */ - - /* click flags */ - st,click-single-x; - st,click-single-y; - st,click-single-z; - - /* Limits are 0.5g * value */ - st,click-threshold-x = <8>; - st,click-threshold-y = <8>; - st,click-threshold-z = <10>; - - /* Click must be longer than time limit */ - st,click-time-limit = <9>; - - /* Kind of debounce filter */ - st,click-latency = <50>; - - /* Interrupt line 2 for click detection */ - st,irq2-click; - - st,wakeup-x-hi; - st,wakeup-y-hi; - st,wakeup-threshold = <(800/18)>; /* millig-value / 18 to get HW values */ - - st,wakeup2-z-hi; - st,wakeup2-threshold = <(900/18)>; /* millig-value / 18 to get HW values */ - - st,hipass1-disable; - st,hipass2-disable; - - st,axis-x = <1>; /* LIS3_DEV_X */ - st,axis-y = <(-2)>; /* LIS3_INV_DEV_Y */ - st,axis-z = <(-3)>; /* LIS3_INV_DEV_Z */ - - st,min-limit-x = <(-32)>; - st,min-limit-y = <3>; - st,min-limit-z = <3>; + interrupts = <21 IRQ_TYPE_EDGE_RISING>, + <20 IRQ_TYPE_EDGE_RISING>; /* 181 and 180 */ - st,max-limit-x = <(-3)>; - st,max-limit-y = <32>; - st,max-limit-z = <32>; + mount-matrix = "-1", "0", "0", + "0", "1", "0", + "0", "0", "1"; }; cam1: camera@3e { @@ -835,7 +800,7 @@ port { csi_cam1: endpoint { - bus-type = <3>; /* CCP2 */ + bus-type = <MEDIA_BUS_TYPE_CCP2>; strobe = <1>; clock-inv = <0>; crc = <1>; diff --git a/arch/arm/boot/dts/qcom-apq8026-samsung-matisse-wifi.dts b/arch/arm/boot/dts/qcom-apq8026-samsung-matisse-wifi.dts index 1c52337af560..91b860e24681 100644 --- a/arch/arm/boot/dts/qcom-apq8026-samsung-matisse-wifi.dts +++ b/arch/arm/boot/dts/qcom-apq8026-samsung-matisse-wifi.dts @@ -9,6 +9,9 @@ #include "qcom-msm8226.dtsi" #include "qcom-pm8226.dtsi" +/delete-node/ &adsp_region; +/delete-node/ &smem_region; + / { model = "Samsung Galaxy Tab 4 10.1"; compatible = "samsung,matisse-wifi", "qcom,apq8026"; @@ -77,6 +80,55 @@ }; }; + i2c-backlight { + compatible = "i2c-gpio"; + sda-gpios = <&tlmm 20 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&tlmm 21 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + + pinctrl-0 = <&backlight_i2c_default_state>; + pinctrl-names = "default"; + + i2c-gpio,delay-us = <4>; + + #address-cells = <1>; + #size-cells = <0>; + + backlight@2c { + compatible = "ti,lp8556"; + reg = <0x2c>; + + dev-ctrl = /bits/ 8 <0x80>; + init-brt = /bits/ 8 <0x3f>; + pwm-period = <100000>; + + pwms = <&backlight_pwm 0 100000>; + pwm-names = "lp8556"; + + rom-a0h { + rom-addr = /bits/ 8 <0xa0>; + rom-val = /bits/ 8 <0x44>; + }; + + rom-a1h { + rom-addr = /bits/ 8 <0xa1>; + rom-val = /bits/ 8 <0x6c>; + }; + + rom-a5h { + rom-addr = /bits/ 8 <0xa5>; + rom-val = /bits/ 8 <0x24>; + }; + }; + }; + + backlight_pwm: pwm { + compatible = "clk-pwm"; + #pwm-cells = <2>; + clocks = <&mmcc CAMSS_GP0_CLK>; + pinctrl-0 = <&backlight_pwm_default_state>; + pinctrl-names = "default"; + }; + reg_tsp_1p8v: regulator-tsp-1p8v { compatible = "regulator-fixed"; regulator-name = "tsp_1p8v"; @@ -133,7 +185,7 @@ no-map; }; - adsp@d900000 { + adsp_region: adsp@d900000 { reg = <0x0d900000 0x1800000>; no-map; }; @@ -143,7 +195,6 @@ no-map; }; - /delete-node/ smem@3000000; smem_region: smem@fa00000 { reg = <0x0fa00000 0x100000>; no-map; @@ -169,6 +220,10 @@ }; }; +&adsp { + status = "okay"; +}; + &blsp1_i2c2 { status = "okay"; @@ -412,6 +467,18 @@ bias-disable; }; + backlight_i2c_default_state: backlight-i2c-default-state { + pins = "gpio20", "gpio21"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + backlight_pwm_default_state: backlight-pwm-default-state { + pins = "gpio33"; + function = "gp0_clk"; + }; + muic_int_default_state: muic-int-default-state { pins = "gpio67"; function = "gpio"; diff --git a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts index bf2fb0f70fe4..c57c27cd8a20 100644 --- a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts +++ b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts @@ -22,7 +22,7 @@ #size-cells = <1>; ranges; - ramoops@88d00000{ + ramoops@88d00000 { compatible = "ramoops"; reg = <0x88d00000 0x100000>; record-size = <0x00020000>; diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 0da9623ea084..95705703fe8f 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -375,14 +375,13 @@ }; timer@200a000 { - compatible = "qcom,kpss-timer", - "qcom,kpss-wdt-apq8064", "qcom,msm-timer"; + compatible = "qcom,kpss-wdt-apq8064", "qcom,kpss-timer", + "qcom,msm-timer"; interrupts = <1 1 0x301>, <1 2 0x301>, <1 3 0x301>; reg = <0x0200a000 0x100>; - clock-frequency = <27000000>, - <32768>; + clock-frequency = <27000000>; cpu-offset = <0x80000>; }; @@ -1102,7 +1101,7 @@ dma-names = "tx", "rx"; }; - sdcc3bam: dma-controller@12182000{ + sdcc3bam: dma-controller@12182000 { compatible = "qcom,bam-v1.3.0"; reg = <0x12182000 0x8000>; interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>; @@ -1130,7 +1129,7 @@ pinctrl-0 = <&sdc4_gpios>; }; - sdcc4bam: dma-controller@121c2000{ + sdcc4bam: dma-controller@121c2000 { compatible = "qcom,bam-v1.3.0"; reg = <0x121c2000 0x8000>; interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; @@ -1159,7 +1158,7 @@ dma-names = "tx", "rx"; }; - sdcc1bam: dma-controller@12402000{ + sdcc1bam: dma-controller@12402000 { compatible = "qcom,bam-v1.3.0"; reg = <0x12402000 0x8000>; interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; @@ -1277,7 +1276,8 @@ }; dsi0: dsi@4700000 { - compatible = "qcom,mdss-dsi-ctrl"; + compatible = "qcom,apq8064-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; label = "MDSS DSI CTRL->0"; #address-cells = <1>; #size-cells = <0>; @@ -1493,7 +1493,7 @@ status = "disabled"; }; - mdp: mdp@5100000 { + mdp: display-controller@5100000 { compatible = "qcom,mdp4"; reg = <0x05100000 0xf0000>; interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts b/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts index 44cd72f1b1be..116e59a3b76d 100644 --- a/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts +++ b/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts @@ -19,16 +19,16 @@ serial@f995e000 { status = "okay"; }; + }; +}; - sdhci@f9824900 { - bus-width = <8>; - non-removable; - status = "okay"; - }; +&sdhc_1 { + bus-width = <8>; + non-removable; + status = "okay"; +}; - sdhci@f98a4900 { - cd-gpios = <&tlmm 122 GPIO_ACTIVE_LOW>; - bus-width = <4>; - }; - }; +&sdhc_2 { + cd-gpios = <&tlmm 122 GPIO_ACTIVE_LOW>; + bus-width = <4>; }; diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi index fe30abfff90a..fabd7455eb8f 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -249,11 +249,260 @@ reg = <0xfc4bc000 0x1000>; #address-cells = <1>; #size-cells = <1>; - tsens_calib: calib@d0 { - reg = <0xd0 0x18>; + + tsens_base1: base1@d0 { + reg = <0xd0 0x1>; + bits = <0 8>; + }; + + tsens_s0_p1: s0-p1@d1 { + reg = <0xd1 0x1>; + bits = <0 6>; + }; + + tsens_s1_p1: s1-p1@d2 { + reg = <0xd1 0x2>; + bits = <6 6>; + }; + + tsens_s2_p1: s2-p1@d2 { + reg = <0xd2 0x2>; + bits = <4 6>; + }; + + tsens_s3_p1: s3-p1@d3 { + reg = <0xd3 0x1>; + bits = <2 6>; + }; + + tsens_s4_p1: s4-p1@d4 { + reg = <0xd4 0x1>; + bits = <0 6>; + }; + + tsens_s5_p1: s5-p1@d4 { + reg = <0xd4 0x2>; + bits = <6 6>; + }; + + tsens_s6_p1: s6-p1@d5 { + reg = <0xd5 0x2>; + bits = <4 6>; + }; + + tsens_s7_p1: s7-p1@d6 { + reg = <0xd6 0x1>; + bits = <2 6>; + }; + + tsens_s8_p1: s8-p1@d7 { + reg = <0xd7 0x1>; + bits = <0 6>; + }; + + tsens_mode: mode@d7 { + reg = <0xd7 0x1>; + bits = <6 2>; + }; + + tsens_s9_p1: s9-p1@d8 { + reg = <0xd8 0x1>; + bits = <0 6>; + }; + + tsens_s10_p1: s10_p1@d8 { + reg = <0xd8 0x2>; + bits = <6 6>; + }; + + tsens_base2: base2@d9 { + reg = <0xd9 0x2>; + bits = <4 8>; + }; + + tsens_s0_p2: s0-p2@da { + reg = <0xda 0x2>; + bits = <4 6>; + }; + + tsens_s1_p2: s1-p2@db { + reg = <0xdb 0x1>; + bits = <2 6>; + }; + + tsens_s2_p2: s2-p2@dc { + reg = <0xdc 0x1>; + bits = <0 6>; + }; + + tsens_s3_p2: s3-p2@dc { + reg = <0xdc 0x2>; + bits = <6 6>; + }; + + tsens_s4_p2: s4-p2@dd { + reg = <0xdd 0x2>; + bits = <4 6>; + }; + + tsens_s5_p2: s5-p2@de { + reg = <0xde 0x2>; + bits = <2 6>; + }; + + tsens_s6_p2: s6-p2@df { + reg = <0xdf 0x1>; + bits = <0 6>; + }; + + tsens_s7_p2: s7-p2@e0 { + reg = <0xe0 0x1>; + bits = <0 6>; + }; + + tsens_s8_p2: s8-p2@e0 { + reg = <0xe0 0x2>; + bits = <6 6>; + }; + + tsens_s9_p2: s9-p2@e1 { + reg = <0xe1 0x2>; + bits = <4 6>; + }; + + tsens_s10_p2: s10_p2@e2 { + reg = <0xe2 0x2>; + bits = <2 6>; + }; + + tsens_s5_p2_backup: s5-p2_backup@e3 { + reg = <0xe3 0x2>; + bits = <0 6>; + }; + + tsens_mode_backup: mode_backup@e3 { + reg = <0xe3 0x1>; + bits = <6 2>; + }; + + tsens_s6_p2_backup: s6-p2_backup@e4 { + reg = <0xe4 0x1>; + bits = <0 6>; + }; + + tsens_s7_p2_backup: s7-p2_backup@e4 { + reg = <0xe4 0x2>; + bits = <6 6>; + }; + + tsens_s8_p2_backup: s8-p2_backup@e5 { + reg = <0xe5 0x2>; + bits = <4 6>; + }; + + tsens_s9_p2_backup: s9-p2_backup@e6 { + reg = <0xe6 0x2>; + bits = <2 6>; + }; + + tsens_s10_p2_backup: s10_p2_backup@e7 { + reg = <0xe7 0x1>; + bits = <0 6>; + }; + + tsens_base1_backup: base1_backup@440 { + reg = <0x440 0x1>; + bits = <0 8>; + }; + + tsens_s0_p1_backup: s0-p1_backup@441 { + reg = <0x441 0x1>; + bits = <0 6>; + }; + + tsens_s1_p1_backup: s1-p1_backup@442 { + reg = <0x441 0x2>; + bits = <6 6>; + }; + + tsens_s2_p1_backup: s2-p1_backup@442 { + reg = <0x442 0x2>; + bits = <4 6>; + }; + + tsens_s3_p1_backup: s3-p1_backup@443 { + reg = <0x443 0x1>; + bits = <2 6>; + }; + + tsens_s4_p1_backup: s4-p1_backup@444 { + reg = <0x444 0x1>; + bits = <0 6>; }; - tsens_backup: backup@440 { - reg = <0x440 0x10>; + + tsens_s5_p1_backup: s5-p1_backup@444 { + reg = <0x444 0x2>; + bits = <6 6>; + }; + + tsens_s6_p1_backup: s6-p1_backup@445 { + reg = <0x445 0x2>; + bits = <4 6>; + }; + + tsens_s7_p1_backup: s7-p1_backup@446 { + reg = <0x446 0x1>; + bits = <2 6>; + }; + + tsens_use_backup: use_backup@447 { + reg = <0x447 0x1>; + bits = <5 3>; + }; + + tsens_s8_p1_backup: s8-p1_backup@448 { + reg = <0x448 0x1>; + bits = <0 6>; + }; + + tsens_s9_p1_backup: s9-p1_backup@448 { + reg = <0x448 0x2>; + bits = <6 6>; + }; + + tsens_s10_p1_backup: s10_p1_backup@449 { + reg = <0x449 0x2>; + bits = <4 6>; + }; + + tsens_base2_backup: base2_backup@44a { + reg = <0x44a 0x2>; + bits = <2 8>; + }; + + tsens_s0_p2_backup: s0-p2_backup@44b { + reg = <0x44b 0x3>; + bits = <2 6>; + }; + + tsens_s1_p2_backup: s1-p2_backup@44c { + reg = <0x44c 0x1>; + bits = <0 6>; + }; + + tsens_s2_p2_backup: s2-p2_backup@44c { + reg = <0x44c 0x2>; + bits = <6 6>; + }; + + tsens_s3_p2_backup: s3-p2_backup@44d { + reg = <0x44d 0x2>; + bits = <4 6>; + }; + + tsens_s4_p2_backup: s4-p2_backup@44e { + reg = <0x44e 0x1>; + bits = <2 6>; }; }; @@ -261,8 +510,60 @@ compatible = "qcom,msm8974-tsens", "qcom,tsens-v0_1"; reg = <0xfc4a9000 0x1000>, /* TM */ <0xfc4a8000 0x1000>; /* SROT */ - nvmem-cells = <&tsens_calib>, <&tsens_backup>; - nvmem-cell-names = "calib", "calib_backup"; + nvmem-cells = <&tsens_mode>, + <&tsens_base1>, <&tsens_base2>, + <&tsens_use_backup>, + <&tsens_mode_backup>, + <&tsens_base1_backup>, <&tsens_base2_backup>, + <&tsens_s0_p1>, <&tsens_s0_p2>, + <&tsens_s1_p1>, <&tsens_s1_p2>, + <&tsens_s2_p1>, <&tsens_s2_p2>, + <&tsens_s3_p1>, <&tsens_s3_p2>, + <&tsens_s4_p1>, <&tsens_s4_p2>, + <&tsens_s5_p1>, <&tsens_s5_p2>, + <&tsens_s6_p1>, <&tsens_s6_p2>, + <&tsens_s7_p1>, <&tsens_s7_p2>, + <&tsens_s8_p1>, <&tsens_s8_p2>, + <&tsens_s9_p1>, <&tsens_s9_p2>, + <&tsens_s10_p1>, <&tsens_s10_p2>, + <&tsens_s0_p1_backup>, <&tsens_s0_p2_backup>, + <&tsens_s1_p1_backup>, <&tsens_s1_p2_backup>, + <&tsens_s2_p1_backup>, <&tsens_s2_p2_backup>, + <&tsens_s3_p1_backup>, <&tsens_s3_p2_backup>, + <&tsens_s4_p1_backup>, <&tsens_s4_p2_backup>, + <&tsens_s5_p1_backup>, <&tsens_s5_p2_backup>, + <&tsens_s6_p1_backup>, <&tsens_s6_p2_backup>, + <&tsens_s7_p1_backup>, <&tsens_s7_p2_backup>, + <&tsens_s8_p1_backup>, <&tsens_s8_p2_backup>, + <&tsens_s9_p1_backup>, <&tsens_s9_p2_backup>, + <&tsens_s10_p1_backup>, <&tsens_s10_p2_backup>; + nvmem-cell-names = "mode", + "base1", "base2", + "use_backup", + "mode_backup", + "base1_backup", "base2_backup", + "s0_p1", "s0_p2", + "s1_p1", "s1_p2", + "s2_p1", "s2_p2", + "s3_p1", "s3_p2", + "s4_p1", "s4_p2", + "s5_p1", "s5_p2", + "s6_p1", "s6_p2", + "s7_p1", "s7_p2", + "s8_p1", "s8_p2", + "s9_p1", "s9_p2", + "s10_p1", "s10_p2", + "s0_p1_backup", "s0_p2_backup", + "s1_p1_backup", "s1_p2_backup", + "s2_p1_backup", "s2_p2_backup", + "s3_p1_backup", "s3_p2_backup", + "s4_p1_backup", "s4_p2_backup", + "s5_p1_backup", "s5_p2_backup", + "s6_p1_backup", "s6_p2_backup", + "s7_p1_backup", "s7_p2_backup", + "s8_p1_backup", "s8_p2_backup", + "s9_p1_backup", "s9_p2_backup", + "s10_p1_backup", "s10_p2_backup"; #qcom,sensors = <11>; interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "uplow"; @@ -388,6 +689,24 @@ #reset-cells = <1>; #power-domain-cells = <1>; reg = <0xfc400000 0x4000>; + clocks = <&xo_board>, + <&sleep_clk>, + <0>, /* ufs */ + <0>, + <0>, + <0>, + <0>, /* sata */ + <0>, + <0>; /* pcie */ + clock-names = "xo", + "sleep_clk", + "ufs_rx_symbol_0_clk_src", + "ufs_rx_symbol_1_clk_src", + "ufs_tx_symbol_0_clk_src", + "ufs_tx_symbol_1_clk_src", + "sata_asic0_clk", + "sata_rx_clk", + "pcie_pipe"; }; tcsr_mutex: hwlock@fd484000 { @@ -421,7 +740,7 @@ status = "disabled"; }; - mmc@f9824900 { + sdhc_1: mmc@f9824900 { compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; reg-names = "hc", "core"; @@ -434,7 +753,7 @@ status = "disabled"; }; - mmc@f98a4900 { + sdhc_2: mmc@f98a4900 { compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; reg-names = "hc", "core"; diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index acb08dcf9442..a73c3a17b6a4 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -400,7 +400,7 @@ }; watchdog: watchdog@b017000 { - compatible = "qcom,kpss-wdt", "qcom,kpss-wdt-ipq4019"; + compatible = "qcom,kpss-wdt-ipq4019", "qcom,kpss-wdt"; reg = <0xb017000 0x40>; clocks = <&sleep_clk>; timeout-sec = <10>; diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 7e784b0995da..ae018a7dc6fd 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -549,8 +549,8 @@ }; timer@200a000 { - compatible = "qcom,kpss-timer", - "qcom,kpss-wdt-ipq8064", "qcom,msm-timer"; + compatible = "qcom,kpss-wdt-ipq8064", "qcom,kpss-timer", + "qcom,msm-timer"; interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>, <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | @@ -562,8 +562,7 @@ <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; reg = <0x0200a000 0x100>; - clock-frequency = <25000000>, - <32768>; + clock-frequency = <25000000>; clocks = <&sleep_clk>; clock-names = "sleep"; cpu-offset = <0x80000>; diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi index b0fe1d95d88f..8e9ea61a1e48 100644 --- a/arch/arm/boot/dts/qcom-mdm9615.dtsi +++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi @@ -79,13 +79,13 @@ }; timer@200a000 { - compatible = "qcom,kpss-timer", "qcom,msm-timer"; + compatible = "qcom,kpss-wdt-mdm9615", "qcom,kpss-timer", + "qcom,msm-timer"; interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>, <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>, <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>; reg = <0x0200a000 0x100>; - clock-frequency = <27000000>, - <32768>; + clock-frequency = <27000000>; cpu-offset = <0x80000>; }; @@ -294,7 +294,7 @@ }; }; - sdcc1bam: dma-controller@12182000{ + sdcc1bam: dma-controller@12182000 { compatible = "qcom,bam-v1.3.0"; reg = <0x12182000 0x8000>; interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; @@ -304,7 +304,7 @@ qcom,ee = <0>; }; - sdcc2bam: dma-controller@12142000{ + sdcc2bam: dma-controller@12142000 { compatible = "qcom,bam-v1.3.0"; reg = <0x12142000 0x8000>; interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom-msm8226.dtsi index 4cba25dad8d6..c373081bc21b 100644 --- a/arch/arm/boot/dts/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom-msm8226.dtsi @@ -74,6 +74,13 @@ compatible = "qcom,rpm-msm8226"; qcom,smd-channels = "rpm_requests"; + rpmcc: clock-controller { + compatible = "qcom,rpmcc-msm8226", "qcom,rpmcc"; + #clock-cells = <1>; + clocks = <&xo_board>; + clock-names = "xo"; + }; + rpmpd: power-controller { compatible = "qcom,msm8226-rpmpd"; #power-domain-cells = <1>; diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi index 7debf9db7cb1..a0369b38fe07 100644 --- a/arch/arm/boot/dts/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom-msm8960.dtsi @@ -103,14 +103,13 @@ }; timer@200a000 { - compatible = "qcom,kpss-timer", - "qcom,kpss-wdt-msm8960", "qcom,msm-timer"; + compatible = "qcom,kpss-wdt-msm8960", "qcom,kpss-timer", + "qcom,msm-timer"; interrupts = <GIC_PPI 1 0x301>, <GIC_PPI 2 0x301>, <GIC_PPI 3 0x301>; reg = <0x0200a000 0x100>; - clock-frequency = <27000000>, - <32768>; + clock-frequency = <27000000>; cpu-offset = <0x80000>; }; diff --git a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts index 280e63e3ebf2..ab35f2d644c0 100644 --- a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts +++ b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts @@ -319,6 +319,17 @@ }; }; +&remoteproc_adsp { + cx-supply = <&pm8841_s2>; +}; + +&remoteproc_mss { + cx-supply = <&pm8841_s2>; + mss-supply = <&pm8841_s3>; + mx-supply = <&pm8841_s1>; + pll-supply = <&pm8941_l12>; +}; + &rpm_requests { regulators-0 { compatible = "qcom,rpm-pm8841-regulators"; diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi index 1b683690a1ad..d3bec03b126c 100644 --- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi @@ -188,6 +188,17 @@ qcom,num-strings = <2>; }; +&remoteproc_adsp { + cx-supply = <&pm8841_s2>; +}; + +&remoteproc_mss { + cx-supply = <&pm8841_s2>; + mss-supply = <&pm8841_s3>; + mx-supply = <&pm8841_s1>; + pll-supply = <&pm8941_l12>; +}; + &rpm_requests { regulators-0 { compatible = "qcom,rpm-pm8841-regulators"; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 8d216a3c0851..834ad95515b1 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -307,6 +307,8 @@ rpmcc: clock-controller { compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc"; #clock-cells = <1>; + clocks = <&xo_board>; + clock-names = "xo"; }; }; }; @@ -1054,6 +1056,11 @@ #reset-cells = <1>; #power-domain-cells = <1>; reg = <0xfc400000 0x4000>; + + clocks = <&xo_board>, + <&sleep_clk>; + clock-names = "xo", + "sleep_clk"; }; rpm_msg_ram: sram@fc428000 { @@ -1119,8 +1126,60 @@ compatible = "qcom,msm8974-tsens", "qcom,tsens-v0_1"; reg = <0xfc4a9000 0x1000>, /* TM */ <0xfc4a8000 0x1000>; /* SROT */ - nvmem-cells = <&tsens_calib>, <&tsens_backup>; - nvmem-cell-names = "calib", "calib_backup"; + nvmem-cells = <&tsens_mode>, + <&tsens_base1>, <&tsens_base2>, + <&tsens_use_backup>, + <&tsens_mode_backup>, + <&tsens_base1_backup>, <&tsens_base2_backup>, + <&tsens_s0_p1>, <&tsens_s0_p2>, + <&tsens_s1_p1>, <&tsens_s1_p2>, + <&tsens_s2_p1>, <&tsens_s2_p2>, + <&tsens_s3_p1>, <&tsens_s3_p2>, + <&tsens_s4_p1>, <&tsens_s4_p2>, + <&tsens_s5_p1>, <&tsens_s5_p2>, + <&tsens_s6_p1>, <&tsens_s6_p2>, + <&tsens_s7_p1>, <&tsens_s7_p2>, + <&tsens_s8_p1>, <&tsens_s8_p2>, + <&tsens_s9_p1>, <&tsens_s9_p2>, + <&tsens_s10_p1>, <&tsens_s10_p2>, + <&tsens_s0_p1_backup>, <&tsens_s0_p2_backup>, + <&tsens_s1_p1_backup>, <&tsens_s1_p2_backup>, + <&tsens_s2_p1_backup>, <&tsens_s2_p2_backup>, + <&tsens_s3_p1_backup>, <&tsens_s3_p2_backup>, + <&tsens_s4_p1_backup>, <&tsens_s4_p2_backup>, + <&tsens_s5_p1_backup>, <&tsens_s5_p2_backup>, + <&tsens_s6_p1_backup>, <&tsens_s6_p2_backup>, + <&tsens_s7_p1_backup>, <&tsens_s7_p2_backup>, + <&tsens_s8_p1_backup>, <&tsens_s8_p2_backup>, + <&tsens_s9_p1_backup>, <&tsens_s9_p2_backup>, + <&tsens_s10_p1_backup>, <&tsens_s10_p2_backup>; + nvmem-cell-names = "mode", + "base1", "base2", + "use_backup", + "mode_backup", + "base1_backup", "base2_backup", + "s0_p1", "s0_p2", + "s1_p1", "s1_p2", + "s2_p1", "s2_p2", + "s3_p1", "s3_p2", + "s4_p1", "s4_p2", + "s5_p1", "s5_p2", + "s6_p1", "s6_p2", + "s7_p1", "s7_p2", + "s8_p1", "s8_p2", + "s9_p1", "s9_p2", + "s10_p1", "s10_p2", + "s0_p1_backup", "s0_p2_backup", + "s1_p1_backup", "s1_p2_backup", + "s2_p1_backup", "s2_p2_backup", + "s3_p1_backup", "s3_p2_backup", + "s4_p1_backup", "s4_p2_backup", + "s5_p1_backup", "s5_p2_backup", + "s6_p1_backup", "s6_p2_backup", + "s7_p1_backup", "s7_p2_backup", + "s8_p1_backup", "s8_p2_backup", + "s9_p1_backup", "s9_p2_backup", + "s10_p1_backup", "s10_p2_backup"; #qcom,sensors = <11>; interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "uplow"; @@ -1137,11 +1196,260 @@ reg = <0xfc4bc000 0x1000>; #address-cells = <1>; #size-cells = <1>; - tsens_calib: calib@d0 { - reg = <0xd0 0x18>; + + tsens_base1: base1@d0 { + reg = <0xd0 0x1>; + bits = <0 8>; + }; + + tsens_s0_p1: s0-p1@d1 { + reg = <0xd1 0x1>; + bits = <0 6>; + }; + + tsens_s1_p1: s1-p1@d2 { + reg = <0xd1 0x2>; + bits = <6 6>; + }; + + tsens_s2_p1: s2-p1@d2 { + reg = <0xd2 0x2>; + bits = <4 6>; + }; + + tsens_s3_p1: s3-p1@d3 { + reg = <0xd3 0x1>; + bits = <2 6>; + }; + + tsens_s4_p1: s4-p1@d4 { + reg = <0xd4 0x1>; + bits = <0 6>; + }; + + tsens_s5_p1: s5-p1@d4 { + reg = <0xd4 0x2>; + bits = <6 6>; + }; + + tsens_s6_p1: s6-p1@d5 { + reg = <0xd5 0x2>; + bits = <4 6>; + }; + + tsens_s7_p1: s7-p1@d6 { + reg = <0xd6 0x1>; + bits = <2 6>; + }; + + tsens_s8_p1: s8-p1@d7 { + reg = <0xd7 0x1>; + bits = <0 6>; + }; + + tsens_mode: mode@d7 { + reg = <0xd7 0x1>; + bits = <6 2>; + }; + + tsens_s9_p1: s9-p1@d8 { + reg = <0xd8 0x1>; + bits = <0 6>; + }; + + tsens_s10_p1: s10_p1@d8 { + reg = <0xd8 0x2>; + bits = <6 6>; + }; + + tsens_base2: base2@d9 { + reg = <0xd9 0x2>; + bits = <4 8>; + }; + + tsens_s0_p2: s0-p2@da { + reg = <0xda 0x2>; + bits = <4 6>; + }; + + tsens_s1_p2: s1-p2@db { + reg = <0xdb 0x1>; + bits = <2 6>; + }; + + tsens_s2_p2: s2-p2@dc { + reg = <0xdc 0x1>; + bits = <0 6>; + }; + + tsens_s3_p2: s3-p2@dc { + reg = <0xdc 0x2>; + bits = <6 6>; + }; + + tsens_s4_p2: s4-p2@dd { + reg = <0xdd 0x2>; + bits = <4 6>; + }; + + tsens_s5_p2: s5-p2@de { + reg = <0xde 0x2>; + bits = <2 6>; + }; + + tsens_s6_p2: s6-p2@df { + reg = <0xdf 0x1>; + bits = <0 6>; + }; + + tsens_s7_p2: s7-p2@e0 { + reg = <0xe0 0x1>; + bits = <0 6>; + }; + + tsens_s8_p2: s8-p2@e0 { + reg = <0xe0 0x2>; + bits = <6 6>; + }; + + tsens_s9_p2: s9-p2@e1 { + reg = <0xe1 0x2>; + bits = <4 6>; + }; + + tsens_s10_p2: s10_p2@e2 { + reg = <0xe2 0x2>; + bits = <2 6>; + }; + + tsens_s5_p2_backup: s5-p2_backup@e3 { + reg = <0xe3 0x2>; + bits = <0 6>; + }; + + tsens_mode_backup: mode_backup@e3 { + reg = <0xe3 0x1>; + bits = <6 2>; + }; + + tsens_s6_p2_backup: s6-p2_backup@e4 { + reg = <0xe4 0x1>; + bits = <0 6>; + }; + + tsens_s7_p2_backup: s7-p2_backup@e4 { + reg = <0xe4 0x2>; + bits = <6 6>; + }; + + tsens_s8_p2_backup: s8-p2_backup@e5 { + reg = <0xe5 0x2>; + bits = <4 6>; + }; + + tsens_s9_p2_backup: s9-p2_backup@e6 { + reg = <0xe6 0x2>; + bits = <2 6>; + }; + + tsens_s10_p2_backup: s10_p2_backup@e7 { + reg = <0xe7 0x1>; + bits = <0 6>; + }; + + tsens_base1_backup: base1_backup@440 { + reg = <0x440 0x1>; + bits = <0 8>; + }; + + tsens_s0_p1_backup: s0-p1_backup@441 { + reg = <0x441 0x1>; + bits = <0 6>; + }; + + tsens_s1_p1_backup: s1-p1_backup@442 { + reg = <0x441 0x2>; + bits = <6 6>; + }; + + tsens_s2_p1_backup: s2-p1_backup@442 { + reg = <0x442 0x2>; + bits = <4 6>; + }; + + tsens_s3_p1_backup: s3-p1_backup@443 { + reg = <0x443 0x1>; + bits = <2 6>; + }; + + tsens_s4_p1_backup: s4-p1_backup@444 { + reg = <0x444 0x1>; + bits = <0 6>; + }; + + tsens_s5_p1_backup: s5-p1_backup@444 { + reg = <0x444 0x2>; + bits = <6 6>; + }; + + tsens_s6_p1_backup: s6-p1_backup@445 { + reg = <0x445 0x2>; + bits = <4 6>; + }; + + tsens_s7_p1_backup: s7-p1_backup@446 { + reg = <0x446 0x1>; + bits = <2 6>; + }; + + tsens_use_backup: use_backup@447 { + reg = <0x447 0x1>; + bits = <5 3>; }; - tsens_backup: backup@440 { - reg = <0x440 0x10>; + + tsens_s8_p1_backup: s8-p1_backup@448 { + reg = <0x448 0x1>; + bits = <0 6>; + }; + + tsens_s9_p1_backup: s9-p1_backup@448 { + reg = <0x448 0x2>; + bits = <6 6>; + }; + + tsens_s10_p1_backup: s10_p1_backup@449 { + reg = <0x449 0x2>; + bits = <4 6>; + }; + + tsens_base2_backup: base2_backup@44a { + reg = <0x44a 0x2>; + bits = <2 8>; + }; + + tsens_s0_p2_backup: s0-p2_backup@44b { + reg = <0x44b 0x3>; + bits = <2 6>; + }; + + tsens_s1_p2_backup: s1-p2_backup@44c { + reg = <0x44c 0x1>; + bits = <0 6>; + }; + + tsens_s2_p2_backup: s2-p2_backup@44c { + reg = <0x44c 0x2>; + bits = <6 6>; + }; + + tsens_s3_p2_backup: s3-p2_backup@44d { + reg = <0x44d 0x2>; + bits = <4 6>; + }; + + tsens_s4_p2_backup: s4-p2_backup@44e { + reg = <0x44e 0x1>; + bits = <2 6>; }; }; @@ -1523,9 +1831,33 @@ #reset-cells = <1>; #power-domain-cells = <1>; reg = <0xfd8c0000 0x6000>; - }; - - mdss: mdss@fd900000 { + clocks = <&xo_board>, + <&gcc GCC_MMSS_GPLL0_CLK_SRC>, + <&gcc GPLL0_VOTE>, + <&gcc GPLL1_VOTE>, + <&rpmcc RPM_SMD_GFX3D_CLK_SRC>, + <&dsi0_phy 1>, + <&dsi0_phy 0>, + <&dsi1_phy 1>, + <&dsi1_phy 0>, + <0>, + <0>, + <0>; + clock-names = "xo", + "mmss_gpll0_vote", + "gpll0_vote", + "gpll1_vote", + "gfx3d_clk_src", + "dsi0pll", + "dsi0pllbyte", + "dsi1pll", + "dsi1pllbyte", + "hdmipll", + "edp_link_clk", + "edp_vco_div"; + }; + + mdss: display-subsystem@fd900000 { compatible = "qcom,mdss"; reg = <0xfd900000 0x100>, <0xfd924000 0x1000>; reg-names = "mdss_phys", "vbif_phys"; @@ -1548,8 +1880,8 @@ #size-cells = <1>; ranges; - mdp: mdp@fd900000 { - compatible = "qcom,mdp5"; + mdp: display-controller@fd900000 { + compatible = "qcom,msm8974-mdp5", "qcom,mdp5"; reg = <0xfd900100 0x22000>; reg-names = "mdp_phys"; @@ -1575,11 +1907,19 @@ remote-endpoint = <&dsi0_in>; }; }; + + port@1 { + reg = <1>; + mdp5_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; }; }; dsi0: dsi@fd922800 { - compatible = "qcom,mdss-dsi-ctrl"; + compatible = "qcom,msm8974-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; reg = <0xfd922800 0x1f8>; reg-names = "dsi_ctrl"; @@ -1647,6 +1987,77 @@ status = "disabled"; }; + + dsi1: dsi@fd922e00 { + compatible = "qcom,msm8974-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg = <0xfd922e00 0x1f8>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>; + assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; + + clocks = <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_BYTE1_CLK>, + <&mmcc MDSS_PCLK1_CLK>, + <&mmcc MDSS_ESC1_CLK>, + <&mmcc MMSS_MISC_AHB_CLK>; + clock-names = "mdp_core", + "iface", + "bus", + "byte", + "pixel", + "core", + "core_mmss"; + + phys = <&dsi1_phy>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + remote-endpoint = <&mdp5_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + dsi1_out: endpoint { + }; + }; + }; + }; + + dsi1_phy: phy@fd923000 { + compatible = "qcom,dsi-phy-28nm-hpm"; + reg = <0xfd923000 0xd4>, + <0xfd923100 0x280>, + <0xfd923380 0x30>; + reg-names = "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; }; cci: cci@fda0c000 { diff --git a/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts b/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts index 3b1cc39f2269..04bc58d87abf 100644 --- a/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts +++ b/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts @@ -123,7 +123,7 @@ pinctrl-names = "default"; pinctrl-0 = <&ts_int_pin>; - syna,startup-delay-ms = <10>; + syna,startup-delay-ms = <100>; rmi-f01@1 { reg = <0x1>; @@ -294,8 +294,43 @@ }; }; +&remoteproc_adsp { + cx-supply = <&pm8841_s2>; +}; + +&remoteproc_mss { + cx-supply = <&pm8841_s2>; + mss-supply = <&pm8841_s3>; + mx-supply = <&pm8841_s1>; + pll-supply = <&pm8941_l12>; +}; + &rpm_requests { regulators-0 { + compatible = "qcom,rpm-pm8841-regulators"; + + pm8841_s1: s1 { + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + }; + + pm8841_s2: s2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + }; + + pm8841_s3: s3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + }; + + pm8841_s4: s4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + }; + }; + + regulators-1 { compatible = "qcom,rpm-pm8941-regulators"; vdd_l1_l3-supply = <&pm8941_s1>; @@ -516,6 +551,7 @@ qcom,fast-charge-safe-current = <1500000>; qcom,fast-charge-current-limit = <1500000>; qcom,dc-current-limit = <1800000>; + usb-charge-current-limit = <1800000>; qcom,fast-charge-safe-voltage = <4400000>; qcom,fast-charge-high-threshold-voltage = <4350000>; qcom,fast-charge-low-threshold-voltage = <3400000>; diff --git a/arch/arm/boot/dts/qcom-pm8226.dtsi b/arch/arm/boot/dts/qcom-pm8226.dtsi index eb36d3662464..46ba84f86c9f 100644 --- a/arch/arm/boot/dts/qcom-pm8226.dtsi +++ b/arch/arm/boot/dts/qcom-pm8226.dtsi @@ -1,7 +1,8 @@ // SPDX-License-Identifier: BSD-3-Clause +#include <dt-bindings/iio/qcom,spmi-vadc.h> +#include <dt-bindings/input/linux-event-codes.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/spmi/spmi.h> -#include <dt-bindings/iio/qcom,spmi-vadc.h> &spmi_bus { pm8226_0: pm8226@0 { @@ -10,12 +11,25 @@ #address-cells = <1>; #size-cells = <0>; - pwrkey@800 { - compatible = "qcom,pm8941-pwrkey"; + pon@800 { + compatible = "qcom,pm8916-pon"; reg = <0x800>; - interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; + + pwrkey { + compatible = "qcom,pm8941-pwrkey"; + interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + linux,code = <KEY_POWER>; + }; + + pm8226_resin: resin { + compatible = "qcom,pm8941-resin"; + interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + status = "disabled"; + }; }; smbb: charger@1000 { @@ -41,13 +55,6 @@ chg_otg: otg-vbus { }; }; - rtc@6000 { - compatible = "qcom,pm8941-rtc"; - reg = <0x6000>, <0x6100>; - reg-names = "rtc", "alarm"; - interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; - }; - pm8226_vadc: adc@3100 { compatible = "qcom,spmi-vadc"; reg = <0x3100>; @@ -81,6 +88,19 @@ }; }; + pm8226_iadc: adc@3600 { + compatible = "qcom,pm8226-iadc", "qcom,spmi-iadc"; + reg = <0x3600>; + interrupts = <0x0 0x36 0x0 IRQ_TYPE_EDGE_RISING>; + }; + + rtc@6000 { + compatible = "qcom,pm8941-rtc"; + reg = <0x6000>, <0x6100>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; + }; + pm8226_mpps: mpps@a000 { compatible = "qcom,pm8226-mpp", "qcom,spmi-mpp"; reg = <0xa000>; diff --git a/arch/arm/boot/dts/qcom-sdx55-mtp.dts b/arch/arm/boot/dts/qcom-sdx55-mtp.dts index 9649c1e11311..6f8909731faf 100644 --- a/arch/arm/boot/dts/qcom-sdx55-mtp.dts +++ b/arch/arm/boot/dts/qcom-sdx55-mtp.dts @@ -229,6 +229,10 @@ }; }; +&remoteproc_mpss { + memory-region = <&mpss_adsp_mem>; +}; + &usb { status = "okay"; }; diff --git a/arch/arm/boot/dts/qcom-sdx55-t55.dts b/arch/arm/boot/dts/qcom-sdx55-t55.dts index 7ed8feb99afb..61ac5f54cd57 100644 --- a/arch/arm/boot/dts/qcom-sdx55-t55.dts +++ b/arch/arm/boot/dts/qcom-sdx55-t55.dts @@ -237,9 +237,9 @@ }; &ipa { - status = "okay"; - + qcom,gsi-loader = "self"; memory-region = <&ipa_fw_mem>; + status = "okay"; }; &qpic_bam { diff --git a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts index ac8b4626ae9a..c9c1f7da1261 100644 --- a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts +++ b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts @@ -237,9 +237,9 @@ }; &ipa { - status = "okay"; - + qcom,gsi-loader = "self"; memory-region = <&ipa_fw_mem>; + status = "okay"; }; &pcie0_phy { diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index f1c0dab40992..a9433d1e4f54 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -62,7 +62,13 @@ }; }; - cpu_opp_table: cpu-opp-table { + firmware { + scm { + compatible = "qcom,scm-sdx55", "qcom,scm"; + }; + }; + + cpu_opp_table: opp-table-cpu { compatible = "operating-points-v2"; opp-shared; @@ -87,12 +93,6 @@ }; }; - firmware { - scm { - compatible = "qcom,scm-sdx55", "qcom,scm"; - }; - }; - psci { compatible = "arm,psci-1.0"; method = "smc"; @@ -214,7 +214,8 @@ }; usb_hsphy: phy@ff4000 { - compatible = "qcom,usb-snps-hs-7nm-phy"; + compatible = "qcom,sdx55-usb-hs-phy", + "qcom,usb-snps-hs-7nm-phy"; reg = <0x00ff4000 0x114>; status = "disabled"; #phy-cells = <0>; diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index b073e0c63df4..619cafb6d9b3 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -61,7 +61,19 @@ }; }; - cpu_opp_table: cpu-opp-table { + firmware { + scm { + compatible = "qcom,scm-sdx65", "qcom,scm"; + }; + }; + + mc_virt: interconnect-mc-virt { + compatible = "qcom,sdx65-mc-virt"; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + cpu_opp_table: opp-table-cpu { compatible = "operating-points-v2"; opp-shared; @@ -86,18 +98,6 @@ }; }; - firmware { - scm { - compatible = "qcom,scm-sdx65", "qcom,scm"; - }; - }; - - mc_virt: interconnect-mc-virt { - compatible = "qcom,sdx65-mc-virt"; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - psci { compatible = "arm,psci-1.0"; method = "smc"; @@ -219,7 +219,8 @@ }; usb_hsphy: phy@ff4000 { - compatible = "qcom,usb-snps-hs-7nm-phy"; + compatible = "qcom,sdx65-usb-hs-phy", + "qcom,usb-snps-hs-7nm-phy"; reg = <0xff4000 0x120>; #phy-cells = <0>; status = "disabled"; diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts index 4e58c54cde17..33ac4bd1e63b 100644 --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts @@ -7,6 +7,9 @@ */ /dts-v1/; + +#include <dt-bindings/media/video-interfaces.h> + #include "r8a7742-iwg21d-q7.dts" / { @@ -242,7 +245,7 @@ vin0ep: endpoint { remote-endpoint = <&cam0ep>; bus-width = <8>; - bus-type = <6>; + bus-type = <MEDIA_BUS_TYPE_BT656>; }; }; }; @@ -273,7 +276,7 @@ vin1ep: endpoint { remote-endpoint = <&cam1ep>; bus-width = <8>; - bus-type = <6>; + bus-type = <MEDIA_BUS_TYPE_BT656>; }; }; }; @@ -305,7 +308,7 @@ remote-endpoint = <&cam2ep>; bus-width = <8>; data-shift = <8>; - bus-type = <6>; + bus-type = <MEDIA_BUS_TYPE_BT656>; }; }; }; @@ -335,7 +338,7 @@ vin3ep: endpoint { remote-endpoint = <&cam3ep>; bus-width = <8>; - bus-type = <6>; + bus-type = <MEDIA_BUS_TYPE_BT656>; }; }; }; diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi index 40cef0b1d1e6..c73160df619d 100644 --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi @@ -7,6 +7,8 @@ * Copyright (C) 2020 Renesas Electronics Corp. */ +#include <dt-bindings/media/video-interfaces.h> + #define CAM_ENABLED 1 &CAM_PARENT_I2C { @@ -26,7 +28,7 @@ CAM_EP: endpoint { bus-width = <8>; data-shift = <2>; - bus-type = <6>; + bus-type = <MEDIA_BUS_TYPE_BT656>; pclk-sample = <1>; remote-endpoint = <&VIN_EP>; }; diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi index f5e77f024251..a7f5cfec64b8 100644 --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi @@ -7,6 +7,8 @@ * Copyright (C) 2020 Renesas Electronics Corp. */ +#include <dt-bindings/media/video-interfaces.h> + #define CAM_ENABLED 1 &CAM_PARENT_I2C { @@ -21,7 +23,7 @@ port { CAM_EP: endpoint { bus-width = <8>; - bus-type = <6>; + bus-type = <MEDIA_BUS_TYPE_BT656>; remote-endpoint = <&VIN_EP>; }; }; diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi index 73be346001cb..16d146db824a 100644 --- a/arch/arm/boot/dts/r8a7742.dtsi +++ b/arch/arm/boot/dts/r8a7742.dtsi @@ -1155,7 +1155,7 @@ rcar_sound: sound@ec500000 { /* - * #sound-dai-cells is required + * #sound-dai-cells is required if simple-card * * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index 20f1d98a048d..2245d19a23bb 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -1190,7 +1190,7 @@ rcar_sound: sound@ec500000 { /* - * #sound-dai-cells is required + * #sound-dai-cells is required if simple-card * * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi index 96b2d5a4e8f6..aa13841f9781 100644 --- a/arch/arm/boot/dts/r8a7744.dtsi +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -1190,7 +1190,7 @@ rcar_sound: sound@ec500000 { /* - * #sound-dai-cells is required + * #sound-dai-cells is required if simple-card * * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi index afc902e532d8..44688b8431c3 100644 --- a/arch/arm/boot/dts/r8a7745.dtsi +++ b/arch/arm/boot/dts/r8a7745.dtsi @@ -1120,7 +1120,7 @@ rcar_sound: sound@ec500000 { /* - * #sound-dai-cells is required + * #sound-dai-cells is required if simple-card * * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi index 95efbafb0b70..8d4530ed2fc6 100644 --- a/arch/arm/boot/dts/r8a7778.dtsi +++ b/arch/arm/boot/dts/r8a7778.dtsi @@ -241,7 +241,7 @@ rcar_sound: sound@ffd90000 { /* - * #sound-dai-cells is required + * #sound-dai-cells is required if simple-card * * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 111a6d23159e..2f2e483a2c2a 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -1109,7 +1109,7 @@ rcar_sound: sound@ec500000 { /* - * #sound-dai-cells is required + * #sound-dai-cells is required if simple-card * * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 777b672b59cc..b9d34147628e 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -1223,7 +1223,7 @@ rcar_sound: sound@ec500000 { /* - * #sound-dai-cells is required + * #sound-dai-cells is required if simple-card * * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi index 3e0be1b58931..f51bf687f4bd 100644 --- a/arch/arm/boot/dts/r8a7793.dtsi +++ b/arch/arm/boot/dts/r8a7793.dtsi @@ -988,7 +988,7 @@ rcar_sound: sound@ec500000 { /* - * #sound-dai-cells is required + * #sound-dai-cells is required if simple-card * * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 7aa781ff3bff..371dd4715dde 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -955,7 +955,7 @@ rcar_sound: sound@ec500000 { /* - * #sound-dai-cells is required + * #sound-dai-cells is required if simple-card * * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi index 41e19c0986ce..0fa565a1c3ad 100644 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -117,6 +117,18 @@ }; }; + udc: usb@4001e000 { + compatible = "renesas,r9a06g032-usbf", "renesas,rzn1-usbf"; + reg = <0x4001e000 0x2000>; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sysctrl R9A06G032_HCLK_USBF>, + <&sysctrl R9A06G032_HCLK_USBPM>; + clock-names = "hclkf", "hclkpm"; + power-domains = <&sysctrl>; + status = "disabled"; + }; + pci_usb: pci@40030000 { compatible = "renesas,pci-r9a06g032", "renesas,pci-rzn1"; device_type = "pci"; diff --git a/arch/arm/boot/dts/sama5d31ek.dts b/arch/arm/boot/dts/sama5d31ek.dts index 10fc80d6d30d..1f2dfb3127ab 100644 --- a/arch/arm/boot/dts/sama5d31ek.dts +++ b/arch/arm/boot/dts/sama5d31ek.dts @@ -40,7 +40,7 @@ }; leds { - d3 { + led-d3 { label = "d3"; gpios = <&pioE 24 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/sama5d34ek.dts b/arch/arm/boot/dts/sama5d34ek.dts index 2335bf906f69..bffd61397cb5 100644 --- a/arch/arm/boot/dts/sama5d34ek.dts +++ b/arch/arm/boot/dts/sama5d34ek.dts @@ -50,7 +50,7 @@ }; leds { - d3 { + led-d3 { label = "d3"; gpios = <&pioE 24 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi index 384335635792..7d1d7859edb4 100644 --- a/arch/arm/boot/dts/sama5d3xcm.dtsi +++ b/arch/arm/boot/dts/sama5d3xcm.dtsi @@ -130,7 +130,7 @@ leds { compatible = "gpio-leds"; - d2 { + led-d2 { label = "d2"; gpios = <&pioE 25 GPIO_ACTIVE_LOW>; /* PE25, conflicts with A25, RXD2 */ linux,default-trigger = "heartbeat"; diff --git a/arch/arm/boot/dts/sama5d3xcm_cmp.dtsi b/arch/arm/boot/dts/sama5d3xcm_cmp.dtsi index 5579c955f141..830a0954ba1b 100644 --- a/arch/arm/boot/dts/sama5d3xcm_cmp.dtsi +++ b/arch/arm/boot/dts/sama5d3xcm_cmp.dtsi @@ -184,7 +184,7 @@ leds { compatible = "gpio-leds"; - d2 { + led-d2 { label = "d2"; gpios = <&pioE 25 GPIO_ACTIVE_LOW>; linux,default-trigger = "heartbeat"; diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi index ab131762ecb5..929ba73702e9 100644 --- a/arch/arm/boot/dts/sama7g5.dtsi +++ b/arch/arm/boot/dts/sama7g5.dtsi @@ -516,6 +516,57 @@ status = "disabled"; }; + csi2dc: csi2dc@e1404000 { + compatible = "microchip,sama7g5-csi2dc"; + reg = <0xe1404000 0x500>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&xisc>; + clock-names = "pclk", "scck"; + assigned-clocks = <&xisc>; + assigned-clock-rates = <266000000>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + csi2dc_in: endpoint { + }; + }; + + port@1 { + reg = <1>; + csi2dc_out: endpoint { + bus-width = <14>; + hsync-active = <1>; + vsync-active = <1>; + remote-endpoint = <&xisc_in>; + }; + }; + }; + }; + + xisc: xisc@e1408000 { + compatible = "microchip,sama7g5-isc"; + reg = <0xe1408000 0x2000>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 56>; + clock-names = "hclock"; + #clock-cells = <0>; + clock-output-names = "isc-mck"; + status = "disabled"; + + port { + xisc_in: endpoint { + bus-type = <5>; /* Parallel */ + bus-width = <14>; + hsync-active = <1>; + vsync-active = <1>; + remote-endpoint = <&csi2dc_out>; + }; + }; + }; + pwm: pwm@e1604000 { compatible = "microchip,sama7g5-pwm", "atmel,sama5d2-pwm"; reg = <0xe1604000 0x4000>; diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 6eda6fdc101b..3fee80bbae21 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -749,7 +749,7 @@ arm,prefetch-offset = <7>; }; - l3regs@0xff800000 { + l3regs@ff800000 { compatible = "altr,l3regs", "syscon"; reg = <0xff800000 0x1000>; }; diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index a42a4fd69299..fead7afd5517 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -5,6 +5,7 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/ste-db8500-clkout.h> #include <dt-bindings/reset/stericsson,db8500-prcc-reset.h> #include <dt-bindings/mfd/dbx500-prcmu.h> #include <dt-bindings/arm/ux500_pm_domains.h> @@ -312,6 +313,11 @@ smp_twd_clk: smp-twd-clock { #clock-cells = <0>; }; + + clkout_clk: clkout-clock { + /* Cell 1 id, cell 2 source, cell 3 div */ + #clock-cells = <3>; + }; }; mtu@a03c6000 { diff --git a/arch/arm/boot/dts/ste-href.dtsi b/arch/arm/boot/dts/ste-href.dtsi index 8f1bb78fc1e4..e716121a78ce 100644 --- a/arch/arm/boot/dts/ste-href.dtsi +++ b/arch/arm/boot/dts/ste-href.dtsi @@ -92,20 +92,20 @@ clock-mode = /bits/ 8 <2>; #address-cells = <1>; #size-cells = <0>; - chan@0 { + led@0 { reg = <0>; led-cur = /bits/ 8 <0x2f>; max-cur = /bits/ 8 <0x5f>; color = <LED_COLOR_ID_BLUE>; linux,default-trigger = "heartbeat"; }; - chan@1 { + led@1 { reg = <1>; led-cur = /bits/ 8 <0x2f>; max-cur = /bits/ 8 <0x5f>; color = <LED_COLOR_ID_BLUE>; }; - chan@2 { + led@2 { reg = <2>; led-cur = /bits/ 8 <0x2f>; max-cur = /bits/ 8 <0x5f>; @@ -119,19 +119,19 @@ clock-mode = /bits/ 8 <2>; #address-cells = <1>; #size-cells = <0>; - chan@0 { + led@0 { reg = <0>; led-cur = /bits/ 8 <0x2f>; max-cur = /bits/ 8 <0x5f>; color = <LED_COLOR_ID_BLUE>; }; - chan@1 { + led@1 { reg = <1>; led-cur = /bits/ 8 <0x2f>; max-cur = /bits/ 8 <0x5f>; color = <LED_COLOR_ID_BLUE>; }; - chan@2 { + led@2 { reg = <2>; led-cur = /bits/ 8 <0x2f>; max-cur = /bits/ 8 <0x5f>; diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/stih410.dtsi index a39dd5f7bcae..29e95e9d3229 100644 --- a/arch/arm/boot/dts/stih410.dtsi +++ b/arch/arm/boot/dts/stih410.dtsi @@ -272,7 +272,7 @@ interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>; }; - sti-cec@94a087c { + cec@94a087c { compatible = "st,stih-cec"; reg = <0x94a087c 0x64>; clocks = <&clk_sysin>; diff --git a/arch/arm/boot/dts/tegra114-asus-tf701t.dts b/arch/arm/boot/dts/tegra114-asus-tf701t.dts index 9279d24db009..84a3eb38e71d 100644 --- a/arch/arm/boot/dts/tegra114-asus-tf701t.dts +++ b/arch/arm/boot/dts/tegra114-asus-tf701t.dts @@ -25,6 +25,14 @@ serial2 = &uartb; /* GPS */ }; + firmware { + trusted-foundations { + compatible = "tlm,trusted-foundations"; + tlm,version-major = <2>; + tlm,version-minor = <8>; + }; + }; + memory@80000000 { reg = <0x80000000 0x80000000>; }; @@ -109,6 +117,15 @@ }; codec_default: pinmux-codec-default { + interrupt { + nvidia,pins = "gpio_w2_aud_pw2", + "gpio_w3_aud_pw3"; + nvidia,function = "spi6"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ldo1-en { nvidia,pins = "sdmmc1_wp_n_pv3"; nvidia,function = "sdmmc1"; @@ -116,11 +133,12 @@ nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_DISABLE>; }; + }; - interrupt { - nvidia,pins = "gpio_w2_aud_pw2", - "gpio_w3_aud_pw3"; - nvidia,function = "spi6"; + gpio_hall_sensor_default: pinmux-gpio-hall-sensor-default { + ulpi_data4_po5 { + nvidia,pins = "ulpi_data4_po5"; + nvidia,function = "spi2"; nvidia,pull = <TEGRA_PIN_PULL_UP>; nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; @@ -146,16 +164,6 @@ }; }; - gpio_hall_sensor_default: pinmux-gpio-hall-sensor-default { - ulpi_data4_po5 { - nvidia,pins = "ulpi_data4_po5"; - nvidia,function = "spi2"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - }; - hp_det_default: pinmux-hp-det-default { gmi_iordy_pi5 { nvidia,pins = "kb_row7_pr7"; @@ -198,6 +206,16 @@ }; sdmmc3_default: pinmux-sdmmc3-default { + drive_sdio3 { + nvidia,pins = "drive_sdio3"; + nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; + nvidia,schmitt = <TEGRA_PIN_DISABLE>; + nvidia,pull-down-strength = <22>; + nvidia,pull-up-strength = <36>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; + }; + sdmmc3_clk_pa6 { nvidia,pins = "sdmmc3_clk_pa6"; nvidia,function = "sdmmc3"; @@ -221,16 +239,6 @@ nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; - - drive_sdio3 { - nvidia,pins = "drive_sdio3"; - nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; - nvidia,schmitt = <TEGRA_PIN_DISABLE>; - nvidia,pull-down-strength = <22>; - nvidia,pull-up-strength = <36>; - nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; - nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; - }; }; sdmmc3_vdd_default: pinmux-sdmmc3-vdd-default { @@ -298,6 +306,14 @@ pinctrl-0 = <&codec_default>; }; + temp_sensor: temperature-sensor@4c { + compatible = "onnn,nct1008"; + reg = <0x4c>; + + vcc-supply = <&vdd_3v3_sys>; + #thermal-sensor-cells = <1>; + }; + motion-tracker@68 { compatible = "invensense,mpu6500"; reg = <0x68>; @@ -312,14 +328,6 @@ pinctrl-names = "default"; pinctrl-0 = <&imu_default>; }; - - temp_sensor: temperature-sensor@4c { - compatible = "onnn,nct1008"; - reg = <0x4c>; - - vcc-supply = <&vdd_3v3_sys>; - #thermal-sensor-cells = <1>; - }; }; i2c@7000c400 { @@ -368,6 +376,66 @@ #gpio-cells = <2>; }; + pinmux { + compatible = "ti,tps65913-pinctrl"; + ti,palmas-enable-dvfs1; + + pinctrl-names = "default"; + pinctrl-0 = <&palmas_default>; + + palmas_default: pinmux { + pin_gpio0 { + pins = "gpio0"; + function = "gpio"; + }; + + pin_gpio1 { + pins = "gpio1"; + function = "gpio"; + }; + + pin_gpio2 { + pins = "gpio2"; + function = "gpio"; + }; + + pin_gpio3 { + pins = "gpio3"; + function = "gpio"; + }; + + pin_gpio4 { + pins = "gpio4"; + function = "gpio"; + }; + + pin_gpio5 { + pins = "gpio5"; + function = "gpio"; + }; + + pin_gpio6 { + pins = "gpio6"; + function = "gpio"; + }; + + pin_gpio7 { + pins = "gpio7"; + function = "gpio"; + }; + + pin_powergood { + pins = "powergood"; + function = "powergood"; + }; + + pin_vac { + pins = "vac"; + function = "vac"; + }; + }; + }; + pmic { compatible = "ti,tps65913-pmic", "ti,palmas-pmic"; @@ -528,66 +596,6 @@ interrupt-parent = <&palmas>; interrupts = <8 0>; }; - - pinmux { - compatible = "ti,tps65913-pinctrl"; - ti,palmas-enable-dvfs1; - - pinctrl-names = "default"; - pinctrl-0 = <&palmas_default>; - - palmas_default: pinmux { - pin_powergood { - pins = "powergood"; - function = "powergood"; - }; - - pin_vac { - pins = "vac"; - function = "vac"; - }; - - pin_gpio0 { - pins = "gpio0"; - function = "gpio"; - }; - - pin_gpio1 { - pins = "gpio1"; - function = "gpio"; - }; - - pin_gpio2 { - pins = "gpio2"; - function = "gpio"; - }; - - pin_gpio3 { - pins = "gpio3"; - function = "gpio"; - }; - - pin_gpio4 { - pins = "gpio4"; - function = "gpio"; - }; - - pin_gpio5 { - pins = "gpio5"; - function = "gpio"; - }; - - pin_gpio6 { - pins = "gpio6"; - function = "gpio"; - }; - - pin_gpio7 { - pins = "gpio7"; - function = "gpio"; - }; - }; - }; }; }; @@ -668,11 +676,21 @@ clock-output-names = "pmic-oscillator"; }; - firmware { - trusted-foundations { - compatible = "tlm,trusted-foundations"; - tlm,version-major = <2>; - tlm,version-minor = <8>; + gpio-hall-sensor { + compatible = "gpio-keys"; + + label = "GPIO Hall Effect Sensor"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_hall_sensor_default>; + + switch-hall-sensor { + label = "Hall Effect Sensor"; + gpios = <&gpio TEGRA_GPIO(O, 5) GPIO_ACTIVE_LOW>; + linux,input-type = <EV_SW>; + linux,code = <SW_LID>; + linux,can-disable; + wakeup-source; }; }; @@ -692,36 +710,18 @@ wakeup-source; }; - button-volume-up { - label = "Volume Up"; - gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; - linux,code = <KEY_VOLUMEUP>; - debounce-interval = <10>; - }; - button-volume-down { label = "Volume Down"; gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEDOWN>; debounce-interval = <10>; }; - }; - - gpio-hall-sensor { - compatible = "gpio-keys"; - - label = "GPIO Hall Effect Sensor"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_hall_sensor_default>; - - switch-hall-sensor { - label = "Hall Effect Sensor"; - gpios = <&gpio TEGRA_GPIO(O, 5) GPIO_ACTIVE_LOW>; - linux,input-type = <EV_SW>; - linux,code = <SW_LID>; - linux,can-disable; - wakeup-source; + button-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + debounce-interval = <10>; }; }; diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index fffd62bcea6a..a685fcb129d0 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -909,6 +909,19 @@ #gpio-cells = <2>; }; + pinmux { + compatible = "ti,tps65913-pinctrl"; + pinctrl-names = "default"; + pinctrl-0 = <&palmas_default>; + + palmas_default: pinmux { + pin_gpio6 { + pins = "gpio6"; + function = "gpio"; + }; + }; + }; + pmic { compatible = "ti,tps65913-pmic", "ti,palmas-pmic"; smps1-in-supply = <&tps65090_dcdc3_reg>; @@ -1065,19 +1078,6 @@ interrupt-parent = <&palmas>; interrupts = <8 0>; }; - - pinmux { - compatible = "ti,tps65913-pinctrl"; - pinctrl-names = "default"; - pinctrl-0 = <&palmas_default>; - - palmas_default: pinmux { - pin_gpio6 { - pins = "gpio6"; - function = "gpio"; - }; - }; - }; }; }; diff --git a/arch/arm/boot/dts/tegra124-apalis-emc.dtsi b/arch/arm/boot/dts/tegra124-apalis-emc.dtsi index 7143c6b2ec3e..970f33dd9101 100644 --- a/arch/arm/boot/dts/tegra124-apalis-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-emc.dtsi @@ -4,6 +4,8 @@ * */ +#include <dt-bindings/clock/tegra124-car.h> + / { clock@60006000 { emc-timings-1 { @@ -1474,12 +1476,12 @@ }; }; }; -}; -&emc_icc_dvfs_opp_table { - /delete-node/ opp-1200000000-1100; -}; + opp-table-actmon { + /delete-node/ opp-1200000000; + }; -&emc_bw_dfs_opp_table { - /delete-node/ opp-1200000000; + opp-table-emc { + /delete-node/ opp-1200000000-1100; + }; }; diff --git a/arch/arm/boot/dts/tegra124-apalis-eval.dts b/arch/arm/boot/dts/tegra124-apalis-eval.dts index bce12b3411fc..2df2d8a6b552 100644 --- a/arch/arm/boot/dts/tegra124-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra124-apalis-eval.dts @@ -40,6 +40,16 @@ }; }; + gpio: gpio@6000d000 { + /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ + pex-perst-n-hog { + gpio-hog; + gpios = <TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "PEX_PERST_N"; + }; + }; + /* Apalis UART1 */ serial@70006000 { status = "okay"; @@ -243,13 +253,3 @@ vin-supply = <®_5v0>; }; }; - -&gpio { - /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ - pex-perst-n-hog { - gpio-hog; - gpios = <TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>; - output-high; - line-name = "PEX_PERST_N"; - }; -}; diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts index 800283ad6bdc..f4521fd15f6a 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts @@ -41,6 +41,16 @@ }; }; + gpio@6000d000 { + /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ + pex-perst-n-hog { + gpio-hog; + gpios = <TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "PEX_PERST_N"; + }; + }; + /* Apalis UART1 */ serial@70006000 { status = "okay"; @@ -245,13 +255,3 @@ vin-supply = <®_5v0>; }; }; - -&gpio { - /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ - pex-perst-n-hog { - gpio-hog; - gpios = <TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>; - output-high; - line-name = "PEX_PERST_N"; - }; -}; diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi index dbb0da08cb95..75cfe718737c 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi @@ -65,6 +65,24 @@ vdd-supply = <®_vdd_gpu>; }; + gpio@6000d000 { + /* I210 Gigabit Ethernet Controller Reset */ + lan-reset-n-hog { + gpio-hog; + gpios = <TEGRA_GPIO(S, 2) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "LAN_RESET_N"; + }; + + /* Control MXM3 pin 26 Reset Module Output Carrier Input */ + reset-moci-ctrl-hog { + gpio-hog; + gpios = <TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "RESET_MOCI_CTRL"; + }; + }; + pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -1585,18 +1603,18 @@ pinctrl-0 = <&as3722_default>; as3722_default: pinmux { + gpio0-1-3-4-5-6 { + pins = "gpio0", "gpio1", "gpio3", + "gpio4", "gpio5", "gpio6"; + bias-high-impedance; + }; + gpio2-7 { pins = "gpio2", /* PWR_EN_+V3.3 */ "gpio7"; /* +V1.6_LPO */ function = "gpio"; bias-pull-up; }; - - gpio0-1-3-4-5-6 { - pins = "gpio0", "gpio1", "gpio3", - "gpio4", "gpio5", "gpio6"; - bias-high-impedance; - }; }; regulators { @@ -1943,18 +1961,18 @@ }; }; - clk32k_in: osc3 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - cpus { cpu@0 { vdd-cpu-supply = <®_vdd_cpu>; }; }; + clk32k_in: osc3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + reg_1v05_avdd_hdmi_pll: regulator-1v05-avdd-hdmi-pll { compatible = "regulator-fixed"; regulator-name = "+V1.05_AVDD_HDMI_PLL"; @@ -2056,21 +2074,3 @@ }; }; }; - -&gpio { - /* I210 Gigabit Ethernet Controller Reset */ - lan-reset-n-hog { - gpio-hog; - gpios = <TEGRA_GPIO(S, 2) GPIO_ACTIVE_HIGH>; - output-high; - line-name = "LAN_RESET_N"; - }; - - /* Control MXM3 pin 26 Reset Module Output Carrier Input */ - reset-moci-ctrl-hog { - gpio-hog; - gpios = <TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>; - output-high; - line-name = "RESET_MOCI_CTRL"; - }; -}; diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi index d3f16c117b0c..554c8089491c 100644 --- a/arch/arm/boot/dts/tegra124-apalis.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi @@ -64,6 +64,24 @@ vdd-supply = <®_vdd_gpu>; }; + gpio@6000d000 { + /* I210 Gigabit Ethernet Controller Reset */ + lan-reset-n-hog { + gpio-hog; + gpios = <TEGRA_GPIO(S, 2) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "LAN_RESET_N"; + }; + + /* Control MXM3 pin 26 Reset Module Output Carrier Input */ + reset-moci-ctrl-hog { + gpio-hog; + gpios = <TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "RESET_MOCI_CTRL"; + }; + }; + pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -1578,18 +1596,18 @@ pinctrl-0 = <&as3722_default>; as3722_default: pinmux { + gpio0-1-3-4-5-6 { + pins = "gpio0", "gpio1", "gpio3", + "gpio4", "gpio5", "gpio6"; + bias-high-impedance; + }; + gpio2-7 { pins = "gpio2", /* PWR_EN_+V3.3 */ "gpio7"; /* +V1.6_LPO */ function = "gpio"; bias-pull-up; }; - - gpio0-1-3-4-5-6 { - pins = "gpio0", "gpio1", "gpio3", - "gpio4", "gpio5", "gpio6"; - bias-high-impedance; - }; }; regulators { @@ -1935,18 +1953,18 @@ }; }; - clk32k_in: osc3 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - cpus { cpu@0 { vdd-cpu-supply = <®_vdd_cpu>; }; }; + clk32k_in: osc3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + reg_1v05_avdd_hdmi_pll: regulator-1v05-avdd-hdmi-pll { compatible = "regulator-fixed"; regulator-name = "+V1.05_AVDD_HDMI_PLL"; @@ -2048,21 +2066,3 @@ }; }; }; - -&gpio { - /* I210 Gigabit Ethernet Controller Reset */ - lan-reset-n-hog { - gpio-hog; - gpios = <TEGRA_GPIO(S, 2) GPIO_ACTIVE_HIGH>; - output-high; - line-name = "LAN_RESET_N"; - }; - - /* Control MXM3 pin 26 Reset Module Output Carrier Input */ - reset-moci-ctrl-hog { - gpio-hog; - gpios = <TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>; - output-high; - line-name = "RESET_MOCI_CTRL"; - }; -}; diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi index 79e776db5f37..d10e5334a6c6 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi @@ -1,4 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 + +#include <dt-bindings/clock/tegra124-car.h> + / { clock@60006000 { emc-timings-3 { @@ -2429,12 +2432,12 @@ }; }; }; -}; -&emc_icc_dvfs_opp_table { - /delete-node/ opp-1200000000-1100; -}; + opp-table-actmon { + /delete-node/ opp-1200000000; + }; -&emc_bw_dfs_opp_table { - /delete-node/ opp-1200000000; + opp-table-emc { + /delete-node/ opp-1200000000-1100; + }; }; diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index f41dd4039c07..4196f2401c90 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -68,10 +68,6 @@ }; }; - cec@70015000 { - status = "okay"; - }; - gpu@57000000 { /* * Node left disabled on purpose - the bootloader will enable @@ -1683,6 +1679,10 @@ }; }; + cec@70015000 { + status = "okay"; + }; + /* Serial ATA */ sata@70020000 { status = "okay"; diff --git a/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi b/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi index 31b2e26c69d4..cadb1969f1cc 100644 --- a/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi @@ -1,9 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 -/ { - apbmisc@70000800 { - nvidia,long-ram-code; - }; +#include <dt-bindings/clock/tegra124-car.h> + +/ { clock@60006000 { emc-timings-1 { nvidia,ram-code = <1>; @@ -249,6 +248,10 @@ }; }; + apbmisc@70000800 { + nvidia,long-ram-code; + }; + memory-controller@70019000 { emc-timings-1 { nvidia,ram-code = <1>; @@ -6678,14 +6681,14 @@ }; }; }; -}; -&emc_icc_dvfs_opp_table { - /delete-node/ opp-924000000-1100; - /delete-node/ opp-1200000000-1100; -}; + opp-table-actmon { + /delete-node/ opp-924000000; + /delete-node/ opp-1200000000; + }; -&emc_bw_dfs_opp_table { - /delete-node/ opp-924000000; - /delete-node/ opp-1200000000; + opp-table-emc { + /delete-node/ opp-924000000-1100; + /delete-node/ opp-1200000000-1100; + }; }; diff --git a/arch/arm/boot/dts/tegra124-nyan-big.dts b/arch/arm/boot/dts/tegra124-nyan-big.dts index 9a01dfed1379..8bca9599ad6e 100644 --- a/arch/arm/boot/dts/tegra124-nyan-big.dts +++ b/arch/arm/boot/dts/tegra124-nyan-big.dts @@ -25,17 +25,6 @@ }; }; - mmc@700b0400 { /* SD Card on this bus */ - wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; - }; - - sound { - compatible = "nvidia,tegra-audio-max98090-nyan-big", - "nvidia,tegra-audio-max98090-nyan", - "nvidia,tegra-audio-max98090"; - nvidia,model = "GoogleNyanBig"; - }; - pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&pinmux_default>; @@ -1345,4 +1334,15 @@ }; }; }; + + mmc@700b0400 { /* SD Card on this bus */ + wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; + }; + + sound { + compatible = "nvidia,tegra-audio-max98090-nyan-big", + "nvidia,tegra-audio-max98090-nyan", + "nvidia,tegra-audio-max98090"; + nvidia,model = "GoogleNyanBig"; + }; }; diff --git a/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi b/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi index 2ce1b12be44d..e8dcc4f51fc5 100644 --- a/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi @@ -1,4 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 + +#include <dt-bindings/clock/tegra124-car.h> + / { clock@60006000 { emc-timings-1 { @@ -2055,14 +2058,14 @@ }; }; }; -}; -&emc_icc_dvfs_opp_table { - /delete-node/ opp-924000000-1100; - /delete-node/ opp-1200000000-1100; -}; + opp-table-actmon { + /delete-node/ opp-924000000; + /delete-node/ opp-1200000000; + }; -&emc_bw_dfs_opp_table { - /delete-node/ opp-924000000; - /delete-node/ opp-1200000000; + opp-table-emc { + /delete-node/ opp-924000000-1100; + /delete-node/ opp-1200000000-1100; + }; }; diff --git a/arch/arm/boot/dts/tegra124-nyan-blaze.dts b/arch/arm/boot/dts/tegra124-nyan-blaze.dts index 0beef1c03ff3..432540c10065 100644 --- a/arch/arm/boot/dts/tegra124-nyan-blaze.dts +++ b/arch/arm/boot/dts/tegra124-nyan-blaze.dts @@ -27,13 +27,6 @@ }; }; - sound { - compatible = "nvidia,tegra-audio-max98090-nyan-blaze", - "nvidia,tegra-audio-max98090-nyan", - "nvidia,tegra-audio-max98090"; - nvidia,model = "GoogleNyanBlaze"; - }; - pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&pinmux_default>; @@ -1343,4 +1336,11 @@ }; }; }; + + sound { + compatible = "nvidia,tegra-audio-max98090-nyan-blaze", + "nvidia,tegra-audio-max98090-nyan", + "nvidia,tegra-audio-max98090"; + nvidia,model = "GoogleNyanBlaze"; + }; }; diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi index 13061ab5247b..56952333ae28 100644 --- a/arch/arm/boot/dts/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan.dtsi @@ -498,12 +498,6 @@ }; }; - sdhci0_pwrseq: sdhci0_pwrseq { - compatible = "mmc-pwrseq-simple"; - - reset-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; - }; - mmc@700b0000 { /* WiFi/BT on this bus */ status = "okay"; bus-width = <4>; @@ -595,14 +589,35 @@ }; cpus { - cpu@0 { + cpu0: cpu@0 { + #cooling-cells = <2>; vdd-cpu-supply = <&vdd_cpu>; }; + + cpu1: cpu@1 { + #cooling-cells = <2>; + }; + + cpu2: cpu@2 { + #cooling-cells = <2>; + }; + + cpu3: cpu@3 { + #cooling-cells = <2>; + }; }; gpio-keys { compatible = "gpio-keys"; + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; + linux,code = <KEY_POWER>; + debounce-interval = <30>; + wakeup-source; + }; + switch-lid { label = "Lid"; gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>; @@ -611,14 +626,18 @@ debounce-interval = <1>; wakeup-source; }; + }; - key-power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; - linux,code = <KEY_POWER>; - debounce-interval = <30>; - wakeup-source; - }; + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + priority = <200>; + }; + + sdhci0_pwrseq: pwrseq-sdhci0 { + compatible = "mmc-pwrseq-simple"; + + reset-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; }; vdd_mux: regulator-mux { @@ -785,30 +804,6 @@ <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>; }; - gpio-restart { - compatible = "gpio-restart"; - gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; - priority = <200>; - }; - - cpus { - cpu0: cpu@0 { - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - #cooling-cells = <2>; - }; - - cpu2: cpu@2 { - #cooling-cells = <2>; - }; - - cpu3: cpu@3 { - #cooling-cells = <2>; - }; - }; - thermal-zones { cpu-skin-thermal { polling-delay-passive = <1000>; /* milliseconds */ diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index a9ab548781e1..b3fbecf5c818 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -639,6 +639,16 @@ reset-names = "fuse"; }; + cec@70015000 { + compatible = "nvidia,tegra124-cec"; + reg = <0x0 0x70015000 0x0 0x00001000>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_CEC>; + clock-names = "cec"; + status = "disabled"; + hdmi-phandle = <&hdmi>; + }; + mc: memory-controller@70019000 { compatible = "nvidia,tegra124-mc"; reg = <0x0 0x70019000 0x0 0x1000>; @@ -906,16 +916,6 @@ status = "disabled"; }; - cec@70015000 { - compatible = "nvidia,tegra124-cec"; - reg = <0x0 0x70015000 0x0 0x00001000>; - interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&tegra_car TEGRA124_CLK_CEC>; - clock-names = "cec"; - status = "disabled"; - hdmi-phandle = <&hdmi>; - }; - soctherm: thermal-sensor@700e2000 { compatible = "nvidia,tegra124-soctherm"; reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */ diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts index 17afc2c7cb37..08b42952f4de 100644 --- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts @@ -347,31 +347,34 @@ nvidia,pins = "ddc"; nvidia,function = "i2c2"; }; + pta { nvidia,pins = "pta"; nvidia,function = "rsvd4"; }; }; - state_i2cmux_pta: pinmux-i2cmux-pta { + state_i2cmux_idle: pinmux-i2cmux-idle { ddc { nvidia,pins = "ddc"; nvidia,function = "rsvd4"; }; + pta { nvidia,pins = "pta"; - nvidia,function = "i2c2"; + nvidia,function = "rsvd4"; }; }; - state_i2cmux_idle: pinmux-i2cmux-idle { + state_i2cmux_pta: pinmux-i2cmux-pta { ddc { nvidia,pins = "ddc"; nvidia,function = "rsvd4"; }; + pta { nvidia,pins = "pta"; - nvidia,function = "rsvd4"; + nvidia,function = "i2c2"; }; }; }; @@ -425,6 +428,10 @@ /* Docking station */ }; + pwm: pwm@7000a000 { + status = "okay"; + }; + i2c@7000c000 { clock-frequency = <400000>; status = "okay"; @@ -512,45 +519,6 @@ status = "okay"; }; - i2cmux { - compatible = "i2c-mux-pinctrl"; - #address-cells = <1>; - #size-cells = <0>; - - i2c-parent = <&{/i2c@7000c400}>; - - pinctrl-names = "ddc", "pta", "idle"; - pinctrl-0 = <&state_i2cmux_ddc>; - pinctrl-1 = <&state_i2cmux_pta>; - pinctrl-2 = <&state_i2cmux_idle>; - - hdmi_ddc: i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - panel_ddc: i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - embedded-controller@58 { - compatible = "acer,a500-iconia-ec", "ene,kb930"; - reg = <0x58>; - - system-power-controller; - - monitored-battery = <&bat1010>; - power-supplies = <&mains>; - }; - }; - }; - - pwm: pwm@7000a000 { - status = "okay"; - }; - i2c@7000d000 { clock-frequency = <100000>; status = "okay"; @@ -729,396 +697,6 @@ core-supply = <&vdd_core>; }; - usb@c5000000 { - compatible = "nvidia,tegra20-udc"; - status = "okay"; - dr_mode = "peripheral"; - }; - - usb-phy@c5000000 { - status = "okay"; - dr_mode = "peripheral"; - nvidia,xcvr-setup-use-fuses; - nvidia,xcvr-lsfslew = <2>; - nvidia,xcvr-lsrslew = <2>; - }; - - usb@c5008000 { - status = "okay"; - }; - - usb-phy@c5008000 { - status = "okay"; - nvidia,xcvr-setup-use-fuses; - nvidia,xcvr-lsfslew = <2>; - nvidia,xcvr-lsrslew = <2>; - vbus-supply = <&vdd_5v0_sys>; - }; - - brcm_wifi_pwrseq: wifi-pwrseq { - compatible = "mmc-pwrseq-simple"; - - clocks = <&rtc_32k_wifi>; - clock-names = "ext_clock"; - - reset-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_LOW>; - post-power-on-delay-ms = <300>; - power-off-delay-us = <300>; - }; - - sdmmc1: mmc@c8000000 { - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - - assigned-clocks = <&tegra_car TEGRA20_CLK_SDMMC1>; - assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_C>; - assigned-clock-rates = <50000000>; - - max-frequency = <50000000>; - keep-power-in-suspend; - bus-width = <4>; - non-removable; - - mmc-pwrseq = <&brcm_wifi_pwrseq>; - vmmc-supply = <&vdd_3v3_sys>; - vqmmc-supply = <&vdd_1v8_sys>; - - /* Azurewave AW-NH611 BCM4329 */ - wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&gpio>; - interrupts = <TEGRA_GPIO(S, 0) IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "host-wake"; - }; - }; - - sdmmc3: mmc@c8000400 { - status = "okay"; - bus-width = <4>; - cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; - power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; - vmmc-supply = <&vdd_3v3_sys>; - vqmmc-supply = <&vdd_3v3_sys>; - }; - - sdmmc4: mmc@c8000600 { - status = "okay"; - bus-width = <8>; - vmmc-supply = <&vcore_emmc>; - vqmmc-supply = <&vdd_3v3_sys>; - non-removable; - }; - - mains: ac-adapter-detect { - compatible = "gpio-charger"; - charger-type = "mains"; - gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - - enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; - power-supply = <&vdd_3v3_sys>; - pwms = <&pwm 2 41667>; - - brightness-levels = <7 255>; - num-interpolated-steps = <248>; - default-brightness-level = <20>; - }; - - bat1010: battery-2s1p { - compatible = "simple-battery"; - charge-full-design-microamp-hours = <3260000>; - energy-full-design-microwatt-hours = <24000000>; - operating-range-celsius = <0 40>; - }; - - /* PMIC has a built-in 32KHz oscillator which is used by PMC */ - clk32k_in: clock-32k-in { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "tps658621-out32k"; - }; - - /* - * This standalone onboard fixed-clock always-ON 32KHz - * oscillator is used as a reference clock-source by the - * Azurewave WiFi/BT module. - */ - rtc_32k_wifi: clock-32k-wifi { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "kk3270032"; - }; - - cpus { - cpu0: cpu@0 { - cpu-supply = <&vdd_cpu>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - cpu-supply = <&vdd_cpu>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - }; - }; - - display-panel { - compatible = "auo,b101ew05", "panel-lvds"; - - ddc-i2c-bus = <&panel_ddc>; - power-supply = <&vdd_pnl>; - backlight = <&backlight>; - - width-mm = <218>; - height-mm = <135>; - - data-mapping = "jeida-18"; - - panel-timing { - clock-frequency = <71200000>; - hactive = <1280>; - vactive = <800>; - hfront-porch = <8>; - hback-porch = <18>; - hsync-len = <184>; - vsync-len = <3>; - vfront-porch = <4>; - vback-porch = <8>; - }; - - port { - panel_input: endpoint { - remote-endpoint = <&lvds_encoder_output>; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(I, 3) GPIO_ACTIVE_HIGH>; - linux,code = <KEY_POWER>; - debounce-interval = <10>; - wakeup-event-action = <EV_ACT_ASSERTED>; - wakeup-source; - }; - - key-rotation-lock { - label = "Rotate-lock"; - gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_HIGH>; - linux,code = <SW_ROTATE_LOCK>; - linux,input-type = <EV_SW>; - debounce-interval = <10>; - }; - - key-volume-up { - label = "Volume Up"; - gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; - linux,code = <KEY_VOLUMEUP>; - debounce-interval = <10>; - wakeup-event-action = <EV_ACT_ASSERTED>; - wakeup-source; - }; - - key-volume-down { - label = "Volume Down"; - gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>; - linux,code = <KEY_VOLUMEDOWN>; - debounce-interval = <10>; - wakeup-event-action = <EV_ACT_ASSERTED>; - wakeup-source; - }; - }; - - haptic-feedback { - compatible = "gpio-vibrator"; - enable-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>; - vcc-supply = <&vdd_3v3_sys>; - }; - - lvds-encoder { - compatible = "ti,sn75lvds83", "lvds-encoder"; - - powerdown-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_LOW>; - power-supply = <&vdd_3v3_sys>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - lvds_encoder_input: endpoint { - remote-endpoint = <&lcd_output>; - }; - }; - - port@1 { - reg = <1>; - - lvds_encoder_output: endpoint { - remote-endpoint = <&panel_input>; - }; - }; - }; - }; - - vdd_5v0_sys: regulator-5v0 { - compatible = "regulator-fixed"; - regulator-name = "vdd_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - vdd_3v3_sys: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "vdd_3v3_vs"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_1v8_sys: regulator-1v8 { - compatible = "regulator-fixed"; - regulator-name = "vdd_1v8_vs"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_pnl: regulator-panel { - compatible = "regulator-fixed"; - regulator-name = "vdd_panel"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <300000>; - gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; - - sound { - compatible = "nvidia,tegra-audio-wm8903-picasso", - "nvidia,tegra-audio-wm8903"; - nvidia,model = "Acer Iconia Tab A500 WM8903"; - - nvidia,audio-routing = - "Headphone Jack", "HPOUTR", - "Headphone Jack", "HPOUTL", - "Int Spk", "LINEOUTL", - "Int Spk", "LINEOUTR", - "Mic Jack", "MICBIAS", - "IN2L", "Mic Jack", - "IN2R", "Mic Jack", - "IN1L", "Int Mic", - "IN1R", "Int Mic"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&wm8903>; - - nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; - nvidia,int-mic-en-gpios = <&wm8903 1 GPIO_ACTIVE_HIGH>; - nvidia,headset; - - clocks = <&tegra_car TEGRA20_CLK_PLL_A>, - <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA20_CLK_CDEV1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; - - thermal-zones { - /* - * NCT1008 has two sensors: - * - * 0: internal that monitors ambient/skin temperature - * 1: external that is connected to the CPU's diode - * - * Ideally we should use userspace thermal governor, - * but it's a much more complex solution. The "skin" - * zone is a simpler solution which prevents A500 from - * getting too hot from a user's tactile perspective. - * The CPU zone is intended to protect silicon from damage. - */ - - skin-thermal { - polling-delay-passive = <1000>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - thermal-sensors = <&nct1008 0>; - - trips { - trip0: skin-alert { - /* start throttling at 60C */ - temperature = <60000>; - hysteresis = <200>; - type = "passive"; - }; - - trip1: skin-crit { - /* shut down at 70C */ - temperature = <70000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&trip0>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu-thermal { - polling-delay-passive = <1000>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - thermal-sensors = <&nct1008 1>; - - trips { - trip2: cpu-alert { - /* throttle at 85C until temperature drops to 84.8C */ - temperature = <85000>; - hysteresis = <200>; - type = "passive"; - }; - - trip3: cpu-crit { - /* shut down at 90C */ - temperature = <90000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map1 { - trip = <&trip2>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - memory-controller@7000f400 { nvidia,use-ram-code; @@ -1514,9 +1092,434 @@ }; }; }; -}; -&emc_icc_dvfs_opp_table { - /delete-node/ opp-666000000; - /delete-node/ opp-760000000; + usb@c5000000 { + compatible = "nvidia,tegra20-udc"; + status = "okay"; + dr_mode = "peripheral"; + }; + + usb-phy@c5000000 { + status = "okay"; + dr_mode = "peripheral"; + nvidia,xcvr-setup-use-fuses; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + }; + + usb@c5008000 { + status = "okay"; + }; + + usb-phy@c5008000 { + status = "okay"; + nvidia,xcvr-setup-use-fuses; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + vbus-supply = <&vdd_5v0_sys>; + }; + + sdmmc1: mmc@c8000000 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + assigned-clocks = <&tegra_car TEGRA20_CLK_SDMMC1>; + assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_C>; + assigned-clock-rates = <50000000>; + + max-frequency = <50000000>; + keep-power-in-suspend; + bus-width = <4>; + non-removable; + + mmc-pwrseq = <&brcm_wifi_pwrseq>; + vmmc-supply = <&vdd_3v3_sys>; + vqmmc-supply = <&vdd_1v8_sys>; + + /* Azurewave AW-NH611 BCM4329 */ + wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(S, 0) IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; + }; + + sdmmc3: mmc@c8000400 { + status = "okay"; + bus-width = <4>; + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; + vmmc-supply = <&vdd_3v3_sys>; + vqmmc-supply = <&vdd_3v3_sys>; + }; + + sdmmc4: mmc@c8000600 { + status = "okay"; + bus-width = <8>; + vmmc-supply = <&vcore_emmc>; + vqmmc-supply = <&vdd_3v3_sys>; + non-removable; + }; + + mains: ac-adapter-detect { + compatible = "gpio-charger"; + charger-type = "mains"; + gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_3v3_sys>; + pwms = <&pwm 2 41667>; + + brightness-levels = <7 255>; + num-interpolated-steps = <248>; + default-brightness-level = <20>; + }; + + bat1010: battery-2s1p { + compatible = "simple-battery"; + charge-full-design-microamp-hours = <3260000>; + energy-full-design-microwatt-hours = <24000000>; + operating-range-celsius = <0 40>; + }; + + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ + clk32k_in: clock-32k-in { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "tps658621-out32k"; + }; + + /* + * This standalone onboard fixed-clock always-ON 32KHz + * oscillator is used as a reference clock-source by the + * Azurewave WiFi/BT module. + */ + rtc_32k_wifi: clock-32k-wifi { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "kk3270032"; + }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + + cpu1: cpu@1 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + }; + + display-panel { + compatible = "auo,b101ew05", "panel-lvds"; + + ddc-i2c-bus = <&panel_ddc>; + power-supply = <&vdd_pnl>; + backlight = <&backlight>; + + width-mm = <218>; + height-mm = <135>; + + data-mapping = "jeida-18"; + + panel-timing { + clock-frequency = <71200000>; + hactive = <1280>; + vactive = <800>; + hfront-porch = <8>; + hback-porch = <18>; + hsync-len = <184>; + vsync-len = <3>; + vfront-porch = <4>; + vback-porch = <8>; + }; + + port { + panel_input: endpoint { + remote-endpoint = <&lvds_encoder_output>; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(I, 3) GPIO_ACTIVE_HIGH>; + linux,code = <KEY_POWER>; + debounce-interval = <10>; + wakeup-event-action = <EV_ACT_ASSERTED>; + wakeup-source; + }; + + key-rotation-lock { + label = "Rotate-lock"; + gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_HIGH>; + linux,code = <SW_ROTATE_LOCK>; + linux,input-type = <EV_SW>; + debounce-interval = <10>; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEDOWN>; + debounce-interval = <10>; + wakeup-event-action = <EV_ACT_ASSERTED>; + wakeup-source; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + debounce-interval = <10>; + wakeup-event-action = <EV_ACT_ASSERTED>; + wakeup-source; + }; + }; + + haptic-feedback { + compatible = "gpio-vibrator"; + enable-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>; + vcc-supply = <&vdd_3v3_sys>; + }; + + i2cmux { + compatible = "i2c-mux-pinctrl"; + #address-cells = <1>; + #size-cells = <0>; + + i2c-parent = <&{/i2c@7000c400}>; + + pinctrl-names = "ddc", "pta", "idle"; + pinctrl-0 = <&state_i2cmux_ddc>; + pinctrl-1 = <&state_i2cmux_pta>; + pinctrl-2 = <&state_i2cmux_idle>; + + hdmi_ddc: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + panel_ddc: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + embedded-controller@58 { + compatible = "acer,a500-iconia-ec", "ene,kb930"; + reg = <0x58>; + + system-power-controller; + + monitored-battery = <&bat1010>; + power-supplies = <&mains>; + }; + }; + }; + + lvds-encoder { + compatible = "ti,sn75lvds83", "lvds-encoder"; + + powerdown-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_LOW>; + power-supply = <&vdd_3v3_sys>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lvds_encoder_input: endpoint { + remote-endpoint = <&lcd_output>; + }; + }; + + port@1 { + reg = <1>; + + lvds_encoder_output: endpoint { + remote-endpoint = <&panel_input>; + }; + }; + }; + }; + + opp-table-emc { + /delete-node/ opp-666000000; + /delete-node/ opp-760000000; + }; + + vdd_5v0_sys: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + vdd_3v3_sys: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3_vs"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_1v8_sys: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v8_vs"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_pnl: regulator-panel { + compatible = "regulator-fixed"; + regulator-name = "vdd_panel"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <300000>; + gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + + sound { + compatible = "nvidia,tegra-audio-wm8903-picasso", + "nvidia,tegra-audio-wm8903"; + nvidia,model = "Acer Iconia Tab A500 WM8903"; + + nvidia,audio-routing = + "Headphone Jack", "HPOUTR", + "Headphone Jack", "HPOUTL", + "Int Spk", "LINEOUTL", + "Int Spk", "LINEOUTR", + "Mic Jack", "MICBIAS", + "IN2L", "Mic Jack", + "IN2R", "Mic Jack", + "IN1L", "Int Mic", + "IN1R", "Int Mic"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&wm8903>; + + nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; + nvidia,int-mic-en-gpios = <&wm8903 1 GPIO_ACTIVE_HIGH>; + nvidia,headset; + + clocks = <&tegra_car TEGRA20_CLK_PLL_A>, + <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA20_CLK_CDEV1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + }; + + thermal-zones { + /* + * NCT1008 has two sensors: + * + * 0: internal that monitors ambient/skin temperature + * 1: external that is connected to the CPU's diode + * + * Ideally we should use userspace thermal governor, + * but it's a much more complex solution. The "skin" + * zone is a simpler solution which prevents A500 from + * getting too hot from a user's tactile perspective. + * The CPU zone is intended to protect silicon from damage. + */ + + skin-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&nct1008 0>; + + trips { + trip0: skin-alert { + /* start throttling at 60C */ + temperature = <60000>; + hysteresis = <200>; + type = "passive"; + }; + + trip1: skin-crit { + /* shut down at 70C */ + temperature = <70000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&trip0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&nct1008 1>; + + trips { + trip2: cpu-alert { + /* throttle at 85C until temperature drops to 84.8C */ + temperature = <85000>; + hysteresis = <200>; + type = "passive"; + }; + + trip3: cpu-crit { + /* shut down at 90C */ + temperature = <90000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map1 { + trip = <&trip2>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + brcm_wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + + clocks = <&rtc_32k_wifi>; + clock-names = "ext_clock"; + + reset-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <300>; + power-off-delay-us = <300>; + }; }; diff --git a/arch/arm/boot/dts/tegra20-asus-tf101.dts b/arch/arm/boot/dts/tegra20-asus-tf101.dts index c39ddb462ad0..7b2969656ec9 100644 --- a/arch/arm/boot/dts/tegra20-asus-tf101.dts +++ b/arch/arm/boot/dts/tegra20-asus-tf101.dts @@ -411,7 +411,7 @@ }; }; - state_i2cmux_pta: pinmux-i2cmux-pta { + state_i2cmux_idle: pinmux-i2cmux-idle { ddc { nvidia,pins = "ddc"; nvidia,function = "rsvd4"; @@ -419,11 +419,11 @@ pta { nvidia,pins = "pta"; - nvidia,function = "i2c2"; + nvidia,function = "rsvd4"; }; }; - state_i2cmux_idle: pinmux-i2cmux-idle { + state_i2cmux_pta: pinmux-i2cmux-pta { ddc { nvidia,pins = "ddc"; nvidia,function = "rsvd4"; @@ -431,7 +431,7 @@ pta { nvidia,pins = "pta"; - nvidia,function = "rsvd4"; + nvidia,function = "i2c2"; }; }; }; @@ -764,13 +764,6 @@ #address-cells = <1>; #size-cells = <0>; - lpddr2 { - compatible = "elpida,B8132B2PB-6D-F", "jedec,lpddr2-s4"; - revision-id = <1 0>; - density = <2048>; - io-width = <16>; - }; - emc-table@25000 { reg = <25000>; compatible = "nvidia,tegra20-emc-table"; @@ -860,6 +853,13 @@ 0x007e0010 0x00000000 0x00000000 0x0000001b 0x00000000 0x00000000 0x00000000 0x00000000>; }; + + lpddr2 { + compatible = "elpida,B8132B2PB-6D-F", "jedec,lpddr2-s4"; + revision-id = <1 0>; + density = <2048>; + io-width = <16>; + }; }; }; @@ -977,47 +977,6 @@ }; }; - gpio-keys { - compatible = "gpio-keys"; - - switch-dock-hall-sensor { - label = "Lid"; - gpios = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_LOW>; - linux,input-type = <EV_SW>; - linux,code = <SW_LID>; - debounce-interval = <500>; - wakeup-event-action = <EV_ACT_ASSERTED>; - wakeup-source; - }; - - key-power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; - linux,code = <KEY_POWER>; - debounce-interval = <10>; - wakeup-event-action = <EV_ACT_ASSERTED>; - wakeup-source; - }; - - key-volume-up { - label = "Volume Up"; - gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>; - linux,code = <KEY_VOLUMEUP>; - debounce-interval = <10>; - wakeup-event-action = <EV_ACT_ASSERTED>; - wakeup-source; - }; - - key-volume-down { - label = "Volume Down"; - gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; - linux,code = <KEY_VOLUMEDOWN>; - debounce-interval = <10>; - wakeup-event-action = <EV_ACT_ASSERTED>; - wakeup-source; - }; - }; - display-panel { compatible = "auo,b101ew05", "panel-lvds"; @@ -1051,6 +1010,47 @@ }; }; + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; + linux,code = <KEY_POWER>; + debounce-interval = <10>; + wakeup-event-action = <EV_ACT_ASSERTED>; + wakeup-source; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEDOWN>; + debounce-interval = <10>; + wakeup-event-action = <EV_ACT_ASSERTED>; + wakeup-source; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + debounce-interval = <10>; + wakeup-event-action = <EV_ACT_ASSERTED>; + wakeup-source; + }; + + switch-dock-hall-sensor { + label = "Lid"; + gpios = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_LOW>; + linux,input-type = <EV_SW>; + linux,code = <SW_LID>; + debounce-interval = <500>; + wakeup-event-action = <EV_ACT_ASSERTED>; + wakeup-source; + }; + }; + i2cmux { compatible = "i2c-mux-pinctrl"; #address-cells = <1>; @@ -1112,6 +1112,11 @@ }; }; + opp-table-emc { + /delete-node/ opp-666000000; + /delete-node/ opp-760000000; + }; + vdd_5v0_sys: regulator-5v0 { compatible = "regulator-fixed"; regulator-name = "vdd_5v0"; @@ -1283,8 +1288,3 @@ power-off-delay-us = <200>; }; }; - -&emc_icc_dvfs_opp_table { - /delete-node/ opp-666000000; - /delete-node/ opp-760000000; -}; diff --git a/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts index cb1190b77db3..612f4e54cb20 100644 --- a/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts @@ -143,6 +143,24 @@ status = "okay"; }; + /* SPI4: Colibri SSP */ + spi@7000da00 { + status = "okay"; + spi-max-frequency = <25000000>; + + can@0 { + compatible = "microchip,mcp2515"; + reg = <0>; + clocks = <&clk16m>; + interrupt-parent = <&gpio>; + /* CAN_INT */ + interrupts = <TEGRA_GPIO(A, 0) IRQ_TYPE_EDGE_FALLING>; + spi-max-frequency = <10000000>; + vdd-supply = <®_3v3>; + xceiver-supply = <®_5v0>; + }; + }; + /* EHCI instance 0: USB1_DP/N -> USBC_P/N */ usb@c5000000 { status = "okay"; @@ -164,24 +182,6 @@ vbus-supply = <®_usbh_vbus>; }; - /* SPI4: Colibri SSP */ - spi@7000da00 { - status = "okay"; - spi-max-frequency = <25000000>; - - can@0 { - compatible = "microchip,mcp2515"; - reg = <0>; - clocks = <&clk16m>; - interrupt-parent = <&gpio>; - /* CAN_INT */ - interrupts = <TEGRA_GPIO(A, 0) IRQ_TYPE_EDGE_FALLING>; - spi-max-frequency = <10000000>; - vdd-supply = <®_3v3>; - xceiver-supply = <®_5v0>; - }; - }; - /* SD/MMC */ mmc@c8000600 { status = "okay"; @@ -200,7 +200,7 @@ pwms = <&pwm 0 5000000>; /* PWM<A> */ }; - clk16m: osc3 { + clk16m: clock-osc3 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <16000000>; diff --git a/arch/arm/boot/dts/tegra20-colibri-iris.dts b/arch/arm/boot/dts/tegra20-colibri-iris.dts index 53487cc21513..25a9f5dfe62d 100644 --- a/arch/arm/boot/dts/tegra20-colibri-iris.dts +++ b/arch/arm/boot/dts/tegra20-colibri-iris.dts @@ -143,6 +143,12 @@ status = "okay"; }; + /* SPI4: Colibri SSP */ + spi@7000da00 { + status = "okay"; + spi-max-frequency = <25000000>; + }; + /* EHCI instance 0: USB1_DP/N -> USBC_P/N */ usb@c5000000 { status = "okay"; @@ -164,12 +170,6 @@ vbus-supply = <®_usbh_vbus>; }; - /* SPI4: Colibri SSP */ - spi@7000da00 { - status = "okay"; - spi-max-frequency = <25000000>; - }; - /* SD/MMC */ mmc@c8000600 { status = "okay"; diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index 8ebd8afc857d..0e03910abbe6 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -27,6 +27,31 @@ }; }; + gpio@6000d000 { + lan-reset-n-hog { + gpio-hog; + gpios = <TEGRA_GPIO(V, 4) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "LAN_RESET#"; + }; + + /* Tri-stating GMI_WR_N on SODIMM pin 99 nPWE */ + npwe-hog { + gpio-hog; + gpios = <TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "Tri-state nPWE"; + }; + + /* Not tri-stating GMI_WR_N on SODIMM pin 93 RDnWR */ + rdnwr-hog { + gpio-hog; + gpios = <TEGRA_GPIO(T, 6) GPIO_ACTIVE_HIGH>; + output-low; + line-name = "Not tri-state RDnWR"; + }; + }; + pinmux@70000014 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -705,12 +730,16 @@ vbus-supply = <®_lan_v_bus>; }; - clk32k_in: xtal3 { + clk32k_in: clock-xtal3 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; }; + opp-table-emc { + /delete-node/ opp-760000000; + }; + reg_lan_v_bus: regulator-lan-v-bus { compatible = "regulator-fixed"; regulator-name = "LAN_V_BUS"; @@ -745,32 +774,3 @@ clock-names = "pll_a", "pll_a_out0", "mclk"; }; }; - -&emc_icc_dvfs_opp_table { - /delete-node/ opp-760000000; -}; - -&gpio { - lan-reset-n-hog { - gpio-hog; - gpios = <TEGRA_GPIO(V, 4) GPIO_ACTIVE_HIGH>; - output-high; - line-name = "LAN_RESET#"; - }; - - /* Tri-stating GMI_WR_N on SODIMM pin 99 nPWE */ - npwe-hog { - gpio-hog; - gpios = <TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>; - output-high; - line-name = "Tri-state nPWE"; - }; - - /* Not tri-stating GMI_WR_N on SODIMM pin 93 RDnWR */ - rdnwr-hog { - gpio-hog; - gpios = <TEGRA_GPIO(T, 6) GPIO_ACTIVE_HIGH>; - output-low; - line-name = "Not tri-state RDnWR"; - }; -}; diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts index f144487c5da3..8c657182fff3 100644 --- a/arch/arm/boot/dts/tegra20-medcom-wide.dts +++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts @@ -15,10 +15,6 @@ stdout-path = "serial0:115200n8"; }; - pwm@7000a000 { - status = "okay"; - }; - host1x@50000000 { dc@54200000 { rgb { @@ -28,6 +24,10 @@ }; }; + pwm@7000a000 { + status = "okay"; + }; + i2c@7000c000 { wm8903: wm8903@1a { compatible = "wlf,wm8903"; diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index 48fe628c6d87..e995f428dc2e 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -323,53 +323,6 @@ reset-names = "i2c"; }; - memory-controller@7000f400 { - nvidia,use-ram-code; - - emc-tables@0 { - nvidia,ram-code = <0x0>; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - emc-table@166500 { - reg = <166500>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <166500>; - nvidia,emc-registers = <0x0000000a 0x00000016 - 0x00000008 0x00000003 0x00000004 0x00000004 - 0x00000002 0x0000000c 0x00000003 0x00000003 - 0x00000002 0x00000001 0x00000004 0x00000005 - 0x00000004 0x00000009 0x0000000d 0x000004df - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000003 0x00000001 0x0000000a 0x000000c8 - 0x00000003 0x00000006 0x00000004 0x00000008 - 0x00000002 0x00000000 0x00000000 0x00000002 - 0x00000000 0x00000000 0x00000083 0xe03b0323 - 0x007fe010 0x00001414 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - - emc-table@333000 { - reg = <333000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <333000>; - nvidia,emc-registers = <0x00000018 0x00000033 - 0x00000012 0x00000004 0x00000004 0x00000005 - 0x00000003 0x0000000c 0x00000006 0x00000006 - 0x00000003 0x00000001 0x00000004 0x00000005 - 0x00000004 0x00000009 0x0000000d 0x00000bff - 0x00000000 0x00000003 0x00000003 0x00000006 - 0x00000006 0x00000001 0x00000011 0x000000c8 - 0x00000003 0x0000000e 0x00000007 0x00000008 - 0x00000002 0x00000000 0x00000000 0x00000002 - 0x00000000 0x00000000 0x00000083 0xf0440303 - 0x007fe010 0x00001414 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - }; - }; - i2c@7000d000 { status = "okay"; clock-frequency = <400000>; @@ -532,6 +485,53 @@ core-supply = <&core_vdd_reg>; }; + memory-controller@7000f400 { + nvidia,use-ram-code; + + emc-tables@0 { + nvidia,ram-code = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + emc-table@166500 { + reg = <166500>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <166500>; + nvidia,emc-registers = <0x0000000a 0x00000016 + 0x00000008 0x00000003 0x00000004 0x00000004 + 0x00000002 0x0000000c 0x00000003 0x00000003 + 0x00000002 0x00000001 0x00000004 0x00000005 + 0x00000004 0x00000009 0x0000000d 0x000004df + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000003 0x00000001 0x0000000a 0x000000c8 + 0x00000003 0x00000006 0x00000004 0x00000008 + 0x00000002 0x00000000 0x00000000 0x00000002 + 0x00000000 0x00000000 0x00000083 0xe03b0323 + 0x007fe010 0x00001414 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@333000 { + reg = <333000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <333000>; + nvidia,emc-registers = <0x00000018 0x00000033 + 0x00000012 0x00000004 0x00000004 0x00000005 + 0x00000003 0x0000000c 0x00000006 0x00000006 + 0x00000003 0x00000001 0x00000004 0x00000005 + 0x00000004 0x00000009 0x0000000d 0x00000bff + 0x00000000 0x00000003 0x00000003 0x00000006 + 0x00000006 0x00000001 0x00000011 0x000000c8 + 0x00000003 0x0000000e 0x00000007 0x00000008 + 0x00000002 0x00000000 0x00000000 0x00000002 + 0x00000000 0x00000000 0x00000083 0xf0440303 + 0x007fe010 0x00001414 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + }; + }; + usb@c5000000 { compatible = "nvidia,tegra20-udc"; status = "okay"; @@ -593,6 +593,20 @@ #clock-cells = <0>; }; + cpus { + cpu0: cpu@0 { + cpu-supply = <&cpu_vdd_reg>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + + cpu1: cpu@1 { + cpu-supply = <&cpu_vdd_reg>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + }; + gpio-keys { compatible = "gpio-keys"; @@ -614,6 +628,10 @@ }; }; + opp-table-emc { + /delete-node/ opp-760000000; + }; + panel: panel { compatible = "samsung,ltn101nt05"; @@ -668,20 +686,6 @@ clock-names = "pll_a", "pll_a_out0", "mclk"; }; - cpus { - cpu0: cpu@0 { - cpu-supply = <&cpu_vdd_reg>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - cpu-supply = <&cpu_vdd_reg>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - }; - }; - thermal-zones { cpu-thermal { polling-delay-passive = <500>; /* milliseconds */ @@ -715,7 +719,3 @@ }; }; }; - -&emc_icc_dvfs_opp_table { - /delete-node/ opp-760000000; -}; diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index ab33ff67fdb9..bd4ff8b40b20 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -296,25 +296,25 @@ }; }; - state_i2cmux_pta: pinmux-i2cmux-pta { + state_i2cmux_idle: pinmux-i2cmux-idle { ddc { nvidia,pins = "ddc"; nvidia,function = "rsvd4"; }; pta { nvidia,pins = "pta"; - nvidia,function = "i2c2"; + nvidia,function = "rsvd4"; }; }; - state_i2cmux_idle: pinmux-i2cmux-idle { + state_i2cmux_pta: pinmux-i2cmux-pta { ddc { nvidia,pins = "ddc"; nvidia,function = "rsvd4"; }; pta { nvidia,pins = "pta"; - nvidia,function = "rsvd4"; + nvidia,function = "i2c2"; }; }; }; @@ -370,38 +370,6 @@ clock-frequency = <100000>; }; - i2cmux { - compatible = "i2c-mux-pinctrl"; - #address-cells = <1>; - #size-cells = <0>; - - i2c-parent = <&{/i2c@7000c400}>; - - pinctrl-names = "ddc", "pta", "idle"; - pinctrl-0 = <&state_i2cmux_ddc>; - pinctrl-1 = <&state_i2cmux_pta>; - pinctrl-2 = <&state_i2cmux_idle>; - - hdmi_ddc: i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - lvds_ddc: i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - smart-battery@b { - compatible = "ti,bq20z75", "sbs,sbs-battery"; - reg = <0xb>; - sbs,i2c-retry-count = <2>; - sbs,poll-retry-count = <10>; - }; - }; - }; - i2c@7000c500 { status = "okay"; clock-frequency = <400000>; @@ -817,6 +785,38 @@ }; }; + i2cmux { + compatible = "i2c-mux-pinctrl"; + #address-cells = <1>; + #size-cells = <0>; + + i2c-parent = <&{/i2c@7000c400}>; + + pinctrl-names = "ddc", "pta", "idle"; + pinctrl-0 = <&state_i2cmux_ddc>; + pinctrl-1 = <&state_i2cmux_pta>; + pinctrl-2 = <&state_i2cmux_idle>; + + hdmi_ddc: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + lvds_ddc: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + smart-battery@b { + compatible = "ti,bq20z75", "sbs,sbs-battery"; + reg = <0xb>; + sbs,i2c-retry-count = <2>; + sbs,poll-retry-count = <10>; + }; + }; + }; + panel: panel { compatible = "chunghwa,claa101wa01a"; diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi index 980272ad59a4..ddb84e4a9f8b 100644 --- a/arch/arm/boot/dts/tegra20-tamonten.dtsi +++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi @@ -260,25 +260,25 @@ }; }; - state_i2cmux_pta: pinmux-i2cmux-pta { + state_i2cmux_idle: pinmux-i2cmux-idle { ddc { nvidia,pins = "ddc"; nvidia,function = "rsvd4"; }; pta { nvidia,pins = "pta"; - nvidia,function = "i2c2"; + nvidia,function = "rsvd4"; }; }; - state_i2cmux_idle: pinmux-i2cmux-idle { + state_i2cmux_pta: pinmux-i2cmux-pta { ddc { nvidia,pins = "ddc"; nvidia,function = "rsvd4"; }; pta { nvidia,pins = "pta"; - nvidia,function = "rsvd4"; + nvidia,function = "i2c2"; }; }; }; @@ -301,31 +301,6 @@ status = "okay"; }; - i2cmux { - compatible = "i2c-mux-pinctrl"; - #address-cells = <1>; - #size-cells = <0>; - - i2c-parent = <&{/i2c@7000c400}>; - - pinctrl-names = "ddc", "pta", "idle"; - pinctrl-0 = <&state_i2cmux_ddc>; - pinctrl-1 = <&state_i2cmux_pta>; - pinctrl-2 = <&state_i2cmux_idle>; - - hdmi_ddc: i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - i2c@7000d000 { clock-frequency = <400000>; status = "okay"; @@ -509,6 +484,31 @@ #clock-cells = <0>; }; + i2cmux { + compatible = "i2c-mux-pinctrl"; + #address-cells = <1>; + #size-cells = <0>; + + i2c-parent = <&{/i2c@7000c400}>; + + pinctrl-names = "ddc", "pta", "idle"; + pinctrl-0 = <&state_i2cmux_ddc>; + pinctrl-1 = <&state_i2cmux_pta>; + pinctrl-2 = <&state_i2cmux_idle>; + + hdmi_ddc: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + pci_vdd_reg: regulator-1v05 { compatible = "regulator-fixed"; regulator-name = "vdd_1v05"; diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index dc51835423a9..1944121e2dd6 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts @@ -385,6 +385,16 @@ #clock-cells = <0>; }; + cpus { + cpu0: cpu@0 { + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@1 { + operating-points-v2 = <&cpu0_opp_table>; + }; + }; + gpio-keys { compatible = "gpio-keys"; @@ -462,14 +472,4 @@ <&tegra_car TEGRA20_CLK_CDEV1>; clock-names = "pll_a", "pll_a_out0", "mclk"; }; - - cpus { - cpu0: cpu@0 { - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu@1 { - operating-points-v2 = <&cpu0_opp_table>; - }; - }; }; diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index 2d7bb442d6b6..433575a6ad38 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -295,25 +295,25 @@ }; }; - state_i2cmux_pta: pinmux-i2cmux-pta { + state_i2cmux_idle: pinmux-i2cmux-idle { ddc { nvidia,pins = "ddc"; nvidia,function = "rsvd4"; }; pta { nvidia,pins = "pta"; - nvidia,function = "i2c2"; + nvidia,function = "rsvd4"; }; }; - state_i2cmux_idle: pinmux-i2cmux-idle { + state_i2cmux_pta: pinmux-i2cmux-pta { ddc { nvidia,pins = "ddc"; nvidia,function = "rsvd4"; }; pta { nvidia,pins = "pta"; - nvidia,function = "rsvd4"; + nvidia,function = "i2c2"; }; }; }; @@ -362,31 +362,6 @@ clock-frequency = <100000>; }; - i2cmux { - compatible = "i2c-mux-pinctrl"; - #address-cells = <1>; - #size-cells = <0>; - - i2c-parent = <&{/i2c@7000c400}>; - - pinctrl-names = "ddc", "pta", "idle"; - pinctrl-0 = <&state_i2cmux_ddc>; - pinctrl-1 = <&state_i2cmux_pta>; - pinctrl-2 = <&state_i2cmux_idle>; - - hdmi_ddc: i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - lvds_ddc: i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - i2c@7000c500 { status = "okay"; clock-frequency = <400000>; @@ -636,6 +611,31 @@ }; }; + i2cmux { + compatible = "i2c-mux-pinctrl"; + #address-cells = <1>; + #size-cells = <0>; + + i2c-parent = <&{/i2c@7000c400}>; + + pinctrl-names = "ddc", "pta", "idle"; + pinctrl-0 = <&state_i2cmux_ddc>; + pinctrl-1 = <&state_i2cmux_pta>; + pinctrl-2 = <&state_i2cmux_idle>; + + hdmi_ddc: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + lvds_ddc: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + panel: panel { compatible = "chunghwa,claa101wa01a"; diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 62bf0b306472..4177d04265d8 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -356,12 +356,6 @@ operating-points-v2 = <&vde_dvfs_opp_table>; }; - apbmisc@70000800 { - compatible = "nvidia,tegra20-apbmisc"; - reg = <0x70000800 0x64>, /* Chip revision */ - <0x70000008 0x04>; /* Strapping options */ - }; - pinmux: pinmux@70000014 { compatible = "nvidia,tegra20-pinmux"; reg = <0x70000014 0x10>, /* Tri-state registers */ @@ -370,6 +364,12 @@ <0x70000868 0xa8>; /* Pad control registers */ }; + apbmisc@70000800 { + compatible = "nvidia,tegra20-apbmisc"; + reg = <0x70000800 0x64>, /* Chip revision */ + <0x70000008 0x04>; /* Strapping options */ + }; + das@70000c00 { compatible = "nvidia,tegra20-das"; reg = <0x70000c00 0x80>; @@ -542,13 +542,6 @@ status = "disabled"; }; - rtc@7000e000 { - compatible = "nvidia,tegra20-rtc"; - reg = <0x7000e000 0x100>; - interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&tegra_car TEGRA20_CLK_RTC>; - }; - i2c@7000c000 { compatible = "nvidia,tegra20-i2c"; reg = <0x7000c000 0x100>; @@ -683,6 +676,13 @@ status = "disabled"; }; + rtc@7000e000 { + compatible = "nvidia,tegra20-rtc"; + reg = <0x7000e000 0x100>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA20_CLK_RTC>; + }; + kbc@7000e200 { compatible = "nvidia,tegra20-kbc"; reg = <0x7000e200 0x100>; @@ -706,6 +706,16 @@ }; powergates { + pd_mpe: mpe { + clocks = <&tegra_car TEGRA20_CLK_MPE>; + resets = <&mc TEGRA20_MC_RESET_MPEA>, + <&mc TEGRA20_MC_RESET_MPEB>, + <&mc TEGRA20_MC_RESET_MPEC>, + <&tegra_car TEGRA20_CLK_MPE>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + pd_3d: td { clocks = <&tegra_car TEGRA20_CLK_GR3D>; resets = <&mc TEGRA20_MC_RESET_3D>, @@ -714,6 +724,14 @@ #power-domain-cells = <0>; }; + pd_vde: vdec { + clocks = <&tegra_car TEGRA20_CLK_VDE>; + resets = <&mc TEGRA20_MC_RESET_VDE>, + <&tegra_car TEGRA20_CLK_VDE>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + pd_venc: venc { clocks = <&tegra_car TEGRA20_CLK_ISP>, <&tegra_car TEGRA20_CLK_VI>, @@ -726,24 +744,6 @@ power-domains = <&pd_core>; #power-domain-cells = <0>; }; - - pd_vde: vdec { - clocks = <&tegra_car TEGRA20_CLK_VDE>; - resets = <&mc TEGRA20_MC_RESET_VDE>, - <&tegra_car TEGRA20_CLK_VDE>; - power-domains = <&pd_core>; - #power-domain-cells = <0>; - }; - - pd_mpe: mpe { - clocks = <&tegra_car TEGRA20_CLK_MPE>; - resets = <&mc TEGRA20_MC_RESET_MPEA>, - <&mc TEGRA20_MC_RESET_MPEB>, - <&mc TEGRA20_MC_RESET_MPEC>, - <&tegra_car TEGRA20_CLK_MPE>; - power-domains = <&pd_core>; - #power-domain-cells = <0>; - }; }; }; @@ -1049,13 +1049,13 @@ simple-audio-card,dai-link@0 { reg = <0>; - cpu { - sound-dai = <&tegra_spdif>; - }; - codec { sound-dai = <&tegra_hdmi>; }; + + cpu { + sound-dai = <&tegra_spdif>; + }; }; }; }; diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts index ad968ff968d7..842b5faba285 100644 --- a/arch/arm/boot/dts/tegra30-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts @@ -47,6 +47,16 @@ }; }; + gpio@6000d000 { + /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ + pex-perst-n-hog { + gpio-hog; + gpios = <TEGRA_GPIO(S, 7) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "PEX_PERST_N"; + }; + }; + /* Apalis UART1 */ serial@70006000 { status = "okay"; @@ -236,13 +246,3 @@ vin-supply = <®_5v0>; }; }; - -&gpio { - /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ - pex-perst-n-hog { - gpio-hog; - gpios = <TEGRA_GPIO(S, 7) GPIO_ACTIVE_HIGH>; - output-high; - line-name = "PEX_PERST_N"; - }; -}; diff --git a/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts b/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts index c172fdb5e1ae..ca277bf1df78 100644 --- a/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts +++ b/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts @@ -48,6 +48,16 @@ }; }; + gpio@6000d000 { + /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ + pex-perst-n-hog { + gpio-hog; + gpios = <TEGRA_GPIO(S, 7) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "PEX_PERST_N"; + }; + }; + /* Apalis UART1 */ serial@70006000 { status = "okay"; @@ -254,13 +264,3 @@ vin-supply = <&vddio_sdmmc_1v8_reg>; }; }; - -&gpio { - /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ - pex-perst-n-hog { - gpio-hog; - gpios = <TEGRA_GPIO(S, 7) GPIO_ACTIVE_HIGH>; - output-high; - line-name = "PEX_PERST_N"; - }; -}; diff --git a/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi b/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi index a1bcd67fa505..a4b7fe5c3d23 100644 --- a/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi @@ -1007,6 +1007,12 @@ /* ADC converstion time: 80 clocks */ st,sample-time = <4>; + stmpe_adc { + compatible = "st,stmpe-adc"; + /* forbid to use ADC channels 3-0 (touch) */ + st,norequest-mask = <0x0F>; + }; + stmpe_touchscreen { compatible = "st,stmpe-ts"; /* 8 sample average control */ @@ -1023,12 +1029,6 @@ /* 5 ms touch detect interrupt delay */ st,touch-det-delay = <5>; }; - - stmpe_adc { - compatible = "st,stmpe-adc"; - /* forbid to use ADC channels 3-0 (touch) */ - st,norequest-mask = <0x0F>; - }; }; /* @@ -1122,16 +1122,16 @@ mmc-ddr-1_8v; }; - clk32k_in: xtal1 { + clk16m: clock-osc4 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <32768>; + clock-frequency = <16000000>; }; - clk16m: osc4 { + clk32k_in: clock-xtal1 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <16000000>; + clock-frequency = <32768>; }; reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll { diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index 99d7dad72d29..d73103884000 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -990,6 +990,12 @@ /* ADC converstion time: 80 clocks */ st,sample-time = <4>; + stmpe_adc { + compatible = "st,stmpe-adc"; + /* forbid to use ADC channels 3-0 (touch) */ + st,norequest-mask = <0x0F>; + }; + stmpe_touchscreen { compatible = "st,stmpe-ts"; /* 8 sample average control */ @@ -1006,12 +1012,6 @@ /* 5 ms touch detect interrupt delay */ st,touch-det-delay = <5>; }; - - stmpe_adc { - compatible = "st,stmpe-adc"; - /* forbid to use ADC channels 3-0 (touch) */ - st,norequest-mask = <0x0F>; - }; }; /* @@ -1105,16 +1105,16 @@ mmc-ddr-1_8v; }; - clk32k_in: xtal1 { + clk16m: clock-osc4 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <32768>; + clock-frequency = <16000000>; }; - clk16m: osc4 { + clk32k_in: clock-xtal1 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <16000000>; + clock-frequency = <32768>; }; reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll { diff --git a/arch/arm/boot/dts/tegra30-asus-lvds-display.dtsi b/arch/arm/boot/dts/tegra30-asus-lvds-display.dtsi index a047abfa6369..bae09d82594d 100644 --- a/arch/arm/boot/dts/tegra30-asus-lvds-display.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-lvds-display.dtsi @@ -2,6 +2,8 @@ /* This dtsi file describes parts common for Asus T30 devices with a LVDS panel. */ +#include <dt-bindings/gpio/tegra-gpio.h> + / { host1x@50000000 { lcd: dc@54200000 { diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi index ee683c5a9c62..c0062353c1f1 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi @@ -29,6 +29,14 @@ */ chosen {}; + firmware { + trusted-foundations { + compatible = "tlm,trusted-foundations"; + tlm,version-major = <0x0>; + tlm,version-minor = <0x0>; + }; + }; + memory@80000000 { reg = <0x80000000 0x40000000>; }; @@ -61,6 +69,12 @@ }; gpio@6000d000 { + init-low-power-mode-hog { + gpio-hog; + gpios = <TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; + input; + }; + init-mode-hog { gpio-hog; gpios = <TEGRA_GPIO(DD, 7) GPIO_ACTIVE_HIGH>, @@ -68,12 +82,6 @@ <TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; output-low; }; - - init-low-power-mode-hog { - gpio-hog; - gpios = <TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; - input; - }; }; pinmux@70000868 { @@ -977,17 +985,6 @@ }; }; - brcm_wifi_pwrseq: wifi-pwrseq { - compatible = "mmc-pwrseq-simple"; - - clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; - clock-names = "ext_clock"; - - reset-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_LOW>; - post-power-on-delay-ms = <300>; - power-off-delay-us = <300>; - }; - sdmmc3: mmc@78000400 { status = "okay"; @@ -1113,27 +1110,9 @@ /delete-property/ ddc-i2c-bus; }; - firmware { - trusted-foundations { - compatible = "tlm,trusted-foundations"; - tlm,version-major = <0x0>; - tlm,version-minor = <0x0>; - }; - }; - gpio-keys { compatible = "gpio-keys"; - switch-hall-sensor { - label = "Lid"; - gpios = <&gpio TEGRA_GPIO(S, 6) GPIO_ACTIVE_LOW>; - linux,input-type = <EV_SW>; - linux,code = <SW_LID>; - debounce-interval = <500>; - wakeup-event-action = <EV_ACT_DEASSERTED>; - wakeup-source; - }; - key-power { label = "Power"; gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; @@ -1143,6 +1122,15 @@ wakeup-source; }; + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEDOWN>; + debounce-interval = <10>; + wakeup-event-action = <EV_ACT_ASSERTED>; + wakeup-source; + }; + key-volume-up { label = "Volume Up"; gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>; @@ -1152,16 +1140,28 @@ wakeup-source; }; - key-volume-down { - label = "Volume Down"; - gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>; - linux,code = <KEY_VOLUMEDOWN>; - debounce-interval = <10>; - wakeup-event-action = <EV_ACT_ASSERTED>; + switch-hall-sensor { + label = "Lid"; + gpios = <&gpio TEGRA_GPIO(S, 6) GPIO_ACTIVE_LOW>; + linux,input-type = <EV_SW>; + linux,code = <SW_LID>; + debounce-interval = <500>; + wakeup-event-action = <EV_ACT_DEASSERTED>; wakeup-source; }; }; + brcm_wifi_pwrseq: pwrseq-wifi { + compatible = "mmc-pwrseq-simple"; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "ext_clock"; + + reset-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <300>; + power-off-delay-us = <300>; + }; + vdd_5v0_sys: regulator-5v0 { compatible = "regulator-fixed"; regulator-name = "vdd_5v0"; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi index cd28e8782f7d..694c7fe37eb8 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi @@ -22,13 +22,6 @@ pinctrl-names = "default"; pinctrl-0 = <&max77620_default>; - max77620_default: pinmux { - gpio4 { - pins = "gpio4"; - function = "32k-out1"; - }; - }; - cpu-pwr-req-hog { gpio-hog; gpios = <6 GPIO_ACTIVE_HIGH>; @@ -49,6 +42,13 @@ }; }; + max77620_default: pinmux { + gpio4 { + pins = "gpio4"; + function = "32k-out1"; + }; + }; + regulators { in-sd0-supply = <&vdd_5v0_sys>; in-sd1-supply = <&vdd_5v0_sys>; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-memory-timings.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-memory-timings.dtsi index 6c229e1d67e7..8944a4a5a8d7 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-memory-timings.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-memory-timings.dtsi @@ -1562,16 +1562,16 @@ }; }; }; -}; -&emc_icc_dvfs_opp_table { - /delete-node/ opp-750000000-1300; - /delete-node/ opp-800000000-1300; - /delete-node/ opp-900000000-1350; -}; + opp-table-actmon { + /delete-node/ opp-750000000; + /delete-node/ opp-800000000; + /delete-node/ opp-900000000; + }; -&emc_bw_dfs_opp_table { - /delete-node/ opp-750000000; - /delete-node/ opp-800000000; - /delete-node/ opp-900000000; + opp-table-emc { + /delete-node/ opp-750000000-1300; + /delete-node/ opp-800000000-1300; + /delete-node/ opp-900000000-1350; + }; }; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper.dtsi index 564cfcde21a9..c19a0419112a 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper.dtsi @@ -6,20 +6,6 @@ / { compatible = "asus,grouper", "nvidia,tegra30"; - display-panel { - panel-timing { - clock-frequency = <68000000>; - hactive = <800>; - vactive = <1280>; - hfront-porch = <24>; - hback-porch = <32>; - hsync-len = <24>; - vsync-len = <1>; - vfront-porch = <5>; - vback-porch = <32>; - }; - }; - pinmux@70000868 { state_default: pinmux { lcd_dc1_pd2 { @@ -145,4 +131,18 @@ firmware-gpios = <&gpio TEGRA_GPIO(R, 3) GPIO_ACTIVE_HIGH>; }; }; + + display-panel { + panel-timing { + clock-frequency = <68000000>; + hactive = <800>; + vactive = <1280>; + hfront-porch = <24>; + hback-porch = <32>; + hsync-len = <24>; + vsync-len = <1>; + vfront-porch = <5>; + vback-porch = <32>; + }; + }; }; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi index 1b241f0542b8..94c80134574e 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi @@ -6,22 +6,6 @@ / { compatible = "asus,tilapia", "asus,grouper", "nvidia,tegra30"; - display-panel { - enable-gpios = <&gpio TEGRA_GPIO(V, 6) GPIO_ACTIVE_HIGH>; - - panel-timing { - clock-frequency = <81750000>; - hactive = <800>; - vactive = <1280>; - hfront-porch = <64>; - hback-porch = <128>; - hsync-len = <64>; - vsync-len = <1>; - vfront-porch = <5>; - vback-porch = <2>; - }; - }; - gpio@6000d000 { init-mode-3g-hog { gpio-hog; @@ -230,4 +214,20 @@ firmware-gpios = <&gpio TEGRA_GPIO(P, 3) GPIO_ACTIVE_HIGH>; }; }; + + display-panel { + enable-gpios = <&gpio TEGRA_GPIO(V, 6) GPIO_ACTIVE_HIGH>; + + panel-timing { + clock-frequency = <81750000>; + hactive = <800>; + vactive = <1280>; + hfront-porch = <64>; + hback-porch = <128>; + hsync-len = <64>; + vsync-len = <1>; + vfront-porch = <5>; + vback-porch = <2>; + }; + }; }; diff --git a/arch/arm/boot/dts/tegra30-asus-tf201.dts b/arch/arm/boot/dts/tegra30-asus-tf201.dts index 315c6dc068c5..3c2b9e93e028 100644 --- a/arch/arm/boot/dts/tegra30-asus-tf201.dts +++ b/arch/arm/boot/dts/tegra30-asus-tf201.dts @@ -605,23 +605,23 @@ enable-gpios = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>; vcc-supply = <&vdd_3v3_sys>; }; -}; -&emc_icc_dvfs_opp_table { - /delete-node/ opp-533000000-1200; - /delete-node/ opp-625000000-1200; - /delete-node/ opp-625000000-1250; - /delete-node/ opp-667000000-1200; - /delete-node/ opp-750000000-1300; - /delete-node/ opp-800000000-1300; - /delete-node/ opp-900000000-1350; -}; + opp-table-actmon { + /delete-node/ opp-533000000; + /delete-node/ opp-625000000; + /delete-node/ opp-667000000; + /delete-node/ opp-750000000; + /delete-node/ opp-800000000; + /delete-node/ opp-900000000; + }; -&emc_bw_dfs_opp_table { - /delete-node/ opp-533000000; - /delete-node/ opp-625000000; - /delete-node/ opp-667000000; - /delete-node/ opp-750000000; - /delete-node/ opp-800000000; - /delete-node/ opp-900000000; + opp-table-emc { + /delete-node/ opp-533000000-1200; + /delete-node/ opp-625000000-1200; + /delete-node/ opp-625000000-1250; + /delete-node/ opp-667000000-1200; + /delete-node/ opp-750000000-1300; + /delete-node/ opp-800000000-1300; + /delete-node/ opp-900000000-1350; + }; }; diff --git a/arch/arm/boot/dts/tegra30-asus-tf300t.dts b/arch/arm/boot/dts/tegra30-asus-tf300t.dts index f47434871a5c..506ae3626731 100644 --- a/arch/arm/boot/dts/tegra30-asus-tf300t.dts +++ b/arch/arm/boot/dts/tegra30-asus-tf300t.dts @@ -999,6 +999,18 @@ compatible = "innolux,g101ice-l01"; }; + opp-table-emc { + /delete-node/ opp-750000000-1300; + /delete-node/ opp-800000000-1300; + /delete-node/ opp-900000000-1350; + }; + + opp-table-actmon { + /delete-node/ opp-750000000; + /delete-node/ opp-800000000; + /delete-node/ opp-900000000; + }; + sound { compatible = "asus,tegra-audio-wm8903-tf300t", "nvidia,tegra-audio-wm8903"; @@ -1020,15 +1032,3 @@ nvidia,headset; }; }; - -&emc_icc_dvfs_opp_table { - /delete-node/ opp-750000000-1300; - /delete-node/ opp-800000000-1300; - /delete-node/ opp-900000000-1350; -}; - -&emc_bw_dfs_opp_table { - /delete-node/ opp-750000000; - /delete-node/ opp-800000000; - /delete-node/ opp-900000000; -}; diff --git a/arch/arm/boot/dts/tegra30-asus-tf300tg.dts b/arch/arm/boot/dts/tegra30-asus-tf300tg.dts index 96345f821c3d..573deeafb7ba 100644 --- a/arch/arm/boot/dts/tegra30-asus-tf300tg.dts +++ b/arch/arm/boot/dts/tegra30-asus-tf300tg.dts @@ -1072,16 +1072,16 @@ display-panel { compatible = "innolux,g101ice-l01"; }; -}; -&emc_icc_dvfs_opp_table { - /delete-node/ opp-750000000-1300; - /delete-node/ opp-800000000-1300; - /delete-node/ opp-900000000-1350; -}; + opp-table-emc { + /delete-node/ opp-750000000-1300; + /delete-node/ opp-800000000-1300; + /delete-node/ opp-900000000-1350; + }; -&emc_bw_dfs_opp_table { - /delete-node/ opp-750000000; - /delete-node/ opp-800000000; - /delete-node/ opp-900000000; + opp-table-actmon { + /delete-node/ opp-750000000; + /delete-node/ opp-800000000; + /delete-node/ opp-900000000; + }; }; diff --git a/arch/arm/boot/dts/tegra30-asus-tf700t.dts b/arch/arm/boot/dts/tegra30-asus-tf700t.dts index 1a331dec3cfe..e7fe8c7a7435 100644 --- a/arch/arm/boot/dts/tegra30-asus-tf700t.dts +++ b/arch/arm/boot/dts/tegra30-asus-tf700t.dts @@ -758,6 +758,24 @@ vddio-supply = <&vdd_1v8_vio>; vddmipi-supply = <&vdd_1v2_mipi>; + /* + * Panasonic VVX10F004B00 or HYDIS HV101WU1-1E1 + * LCD SuperIPS+ Full HD panel. + */ + panel@1 { + compatible = "panasonic,vvx10f004b00"; + reg = <1>; + + power-supply = <&vdd_pnl>; + backlight = <&backlight>; + + port { + panel_input: endpoint { + remote-endpoint = <&bridge_output>; + }; + }; + }; + ports { #address-cells = <1>; #size-cells = <0>; @@ -779,28 +797,18 @@ }; }; }; - - /* - * Panasonic VVX10F004B00 or HYDIS HV101WU1-1E1 - * LCD SuperIPS+ Full HD panel. - */ - panel@1 { - compatible = "panasonic,vvx10f004b00"; - reg = <1>; - - power-supply = <&vdd_pnl>; - backlight = <&backlight>; - - port { - panel_input: endpoint { - remote-endpoint = <&bridge_output>; - }; - }; - }; }; }; }; + opp-table-actmon { + /delete-node/ opp-900000000; + }; + + opp-table-emc { + /delete-node/ opp-900000000-1350; + }; + vdd_1v2_mipi: regulator-mipi { compatible = "regulator-fixed"; regulator-name = "tc358768_1v2_vdd"; @@ -813,11 +821,3 @@ vin-supply = <&vdd_3v3_sys>; }; }; - -&emc_icc_dvfs_opp_table { - /delete-node/ opp-900000000-1350; -}; - -&emc_bw_dfs_opp_table { - /delete-node/ opp-900000000; -}; diff --git a/arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi b/arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi index 08ea9cb32d0e..1861b2de2dc3 100644 --- a/arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi @@ -33,6 +33,14 @@ */ chosen {}; + firmware { + trusted-foundations { + compatible = "tlm,trusted-foundations"; + tlm,version-major = <2>; + tlm,version-minor = <8>; + }; + }; + memory@80000000 { reg = <0x80000000 0x40000000>; }; @@ -1187,17 +1195,6 @@ status = "okay"; clock-frequency = <400000>; - nct72: temperature-sensor@4c { - compatible = "onnn,nct1008"; - reg = <0x4c>; - - interrupt-parent = <&gpio>; - interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_EDGE_FALLING>; - - vcc-supply = <&vdd_3v3_sys>; - #thermal-sensor-cells = <1>; - }; - /* Texas Instruments TPS659110 PMIC */ pmic: pmic@2d { compatible = "ti,tps65911"; @@ -1323,6 +1320,17 @@ }; }; + nct72: temperature-sensor@4c { + compatible = "onnn,nct1008"; + reg = <0x4c>; + + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_EDGE_FALLING>; + + vcc-supply = <&vdd_3v3_sys>; + #thermal-sensor-cells = <1>; + }; + vdd_core: core-regulator@60 { compatible = "ti,tps62361"; reg = <0x60>; @@ -1531,14 +1539,6 @@ }; }; - firmware { - trusted-foundations { - compatible = "tlm,trusted-foundations"; - tlm,version-major = <2>; - tlm,version-minor = <8>; - }; - }; - gpio-keys { compatible = "gpio-keys"; @@ -1551,19 +1551,19 @@ wakeup-source; }; - key-volume-up { - label = "Volume Up"; - gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>; - linux,code = <KEY_VOLUMEUP>; + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEDOWN>; debounce-interval = <10>; wakeup-event-action = <EV_ACT_ASSERTED>; wakeup-source; }; - key-volume-down { - label = "Volume Down"; - gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>; - linux,code = <KEY_VOLUMEDOWN>; + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; debounce-interval = <10>; wakeup-event-action = <EV_ACT_ASSERTED>; wakeup-source; diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index 5ad62b567d32..51769d5132ae 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -1974,6 +1974,28 @@ #clock-cells = <0>; }; + cpus { + cpu0: cpu@0 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@1 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@2 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@3 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + }; + gpio-leds { compatible = "gpio-leds"; @@ -2113,26 +2135,4 @@ assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, <&tegra_car TEGRA30_CLK_EXTERN1>; }; - - cpus { - cpu0: cpu@0 { - cpu-supply = <&vddctrl_reg>; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu@1 { - cpu-supply = <&vddctrl_reg>; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu@2 { - cpu-supply = <&vddctrl_reg>; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu@3 { - cpu-supply = <&vddctrl_reg>; - operating-points-v2 = <&cpu0_opp_table>; - }; - }; }; diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index 540530c983ff..37a9c5a0ca30 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -468,6 +468,33 @@ }; }; + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + interrupt-parent = <&pmic>; + interrupts = <2 0>; + linux,code = <KEY_POWER>; + debounce-interval = <100>; + wakeup-source; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEDOWN>; + debounce-interval = <10>; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + debounce-interval = <10>; + }; + }; + panel: panel { compatible = "chunghwa,claa101wb01"; ddc-i2c-bus = <&panelddc>; @@ -681,31 +708,4 @@ }; }; }; - - gpio-keys { - compatible = "gpio-keys"; - - key-power { - label = "Power"; - interrupt-parent = <&pmic>; - interrupts = <2 0>; - linux,code = <KEY_POWER>; - debounce-interval = <100>; - wakeup-source; - }; - - key-volume-down { - label = "Volume Down"; - gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_LOW>; - linux,code = <KEY_VOLUMEDOWN>; - debounce-interval = <10>; - }; - - key-volume-up { - label = "Volume Up"; - gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; - linux,code = <KEY_VOLUMEUP>; - debounce-interval = <10>; - }; - }; }; diff --git a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts index 8dbc15f9a9e4..36615c5fda2c 100644 --- a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts @@ -136,7 +136,7 @@ pwms = <&pwm 0 5000000>; /* PWM<A> */ }; - clk16m: osc3 { + clk16m: clock-osc3 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <16000000>; diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index 2867a138e011..ed6106f1bea1 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -20,6 +20,15 @@ }; }; + gpio: gpio@6000d000 { + lan-reset-n-hog { + gpio-hog; + gpios = <TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "LAN_RESET#"; + }; + }; + pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -864,6 +873,11 @@ st,sample-time = <4>; /* forbid to use ADC channels 3-0 (touch) */ + stmpe_adc { + compatible = "st,stmpe-adc"; + st,norequest-mask = <0x0F>; + }; + stmpe_touchscreen { compatible = "st,stmpe-ts"; /* 8 sample average control */ @@ -880,11 +894,6 @@ /* 5 ms touch detect interrupt delay */ st,touch-det-delay = <5>; }; - - stmpe_adc { - compatible = "st,stmpe-adc"; - st,norequest-mask = <0x0F>; - }; }; /* @@ -972,7 +981,7 @@ vbus-supply = <®_lan_v_bus>; }; - clk32k_in: xtal1 { + clk32k_in: clock-xtal1 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; @@ -1053,12 +1062,3 @@ <&tegra_car TEGRA30_CLK_EXTERN1>; }; }; - -&gpio { - lan-reset-n-hog { - gpio-hog; - gpios = <TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>; - output-high; - line-name = "LAN_RESET#"; - }; -}; diff --git a/arch/arm/boot/dts/tegra30-ouya.dts b/arch/arm/boot/dts/tegra30-ouya.dts index b7acea39b942..eef27c82987b 100644 --- a/arch/arm/boot/dts/tegra30-ouya.dts +++ b/arch/arm/boot/dts/tegra30-ouya.dts @@ -26,6 +26,14 @@ stdout-path = "serial0:115200n8"; }; + firmware { + trusted-foundations { + compatible = "tlm,trusted-foundations"; + tlm,version-major = <0x0>; + tlm,version-minor = <0x0>; + }; + }; + memory@80000000 { reg = <0x80000000 0x40000000>; }; @@ -2037,17 +2045,6 @@ status = "okay"; clock-frequency = <400000>; - cpu_temp: nct1008@4c { - compatible = "onnn,nct1008"; - reg = <0x4c>; - vcc-supply = <&sys_3v3_reg>; - - interrupt-parent = <&gpio>; - interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_EDGE_FALLING>; - - #thermal-sensor-cells = <1>; - }; - pmic: pmic@2d { compatible = "ti,tps65911"; reg = <0x2d>; @@ -2161,6 +2158,17 @@ }; }; + cpu_temp: nct1008@4c { + compatible = "onnn,nct1008"; + reg = <0x4c>; + vcc-supply = <&sys_3v3_reg>; + + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_EDGE_FALLING>; + + #thermal-sensor-cells = <1>; + }; + vdd_core: tps62361@60 { compatible = "ti,tps62361"; reg = <0x60>; @@ -4485,17 +4493,6 @@ status = "okay"; }; - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - - clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; - clock-names = "ext_clock"; - - reset-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>; - post-power-on-delay-ms = <300>; - power-off-delay-us = <300>; - }; - sdmmc3: mmc@78000400 { status = "okay"; @@ -4608,15 +4605,7 @@ }; }; - firmware { - trusted-foundations { - compatible = "tlm,trusted-foundations"; - tlm,version-major = <0x0>; - tlm,version-minor = <0x0>; - }; - }; - - fan: gpio_fan { + fan: fan { compatible = "gpio-fan"; gpios = <&gpio TEGRA_GPIO(J, 2) GPIO_ACTIVE_HIGH>; gpio-fan,speed-map = <0 0 @@ -4624,50 +4613,50 @@ #cooling-cells = <2>; }; - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay = <5000>; - polling-delay-passive = <5000>; + gpio-keys { + compatible = "gpio-keys"; - thermal-sensors = <&cpu_temp 1>; + key-power { + gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; + debounce-interval = <10>; + linux,code = <KEY_POWER>; + wakeup-event-action = <EV_ACT_ASSERTED>; + wakeup-source; + }; + }; - trips { - cpu_alert0: cpu-alert0 { - temperature = <50000>; - hysteresis = <10000>; - type = "active"; - }; - cpu_alert1: cpu-alert1 { - temperature = <70000>; - hysteresis = <5000>; - type = "passive"; - }; - cpu_crit: cpu-crit { - temperature = <90000>; - hysteresis = <2000>; - type = "critical"; - }; - }; + leds { + compatible = "gpio-leds"; - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu_alert1>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&actmon THERMAL_NO_LIMIT - THERMAL_NO_LIMIT>; - }; - }; + led-power { + label = "power-led"; + gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + retain-state-suspended; }; }; - vdd_12v_in: vdd_12v_in { + opp-table-actmon { + /delete-node/ opp-900000000; + }; + + opp-table-emc { + /delete-node/ opp-900000000-1350; + }; + + wifi_pwrseq: pwrseq-wifi { + compatible = "mmc-pwrseq-simple"; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "ext_clock"; + + reset-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <300>; + power-off-delay-us = <300>; + }; + + vdd_12v_in: regulator-vdd-12v-in { compatible = "regulator-fixed"; regulator-name = "vdd_12v_in"; regulator-min-microvolt = <12000000>; @@ -4675,7 +4664,7 @@ regulator-always-on; }; - sdmmc_3v3_reg: sdmmc_3v3_reg { + sdmmc_3v3_reg: regulator-sdmmc-3v3 { compatible = "regulator-fixed"; regulator-name = "sdmmc_3v3"; regulator-min-microvolt = <3300000>; @@ -4686,7 +4675,7 @@ vin-supply = <&sys_3v3_reg>; }; - vdd_fuse_3v3_reg: vdd_fuse_3v3_reg { + vdd_fuse_3v3_reg: regulator-vdd-fuse-3v3 { compatible = "regulator-fixed"; regulator-name = "vdd_fuse_3v3"; regulator-min-microvolt = <3300000>; @@ -4697,7 +4686,7 @@ regulator-always-on; }; - vdd_vid_reg: vdd_vid_reg { + vdd_vid_reg: regulator-vdd-vid { compatible = "regulator-fixed"; regulator-name = "vddio_vid"; regulator-min-microvolt = <5000000>; @@ -4708,7 +4697,7 @@ regulator-boot-on; }; - ddr_reg: ddr_reg { + ddr_reg: regulator-ddr { compatible = "regulator-fixed"; regulator-name = "vdd_ddr"; regulator-min-microvolt = <1500000>; @@ -4720,7 +4709,7 @@ vin-supply = <&vdd_12v_in>; }; - sys_3v3_reg: sys_3v3_reg { + sys_3v3_reg: regulator-sys-3v3 { compatible = "regulator-fixed"; regulator-name = "sys_3v3"; regulator-min-microvolt = <3300000>; @@ -4732,7 +4721,7 @@ vin-supply = <&vdd_12v_in>; }; - vdd_5v0_reg: vdd_5v0_reg { + vdd_5v0_reg: regulator-vdd-5v0 { compatible = "regulator-fixed"; regulator-name = "vdd_5v0"; regulator-min-microvolt = <5000000>; @@ -4744,14 +4733,14 @@ vin-supply = <&vdd_12v_in>; }; - vdd_smsc: vdd_smsc { + vdd_smsc: regulator-vdd-smsc { compatible = "regulator-fixed"; regulator-name = "vdd_smsc"; enable-active-high; gpio = <&gpio TEGRA_GPIO(DD, 5) GPIO_ACTIVE_HIGH>; }; - usb3_vbus_reg: usb3_vbus_reg { + usb3_vbus_reg: regulator-usb3-vbus { compatible = "regulator-fixed"; regulator-name = "usb3_vbus"; regulator-min-microvolt = <5000000>; @@ -4761,36 +4750,46 @@ vin-supply = <&vdd_5v0_reg>; }; - gpio-keys { - compatible = "gpio-keys"; - - key-power { - gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; - debounce-interval = <10>; - linux,code = <KEY_POWER>; - wakeup-event-action = <EV_ACT_ASSERTED>; - wakeup-source; - }; - }; + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay = <5000>; + polling-delay-passive = <5000>; + thermal-sensors = <&cpu_temp 1>; - leds { - compatible = "gpio-leds"; + trips { + cpu_alert0: cpu-alert0 { + temperature = <50000>; + hysteresis = <10000>; + type = "active"; + }; + cpu_alert1: cpu-alert1 { + temperature = <70000>; + hysteresis = <5000>; + type = "passive"; + }; + cpu_crit: cpu-crit { + temperature = <90000>; + hysteresis = <2000>; + type = "critical"; + }; + }; - led-power { - label = "power-led"; - gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - retain-state-suspended; + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu_alert1>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&actmon THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; }; }; }; - -&emc_icc_dvfs_opp_table { - /delete-node/ opp-900000000-1350; -}; - -&emc_bw_dfs_opp_table { - /delete-node/ opp-900000000; -}; diff --git a/arch/arm/boot/dts/tegra30-pegatron-chagall.dts b/arch/arm/boot/dts/tegra30-pegatron-chagall.dts index d9408a90653a..8d10eb8b48b9 100644 --- a/arch/arm/boot/dts/tegra30-pegatron-chagall.dts +++ b/arch/arm/boot/dts/tegra30-pegatron-chagall.dts @@ -37,6 +37,14 @@ */ chosen {}; + firmware { + trusted-foundations { + compatible = "tlm,trusted-foundations"; + tlm,version-major = <2>; + tlm,version-minor = <8>; + }; + }; + memory@80000000 { reg = <0x80000000 0x40000000>; }; @@ -1190,16 +1198,6 @@ status = "okay"; clock-frequency = <400000>; - light-sensor@44 { - compatible = "isil,isl29023"; - reg = <0x44>; - - interrupt-parent = <&gpio>; - interrupts = <TEGRA_GPIO(Q, 3) IRQ_TYPE_LEVEL_HIGH>; - - vcc-supply = <&vdd_3v3_sen>; - }; - /* AsahiKASEI AK8975 magnetometer sensor */ magnetometer@c { compatible = "asahi-kasei,ak8975"; @@ -1213,6 +1211,16 @@ "0", "0", "-1"; }; + light-sensor@44 { + compatible = "isil,isl29023"; + reg = <0x44>; + + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(Q, 3) IRQ_TYPE_LEVEL_HIGH>; + + vcc-supply = <&vdd_3v3_sen>; + }; + gyroscope@68 { compatible = "invensense,mpu3050"; reg = <0x68>; @@ -1259,17 +1267,6 @@ status = "okay"; clock-frequency = <400000>; - nct72: temperature-sensor@4c { - compatible = "onnn,nct1008"; - reg = <0x4c>; - - interrupt-parent = <&gpio>; - interrupts = <TEGRA_GPIO(U, 5) IRQ_TYPE_EDGE_FALLING>; - - vcc-supply = <&vdd_3v3_sys>; - #thermal-sensor-cells = <1>; - }; - /* Texas Instruments TPS659110 PMIC */ pmic: pmic@2d { compatible = "ti,tps65911"; @@ -1400,6 +1397,17 @@ }; }; + nct72: temperature-sensor@4c { + compatible = "onnn,nct1008"; + reg = <0x4c>; + + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(U, 5) IRQ_TYPE_EDGE_FALLING>; + + vcc-supply = <&vdd_3v3_sys>; + #thermal-sensor-cells = <1>; + }; + vdd_core: core-regulator@60 { compatible = "ti,tps62361"; reg = <0x60>; @@ -2506,17 +2514,6 @@ vqmmc-supply = <&vddio_usd>; /* ldo3 */ }; - brcm_wifi_pwrseq: wifi-pwrseq { - compatible = "mmc-pwrseq-simple"; - - clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; - clock-names = "ext_clock"; - - reset-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>; - post-power-on-delay-ms = <300>; - power-off-delay-us = <300>; - }; - sdmmc3: mmc@78000400 { status = "okay"; @@ -2674,14 +2671,6 @@ }; }; - firmware { - trusted-foundations { - compatible = "tlm,trusted-foundations"; - tlm,version-major = <2>; - tlm,version-minor = <8>; - }; - }; - gpio-keys { compatible = "gpio-keys"; @@ -2694,19 +2683,19 @@ wakeup-source; }; - key-volume-up { - label = "Volume Up"; - gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; - linux,code = <KEY_VOLUMEUP>; + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 1) GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEDOWN>; debounce-interval = <10>; wakeup-event-action = <EV_ACT_ASSERTED>; wakeup-source; }; - key-volume-down { - label = "Volume Down"; - gpios = <&gpio TEGRA_GPIO(Q, 1) GPIO_ACTIVE_LOW>; - linux,code = <KEY_VOLUMEDOWN>; + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; debounce-interval = <10>; wakeup-event-action = <EV_ACT_ASSERTED>; wakeup-source; @@ -2719,6 +2708,34 @@ vcc-supply = <&vdd_3v3_sys>; }; + opp-table-actmon { + /delete-node/ opp-625000000; + /delete-node/ opp-667000000; + /delete-node/ opp-750000000; + /delete-node/ opp-800000000; + /delete-node/ opp-900000000; + }; + + opp-table-emc { + /delete-node/ opp-625000000-1200; + /delete-node/ opp-625000000-1250; + /delete-node/ opp-667000000-1200; + /delete-node/ opp-750000000-1300; + /delete-node/ opp-800000000-1300; + /delete-node/ opp-900000000-1350; + }; + + brcm_wifi_pwrseq: pwrseq-wifi { + compatible = "mmc-pwrseq-simple"; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "ext_clock"; + + reset-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <300>; + power-off-delay-us = <300>; + }; + sound { compatible = "pegatron,tegra-audio-wm8903-chagall", "nvidia,tegra-audio-wm8903"; @@ -2839,20 +2856,3 @@ }; }; }; - -&emc_icc_dvfs_opp_table { - /delete-node/ opp-625000000-1200; - /delete-node/ opp-625000000-1250; - /delete-node/ opp-667000000-1200; - /delete-node/ opp-750000000-1300; - /delete-node/ opp-800000000-1300; - /delete-node/ opp-900000000-1350; -}; - -&emc_bw_dfs_opp_table { - /delete-node/ opp-625000000; - /delete-node/ opp-667000000; - /delete-node/ opp-750000000; - /delete-node/ opp-800000000; - /delete-node/ opp-900000000; -}; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 9dab8d2c158a..b6fcac6016e0 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -397,13 +397,6 @@ #clock-cells = <1>; #reset-cells = <1>; - sclk { - compatible = "nvidia,tegra30-sclk"; - clocks = <&tegra_car TEGRA30_CLK_SCLK>; - power-domains = <&pd_core>; - operating-points-v2 = <&sclk_dvfs_opp_table>; - }; - pll-c { compatible = "nvidia,tegra30-pllc"; clocks = <&tegra_car TEGRA30_CLK_PLL_C>; @@ -424,6 +417,13 @@ power-domains = <&pd_core>; operating-points-v2 = <&pll_m_dvfs_opp_table>; }; + + sclk { + compatible = "nvidia,tegra30-sclk"; + clocks = <&tegra_car TEGRA30_CLK_SCLK>; + power-domains = <&pd_core>; + operating-points-v2 = <&sclk_dvfs_opp_table>; + }; }; flow-controller@60007000 { @@ -648,13 +648,6 @@ status = "disabled"; }; - rtc@7000e000 { - compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc"; - reg = <0x7000e000 0x100>; - interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&tegra_car TEGRA30_CLK_RTC>; - }; - i2c@7000c000 { compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; reg = <0x7000c000 0x100>; @@ -831,6 +824,13 @@ status = "disabled"; }; + rtc@7000e000 { + compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc"; + reg = <0x7000e000 0x100>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA30_CLK_RTC>; + }; + kbc@7000e200 { compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc"; reg = <0x7000e200 0x100>; @@ -854,6 +854,28 @@ }; powergates { + pd_heg: heg { + clocks = <&tegra_car TEGRA30_CLK_GR2D>, + <&tegra_car TEGRA30_CLK_EPP>, + <&tegra_car TEGRA30_CLK_HOST1X>; + resets = <&mc TEGRA30_MC_RESET_2D>, + <&mc TEGRA30_MC_RESET_EPP>, + <&mc TEGRA30_MC_RESET_HC>, + <&tegra_car TEGRA30_CLK_GR2D>, + <&tegra_car TEGRA30_CLK_EPP>, + <&tegra_car TEGRA30_CLK_HOST1X>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + + pd_mpe: mpe { + clocks = <&tegra_car TEGRA30_CLK_MPE>; + resets = <&mc TEGRA30_MC_RESET_MPE>, + <&tegra_car TEGRA30_CLK_MPE>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + pd_3d0: td { clocks = <&tegra_car TEGRA30_CLK_GR3D>; resets = <&mc TEGRA30_MC_RESET_3D>, @@ -870,6 +892,14 @@ #power-domain-cells = <0>; }; + pd_vde: vdec { + clocks = <&tegra_car TEGRA30_CLK_VDE>; + resets = <&mc TEGRA30_MC_RESET_VDE>, + <&tegra_car TEGRA30_CLK_VDE>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + pd_venc: venc { clocks = <&tegra_car TEGRA30_CLK_ISP>, <&tegra_car TEGRA30_CLK_VI>, @@ -882,36 +912,6 @@ power-domains = <&pd_core>; #power-domain-cells = <0>; }; - - pd_vde: vdec { - clocks = <&tegra_car TEGRA30_CLK_VDE>; - resets = <&mc TEGRA30_MC_RESET_VDE>, - <&tegra_car TEGRA30_CLK_VDE>; - power-domains = <&pd_core>; - #power-domain-cells = <0>; - }; - - pd_mpe: mpe { - clocks = <&tegra_car TEGRA30_CLK_MPE>; - resets = <&mc TEGRA30_MC_RESET_MPE>, - <&tegra_car TEGRA30_CLK_MPE>; - power-domains = <&pd_core>; - #power-domain-cells = <0>; - }; - - pd_heg: heg { - clocks = <&tegra_car TEGRA30_CLK_GR2D>, - <&tegra_car TEGRA30_CLK_EPP>, - <&tegra_car TEGRA30_CLK_HOST1X>; - resets = <&mc TEGRA30_MC_RESET_2D>, - <&mc TEGRA30_MC_RESET_EPP>, - <&mc TEGRA30_MC_RESET_HC>, - <&tegra_car TEGRA30_CLK_GR2D>, - <&tegra_car TEGRA30_CLK_EPP>, - <&tegra_car TEGRA30_CLK_HOST1X>; - power-domains = <&pd_core>; - #power-domain-cells = <0>; - }; }; }; diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h index aecc403b2880..7f092cb55a41 100644 --- a/arch/arm/include/asm/thread_info.h +++ b/arch/arm/include/asm/thread_info.h @@ -128,15 +128,16 @@ extern int vfp_restore_user_hwstate(struct user_vfp *, #define TIF_NEED_RESCHED 1 /* rescheduling necessary */ #define TIF_NOTIFY_RESUME 2 /* callback before returning to user */ #define TIF_UPROBE 3 /* breakpointed or singlestepping */ -#define TIF_SYSCALL_TRACE 4 /* syscall trace active */ -#define TIF_SYSCALL_AUDIT 5 /* syscall auditing active */ -#define TIF_SYSCALL_TRACEPOINT 6 /* syscall tracepoint instrumentation */ -#define TIF_SECCOMP 7 /* seccomp syscall filtering active */ -#define TIF_NOTIFY_SIGNAL 8 /* signal notifications exist */ +#define TIF_NOTIFY_SIGNAL 4 /* signal notifications exist */ #define TIF_USING_IWMMXT 17 #define TIF_MEMDIE 18 /* is terminating due to OOM killer */ -#define TIF_RESTORE_SIGMASK 20 +#define TIF_RESTORE_SIGMASK 19 +#define TIF_SYSCALL_TRACE 20 /* syscall trace active */ +#define TIF_SYSCALL_AUDIT 21 /* syscall auditing active */ +#define TIF_SYSCALL_TRACEPOINT 22 /* syscall tracepoint instrumentation */ +#define TIF_SECCOMP 23 /* seccomp syscall filtering active */ + #define _TIF_SIGPENDING (1 << TIF_SIGPENDING) #define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED) diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi index bde6a6bb8dfc..6f701297a665 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi @@ -96,10 +96,10 @@ max98504: amplifier@31 { compatible = "maxim,max98504"; reg = <0x31>; - maxim,rx-path = <1>; - maxim,tx-path = <1>; - maxim,tx-channel-mask = <3>; - maxim,tx-channel-source = <2>; + + DIOVDD-supply = <&ldo3_reg>; + DVDD-supply = <&ldo3_reg>; + /* PVDD-supply to VPH_PWR */ }; }; @@ -925,7 +925,6 @@ compatible = "maxim,max77843-haptic"; haptic-supply = <&ldo38_reg>; pwms = <&pwm 0 33670 0>; - pwm-names = "haptic"; }; }; }; @@ -1315,7 +1314,7 @@ reg = <0x0>; spi-max-frequency = <5000000>; power-supply = <&irda_regulator>; - duty-cycle = <60>; + duty-cycle = /bits/ 8 <60>; led-active-low; controller-data { diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index bd6a354b9cb5..47b5ac06f0d6 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -89,7 +89,6 @@ compatible = "arm,cortex-a53"; enable-method = "psci"; reg = <0x100>; - clock-frequency = <1300000000>; clocks = <&cmu_apollo CLK_SCLK_APOLLO>; clock-names = "apolloclk"; operating-points-v2 = <&cluster_a53_opp_table>; @@ -108,7 +107,6 @@ compatible = "arm,cortex-a53"; enable-method = "psci"; reg = <0x101>; - clock-frequency = <1300000000>; operating-points-v2 = <&cluster_a53_opp_table>; #cooling-cells = <2>; i-cache-size = <0x8000>; @@ -125,7 +123,6 @@ compatible = "arm,cortex-a53"; enable-method = "psci"; reg = <0x102>; - clock-frequency = <1300000000>; operating-points-v2 = <&cluster_a53_opp_table>; #cooling-cells = <2>; i-cache-size = <0x8000>; @@ -142,7 +139,6 @@ compatible = "arm,cortex-a53"; enable-method = "psci"; reg = <0x103>; - clock-frequency = <1300000000>; operating-points-v2 = <&cluster_a53_opp_table>; #cooling-cells = <2>; i-cache-size = <0x8000>; @@ -159,7 +155,6 @@ compatible = "arm,cortex-a57"; enable-method = "psci"; reg = <0x0>; - clock-frequency = <1900000000>; clocks = <&cmu_atlas CLK_SCLK_ATLAS>; clock-names = "atlasclk"; operating-points-v2 = <&cluster_a57_opp_table>; @@ -178,7 +173,6 @@ compatible = "arm,cortex-a57"; enable-method = "psci"; reg = <0x1>; - clock-frequency = <1900000000>; operating-points-v2 = <&cluster_a57_opp_table>; #cooling-cells = <2>; i-cache-size = <0xc000>; @@ -195,7 +189,6 @@ compatible = "arm,cortex-a57"; enable-method = "psci"; reg = <0x2>; - clock-frequency = <1900000000>; operating-points-v2 = <&cluster_a57_opp_table>; #cooling-cells = <2>; i-cache-size = <0xc000>; @@ -212,7 +205,6 @@ compatible = "arm,cortex-a57"; enable-method = "psci"; reg = <0x3>; - clock-frequency = <1900000000>; operating-points-v2 = <&cluster_a57_opp_table>; #cooling-cells = <2>; i-cache-size = <0xc000>; @@ -226,6 +218,8 @@ cluster_a57_l2: l2-cache0 { compatible = "cache"; + cache-level = <2>; + cache-unified; cache-size = <0x200000>; cache-line-size = <64>; cache-sets = <2048>; @@ -233,6 +227,8 @@ cluster_a53_l2: l2-cache1 { compatible = "cache"; + cache-level = <2>; + cache-unified; cache-size = <0x40000>; cache-line-size = <64>; cache-sets = <256>; @@ -1118,22 +1114,26 @@ }; syscon_disp: syscon@13b80000 { - compatible = "samsung,exynos5433-sysreg", "syscon"; + compatible = "samsung,exynos5433-disp-sysreg", + "samsung,exynos5433-sysreg", "syscon"; reg = <0x13b80000 0x1010>; }; syscon_cam0: syscon@120f0000 { - compatible = "samsung,exynos5433-sysreg", "syscon"; + compatible = "samsung,exynos5433-cam0-sysreg", + "samsung,exynos5433-sysreg", "syscon"; reg = <0x120f0000 0x1020>; }; syscon_cam1: syscon@145f0000 { - compatible = "samsung,exynos5433-sysreg", "syscon"; + compatible = "samsung,exynos5433-cam1-sysreg", + "samsung,exynos5433-sysreg", "syscon"; reg = <0x145f0000 0x1038>; }; syscon_fsys: syscon@156f0000 { - compatible = "samsung,exynos5433-sysreg", "syscon"; + compatible = "samsung,exynos5433-fsys-sysreg", + "samsung,exynos5433-sysreg", "syscon"; reg = <0x156f0000 0x1044>; }; diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts index e38c59cf18dc..b846c0be90e3 100644 --- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts +++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts @@ -83,8 +83,6 @@ }; &hsi2c_4 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <200000>; status = "okay"; pmic@66 { diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi index 1cd771c90b47..f378d8629d88 100644 --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi @@ -107,6 +107,8 @@ atlas_l2: l2-cache0 { compatible = "cache"; + cache-level = <2>; + cache-unified; cache-size = <0x200000>; cache-line-size = <64>; cache-sets = <2048>; diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi index c61441f3a89a..a38fe5129937 100644 --- a/arch/arm64/boot/dts/exynos/exynos850.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi @@ -549,13 +549,15 @@ }; sysreg_peri: syscon@10020000 { - compatible = "samsung,exynos850-sysreg", "syscon"; + compatible = "samsung,exynos850-peri-sysreg", + "samsung,exynos850-sysreg", "syscon"; reg = <0x10020000 0x10000>; clocks = <&cmu_peri CLK_GOUT_SYSREG_PERI_PCLK>; }; sysreg_cmgp: syscon@11c20000 { - compatible = "samsung,exynos850-sysreg", "syscon"; + compatible = "samsung,exynos850-cmgp-sysreg", + "samsung,exynos850-sysreg", "syscon"; reg = <0x11c20000 0x10000>; clocks = <&cmu_cmgp CLK_GOUT_SYSREG_CMGP_PCLK>; }; diff --git a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi index 5dc361734cfe..d3c5cdeff47f 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi @@ -370,17 +370,20 @@ }; syscon_fsys2: syscon@17c20000 { - compatible = "samsung,exynosautov9-sysreg", "syscon"; + compatible = "samsung,exynosautov9-fsys2-sysreg", + "samsung,exynosautov9-sysreg", "syscon"; reg = <0x17c20000 0x1000>; }; syscon_peric0: syscon@10220000 { - compatible = "samsung,exynosautov9-sysreg", "syscon"; + compatible = "samsung,exynosautov9-peric0-sysreg", + "samsung,exynosautov9-sysreg", "syscon"; reg = <0x10220000 0x2000>; }; syscon_peric1: syscon@10820000 { - compatible = "samsung,exynosautov9-sysreg", "syscon"; + compatible = "samsung,exynosautov9-peric1-sysreg", + "samsung,exynosautov9-sysreg", "syscon"; reg = <0x10820000 0x2000>; }; diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts index 0192a01bf852..3f13a960f34e 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts @@ -85,28 +85,28 @@ leds { compatible = "gpio-leds"; - user_led1 { + led-user-1 { label = "green:user1"; /* gpio_150_user_led1 */ gpios = <&gpio18 6 0>; linux,default-trigger = "heartbeat"; }; - user_led2 { + led-user-2 { label = "green:user2"; /* gpio_151_user_led2 */ gpios = <&gpio18 7 0>; linux,default-trigger = "none"; }; - user_led3 { + led-user-3 { label = "green:user3"; /* gpio_189_user_led3 */ gpios = <&gpio23 5 0>; linux,default-trigger = "mmc0"; }; - user_led4 { + led-user-4 { label = "green:user4"; /* gpio_190_user_led4 */ gpios = <&gpio23 6 0>; @@ -114,7 +114,7 @@ linux,default-trigger = "none"; }; - wlan_active_led { + led-wlan { label = "yellow:wlan"; /* gpio_205_wifi_active */ gpios = <&gpio25 5 0>; @@ -122,7 +122,7 @@ default-state = "off"; }; - bt_active_led { + led-bt { label = "blue:bt"; gpios = <&gpio25 7 0>; /* gpio_207_user_led1 */ diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts index 629e604aa281..f0672ec65b26 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts +++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts @@ -125,39 +125,39 @@ leds { compatible = "gpio-leds"; - user_led1 { + led-user-1 { label = "green:user1"; gpios = <&gpio4 0 0>; /* <&gpio_user_led_1>; */ linux,default-trigger = "heartbeat"; }; - user_led2 { + led-user-2 { label = "green:user2"; gpios = <&gpio4 1 0>; /* <&gpio_user_led_2>; */ linux,default-trigger = "mmc0"; }; - user_led3 { + led-user-3 { label = "green:user3"; gpios = <&gpio4 2 0>; /* <&gpio_user_led_3>; */ linux,default-trigger = "mmc1"; }; - user_led4 { + led-user-4 { label = "green:user4"; gpios = <&gpio4 3 0>; /* <&gpio_user_led_4>; */ panic-indicator; linux,default-trigger = "none"; }; - wlan_active_led { + led-wlan { label = "yellow:wlan"; gpios = <&gpio3 5 0>; /* <&gpio_wlan_active_led>; */ linux,default-trigger = "phy0tx"; default-state = "off"; }; - bt_active_led { + led-bt { label = "blue:bt"; gpios = <&gpio4 7 0>; /* <&gpio_bt_active_led>; */ linux,default-trigger = "hci0-power"; diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index 2dd5e38820b1..0367a00a269b 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -465,7 +465,7 @@ reg = <0x6 0x10808000 0x5d0000>; }; - switch: switch@0x600000000 { + switch: switch@600000000 { compatible = "microchip,sparx5-switch"; reg = <0x6 0 0x401000>, <0x6 0x10004000 0x7fc000>, diff --git a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts index 3e8dee85d55f..d4c034ac1244 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts +++ b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts @@ -1030,6 +1030,14 @@ gpio-keys { compatible = "gpio-keys"; + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; + linux,code = <KEY_POWER>; + debounce-interval = <10>; + wakeup-source; + }; + switch-lid { label = "Lid"; gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>; @@ -1038,14 +1046,6 @@ debounce-interval = <1>; wakeup-source; }; - - key-power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; - linux,code = <KEY_POWER>; - debounce-interval = <10>; - wakeup-source; - }; }; panel: panel { diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index 858fc01cecb6..c017764bc27e 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -893,122 +893,6 @@ }; }; - thermal-zones { - cpu-thermal { - polling-delay-passive = <1000>; - polling-delay = <0>; - - thermal-sensors = - <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; - - trips { - cpu_shutdown_trip { - temperature = <105000>; - hysteresis = <1000>; - type = "critical"; - }; - - cpu_throttle_trip: throttle-trip { - temperature = <102000>; - hysteresis = <1000>; - type = "hot"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_throttle_trip>; - cooling-device = <&throttle_heavy 1 1>; - }; - }; - }; - - mem-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = - <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; - - trips { - mem_shutdown_trip { - temperature = <101000>; - hysteresis = <1000>; - type = "critical"; - }; - mem_throttle_trip { - temperature = <99000>; - hysteresis = <1000>; - type = "hot"; - }; - }; - - cooling-maps { - /* - * There are currently no cooling maps, - * because there are no cooling devices. - */ - }; - }; - - gpu-thermal { - polling-delay-passive = <1000>; - polling-delay = <0>; - - thermal-sensors = - <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; - - trips { - gpu_shutdown_trip { - temperature = <101000>; - hysteresis = <1000>; - type = "critical"; - }; - - gpu_throttle_trip: throttle-trip { - temperature = <99000>; - hysteresis = <1000>; - type = "hot"; - }; - }; - - cooling-maps { - map0 { - trip = <&gpu_throttle_trip>; - cooling-device = <&throttle_heavy 1 1>; - }; - }; - }; - - pllx-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = - <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; - - trips { - pllx_shutdown_trip { - temperature = <105000>; - hysteresis = <1000>; - type = "critical"; - }; - pllx_throttle_trip { - temperature = <99000>; - hysteresis = <1000>; - type = "hot"; - }; - }; - - cooling-maps { - /* - * There are currently no cooling maps, - * because there are no cooling devices. - */ - }; - }; - }; - ahub@70300000 { compatible = "nvidia,tegra124-ahub"; reg = <0x0 0x70300000 0x0 0x200>, @@ -1255,6 +1139,122 @@ }; }; + thermal-zones { + cpu-thermal { + polling-delay-passive = <1000>; + polling-delay = <0>; + + thermal-sensors = + <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; + + trips { + cpu_shutdown_trip { + temperature = <105000>; + hysteresis = <1000>; + type = "critical"; + }; + + cpu_throttle_trip: throttle-trip { + temperature = <102000>; + hysteresis = <1000>; + type = "hot"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_throttle_trip>; + cooling-device = <&throttle_heavy 1 1>; + }; + }; + }; + + mem-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = + <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; + + trips { + mem_shutdown_trip { + temperature = <101000>; + hysteresis = <1000>; + type = "critical"; + }; + mem_throttle_trip { + temperature = <99000>; + hysteresis = <1000>; + type = "hot"; + }; + }; + + cooling-maps { + /* + * There are currently no cooling maps, + * because there are no cooling devices. + */ + }; + }; + + gpu-thermal { + polling-delay-passive = <1000>; + polling-delay = <0>; + + thermal-sensors = + <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; + + trips { + gpu_shutdown_trip { + temperature = <101000>; + hysteresis = <1000>; + type = "critical"; + }; + + gpu_throttle_trip: throttle-trip { + temperature = <99000>; + hysteresis = <1000>; + type = "hot"; + }; + }; + + cooling-maps { + map0 { + trip = <&gpu_throttle_trip>; + cooling-device = <&throttle_heavy 1 1>; + }; + }; + }; + + pllx-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = + <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; + + trips { + pllx_shutdown_trip { + temperature = <105000>; + hysteresis = <1000>; + type = "critical"; + }; + pllx_throttle_trip { + temperature = <99000>; + hysteresis = <1000>; + type = "hot"; + }; + }; + + cooling-maps { + /* + * There are currently no cooling maps, + * because there are no cooling devices. + */ + }; + }; + }; + timer { compatible = "arm,armv7-timer"; interrupts = <GIC_PPI 13 diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts index 47cf2013afcc..15aa49fc4503 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts @@ -13,1095 +13,9 @@ aconnect@2900000 { status = "okay"; - dma-controller@2930000 { - status = "okay"; - }; - - interrupt-controller@2a40000 { - status = "okay"; - }; - ahub@2900800 { status = "okay"; - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0x0>; - - xbar_admaif0_ep: endpoint { - remote-endpoint = <&admaif0_ep>; - }; - }; - - port@1 { - reg = <0x1>; - - xbar_admaif1_ep: endpoint { - remote-endpoint = <&admaif1_ep>; - }; - }; - - port@2 { - reg = <0x2>; - - xbar_admaif2_ep: endpoint { - remote-endpoint = <&admaif2_ep>; - }; - }; - - port@3 { - reg = <0x3>; - - xbar_admaif3_ep: endpoint { - remote-endpoint = <&admaif3_ep>; - }; - }; - - port@4 { - reg = <0x4>; - - xbar_admaif4_ep: endpoint { - remote-endpoint = <&admaif4_ep>; - }; - }; - - port@5 { - reg = <0x5>; - - xbar_admaif5_ep: endpoint { - remote-endpoint = <&admaif5_ep>; - }; - }; - - port@6 { - reg = <0x6>; - - xbar_admaif6_ep: endpoint { - remote-endpoint = <&admaif6_ep>; - }; - }; - - port@7 { - reg = <0x7>; - - xbar_admaif7_ep: endpoint { - remote-endpoint = <&admaif7_ep>; - }; - }; - - port@8 { - reg = <0x8>; - - xbar_admaif8_ep: endpoint { - remote-endpoint = <&admaif8_ep>; - }; - }; - - port@9 { - reg = <0x9>; - - xbar_admaif9_ep: endpoint { - remote-endpoint = <&admaif9_ep>; - }; - }; - - port@a { - reg = <0xa>; - - xbar_admaif10_ep: endpoint { - remote-endpoint = <&admaif10_ep>; - }; - }; - - port@b { - reg = <0xb>; - - xbar_admaif11_ep: endpoint { - remote-endpoint = <&admaif11_ep>; - }; - }; - - port@c { - reg = <0xc>; - - xbar_admaif12_ep: endpoint { - remote-endpoint = <&admaif12_ep>; - }; - }; - - port@d { - reg = <0xd>; - - xbar_admaif13_ep: endpoint { - remote-endpoint = <&admaif13_ep>; - }; - }; - - port@e { - reg = <0xe>; - - xbar_admaif14_ep: endpoint { - remote-endpoint = <&admaif14_ep>; - }; - }; - - port@f { - reg = <0xf>; - - xbar_admaif15_ep: endpoint { - remote-endpoint = <&admaif15_ep>; - }; - }; - - port@10 { - reg = <0x10>; - - xbar_admaif16_ep: endpoint { - remote-endpoint = <&admaif16_ep>; - }; - }; - - port@11 { - reg = <0x11>; - - xbar_admaif17_ep: endpoint { - remote-endpoint = <&admaif17_ep>; - }; - }; - - port@12 { - reg = <0x12>; - - xbar_admaif18_ep: endpoint { - remote-endpoint = <&admaif18_ep>; - }; - }; - - port@13 { - reg = <0x13>; - - xbar_admaif19_ep: endpoint { - remote-endpoint = <&admaif19_ep>; - }; - }; - - xbar_i2s1_port: port@14 { - reg = <0x14>; - - xbar_i2s1_ep: endpoint { - remote-endpoint = <&i2s1_cif_ep>; - }; - }; - - xbar_i2s2_port: port@15 { - reg = <0x15>; - - xbar_i2s2_ep: endpoint { - remote-endpoint = <&i2s2_cif_ep>; - }; - }; - - xbar_i2s3_port: port@16 { - reg = <0x16>; - - xbar_i2s3_ep: endpoint { - remote-endpoint = <&i2s3_cif_ep>; - }; - }; - - xbar_i2s4_port: port@17 { - reg = <0x17>; - - xbar_i2s4_ep: endpoint { - remote-endpoint = <&i2s4_cif_ep>; - }; - }; - - xbar_i2s5_port: port@18 { - reg = <0x18>; - - xbar_i2s5_ep: endpoint { - remote-endpoint = <&i2s5_cif_ep>; - }; - }; - - xbar_i2s6_port: port@19 { - reg = <0x19>; - - xbar_i2s6_ep: endpoint { - remote-endpoint = <&i2s6_cif_ep>; - }; - }; - - xbar_dmic1_port: port@1a { - reg = <0x1a>; - - xbar_dmic1_ep: endpoint { - remote-endpoint = <&dmic1_cif_ep>; - }; - }; - - xbar_dmic2_port: port@1b { - reg = <0x1b>; - - xbar_dmic2_ep: endpoint { - remote-endpoint = <&dmic2_cif_ep>; - }; - }; - - xbar_dmic3_port: port@1c { - reg = <0x1c>; - - xbar_dmic3_ep: endpoint { - remote-endpoint = <&dmic3_cif_ep>; - }; - }; - - xbar_dspk1_port: port@1e { - reg = <0x1e>; - - xbar_dspk1_ep: endpoint { - remote-endpoint = <&dspk1_cif_ep>; - }; - }; - - xbar_dspk2_port: port@1f { - reg = <0x1f>; - - xbar_dspk2_ep: endpoint { - remote-endpoint = <&dspk2_cif_ep>; - }; - }; - - xbar_sfc1_in_port: port@20 { - reg = <0x20>; - - xbar_sfc1_in_ep: endpoint { - remote-endpoint = <&sfc1_cif_in_ep>; - }; - }; - - port@21 { - reg = <0x21>; - - xbar_sfc1_out_ep: endpoint { - remote-endpoint = <&sfc1_cif_out_ep>; - }; - }; - - xbar_sfc2_in_port: port@22 { - reg = <0x22>; - - xbar_sfc2_in_ep: endpoint { - remote-endpoint = <&sfc2_cif_in_ep>; - }; - }; - - port@23 { - reg = <0x23>; - - xbar_sfc2_out_ep: endpoint { - remote-endpoint = <&sfc2_cif_out_ep>; - }; - }; - - xbar_sfc3_in_port: port@24 { - reg = <0x24>; - - xbar_sfc3_in_ep: endpoint { - remote-endpoint = <&sfc3_cif_in_ep>; - }; - }; - - port@25 { - reg = <0x25>; - - xbar_sfc3_out_ep: endpoint { - remote-endpoint = <&sfc3_cif_out_ep>; - }; - }; - - xbar_sfc4_in_port: port@26 { - reg = <0x26>; - - xbar_sfc4_in_ep: endpoint { - remote-endpoint = <&sfc4_cif_in_ep>; - }; - }; - - port@27 { - reg = <0x27>; - - xbar_sfc4_out_ep: endpoint { - remote-endpoint = <&sfc4_cif_out_ep>; - }; - }; - - xbar_mvc1_in_port: port@28 { - reg = <0x28>; - - xbar_mvc1_in_ep: endpoint { - remote-endpoint = <&mvc1_cif_in_ep>; - }; - }; - - port@29 { - reg = <0x29>; - - xbar_mvc1_out_ep: endpoint { - remote-endpoint = <&mvc1_cif_out_ep>; - }; - }; - - xbar_mvc2_in_port: port@2a { - reg = <0x2a>; - - xbar_mvc2_in_ep: endpoint { - remote-endpoint = <&mvc2_cif_in_ep>; - }; - }; - - port@2b { - reg = <0x2b>; - - xbar_mvc2_out_ep: endpoint { - remote-endpoint = <&mvc2_cif_out_ep>; - }; - }; - - xbar_amx1_in1_port: port@2c { - reg = <0x2c>; - - xbar_amx1_in1_ep: endpoint { - remote-endpoint = <&amx1_in1_ep>; - }; - }; - - xbar_amx1_in2_port: port@2d { - reg = <0x2d>; - - xbar_amx1_in2_ep: endpoint { - remote-endpoint = <&amx1_in2_ep>; - }; - }; - - xbar_amx1_in3_port: port@2e { - reg = <0x2e>; - - xbar_amx1_in3_ep: endpoint { - remote-endpoint = <&amx1_in3_ep>; - }; - }; - - xbar_amx1_in4_port: port@2f { - reg = <0x2f>; - - xbar_amx1_in4_ep: endpoint { - remote-endpoint = <&amx1_in4_ep>; - }; - }; - - port@30 { - reg = <0x30>; - - xbar_amx1_out_ep: endpoint { - remote-endpoint = <&amx1_out_ep>; - }; - }; - - xbar_amx2_in1_port: port@31 { - reg = <0x31>; - - xbar_amx2_in1_ep: endpoint { - remote-endpoint = <&amx2_in1_ep>; - }; - }; - - xbar_amx2_in2_port: port@32 { - reg = <0x32>; - - xbar_amx2_in2_ep: endpoint { - remote-endpoint = <&amx2_in2_ep>; - }; - }; - - xbar_amx2_in3_port: port@33 { - reg = <0x33>; - - xbar_amx2_in3_ep: endpoint { - remote-endpoint = <&amx2_in3_ep>; - }; - }; - - xbar_amx2_in4_port: port@34 { - reg = <0x34>; - - xbar_amx2_in4_ep: endpoint { - remote-endpoint = <&amx2_in4_ep>; - }; - }; - - port@35 { - reg = <0x35>; - - xbar_amx2_out_ep: endpoint { - remote-endpoint = <&amx2_out_ep>; - }; - }; - - xbar_amx3_in1_port: port@36 { - reg = <0x36>; - - xbar_amx3_in1_ep: endpoint { - remote-endpoint = <&amx3_in1_ep>; - }; - }; - - xbar_amx3_in2_port: port@37 { - reg = <0x37>; - - xbar_amx3_in2_ep: endpoint { - remote-endpoint = <&amx3_in2_ep>; - }; - }; - - xbar_amx3_in3_port: port@38 { - reg = <0x38>; - - xbar_amx3_in3_ep: endpoint { - remote-endpoint = <&amx3_in3_ep>; - }; - }; - - xbar_amx3_in4_port: port@39 { - reg = <0x39>; - - xbar_amx3_in4_ep: endpoint { - remote-endpoint = <&amx3_in4_ep>; - }; - }; - - port@3a { - reg = <0x3a>; - - xbar_amx3_out_ep: endpoint { - remote-endpoint = <&amx3_out_ep>; - }; - }; - - xbar_amx4_in1_port: port@3b { - reg = <0x3b>; - - xbar_amx4_in1_ep: endpoint { - remote-endpoint = <&amx4_in1_ep>; - }; - }; - - xbar_amx4_in2_port: port@3c { - reg = <0x3c>; - - xbar_amx4_in2_ep: endpoint { - remote-endpoint = <&amx4_in2_ep>; - }; - }; - - xbar_amx4_in3_port: port@3d { - reg = <0x3d>; - - xbar_amx4_in3_ep: endpoint { - remote-endpoint = <&amx4_in3_ep>; - }; - }; - - xbar_amx4_in4_port: port@3e { - reg = <0x3e>; - - xbar_amx4_in4_ep: endpoint { - remote-endpoint = <&amx4_in4_ep>; - }; - }; - - port@3f { - reg = <0x3f>; - - xbar_amx4_out_ep: endpoint { - remote-endpoint = <&amx4_out_ep>; - }; - }; - - xbar_adx1_in_port: port@40 { - reg = <0x40>; - - xbar_adx1_in_ep: endpoint { - remote-endpoint = <&adx1_in_ep>; - }; - }; - - port@41 { - reg = <0x41>; - - xbar_adx1_out1_ep: endpoint { - remote-endpoint = <&adx1_out1_ep>; - }; - }; - - port@42 { - reg = <0x42>; - - xbar_adx1_out2_ep: endpoint { - remote-endpoint = <&adx1_out2_ep>; - }; - }; - - port@43 { - reg = <0x43>; - - xbar_adx1_out3_ep: endpoint { - remote-endpoint = <&adx1_out3_ep>; - }; - }; - - port@44 { - reg = <0x44>; - - xbar_adx1_out4_ep: endpoint { - remote-endpoint = <&adx1_out4_ep>; - }; - }; - - xbar_adx2_in_port: port@45 { - reg = <0x45>; - - xbar_adx2_in_ep: endpoint { - remote-endpoint = <&adx2_in_ep>; - }; - }; - - port@46 { - reg = <0x46>; - - xbar_adx2_out1_ep: endpoint { - remote-endpoint = <&adx2_out1_ep>; - }; - }; - - port@47 { - reg = <0x47>; - - xbar_adx2_out2_ep: endpoint { - remote-endpoint = <&adx2_out2_ep>; - }; - }; - - port@48 { - reg = <0x48>; - - xbar_adx2_out3_ep: endpoint { - remote-endpoint = <&adx2_out3_ep>; - }; - }; - - port@49 { - reg = <0x49>; - - xbar_adx2_out4_ep: endpoint { - remote-endpoint = <&adx2_out4_ep>; - }; - }; - - xbar_adx3_in_port: port@4a { - reg = <0x4a>; - - xbar_adx3_in_ep: endpoint { - remote-endpoint = <&adx3_in_ep>; - }; - }; - - port@4b { - reg = <0x4b>; - - xbar_adx3_out1_ep: endpoint { - remote-endpoint = <&adx3_out1_ep>; - }; - }; - - port@4c { - reg = <0x4c>; - - xbar_adx3_out2_ep: endpoint { - remote-endpoint = <&adx3_out2_ep>; - }; - }; - - port@4d { - reg = <0x4d>; - - xbar_adx3_out3_ep: endpoint { - remote-endpoint = <&adx3_out3_ep>; - }; - }; - - port@4e { - reg = <0x4e>; - - xbar_adx3_out4_ep: endpoint { - remote-endpoint = <&adx3_out4_ep>; - }; - }; - - xbar_adx4_in_port: port@4f { - reg = <0x4f>; - - xbar_adx4_in_ep: endpoint { - remote-endpoint = <&adx4_in_ep>; - }; - }; - - port@50 { - reg = <0x50>; - - xbar_adx4_out1_ep: endpoint { - remote-endpoint = <&adx4_out1_ep>; - }; - }; - - port@51 { - reg = <0x51>; - - xbar_adx4_out2_ep: endpoint { - remote-endpoint = <&adx4_out2_ep>; - }; - }; - - port@52 { - reg = <0x52>; - - xbar_adx4_out3_ep: endpoint { - remote-endpoint = <&adx4_out3_ep>; - }; - }; - - port@53 { - reg = <0x53>; - - xbar_adx4_out4_ep: endpoint { - remote-endpoint = <&adx4_out4_ep>; - }; - }; - - xbar_mixer_in1_port: port@54 { - reg = <0x54>; - - xbar_mixer_in1_ep: endpoint { - remote-endpoint = <&mixer_in1_ep>; - }; - }; - - xbar_mixer_in2_port: port@55 { - reg = <0x55>; - - xbar_mixer_in2_ep: endpoint { - remote-endpoint = <&mixer_in2_ep>; - }; - }; - - xbar_mixer_in3_port: port@56 { - reg = <0x56>; - - xbar_mixer_in3_ep: endpoint { - remote-endpoint = <&mixer_in3_ep>; - }; - }; - - xbar_mixer_in4_port: port@57 { - reg = <0x57>; - - xbar_mixer_in4_ep: endpoint { - remote-endpoint = <&mixer_in4_ep>; - }; - }; - - xbar_mixer_in5_port: port@58 { - reg = <0x58>; - - xbar_mixer_in5_ep: endpoint { - remote-endpoint = <&mixer_in5_ep>; - }; - }; - - xbar_mixer_in6_port: port@59 { - reg = <0x59>; - - xbar_mixer_in6_ep: endpoint { - remote-endpoint = <&mixer_in6_ep>; - }; - }; - - xbar_mixer_in7_port: port@5a { - reg = <0x5a>; - - xbar_mixer_in7_ep: endpoint { - remote-endpoint = <&mixer_in7_ep>; - }; - }; - - xbar_mixer_in8_port: port@5b { - reg = <0x5b>; - - xbar_mixer_in8_ep: endpoint { - remote-endpoint = <&mixer_in8_ep>; - }; - }; - - xbar_mixer_in9_port: port@5c { - reg = <0x5c>; - - xbar_mixer_in9_ep: endpoint { - remote-endpoint = <&mixer_in9_ep>; - }; - }; - - xbar_mixer_in10_port: port@5d { - reg = <0x5d>; - - xbar_mixer_in10_ep: endpoint { - remote-endpoint = <&mixer_in10_ep>; - }; - }; - - port@5e { - reg = <0x5e>; - - xbar_mixer_out1_ep: endpoint { - remote-endpoint = <&mixer_out1_ep>; - }; - }; - - port@5f { - reg = <0x5f>; - - xbar_mixer_out2_ep: endpoint { - remote-endpoint = <&mixer_out2_ep>; - }; - }; - - port@60 { - reg = <0x60>; - - xbar_mixer_out3_ep: endpoint { - remote-endpoint = <&mixer_out3_ep>; - }; - }; - - port@61 { - reg = <0x61>; - - xbar_mixer_out4_ep: endpoint { - remote-endpoint = <&mixer_out4_ep>; - }; - }; - - port@62 { - reg = <0x62>; - - xbar_mixer_out5_ep: endpoint { - remote-endpoint = <&mixer_out5_ep>; - }; - }; - - xbar_asrc_in1_port: port@63 { - reg = <0x63>; - - xbar_asrc_in1_ep: endpoint { - remote-endpoint = <&asrc_in1_ep>; - }; - }; - - port@64 { - reg = <0x64>; - - xbar_asrc_out1_ep: endpoint { - remote-endpoint = <&asrc_out1_ep>; - }; - }; - - xbar_asrc_in2_port: port@65 { - reg = <0x65>; - - xbar_asrc_in2_ep: endpoint { - remote-endpoint = <&asrc_in2_ep>; - }; - }; - - port@66 { - reg = <0x66>; - - xbar_asrc_out2_ep: endpoint { - remote-endpoint = <&asrc_out2_ep>; - }; - }; - - xbar_asrc_in3_port: port@67 { - reg = <0x67>; - - xbar_asrc_in3_ep: endpoint { - remote-endpoint = <&asrc_in3_ep>; - }; - }; - - port@68 { - reg = <0x68>; - - xbar_asrc_out3_ep: endpoint { - remote-endpoint = <&asrc_out3_ep>; - }; - }; - - xbar_asrc_in4_port: port@69 { - reg = <0x69>; - - xbar_asrc_in4_ep: endpoint { - remote-endpoint = <&asrc_in4_ep>; - }; - }; - - port@6a { - reg = <0x6a>; - - xbar_asrc_out4_ep: endpoint { - remote-endpoint = <&asrc_out4_ep>; - }; - }; - - xbar_asrc_in5_port: port@6b { - reg = <0x6b>; - - xbar_asrc_in5_ep: endpoint { - remote-endpoint = <&asrc_in5_ep>; - }; - }; - - port@6c { - reg = <0x6c>; - - xbar_asrc_out5_ep: endpoint { - remote-endpoint = <&asrc_out5_ep>; - }; - }; - - xbar_asrc_in6_port: port@6d { - reg = <0x6d>; - - xbar_asrc_in6_ep: endpoint { - remote-endpoint = <&asrc_in6_ep>; - }; - }; - - port@6e { - reg = <0x6e>; - - xbar_asrc_out6_ep: endpoint { - remote-endpoint = <&asrc_out6_ep>; - }; - }; - - xbar_asrc_in7_port: port@6f { - reg = <0x6f>; - - xbar_asrc_in7_ep: endpoint { - remote-endpoint = <&asrc_in7_ep>; - }; - }; - - xbar_ope1_in_port: port@70 { - reg = <0x70>; - - xbar_ope1_in_ep: endpoint { - remote-endpoint = <&ope1_cif_in_ep>; - }; - }; - - port@71 { - reg = <0x71>; - - xbar_ope1_out_ep: endpoint { - remote-endpoint = <&ope1_cif_out_ep>; - }; - }; - }; - - admaif@290f000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - admaif0_port: port@0 { - reg = <0x0>; - - admaif0_ep: endpoint { - remote-endpoint = <&xbar_admaif0_ep>; - }; - }; - - admaif1_port: port@1 { - reg = <0x1>; - - admaif1_ep: endpoint { - remote-endpoint = <&xbar_admaif1_ep>; - }; - }; - - admaif2_port: port@2 { - reg = <0x2>; - - admaif2_ep: endpoint { - remote-endpoint = <&xbar_admaif2_ep>; - }; - }; - - admaif3_port: port@3 { - reg = <0x3>; - - admaif3_ep: endpoint { - remote-endpoint = <&xbar_admaif3_ep>; - }; - }; - - admaif4_port: port@4 { - reg = <0x4>; - - admaif4_ep: endpoint { - remote-endpoint = <&xbar_admaif4_ep>; - }; - }; - - admaif5_port: port@5 { - reg = <0x5>; - - admaif5_ep: endpoint { - remote-endpoint = <&xbar_admaif5_ep>; - }; - }; - - admaif6_port: port@6 { - reg = <0x6>; - - admaif6_ep: endpoint { - remote-endpoint = <&xbar_admaif6_ep>; - }; - }; - - admaif7_port: port@7 { - reg = <0x7>; - - admaif7_ep: endpoint { - remote-endpoint = <&xbar_admaif7_ep>; - }; - }; - - admaif8_port: port@8 { - reg = <0x8>; - - admaif8_ep: endpoint { - remote-endpoint = <&xbar_admaif8_ep>; - }; - }; - - admaif9_port: port@9 { - reg = <0x9>; - - admaif9_ep: endpoint { - remote-endpoint = <&xbar_admaif9_ep>; - }; - }; - - admaif10_port: port@a { - reg = <0xa>; - - admaif10_ep: endpoint { - remote-endpoint = <&xbar_admaif10_ep>; - }; - }; - - admaif11_port: port@b { - reg = <0xb>; - - admaif11_ep: endpoint { - remote-endpoint = <&xbar_admaif11_ep>; - }; - }; - - admaif12_port: port@c { - reg = <0xc>; - - admaif12_ep: endpoint { - remote-endpoint = <&xbar_admaif12_ep>; - }; - }; - - admaif13_port: port@d { - reg = <0xd>; - - admaif13_ep: endpoint { - remote-endpoint = <&xbar_admaif13_ep>; - }; - }; - - admaif14_port: port@e { - reg = <0xe>; - - admaif14_ep: endpoint { - remote-endpoint = <&xbar_admaif14_ep>; - }; - }; - - admaif15_port: port@f { - reg = <0xf>; - - admaif15_ep: endpoint { - remote-endpoint = <&xbar_admaif15_ep>; - }; - }; - - admaif16_port: port@10 { - reg = <0x10>; - - admaif16_ep: endpoint { - remote-endpoint = <&xbar_admaif16_ep>; - }; - }; - - admaif17_port: port@11 { - reg = <0x11>; - - admaif17_ep: endpoint { - remote-endpoint = <&xbar_admaif17_ep>; - }; - }; - - admaif18_port: port@12 { - reg = <0x12>; - - admaif18_ep: endpoint { - remote-endpoint = <&xbar_admaif18_ep>; - }; - }; - - admaif19_port: port@13 { - reg = <0x13>; - - admaif19_ep: endpoint { - remote-endpoint = <&xbar_admaif19_ep>; - }; - }; - }; - }; - i2s@2901000 { status = "okay"; @@ -1258,131 +172,6 @@ }; }; - dmic@2904000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dmic1_cif_ep: endpoint { - remote-endpoint = <&xbar_dmic1_ep>; - }; - }; - - dmic1_port: port@1 { - reg = <1>; - - dmic1_dap_ep: endpoint { - /* Place holder for external Codec */ - }; - }; - }; - }; - - dmic@2904100 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dmic2_cif_ep: endpoint { - remote-endpoint = <&xbar_dmic2_ep>; - }; - }; - - dmic2_port: port@1 { - reg = <1>; - - dmic2_dap_ep: endpoint { - /* Place holder for external Codec */ - }; - }; - }; - }; - - dmic@2904200 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dmic3_cif_ep: endpoint { - remote-endpoint = <&xbar_dmic3_ep>; - }; - }; - - dmic3_port: port@1 { - reg = <1>; - - dmic3_dap_ep: endpoint { - /* Place holder for external Codec */ - }; - }; - }; - }; - - dspk@2905000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dspk1_cif_ep: endpoint { - remote-endpoint = <&xbar_dspk1_ep>; - }; - }; - - dspk1_port: port@1 { - reg = <1>; - - dspk1_dap_ep: endpoint { - /* Place holder for external Codec */ - }; - }; - }; - }; - - dspk@2905100 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dspk2_cif_ep: endpoint { - remote-endpoint = <&xbar_dspk2_ep>; - }; - }; - - dspk2_port: port@1 { - reg = <1>; - - dspk2_dap_ep: endpoint { - /* Place holder for external Codec */ - }; - }; - }; - }; - sfc@2902000 { status = "okay"; @@ -1485,56 +274,6 @@ }; }; - mvc@290a000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - mvc1_cif_in_ep: endpoint { - remote-endpoint = <&xbar_mvc1_in_ep>; - }; - }; - - mvc1_out_port: port@1 { - reg = <1>; - - mvc1_cif_out_ep: endpoint { - remote-endpoint = <&xbar_mvc1_out_ep>; - }; - }; - }; - }; - - mvc@290a200 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - mvc2_cif_in_ep: endpoint { - remote-endpoint = <&xbar_mvc2_in_ep>; - }; - }; - - mvc2_out_port: port@1 { - reg = <1>; - - mvc2_cif_out_ep: endpoint { - remote-endpoint = <&xbar_mvc2_out_ep>; - }; - }; - }; - }; - amx@2903000 { status = "okay"; @@ -1927,6 +666,131 @@ }; }; + dmic@2904000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dmic1_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic1_ep>; + }; + }; + + dmic1_port: port@1 { + reg = <1>; + + dmic1_dap_ep: endpoint { + /* Place holder for external Codec */ + }; + }; + }; + }; + + dmic@2904100 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dmic2_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic2_ep>; + }; + }; + + dmic2_port: port@1 { + reg = <1>; + + dmic2_dap_ep: endpoint { + /* Place holder for external Codec */ + }; + }; + }; + }; + + dmic@2904200 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dmic3_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic3_ep>; + }; + }; + + dmic3_port: port@1 { + reg = <1>; + + dmic3_dap_ep: endpoint { + /* Place holder for external Codec */ + }; + }; + }; + }; + + dspk@2905000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dspk1_cif_ep: endpoint { + remote-endpoint = <&xbar_dspk1_ep>; + }; + }; + + dspk1_port: port@1 { + reg = <1>; + + dspk1_dap_ep: endpoint { + /* Place holder for external Codec */ + }; + }; + }; + }; + + dspk@2905100 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dspk2_cif_ep: endpoint { + remote-endpoint = <&xbar_dspk2_ep>; + }; + }; + + dspk2_port: port@1 { + reg = <1>; + + dspk2_dap_ep: endpoint { + /* Place holder for external Codec */ + }; + }; + }; + }; + processing-engine@2908000 { status = "okay"; @@ -1952,6 +816,56 @@ }; }; + mvc@290a000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mvc1_cif_in_ep: endpoint { + remote-endpoint = <&xbar_mvc1_in_ep>; + }; + }; + + mvc1_out_port: port@1 { + reg = <1>; + + mvc1_cif_out_ep: endpoint { + remote-endpoint = <&xbar_mvc1_out_ep>; + }; + }; + }; + }; + + mvc@290a200 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mvc2_cif_in_ep: endpoint { + remote-endpoint = <&xbar_mvc2_in_ep>; + }; + }; + + mvc2_out_port: port@1 { + reg = <1>; + + mvc2_cif_out_ep: endpoint { + remote-endpoint = <&xbar_mvc2_out_ep>; + }; + }; + }; + }; + amixer@290bb00 { status = "okay"; @@ -2081,6 +995,175 @@ }; }; + admaif@290f000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + admaif0_port: port@0 { + reg = <0x0>; + + admaif0_ep: endpoint { + remote-endpoint = <&xbar_admaif0_ep>; + }; + }; + + admaif1_port: port@1 { + reg = <0x1>; + + admaif1_ep: endpoint { + remote-endpoint = <&xbar_admaif1_ep>; + }; + }; + + admaif2_port: port@2 { + reg = <0x2>; + + admaif2_ep: endpoint { + remote-endpoint = <&xbar_admaif2_ep>; + }; + }; + + admaif3_port: port@3 { + reg = <0x3>; + + admaif3_ep: endpoint { + remote-endpoint = <&xbar_admaif3_ep>; + }; + }; + + admaif4_port: port@4 { + reg = <0x4>; + + admaif4_ep: endpoint { + remote-endpoint = <&xbar_admaif4_ep>; + }; + }; + + admaif5_port: port@5 { + reg = <0x5>; + + admaif5_ep: endpoint { + remote-endpoint = <&xbar_admaif5_ep>; + }; + }; + + admaif6_port: port@6 { + reg = <0x6>; + + admaif6_ep: endpoint { + remote-endpoint = <&xbar_admaif6_ep>; + }; + }; + + admaif7_port: port@7 { + reg = <0x7>; + + admaif7_ep: endpoint { + remote-endpoint = <&xbar_admaif7_ep>; + }; + }; + + admaif8_port: port@8 { + reg = <0x8>; + + admaif8_ep: endpoint { + remote-endpoint = <&xbar_admaif8_ep>; + }; + }; + + admaif9_port: port@9 { + reg = <0x9>; + + admaif9_ep: endpoint { + remote-endpoint = <&xbar_admaif9_ep>; + }; + }; + + admaif10_port: port@a { + reg = <0xa>; + + admaif10_ep: endpoint { + remote-endpoint = <&xbar_admaif10_ep>; + }; + }; + + admaif11_port: port@b { + reg = <0xb>; + + admaif11_ep: endpoint { + remote-endpoint = <&xbar_admaif11_ep>; + }; + }; + + admaif12_port: port@c { + reg = <0xc>; + + admaif12_ep: endpoint { + remote-endpoint = <&xbar_admaif12_ep>; + }; + }; + + admaif13_port: port@d { + reg = <0xd>; + + admaif13_ep: endpoint { + remote-endpoint = <&xbar_admaif13_ep>; + }; + }; + + admaif14_port: port@e { + reg = <0xe>; + + admaif14_ep: endpoint { + remote-endpoint = <&xbar_admaif14_ep>; + }; + }; + + admaif15_port: port@f { + reg = <0xf>; + + admaif15_ep: endpoint { + remote-endpoint = <&xbar_admaif15_ep>; + }; + }; + + admaif16_port: port@10 { + reg = <0x10>; + + admaif16_ep: endpoint { + remote-endpoint = <&xbar_admaif16_ep>; + }; + }; + + admaif17_port: port@11 { + reg = <0x11>; + + admaif17_ep: endpoint { + remote-endpoint = <&xbar_admaif17_ep>; + }; + }; + + admaif18_port: port@12 { + reg = <0x12>; + + admaif18_ep: endpoint { + remote-endpoint = <&xbar_admaif18_ep>; + }; + }; + + admaif19_port: port@13 { + reg = <0x13>; + + admaif19_ep: endpoint { + remote-endpoint = <&xbar_admaif19_ep>; + }; + }; + }; + }; + asrc@2910000 { status = "okay"; @@ -2184,7 +1267,7 @@ }; }; - asrc_out6_port: port@c { + asrc_out6_port: port@c { reg = <0xc>; asrc_out6_ep: endpoint { @@ -2193,6 +1276,923 @@ }; }; }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + xbar_admaif0_ep: endpoint { + remote-endpoint = <&admaif0_ep>; + }; + }; + + port@1 { + reg = <0x1>; + + xbar_admaif1_ep: endpoint { + remote-endpoint = <&admaif1_ep>; + }; + }; + + port@2 { + reg = <0x2>; + + xbar_admaif2_ep: endpoint { + remote-endpoint = <&admaif2_ep>; + }; + }; + + port@3 { + reg = <0x3>; + + xbar_admaif3_ep: endpoint { + remote-endpoint = <&admaif3_ep>; + }; + }; + + port@4 { + reg = <0x4>; + + xbar_admaif4_ep: endpoint { + remote-endpoint = <&admaif4_ep>; + }; + }; + + port@5 { + reg = <0x5>; + + xbar_admaif5_ep: endpoint { + remote-endpoint = <&admaif5_ep>; + }; + }; + + port@6 { + reg = <0x6>; + + xbar_admaif6_ep: endpoint { + remote-endpoint = <&admaif6_ep>; + }; + }; + + port@7 { + reg = <0x7>; + + xbar_admaif7_ep: endpoint { + remote-endpoint = <&admaif7_ep>; + }; + }; + + port@8 { + reg = <0x8>; + + xbar_admaif8_ep: endpoint { + remote-endpoint = <&admaif8_ep>; + }; + }; + + port@9 { + reg = <0x9>; + + xbar_admaif9_ep: endpoint { + remote-endpoint = <&admaif9_ep>; + }; + }; + + port@a { + reg = <0xa>; + + xbar_admaif10_ep: endpoint { + remote-endpoint = <&admaif10_ep>; + }; + }; + + port@b { + reg = <0xb>; + + xbar_admaif11_ep: endpoint { + remote-endpoint = <&admaif11_ep>; + }; + }; + + port@c { + reg = <0xc>; + + xbar_admaif12_ep: endpoint { + remote-endpoint = <&admaif12_ep>; + }; + }; + + port@d { + reg = <0xd>; + + xbar_admaif13_ep: endpoint { + remote-endpoint = <&admaif13_ep>; + }; + }; + + port@e { + reg = <0xe>; + + xbar_admaif14_ep: endpoint { + remote-endpoint = <&admaif14_ep>; + }; + }; + + port@f { + reg = <0xf>; + + xbar_admaif15_ep: endpoint { + remote-endpoint = <&admaif15_ep>; + }; + }; + + port@10 { + reg = <0x10>; + + xbar_admaif16_ep: endpoint { + remote-endpoint = <&admaif16_ep>; + }; + }; + + port@11 { + reg = <0x11>; + + xbar_admaif17_ep: endpoint { + remote-endpoint = <&admaif17_ep>; + }; + }; + + port@12 { + reg = <0x12>; + + xbar_admaif18_ep: endpoint { + remote-endpoint = <&admaif18_ep>; + }; + }; + + port@13 { + reg = <0x13>; + + xbar_admaif19_ep: endpoint { + remote-endpoint = <&admaif19_ep>; + }; + }; + + xbar_i2s1_port: port@14 { + reg = <0x14>; + + xbar_i2s1_ep: endpoint { + remote-endpoint = <&i2s1_cif_ep>; + }; + }; + + xbar_i2s2_port: port@15 { + reg = <0x15>; + + xbar_i2s2_ep: endpoint { + remote-endpoint = <&i2s2_cif_ep>; + }; + }; + + xbar_i2s3_port: port@16 { + reg = <0x16>; + + xbar_i2s3_ep: endpoint { + remote-endpoint = <&i2s3_cif_ep>; + }; + }; + + xbar_i2s4_port: port@17 { + reg = <0x17>; + + xbar_i2s4_ep: endpoint { + remote-endpoint = <&i2s4_cif_ep>; + }; + }; + + xbar_i2s5_port: port@18 { + reg = <0x18>; + + xbar_i2s5_ep: endpoint { + remote-endpoint = <&i2s5_cif_ep>; + }; + }; + + xbar_i2s6_port: port@19 { + reg = <0x19>; + + xbar_i2s6_ep: endpoint { + remote-endpoint = <&i2s6_cif_ep>; + }; + }; + + xbar_dmic1_port: port@1a { + reg = <0x1a>; + + xbar_dmic1_ep: endpoint { + remote-endpoint = <&dmic1_cif_ep>; + }; + }; + + xbar_dmic2_port: port@1b { + reg = <0x1b>; + + xbar_dmic2_ep: endpoint { + remote-endpoint = <&dmic2_cif_ep>; + }; + }; + + xbar_dmic3_port: port@1c { + reg = <0x1c>; + + xbar_dmic3_ep: endpoint { + remote-endpoint = <&dmic3_cif_ep>; + }; + }; + + xbar_dspk1_port: port@1e { + reg = <0x1e>; + + xbar_dspk1_ep: endpoint { + remote-endpoint = <&dspk1_cif_ep>; + }; + }; + + xbar_dspk2_port: port@1f { + reg = <0x1f>; + + xbar_dspk2_ep: endpoint { + remote-endpoint = <&dspk2_cif_ep>; + }; + }; + + xbar_sfc1_in_port: port@20 { + reg = <0x20>; + + xbar_sfc1_in_ep: endpoint { + remote-endpoint = <&sfc1_cif_in_ep>; + }; + }; + + port@21 { + reg = <0x21>; + + xbar_sfc1_out_ep: endpoint { + remote-endpoint = <&sfc1_cif_out_ep>; + }; + }; + + xbar_sfc2_in_port: port@22 { + reg = <0x22>; + + xbar_sfc2_in_ep: endpoint { + remote-endpoint = <&sfc2_cif_in_ep>; + }; + }; + + port@23 { + reg = <0x23>; + + xbar_sfc2_out_ep: endpoint { + remote-endpoint = <&sfc2_cif_out_ep>; + }; + }; + + xbar_sfc3_in_port: port@24 { + reg = <0x24>; + + xbar_sfc3_in_ep: endpoint { + remote-endpoint = <&sfc3_cif_in_ep>; + }; + }; + + port@25 { + reg = <0x25>; + + xbar_sfc3_out_ep: endpoint { + remote-endpoint = <&sfc3_cif_out_ep>; + }; + }; + + xbar_sfc4_in_port: port@26 { + reg = <0x26>; + + xbar_sfc4_in_ep: endpoint { + remote-endpoint = <&sfc4_cif_in_ep>; + }; + }; + + port@27 { + reg = <0x27>; + + xbar_sfc4_out_ep: endpoint { + remote-endpoint = <&sfc4_cif_out_ep>; + }; + }; + + xbar_mvc1_in_port: port@28 { + reg = <0x28>; + + xbar_mvc1_in_ep: endpoint { + remote-endpoint = <&mvc1_cif_in_ep>; + }; + }; + + port@29 { + reg = <0x29>; + + xbar_mvc1_out_ep: endpoint { + remote-endpoint = <&mvc1_cif_out_ep>; + }; + }; + + xbar_mvc2_in_port: port@2a { + reg = <0x2a>; + + xbar_mvc2_in_ep: endpoint { + remote-endpoint = <&mvc2_cif_in_ep>; + }; + }; + + port@2b { + reg = <0x2b>; + + xbar_mvc2_out_ep: endpoint { + remote-endpoint = <&mvc2_cif_out_ep>; + }; + }; + + xbar_amx1_in1_port: port@2c { + reg = <0x2c>; + + xbar_amx1_in1_ep: endpoint { + remote-endpoint = <&amx1_in1_ep>; + }; + }; + + xbar_amx1_in2_port: port@2d { + reg = <0x2d>; + + xbar_amx1_in2_ep: endpoint { + remote-endpoint = <&amx1_in2_ep>; + }; + }; + + xbar_amx1_in3_port: port@2e { + reg = <0x2e>; + + xbar_amx1_in3_ep: endpoint { + remote-endpoint = <&amx1_in3_ep>; + }; + }; + + xbar_amx1_in4_port: port@2f { + reg = <0x2f>; + + xbar_amx1_in4_ep: endpoint { + remote-endpoint = <&amx1_in4_ep>; + }; + }; + + port@30 { + reg = <0x30>; + + xbar_amx1_out_ep: endpoint { + remote-endpoint = <&amx1_out_ep>; + }; + }; + + xbar_amx2_in1_port: port@31 { + reg = <0x31>; + + xbar_amx2_in1_ep: endpoint { + remote-endpoint = <&amx2_in1_ep>; + }; + }; + + xbar_amx2_in2_port: port@32 { + reg = <0x32>; + + xbar_amx2_in2_ep: endpoint { + remote-endpoint = <&amx2_in2_ep>; + }; + }; + + xbar_amx2_in3_port: port@33 { + reg = <0x33>; + + xbar_amx2_in3_ep: endpoint { + remote-endpoint = <&amx2_in3_ep>; + }; + }; + + xbar_amx2_in4_port: port@34 { + reg = <0x34>; + + xbar_amx2_in4_ep: endpoint { + remote-endpoint = <&amx2_in4_ep>; + }; + }; + + port@35 { + reg = <0x35>; + + xbar_amx2_out_ep: endpoint { + remote-endpoint = <&amx2_out_ep>; + }; + }; + + xbar_amx3_in1_port: port@36 { + reg = <0x36>; + + xbar_amx3_in1_ep: endpoint { + remote-endpoint = <&amx3_in1_ep>; + }; + }; + + xbar_amx3_in2_port: port@37 { + reg = <0x37>; + + xbar_amx3_in2_ep: endpoint { + remote-endpoint = <&amx3_in2_ep>; + }; + }; + + xbar_amx3_in3_port: port@38 { + reg = <0x38>; + + xbar_amx3_in3_ep: endpoint { + remote-endpoint = <&amx3_in3_ep>; + }; + }; + + xbar_amx3_in4_port: port@39 { + reg = <0x39>; + + xbar_amx3_in4_ep: endpoint { + remote-endpoint = <&amx3_in4_ep>; + }; + }; + + port@3a { + reg = <0x3a>; + + xbar_amx3_out_ep: endpoint { + remote-endpoint = <&amx3_out_ep>; + }; + }; + + xbar_amx4_in1_port: port@3b { + reg = <0x3b>; + + xbar_amx4_in1_ep: endpoint { + remote-endpoint = <&amx4_in1_ep>; + }; + }; + + xbar_amx4_in2_port: port@3c { + reg = <0x3c>; + + xbar_amx4_in2_ep: endpoint { + remote-endpoint = <&amx4_in2_ep>; + }; + }; + + xbar_amx4_in3_port: port@3d { + reg = <0x3d>; + + xbar_amx4_in3_ep: endpoint { + remote-endpoint = <&amx4_in3_ep>; + }; + }; + + xbar_amx4_in4_port: port@3e { + reg = <0x3e>; + + xbar_amx4_in4_ep: endpoint { + remote-endpoint = <&amx4_in4_ep>; + }; + }; + + port@3f { + reg = <0x3f>; + + xbar_amx4_out_ep: endpoint { + remote-endpoint = <&amx4_out_ep>; + }; + }; + + xbar_adx1_in_port: port@40 { + reg = <0x40>; + + xbar_adx1_in_ep: endpoint { + remote-endpoint = <&adx1_in_ep>; + }; + }; + + port@41 { + reg = <0x41>; + + xbar_adx1_out1_ep: endpoint { + remote-endpoint = <&adx1_out1_ep>; + }; + }; + + port@42 { + reg = <0x42>; + + xbar_adx1_out2_ep: endpoint { + remote-endpoint = <&adx1_out2_ep>; + }; + }; + + port@43 { + reg = <0x43>; + + xbar_adx1_out3_ep: endpoint { + remote-endpoint = <&adx1_out3_ep>; + }; + }; + + port@44 { + reg = <0x44>; + + xbar_adx1_out4_ep: endpoint { + remote-endpoint = <&adx1_out4_ep>; + }; + }; + + xbar_adx2_in_port: port@45 { + reg = <0x45>; + + xbar_adx2_in_ep: endpoint { + remote-endpoint = <&adx2_in_ep>; + }; + }; + + port@46 { + reg = <0x46>; + + xbar_adx2_out1_ep: endpoint { + remote-endpoint = <&adx2_out1_ep>; + }; + }; + + port@47 { + reg = <0x47>; + + xbar_adx2_out2_ep: endpoint { + remote-endpoint = <&adx2_out2_ep>; + }; + }; + + port@48 { + reg = <0x48>; + + xbar_adx2_out3_ep: endpoint { + remote-endpoint = <&adx2_out3_ep>; + }; + }; + + port@49 { + reg = <0x49>; + + xbar_adx2_out4_ep: endpoint { + remote-endpoint = <&adx2_out4_ep>; + }; + }; + + xbar_adx3_in_port: port@4a { + reg = <0x4a>; + + xbar_adx3_in_ep: endpoint { + remote-endpoint = <&adx3_in_ep>; + }; + }; + + port@4b { + reg = <0x4b>; + + xbar_adx3_out1_ep: endpoint { + remote-endpoint = <&adx3_out1_ep>; + }; + }; + + port@4c { + reg = <0x4c>; + + xbar_adx3_out2_ep: endpoint { + remote-endpoint = <&adx3_out2_ep>; + }; + }; + + port@4d { + reg = <0x4d>; + + xbar_adx3_out3_ep: endpoint { + remote-endpoint = <&adx3_out3_ep>; + }; + }; + + port@4e { + reg = <0x4e>; + + xbar_adx3_out4_ep: endpoint { + remote-endpoint = <&adx3_out4_ep>; + }; + }; + + xbar_adx4_in_port: port@4f { + reg = <0x4f>; + + xbar_adx4_in_ep: endpoint { + remote-endpoint = <&adx4_in_ep>; + }; + }; + + port@50 { + reg = <0x50>; + + xbar_adx4_out1_ep: endpoint { + remote-endpoint = <&adx4_out1_ep>; + }; + }; + + port@51 { + reg = <0x51>; + + xbar_adx4_out2_ep: endpoint { + remote-endpoint = <&adx4_out2_ep>; + }; + }; + + port@52 { + reg = <0x52>; + + xbar_adx4_out3_ep: endpoint { + remote-endpoint = <&adx4_out3_ep>; + }; + }; + + port@53 { + reg = <0x53>; + + xbar_adx4_out4_ep: endpoint { + remote-endpoint = <&adx4_out4_ep>; + }; + }; + + xbar_mixer_in1_port: port@54 { + reg = <0x54>; + + xbar_mixer_in1_ep: endpoint { + remote-endpoint = <&mixer_in1_ep>; + }; + }; + + xbar_mixer_in2_port: port@55 { + reg = <0x55>; + + xbar_mixer_in2_ep: endpoint { + remote-endpoint = <&mixer_in2_ep>; + }; + }; + + xbar_mixer_in3_port: port@56 { + reg = <0x56>; + + xbar_mixer_in3_ep: endpoint { + remote-endpoint = <&mixer_in3_ep>; + }; + }; + + xbar_mixer_in4_port: port@57 { + reg = <0x57>; + + xbar_mixer_in4_ep: endpoint { + remote-endpoint = <&mixer_in4_ep>; + }; + }; + + xbar_mixer_in5_port: port@58 { + reg = <0x58>; + + xbar_mixer_in5_ep: endpoint { + remote-endpoint = <&mixer_in5_ep>; + }; + }; + + xbar_mixer_in6_port: port@59 { + reg = <0x59>; + + xbar_mixer_in6_ep: endpoint { + remote-endpoint = <&mixer_in6_ep>; + }; + }; + + xbar_mixer_in7_port: port@5a { + reg = <0x5a>; + + xbar_mixer_in7_ep: endpoint { + remote-endpoint = <&mixer_in7_ep>; + }; + }; + + xbar_mixer_in8_port: port@5b { + reg = <0x5b>; + + xbar_mixer_in8_ep: endpoint { + remote-endpoint = <&mixer_in8_ep>; + }; + }; + + xbar_mixer_in9_port: port@5c { + reg = <0x5c>; + + xbar_mixer_in9_ep: endpoint { + remote-endpoint = <&mixer_in9_ep>; + }; + }; + + xbar_mixer_in10_port: port@5d { + reg = <0x5d>; + + xbar_mixer_in10_ep: endpoint { + remote-endpoint = <&mixer_in10_ep>; + }; + }; + + port@5e { + reg = <0x5e>; + + xbar_mixer_out1_ep: endpoint { + remote-endpoint = <&mixer_out1_ep>; + }; + }; + + port@5f { + reg = <0x5f>; + + xbar_mixer_out2_ep: endpoint { + remote-endpoint = <&mixer_out2_ep>; + }; + }; + + port@60 { + reg = <0x60>; + + xbar_mixer_out3_ep: endpoint { + remote-endpoint = <&mixer_out3_ep>; + }; + }; + + port@61 { + reg = <0x61>; + + xbar_mixer_out4_ep: endpoint { + remote-endpoint = <&mixer_out4_ep>; + }; + }; + + port@62 { + reg = <0x62>; + + xbar_mixer_out5_ep: endpoint { + remote-endpoint = <&mixer_out5_ep>; + }; + }; + + xbar_asrc_in1_port: port@63 { + reg = <0x63>; + + xbar_asrc_in1_ep: endpoint { + remote-endpoint = <&asrc_in1_ep>; + }; + }; + + port@64 { + reg = <0x64>; + + xbar_asrc_out1_ep: endpoint { + remote-endpoint = <&asrc_out1_ep>; + }; + }; + + xbar_asrc_in2_port: port@65 { + reg = <0x65>; + + xbar_asrc_in2_ep: endpoint { + remote-endpoint = <&asrc_in2_ep>; + }; + }; + + port@66 { + reg = <0x66>; + + xbar_asrc_out2_ep: endpoint { + remote-endpoint = <&asrc_out2_ep>; + }; + }; + + xbar_asrc_in3_port: port@67 { + reg = <0x67>; + + xbar_asrc_in3_ep: endpoint { + remote-endpoint = <&asrc_in3_ep>; + }; + }; + + port@68 { + reg = <0x68>; + + xbar_asrc_out3_ep: endpoint { + remote-endpoint = <&asrc_out3_ep>; + }; + }; + + xbar_asrc_in4_port: port@69 { + reg = <0x69>; + + xbar_asrc_in4_ep: endpoint { + remote-endpoint = <&asrc_in4_ep>; + }; + }; + + port@6a { + reg = <0x6a>; + + xbar_asrc_out4_ep: endpoint { + remote-endpoint = <&asrc_out4_ep>; + }; + }; + + xbar_asrc_in5_port: port@6b { + reg = <0x6b>; + + xbar_asrc_in5_ep: endpoint { + remote-endpoint = <&asrc_in5_ep>; + }; + }; + + port@6c { + reg = <0x6c>; + + xbar_asrc_out5_ep: endpoint { + remote-endpoint = <&asrc_out5_ep>; + }; + }; + + xbar_asrc_in6_port: port@6d { + reg = <0x6d>; + + xbar_asrc_in6_ep: endpoint { + remote-endpoint = <&asrc_in6_ep>; + }; + }; + + port@6e { + reg = <0x6e>; + + xbar_asrc_out6_ep: endpoint { + remote-endpoint = <&asrc_out6_ep>; + }; + }; + + xbar_asrc_in7_port: port@6f { + reg = <0x6f>; + + xbar_asrc_in7_ep: endpoint { + remote-endpoint = <&asrc_in7_ep>; + }; + }; + + xbar_ope1_in_port: port@70 { + reg = <0x70>; + + xbar_ope1_in_ep: endpoint { + remote-endpoint = <&ope1_cif_in_ep>; + }; + }; + + port@71 { + reg = <0x71>; + + xbar_ope1_out_ep: endpoint { + remote-endpoint = <&ope1_cif_out_ep>; + }; + }; + }; + }; + + dma-controller@2930000 { + status = "okay"; + }; + + interrupt-controller@2a40000 { + status = "okay"; }; }; @@ -2283,6 +2283,10 @@ vmmc-supply = <&vdd_sd>; }; + sata@3507000 { + status = "okay"; + }; + hda@3510000 { nvidia,model = "NVIDIA Jetson TX2 HDA"; status = "okay"; @@ -2471,10 +2475,6 @@ }; }; - sata@3507000 { - status = "okay"; - }; - gpio-keys { compatible = "gpio-keys"; @@ -2489,21 +2489,21 @@ wakeup-source; }; - key-volume-up { - label = "Volume Up"; - gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 1) + key-volume-down { + label = "Volume Down"; + gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 2) GPIO_ACTIVE_LOW>; linux,input-type = <EV_KEY>; - linux,code = <KEY_VOLUMEUP>; + linux,code = <KEY_VOLUMEDOWN>; debounce-interval = <10>; }; - key-volume-down { - label = "Volume Down"; - gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 2) + key-volume-up { + label = "Volume Up"; + gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 1) GPIO_ACTIVE_LOW>; linux,input-type = <EV_KEY>; - linux,code = <KEY_VOLUMEDOWN>; + linux,code = <KEY_VOLUMEUP>; debounce-interval = <10>; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi index aff857df25cf..a4264ea41728 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi @@ -190,32 +190,6 @@ nvidia,invert-interrupt; }; - cpus { - cpu@0 { - enable-method = "psci"; - }; - - cpu@1 { - enable-method = "psci"; - }; - - cpu@2 { - enable-method = "psci"; - }; - - cpu@3 { - enable-method = "psci"; - }; - - cpu@4 { - enable-method = "psci"; - }; - - cpu@5 { - enable-method = "psci"; - }; - }; - bpmp { i2c { status = "okay"; @@ -235,6 +209,23 @@ pinctrl-names = "default"; pinctrl-0 = <&max77620_default>; + fps { + fps0 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; + maxim,shutdown-fps-time-period-us = <640>; + }; + + fps1 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; + maxim,shutdown-fps-time-period-us = <640>; + }; + + fps2 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; + maxim,shutdown-fps-time-period-us = <640>; + }; + }; + max77620_default: pinmux { gpio0 { pins = "gpio0"; @@ -284,23 +275,6 @@ }; }; - fps { - fps0 { - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; - maxim,shutdown-fps-time-period-us = <640>; - }; - - fps1 { - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; - maxim,shutdown-fps-time-period-us = <640>; - }; - - fps2 { - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; - maxim,shutdown-fps-time-period-us = <640>; - }; - }; - regulators { in-sd0-supply = <&vdd_5v0_sys>; in-sd1-supply = <&vdd_5v0_sys>; @@ -387,6 +361,32 @@ }; }; + cpus { + cpu@0 { + enable-method = "psci"; + }; + + cpu@1 { + enable-method = "psci"; + }; + + cpu@2 { + enable-method = "psci"; + }; + + cpu@3 { + enable-method = "psci"; + }; + + cpu@4 { + enable-method = "psci"; + }; + + cpu@5 { + enable-method = "psci"; + }; + }; + psci { compatible = "arm,psci-1.0"; status = "okay"; diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts b/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts index 3e83a4d52eb1..26f71651933d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts @@ -56,6 +56,490 @@ }; }; + aconnect@2900000 { + status = "okay"; + + ahub@2900800 { + status = "okay"; + + i2s@2901000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s1_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s1_ep>; + }; + }; + + i2s1_port: port@1 { + reg = <1>; + + i2s1_dap_ep: endpoint { + dai-format = "i2s"; + /* Placeholder for external Codec */ + }; + }; + }; + }; + + i2s@2901200 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s3_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s3_ep>; + }; + }; + + i2s3_port: port@1 { + reg = <1>; + + i2s3_dap_ep: endpoint { + dai-format = "i2s"; + /* Placeholder for external Codec */ + }; + }; + }; + }; + + dmic@2904000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dmic1_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic1_ep>; + }; + }; + + dmic1_port: port@1 { + reg = <1>; + + dmic1_dap_ep: endpoint { + /* Place holder for external Codec */ + }; + }; + }; + }; + + dmic@2904100 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dmic2_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic2_ep>; + }; + }; + + dmic2_port: port@1 { + reg = <1>; + + dmic2_dap_ep: endpoint { + /* Place holder for external Codec */ + }; + }; + }; + }; + + admaif@290f000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + admaif0_port: port@0 { + reg = <0x0>; + + admaif0_ep: endpoint { + remote-endpoint = <&xbar_admaif0_ep>; + }; + }; + + admaif1_port: port@1 { + reg = <0x1>; + + admaif1_ep: endpoint { + remote-endpoint = <&xbar_admaif1_ep>; + }; + }; + + admaif2_port: port@2 { + reg = <0x2>; + + admaif2_ep: endpoint { + remote-endpoint = <&xbar_admaif2_ep>; + }; + }; + + admaif3_port: port@3 { + reg = <0x3>; + + admaif3_ep: endpoint { + remote-endpoint = <&xbar_admaif3_ep>; + }; + }; + + admaif4_port: port@4 { + reg = <0x4>; + + admaif4_ep: endpoint { + remote-endpoint = <&xbar_admaif4_ep>; + }; + }; + + admaif5_port: port@5 { + reg = <0x5>; + + admaif5_ep: endpoint { + remote-endpoint = <&xbar_admaif5_ep>; + }; + }; + + admaif6_port: port@6 { + reg = <0x6>; + + admaif6_ep: endpoint { + remote-endpoint = <&xbar_admaif6_ep>; + }; + }; + + admaif7_port: port@7 { + reg = <0x7>; + + admaif7_ep: endpoint { + remote-endpoint = <&xbar_admaif7_ep>; + }; + }; + + admaif8_port: port@8 { + reg = <0x8>; + + admaif8_ep: endpoint { + remote-endpoint = <&xbar_admaif8_ep>; + }; + }; + + admaif9_port: port@9 { + reg = <0x9>; + + admaif9_ep: endpoint { + remote-endpoint = <&xbar_admaif9_ep>; + }; + }; + + admaif10_port: port@a { + reg = <0xa>; + + admaif10_ep: endpoint { + remote-endpoint = <&xbar_admaif10_ep>; + }; + }; + + admaif11_port: port@b { + reg = <0xb>; + + admaif11_ep: endpoint { + remote-endpoint = <&xbar_admaif11_ep>; + }; + }; + + admaif12_port: port@c { + reg = <0xc>; + + admaif12_ep: endpoint { + remote-endpoint = <&xbar_admaif12_ep>; + }; + }; + + admaif13_port: port@d { + reg = <0xd>; + + admaif13_ep: endpoint { + remote-endpoint = <&xbar_admaif13_ep>; + }; + }; + + admaif14_port: port@e { + reg = <0xe>; + + admaif14_ep: endpoint { + remote-endpoint = <&xbar_admaif14_ep>; + }; + }; + + admaif15_port: port@f { + reg = <0xf>; + + admaif15_ep: endpoint { + remote-endpoint = <&xbar_admaif15_ep>; + }; + }; + + admaif16_port: port@10 { + reg = <0x10>; + + admaif16_ep: endpoint { + remote-endpoint = <&xbar_admaif16_ep>; + }; + }; + + admaif17_port: port@11 { + reg = <0x11>; + + admaif17_ep: endpoint { + remote-endpoint = <&xbar_admaif17_ep>; + }; + }; + + admaif18_port: port@12 { + reg = <0x12>; + + admaif18_ep: endpoint { + remote-endpoint = <&xbar_admaif18_ep>; + }; + }; + + admaif19_port: port@13 { + reg = <0x13>; + + admaif19_ep: endpoint { + remote-endpoint = <&xbar_admaif19_ep>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + xbar_admaif0_ep: endpoint { + remote-endpoint = <&admaif0_ep>; + }; + }; + + port@1 { + reg = <0x1>; + + xbar_admaif1_ep: endpoint { + remote-endpoint = <&admaif1_ep>; + }; + }; + + port@2 { + reg = <0x2>; + + xbar_admaif2_ep: endpoint { + remote-endpoint = <&admaif2_ep>; + }; + }; + + port@3 { + reg = <0x3>; + + xbar_admaif3_ep: endpoint { + remote-endpoint = <&admaif3_ep>; + }; + }; + + port@4 { + reg = <0x4>; + + xbar_admaif4_ep: endpoint { + remote-endpoint = <&admaif4_ep>; + }; + }; + + port@5 { + reg = <0x5>; + + xbar_admaif5_ep: endpoint { + remote-endpoint = <&admaif5_ep>; + }; + }; + + port@6 { + reg = <0x6>; + + xbar_admaif6_ep: endpoint { + remote-endpoint = <&admaif6_ep>; + }; + }; + + port@7 { + reg = <0x7>; + + xbar_admaif7_ep: endpoint { + remote-endpoint = <&admaif7_ep>; + }; + }; + + port@8 { + reg = <0x8>; + + xbar_admaif8_ep: endpoint { + remote-endpoint = <&admaif8_ep>; + }; + }; + + port@9 { + reg = <0x9>; + + xbar_admaif9_ep: endpoint { + remote-endpoint = <&admaif9_ep>; + }; + }; + + port@a { + reg = <0xa>; + + xbar_admaif10_ep: endpoint { + remote-endpoint = <&admaif10_ep>; + }; + }; + + port@b { + reg = <0xb>; + + xbar_admaif11_ep: endpoint { + remote-endpoint = <&admaif11_ep>; + }; + }; + + port@c { + reg = <0xc>; + + xbar_admaif12_ep: endpoint { + remote-endpoint = <&admaif12_ep>; + }; + }; + + port@d { + reg = <0xd>; + + xbar_admaif13_ep: endpoint { + remote-endpoint = <&admaif13_ep>; + }; + }; + + port@e { + reg = <0xe>; + + xbar_admaif14_ep: endpoint { + remote-endpoint = <&admaif14_ep>; + }; + }; + + port@f { + reg = <0xf>; + + xbar_admaif15_ep: endpoint { + remote-endpoint = <&admaif15_ep>; + }; + }; + + port@10 { + reg = <0x10>; + + xbar_admaif16_ep: endpoint { + remote-endpoint = <&admaif16_ep>; + }; + }; + + port@11 { + reg = <0x11>; + + xbar_admaif17_ep: endpoint { + remote-endpoint = <&admaif17_ep>; + }; + }; + + port@12 { + reg = <0x12>; + + xbar_admaif18_ep: endpoint { + remote-endpoint = <&admaif18_ep>; + }; + }; + + port@13 { + reg = <0x13>; + + xbar_admaif19_ep: endpoint { + remote-endpoint = <&admaif19_ep>; + }; + }; + + xbar_i2s1_port: port@14 { + reg = <0x14>; + + xbar_i2s1_ep: endpoint { + remote-endpoint = <&i2s1_cif_ep>; + }; + }; + + xbar_i2s3_port: port@16 { + reg = <0x16>; + + xbar_i2s3_ep: endpoint { + remote-endpoint = <&i2s3_cif_ep>; + }; + }; + + xbar_dmic1_port: port@1a { + reg = <0x1a>; + + xbar_dmic1_ep: endpoint { + remote-endpoint = <&dmic1_cif_ep>; + }; + }; + + xbar_dmic2_port: port@1b { + reg = <0x1b>; + + xbar_dmic2_ep: endpoint { + remote-endpoint = <&dmic2_cif_ep>; + }; + }; + }; + }; + + dma-controller@2930000 { + status = "okay"; + }; + + interrupt-controller@2a40000 { + status = "okay"; + }; + }; + memory-controller@2c00000 { status = "okay"; }; @@ -349,73 +833,6 @@ status = "okay"; }; - fan: pwm-fan { - compatible = "pwm-fan"; - pwms = <&pwm4 0 45334>; - - cooling-levels = <0 64 128 255>; - #cooling-cells = <2>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-power { - label = "Power"; - gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 0) - GPIO_ACTIVE_LOW>; - linux,input-type = <EV_KEY>; - linux,code = <KEY_POWER>; - debounce-interval = <10>; - wakeup-event-action = <EV_ACT_ASSERTED>; - wakeup-source; - }; - - key-volume-up { - label = "Volume Up"; - gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 1) - GPIO_ACTIVE_LOW>; - linux,input-type = <EV_KEY>; - linux,code = <KEY_VOLUMEUP>; - debounce-interval = <10>; - }; - - key-volume-down { - label = "Volume Down"; - gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 2) - GPIO_ACTIVE_LOW>; - linux,input-type = <EV_KEY>; - linux,code = <KEY_VOLUMEDOWN>; - debounce-interval = <10>; - }; - }; - - cpus { - cpu@0 { - enable-method = "psci"; - }; - - cpu@1 { - enable-method = "psci"; - }; - - cpu@2 { - enable-method = "psci"; - }; - - cpu@3 { - enable-method = "psci"; - }; - - cpu@4 { - enable-method = "psci"; - }; - - cpu@5 { - enable-method = "psci"; - }; - }; - bpmp { i2c { status = "okay"; @@ -435,6 +852,23 @@ pinctrl-names = "default"; pinctrl-0 = <&max77620_default>; + fps { + fps0 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; + maxim,shutdown-fps-time-period-us = <640>; + }; + + fps1 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; + maxim,shutdown-fps-time-period-us = <640>; + }; + + fps2 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; + maxim,shutdown-fps-time-period-us = <640>; + }; + }; + max77620_default: pinmux { gpio0 { pins = "gpio0"; @@ -484,23 +918,6 @@ }; }; - fps { - fps0 { - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; - maxim,shutdown-fps-time-period-us = <640>; - }; - - fps1 { - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; - maxim,shutdown-fps-time-period-us = <640>; - }; - - fps2 { - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; - maxim,shutdown-fps-time-period-us = <640>; - }; - }; - regulators { in-sd0-supply = <&vdd_5v0_sys>; in-sd1-supply = <&vdd_5v0_sys>; @@ -587,12 +1004,79 @@ }; }; + cpus { + cpu@0 { + enable-method = "psci"; + }; + + cpu@1 { + enable-method = "psci"; + }; + + cpu@2 { + enable-method = "psci"; + }; + + cpu@3 { + enable-method = "psci"; + }; + + cpu@4 { + enable-method = "psci"; + }; + + cpu@5 { + enable-method = "psci"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 0) + GPIO_ACTIVE_LOW>; + linux,input-type = <EV_KEY>; + linux,code = <KEY_POWER>; + debounce-interval = <10>; + wakeup-event-action = <EV_ACT_ASSERTED>; + wakeup-source; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 2) + GPIO_ACTIVE_LOW>; + linux,input-type = <EV_KEY>; + linux,code = <KEY_VOLUMEDOWN>; + debounce-interval = <10>; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 1) + GPIO_ACTIVE_LOW>; + linux,input-type = <EV_KEY>; + linux,code = <KEY_VOLUMEUP>; + debounce-interval = <10>; + }; + }; + psci { compatible = "arm,psci-1.0"; status = "okay"; method = "smc"; }; + fan: pwm-fan { + compatible = "pwm-fan"; + pwms = <&pwm4 0 45334>; + + cooling-levels = <0 64 128 255>; + #cooling-cells = <2>; + }; + gnd: regulator-gnd { compatible = "regulator-fixed"; regulator-name = "GND"; @@ -632,6 +1116,26 @@ vin-supply = <&vdd_5v0_sys>; }; + sound { + compatible = "nvidia,tegra186-audio-graph-card"; + status = "okay"; + + dais = /* FE */ + <&admaif0_port>, <&admaif1_port>, <&admaif2_port>, <&admaif3_port>, + <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, <&admaif7_port>, + <&admaif8_port>, <&admaif9_port>, <&admaif10_port>, <&admaif11_port>, + <&admaif12_port>, <&admaif13_port>, <&admaif14_port>, <&admaif15_port>, + <&admaif16_port>, <&admaif17_port>, <&admaif18_port>, <&admaif19_port>, + /* Router */ + <&xbar_i2s1_port>, <&xbar_i2s3_port>, + <&xbar_dmic1_port>, <&xbar_dmic2_port>, + /* I/O */ + <&i2s1_port>, <&i2s3_port>, + <&dmic1_port>, <&dmic2_port>; + + label = "NVIDIA Jetson TX2 NX APE"; + }; + thermal-zones { cpu-thermal { polling-delay = <0>; @@ -715,508 +1219,4 @@ }; }; }; - - aconnect@2900000 { - status = "okay"; - - dma-controller@2930000 { - status = "okay"; - }; - - interrupt-controller@2a40000 { - status = "okay"; - }; - - ahub@2900800 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0x0>; - - xbar_admaif0_ep: endpoint { - remote-endpoint = <&admaif0_ep>; - }; - }; - - port@1 { - reg = <0x1>; - - xbar_admaif1_ep: endpoint { - remote-endpoint = <&admaif1_ep>; - }; - }; - - port@2 { - reg = <0x2>; - - xbar_admaif2_ep: endpoint { - remote-endpoint = <&admaif2_ep>; - }; - }; - - port@3 { - reg = <0x3>; - - xbar_admaif3_ep: endpoint { - remote-endpoint = <&admaif3_ep>; - }; - }; - - port@4 { - reg = <0x4>; - - xbar_admaif4_ep: endpoint { - remote-endpoint = <&admaif4_ep>; - }; - }; - - port@5 { - reg = <0x5>; - - xbar_admaif5_ep: endpoint { - remote-endpoint = <&admaif5_ep>; - }; - }; - - port@6 { - reg = <0x6>; - - xbar_admaif6_ep: endpoint { - remote-endpoint = <&admaif6_ep>; - }; - }; - - port@7 { - reg = <0x7>; - - xbar_admaif7_ep: endpoint { - remote-endpoint = <&admaif7_ep>; - }; - }; - - port@8 { - reg = <0x8>; - - xbar_admaif8_ep: endpoint { - remote-endpoint = <&admaif8_ep>; - }; - }; - - port@9 { - reg = <0x9>; - - xbar_admaif9_ep: endpoint { - remote-endpoint = <&admaif9_ep>; - }; - }; - - port@a { - reg = <0xa>; - - xbar_admaif10_ep: endpoint { - remote-endpoint = <&admaif10_ep>; - }; - }; - - port@b { - reg = <0xb>; - - xbar_admaif11_ep: endpoint { - remote-endpoint = <&admaif11_ep>; - }; - }; - - port@c { - reg = <0xc>; - - xbar_admaif12_ep: endpoint { - remote-endpoint = <&admaif12_ep>; - }; - }; - - port@d { - reg = <0xd>; - - xbar_admaif13_ep: endpoint { - remote-endpoint = <&admaif13_ep>; - }; - }; - - port@e { - reg = <0xe>; - - xbar_admaif14_ep: endpoint { - remote-endpoint = <&admaif14_ep>; - }; - }; - - port@f { - reg = <0xf>; - - xbar_admaif15_ep: endpoint { - remote-endpoint = <&admaif15_ep>; - }; - }; - - port@10 { - reg = <0x10>; - - xbar_admaif16_ep: endpoint { - remote-endpoint = <&admaif16_ep>; - }; - }; - - port@11 { - reg = <0x11>; - - xbar_admaif17_ep: endpoint { - remote-endpoint = <&admaif17_ep>; - }; - }; - - port@12 { - reg = <0x12>; - - xbar_admaif18_ep: endpoint { - remote-endpoint = <&admaif18_ep>; - }; - }; - - port@13 { - reg = <0x13>; - - xbar_admaif19_ep: endpoint { - remote-endpoint = <&admaif19_ep>; - }; - }; - - xbar_i2s1_port: port@14 { - reg = <0x14>; - - xbar_i2s1_ep: endpoint { - remote-endpoint = <&i2s1_cif_ep>; - }; - }; - - xbar_i2s3_port: port@16 { - reg = <0x16>; - - xbar_i2s3_ep: endpoint { - remote-endpoint = <&i2s3_cif_ep>; - }; - }; - - xbar_dmic1_port: port@1a { - reg = <0x1a>; - - xbar_dmic1_ep: endpoint { - remote-endpoint = <&dmic1_cif_ep>; - }; - }; - - xbar_dmic2_port: port@1b { - reg = <0x1b>; - - xbar_dmic2_ep: endpoint { - remote-endpoint = <&dmic2_cif_ep>; - }; - }; - }; - - admaif@290f000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - admaif0_port: port@0 { - reg = <0x0>; - - admaif0_ep: endpoint { - remote-endpoint = <&xbar_admaif0_ep>; - }; - }; - - admaif1_port: port@1 { - reg = <0x1>; - - admaif1_ep: endpoint { - remote-endpoint = <&xbar_admaif1_ep>; - }; - }; - - admaif2_port: port@2 { - reg = <0x2>; - - admaif2_ep: endpoint { - remote-endpoint = <&xbar_admaif2_ep>; - }; - }; - - admaif3_port: port@3 { - reg = <0x3>; - - admaif3_ep: endpoint { - remote-endpoint = <&xbar_admaif3_ep>; - }; - }; - - admaif4_port: port@4 { - reg = <0x4>; - - admaif4_ep: endpoint { - remote-endpoint = <&xbar_admaif4_ep>; - }; - }; - - admaif5_port: port@5 { - reg = <0x5>; - - admaif5_ep: endpoint { - remote-endpoint = <&xbar_admaif5_ep>; - }; - }; - - admaif6_port: port@6 { - reg = <0x6>; - - admaif6_ep: endpoint { - remote-endpoint = <&xbar_admaif6_ep>; - }; - }; - - admaif7_port: port@7 { - reg = <0x7>; - - admaif7_ep: endpoint { - remote-endpoint = <&xbar_admaif7_ep>; - }; - }; - - admaif8_port: port@8 { - reg = <0x8>; - - admaif8_ep: endpoint { - remote-endpoint = <&xbar_admaif8_ep>; - }; - }; - - admaif9_port: port@9 { - reg = <0x9>; - - admaif9_ep: endpoint { - remote-endpoint = <&xbar_admaif9_ep>; - }; - }; - - admaif10_port: port@a { - reg = <0xa>; - - admaif10_ep: endpoint { - remote-endpoint = <&xbar_admaif10_ep>; - }; - }; - - admaif11_port: port@b { - reg = <0xb>; - - admaif11_ep: endpoint { - remote-endpoint = <&xbar_admaif11_ep>; - }; - }; - - admaif12_port: port@c { - reg = <0xc>; - - admaif12_ep: endpoint { - remote-endpoint = <&xbar_admaif12_ep>; - }; - }; - - admaif13_port: port@d { - reg = <0xd>; - - admaif13_ep: endpoint { - remote-endpoint = <&xbar_admaif13_ep>; - }; - }; - - admaif14_port: port@e { - reg = <0xe>; - - admaif14_ep: endpoint { - remote-endpoint = <&xbar_admaif14_ep>; - }; - }; - - admaif15_port: port@f { - reg = <0xf>; - - admaif15_ep: endpoint { - remote-endpoint = <&xbar_admaif15_ep>; - }; - }; - - admaif16_port: port@10 { - reg = <0x10>; - - admaif16_ep: endpoint { - remote-endpoint = <&xbar_admaif16_ep>; - }; - }; - - admaif17_port: port@11 { - reg = <0x11>; - - admaif17_ep: endpoint { - remote-endpoint = <&xbar_admaif17_ep>; - }; - }; - - admaif18_port: port@12 { - reg = <0x12>; - - admaif18_ep: endpoint { - remote-endpoint = <&xbar_admaif18_ep>; - }; - }; - - admaif19_port: port@13 { - reg = <0x13>; - - admaif19_ep: endpoint { - remote-endpoint = <&xbar_admaif19_ep>; - }; - }; - }; - }; - - i2s@2901000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2s1_cif_ep: endpoint { - remote-endpoint = <&xbar_i2s1_ep>; - }; - }; - - i2s1_port: port@1 { - reg = <1>; - - i2s1_dap_ep: endpoint { - dai-format = "i2s"; - /* Placeholder for external Codec */ - }; - }; - }; - }; - - i2s@2901200 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2s3_cif_ep: endpoint { - remote-endpoint = <&xbar_i2s3_ep>; - }; - }; - - i2s3_port: port@1 { - reg = <1>; - - i2s3_dap_ep: endpoint { - dai-format = "i2s"; - /* Placeholder for external Codec */ - }; - }; - }; - }; - - dmic@2904000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dmic1_cif_ep: endpoint { - remote-endpoint = <&xbar_dmic1_ep>; - }; - }; - - dmic1_port: port@1 { - reg = <1>; - - dmic1_dap_ep: endpoint { - /* Place holder for external Codec */ - }; - }; - }; - }; - - dmic@2904100 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dmic2_cif_ep: endpoint { - remote-endpoint = <&xbar_dmic2_ep>; - }; - }; - - dmic2_port: port@1 { - reg = <1>; - - dmic2_dap_ep: endpoint { - /* Place holder for external Codec */ - }; - }; - }; - }; - }; - }; - - sound { - compatible = "nvidia,tegra186-audio-graph-card"; - status = "okay"; - - dais = /* FE */ - <&admaif0_port>, <&admaif1_port>, <&admaif2_port>, <&admaif3_port>, - <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, <&admaif7_port>, - <&admaif8_port>, <&admaif9_port>, <&admaif10_port>, <&admaif11_port>, - <&admaif12_port>, <&admaif13_port>, <&admaif14_port>, <&admaif15_port>, - <&admaif16_port>, <&admaif17_port>, <&admaif18_port>, <&admaif19_port>, - /* Router */ - <&xbar_i2s1_port>, <&xbar_i2s3_port>, - <&xbar_dmic1_port>, <&xbar_dmic2_port>, - /* I/O */ - <&i2s1_port>, <&i2s3_port>, - <&dmic1_port>, <&dmic2_port>; - - label = "NVIDIA Jetson TX2 NX APE"; - }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index b3f1494c02c1..efc450821398 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -129,62 +129,6 @@ ranges = <0x02900000 0x0 0x02900000 0x200000>; status = "disabled"; - adma: dma-controller@2930000 { - compatible = "nvidia,tegra186-adma"; - reg = <0x02930000 0x20000>; - interrupt-parent = <&agic>; - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - clocks = <&bpmp TEGRA186_CLK_AHUB>; - clock-names = "d_audio"; - status = "disabled"; - }; - - agic: interrupt-controller@2a40000 { - compatible = "nvidia,tegra186-agic", - "nvidia,tegra210-agic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x02a41000 0x1000>, - <0x02a42000 0x2000>; - interrupts = <GIC_SPI 145 - (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; - clocks = <&bpmp TEGRA186_CLK_APE>; - clock-names = "clk"; - status = "disabled"; - }; - tegra_ahub: ahub@2900800 { compatible = "nvidia,tegra186-ahub"; reg = <0x02900800 0x800>; @@ -197,52 +141,6 @@ ranges = <0x02900800 0x02900800 0x11800>; status = "disabled"; - tegra_admaif: admaif@290f000 { - compatible = "nvidia,tegra186-admaif"; - reg = <0x0290f000 0x1000>; - dmas = <&adma 1>, <&adma 1>, - <&adma 2>, <&adma 2>, - <&adma 3>, <&adma 3>, - <&adma 4>, <&adma 4>, - <&adma 5>, <&adma 5>, - <&adma 6>, <&adma 6>, - <&adma 7>, <&adma 7>, - <&adma 8>, <&adma 8>, - <&adma 9>, <&adma 9>, - <&adma 10>, <&adma 10>, - <&adma 11>, <&adma 11>, - <&adma 12>, <&adma 12>, - <&adma 13>, <&adma 13>, - <&adma 14>, <&adma 14>, - <&adma 15>, <&adma 15>, - <&adma 16>, <&adma 16>, - <&adma 17>, <&adma 17>, - <&adma 18>, <&adma 18>, - <&adma 19>, <&adma 19>, - <&adma 20>, <&adma 20>; - dma-names = "rx1", "tx1", - "rx2", "tx2", - "rx3", "tx3", - "rx4", "tx4", - "rx5", "tx5", - "rx6", "tx6", - "rx7", "tx7", - "rx8", "tx8", - "rx9", "tx9", - "rx10", "tx10", - "rx11", "tx11", - "rx12", "tx12", - "rx13", "tx13", - "rx14", "tx14", - "rx15", "tx15", - "rx16", "tx16", - "rx17", "tx17", - "rx18", "tx18", - "rx19", "tx19", - "rx20", "tx20"; - status = "disabled"; - }; - tegra_i2s1: i2s@2901000 { compatible = "nvidia,tegra186-i2s", "nvidia,tegra210-i2s"; @@ -327,78 +225,6 @@ status = "disabled"; }; - tegra_dmic1: dmic@2904000 { - compatible = "nvidia,tegra210-dmic"; - reg = <0x2904000 0x100>; - clocks = <&bpmp TEGRA186_CLK_DMIC1>; - clock-names = "dmic"; - assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>; - assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; - assigned-clock-rates = <3072000>; - sound-name-prefix = "DMIC1"; - status = "disabled"; - }; - - tegra_dmic2: dmic@2904100 { - compatible = "nvidia,tegra210-dmic"; - reg = <0x2904100 0x100>; - clocks = <&bpmp TEGRA186_CLK_DMIC2>; - clock-names = "dmic"; - assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>; - assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; - assigned-clock-rates = <3072000>; - sound-name-prefix = "DMIC2"; - status = "disabled"; - }; - - tegra_dmic3: dmic@2904200 { - compatible = "nvidia,tegra210-dmic"; - reg = <0x2904200 0x100>; - clocks = <&bpmp TEGRA186_CLK_DMIC3>; - clock-names = "dmic"; - assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>; - assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; - assigned-clock-rates = <3072000>; - sound-name-prefix = "DMIC3"; - status = "disabled"; - }; - - tegra_dmic4: dmic@2904300 { - compatible = "nvidia,tegra210-dmic"; - reg = <0x2904300 0x100>; - clocks = <&bpmp TEGRA186_CLK_DMIC4>; - clock-names = "dmic"; - assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>; - assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; - assigned-clock-rates = <3072000>; - sound-name-prefix = "DMIC4"; - status = "disabled"; - }; - - tegra_dspk1: dspk@2905000 { - compatible = "nvidia,tegra186-dspk"; - reg = <0x2905000 0x100>; - clocks = <&bpmp TEGRA186_CLK_DSPK1>; - clock-names = "dspk"; - assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>; - assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; - assigned-clock-rates = <12288000>; - sound-name-prefix = "DSPK1"; - status = "disabled"; - }; - - tegra_dspk2: dspk@2905100 { - compatible = "nvidia,tegra186-dspk"; - reg = <0x2905100 0x100>; - clocks = <&bpmp TEGRA186_CLK_DSPK2>; - clock-names = "dspk"; - assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>; - assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; - assigned-clock-rates = <12288000>; - sound-name-prefix = "DSPK2"; - status = "disabled"; - }; - tegra_sfc1: sfc@2902000 { compatible = "nvidia,tegra186-sfc", "nvidia,tegra210-sfc"; @@ -431,22 +257,6 @@ status = "disabled"; }; - tegra_mvc1: mvc@290a000 { - compatible = "nvidia,tegra186-mvc", - "nvidia,tegra210-mvc"; - reg = <0x290a000 0x200>; - sound-name-prefix = "MVC1"; - status = "disabled"; - }; - - tegra_mvc2: mvc@290a200 { - compatible = "nvidia,tegra186-mvc", - "nvidia,tegra210-mvc"; - reg = <0x290a200 0x200>; - sound-name-prefix = "MVC2"; - status = "disabled"; - }; - tegra_amx1: amx@2903000 { compatible = "nvidia,tegra186-amx", "nvidia,tegra210-amx"; @@ -511,6 +321,78 @@ status = "disabled"; }; + tegra_dmic1: dmic@2904000 { + compatible = "nvidia,tegra210-dmic"; + reg = <0x2904000 0x100>; + clocks = <&bpmp TEGRA186_CLK_DMIC1>; + clock-names = "dmic"; + assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC1"; + status = "disabled"; + }; + + tegra_dmic2: dmic@2904100 { + compatible = "nvidia,tegra210-dmic"; + reg = <0x2904100 0x100>; + clocks = <&bpmp TEGRA186_CLK_DMIC2>; + clock-names = "dmic"; + assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC2"; + status = "disabled"; + }; + + tegra_dmic3: dmic@2904200 { + compatible = "nvidia,tegra210-dmic"; + reg = <0x2904200 0x100>; + clocks = <&bpmp TEGRA186_CLK_DMIC3>; + clock-names = "dmic"; + assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC3"; + status = "disabled"; + }; + + tegra_dmic4: dmic@2904300 { + compatible = "nvidia,tegra210-dmic"; + reg = <0x2904300 0x100>; + clocks = <&bpmp TEGRA186_CLK_DMIC4>; + clock-names = "dmic"; + assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC4"; + status = "disabled"; + }; + + tegra_dspk1: dspk@2905000 { + compatible = "nvidia,tegra186-dspk"; + reg = <0x2905000 0x100>; + clocks = <&bpmp TEGRA186_CLK_DSPK1>; + clock-names = "dspk"; + assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; + assigned-clock-rates = <12288000>; + sound-name-prefix = "DSPK1"; + status = "disabled"; + }; + + tegra_dspk2: dspk@2905100 { + compatible = "nvidia,tegra186-dspk"; + reg = <0x2905100 0x100>; + clocks = <&bpmp TEGRA186_CLK_DSPK2>; + clock-names = "dspk"; + assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; + assigned-clock-rates = <12288000>; + sound-name-prefix = "DSPK2"; + status = "disabled"; + }; + tegra_ope1: processing-engine@2908000 { compatible = "nvidia,tegra186-ope", "nvidia,tegra210-ope"; @@ -534,6 +416,22 @@ }; }; + tegra_mvc1: mvc@290a000 { + compatible = "nvidia,tegra186-mvc", + "nvidia,tegra210-mvc"; + reg = <0x290a000 0x200>; + sound-name-prefix = "MVC1"; + status = "disabled"; + }; + + tegra_mvc2: mvc@290a200 { + compatible = "nvidia,tegra186-mvc", + "nvidia,tegra210-mvc"; + reg = <0x290a200 0x200>; + sound-name-prefix = "MVC2"; + status = "disabled"; + }; + tegra_amixer: amixer@290bb00 { compatible = "nvidia,tegra186-amixer", "nvidia,tegra210-amixer"; @@ -542,6 +440,52 @@ status = "disabled"; }; + tegra_admaif: admaif@290f000 { + compatible = "nvidia,tegra186-admaif"; + reg = <0x0290f000 0x1000>; + dmas = <&adma 1>, <&adma 1>, + <&adma 2>, <&adma 2>, + <&adma 3>, <&adma 3>, + <&adma 4>, <&adma 4>, + <&adma 5>, <&adma 5>, + <&adma 6>, <&adma 6>, + <&adma 7>, <&adma 7>, + <&adma 8>, <&adma 8>, + <&adma 9>, <&adma 9>, + <&adma 10>, <&adma 10>, + <&adma 11>, <&adma 11>, + <&adma 12>, <&adma 12>, + <&adma 13>, <&adma 13>, + <&adma 14>, <&adma 14>, + <&adma 15>, <&adma 15>, + <&adma 16>, <&adma 16>, + <&adma 17>, <&adma 17>, + <&adma 18>, <&adma 18>, + <&adma 19>, <&adma 19>, + <&adma 20>, <&adma 20>; + dma-names = "rx1", "tx1", + "rx2", "tx2", + "rx3", "tx3", + "rx4", "tx4", + "rx5", "tx5", + "rx6", "tx6", + "rx7", "tx7", + "rx8", "tx8", + "rx9", "tx9", + "rx10", "tx10", + "rx11", "tx11", + "rx12", "tx12", + "rx13", "tx13", + "rx14", "tx14", + "rx15", "tx15", + "rx16", "tx16", + "rx17", "tx17", + "rx18", "tx18", + "rx19", "tx19", + "rx20", "tx20"; + status = "disabled"; + }; + tegra_asrc: asrc@2910000 { compatible = "nvidia,tegra186-asrc"; reg = <0x2910000 0x2000>; @@ -549,6 +493,62 @@ status = "disabled"; }; }; + + adma: dma-controller@2930000 { + compatible = "nvidia,tegra186-adma"; + reg = <0x02930000 0x20000>; + interrupt-parent = <&agic>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + clocks = <&bpmp TEGRA186_CLK_AHUB>; + clock-names = "d_audio"; + status = "disabled"; + }; + + agic: interrupt-controller@2a40000 { + compatible = "nvidia,tegra186-agic", + "nvidia,tegra210-agic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x02a41000 0x1000>, + <0x02a42000 0x2000>; + interrupts = <GIC_SPI 145 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&bpmp TEGRA186_CLK_APE>; + clock-names = "clk"; + status = "disabled"; + }; }; mc: memory-controller@2c00000 { @@ -674,8 +674,6 @@ clock-names = "div-clk"; resets = <&bpmp TEGRA186_RESET_I2C1>; reset-names = "i2c"; - iommus = <&smmu TEGRA186_SID_GPCDMA_0>; - dma-coherent; dmas = <&gpcdma 21>, <&gpcdma 21>; dma-names = "rx", "tx"; status = "disabled"; @@ -691,8 +689,6 @@ clock-names = "div-clk"; resets = <&bpmp TEGRA186_RESET_I2C3>; reset-names = "i2c"; - iommus = <&smmu TEGRA186_SID_GPCDMA_0>; - dma-coherent; dmas = <&gpcdma 23>, <&gpcdma 23>; dma-names = "rx", "tx"; status = "disabled"; @@ -712,8 +708,6 @@ pinctrl-names = "default", "idle"; pinctrl-0 = <&state_dpaux1_i2c>; pinctrl-1 = <&state_dpaux1_off>; - iommus = <&smmu TEGRA186_SID_GPCDMA_0>; - dma-coherent; dmas = <&gpcdma 26>, <&gpcdma 26>; dma-names = "rx", "tx"; status = "disabled"; @@ -747,8 +741,6 @@ pinctrl-names = "default", "idle"; pinctrl-0 = <&state_dpaux_i2c>; pinctrl-1 = <&state_dpaux_off>; - iommus = <&smmu TEGRA186_SID_GPCDMA_0>; - dma-coherent; dmas = <&gpcdma 30>, <&gpcdma 30>; dma-names = "rx", "tx"; status = "disabled"; @@ -764,8 +756,6 @@ clock-names = "div-clk"; resets = <&bpmp TEGRA186_RESET_I2C7>; reset-names = "i2c"; - iommus = <&smmu TEGRA186_SID_GPCDMA_0>; - dma-coherent; dmas = <&gpcdma 27>, <&gpcdma 27>; dma-names = "rx", "tx"; status = "disabled"; @@ -781,8 +771,6 @@ clock-names = "div-clk"; resets = <&bpmp TEGRA186_RESET_I2C9>; reset-names = "i2c"; - iommus = <&smmu TEGRA186_SID_GPCDMA_0>; - dma-coherent; dmas = <&gpcdma 31>, <&gpcdma 31>; dma-names = "rx", "tx"; status = "disabled"; @@ -970,6 +958,34 @@ status = "disabled"; }; + sata@3507000 { + compatible = "nvidia,tegra186-ahci"; + reg = <0x0 0x03507000 0x0 0x00002000>, /* AHCI */ + <0x0 0x03500000 0x0 0x00007000>, /* SATA */ + <0x0 0x03A90000 0x0 0x00010000>; /* SATA AUX */ + interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; + + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_SAX>; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_SATAR &emc>, + <&mc TEGRA186_MEMORY_CLIENT_SATAW &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA186_SID_SATA>; + + clocks = <&bpmp TEGRA186_CLK_SATA>, + <&bpmp TEGRA186_CLK_SATA_OOB>; + clock-names = "sata", "sata-oob"; + assigned-clocks = <&bpmp TEGRA186_CLK_SATA>, + <&bpmp TEGRA186_CLK_SATA_OOB>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>, + <&bpmp TEGRA186_CLK_PLLP>; + assigned-clock-rates = <102000000>, + <204000000>; + resets = <&bpmp TEGRA186_RESET_SATA>, + <&bpmp TEGRA186_RESET_SATACOLD>; + reset-names = "sata", "sata-cold"; + status = "disabled"; + }; + hda@3510000 { compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda"; reg = <0x0 0x03510000 0x0 0x10000>; @@ -1195,8 +1211,6 @@ clock-names = "div-clk"; resets = <&bpmp TEGRA186_RESET_I2C2>; reset-names = "i2c"; - iommus = <&smmu TEGRA186_SID_GPCDMA_0>; - dma-coherent; dmas = <&gpcdma 22>, <&gpcdma 22>; dma-names = "rx", "tx"; status = "disabled"; @@ -1212,8 +1226,6 @@ clock-names = "div-clk"; resets = <&bpmp TEGRA186_RESET_I2C8>; reset-names = "i2c"; - iommus = <&smmu TEGRA186_SID_GPCDMA_0>; - dma-coherent; dmas = <&gpcdma 0>, <&gpcdma 0>; dma-names = "rx", "tx"; status = "disabled"; @@ -1286,18 +1298,13 @@ #interrupt-cells = <2>; interrupt-controller; - sdmmc1_3v3: sdmmc1-3v3 { - pins = "sdmmc1-hv"; - power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; - }; - sdmmc1_1v8: sdmmc1-1v8 { pins = "sdmmc1-hv"; power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; }; - sdmmc2_3v3: sdmmc2-3v3 { - pins = "sdmmc2-hv"; + sdmmc1_3v3: sdmmc1-3v3 { + pins = "sdmmc1-hv"; power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; }; @@ -1306,8 +1313,8 @@ power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; }; - sdmmc3_3v3: sdmmc3-3v3 { - pins = "sdmmc3-hv"; + sdmmc2_3v3: sdmmc2-3v3 { + pins = "sdmmc2-hv"; power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; }; @@ -1315,6 +1322,11 @@ pins = "sdmmc3-hv"; power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; }; + + sdmmc3_3v3: sdmmc3-3v3 { + pins = "sdmmc3-hv"; + power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; + }; }; ccplex@e000000 { @@ -1894,34 +1906,6 @@ }; }; - sata@3507000 { - compatible = "nvidia,tegra186-ahci"; - reg = <0x0 0x03507000 0x0 0x00002000>, /* AHCI */ - <0x0 0x03500000 0x0 0x00007000>, /* SATA */ - <0x0 0x03A90000 0x0 0x00010000>; /* SATA AUX */ - interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; - - power-domains = <&bpmp TEGRA186_POWER_DOMAIN_SAX>; - interconnects = <&mc TEGRA186_MEMORY_CLIENT_SATAR &emc>, - <&mc TEGRA186_MEMORY_CLIENT_SATAW &emc>; - interconnect-names = "dma-mem", "write"; - iommus = <&smmu TEGRA186_SID_SATA>; - - clocks = <&bpmp TEGRA186_CLK_SATA>, - <&bpmp TEGRA186_CLK_SATA_OOB>; - clock-names = "sata", "sata-oob"; - assigned-clocks = <&bpmp TEGRA186_CLK_SATA>, - <&bpmp TEGRA186_CLK_SATA_OOB>; - assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>, - <&bpmp TEGRA186_CLK_PLLP>; - assigned-clock-rates = <102000000>, - <204000000>; - resets = <&bpmp TEGRA186_RESET_SATA>, - <&bpmp TEGRA186_RESET_SATACOLD>; - reset-names = "sata", "sata-cold"; - status = "disabled"; - }; - bpmp: bpmp { compatible = "nvidia,tegra186-bpmp"; interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>, @@ -2052,14 +2036,7 @@ }; }; - pmu_denver { - compatible = "nvidia,denver-pmu"; - interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&denver_0 &denver_1>; - }; - - pmu_a57 { + pmu-a57 { compatible = "arm,cortex-a57-pmu"; interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, @@ -2068,6 +2045,13 @@ interrupt-affinity = <&ca57_0 &ca57_1 &ca57_2 &ca57_3>; }; + pmu-denver { + compatible = "nvidia,denver-pmu"; + interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&denver_0 &denver_1>; + }; + sound { status = "disabled"; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi index cd272d407e01..5b59c1986e9b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi @@ -147,6 +147,24 @@ pinctrl-names = "default"; pinctrl-0 = <&max20024_default>; + fps { + fps0 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; + maxim,shutdown-fps-time-period-us = <640>; + }; + + fps1 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; + maxim,shutdown-fps-time-period-us = <640>; + maxim,device-state-on-disabled-event = <MAX77620_FPS_INACTIVE_STATE_SLEEP>; + }; + + fps2 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; + maxim,shutdown-fps-time-period-us = <640>; + }; + }; + max20024_default: pinmux { gpio0 { pins = "gpio0"; @@ -190,24 +208,6 @@ }; }; - fps { - fps0 { - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; - maxim,shutdown-fps-time-period-us = <640>; - }; - - fps1 { - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; - maxim,shutdown-fps-time-period-us = <640>; - maxim,device-state-on-disabled-event = <MAX77620_FPS_INACTIVE_STATE_SLEEP>; - }; - - fps2 { - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; - maxim,shutdown-fps-time-period-us = <640>; - }; - }; - regulators { in-sd0-supply = <&vdd_5v0_sys>; in-sd1-supply = <&vdd_5v0_sys>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts index bc1041d11f6d..64a3398fe7a6 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts @@ -14,16 +14,1115 @@ aconnect@2900000 { status = "okay"; - dma-controller@2930000 { + ahub@2900800 { status = "okay"; - }; - interrupt-controller@2a40000 { - status = "okay"; - }; + i2s@2901000 { + status = "okay"; - ahub@2900800 { - status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s1_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s1_ep>; + }; + }; + + i2s1_port: port@1 { + reg = <1>; + + i2s1_dap_ep: endpoint { + dai-format = "i2s"; + remote-endpoint = <&rt5658_ep>; + }; + }; + }; + }; + + i2s@2901100 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s2_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s2_ep>; + }; + }; + + i2s2_port: port@1 { + reg = <1>; + + i2s2_dap_ep: endpoint { + dai-format = "i2s"; + /* Place holder for external Codec */ + }; + }; + }; + }; + + i2s@2901300 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s4_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s4_ep>; + }; + }; + + i2s4_port: port@1 { + reg = <1>; + + i2s4_dap_ep: endpoint { + dai-format = "i2s"; + /* Place holder for external Codec */ + }; + }; + }; + }; + + i2s@2901500 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s6_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s6_ep>; + }; + }; + + i2s6_port: port@1 { + reg = <1>; + + i2s6_dap_ep: endpoint { + dai-format = "i2s"; + /* Place holder for external Codec */ + }; + }; + }; + }; + + sfc@2902000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sfc1_cif_in_ep: endpoint { + remote-endpoint = <&xbar_sfc1_in_ep>; + }; + }; + + sfc1_out_port: port@1 { + reg = <1>; + + sfc1_cif_out_ep: endpoint { + remote-endpoint = <&xbar_sfc1_out_ep>; + }; + }; + }; + }; + + sfc@2902200 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sfc2_cif_in_ep: endpoint { + remote-endpoint = <&xbar_sfc2_in_ep>; + }; + }; + + sfc2_out_port: port@1 { + reg = <1>; + + sfc2_cif_out_ep: endpoint { + remote-endpoint = <&xbar_sfc2_out_ep>; + }; + }; + }; + }; + + sfc@2902400 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sfc3_cif_in_ep: endpoint { + remote-endpoint = <&xbar_sfc3_in_ep>; + }; + }; + + sfc3_out_port: port@1 { + reg = <1>; + + sfc3_cif_out_ep: endpoint { + remote-endpoint = <&xbar_sfc3_out_ep>; + }; + }; + }; + }; + + sfc@2902600 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sfc4_cif_in_ep: endpoint { + remote-endpoint = <&xbar_sfc4_in_ep>; + }; + }; + + sfc4_out_port: port@1 { + reg = <1>; + + sfc4_cif_out_ep: endpoint { + remote-endpoint = <&xbar_sfc4_out_ep>; + }; + }; + }; + }; + + amx@2903000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + amx1_in1_ep: endpoint { + remote-endpoint = <&xbar_amx1_in1_ep>; + }; + }; + + port@1 { + reg = <1>; + + amx1_in2_ep: endpoint { + remote-endpoint = <&xbar_amx1_in2_ep>; + }; + }; + + port@2 { + reg = <2>; + + amx1_in3_ep: endpoint { + remote-endpoint = <&xbar_amx1_in3_ep>; + }; + }; + + port@3 { + reg = <3>; + + amx1_in4_ep: endpoint { + remote-endpoint = <&xbar_amx1_in4_ep>; + }; + }; + + amx1_out_port: port@4 { + reg = <4>; + + amx1_out_ep: endpoint { + remote-endpoint = <&xbar_amx1_out_ep>; + }; + }; + }; + }; + + amx@2903100 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + amx2_in1_ep: endpoint { + remote-endpoint = <&xbar_amx2_in1_ep>; + }; + }; + + port@1 { + reg = <1>; + + amx2_in2_ep: endpoint { + remote-endpoint = <&xbar_amx2_in2_ep>; + }; + }; + + amx2_in3_port: port@2 { + reg = <2>; + + amx2_in3_ep: endpoint { + remote-endpoint = <&xbar_amx2_in3_ep>; + }; + }; + + amx2_in4_port: port@3 { + reg = <3>; + + amx2_in4_ep: endpoint { + remote-endpoint = <&xbar_amx2_in4_ep>; + }; + }; + + amx2_out_port: port@4 { + reg = <4>; + + amx2_out_ep: endpoint { + remote-endpoint = <&xbar_amx2_out_ep>; + }; + }; + }; + }; + + amx@2903200 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + amx3_in1_ep: endpoint { + remote-endpoint = <&xbar_amx3_in1_ep>; + }; + }; + + port@1 { + reg = <1>; + + amx3_in2_ep: endpoint { + remote-endpoint = <&xbar_amx3_in2_ep>; + }; + }; + + port@2 { + reg = <2>; + + amx3_in3_ep: endpoint { + remote-endpoint = <&xbar_amx3_in3_ep>; + }; + }; + + port@3 { + reg = <3>; + + amx3_in4_ep: endpoint { + remote-endpoint = <&xbar_amx3_in4_ep>; + }; + }; + + amx3_out_port: port@4 { + reg = <4>; + + amx3_out_ep: endpoint { + remote-endpoint = <&xbar_amx3_out_ep>; + }; + }; + }; + }; + + amx@2903300 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + amx4_in1_ep: endpoint { + remote-endpoint = <&xbar_amx4_in1_ep>; + }; + }; + + port@1 { + reg = <1>; + + amx4_in2_ep: endpoint { + remote-endpoint = <&xbar_amx4_in2_ep>; + }; + }; + + port@2 { + reg = <2>; + + amx4_in3_ep: endpoint { + remote-endpoint = <&xbar_amx4_in3_ep>; + }; + }; + + port@3 { + reg = <3>; + + amx4_in4_ep: endpoint { + remote-endpoint = <&xbar_amx4_in4_ep>; + }; + }; + + amx4_out_port: port@4 { + reg = <4>; + + amx4_out_ep: endpoint { + remote-endpoint = <&xbar_amx4_out_ep>; + }; + }; + }; + }; + + adx@2903800 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adx1_in_ep: endpoint { + remote-endpoint = <&xbar_adx1_in_ep>; + }; + }; + + adx1_out1_port: port@1 { + reg = <1>; + + adx1_out1_ep: endpoint { + remote-endpoint = <&xbar_adx1_out1_ep>; + }; + }; + + adx1_out2_port: port@2 { + reg = <2>; + + adx1_out2_ep: endpoint { + remote-endpoint = <&xbar_adx1_out2_ep>; + }; + }; + + adx1_out3_port: port@3 { + reg = <3>; + + adx1_out3_ep: endpoint { + remote-endpoint = <&xbar_adx1_out3_ep>; + }; + }; + + adx1_out4_port: port@4 { + reg = <4>; + + adx1_out4_ep: endpoint { + remote-endpoint = <&xbar_adx1_out4_ep>; + }; + }; + }; + }; + + adx@2903900 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adx2_in_ep: endpoint { + remote-endpoint = <&xbar_adx2_in_ep>; + }; + }; + + adx2_out1_port: port@1 { + reg = <1>; + + adx2_out1_ep: endpoint { + remote-endpoint = <&xbar_adx2_out1_ep>; + }; + }; + + adx2_out2_port: port@2 { + reg = <2>; + + adx2_out2_ep: endpoint { + remote-endpoint = <&xbar_adx2_out2_ep>; + }; + }; + + adx2_out3_port: port@3 { + reg = <3>; + + adx2_out3_ep: endpoint { + remote-endpoint = <&xbar_adx2_out3_ep>; + }; + }; + + adx2_out4_port: port@4 { + reg = <4>; + + adx2_out4_ep: endpoint { + remote-endpoint = <&xbar_adx2_out4_ep>; + }; + }; + }; + }; + + adx@2903a00 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adx3_in_ep: endpoint { + remote-endpoint = <&xbar_adx3_in_ep>; + }; + }; + + adx3_out1_port: port@1 { + reg = <1>; + + adx3_out1_ep: endpoint { + remote-endpoint = <&xbar_adx3_out1_ep>; + }; + }; + + adx3_out2_port: port@2 { + reg = <2>; + + adx3_out2_ep: endpoint { + remote-endpoint = <&xbar_adx3_out2_ep>; + }; + }; + + adx3_out3_port: port@3 { + reg = <3>; + + adx3_out3_ep: endpoint { + remote-endpoint = <&xbar_adx3_out3_ep>; + }; + }; + + adx3_out4_port: port@4 { + reg = <4>; + + adx3_out4_ep: endpoint { + remote-endpoint = <&xbar_adx3_out4_ep>; + }; + }; + }; + }; + + adx@2903b00 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adx4_in_ep: endpoint { + remote-endpoint = <&xbar_adx4_in_ep>; + }; + }; + + adx4_out1_port: port@1 { + reg = <1>; + + adx4_out1_ep: endpoint { + remote-endpoint = <&xbar_adx4_out1_ep>; + }; + }; + + adx4_out2_port: port@2 { + reg = <2>; + + adx4_out2_ep: endpoint { + remote-endpoint = <&xbar_adx4_out2_ep>; + }; + }; + + adx4_out3_port: port@3 { + reg = <3>; + + adx4_out3_ep: endpoint { + remote-endpoint = <&xbar_adx4_out3_ep>; + }; + }; + + adx4_out4_port: port@4 { + reg = <4>; + + adx4_out4_ep: endpoint { + remote-endpoint = <&xbar_adx4_out4_ep>; + }; + }; + }; + }; + + dmic@2904200 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dmic3_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic3_ep>; + }; + }; + + dmic3_port: port@1 { + reg = <1>; + + dmic3_dap_ep: endpoint { + /* Place holder for external Codec */ + }; + }; + }; + }; + + processing-engine@2908000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + ope1_cif_in_ep: endpoint { + remote-endpoint = <&xbar_ope1_in_ep>; + }; + }; + + ope1_out_port: port@1 { + reg = <0x1>; + + ope1_cif_out_ep: endpoint { + remote-endpoint = <&xbar_ope1_out_ep>; + }; + }; + }; + }; + + mvc@290a000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mvc1_cif_in_ep: endpoint { + remote-endpoint = <&xbar_mvc1_in_ep>; + }; + }; + + mvc1_out_port: port@1 { + reg = <1>; + + mvc1_cif_out_ep: endpoint { + remote-endpoint = <&xbar_mvc1_out_ep>; + }; + }; + }; + }; + + mvc@290a200 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mvc2_cif_in_ep: endpoint { + remote-endpoint = <&xbar_mvc2_in_ep>; + }; + }; + + mvc2_out_port: port@1 { + reg = <1>; + + mvc2_cif_out_ep: endpoint { + remote-endpoint = <&xbar_mvc2_out_ep>; + }; + }; + }; + }; + + amixer@290bb00 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + mixer_in1_ep: endpoint { + remote-endpoint = <&xbar_mixer_in1_ep>; + }; + }; + + port@1 { + reg = <0x1>; + + mixer_in2_ep: endpoint { + remote-endpoint = <&xbar_mixer_in2_ep>; + }; + }; + + port@2 { + reg = <0x2>; + + mixer_in3_ep: endpoint { + remote-endpoint = <&xbar_mixer_in3_ep>; + }; + }; + + port@3 { + reg = <0x3>; + + mixer_in4_ep: endpoint { + remote-endpoint = <&xbar_mixer_in4_ep>; + }; + }; + + port@4 { + reg = <0x4>; + + mixer_in5_ep: endpoint { + remote-endpoint = <&xbar_mixer_in5_ep>; + }; + }; + + port@5 { + reg = <0x5>; + + mixer_in6_ep: endpoint { + remote-endpoint = <&xbar_mixer_in6_ep>; + }; + }; + + port@6 { + reg = <0x6>; + + mixer_in7_ep: endpoint { + remote-endpoint = <&xbar_mixer_in7_ep>; + }; + }; + + port@7 { + reg = <0x7>; + + mixer_in8_ep: endpoint { + remote-endpoint = <&xbar_mixer_in8_ep>; + }; + }; + + port@8 { + reg = <0x8>; + + mixer_in9_ep: endpoint { + remote-endpoint = <&xbar_mixer_in9_ep>; + }; + }; + + port@9 { + reg = <0x9>; + + mixer_in10_ep: endpoint { + remote-endpoint = <&xbar_mixer_in10_ep>; + }; + }; + + mixer_out1_port: port@a { + reg = <0xa>; + + mixer_out1_ep: endpoint { + remote-endpoint = <&xbar_mixer_out1_ep>; + }; + }; + + mixer_out2_port: port@b { + reg = <0xb>; + + mixer_out2_ep: endpoint { + remote-endpoint = <&xbar_mixer_out2_ep>; + }; + }; + + mixer_out3_port: port@c { + reg = <0xc>; + + mixer_out3_ep: endpoint { + remote-endpoint = <&xbar_mixer_out3_ep>; + }; + }; + + mixer_out4_port: port@d { + reg = <0xd>; + + mixer_out4_ep: endpoint { + remote-endpoint = <&xbar_mixer_out4_ep>; + }; + }; + + mixer_out5_port: port@e { + reg = <0xe>; + + mixer_out5_ep: endpoint { + remote-endpoint = <&xbar_mixer_out5_ep>; + }; + }; + }; + }; + + admaif@290f000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + admaif0_port: port@0 { + reg = <0x0>; + + admaif0_ep: endpoint { + remote-endpoint = <&xbar_admaif0_ep>; + }; + }; + + admaif1_port: port@1 { + reg = <0x1>; + + admaif1_ep: endpoint { + remote-endpoint = <&xbar_admaif1_ep>; + }; + }; + + admaif2_port: port@2 { + reg = <0x2>; + + admaif2_ep: endpoint { + remote-endpoint = <&xbar_admaif2_ep>; + }; + }; + + admaif3_port: port@3 { + reg = <0x3>; + + admaif3_ep: endpoint { + remote-endpoint = <&xbar_admaif3_ep>; + }; + }; + + admaif4_port: port@4 { + reg = <0x4>; + + admaif4_ep: endpoint { + remote-endpoint = <&xbar_admaif4_ep>; + }; + }; + + admaif5_port: port@5 { + reg = <0x5>; + + admaif5_ep: endpoint { + remote-endpoint = <&xbar_admaif5_ep>; + }; + }; + + admaif6_port: port@6 { + reg = <0x6>; + + admaif6_ep: endpoint { + remote-endpoint = <&xbar_admaif6_ep>; + }; + }; + + admaif7_port: port@7 { + reg = <0x7>; + + admaif7_ep: endpoint { + remote-endpoint = <&xbar_admaif7_ep>; + }; + }; + + admaif8_port: port@8 { + reg = <0x8>; + + admaif8_ep: endpoint { + remote-endpoint = <&xbar_admaif8_ep>; + }; + }; + + admaif9_port: port@9 { + reg = <0x9>; + + admaif9_ep: endpoint { + remote-endpoint = <&xbar_admaif9_ep>; + }; + }; + + admaif10_port: port@a { + reg = <0xa>; + + admaif10_ep: endpoint { + remote-endpoint = <&xbar_admaif10_ep>; + }; + }; + + admaif11_port: port@b { + reg = <0xb>; + + admaif11_ep: endpoint { + remote-endpoint = <&xbar_admaif11_ep>; + }; + }; + + admaif12_port: port@c { + reg = <0xc>; + + admaif12_ep: endpoint { + remote-endpoint = <&xbar_admaif12_ep>; + }; + }; + + admaif13_port: port@d { + reg = <0xd>; + + admaif13_ep: endpoint { + remote-endpoint = <&xbar_admaif13_ep>; + }; + }; + + admaif14_port: port@e { + reg = <0xe>; + + admaif14_ep: endpoint { + remote-endpoint = <&xbar_admaif14_ep>; + }; + }; + + admaif15_port: port@f { + reg = <0xf>; + + admaif15_ep: endpoint { + remote-endpoint = <&xbar_admaif15_ep>; + }; + }; + + admaif16_port: port@10 { + reg = <0x10>; + + admaif16_ep: endpoint { + remote-endpoint = <&xbar_admaif16_ep>; + }; + }; + + admaif17_port: port@11 { + reg = <0x11>; + + admaif17_ep: endpoint { + remote-endpoint = <&xbar_admaif17_ep>; + }; + }; + + admaif18_port: port@12 { + reg = <0x12>; + + admaif18_ep: endpoint { + remote-endpoint = <&xbar_admaif18_ep>; + }; + }; + + admaif19_port: port@13 { + reg = <0x13>; + + admaif19_ep: endpoint { + remote-endpoint = <&xbar_admaif19_ep>; + }; + }; + }; + }; + + asrc@2910000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + asrc_in1_ep: endpoint { + remote-endpoint = <&xbar_asrc_in1_ep>; + }; + }; + + port@1 { + reg = <0x1>; + + asrc_in2_ep: endpoint { + remote-endpoint = <&xbar_asrc_in2_ep>; + }; + }; + + port@2 { + reg = <0x2>; + + asrc_in3_ep: endpoint { + remote-endpoint = <&xbar_asrc_in3_ep>; + }; + }; + + port@3 { + reg = <0x3>; + + asrc_in4_ep: endpoint { + remote-endpoint = <&xbar_asrc_in4_ep>; + }; + }; + + port@4 { + reg = <0x4>; + + asrc_in5_ep: endpoint { + remote-endpoint = <&xbar_asrc_in5_ep>; + }; + }; + + port@5 { + reg = <0x5>; + + asrc_in6_ep: endpoint { + remote-endpoint = <&xbar_asrc_in6_ep>; + }; + }; + + port@6 { + reg = <0x6>; + + asrc_in7_ep: endpoint { + remote-endpoint = <&xbar_asrc_in7_ep>; + }; + }; + + asrc_out1_port: port@7 { + reg = <0x7>; + + asrc_out1_ep: endpoint { + remote-endpoint = <&xbar_asrc_out1_ep>; + }; + }; + + asrc_out2_port: port@8 { + reg = <0x8>; + + asrc_out2_ep: endpoint { + remote-endpoint = <&xbar_asrc_out2_ep>; + }; + }; + + asrc_out3_port: port@9 { + reg = <0x9>; + + asrc_out3_ep: endpoint { + remote-endpoint = <&xbar_asrc_out3_ep>; + }; + }; + + asrc_out4_port: port@a { + reg = <0xa>; + + asrc_out4_ep: endpoint { + remote-endpoint = <&xbar_asrc_out4_ep>; + }; + }; + + asrc_out5_port: port@b { + reg = <0xb>; + + asrc_out5_ep: endpoint { + remote-endpoint = <&xbar_asrc_out5_ep>; + }; + }; + + asrc_out6_port: port@c { + reg = <0xc>; + + asrc_out6_ep: endpoint { + remote-endpoint = <&xbar_asrc_out6_ep>; + }; + }; + }; + }; ports { #address-cells = <1>; @@ -885,1113 +1984,14 @@ }; }; }; + }; - admaif@290f000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - admaif0_port: port@0 { - reg = <0x0>; - - admaif0_ep: endpoint { - remote-endpoint = <&xbar_admaif0_ep>; - }; - }; - - admaif1_port: port@1 { - reg = <0x1>; - - admaif1_ep: endpoint { - remote-endpoint = <&xbar_admaif1_ep>; - }; - }; - - admaif2_port: port@2 { - reg = <0x2>; - - admaif2_ep: endpoint { - remote-endpoint = <&xbar_admaif2_ep>; - }; - }; - - admaif3_port: port@3 { - reg = <0x3>; - - admaif3_ep: endpoint { - remote-endpoint = <&xbar_admaif3_ep>; - }; - }; - - admaif4_port: port@4 { - reg = <0x4>; - - admaif4_ep: endpoint { - remote-endpoint = <&xbar_admaif4_ep>; - }; - }; - - admaif5_port: port@5 { - reg = <0x5>; - - admaif5_ep: endpoint { - remote-endpoint = <&xbar_admaif5_ep>; - }; - }; - - admaif6_port: port@6 { - reg = <0x6>; - - admaif6_ep: endpoint { - remote-endpoint = <&xbar_admaif6_ep>; - }; - }; - - admaif7_port: port@7 { - reg = <0x7>; - - admaif7_ep: endpoint { - remote-endpoint = <&xbar_admaif7_ep>; - }; - }; - - admaif8_port: port@8 { - reg = <0x8>; - - admaif8_ep: endpoint { - remote-endpoint = <&xbar_admaif8_ep>; - }; - }; - - admaif9_port: port@9 { - reg = <0x9>; - - admaif9_ep: endpoint { - remote-endpoint = <&xbar_admaif9_ep>; - }; - }; - - admaif10_port: port@a { - reg = <0xa>; - - admaif10_ep: endpoint { - remote-endpoint = <&xbar_admaif10_ep>; - }; - }; - - admaif11_port: port@b { - reg = <0xb>; - - admaif11_ep: endpoint { - remote-endpoint = <&xbar_admaif11_ep>; - }; - }; - - admaif12_port: port@c { - reg = <0xc>; - - admaif12_ep: endpoint { - remote-endpoint = <&xbar_admaif12_ep>; - }; - }; - - admaif13_port: port@d { - reg = <0xd>; - - admaif13_ep: endpoint { - remote-endpoint = <&xbar_admaif13_ep>; - }; - }; - - admaif14_port: port@e { - reg = <0xe>; - - admaif14_ep: endpoint { - remote-endpoint = <&xbar_admaif14_ep>; - }; - }; - - admaif15_port: port@f { - reg = <0xf>; - - admaif15_ep: endpoint { - remote-endpoint = <&xbar_admaif15_ep>; - }; - }; - - admaif16_port: port@10 { - reg = <0x10>; - - admaif16_ep: endpoint { - remote-endpoint = <&xbar_admaif16_ep>; - }; - }; - - admaif17_port: port@11 { - reg = <0x11>; - - admaif17_ep: endpoint { - remote-endpoint = <&xbar_admaif17_ep>; - }; - }; - - admaif18_port: port@12 { - reg = <0x12>; - - admaif18_ep: endpoint { - remote-endpoint = <&xbar_admaif18_ep>; - }; - }; - - admaif19_port: port@13 { - reg = <0x13>; - - admaif19_ep: endpoint { - remote-endpoint = <&xbar_admaif19_ep>; - }; - }; - }; - }; - - i2s@2901000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2s1_cif_ep: endpoint { - remote-endpoint = <&xbar_i2s1_ep>; - }; - }; - - i2s1_port: port@1 { - reg = <1>; - - i2s1_dap_ep: endpoint { - dai-format = "i2s"; - remote-endpoint = <&rt5658_ep>; - }; - }; - }; - }; - - i2s@2901100 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2s2_cif_ep: endpoint { - remote-endpoint = <&xbar_i2s2_ep>; - }; - }; - - i2s2_port: port@1 { - reg = <1>; - - i2s2_dap_ep: endpoint { - dai-format = "i2s"; - /* Place holder for external Codec */ - }; - }; - }; - }; - - i2s@2901300 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2s4_cif_ep: endpoint { - remote-endpoint = <&xbar_i2s4_ep>; - }; - }; - - i2s4_port: port@1 { - reg = <1>; - - i2s4_dap_ep: endpoint { - dai-format = "i2s"; - /* Place holder for external Codec */ - }; - }; - }; - }; - - i2s@2901500 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2s6_cif_ep: endpoint { - remote-endpoint = <&xbar_i2s6_ep>; - }; - }; - - i2s6_port: port@1 { - reg = <1>; - - i2s6_dap_ep: endpoint { - dai-format = "i2s"; - /* Place holder for external Codec */ - }; - }; - }; - }; - - dmic@2904200 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dmic3_cif_ep: endpoint { - remote-endpoint = <&xbar_dmic3_ep>; - }; - }; - - dmic3_port: port@1 { - reg = <1>; - - dmic3_dap_ep: endpoint { - /* Place holder for external Codec */ - }; - }; - }; - }; - - sfc@2902000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - sfc1_cif_in_ep: endpoint { - remote-endpoint = <&xbar_sfc1_in_ep>; - }; - }; - - sfc1_out_port: port@1 { - reg = <1>; - - sfc1_cif_out_ep: endpoint { - remote-endpoint = <&xbar_sfc1_out_ep>; - }; - }; - }; - }; - - sfc@2902200 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - sfc2_cif_in_ep: endpoint { - remote-endpoint = <&xbar_sfc2_in_ep>; - }; - }; - - sfc2_out_port: port@1 { - reg = <1>; - - sfc2_cif_out_ep: endpoint { - remote-endpoint = <&xbar_sfc2_out_ep>; - }; - }; - }; - }; - - sfc@2902400 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - sfc3_cif_in_ep: endpoint { - remote-endpoint = <&xbar_sfc3_in_ep>; - }; - }; - - sfc3_out_port: port@1 { - reg = <1>; - - sfc3_cif_out_ep: endpoint { - remote-endpoint = <&xbar_sfc3_out_ep>; - }; - }; - }; - }; - - sfc@2902600 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - sfc4_cif_in_ep: endpoint { - remote-endpoint = <&xbar_sfc4_in_ep>; - }; - }; - - sfc4_out_port: port@1 { - reg = <1>; - - sfc4_cif_out_ep: endpoint { - remote-endpoint = <&xbar_sfc4_out_ep>; - }; - }; - }; - }; - - mvc@290a000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - mvc1_cif_in_ep: endpoint { - remote-endpoint = <&xbar_mvc1_in_ep>; - }; - }; - - mvc1_out_port: port@1 { - reg = <1>; - - mvc1_cif_out_ep: endpoint { - remote-endpoint = <&xbar_mvc1_out_ep>; - }; - }; - }; - }; - - mvc@290a200 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - mvc2_cif_in_ep: endpoint { - remote-endpoint = <&xbar_mvc2_in_ep>; - }; - }; - - mvc2_out_port: port@1 { - reg = <1>; - - mvc2_cif_out_ep: endpoint { - remote-endpoint = <&xbar_mvc2_out_ep>; - }; - }; - }; - }; - - amx@2903000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - amx1_in1_ep: endpoint { - remote-endpoint = <&xbar_amx1_in1_ep>; - }; - }; - - port@1 { - reg = <1>; - - amx1_in2_ep: endpoint { - remote-endpoint = <&xbar_amx1_in2_ep>; - }; - }; - - port@2 { - reg = <2>; - - amx1_in3_ep: endpoint { - remote-endpoint = <&xbar_amx1_in3_ep>; - }; - }; - - port@3 { - reg = <3>; - - amx1_in4_ep: endpoint { - remote-endpoint = <&xbar_amx1_in4_ep>; - }; - }; - - amx1_out_port: port@4 { - reg = <4>; - - amx1_out_ep: endpoint { - remote-endpoint = <&xbar_amx1_out_ep>; - }; - }; - }; - }; - - amx@2903100 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - amx2_in1_ep: endpoint { - remote-endpoint = <&xbar_amx2_in1_ep>; - }; - }; - - port@1 { - reg = <1>; - - amx2_in2_ep: endpoint { - remote-endpoint = <&xbar_amx2_in2_ep>; - }; - }; - - amx2_in3_port: port@2 { - reg = <2>; - - amx2_in3_ep: endpoint { - remote-endpoint = <&xbar_amx2_in3_ep>; - }; - }; - - amx2_in4_port: port@3 { - reg = <3>; - - amx2_in4_ep: endpoint { - remote-endpoint = <&xbar_amx2_in4_ep>; - }; - }; - - amx2_out_port: port@4 { - reg = <4>; - - amx2_out_ep: endpoint { - remote-endpoint = <&xbar_amx2_out_ep>; - }; - }; - }; - }; - - amx@2903200 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - amx3_in1_ep: endpoint { - remote-endpoint = <&xbar_amx3_in1_ep>; - }; - }; - - port@1 { - reg = <1>; - - amx3_in2_ep: endpoint { - remote-endpoint = <&xbar_amx3_in2_ep>; - }; - }; - - port@2 { - reg = <2>; - - amx3_in3_ep: endpoint { - remote-endpoint = <&xbar_amx3_in3_ep>; - }; - }; - - port@3 { - reg = <3>; - - amx3_in4_ep: endpoint { - remote-endpoint = <&xbar_amx3_in4_ep>; - }; - }; - - amx3_out_port: port@4 { - reg = <4>; - - amx3_out_ep: endpoint { - remote-endpoint = <&xbar_amx3_out_ep>; - }; - }; - }; - }; - - amx@2903300 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - amx4_in1_ep: endpoint { - remote-endpoint = <&xbar_amx4_in1_ep>; - }; - }; - - port@1 { - reg = <1>; - - amx4_in2_ep: endpoint { - remote-endpoint = <&xbar_amx4_in2_ep>; - }; - }; - - port@2 { - reg = <2>; - - amx4_in3_ep: endpoint { - remote-endpoint = <&xbar_amx4_in3_ep>; - }; - }; - - port@3 { - reg = <3>; - - amx4_in4_ep: endpoint { - remote-endpoint = <&xbar_amx4_in4_ep>; - }; - }; - - amx4_out_port: port@4 { - reg = <4>; - - amx4_out_ep: endpoint { - remote-endpoint = <&xbar_amx4_out_ep>; - }; - }; - }; - }; - - adx@2903800 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - adx1_in_ep: endpoint { - remote-endpoint = <&xbar_adx1_in_ep>; - }; - }; - - adx1_out1_port: port@1 { - reg = <1>; - - adx1_out1_ep: endpoint { - remote-endpoint = <&xbar_adx1_out1_ep>; - }; - }; - - adx1_out2_port: port@2 { - reg = <2>; - - adx1_out2_ep: endpoint { - remote-endpoint = <&xbar_adx1_out2_ep>; - }; - }; - - adx1_out3_port: port@3 { - reg = <3>; - - adx1_out3_ep: endpoint { - remote-endpoint = <&xbar_adx1_out3_ep>; - }; - }; - - adx1_out4_port: port@4 { - reg = <4>; - - adx1_out4_ep: endpoint { - remote-endpoint = <&xbar_adx1_out4_ep>; - }; - }; - }; - }; - - adx@2903900 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - adx2_in_ep: endpoint { - remote-endpoint = <&xbar_adx2_in_ep>; - }; - }; - - adx2_out1_port: port@1 { - reg = <1>; - - adx2_out1_ep: endpoint { - remote-endpoint = <&xbar_adx2_out1_ep>; - }; - }; - - adx2_out2_port: port@2 { - reg = <2>; - - adx2_out2_ep: endpoint { - remote-endpoint = <&xbar_adx2_out2_ep>; - }; - }; - - adx2_out3_port: port@3 { - reg = <3>; - - adx2_out3_ep: endpoint { - remote-endpoint = <&xbar_adx2_out3_ep>; - }; - }; - - adx2_out4_port: port@4 { - reg = <4>; - - adx2_out4_ep: endpoint { - remote-endpoint = <&xbar_adx2_out4_ep>; - }; - }; - }; - }; - - adx@2903a00 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - adx3_in_ep: endpoint { - remote-endpoint = <&xbar_adx3_in_ep>; - }; - }; - - adx3_out1_port: port@1 { - reg = <1>; - - adx3_out1_ep: endpoint { - remote-endpoint = <&xbar_adx3_out1_ep>; - }; - }; - - adx3_out2_port: port@2 { - reg = <2>; - - adx3_out2_ep: endpoint { - remote-endpoint = <&xbar_adx3_out2_ep>; - }; - }; - - adx3_out3_port: port@3 { - reg = <3>; - - adx3_out3_ep: endpoint { - remote-endpoint = <&xbar_adx3_out3_ep>; - }; - }; - - adx3_out4_port: port@4 { - reg = <4>; - - adx3_out4_ep: endpoint { - remote-endpoint = <&xbar_adx3_out4_ep>; - }; - }; - }; - }; - - adx@2903b00 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - adx4_in_ep: endpoint { - remote-endpoint = <&xbar_adx4_in_ep>; - }; - }; - - adx4_out1_port: port@1 { - reg = <1>; - - adx4_out1_ep: endpoint { - remote-endpoint = <&xbar_adx4_out1_ep>; - }; - }; - - adx4_out2_port: port@2 { - reg = <2>; - - adx4_out2_ep: endpoint { - remote-endpoint = <&xbar_adx4_out2_ep>; - }; - }; - - adx4_out3_port: port@3 { - reg = <3>; - - adx4_out3_ep: endpoint { - remote-endpoint = <&xbar_adx4_out3_ep>; - }; - }; - - adx4_out4_port: port@4 { - reg = <4>; - - adx4_out4_ep: endpoint { - remote-endpoint = <&xbar_adx4_out4_ep>; - }; - }; - }; - }; - - processing-engine@2908000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0x0>; - - ope1_cif_in_ep: endpoint { - remote-endpoint = <&xbar_ope1_in_ep>; - }; - }; - - ope1_out_port: port@1 { - reg = <0x1>; - - ope1_cif_out_ep: endpoint { - remote-endpoint = <&xbar_ope1_out_ep>; - }; - }; - }; - }; - - amixer@290bb00 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0x0>; - - mixer_in1_ep: endpoint { - remote-endpoint = <&xbar_mixer_in1_ep>; - }; - }; - - port@1 { - reg = <0x1>; - - mixer_in2_ep: endpoint { - remote-endpoint = <&xbar_mixer_in2_ep>; - }; - }; - - port@2 { - reg = <0x2>; - - mixer_in3_ep: endpoint { - remote-endpoint = <&xbar_mixer_in3_ep>; - }; - }; - - port@3 { - reg = <0x3>; - - mixer_in4_ep: endpoint { - remote-endpoint = <&xbar_mixer_in4_ep>; - }; - }; - - port@4 { - reg = <0x4>; - - mixer_in5_ep: endpoint { - remote-endpoint = <&xbar_mixer_in5_ep>; - }; - }; - - port@5 { - reg = <0x5>; - - mixer_in6_ep: endpoint { - remote-endpoint = <&xbar_mixer_in6_ep>; - }; - }; - - port@6 { - reg = <0x6>; - - mixer_in7_ep: endpoint { - remote-endpoint = <&xbar_mixer_in7_ep>; - }; - }; - - port@7 { - reg = <0x7>; - - mixer_in8_ep: endpoint { - remote-endpoint = <&xbar_mixer_in8_ep>; - }; - }; - - port@8 { - reg = <0x8>; - - mixer_in9_ep: endpoint { - remote-endpoint = <&xbar_mixer_in9_ep>; - }; - }; - - port@9 { - reg = <0x9>; - - mixer_in10_ep: endpoint { - remote-endpoint = <&xbar_mixer_in10_ep>; - }; - }; - - mixer_out1_port: port@a { - reg = <0xa>; - - mixer_out1_ep: endpoint { - remote-endpoint = <&xbar_mixer_out1_ep>; - }; - }; - - mixer_out2_port: port@b { - reg = <0xb>; - - mixer_out2_ep: endpoint { - remote-endpoint = <&xbar_mixer_out2_ep>; - }; - }; - - mixer_out3_port: port@c { - reg = <0xc>; - - mixer_out3_ep: endpoint { - remote-endpoint = <&xbar_mixer_out3_ep>; - }; - }; - - mixer_out4_port: port@d { - reg = <0xd>; - - mixer_out4_ep: endpoint { - remote-endpoint = <&xbar_mixer_out4_ep>; - }; - }; - - mixer_out5_port: port@e { - reg = <0xe>; - - mixer_out5_ep: endpoint { - remote-endpoint = <&xbar_mixer_out5_ep>; - }; - }; - }; - }; - - asrc@2910000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0x0>; - - asrc_in1_ep: endpoint { - remote-endpoint = <&xbar_asrc_in1_ep>; - }; - }; - - port@1 { - reg = <0x1>; - - asrc_in2_ep: endpoint { - remote-endpoint = <&xbar_asrc_in2_ep>; - }; - }; - - port@2 { - reg = <0x2>; - - asrc_in3_ep: endpoint { - remote-endpoint = <&xbar_asrc_in3_ep>; - }; - }; - - port@3 { - reg = <0x3>; - - asrc_in4_ep: endpoint { - remote-endpoint = <&xbar_asrc_in4_ep>; - }; - }; - - port@4 { - reg = <0x4>; - - asrc_in5_ep: endpoint { - remote-endpoint = <&xbar_asrc_in5_ep>; - }; - }; - - port@5 { - reg = <0x5>; - - asrc_in6_ep: endpoint { - remote-endpoint = <&xbar_asrc_in6_ep>; - }; - }; - - port@6 { - reg = <0x6>; - - asrc_in7_ep: endpoint { - remote-endpoint = <&xbar_asrc_in7_ep>; - }; - }; - - asrc_out1_port: port@7 { - reg = <0x7>; - - asrc_out1_ep: endpoint { - remote-endpoint = <&xbar_asrc_out1_ep>; - }; - }; - - asrc_out2_port: port@8 { - reg = <0x8>; - - asrc_out2_ep: endpoint { - remote-endpoint = <&xbar_asrc_out2_ep>; - }; - }; - - asrc_out3_port: port@9 { - reg = <0x9>; - - asrc_out3_ep: endpoint { - remote-endpoint = <&xbar_asrc_out3_ep>; - }; - }; - - asrc_out4_port: port@a { - reg = <0xa>; - - asrc_out4_ep: endpoint { - remote-endpoint = <&xbar_asrc_out4_ep>; - }; - }; - - asrc_out5_port: port@b { - reg = <0xb>; - - asrc_out5_ep: endpoint { - remote-endpoint = <&xbar_asrc_out5_ep>; - }; - }; - - asrc_out6_port: port@c { - reg = <0xc>; + dma-controller@2930000 { + status = "okay"; + }; - asrc_out6_ep: endpoint { - remote-endpoint = <&xbar_asrc_out6_ep>; - }; - }; - }; - }; + interrupt-controller@2a40000 { + status = "okay"; }; }; @@ -2184,75 +2184,67 @@ GPIO_ACTIVE_LOW>; }; }; - }; - pcie@14100000 { - status = "okay"; + pcie@14100000 { + status = "okay"; - vddio-pex-ctl-supply = <&vdd_1v8ao>; + vddio-pex-ctl-supply = <&vdd_1v8ao>; - phys = <&p2u_hsio_0>; - phy-names = "p2u-0"; - }; - - pcie@14140000 { - status = "okay"; + phys = <&p2u_hsio_0>; + phy-names = "p2u-0"; + }; - vddio-pex-ctl-supply = <&vdd_1v8ao>; + pcie@14140000 { + status = "okay"; - phys = <&p2u_hsio_7>; - phy-names = "p2u-0"; - }; + vddio-pex-ctl-supply = <&vdd_1v8ao>; - pcie@14180000 { - status = "okay"; + phys = <&p2u_hsio_7>; + phy-names = "p2u-0"; + }; - vddio-pex-ctl-supply = <&vdd_1v8ao>; + pcie@14180000 { + status = "okay"; - phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>, - <&p2u_hsio_5>; - phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3"; - }; + vddio-pex-ctl-supply = <&vdd_1v8ao>; - pcie@141a0000 { - status = "okay"; + phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>, + <&p2u_hsio_5>; + phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3"; + }; - vddio-pex-ctl-supply = <&vdd_1v8ao>; - vpcie3v3-supply = <&vdd_3v3_pcie>; - vpcie12v-supply = <&vdd_12v_pcie>; + pcie@141a0000 { + status = "okay"; - phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, - <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, - <&p2u_nvhs_6>, <&p2u_nvhs_7>; + vddio-pex-ctl-supply = <&vdd_1v8ao>; + vpcie3v3-supply = <&vdd_3v3_pcie>; + vpcie12v-supply = <&vdd_12v_pcie>; - phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", - "p2u-5", "p2u-6", "p2u-7"; - }; + phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, + <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, + <&p2u_nvhs_6>, <&p2u_nvhs_7>; - pcie-ep@141a0000 { - status = "disabled"; + phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", + "p2u-5", "p2u-6", "p2u-7"; + }; - vddio-pex-ctl-supply = <&vdd_1v8ao>; + pcie-ep@141a0000 { + status = "disabled"; - reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>; + vddio-pex-ctl-supply = <&vdd_1v8ao>; - nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5) - GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>; - phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, - <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, - <&p2u_nvhs_6>, <&p2u_nvhs_7>; + nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5) + GPIO_ACTIVE_HIGH>; - phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", - "p2u-5", "p2u-6", "p2u-7"; - }; + phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, + <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, + <&p2u_nvhs_6>, <&p2u_nvhs_7>; - fan: pwm-fan { - compatible = "pwm-fan"; - pwms = <&pwm4 0 45334>; - - cooling-levels = <0 64 128 255>; - #cooling-cells = <2>; + phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", + "p2u-5", "p2u-6", "p2u-7"; + }; }; gpio-keys { @@ -2279,6 +2271,14 @@ }; }; + fan: pwm-fan { + compatible = "pwm-fan"; + pwms = <&pwm4 0 45334>; + + cooling-levels = <0 64 128 255>; + #cooling-cells = <2>; + }; + sound { compatible = "nvidia,tegra186-audio-graph-card"; status = "okay"; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi index f212f6aced04..4a17ea5e40fd 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 +#include <dt-bindings/gpio/tegra194-gpio.h> #include <dt-bindings/input/linux-event-codes.h> #include <dt-bindings/input/gpio-keys.h> @@ -8,16 +9,1165 @@ aconnect@2900000 { status = "okay"; - dma-controller@2930000 { + ahub@2900800 { status = "okay"; - }; - interrupt-controller@2a40000 { - status = "okay"; - }; + i2s@2901200 { + status = "okay"; - ahub@2900800 { - status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s3_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s3_ep>; + }; + }; + + i2s3_port: port@1 { + reg = <1>; + + i2s3_dap_ep: endpoint { + dai-format = "i2s"; + /* Place holder for external Codec */ + }; + }; + }; + }; + + i2s@2901400 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s5_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s5_ep>; + }; + }; + + i2s5_port: port@1 { + reg = <1>; + + i2s5_dap_ep: endpoint { + dai-format = "i2s"; + /* Place holder for external Codec */ + }; + }; + }; + }; + + sfc@2902000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sfc1_cif_in_ep: endpoint { + remote-endpoint = <&xbar_sfc1_in_ep>; + convert-rate = <44100>; + }; + }; + + sfc1_out_port: port@1 { + reg = <1>; + + sfc1_cif_out_ep: endpoint { + remote-endpoint = <&xbar_sfc1_out_ep>; + convert-rate = <48000>; + }; + }; + }; + }; + + sfc@2902200 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sfc2_cif_in_ep: endpoint { + remote-endpoint = <&xbar_sfc2_in_ep>; + }; + }; + + sfc2_out_port: port@1 { + reg = <1>; + + sfc2_cif_out_ep: endpoint { + remote-endpoint = <&xbar_sfc2_out_ep>; + }; + }; + }; + }; + + sfc@2902400 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sfc3_cif_in_ep: endpoint { + remote-endpoint = <&xbar_sfc3_in_ep>; + }; + }; + + sfc3_out_port: port@1 { + reg = <1>; + + sfc3_cif_out_ep: endpoint { + remote-endpoint = <&xbar_sfc3_out_ep>; + }; + }; + }; + }; + + sfc@2902600 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sfc4_cif_in_ep: endpoint { + remote-endpoint = <&xbar_sfc4_in_ep>; + }; + }; + + sfc4_out_port: port@1 { + reg = <1>; + + sfc4_cif_out_ep: endpoint { + remote-endpoint = <&xbar_sfc4_out_ep>; + }; + }; + }; + }; + + amx@2903000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + amx1_in1_ep: endpoint { + remote-endpoint = <&xbar_amx1_in1_ep>; + }; + }; + + port@1 { + reg = <1>; + + amx1_in2_ep: endpoint { + remote-endpoint = <&xbar_amx1_in2_ep>; + }; + }; + + port@2 { + reg = <2>; + + amx1_in3_ep: endpoint { + remote-endpoint = <&xbar_amx1_in3_ep>; + }; + }; + + port@3 { + reg = <3>; + + amx1_in4_ep: endpoint { + remote-endpoint = <&xbar_amx1_in4_ep>; + }; + }; + + amx1_out_port: port@4 { + reg = <4>; + + amx1_out_ep: endpoint { + remote-endpoint = <&xbar_amx1_out_ep>; + }; + }; + }; + }; + + amx@2903100 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + amx2_in1_ep: endpoint { + remote-endpoint = <&xbar_amx2_in1_ep>; + }; + }; + + port@1 { + reg = <1>; + + amx2_in2_ep: endpoint { + remote-endpoint = <&xbar_amx2_in2_ep>; + }; + }; + + amx2_in3_port: port@2 { + reg = <2>; + + amx2_in3_ep: endpoint { + remote-endpoint = <&xbar_amx2_in3_ep>; + }; + }; + + amx2_in4_port: port@3 { + reg = <3>; + + amx2_in4_ep: endpoint { + remote-endpoint = <&xbar_amx2_in4_ep>; + }; + }; + + amx2_out_port: port@4 { + reg = <4>; + + amx2_out_ep: endpoint { + remote-endpoint = <&xbar_amx2_out_ep>; + }; + }; + }; + }; + + amx@2903200 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + amx3_in1_ep: endpoint { + remote-endpoint = <&xbar_amx3_in1_ep>; + }; + }; + + port@1 { + reg = <1>; + + amx3_in2_ep: endpoint { + remote-endpoint = <&xbar_amx3_in2_ep>; + }; + }; + + port@2 { + reg = <2>; + + amx3_in3_ep: endpoint { + remote-endpoint = <&xbar_amx3_in3_ep>; + }; + }; + + port@3 { + reg = <3>; + + amx3_in4_ep: endpoint { + remote-endpoint = <&xbar_amx3_in4_ep>; + }; + }; + + amx3_out_port: port@4 { + reg = <4>; + + amx3_out_ep: endpoint { + remote-endpoint = <&xbar_amx3_out_ep>; + }; + }; + }; + }; + + amx@2903300 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + amx4_in1_ep: endpoint { + remote-endpoint = <&xbar_amx4_in1_ep>; + }; + }; + + port@1 { + reg = <1>; + + amx4_in2_ep: endpoint { + remote-endpoint = <&xbar_amx4_in2_ep>; + }; + }; + + port@2 { + reg = <2>; + + amx4_in3_ep: endpoint { + remote-endpoint = <&xbar_amx4_in3_ep>; + }; + }; + + port@3 { + reg = <3>; + + amx4_in4_ep: endpoint { + remote-endpoint = <&xbar_amx4_in4_ep>; + }; + }; + + amx4_out_port: port@4 { + reg = <4>; + + amx4_out_ep: endpoint { + remote-endpoint = <&xbar_amx4_out_ep>; + }; + }; + }; + }; + + adx@2903800 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adx1_in_ep: endpoint { + remote-endpoint = <&xbar_adx1_in_ep>; + }; + }; + + adx1_out1_port: port@1 { + reg = <1>; + + adx1_out1_ep: endpoint { + remote-endpoint = <&xbar_adx1_out1_ep>; + }; + }; + + adx1_out2_port: port@2 { + reg = <2>; + + adx1_out2_ep: endpoint { + remote-endpoint = <&xbar_adx1_out2_ep>; + }; + }; + + adx1_out3_port: port@3 { + reg = <3>; + + adx1_out3_ep: endpoint { + remote-endpoint = <&xbar_adx1_out3_ep>; + }; + }; + + adx1_out4_port: port@4 { + reg = <4>; + + adx1_out4_ep: endpoint { + remote-endpoint = <&xbar_adx1_out4_ep>; + }; + }; + }; + }; + + adx@2903900 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adx2_in_ep: endpoint { + remote-endpoint = <&xbar_adx2_in_ep>; + }; + }; + + adx2_out1_port: port@1 { + reg = <1>; + + adx2_out1_ep: endpoint { + remote-endpoint = <&xbar_adx2_out1_ep>; + }; + }; + + adx2_out2_port: port@2 { + reg = <2>; + + adx2_out2_ep: endpoint { + remote-endpoint = <&xbar_adx2_out2_ep>; + }; + }; + + adx2_out3_port: port@3 { + reg = <3>; + + adx2_out3_ep: endpoint { + remote-endpoint = <&xbar_adx2_out3_ep>; + }; + }; + + adx2_out4_port: port@4 { + reg = <4>; + + adx2_out4_ep: endpoint { + remote-endpoint = <&xbar_adx2_out4_ep>; + }; + }; + }; + }; + + adx@2903a00 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adx3_in_ep: endpoint { + remote-endpoint = <&xbar_adx3_in_ep>; + }; + }; + + adx3_out1_port: port@1 { + reg = <1>; + + adx3_out1_ep: endpoint { + remote-endpoint = <&xbar_adx3_out1_ep>; + }; + }; + + adx3_out2_port: port@2 { + reg = <2>; + + adx3_out2_ep: endpoint { + remote-endpoint = <&xbar_adx3_out2_ep>; + }; + }; + + adx3_out3_port: port@3 { + reg = <3>; + + adx3_out3_ep: endpoint { + remote-endpoint = <&xbar_adx3_out3_ep>; + }; + }; + + adx3_out4_port: port@4 { + reg = <4>; + + adx3_out4_ep: endpoint { + remote-endpoint = <&xbar_adx3_out4_ep>; + }; + }; + }; + }; + + adx@2903b00 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adx4_in_ep: endpoint { + remote-endpoint = <&xbar_adx4_in_ep>; + }; + }; + + adx4_out1_port: port@1 { + reg = <1>; + + adx4_out1_ep: endpoint { + remote-endpoint = <&xbar_adx4_out1_ep>; + }; + }; + + adx4_out2_port: port@2 { + reg = <2>; + + adx4_out2_ep: endpoint { + remote-endpoint = <&xbar_adx4_out2_ep>; + }; + }; + + adx4_out3_port: port@3 { + reg = <3>; + + adx4_out3_ep: endpoint { + remote-endpoint = <&xbar_adx4_out3_ep>; + }; + }; + + adx4_out4_port: port@4 { + reg = <4>; + + adx4_out4_ep: endpoint { + remote-endpoint = <&xbar_adx4_out4_ep>; + }; + }; + }; + }; + + dmic@2904000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dmic1_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic1_ep>; + }; + }; + + dmic1_port: port@1 { + reg = <1>; + + dmic1_dap_ep: endpoint { + /* Place holder for external Codec */ + }; + }; + }; + }; + + dmic@2904100 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dmic2_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic2_ep>; + }; + }; + + dmic2_port: port@1 { + reg = <1>; + + dmic2_dap_ep: endpoint { + /* Place holder for external Codec */ + }; + }; + }; + }; + + dmic@2904300 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dmic4_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic4_ep>; + }; + }; + + dmic4_port: port@1 { + reg = <1>; + + dmic4_dap_ep: endpoint { + /* Place holder for external Codec */ + }; + }; + }; + }; + + dspk@2905000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dspk1_cif_ep: endpoint { + remote-endpoint = <&xbar_dspk1_ep>; + }; + }; + + dspk1_port: port@1 { + reg = <1>; + + dspk1_dap_ep: endpoint { + /* Place holder for external Codec */ + }; + }; + }; + }; + + dspk@2905100 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dspk2_cif_ep: endpoint { + remote-endpoint = <&xbar_dspk2_ep>; + }; + }; + + dspk2_port: port@1 { + reg = <1>; + + dspk2_dap_ep: endpoint { + /* Place holder for external Codec */ + }; + }; + }; + }; + + processing-engine@2908000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + ope1_cif_in_ep: endpoint { + remote-endpoint = <&xbar_ope1_in_ep>; + }; + }; + + ope1_out_port: port@1 { + reg = <0x1>; + + ope1_cif_out_ep: endpoint { + remote-endpoint = <&xbar_ope1_out_ep>; + }; + }; + }; + }; + + mvc@290a000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mvc1_cif_in_ep: endpoint { + remote-endpoint = <&xbar_mvc1_in_ep>; + }; + }; + + mvc1_out_port: port@1 { + reg = <1>; + + mvc1_cif_out_ep: endpoint { + remote-endpoint = <&xbar_mvc1_out_ep>; + }; + }; + }; + }; + + mvc@290a200 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mvc2_cif_in_ep: endpoint { + remote-endpoint = <&xbar_mvc2_in_ep>; + }; + }; + + mvc2_out_port: port@1 { + reg = <1>; + + mvc2_cif_out_ep: endpoint { + remote-endpoint = <&xbar_mvc2_out_ep>; + }; + }; + }; + }; + + amixer@290bb00 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + mixer_in1_ep: endpoint { + remote-endpoint = <&xbar_mixer_in1_ep>; + }; + }; + + port@1 { + reg = <0x1>; + + mixer_in2_ep: endpoint { + remote-endpoint = <&xbar_mixer_in2_ep>; + }; + }; + + port@2 { + reg = <0x2>; + + mixer_in3_ep: endpoint { + remote-endpoint = <&xbar_mixer_in3_ep>; + }; + }; + + port@3 { + reg = <0x3>; + + mixer_in4_ep: endpoint { + remote-endpoint = <&xbar_mixer_in4_ep>; + }; + }; + + port@4 { + reg = <0x4>; + + mixer_in5_ep: endpoint { + remote-endpoint = <&xbar_mixer_in5_ep>; + }; + }; + + port@5 { + reg = <0x5>; + + mixer_in6_ep: endpoint { + remote-endpoint = <&xbar_mixer_in6_ep>; + }; + }; + + port@6 { + reg = <0x6>; + + mixer_in7_ep: endpoint { + remote-endpoint = <&xbar_mixer_in7_ep>; + }; + }; + + port@7 { + reg = <0x7>; + + mixer_in8_ep: endpoint { + remote-endpoint = <&xbar_mixer_in8_ep>; + }; + }; + + port@8 { + reg = <0x8>; + + mixer_in9_ep: endpoint { + remote-endpoint = <&xbar_mixer_in9_ep>; + }; + }; + + port@9 { + reg = <0x9>; + + mixer_in10_ep: endpoint { + remote-endpoint = <&xbar_mixer_in10_ep>; + }; + }; + + mixer_out1_port: port@a { + reg = <0xa>; + + mixer_out1_ep: endpoint { + remote-endpoint = <&xbar_mixer_out1_ep>; + }; + }; + + mixer_out2_port: port@b { + reg = <0xb>; + + mixer_out2_ep: endpoint { + remote-endpoint = <&xbar_mixer_out2_ep>; + }; + }; + + mixer_out3_port: port@c { + reg = <0xc>; + + mixer_out3_ep: endpoint { + remote-endpoint = <&xbar_mixer_out3_ep>; + }; + }; + + mixer_out4_port: port@d { + reg = <0xd>; + + mixer_out4_ep: endpoint { + remote-endpoint = <&xbar_mixer_out4_ep>; + }; + }; + + mixer_out5_port: port@e { + reg = <0xe>; + + mixer_out5_ep: endpoint { + remote-endpoint = <&xbar_mixer_out5_ep>; + }; + }; + }; + }; + + admaif@290f000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + admaif0_port: port@0 { + reg = <0x0>; + + admaif0_ep: endpoint { + remote-endpoint = <&xbar_admaif0_ep>; + }; + }; + + admaif1_port: port@1 { + reg = <0x1>; + + admaif1_ep: endpoint { + remote-endpoint = <&xbar_admaif1_ep>; + }; + }; + + admaif2_port: port@2 { + reg = <0x2>; + + admaif2_ep: endpoint { + remote-endpoint = <&xbar_admaif2_ep>; + }; + }; + + admaif3_port: port@3 { + reg = <0x3>; + + admaif3_ep: endpoint { + remote-endpoint = <&xbar_admaif3_ep>; + }; + }; + + admaif4_port: port@4 { + reg = <0x4>; + + admaif4_ep: endpoint { + remote-endpoint = <&xbar_admaif4_ep>; + }; + }; + + admaif5_port: port@5 { + reg = <0x5>; + + admaif5_ep: endpoint { + remote-endpoint = <&xbar_admaif5_ep>; + }; + }; + + admaif6_port: port@6 { + reg = <0x6>; + + admaif6_ep: endpoint { + remote-endpoint = <&xbar_admaif6_ep>; + }; + }; + + admaif7_port: port@7 { + reg = <0x7>; + + admaif7_ep: endpoint { + remote-endpoint = <&xbar_admaif7_ep>; + }; + }; + + admaif8_port: port@8 { + reg = <0x8>; + + admaif8_ep: endpoint { + remote-endpoint = <&xbar_admaif8_ep>; + }; + }; + + admaif9_port: port@9 { + reg = <0x9>; + + admaif9_ep: endpoint { + remote-endpoint = <&xbar_admaif9_ep>; + }; + }; + + admaif10_port: port@a { + reg = <0xa>; + + admaif10_ep: endpoint { + remote-endpoint = <&xbar_admaif10_ep>; + }; + }; + + admaif11_port: port@b { + reg = <0xb>; + + admaif11_ep: endpoint { + remote-endpoint = <&xbar_admaif11_ep>; + }; + }; + + admaif12_port: port@c { + reg = <0xc>; + + admaif12_ep: endpoint { + remote-endpoint = <&xbar_admaif12_ep>; + }; + }; + + admaif13_port: port@d { + reg = <0xd>; + + admaif13_ep: endpoint { + remote-endpoint = <&xbar_admaif13_ep>; + }; + }; + + admaif14_port: port@e { + reg = <0xe>; + + admaif14_ep: endpoint { + remote-endpoint = <&xbar_admaif14_ep>; + }; + }; + + admaif15_port: port@f { + reg = <0xf>; + + admaif15_ep: endpoint { + remote-endpoint = <&xbar_admaif15_ep>; + }; + }; + + admaif16_port: port@10 { + reg = <0x10>; + + admaif16_ep: endpoint { + remote-endpoint = <&xbar_admaif16_ep>; + }; + }; + + admaif17_port: port@11 { + reg = <0x11>; + + admaif17_ep: endpoint { + remote-endpoint = <&xbar_admaif17_ep>; + }; + }; + + admaif18_port: port@12 { + reg = <0x12>; + + admaif18_ep: endpoint { + remote-endpoint = <&xbar_admaif18_ep>; + }; + }; + + admaif19_port: port@13 { + reg = <0x13>; + + admaif19_ep: endpoint { + remote-endpoint = <&xbar_admaif19_ep>; + }; + }; + }; + }; + + asrc@2910000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + asrc_in1_ep: endpoint { + remote-endpoint = <&xbar_asrc_in1_ep>; + }; + }; + + port@1 { + reg = <0x1>; + + asrc_in2_ep: endpoint { + remote-endpoint = <&xbar_asrc_in2_ep>; + }; + }; + + port@2 { + reg = <0x2>; + + asrc_in3_ep: endpoint { + remote-endpoint = <&xbar_asrc_in3_ep>; + }; + }; + + port@3 { + reg = <0x3>; + + asrc_in4_ep: endpoint { + remote-endpoint = <&xbar_asrc_in4_ep>; + }; + }; + + port@4 { + reg = <0x4>; + + asrc_in5_ep: endpoint { + remote-endpoint = <&xbar_asrc_in5_ep>; + }; + }; + + port@5 { + reg = <0x5>; + + asrc_in6_ep: endpoint { + remote-endpoint = <&xbar_asrc_in6_ep>; + }; + }; + + port@6 { + reg = <0x6>; + + asrc_in7_ep: endpoint { + remote-endpoint = <&xbar_asrc_in7_ep>; + }; + }; + + asrc_out1_port: port@7 { + reg = <0x7>; + + asrc_out1_ep: endpoint { + remote-endpoint = <&xbar_asrc_out1_ep>; + }; + }; + + asrc_out2_port: port@8 { + reg = <0x8>; + + asrc_out2_ep: endpoint { + remote-endpoint = <&xbar_asrc_out2_ep>; + }; + }; + + asrc_out3_port: port@9 { + reg = <0x9>; + + asrc_out3_ep: endpoint { + remote-endpoint = <&xbar_asrc_out3_ep>; + }; + }; + + asrc_out4_port: port@a { + reg = <0xa>; + + asrc_out4_ep: endpoint { + remote-endpoint = <&xbar_asrc_out4_ep>; + }; + }; + + asrc_out5_port: port@b { + reg = <0xb>; + + asrc_out5_ep: endpoint { + remote-endpoint = <&xbar_asrc_out5_ep>; + }; + }; + + asrc_out6_port: port@c { + reg = <0xc>; + + asrc_out6_ep: endpoint { + remote-endpoint = <&xbar_asrc_out6_ep>; + }; + }; + }; + }; ports { #address-cells = <1>; @@ -895,1168 +2045,15 @@ }; }; }; + }; - admaif@290f000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - admaif0_port: port@0 { - reg = <0x0>; - - admaif0_ep: endpoint { - remote-endpoint = <&xbar_admaif0_ep>; - }; - }; - - admaif1_port: port@1 { - reg = <0x1>; - - admaif1_ep: endpoint { - remote-endpoint = <&xbar_admaif1_ep>; - }; - }; - - admaif2_port: port@2 { - reg = <0x2>; - - admaif2_ep: endpoint { - remote-endpoint = <&xbar_admaif2_ep>; - }; - }; - - admaif3_port: port@3 { - reg = <0x3>; - - admaif3_ep: endpoint { - remote-endpoint = <&xbar_admaif3_ep>; - }; - }; - - admaif4_port: port@4 { - reg = <0x4>; - - admaif4_ep: endpoint { - remote-endpoint = <&xbar_admaif4_ep>; - }; - }; - - admaif5_port: port@5 { - reg = <0x5>; - - admaif5_ep: endpoint { - remote-endpoint = <&xbar_admaif5_ep>; - }; - }; - - admaif6_port: port@6 { - reg = <0x6>; - - admaif6_ep: endpoint { - remote-endpoint = <&xbar_admaif6_ep>; - }; - }; - - admaif7_port: port@7 { - reg = <0x7>; - - admaif7_ep: endpoint { - remote-endpoint = <&xbar_admaif7_ep>; - }; - }; - - admaif8_port: port@8 { - reg = <0x8>; - - admaif8_ep: endpoint { - remote-endpoint = <&xbar_admaif8_ep>; - }; - }; - - admaif9_port: port@9 { - reg = <0x9>; - - admaif9_ep: endpoint { - remote-endpoint = <&xbar_admaif9_ep>; - }; - }; - - admaif10_port: port@a { - reg = <0xa>; - - admaif10_ep: endpoint { - remote-endpoint = <&xbar_admaif10_ep>; - }; - }; - - admaif11_port: port@b { - reg = <0xb>; - - admaif11_ep: endpoint { - remote-endpoint = <&xbar_admaif11_ep>; - }; - }; - - admaif12_port: port@c { - reg = <0xc>; - - admaif12_ep: endpoint { - remote-endpoint = <&xbar_admaif12_ep>; - }; - }; - - admaif13_port: port@d { - reg = <0xd>; - - admaif13_ep: endpoint { - remote-endpoint = <&xbar_admaif13_ep>; - }; - }; - - admaif14_port: port@e { - reg = <0xe>; - - admaif14_ep: endpoint { - remote-endpoint = <&xbar_admaif14_ep>; - }; - }; - - admaif15_port: port@f { - reg = <0xf>; - - admaif15_ep: endpoint { - remote-endpoint = <&xbar_admaif15_ep>; - }; - }; - - admaif16_port: port@10 { - reg = <0x10>; - - admaif16_ep: endpoint { - remote-endpoint = <&xbar_admaif16_ep>; - }; - }; - - admaif17_port: port@11 { - reg = <0x11>; - - admaif17_ep: endpoint { - remote-endpoint = <&xbar_admaif17_ep>; - }; - }; - - admaif18_port: port@12 { - reg = <0x12>; - - admaif18_ep: endpoint { - remote-endpoint = <&xbar_admaif18_ep>; - }; - }; - - admaif19_port: port@13 { - reg = <0x13>; - - admaif19_ep: endpoint { - remote-endpoint = <&xbar_admaif19_ep>; - }; - }; - }; - }; - - i2s@2901200 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2s3_cif_ep: endpoint { - remote-endpoint = <&xbar_i2s3_ep>; - }; - }; - - i2s3_port: port@1 { - reg = <1>; - - i2s3_dap_ep: endpoint { - dai-format = "i2s"; - /* Place holder for external Codec */ - }; - }; - }; - }; - - i2s@2901400 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2s5_cif_ep: endpoint { - remote-endpoint = <&xbar_i2s5_ep>; - }; - }; - - i2s5_port: port@1 { - reg = <1>; - - i2s5_dap_ep: endpoint { - dai-format = "i2s"; - /* Place holder for external Codec */ - }; - }; - }; - }; - - dmic@2904000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dmic1_cif_ep: endpoint { - remote-endpoint = <&xbar_dmic1_ep>; - }; - }; - - dmic1_port: port@1 { - reg = <1>; - - dmic1_dap_ep: endpoint { - /* Place holder for external Codec */ - }; - }; - }; - }; - - dmic@2904100 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dmic2_cif_ep: endpoint { - remote-endpoint = <&xbar_dmic2_ep>; - }; - }; - - dmic2_port: port@1 { - reg = <1>; - - dmic2_dap_ep: endpoint { - /* Place holder for external Codec */ - }; - }; - }; - }; - - dmic@2904300 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dmic4_cif_ep: endpoint { - remote-endpoint = <&xbar_dmic4_ep>; - }; - }; - - dmic4_port: port@1 { - reg = <1>; - - dmic4_dap_ep: endpoint { - /* Place holder for external Codec */ - }; - }; - }; - }; - - dspk@2905000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dspk1_cif_ep: endpoint { - remote-endpoint = <&xbar_dspk1_ep>; - }; - }; - - dspk1_port: port@1 { - reg = <1>; - - dspk1_dap_ep: endpoint { - /* Place holder for external Codec */ - }; - }; - }; - }; - - dspk@2905100 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dspk2_cif_ep: endpoint { - remote-endpoint = <&xbar_dspk2_ep>; - }; - }; - - dspk2_port: port@1 { - reg = <1>; - - dspk2_dap_ep: endpoint { - /* Place holder for external Codec */ - }; - }; - }; - }; - - sfc@2902000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - sfc1_cif_in_ep: endpoint { - remote-endpoint = <&xbar_sfc1_in_ep>; - convert-rate = <44100>; - }; - }; - - sfc1_out_port: port@1 { - reg = <1>; - - sfc1_cif_out_ep: endpoint { - remote-endpoint = <&xbar_sfc1_out_ep>; - convert-rate = <48000>; - }; - }; - }; - }; - - sfc@2902200 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - sfc2_cif_in_ep: endpoint { - remote-endpoint = <&xbar_sfc2_in_ep>; - }; - }; - - sfc2_out_port: port@1 { - reg = <1>; - - sfc2_cif_out_ep: endpoint { - remote-endpoint = <&xbar_sfc2_out_ep>; - }; - }; - }; - }; - - sfc@2902400 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - sfc3_cif_in_ep: endpoint { - remote-endpoint = <&xbar_sfc3_in_ep>; - }; - }; - - sfc3_out_port: port@1 { - reg = <1>; - - sfc3_cif_out_ep: endpoint { - remote-endpoint = <&xbar_sfc3_out_ep>; - }; - }; - }; - }; - - sfc@2902600 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - sfc4_cif_in_ep: endpoint { - remote-endpoint = <&xbar_sfc4_in_ep>; - }; - }; - - sfc4_out_port: port@1 { - reg = <1>; - - sfc4_cif_out_ep: endpoint { - remote-endpoint = <&xbar_sfc4_out_ep>; - }; - }; - }; - }; - - mvc@290a000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - mvc1_cif_in_ep: endpoint { - remote-endpoint = <&xbar_mvc1_in_ep>; - }; - }; - - mvc1_out_port: port@1 { - reg = <1>; - - mvc1_cif_out_ep: endpoint { - remote-endpoint = <&xbar_mvc1_out_ep>; - }; - }; - }; - }; - - mvc@290a200 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - mvc2_cif_in_ep: endpoint { - remote-endpoint = <&xbar_mvc2_in_ep>; - }; - }; - - mvc2_out_port: port@1 { - reg = <1>; - - mvc2_cif_out_ep: endpoint { - remote-endpoint = <&xbar_mvc2_out_ep>; - }; - }; - }; - }; - - amx@2903000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - amx1_in1_ep: endpoint { - remote-endpoint = <&xbar_amx1_in1_ep>; - }; - }; - - port@1 { - reg = <1>; - - amx1_in2_ep: endpoint { - remote-endpoint = <&xbar_amx1_in2_ep>; - }; - }; - - port@2 { - reg = <2>; - - amx1_in3_ep: endpoint { - remote-endpoint = <&xbar_amx1_in3_ep>; - }; - }; - - port@3 { - reg = <3>; - - amx1_in4_ep: endpoint { - remote-endpoint = <&xbar_amx1_in4_ep>; - }; - }; - - amx1_out_port: port@4 { - reg = <4>; - - amx1_out_ep: endpoint { - remote-endpoint = <&xbar_amx1_out_ep>; - }; - }; - }; - }; - - amx@2903100 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - amx2_in1_ep: endpoint { - remote-endpoint = <&xbar_amx2_in1_ep>; - }; - }; - - port@1 { - reg = <1>; - - amx2_in2_ep: endpoint { - remote-endpoint = <&xbar_amx2_in2_ep>; - }; - }; - - amx2_in3_port: port@2 { - reg = <2>; - - amx2_in3_ep: endpoint { - remote-endpoint = <&xbar_amx2_in3_ep>; - }; - }; - - amx2_in4_port: port@3 { - reg = <3>; - - amx2_in4_ep: endpoint { - remote-endpoint = <&xbar_amx2_in4_ep>; - }; - }; - - amx2_out_port: port@4 { - reg = <4>; - - amx2_out_ep: endpoint { - remote-endpoint = <&xbar_amx2_out_ep>; - }; - }; - }; - }; - - amx@2903200 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - amx3_in1_ep: endpoint { - remote-endpoint = <&xbar_amx3_in1_ep>; - }; - }; - - port@1 { - reg = <1>; - - amx3_in2_ep: endpoint { - remote-endpoint = <&xbar_amx3_in2_ep>; - }; - }; - - port@2 { - reg = <2>; - - amx3_in3_ep: endpoint { - remote-endpoint = <&xbar_amx3_in3_ep>; - }; - }; - - port@3 { - reg = <3>; - - amx3_in4_ep: endpoint { - remote-endpoint = <&xbar_amx3_in4_ep>; - }; - }; - - amx3_out_port: port@4 { - reg = <4>; - - amx3_out_ep: endpoint { - remote-endpoint = <&xbar_amx3_out_ep>; - }; - }; - }; - }; - - amx@2903300 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - amx4_in1_ep: endpoint { - remote-endpoint = <&xbar_amx4_in1_ep>; - }; - }; - - port@1 { - reg = <1>; - - amx4_in2_ep: endpoint { - remote-endpoint = <&xbar_amx4_in2_ep>; - }; - }; - - port@2 { - reg = <2>; - - amx4_in3_ep: endpoint { - remote-endpoint = <&xbar_amx4_in3_ep>; - }; - }; - - port@3 { - reg = <3>; - - amx4_in4_ep: endpoint { - remote-endpoint = <&xbar_amx4_in4_ep>; - }; - }; - - amx4_out_port: port@4 { - reg = <4>; - - amx4_out_ep: endpoint { - remote-endpoint = <&xbar_amx4_out_ep>; - }; - }; - }; - }; - - adx@2903800 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - adx1_in_ep: endpoint { - remote-endpoint = <&xbar_adx1_in_ep>; - }; - }; - - adx1_out1_port: port@1 { - reg = <1>; - - adx1_out1_ep: endpoint { - remote-endpoint = <&xbar_adx1_out1_ep>; - }; - }; - - adx1_out2_port: port@2 { - reg = <2>; - - adx1_out2_ep: endpoint { - remote-endpoint = <&xbar_adx1_out2_ep>; - }; - }; - - adx1_out3_port: port@3 { - reg = <3>; - - adx1_out3_ep: endpoint { - remote-endpoint = <&xbar_adx1_out3_ep>; - }; - }; - - adx1_out4_port: port@4 { - reg = <4>; - - adx1_out4_ep: endpoint { - remote-endpoint = <&xbar_adx1_out4_ep>; - }; - }; - }; - }; - - adx@2903900 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - adx2_in_ep: endpoint { - remote-endpoint = <&xbar_adx2_in_ep>; - }; - }; - - adx2_out1_port: port@1 { - reg = <1>; - - adx2_out1_ep: endpoint { - remote-endpoint = <&xbar_adx2_out1_ep>; - }; - }; - - adx2_out2_port: port@2 { - reg = <2>; - - adx2_out2_ep: endpoint { - remote-endpoint = <&xbar_adx2_out2_ep>; - }; - }; - - adx2_out3_port: port@3 { - reg = <3>; - - adx2_out3_ep: endpoint { - remote-endpoint = <&xbar_adx2_out3_ep>; - }; - }; - - adx2_out4_port: port@4 { - reg = <4>; - - adx2_out4_ep: endpoint { - remote-endpoint = <&xbar_adx2_out4_ep>; - }; - }; - }; - }; - - adx@2903a00 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - adx3_in_ep: endpoint { - remote-endpoint = <&xbar_adx3_in_ep>; - }; - }; - - adx3_out1_port: port@1 { - reg = <1>; - - adx3_out1_ep: endpoint { - remote-endpoint = <&xbar_adx3_out1_ep>; - }; - }; - - adx3_out2_port: port@2 { - reg = <2>; - - adx3_out2_ep: endpoint { - remote-endpoint = <&xbar_adx3_out2_ep>; - }; - }; - - adx3_out3_port: port@3 { - reg = <3>; - - adx3_out3_ep: endpoint { - remote-endpoint = <&xbar_adx3_out3_ep>; - }; - }; - - adx3_out4_port: port@4 { - reg = <4>; - - adx3_out4_ep: endpoint { - remote-endpoint = <&xbar_adx3_out4_ep>; - }; - }; - }; - }; - - adx@2903b00 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - adx4_in_ep: endpoint { - remote-endpoint = <&xbar_adx4_in_ep>; - }; - }; - - adx4_out1_port: port@1 { - reg = <1>; - - adx4_out1_ep: endpoint { - remote-endpoint = <&xbar_adx4_out1_ep>; - }; - }; - - adx4_out2_port: port@2 { - reg = <2>; - - adx4_out2_ep: endpoint { - remote-endpoint = <&xbar_adx4_out2_ep>; - }; - }; - - adx4_out3_port: port@3 { - reg = <3>; - - adx4_out3_ep: endpoint { - remote-endpoint = <&xbar_adx4_out3_ep>; - }; - }; - - adx4_out4_port: port@4 { - reg = <4>; - - adx4_out4_ep: endpoint { - remote-endpoint = <&xbar_adx4_out4_ep>; - }; - }; - }; - }; - - processing-engine@2908000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0x0>; - - ope1_cif_in_ep: endpoint { - remote-endpoint = <&xbar_ope1_in_ep>; - }; - }; - - ope1_out_port: port@1 { - reg = <0x1>; - - ope1_cif_out_ep: endpoint { - remote-endpoint = <&xbar_ope1_out_ep>; - }; - }; - }; - }; - - amixer@290bb00 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0x0>; - - mixer_in1_ep: endpoint { - remote-endpoint = <&xbar_mixer_in1_ep>; - }; - }; - - port@1 { - reg = <0x1>; - - mixer_in2_ep: endpoint { - remote-endpoint = <&xbar_mixer_in2_ep>; - }; - }; - - port@2 { - reg = <0x2>; - - mixer_in3_ep: endpoint { - remote-endpoint = <&xbar_mixer_in3_ep>; - }; - }; - - port@3 { - reg = <0x3>; - - mixer_in4_ep: endpoint { - remote-endpoint = <&xbar_mixer_in4_ep>; - }; - }; - - port@4 { - reg = <0x4>; - - mixer_in5_ep: endpoint { - remote-endpoint = <&xbar_mixer_in5_ep>; - }; - }; - - port@5 { - reg = <0x5>; - - mixer_in6_ep: endpoint { - remote-endpoint = <&xbar_mixer_in6_ep>; - }; - }; - - port@6 { - reg = <0x6>; - - mixer_in7_ep: endpoint { - remote-endpoint = <&xbar_mixer_in7_ep>; - }; - }; - - port@7 { - reg = <0x7>; - - mixer_in8_ep: endpoint { - remote-endpoint = <&xbar_mixer_in8_ep>; - }; - }; - - port@8 { - reg = <0x8>; - - mixer_in9_ep: endpoint { - remote-endpoint = <&xbar_mixer_in9_ep>; - }; - }; - - port@9 { - reg = <0x9>; - - mixer_in10_ep: endpoint { - remote-endpoint = <&xbar_mixer_in10_ep>; - }; - }; - - mixer_out1_port: port@a { - reg = <0xa>; - - mixer_out1_ep: endpoint { - remote-endpoint = <&xbar_mixer_out1_ep>; - }; - }; - - mixer_out2_port: port@b { - reg = <0xb>; - - mixer_out2_ep: endpoint { - remote-endpoint = <&xbar_mixer_out2_ep>; - }; - }; - - mixer_out3_port: port@c { - reg = <0xc>; - - mixer_out3_ep: endpoint { - remote-endpoint = <&xbar_mixer_out3_ep>; - }; - }; - - mixer_out4_port: port@d { - reg = <0xd>; - - mixer_out4_ep: endpoint { - remote-endpoint = <&xbar_mixer_out4_ep>; - }; - }; - - mixer_out5_port: port@e { - reg = <0xe>; - - mixer_out5_ep: endpoint { - remote-endpoint = <&xbar_mixer_out5_ep>; - }; - }; - }; - }; - - asrc@2910000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0x0>; - - asrc_in1_ep: endpoint { - remote-endpoint = <&xbar_asrc_in1_ep>; - }; - }; - - port@1 { - reg = <0x1>; - - asrc_in2_ep: endpoint { - remote-endpoint = <&xbar_asrc_in2_ep>; - }; - }; - - port@2 { - reg = <0x2>; - - asrc_in3_ep: endpoint { - remote-endpoint = <&xbar_asrc_in3_ep>; - }; - }; - - port@3 { - reg = <0x3>; - - asrc_in4_ep: endpoint { - remote-endpoint = <&xbar_asrc_in4_ep>; - }; - }; - - port@4 { - reg = <0x4>; - - asrc_in5_ep: endpoint { - remote-endpoint = <&xbar_asrc_in5_ep>; - }; - }; - - port@5 { - reg = <0x5>; - - asrc_in6_ep: endpoint { - remote-endpoint = <&xbar_asrc_in6_ep>; - }; - }; - - port@6 { - reg = <0x6>; - - asrc_in7_ep: endpoint { - remote-endpoint = <&xbar_asrc_in7_ep>; - }; - }; - - asrc_out1_port: port@7 { - reg = <0x7>; - - asrc_out1_ep: endpoint { - remote-endpoint = <&xbar_asrc_out1_ep>; - }; - }; - - asrc_out2_port: port@8 { - reg = <0x8>; - - asrc_out2_ep: endpoint { - remote-endpoint = <&xbar_asrc_out2_ep>; - }; - }; - - asrc_out3_port: port@9 { - reg = <0x9>; - - asrc_out3_ep: endpoint { - remote-endpoint = <&xbar_asrc_out3_ep>; - }; - }; - - asrc_out4_port: port@a { - reg = <0xa>; - - asrc_out4_ep: endpoint { - remote-endpoint = <&xbar_asrc_out4_ep>; - }; - }; - - asrc_out5_port: port@b { - reg = <0xb>; - - asrc_out5_ep: endpoint { - remote-endpoint = <&xbar_asrc_out5_ep>; - }; - }; - - asrc_out6_port: port@c { - reg = <0xc>; - - asrc_out6_ep: endpoint { - remote-endpoint = <&xbar_asrc_out6_ep>; - }; - }; - }; - }; + dma-controller@2930000 { + status = "okay"; }; - }; - ddc: i2c@3190000 { - status = "okay"; + interrupt-controller@2a40000 { + status = "okay"; + }; }; i2c@3160000 { @@ -2073,6 +2070,26 @@ }; }; + ddc: i2c@3190000 { + status = "okay"; + }; + + spi@3270000 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <102000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; + }; + + pwm@32d0000 { + status = "okay"; + }; + hda@3510000 { nvidia,model = "NVIDIA Jetson Xavier NX HDA"; status = "okay"; @@ -2141,15 +2158,6 @@ }; }; - usb@3610000 { - status = "okay"; - - phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-1}>, - <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-2}>, - <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-2}>; - phy-names = "usb2-1", "usb2-2", "usb3-2"; - }; - usb@3550000 { status = "okay"; @@ -2157,20 +2165,13 @@ phy-names = "usb2-0"; }; - spi@3270000 { + usb@3610000 { status = "okay"; - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <102000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - }; - }; - - pwm@32d0000 { - status = "okay"; + phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-1}>, + <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-2}>, + <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-2}>; + phy-names = "usb2-1", "usb2-2", "usb3-2"; }; host1x@13e00000 { @@ -2209,54 +2210,46 @@ GPIO_ACTIVE_LOW>; }; }; - }; - - pcie@14160000 { - status = "okay"; - - vddio-pex-ctl-supply = <&vdd_1v8ao>; - phys = <&p2u_hsio_11>; - phy-names = "p2u-0"; - }; + pcie@14160000 { + status = "okay"; - pcie@141a0000 { - status = "okay"; + vddio-pex-ctl-supply = <&vdd_1v8ao>; - vddio-pex-ctl-supply = <&vdd_1v8ao>; + phys = <&p2u_hsio_11>; + phy-names = "p2u-0"; + }; - phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, - <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, - <&p2u_nvhs_6>, <&p2u_nvhs_7>; + pcie@141a0000 { + status = "okay"; - phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", - "p2u-5", "p2u-6", "p2u-7"; - }; + vddio-pex-ctl-supply = <&vdd_1v8ao>; - pcie-ep@141a0000 { - status = "disabled"; + phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, + <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, + <&p2u_nvhs_6>, <&p2u_nvhs_7>; - vddio-pex-ctl-supply = <&vdd_1v8ao>; + phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", + "p2u-5", "p2u-6", "p2u-7"; + }; - reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>; + pcie-ep@141a0000 { + status = "disabled"; - nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5) - GPIO_ACTIVE_HIGH>; + vddio-pex-ctl-supply = <&vdd_1v8ao>; - phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, - <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, - <&p2u_nvhs_6>, <&p2u_nvhs_7>; + reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>; - phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", - "p2u-5", "p2u-6", "p2u-7"; - }; + nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5) + GPIO_ACTIVE_HIGH>; - fan: pwm-fan { - compatible = "pwm-fan"; - pwms = <&pwm6 0 45334>; + phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, + <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, + <&p2u_nvhs_6>, <&p2u_nvhs_7>; - cooling-levels = <0 64 128 255>; - #cooling-cells = <2>; + phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", + "p2u-5", "p2u-6", "p2u-7"; + }; }; gpio-keys { @@ -2283,6 +2276,14 @@ }; }; + fan: pwm-fan { + compatible = "pwm-fan"; + pwms = <&pwm6 0 45334>; + + cooling-levels = <0 64 128 255>; + #cooling-cells = <2>; + }; + vdd_5v0_sys: regulator-vdd-5v0-sys { compatible = "regulator-fixed"; regulator-name = "VDD_5V_SYS"; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi index 0751edddf7d5..58f190b0f868 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi @@ -121,6 +121,24 @@ pinctrl-names = "default"; pinctrl-0 = <&max20024_default>; + fps { + fps0 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; + maxim,shutdown-fps-time-period-us = <640>; + }; + + fps1 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; + maxim,shutdown-fps-time-period-us = <640>; + maxim,device-state-on-disabled-event = <MAX77620_FPS_INACTIVE_STATE_SLEEP>; + }; + + fps2 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; + maxim,shutdown-fps-time-period-us = <640>; + }; + }; + max20024_default: pinmux { gpio0 { pins = "gpio0"; @@ -164,24 +182,6 @@ }; }; - fps { - fps0 { - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; - maxim,shutdown-fps-time-period-us = <640>; - }; - - fps1 { - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; - maxim,shutdown-fps-time-period-us = <640>; - maxim,device-state-on-disabled-event = <MAX77620_FPS_INACTIVE_STATE_SLEEP>; - }; - - fps2 { - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; - maxim,shutdown-fps-time-period-us = <640>; - }; - }; - regulators { in-sd0-supply = <&vdd_5v0_sys>; in-sd1-supply = <&vdd_5v0_sys>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 4afcbd60e144..133dbe5b429d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -19,21 +19,22 @@ /* control backbone */ bus@0 { compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x0 0x40000000>; + + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0x0 0x0 0x40000000>; apbmisc: misc@100000 { compatible = "nvidia,tegra194-misc"; - reg = <0x00100000 0xf000>, - <0x0010f000 0x1000>; + reg = <0x0 0x00100000 0x0 0xf000>, + <0x0 0x0010f000 0x0 0x1000>; }; gpio: gpio@2200000 { compatible = "nvidia,tegra194-gpio"; reg-names = "security", "gpio"; - reg = <0x2200000 0x10000>, - <0x2210000 0x10000>; + reg = <0x0 0x2200000 0x0 0x10000>, + <0x0 0x2210000 0x0 0x10000>; interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, @@ -91,7 +92,7 @@ cbb-noc@2300000 { compatible = "nvidia,tegra194-cbb-noc"; - reg = <0x02300000 0x1000>; + reg = <0x0 0x02300000 0x0 0x1000>; interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; nvidia,axi2apb = <&axi2apb>; @@ -101,20 +102,48 @@ axi2apb: axi2apb@2390000 { compatible = "nvidia,tegra194-axi2apb"; - reg = <0x2390000 0x1000>, - <0x23a0000 0x1000>, - <0x23b0000 0x1000>, - <0x23c0000 0x1000>, - <0x23d0000 0x1000>, - <0x23e0000 0x1000>; + reg = <0x0 0x2390000 0x0 0x1000>, + <0x0 0x23a0000 0x0 0x1000>, + <0x0 0x23b0000 0x0 0x1000>, + <0x0 0x23c0000 0x0 0x1000>, + <0x0 0x23d0000 0x0 0x1000>, + <0x0 0x23e0000 0x0 0x1000>; + status = "okay"; + }; + + pinmux: pinmux@2430000 { + compatible = "nvidia,tegra194-pinmux"; + reg = <0x0 0x2430000 0x0 0x17000>; status = "okay"; + + pex_clkreq_c5_bi_dir_state: pinmux-pex-clkreq-c5-bi-dir { + clkreq { + nvidia,pins = "pex_l5_clkreq_n_pgg0"; + nvidia,schmitt = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,io-hv = <TEGRA_PIN_ENABLE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + }; + }; + + pex_rst_c5_out_state: pinmux-pex-rst-c5-out { + pex_rst { + nvidia,pins = "pex_l5_rst_n_pgg1"; + nvidia,schmitt = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,io-hv = <TEGRA_PIN_ENABLE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + }; + }; }; ethernet@2490000 { compatible = "nvidia,tegra194-eqos", "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"; - reg = <0x02490000 0x10000>; + reg = <0x0 0x02490000 0x0 0x10000>; interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, <&bpmp TEGRA194_CLK_EQOS_AXI>, @@ -140,7 +169,7 @@ gpcdma: dma-controller@2600000 { compatible = "nvidia,tegra194-gpcdma", "nvidia,tegra186-gpcdma"; - reg = <0x2600000 0x210000>; + reg = <0x0 0x2600000 0x0 0x210000>; resets = <&bpmp TEGRA194_RESET_GPCDMA>; reset-names = "gpcdma"; interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, @@ -189,137 +218,30 @@ <&bpmp TEGRA194_CLK_APB2APE>; clock-names = "ape", "apb2ape"; power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x02900000 0x02900000 0x200000>; status = "disabled"; - adma: dma-controller@2930000 { - compatible = "nvidia,tegra194-adma", - "nvidia,tegra186-adma"; - reg = <0x02930000 0x20000>; - interrupt-parent = <&agic>; - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - clocks = <&bpmp TEGRA194_CLK_AHUB>; - clock-names = "d_audio"; - status = "disabled"; - }; - - agic: interrupt-controller@2a40000 { - compatible = "nvidia,tegra194-agic", - "nvidia,tegra210-agic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x02a41000 0x1000>, - <0x02a42000 0x2000>; - interrupts = <GIC_SPI 145 - (GIC_CPU_MASK_SIMPLE(4) | - IRQ_TYPE_LEVEL_HIGH)>; - clocks = <&bpmp TEGRA194_CLK_APE>; - clock-names = "clk"; - status = "disabled"; - }; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x02900000 0x0 0x02900000 0x0 0x200000>; tegra_ahub: ahub@2900800 { compatible = "nvidia,tegra194-ahub", "nvidia,tegra186-ahub"; - reg = <0x02900800 0x800>; + reg = <0x0 0x02900800 0x0 0x800>; clocks = <&bpmp TEGRA194_CLK_AHUB>; clock-names = "ahub"; assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>; assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x02900800 0x02900800 0x11800>; status = "disabled"; - tegra_admaif: admaif@290f000 { - compatible = "nvidia,tegra194-admaif", - "nvidia,tegra186-admaif"; - reg = <0x0290f000 0x1000>; - dmas = <&adma 1>, <&adma 1>, - <&adma 2>, <&adma 2>, - <&adma 3>, <&adma 3>, - <&adma 4>, <&adma 4>, - <&adma 5>, <&adma 5>, - <&adma 6>, <&adma 6>, - <&adma 7>, <&adma 7>, - <&adma 8>, <&adma 8>, - <&adma 9>, <&adma 9>, - <&adma 10>, <&adma 10>, - <&adma 11>, <&adma 11>, - <&adma 12>, <&adma 12>, - <&adma 13>, <&adma 13>, - <&adma 14>, <&adma 14>, - <&adma 15>, <&adma 15>, - <&adma 16>, <&adma 16>, - <&adma 17>, <&adma 17>, - <&adma 18>, <&adma 18>, - <&adma 19>, <&adma 19>, - <&adma 20>, <&adma 20>; - dma-names = "rx1", "tx1", - "rx2", "tx2", - "rx3", "tx3", - "rx4", "tx4", - "rx5", "tx5", - "rx6", "tx6", - "rx7", "tx7", - "rx8", "tx8", - "rx9", "tx9", - "rx10", "tx10", - "rx11", "tx11", - "rx12", "tx12", - "rx13", "tx13", - "rx14", "tx14", - "rx15", "tx15", - "rx16", "tx16", - "rx17", "tx17", - "rx18", "tx18", - "rx19", "tx19", - "rx20", "tx20"; - status = "disabled"; - interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>, - <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>; - interconnect-names = "dma-mem", "write"; - iommus = <&smmu TEGRA194_SID_APE>; - }; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>; tegra_i2s1: i2s@2901000 { compatible = "nvidia,tegra194-i2s", "nvidia,tegra210-i2s"; - reg = <0x2901000 0x100>; + reg = <0x0 0x2901000 0x0 0x100>; clocks = <&bpmp TEGRA194_CLK_I2S1>, <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>; clock-names = "i2s", "sync_input"; @@ -333,7 +255,7 @@ tegra_i2s2: i2s@2901100 { compatible = "nvidia,tegra194-i2s", "nvidia,tegra210-i2s"; - reg = <0x2901100 0x100>; + reg = <0x0 0x2901100 0x0 0x100>; clocks = <&bpmp TEGRA194_CLK_I2S2>, <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>; clock-names = "i2s", "sync_input"; @@ -347,7 +269,7 @@ tegra_i2s3: i2s@2901200 { compatible = "nvidia,tegra194-i2s", "nvidia,tegra210-i2s"; - reg = <0x2901200 0x100>; + reg = <0x0 0x2901200 0x0 0x100>; clocks = <&bpmp TEGRA194_CLK_I2S3>, <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>; clock-names = "i2s", "sync_input"; @@ -361,7 +283,7 @@ tegra_i2s4: i2s@2901300 { compatible = "nvidia,tegra194-i2s", "nvidia,tegra210-i2s"; - reg = <0x2901300 0x100>; + reg = <0x0 0x2901300 0x0 0x100>; clocks = <&bpmp TEGRA194_CLK_I2S4>, <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>; clock-names = "i2s", "sync_input"; @@ -375,7 +297,7 @@ tegra_i2s5: i2s@2901400 { compatible = "nvidia,tegra194-i2s", "nvidia,tegra210-i2s"; - reg = <0x2901400 0x100>; + reg = <0x0 0x2901400 0x0 0x100>; clocks = <&bpmp TEGRA194_CLK_I2S5>, <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>; clock-names = "i2s", "sync_input"; @@ -389,7 +311,7 @@ tegra_i2s6: i2s@2901500 { compatible = "nvidia,tegra194-i2s", "nvidia,tegra210-i2s"; - reg = <0x2901500 0x100>; + reg = <0x0 0x2901500 0x0 0x100>; clocks = <&bpmp TEGRA194_CLK_I2S6>, <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>; clock-names = "i2s", "sync_input"; @@ -400,88 +322,10 @@ status = "disabled"; }; - tegra_dmic1: dmic@2904000 { - compatible = "nvidia,tegra194-dmic", - "nvidia,tegra210-dmic"; - reg = <0x2904000 0x100>; - clocks = <&bpmp TEGRA194_CLK_DMIC1>; - clock-names = "dmic"; - assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; - assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; - assigned-clock-rates = <3072000>; - sound-name-prefix = "DMIC1"; - status = "disabled"; - }; - - tegra_dmic2: dmic@2904100 { - compatible = "nvidia,tegra194-dmic", - "nvidia,tegra210-dmic"; - reg = <0x2904100 0x100>; - clocks = <&bpmp TEGRA194_CLK_DMIC2>; - clock-names = "dmic"; - assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; - assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; - assigned-clock-rates = <3072000>; - sound-name-prefix = "DMIC2"; - status = "disabled"; - }; - - tegra_dmic3: dmic@2904200 { - compatible = "nvidia,tegra194-dmic", - "nvidia,tegra210-dmic"; - reg = <0x2904200 0x100>; - clocks = <&bpmp TEGRA194_CLK_DMIC3>; - clock-names = "dmic"; - assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; - assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; - assigned-clock-rates = <3072000>; - sound-name-prefix = "DMIC3"; - status = "disabled"; - }; - - tegra_dmic4: dmic@2904300 { - compatible = "nvidia,tegra194-dmic", - "nvidia,tegra210-dmic"; - reg = <0x2904300 0x100>; - clocks = <&bpmp TEGRA194_CLK_DMIC4>; - clock-names = "dmic"; - assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; - assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; - assigned-clock-rates = <3072000>; - sound-name-prefix = "DMIC4"; - status = "disabled"; - }; - - tegra_dspk1: dspk@2905000 { - compatible = "nvidia,tegra194-dspk", - "nvidia,tegra186-dspk"; - reg = <0x2905000 0x100>; - clocks = <&bpmp TEGRA194_CLK_DSPK1>; - clock-names = "dspk"; - assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; - assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; - assigned-clock-rates = <12288000>; - sound-name-prefix = "DSPK1"; - status = "disabled"; - }; - - tegra_dspk2: dspk@2905100 { - compatible = "nvidia,tegra194-dspk", - "nvidia,tegra186-dspk"; - reg = <0x2905100 0x100>; - clocks = <&bpmp TEGRA194_CLK_DSPK2>; - clock-names = "dspk"; - assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; - assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; - assigned-clock-rates = <12288000>; - sound-name-prefix = "DSPK2"; - status = "disabled"; - }; - tegra_sfc1: sfc@2902000 { compatible = "nvidia,tegra194-sfc", "nvidia,tegra210-sfc"; - reg = <0x2902000 0x200>; + reg = <0x0 0x2902000 0x0 0x200>; sound-name-prefix = "SFC1"; status = "disabled"; }; @@ -489,7 +333,7 @@ tegra_sfc2: sfc@2902200 { compatible = "nvidia,tegra194-sfc", "nvidia,tegra210-sfc"; - reg = <0x2902200 0x200>; + reg = <0x0 0x2902200 0x0 0x200>; sound-name-prefix = "SFC2"; status = "disabled"; }; @@ -497,7 +341,7 @@ tegra_sfc3: sfc@2902400 { compatible = "nvidia,tegra194-sfc", "nvidia,tegra210-sfc"; - reg = <0x2902400 0x200>; + reg = <0x0 0x2902400 0x0 0x200>; sound-name-prefix = "SFC3"; status = "disabled"; }; @@ -505,51 +349,35 @@ tegra_sfc4: sfc@2902600 { compatible = "nvidia,tegra194-sfc", "nvidia,tegra210-sfc"; - reg = <0x2902600 0x200>; + reg = <0x0 0x2902600 0x0 0x200>; sound-name-prefix = "SFC4"; status = "disabled"; }; - tegra_mvc1: mvc@290a000 { - compatible = "nvidia,tegra194-mvc", - "nvidia,tegra210-mvc"; - reg = <0x290a000 0x200>; - sound-name-prefix = "MVC1"; - status = "disabled"; - }; - - tegra_mvc2: mvc@290a200 { - compatible = "nvidia,tegra194-mvc", - "nvidia,tegra210-mvc"; - reg = <0x290a200 0x200>; - sound-name-prefix = "MVC2"; - status = "disabled"; - }; - tegra_amx1: amx@2903000 { compatible = "nvidia,tegra194-amx"; - reg = <0x2903000 0x100>; + reg = <0x0 0x2903000 0x0 0x100>; sound-name-prefix = "AMX1"; status = "disabled"; }; tegra_amx2: amx@2903100 { compatible = "nvidia,tegra194-amx"; - reg = <0x2903100 0x100>; + reg = <0x0 0x2903100 0x0 0x100>; sound-name-prefix = "AMX2"; status = "disabled"; }; tegra_amx3: amx@2903200 { compatible = "nvidia,tegra194-amx"; - reg = <0x2903200 0x100>; + reg = <0x0 0x2903200 0x0 0x100>; sound-name-prefix = "AMX3"; status = "disabled"; }; tegra_amx4: amx@2903300 { compatible = "nvidia,tegra194-amx"; - reg = <0x2903300 0x100>; + reg = <0x0 0x2903300 0x0 0x100>; sound-name-prefix = "AMX4"; status = "disabled"; }; @@ -557,7 +385,7 @@ tegra_adx1: adx@2903800 { compatible = "nvidia,tegra194-adx", "nvidia,tegra210-adx"; - reg = <0x2903800 0x100>; + reg = <0x0 0x2903800 0x0 0x100>; sound-name-prefix = "ADX1"; status = "disabled"; }; @@ -565,7 +393,7 @@ tegra_adx2: adx@2903900 { compatible = "nvidia,tegra194-adx", "nvidia,tegra210-adx"; - reg = <0x2903900 0x100>; + reg = <0x0 0x2903900 0x0 0x100>; sound-name-prefix = "ADX2"; status = "disabled"; }; @@ -573,7 +401,7 @@ tegra_adx3: adx@2903a00 { compatible = "nvidia,tegra194-adx", "nvidia,tegra210-adx"; - reg = <0x2903a00 0x100>; + reg = <0x0 0x2903a00 0x0 0x100>; sound-name-prefix = "ADX3"; status = "disabled"; }; @@ -581,100 +409,276 @@ tegra_adx4: adx@2903b00 { compatible = "nvidia,tegra194-adx", "nvidia,tegra210-adx"; - reg = <0x2903b00 0x100>; + reg = <0x0 0x2903b00 0x0 0x100>; sound-name-prefix = "ADX4"; status = "disabled"; }; + tegra_dmic1: dmic@2904000 { + compatible = "nvidia,tegra194-dmic", + "nvidia,tegra210-dmic"; + reg = <0x0 0x2904000 0x0 0x100>; + clocks = <&bpmp TEGRA194_CLK_DMIC1>; + clock-names = "dmic"; + assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; + assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC1"; + status = "disabled"; + }; + + tegra_dmic2: dmic@2904100 { + compatible = "nvidia,tegra194-dmic", + "nvidia,tegra210-dmic"; + reg = <0x0 0x2904100 0x0 0x100>; + clocks = <&bpmp TEGRA194_CLK_DMIC2>; + clock-names = "dmic"; + assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; + assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC2"; + status = "disabled"; + }; + + tegra_dmic3: dmic@2904200 { + compatible = "nvidia,tegra194-dmic", + "nvidia,tegra210-dmic"; + reg = <0x0 0x2904200 0x0 0x100>; + clocks = <&bpmp TEGRA194_CLK_DMIC3>; + clock-names = "dmic"; + assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; + assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC3"; + status = "disabled"; + }; + + tegra_dmic4: dmic@2904300 { + compatible = "nvidia,tegra194-dmic", + "nvidia,tegra210-dmic"; + reg = <0x0 0x2904300 0x0 0x100>; + clocks = <&bpmp TEGRA194_CLK_DMIC4>; + clock-names = "dmic"; + assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; + assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC4"; + status = "disabled"; + }; + + tegra_dspk1: dspk@2905000 { + compatible = "nvidia,tegra194-dspk", + "nvidia,tegra186-dspk"; + reg = <0x0 0x2905000 0x0 0x100>; + clocks = <&bpmp TEGRA194_CLK_DSPK1>; + clock-names = "dspk"; + assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; + assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; + assigned-clock-rates = <12288000>; + sound-name-prefix = "DSPK1"; + status = "disabled"; + }; + + tegra_dspk2: dspk@2905100 { + compatible = "nvidia,tegra194-dspk", + "nvidia,tegra186-dspk"; + reg = <0x0 0x2905100 0x0 0x100>; + clocks = <&bpmp TEGRA194_CLK_DSPK2>; + clock-names = "dspk"; + assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; + assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; + assigned-clock-rates = <12288000>; + sound-name-prefix = "DSPK2"; + status = "disabled"; + }; + tegra_ope1: processing-engine@2908000 { compatible = "nvidia,tegra194-ope", "nvidia,tegra210-ope"; - reg = <0x2908000 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges; + reg = <0x0 0x2908000 0x0 0x100>; sound-name-prefix = "OPE1"; status = "disabled"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + equalizer@2908100 { compatible = "nvidia,tegra194-peq", "nvidia,tegra210-peq"; - reg = <0x2908100 0x100>; + reg = <0x0 0x2908100 0x0 0x100>; }; dynamic-range-compressor@2908200 { compatible = "nvidia,tegra194-mbdrc", "nvidia,tegra210-mbdrc"; - reg = <0x2908200 0x200>; + reg = <0x0 0x2908200 0x0 0x200>; }; }; + tegra_mvc1: mvc@290a000 { + compatible = "nvidia,tegra194-mvc", + "nvidia,tegra210-mvc"; + reg = <0x0 0x290a000 0x0 0x200>; + sound-name-prefix = "MVC1"; + status = "disabled"; + }; + + tegra_mvc2: mvc@290a200 { + compatible = "nvidia,tegra194-mvc", + "nvidia,tegra210-mvc"; + reg = <0x0 0x290a200 0x0 0x200>; + sound-name-prefix = "MVC2"; + status = "disabled"; + }; + tegra_amixer: amixer@290bb00 { compatible = "nvidia,tegra194-amixer", "nvidia,tegra210-amixer"; - reg = <0x290bb00 0x800>; + reg = <0x0 0x290bb00 0x0 0x800>; sound-name-prefix = "MIXER1"; status = "disabled"; }; + tegra_admaif: admaif@290f000 { + compatible = "nvidia,tegra194-admaif", + "nvidia,tegra186-admaif"; + reg = <0x0 0x0290f000 0x0 0x1000>; + dmas = <&adma 1>, <&adma 1>, + <&adma 2>, <&adma 2>, + <&adma 3>, <&adma 3>, + <&adma 4>, <&adma 4>, + <&adma 5>, <&adma 5>, + <&adma 6>, <&adma 6>, + <&adma 7>, <&adma 7>, + <&adma 8>, <&adma 8>, + <&adma 9>, <&adma 9>, + <&adma 10>, <&adma 10>, + <&adma 11>, <&adma 11>, + <&adma 12>, <&adma 12>, + <&adma 13>, <&adma 13>, + <&adma 14>, <&adma 14>, + <&adma 15>, <&adma 15>, + <&adma 16>, <&adma 16>, + <&adma 17>, <&adma 17>, + <&adma 18>, <&adma 18>, + <&adma 19>, <&adma 19>, + <&adma 20>, <&adma 20>; + dma-names = "rx1", "tx1", + "rx2", "tx2", + "rx3", "tx3", + "rx4", "tx4", + "rx5", "tx5", + "rx6", "tx6", + "rx7", "tx7", + "rx8", "tx8", + "rx9", "tx9", + "rx10", "tx10", + "rx11", "tx11", + "rx12", "tx12", + "rx13", "tx13", + "rx14", "tx14", + "rx15", "tx15", + "rx16", "tx16", + "rx17", "tx17", + "rx18", "tx18", + "rx19", "tx19", + "rx20", "tx20"; + status = "disabled"; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>, + <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA194_SID_APE>; + }; + tegra_asrc: asrc@2910000 { compatible = "nvidia,tegra194-asrc", "nvidia,tegra186-asrc"; - reg = <0x2910000 0x2000>; + reg = <0x0 0x2910000 0x0 0x2000>; sound-name-prefix = "ASRC1"; status = "disabled"; }; }; - }; - pinmux: pinmux@2430000 { - compatible = "nvidia,tegra194-pinmux"; - reg = <0x2430000 0x17000>; - status = "okay"; - - pex_rst_c5_out_state: pinmux-pex-rst-c5-out { - pex_rst { - nvidia,pins = "pex_l5_rst_n_pgg1"; - nvidia,schmitt = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,io-hv = <TEGRA_PIN_ENABLE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - }; + adma: dma-controller@2930000 { + compatible = "nvidia,tegra194-adma", + "nvidia,tegra186-adma"; + reg = <0x0 0x02930000 0x0 0x20000>; + interrupt-parent = <&agic>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + clocks = <&bpmp TEGRA194_CLK_AHUB>; + clock-names = "d_audio"; + status = "disabled"; }; - clkreq_c5_bi_dir_state: pinmux-clkreq-c5-bi-dir { - clkreq { - nvidia,pins = "pex_l5_clkreq_n_pgg0"; - nvidia,schmitt = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,io-hv = <TEGRA_PIN_ENABLE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - }; + agic: interrupt-controller@2a40000 { + compatible = "nvidia,tegra194-agic", + "nvidia,tegra210-agic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x02a41000 0x0 0x1000>, + <0x0 0x02a42000 0x0 0x2000>; + interrupts = <GIC_SPI 145 + (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&bpmp TEGRA194_CLK_APE>; + clock-names = "clk"; + status = "disabled"; }; }; mc: memory-controller@2c00000 { compatible = "nvidia,tegra194-mc"; - reg = <0x02c00000 0x10000>, /* MC-SID */ - <0x02c10000 0x10000>, /* MC Broadcast*/ - <0x02c20000 0x10000>, /* MC0 */ - <0x02c30000 0x10000>, /* MC1 */ - <0x02c40000 0x10000>, /* MC2 */ - <0x02c50000 0x10000>, /* MC3 */ - <0x02b80000 0x10000>, /* MC4 */ - <0x02b90000 0x10000>, /* MC5 */ - <0x02ba0000 0x10000>, /* MC6 */ - <0x02bb0000 0x10000>, /* MC7 */ - <0x01700000 0x10000>, /* MC8 */ - <0x01710000 0x10000>, /* MC9 */ - <0x01720000 0x10000>, /* MC10 */ - <0x01730000 0x10000>, /* MC11 */ - <0x01740000 0x10000>, /* MC12 */ - <0x01750000 0x10000>, /* MC13 */ - <0x01760000 0x10000>, /* MC14 */ - <0x01770000 0x10000>; /* MC15 */ + reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ + <0x0 0x02c10000 0x0 0x10000>, /* MC Broadcast*/ + <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ + <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ + <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ + <0x0 0x02c50000 0x0 0x10000>, /* MC3 */ + <0x0 0x02b80000 0x0 0x10000>, /* MC4 */ + <0x0 0x02b90000 0x0 0x10000>, /* MC5 */ + <0x0 0x02ba0000 0x0 0x10000>, /* MC6 */ + <0x0 0x02bb0000 0x0 0x10000>, /* MC7 */ + <0x0 0x01700000 0x0 0x10000>, /* MC8 */ + <0x0 0x01710000 0x0 0x10000>, /* MC9 */ + <0x0 0x01720000 0x0 0x10000>, /* MC10 */ + <0x0 0x01730000 0x0 0x10000>, /* MC11 */ + <0x0 0x01740000 0x0 0x10000>, /* MC12 */ + <0x0 0x01750000 0x0 0x10000>, /* MC13 */ + <0x0 0x01760000 0x0 0x10000>, /* MC14 */ + <0x0 0x01770000 0x0 0x10000>; /* MC15 */ reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14", "ch15"; @@ -684,10 +688,9 @@ #address-cells = <2>; #size-cells = <2>; - - ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, - <0x02b80000 0x0 0x02b80000 0x0 0x040000>, - <0x02c00000 0x0 0x02c00000 0x0 0x100000>; + ranges = <0x0 0x01700000 0x0 0x01700000 0x0 0x100000>, + <0x0 0x02b80000 0x0 0x02b80000 0x0 0x040000>, + <0x0 0x02c00000 0x0 0x02c00000 0x0 0x100000>; /* * Bit 39 of addresses passing through the memory @@ -704,7 +707,7 @@ * * Limit the DMA range for memory clients to [38:0]. */ - dma-ranges = <0x0 0x0 0x0 0x80 0x0>; + dma-ranges = <0x0 0x0 0x0 0x0 0x80 0x0>; emc: external-memory-controller@2c60000 { compatible = "nvidia,tegra194-emc"; @@ -722,7 +725,7 @@ timer@3010000 { compatible = "nvidia,tegra186-timer"; - reg = <0x03010000 0x000e0000>; + reg = <0x0 0x03010000 0x0 0x000e0000>; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, @@ -738,7 +741,7 @@ uarta: serial@3100000 { compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; - reg = <0x03100000 0x40>; + reg = <0x0 0x03100000 0x0 0x40>; reg-shift = <2>; interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_UARTA>; @@ -750,7 +753,7 @@ uartb: serial@3110000 { compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; - reg = <0x03110000 0x40>; + reg = <0x0 0x03110000 0x0 0x40>; reg-shift = <2>; interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_UARTB>; @@ -762,7 +765,7 @@ uartd: serial@3130000 { compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; - reg = <0x03130000 0x40>; + reg = <0x0 0x03130000 0x0 0x40>; reg-shift = <2>; interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_UARTD>; @@ -774,7 +777,7 @@ uarte: serial@3140000 { compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; - reg = <0x03140000 0x40>; + reg = <0x0 0x03140000 0x0 0x40>; reg-shift = <2>; interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_UARTE>; @@ -786,7 +789,7 @@ uartf: serial@3150000 { compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; - reg = <0x03150000 0x40>; + reg = <0x0 0x03150000 0x0 0x40>; reg-shift = <2>; interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_UARTF>; @@ -798,7 +801,7 @@ gen1_i2c: i2c@3160000 { compatible = "nvidia,tegra194-i2c"; - reg = <0x03160000 0x10000>; + reg = <0x0 0x03160000 0x0 0x10000>; interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; @@ -806,8 +809,6 @@ clock-names = "div-clk"; resets = <&bpmp TEGRA194_RESET_I2C1>; reset-names = "i2c"; - iommus = <&smmu TEGRA194_SID_GPCDMA_0>; - dma-coherent; dmas = <&gpcdma 21>, <&gpcdma 21>; dma-names = "rx", "tx"; status = "disabled"; @@ -815,7 +816,7 @@ uarth: serial@3170000 { compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; - reg = <0x03170000 0x40>; + reg = <0x0 0x03170000 0x0 0x40>; reg-shift = <2>; interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_UARTH>; @@ -827,7 +828,7 @@ cam_i2c: i2c@3180000 { compatible = "nvidia,tegra194-i2c"; - reg = <0x03180000 0x10000>; + reg = <0x0 0x03180000 0x0 0x10000>; interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; @@ -835,8 +836,6 @@ clock-names = "div-clk"; resets = <&bpmp TEGRA194_RESET_I2C3>; reset-names = "i2c"; - iommus = <&smmu TEGRA194_SID_GPCDMA_0>; - dma-coherent; dmas = <&gpcdma 23>, <&gpcdma 23>; dma-names = "rx", "tx"; status = "disabled"; @@ -845,7 +844,7 @@ /* shares pads with dpaux1 */ dp_aux_ch1_i2c: i2c@3190000 { compatible = "nvidia,tegra194-i2c"; - reg = <0x03190000 0x10000>; + reg = <0x0 0x03190000 0x0 0x10000>; interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; @@ -856,8 +855,6 @@ pinctrl-0 = <&state_dpaux1_i2c>; pinctrl-1 = <&state_dpaux1_off>; pinctrl-names = "default", "idle"; - iommus = <&smmu TEGRA194_SID_GPCDMA_0>; - dma-coherent; dmas = <&gpcdma 26>, <&gpcdma 26>; dma-names = "rx", "tx"; status = "disabled"; @@ -866,7 +863,7 @@ /* shares pads with dpaux0 */ dp_aux_ch0_i2c: i2c@31b0000 { compatible = "nvidia,tegra194-i2c"; - reg = <0x031b0000 0x10000>; + reg = <0x0 0x031b0000 0x0 0x10000>; interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; @@ -877,8 +874,6 @@ pinctrl-0 = <&state_dpaux0_i2c>; pinctrl-1 = <&state_dpaux0_off>; pinctrl-names = "default", "idle"; - iommus = <&smmu TEGRA194_SID_GPCDMA_0>; - dma-coherent; dmas = <&gpcdma 30>, <&gpcdma 30>; dma-names = "rx", "tx"; status = "disabled"; @@ -887,7 +882,7 @@ /* shares pads with dpaux2 */ dp_aux_ch2_i2c: i2c@31c0000 { compatible = "nvidia,tegra194-i2c"; - reg = <0x031c0000 0x10000>; + reg = <0x0 0x031c0000 0x0 0x10000>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; @@ -898,8 +893,6 @@ pinctrl-0 = <&state_dpaux2_i2c>; pinctrl-1 = <&state_dpaux2_off>; pinctrl-names = "default", "idle"; - iommus = <&smmu TEGRA194_SID_GPCDMA_0>; - dma-coherent; dmas = <&gpcdma 27>, <&gpcdma 27>; dma-names = "rx", "tx"; status = "disabled"; @@ -908,7 +901,7 @@ /* shares pads with dpaux3 */ dp_aux_ch3_i2c: i2c@31e0000 { compatible = "nvidia,tegra194-i2c"; - reg = <0x031e0000 0x10000>; + reg = <0x0 0x031e0000 0x0 0x10000>; interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; @@ -919,8 +912,6 @@ pinctrl-0 = <&state_dpaux3_i2c>; pinctrl-1 = <&state_dpaux3_off>; pinctrl-names = "default", "idle"; - iommus = <&smmu TEGRA194_SID_GPCDMA_0>; - dma-coherent; dmas = <&gpcdma 31>, <&gpcdma 31>; dma-names = "rx", "tx"; status = "disabled"; @@ -928,7 +919,7 @@ spi@3270000 { compatible = "nvidia,tegra194-qspi"; - reg = <0x3270000 0x1000>; + reg = <0x0 0x3270000 0x0 0x1000>; interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; @@ -939,23 +930,10 @@ status = "disabled"; }; - spi@3300000 { - compatible = "nvidia,tegra194-qspi"; - reg = <0x3300000 0x1000>; - interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&bpmp TEGRA194_CLK_QSPI1>, - <&bpmp TEGRA194_CLK_QSPI1_PM>; - clock-names = "qspi", "qspi_out"; - resets = <&bpmp TEGRA194_RESET_QSPI1>; - status = "disabled"; - }; - pwm1: pwm@3280000 { compatible = "nvidia,tegra194-pwm", "nvidia,tegra186-pwm"; - reg = <0x3280000 0x10000>; + reg = <0x0 0x3280000 0x0 0x10000>; clocks = <&bpmp TEGRA194_CLK_PWM1>; resets = <&bpmp TEGRA194_RESET_PWM1>; reset-names = "pwm"; @@ -966,7 +944,7 @@ pwm2: pwm@3290000 { compatible = "nvidia,tegra194-pwm", "nvidia,tegra186-pwm"; - reg = <0x3290000 0x10000>; + reg = <0x0 0x3290000 0x0 0x10000>; clocks = <&bpmp TEGRA194_CLK_PWM2>; resets = <&bpmp TEGRA194_RESET_PWM2>; reset-names = "pwm"; @@ -977,7 +955,7 @@ pwm3: pwm@32a0000 { compatible = "nvidia,tegra194-pwm", "nvidia,tegra186-pwm"; - reg = <0x32a0000 0x10000>; + reg = <0x0 0x32a0000 0x0 0x10000>; clocks = <&bpmp TEGRA194_CLK_PWM3>; resets = <&bpmp TEGRA194_RESET_PWM3>; reset-names = "pwm"; @@ -988,7 +966,7 @@ pwm5: pwm@32c0000 { compatible = "nvidia,tegra194-pwm", "nvidia,tegra186-pwm"; - reg = <0x32c0000 0x10000>; + reg = <0x0 0x32c0000 0x0 0x10000>; clocks = <&bpmp TEGRA194_CLK_PWM5>; resets = <&bpmp TEGRA194_RESET_PWM5>; reset-names = "pwm"; @@ -999,7 +977,7 @@ pwm6: pwm@32d0000 { compatible = "nvidia,tegra194-pwm", "nvidia,tegra186-pwm"; - reg = <0x32d0000 0x10000>; + reg = <0x0 0x32d0000 0x0 0x10000>; clocks = <&bpmp TEGRA194_CLK_PWM6>; resets = <&bpmp TEGRA194_RESET_PWM6>; reset-names = "pwm"; @@ -1010,7 +988,7 @@ pwm7: pwm@32e0000 { compatible = "nvidia,tegra194-pwm", "nvidia,tegra186-pwm"; - reg = <0x32e0000 0x10000>; + reg = <0x0 0x32e0000 0x0 0x10000>; clocks = <&bpmp TEGRA194_CLK_PWM7>; resets = <&bpmp TEGRA194_RESET_PWM7>; reset-names = "pwm"; @@ -1021,7 +999,7 @@ pwm8: pwm@32f0000 { compatible = "nvidia,tegra194-pwm", "nvidia,tegra186-pwm"; - reg = <0x32f0000 0x10000>; + reg = <0x0 0x32f0000 0x0 0x10000>; clocks = <&bpmp TEGRA194_CLK_PWM8>; resets = <&bpmp TEGRA194_RESET_PWM8>; reset-names = "pwm"; @@ -1029,9 +1007,22 @@ #pwm-cells = <2>; }; + spi@3300000 { + compatible = "nvidia,tegra194-qspi"; + reg = <0x0 0x3300000 0x0 0x1000>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bpmp TEGRA194_CLK_QSPI1>, + <&bpmp TEGRA194_CLK_QSPI1_PM>; + clock-names = "qspi", "qspi_out"; + resets = <&bpmp TEGRA194_RESET_QSPI1>; + status = "disabled"; + }; + sdmmc1: mmc@3400000 { compatible = "nvidia,tegra194-sdhci"; - reg = <0x03400000 0x10000>; + reg = <0x0 0x03400000 0x0 0x10000>; interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_SDMMC1>, <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; @@ -1070,7 +1061,7 @@ sdmmc3: mmc@3440000 { compatible = "nvidia,tegra194-sdhci"; - reg = <0x03440000 0x10000>; + reg = <0x0 0x03440000 0x0 0x10000>; interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_SDMMC3>, <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; @@ -1110,7 +1101,7 @@ sdmmc4: mmc@3460000 { compatible = "nvidia,tegra194-sdhci"; - reg = <0x03460000 0x10000>; + reg = <0x0 0x03460000 0x0 0x10000>; interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_SDMMC4>, <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; @@ -1147,7 +1138,7 @@ hda@3510000 { compatible = "nvidia,tegra194-hda"; - reg = <0x3510000 0x10000>; + reg = <0x0 0x3510000 0x0 0x10000>; interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_HDA>, <&bpmp TEGRA194_CLK_HDA2HDMICODEC>, @@ -1166,8 +1157,8 @@ xusb_padctl: padctl@3520000 { compatible = "nvidia,tegra194-xusb-padctl"; - reg = <0x03520000 0x1000>, - <0x03540000 0x1000>; + reg = <0x0 0x03520000 0x0 0x1000>, + <0x0 0x03540000 0x0 0x1000>; reg-names = "padctl", "ao"; interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; @@ -1274,8 +1265,8 @@ usb@3550000 { compatible = "nvidia,tegra194-xudc"; - reg = <0x03550000 0x8000>, - <0x03558000 0x1000>; + reg = <0x0 0x03550000 0x0 0x8000>, + <0x0 0x03558000 0x0 0x1000>; reg-names = "base", "fpci"; interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, @@ -1291,13 +1282,14 @@ <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; power-domain-names = "dev", "ss"; nvidia,xusb-padctl = <&xusb_padctl>; + dma-coherent; status = "disabled"; }; usb@3610000 { compatible = "nvidia,tegra194-xusb"; - reg = <0x03610000 0x40000>, - <0x03600000 0x10000>; + reg = <0x0 0x03610000 0x0 0x40000>, + <0x0 0x03600000 0x0 0x10000>; reg-names = "hcd", "fpci"; interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, @@ -1331,7 +1323,7 @@ fuse@3820000 { compatible = "nvidia,tegra194-efuse"; - reg = <0x03820000 0x10000>; + reg = <0x0 0x03820000 0x0 0x10000>; clocks = <&bpmp TEGRA194_CLK_FUSE>; clock-names = "fuse"; }; @@ -1340,10 +1332,10 @@ compatible = "arm,gic-400"; #interrupt-cells = <3>; interrupt-controller; - reg = <0x03881000 0x1000>, - <0x03882000 0x2000>, - <0x03884000 0x2000>, - <0x03886000 0x2000>; + reg = <0x0 0x03881000 0x0 0x1000>, + <0x0 0x03882000 0x0 0x2000>, + <0x0 0x03884000 0x0 0x2000>, + <0x0 0x03886000 0x0 0x2000>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; interrupt-parent = <&gic>; @@ -1351,7 +1343,7 @@ cec@3960000 { compatible = "nvidia,tegra194-cec"; - reg = <0x03960000 0x10000>; + reg = <0x0 0x03960000 0x0 0x10000>; interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_CEC>; clock-names = "cec"; @@ -1360,7 +1352,7 @@ hte_lic: hardware-timestamp@3aa0000 { compatible = "nvidia,tegra194-gte-lic"; - reg = <0x3aa0000 0x10000>; + reg = <0x0 0x3aa0000 0x0 0x10000>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; nvidia,int-threshold = <1>; nvidia,slices = <11>; @@ -1370,7 +1362,7 @@ hsp_top0: hsp@3c00000 { compatible = "nvidia,tegra194-hsp"; - reg = <0x03c00000 0xa0000>; + reg = <0x0 0x03c00000 0x0 0xa0000>; interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, @@ -1388,7 +1380,7 @@ p2u_hsio_0: phy@3e10000 { compatible = "nvidia,tegra194-p2u"; - reg = <0x03e10000 0x10000>; + reg = <0x0 0x03e10000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1396,7 +1388,7 @@ p2u_hsio_1: phy@3e20000 { compatible = "nvidia,tegra194-p2u"; - reg = <0x03e20000 0x10000>; + reg = <0x0 0x03e20000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1404,7 +1396,7 @@ p2u_hsio_2: phy@3e30000 { compatible = "nvidia,tegra194-p2u"; - reg = <0x03e30000 0x10000>; + reg = <0x0 0x03e30000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1412,7 +1404,7 @@ p2u_hsio_3: phy@3e40000 { compatible = "nvidia,tegra194-p2u"; - reg = <0x03e40000 0x10000>; + reg = <0x0 0x03e40000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1420,7 +1412,7 @@ p2u_hsio_4: phy@3e50000 { compatible = "nvidia,tegra194-p2u"; - reg = <0x03e50000 0x10000>; + reg = <0x0 0x03e50000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1428,7 +1420,7 @@ p2u_hsio_5: phy@3e60000 { compatible = "nvidia,tegra194-p2u"; - reg = <0x03e60000 0x10000>; + reg = <0x0 0x03e60000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1436,7 +1428,7 @@ p2u_hsio_6: phy@3e70000 { compatible = "nvidia,tegra194-p2u"; - reg = <0x03e70000 0x10000>; + reg = <0x0 0x03e70000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1444,7 +1436,7 @@ p2u_hsio_7: phy@3e80000 { compatible = "nvidia,tegra194-p2u"; - reg = <0x03e80000 0x10000>; + reg = <0x0 0x03e80000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1452,7 +1444,7 @@ p2u_hsio_8: phy@3e90000 { compatible = "nvidia,tegra194-p2u"; - reg = <0x03e90000 0x10000>; + reg = <0x0 0x03e90000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1460,7 +1452,7 @@ p2u_hsio_9: phy@3ea0000 { compatible = "nvidia,tegra194-p2u"; - reg = <0x03ea0000 0x10000>; + reg = <0x0 0x03ea0000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1468,7 +1460,7 @@ p2u_nvhs_0: phy@3eb0000 { compatible = "nvidia,tegra194-p2u"; - reg = <0x03eb0000 0x10000>; + reg = <0x0 0x03eb0000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1476,7 +1468,7 @@ p2u_nvhs_1: phy@3ec0000 { compatible = "nvidia,tegra194-p2u"; - reg = <0x03ec0000 0x10000>; + reg = <0x0 0x03ec0000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1484,7 +1476,7 @@ p2u_nvhs_2: phy@3ed0000 { compatible = "nvidia,tegra194-p2u"; - reg = <0x03ed0000 0x10000>; + reg = <0x0 0x03ed0000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1492,7 +1484,7 @@ p2u_nvhs_3: phy@3ee0000 { compatible = "nvidia,tegra194-p2u"; - reg = <0x03ee0000 0x10000>; + reg = <0x0 0x03ee0000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1500,7 +1492,7 @@ p2u_nvhs_4: phy@3ef0000 { compatible = "nvidia,tegra194-p2u"; - reg = <0x03ef0000 0x10000>; + reg = <0x0 0x03ef0000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1508,7 +1500,7 @@ p2u_nvhs_5: phy@3f00000 { compatible = "nvidia,tegra194-p2u"; - reg = <0x03f00000 0x10000>; + reg = <0x0 0x03f00000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1516,7 +1508,7 @@ p2u_nvhs_6: phy@3f10000 { compatible = "nvidia,tegra194-p2u"; - reg = <0x03f10000 0x10000>; + reg = <0x0 0x03f10000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1524,7 +1516,7 @@ p2u_nvhs_7: phy@3f20000 { compatible = "nvidia,tegra194-p2u"; - reg = <0x03f20000 0x10000>; + reg = <0x0 0x03f20000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1532,7 +1524,7 @@ p2u_hsio_10: phy@3f30000 { compatible = "nvidia,tegra194-p2u"; - reg = <0x03f30000 0x10000>; + reg = <0x0 0x03f30000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1540,7 +1532,7 @@ p2u_hsio_11: phy@3f40000 { compatible = "nvidia,tegra194-p2u"; - reg = <0x03f40000 0x10000>; + reg = <0x0 0x03f40000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1548,7 +1540,7 @@ sce-noc@b600000 { compatible = "nvidia,tegra194-sce-noc"; - reg = <0xb600000 0x1000>; + reg = <0x0 0xb600000 0x0 0x1000>; interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; nvidia,axi2apb = <&axi2apb>; @@ -1558,7 +1550,7 @@ rce-noc@be00000 { compatible = "nvidia,tegra194-rce-noc"; - reg = <0xbe00000 0x1000>; + reg = <0x0 0xbe00000 0x0 0x1000>; interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; nvidia,axi2apb = <&axi2apb>; @@ -1568,7 +1560,7 @@ hsp_aon: hsp@c150000 { compatible = "nvidia,tegra194-hsp"; - reg = <0x0c150000 0x90000>; + reg = <0x0 0x0c150000 0x0 0x90000>; interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, @@ -1583,7 +1575,7 @@ hte_aon: hardware-timestamp@c1e0000 { compatible = "nvidia,tegra194-gte-aon"; - reg = <0xc1e0000 0x10000>; + reg = <0x0 0xc1e0000 0x0 0x10000>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; nvidia,int-threshold = <1>; nvidia,slices = <3>; @@ -1593,7 +1585,7 @@ gen2_i2c: i2c@c240000 { compatible = "nvidia,tegra194-i2c"; - reg = <0x0c240000 0x10000>; + reg = <0x0 0x0c240000 0x0 0x10000>; interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; @@ -1601,8 +1593,6 @@ clock-names = "div-clk"; resets = <&bpmp TEGRA194_RESET_I2C2>; reset-names = "i2c"; - iommus = <&smmu TEGRA194_SID_GPCDMA_0>; - dma-coherent; dmas = <&gpcdma 22>, <&gpcdma 22>; dma-names = "rx", "tx"; status = "disabled"; @@ -1610,7 +1600,7 @@ gen8_i2c: i2c@c250000 { compatible = "nvidia,tegra194-i2c"; - reg = <0x0c250000 0x10000>; + reg = <0x0 0x0c250000 0x0 0x10000>; interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; @@ -1618,8 +1608,6 @@ clock-names = "div-clk"; resets = <&bpmp TEGRA194_RESET_I2C8>; reset-names = "i2c"; - iommus = <&smmu TEGRA194_SID_GPCDMA_0>; - dma-coherent; dmas = <&gpcdma 0>, <&gpcdma 0>; dma-names = "rx", "tx"; status = "disabled"; @@ -1627,7 +1615,7 @@ uartc: serial@c280000 { compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; - reg = <0x0c280000 0x40>; + reg = <0x0 0x0c280000 0x0 0x40>; reg-shift = <2>; interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_UARTC>; @@ -1639,7 +1627,7 @@ uartg: serial@c290000 { compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; - reg = <0x0c290000 0x40>; + reg = <0x0 0x0c290000 0x0 0x40>; reg-shift = <2>; interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_UARTG>; @@ -1651,7 +1639,7 @@ rtc: rtc@c2a0000 { compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; - reg = <0x0c2a0000 0x10000>; + reg = <0x0 0x0c2a0000 0x0 0x10000>; interrupt-parent = <&pmc>; interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_CLK_32K>; @@ -1662,8 +1650,8 @@ gpio_aon: gpio@c2f0000 { compatible = "nvidia,tegra194-gpio-aon"; reg-names = "security", "gpio"; - reg = <0xc2f0000 0x1000>, - <0xc2f1000 0x1000>; + reg = <0x0 0xc2f0000 0x0 0x1000>, + <0x0 0xc2f1000 0x0 0x1000>; interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, @@ -1672,12 +1660,12 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - gpio-range = <&pinmux_aon 0 0 30>; + gpio-ranges = <&pinmux_aon 0 0 30>; }; pinmux_aon: pinmux@c300000 { compatible = "nvidia,tegra194-pinmux-aon"; - reg = <0xc300000 0x4000>; + reg = <0x0 0xc300000 0x0 0x4000>; status = "okay"; }; @@ -1685,7 +1673,7 @@ pwm4: pwm@c340000 { compatible = "nvidia,tegra194-pwm", "nvidia,tegra186-pwm"; - reg = <0xc340000 0x10000>; + reg = <0x0 0xc340000 0x0 0x10000>; clocks = <&bpmp TEGRA194_CLK_PWM4>; resets = <&bpmp TEGRA194_RESET_PWM4>; reset-names = "pwm"; @@ -1695,26 +1683,23 @@ pmc: pmc@c360000 { compatible = "nvidia,tegra194-pmc"; - reg = <0x0c360000 0x10000>, - <0x0c370000 0x10000>, - <0x0c380000 0x10000>, - <0x0c390000 0x10000>, - <0x0c3a0000 0x10000>; + reg = <0x0 0x0c360000 0x0 0x10000>, + <0x0 0x0c370000 0x0 0x10000>, + <0x0 0x0c380000 0x0 0x10000>, + <0x0 0x0c390000 0x0 0x10000>, + <0x0 0x0c3a0000 0x0 0x10000>; reg-names = "pmc", "wake", "aotag", "scratch", "misc"; #interrupt-cells = <2>; interrupt-controller; - sdmmc1_3v3: sdmmc1-3v3 { - pins = "sdmmc1-hv"; - power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; - }; sdmmc1_1v8: sdmmc1-1v8 { pins = "sdmmc1-hv"; power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; }; - sdmmc3_3v3: sdmmc3-3v3 { - pins = "sdmmc3-hv"; + + sdmmc1_3v3: sdmmc1-3v3 { + pins = "sdmmc1-hv"; power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; }; @@ -1723,11 +1708,15 @@ power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; }; + sdmmc3_3v3: sdmmc3-3v3 { + pins = "sdmmc3-hv"; + power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; + }; }; aon-noc@c600000 { compatible = "nvidia,tegra194-aon-noc"; - reg = <0xc600000 0x1000>; + reg = <0x0 0xc600000 0x0 0x1000>; interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; nvidia,apbmisc = <&apbmisc>; @@ -1736,7 +1725,7 @@ bpmp-noc@d600000 { compatible = "nvidia,tegra194-bpmp-noc"; - reg = <0xd600000 0x1000>; + reg = <0x0 0xd600000 0x0 0x1000>; interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; nvidia,axi2apb = <&axi2apb>; @@ -1746,7 +1735,7 @@ iommu@10000000 { compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; - reg = <0x10000000 0x800000>; + reg = <0x0 0x10000000 0x0 0x800000>; interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, @@ -1822,8 +1811,8 @@ smmu: iommu@12000000 { compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; - reg = <0x12000000 0x800000>, - <0x11000000 0x800000>; + reg = <0x0 0x12000000 0x0 0x800000>, + <0x0 0x11000000 0x0 0x800000>; interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, @@ -1900,8 +1889,8 @@ host1x@13e00000 { compatible = "nvidia,tegra194-host1x"; - reg = <0x13e00000 0x10000>, - <0x13e10000 0x10000>; + reg = <0x0 0x13e00000 0x0 0x10000>, + <0x0 0x13e10000 0x0 0x10000>; reg-names = "hypervisor", "vm"; interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; @@ -1911,13 +1900,14 @@ resets = <&bpmp TEGRA194_RESET_HOST1X>; reset-names = "host1x"; - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x14800000 0x0 0x14800000 0x0 0x02800000>; - ranges = <0x14800000 0x14800000 0x02800000>; interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; interconnect-names = "dma-mem"; iommus = <&smmu TEGRA194_SID_HOST1X>; + dma-coherent; /* Context isolation domains */ iommu-map = <0 &smmu TEGRA194_SID_HOST1X_CTX0 1>, @@ -1931,7 +1921,7 @@ nvdec@15140000 { compatible = "nvidia,tegra194-nvdec"; - reg = <0x15140000 0x00040000>; + reg = <0x0 0x15140000 0x0 0x00040000>; clocks = <&bpmp TEGRA194_CLK_NVDEC1>; clock-names = "nvdec"; resets = <&bpmp TEGRA194_RESET_NVDEC1>; @@ -1950,7 +1940,7 @@ display-hub@15200000 { compatible = "nvidia,tegra194-display"; - reg = <0x15200000 0x00040000>; + reg = <0x0 0x15200000 0x0 0x00040000>; resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, @@ -1967,14 +1957,13 @@ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0x15200000 0x15200000 0x40000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x15200000 0x0 0x15200000 0x0 0x40000>; display@15200000 { compatible = "nvidia,tegra194-dc"; - reg = <0x15200000 0x10000>; + reg = <0x0 0x15200000 0x0 0x10000>; interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; clock-names = "dc"; @@ -1992,7 +1981,7 @@ display@15210000 { compatible = "nvidia,tegra194-dc"; - reg = <0x15210000 0x10000>; + reg = <0x0 0x15210000 0x0 0x10000>; interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; clock-names = "dc"; @@ -2010,7 +1999,7 @@ display@15220000 { compatible = "nvidia,tegra194-dc"; - reg = <0x15220000 0x10000>; + reg = <0x0 0x15220000 0x0 0x10000>; interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; clock-names = "dc"; @@ -2028,7 +2017,7 @@ display@15230000 { compatible = "nvidia,tegra194-dc"; - reg = <0x15230000 0x10000>; + reg = <0x0 0x15230000 0x0 0x10000>; interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; clock-names = "dc"; @@ -2047,7 +2036,7 @@ vic@15340000 { compatible = "nvidia,tegra194-vic"; - reg = <0x15340000 0x00040000>; + reg = <0x0 0x15340000 0x0 0x00040000>; interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_VIC>; clock-names = "vic"; @@ -2064,7 +2053,7 @@ nvjpg@15380000 { compatible = "nvidia,tegra194-nvjpg"; - reg = <0x15380000 0x40000>; + reg = <0x0 0x15380000 0x0 0x40000>; clocks = <&bpmp TEGRA194_CLK_NVJPG>; clock-names = "nvjpg"; resets = <&bpmp TEGRA194_RESET_NVJPG>; @@ -2080,7 +2069,7 @@ nvdec@15480000 { compatible = "nvidia,tegra194-nvdec"; - reg = <0x15480000 0x00040000>; + reg = <0x0 0x15480000 0x0 0x00040000>; clocks = <&bpmp TEGRA194_CLK_NVDEC>; clock-names = "nvdec"; resets = <&bpmp TEGRA194_RESET_NVDEC>; @@ -2099,7 +2088,7 @@ nvenc@154c0000 { compatible = "nvidia,tegra194-nvenc"; - reg = <0x154c0000 0x40000>; + reg = <0x0 0x154c0000 0x0 0x40000>; clocks = <&bpmp TEGRA194_CLK_NVENC>; clock-names = "nvenc"; resets = <&bpmp TEGRA194_RESET_NVENC>; @@ -2118,7 +2107,7 @@ dpaux0: dpaux@155c0000 { compatible = "nvidia,tegra194-dpaux"; - reg = <0x155c0000 0x10000>; + reg = <0x0 0x155c0000 0x0 0x10000>; interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_DPAUX>, <&bpmp TEGRA194_CLK_PLLDP>; @@ -2152,7 +2141,7 @@ dpaux1: dpaux@155d0000 { compatible = "nvidia,tegra194-dpaux"; - reg = <0x155d0000 0x10000>; + reg = <0x0 0x155d0000 0x0 0x10000>; interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_DPAUX1>, <&bpmp TEGRA194_CLK_PLLDP>; @@ -2186,7 +2175,7 @@ dpaux2: dpaux@155e0000 { compatible = "nvidia,tegra194-dpaux"; - reg = <0x155e0000 0x10000>; + reg = <0x0 0x155e0000 0x0 0x10000>; interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_DPAUX2>, <&bpmp TEGRA194_CLK_PLLDP>; @@ -2220,7 +2209,7 @@ dpaux3: dpaux@155f0000 { compatible = "nvidia,tegra194-dpaux"; - reg = <0x155f0000 0x10000>; + reg = <0x0 0x155f0000 0x0 0x10000>; interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_DPAUX3>, <&bpmp TEGRA194_CLK_PLLDP>; @@ -2254,7 +2243,7 @@ nvenc@15a80000 { compatible = "nvidia,tegra194-nvenc"; - reg = <0x15a80000 0x00040000>; + reg = <0x0 0x15a80000 0x0 0x00040000>; clocks = <&bpmp TEGRA194_CLK_NVENC1>; clock-names = "nvenc"; resets = <&bpmp TEGRA194_RESET_NVENC1>; @@ -2273,7 +2262,7 @@ sor0: sor@15b00000 { compatible = "nvidia,tegra194-sor"; - reg = <0x15b00000 0x40000>; + reg = <0x0 0x15b00000 0x0 0x40000>; interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, <&bpmp TEGRA194_CLK_SOR0_OUT>, @@ -2297,7 +2286,7 @@ sor1: sor@15b40000 { compatible = "nvidia,tegra194-sor"; - reg = <0x15b40000 0x40000>; + reg = <0x0 0x15b40000 0x0 0x40000>; interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, <&bpmp TEGRA194_CLK_SOR1_OUT>, @@ -2321,7 +2310,7 @@ sor2: sor@15b80000 { compatible = "nvidia,tegra194-sor"; - reg = <0x15b80000 0x40000>; + reg = <0x0 0x15b80000 0x0 0x40000>; interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, <&bpmp TEGRA194_CLK_SOR2_OUT>, @@ -2345,7 +2334,7 @@ sor3: sor@15bc0000 { compatible = "nvidia,tegra194-sor"; - reg = <0x15bc0000 0x40000>; + reg = <0x0 0x15bc0000 0x0 0x40000>; interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, <&bpmp TEGRA194_CLK_SOR3_OUT>, @@ -2368,482 +2357,484 @@ }; }; - gpu@17000000 { - compatible = "nvidia,gv11b"; - reg = <0x17000000 0x1000000>, - <0x18000000 0x1000000>; - interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "stall", "nonstall"; - clocks = <&bpmp TEGRA194_CLK_GPCCLK>, - <&bpmp TEGRA194_CLK_GPU_PWR>, - <&bpmp TEGRA194_CLK_FUSE>; - clock-names = "gpu", "pwr", "fuse"; - resets = <&bpmp TEGRA194_RESET_GPU>; - reset-names = "gpu"; - dma-coherent; + pcie@14100000 { + compatible = "nvidia,tegra194-pcie"; + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; + reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ + <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ + reg-names = "appl", "config", "atu_dma", "dbi"; - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; - interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, - <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, - <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, - <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, - <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, - <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, - <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, - <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, - <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, - <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, - <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, - <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; - interconnect-names = "dma-mem", "read-0-hp", "write-0", - "read-1", "read-1-hp", "write-1", - "read-2", "read-2-hp", "write-2", - "read-3", "read-3-hp", "write-3"; - }; - }; + status = "disabled"; - pcie@14100000 { - compatible = "nvidia,tegra194-pcie"; - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; - reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ - <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ - reg-names = "appl", "config", "atu_dma", "dbi"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <1>; + linux,pci-domain = <1>; - status = "disabled"; + clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; + clock-names = "core"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <1>; - linux,pci-domain = <1>; + resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, + <&bpmp TEGRA194_RESET_PEX0_CORE_1>; + reset-names = "apb", "core"; - clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; - clock-names = "core"; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; - resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, - <&bpmp TEGRA194_RESET_PEX0_CORE_1>; - reset-names = "apb", "core"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; - interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ - <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ - interrupt-names = "intr", "msi"; + nvidia,bpmp = <&bpmp 1>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; - nvidia,bpmp = <&bpmp 1>; + bus-range = <0x0 0xff>; - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; + ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ + <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ + <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ - bus-range = <0x0 0xff>; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, + <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; + }; - ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ - <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ - <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ + pcie@14120000 { + compatible = "nvidia,tegra194-pcie"; + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; + reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ + <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ + reg-names = "appl", "config", "atu_dma", "dbi"; - interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, - <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; - interconnect-names = "dma-mem", "write"; - iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>; - iommu-map-mask = <0x0>; - dma-coherent; - }; + status = "disabled"; - pcie@14120000 { - compatible = "nvidia,tegra194-pcie"; - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; - reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ - <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ - reg-names = "appl", "config", "atu_dma", "dbi"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <1>; + linux,pci-domain = <2>; - status = "disabled"; + clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; + clock-names = "core"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <1>; - linux,pci-domain = <2>; + resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, + <&bpmp TEGRA194_RESET_PEX0_CORE_2>; + reset-names = "apb", "core"; - clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; - clock-names = "core"; + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; - resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, - <&bpmp TEGRA194_RESET_PEX0_CORE_2>; - reset-names = "apb", "core"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; - interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ - <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ - interrupt-names = "intr", "msi"; + nvidia,bpmp = <&bpmp 2>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; - nvidia,bpmp = <&bpmp 2>; + bus-range = <0x0 0xff>; - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; + ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ + <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ + <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ - bus-range = <0x0 0xff>; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, + <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; + }; - ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ - <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ - <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ + pcie@14140000 { + compatible = "nvidia,tegra194-pcie"; + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; + reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ + <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ + reg-names = "appl", "config", "atu_dma", "dbi"; - interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, - <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; - interconnect-names = "dma-mem", "write"; - iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>; - iommu-map-mask = <0x0>; - dma-coherent; - }; + status = "disabled"; - pcie@14140000 { - compatible = "nvidia,tegra194-pcie"; - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; - reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ - <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ - reg-names = "appl", "config", "atu_dma", "dbi"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <1>; + linux,pci-domain = <3>; - status = "disabled"; + clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; + clock-names = "core"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <1>; - linux,pci-domain = <3>; + resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, + <&bpmp TEGRA194_RESET_PEX0_CORE_3>; + reset-names = "apb", "core"; - clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; - clock-names = "core"; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; - resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, - <&bpmp TEGRA194_RESET_PEX0_CORE_3>; - reset-names = "apb", "core"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; - interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ - <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ - interrupt-names = "intr", "msi"; + nvidia,bpmp = <&bpmp 3>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; - nvidia,bpmp = <&bpmp 3>; + bus-range = <0x0 0xff>; - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; + ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ + <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ + <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ - bus-range = <0x0 0xff>; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, + <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; + }; - ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ - <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ - <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ + pcie@14160000 { + compatible = "nvidia,tegra194-pcie"; + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; + reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ + <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ + reg-names = "appl", "config", "atu_dma", "dbi"; - interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, - <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; - interconnect-names = "dma-mem", "write"; - iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>; - iommu-map-mask = <0x0>; - dma-coherent; - }; + status = "disabled"; - pcie@14160000 { - compatible = "nvidia,tegra194-pcie"; - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; - reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ - <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ - reg-names = "appl", "config", "atu_dma", "dbi"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + linux,pci-domain = <4>; - status = "disabled"; + clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; + clock-names = "core"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <4>; - linux,pci-domain = <4>; + resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, + <&bpmp TEGRA194_RESET_PEX0_CORE_4>; + reset-names = "apb", "core"; - clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; - clock-names = "core"; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; - resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, - <&bpmp TEGRA194_RESET_PEX0_CORE_4>; - reset-names = "apb", "core"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; - interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ - <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ - interrupt-names = "intr", "msi"; + nvidia,bpmp = <&bpmp 4>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; - nvidia,bpmp = <&bpmp 4>; + bus-range = <0x0 0xff>; - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; + ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ + <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ + <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ - bus-range = <0x0 0xff>; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, + <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; + }; - ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ - <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ - <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ + pcie-ep@14160000 { + compatible = "nvidia,tegra194-pcie-ep"; + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; + reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ + reg-names = "appl", "atu_dma", "dbi", "addr_space"; - interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, - <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; - interconnect-names = "dma-mem", "write"; - iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; - iommu-map-mask = <0x0>; - dma-coherent; - }; + status = "disabled"; - pcie@14180000 { - compatible = "nvidia,tegra194-pcie"; - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; - reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ - <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ - reg-names = "appl", "config", "atu_dma", "dbi"; + num-lanes = <4>; + num-ib-windows = <2>; + num-ob-windows = <8>; - status = "disabled"; + clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; + clock-names = "core"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <8>; - linux,pci-domain = <0>; + resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, + <&bpmp TEGRA194_RESET_PEX0_CORE_4>; + reset-names = "apb", "core"; - clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; - clock-names = "core"; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ + interrupt-names = "intr"; - resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, - <&bpmp TEGRA194_RESET_PEX0_CORE_0>; - reset-names = "apb", "core"; + nvidia,bpmp = <&bpmp 4>; - interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ - <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ - interrupt-names = "intr", "msi"; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, + <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; + }; - nvidia,bpmp = <&bpmp 0>; + pcie@14180000 { + compatible = "nvidia,tegra194-pcie"; + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; + reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ + <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ + reg-names = "appl", "config", "atu_dma", "dbi"; - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; + status = "disabled"; - bus-range = <0x0 0xff>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <8>; + linux,pci-domain = <0>; - ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ - <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ - <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ + clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; + clock-names = "core"; - interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, - <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; - interconnect-names = "dma-mem", "write"; - iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; - iommu-map-mask = <0x0>; - dma-coherent; - }; + resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, + <&bpmp TEGRA194_RESET_PEX0_CORE_0>; + reset-names = "apb", "core"; - pcie@141a0000 { - compatible = "nvidia,tegra194-pcie"; - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; - reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ - <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ - reg-names = "appl", "config", "atu_dma", "dbi"; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; - status = "disabled"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <8>; - linux,pci-domain = <5>; + nvidia,bpmp = <&bpmp 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; - clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; - clock-names = "core"; + bus-range = <0x0 0xff>; - resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, - <&bpmp TEGRA194_RESET_PEX1_CORE_5>; - reset-names = "apb", "core"; + ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ + <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ + <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ - interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ - <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ - interrupt-names = "intr", "msi"; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, + <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; + }; - nvidia,bpmp = <&bpmp 5>; + pcie-ep@14180000 { + compatible = "nvidia,tegra194-pcie-ep"; + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; + reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ + reg-names = "appl", "atu_dma", "dbi", "addr_space"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; + num-lanes = <8>; + num-ib-windows = <2>; + num-ob-windows = <8>; - bus-range = <0x0 0xff>; + clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; + clock-names = "core"; - ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ - <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ - <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ + resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, + <&bpmp TEGRA194_RESET_PEX0_CORE_0>; + reset-names = "apb", "core"; - interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, - <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; - interconnect-names = "dma-mem", "write"; - iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; - iommu-map-mask = <0x0>; - dma-coherent; - }; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ + interrupt-names = "intr"; - pcie-ep@14160000 { - compatible = "nvidia,tegra194-pcie-ep"; - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; - reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ - <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ - reg-names = "appl", "atu_dma", "dbi", "addr_space"; + nvidia,bpmp = <&bpmp 0>; - status = "disabled"; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; - num-lanes = <4>; - num-ib-windows = <2>; - num-ob-windows = <8>; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, + <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; + }; - clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; - clock-names = "core"; + pcie@141a0000 { + compatible = "nvidia,tegra194-pcie"; + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; + reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ + <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ + reg-names = "appl", "config", "atu_dma", "dbi"; - resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, - <&bpmp TEGRA194_RESET_PEX0_CORE_4>; - reset-names = "apb", "core"; + status = "disabled"; - interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ - interrupt-names = "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <8>; + linux,pci-domain = <5>; - nvidia,bpmp = <&bpmp 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pex_rst_c5_out_state>, <&pex_clkreq_c5_bi_dir_state>; - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; + clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; + clock-names = "core"; - interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, - <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; - interconnect-names = "dma-mem", "write"; - iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; - iommu-map-mask = <0x0>; - dma-coherent; - }; + resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, + <&bpmp TEGRA194_RESET_PEX1_CORE_5>; + reset-names = "apb", "core"; - pcie-ep@14180000 { - compatible = "nvidia,tegra194-pcie-ep"; - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; - reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ - <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ - reg-names = "appl", "atu_dma", "dbi", "addr_space"; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; - status = "disabled"; + nvidia,bpmp = <&bpmp 5>; - num-lanes = <8>; - num-ib-windows = <2>; - num-ob-windows = <8>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; - clock-names = "core"; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; - resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, - <&bpmp TEGRA194_RESET_PEX0_CORE_0>; - reset-names = "apb", "core"; + bus-range = <0x0 0xff>; - interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ - interrupt-names = "intr"; + ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ + <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ + <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ - nvidia,bpmp = <&bpmp 0>; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, + <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; + }; - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; + pcie-ep@141a0000 { + compatible = "nvidia,tegra194-pcie-ep"; + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; + reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ + reg-names = "appl", "atu_dma", "dbi", "addr_space"; - interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, - <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; - interconnect-names = "dma-mem", "write"; - iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; - iommu-map-mask = <0x0>; - dma-coherent; - }; + status = "disabled"; - pcie-ep@141a0000 { - compatible = "nvidia,tegra194-pcie-ep"; - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; - reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ - <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ - reg-names = "appl", "atu_dma", "dbi", "addr_space"; + num-lanes = <8>; + num-ib-windows = <2>; + num-ob-windows = <8>; - status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&pex_clkreq_c5_bi_dir_state>; - num-lanes = <8>; - num-ib-windows = <2>; - num-ob-windows = <8>; + clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; + clock-names = "core"; - pinctrl-names = "default"; - pinctrl-0 = <&clkreq_c5_bi_dir_state>; + resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, + <&bpmp TEGRA194_RESET_PEX1_CORE_5>; + reset-names = "apb", "core"; - clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; - clock-names = "core"; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ + interrupt-names = "intr"; - resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, - <&bpmp TEGRA194_RESET_PEX1_CORE_5>; - reset-names = "apb", "core"; + nvidia,bpmp = <&bpmp 5>; - interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ - interrupt-names = "intr"; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; - nvidia,bpmp = <&bpmp 5>; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, + <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; + }; - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; + gpu@17000000 { + compatible = "nvidia,gv11b"; + reg = <0x0 0x17000000 0x0 0x1000000>, + <0x0 0x18000000 0x0 0x1000000>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "stall", "nonstall"; + clocks = <&bpmp TEGRA194_CLK_GPCCLK>, + <&bpmp TEGRA194_CLK_GPU_PWR>, + <&bpmp TEGRA194_CLK_FUSE>; + clock-names = "gpu", "pwr", "fuse"; + resets = <&bpmp TEGRA194_RESET_GPU>; + reset-names = "gpu"; + dma-coherent; - interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, - <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; - interconnect-names = "dma-mem", "write"; - iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; - iommu-map-mask = <0x0>; - dma-coherent; + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; + interconnect-names = "dma-mem", "read-0-hp", "write-0", + "read-1", "read-1-hp", "write-1", + "read-2", "read-2-hp", "write-2", + "read-3", "read-3-hp", "write-3"; + }; }; sram@40000000 { compatible = "nvidia,tegra194-sysram", "mmio-sram"; reg = <0x0 0x40000000 0x0 0x50000>; + #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x40000000 0x50000>; + no-memory-wc; cpu_bpmp_tx: sram@4e000 { @@ -3117,6 +3108,13 @@ method = "smc"; }; + tcu: serial { + compatible = "nvidia,tegra194-tcu"; + mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, + <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; + mbox-names = "rx", "tx"; + }; + sound { status = "disabled"; @@ -3137,13 +3135,6 @@ assigned-clock-rates = <258000000>; }; - tcu: serial { - compatible = "nvidia,tegra194-tcu"; - mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, - <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; - mbox-names = "rx", "tx"; - }; - thermal-zones { cpu-thermal { thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_CPU>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi index 75eb743a7242..92163b680980 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi @@ -31,6 +31,23 @@ status = "okay"; }; + i2c@7000c500 { + status = "okay"; + + /* module ID EEPROM */ + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + + label = "module"; + vcc-supply = <&vdd_1v8>; + address-width = <8>; + pagesize = <8>; + size = <256>; + read-only; + }; + }; + i2c@7000d000 { status = "okay"; clock-frequency = <400000>; @@ -50,6 +67,22 @@ pinctrl-names = "default"; pinctrl-0 = <&max77620_default>; + fps { + fps0 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; + maxim,suspend-fps-time-period-us = <1280>; + }; + + fps1 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; + maxim,suspend-fps-time-period-us = <1280>; + }; + + fps2 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; + }; + }; + max77620_default: pinmux { gpio0 { pins = "gpio0"; @@ -84,22 +117,6 @@ }; }; - fps { - fps0 { - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; - maxim,suspend-fps-time-period-us = <1280>; - }; - - fps1 { - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; - maxim,suspend-fps-time-period-us = <1280>; - }; - - fps2 { - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; - }; - }; - regulators { in-ldo0-1-supply = <&vdd_pre>; in-ldo7-8-supply = <&vdd_pre>; @@ -265,23 +282,6 @@ }; }; - i2c@7000c500 { - status = "okay"; - - /* module ID EEPROM */ - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - - label = "module"; - vcc-supply = <&vdd_1v8>; - address-width = <8>; - pagesize = <8>; - size = <256>; - read-only; - }; - }; - pmc@7000e400 { nvidia,invert-interrupt; nvidia,suspend-mode = <0>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts index 1e26ca91a944..38f4ff229bef 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts @@ -63,17 +63,17 @@ pwms = <&pwm 0 29334>; pwm-names = "lp8557"; - /* 3 LED string */ - rom_14h { - rom-addr = /bits/ 8 <0x14>; - rom-val = /bits/ 8 <0x87>; - }; - /* boost frequency 1 MHz */ rom_13h { rom-addr = /bits/ 8 <0x13>; rom-val = /bits/ 8 <0x01>; }; + + /* 3 LED string */ + rom_14h { + rom-addr = /bits/ 8 <0x14>; + rom-val = /bits/ 8 <0x87>; + }; }; }; @@ -116,14 +116,6 @@ aconnect@702c0000 { status = "okay"; - dma-controller@702e2000 { - status = "okay"; - }; - - interrupt-controller@702f9000 { - status = "okay"; - }; - ahub@702d0800 { status = "okay"; @@ -261,81 +253,6 @@ }; }; - dmic@702d4000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dmic1_cif_ep: endpoint { - remote-endpoint = <&xbar_dmic1_ep>; - }; - }; - - dmic1_port: port@1 { - reg = <1>; - - dmic1_dap_ep: endpoint { - /* Placeholder for external Codec */ - }; - }; - }; - }; - - dmic@702d4100 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dmic2_cif_ep: endpoint { - remote-endpoint = <&xbar_dmic2_ep>; - }; - }; - - dmic2_port: port@1 { - reg = <1>; - - dmic2_dap_ep: endpoint { - /* Placeholder for external Codec */ - }; - }; - }; - }; - - dmic@702d4200 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dmic3_cif_ep: endpoint { - remote-endpoint = <&xbar_dmic3_ep>; - }; - }; - - dmic3_port: port@1 { - reg = <1>; - - dmic3_dap_ep: endpoint { - /* Placeholder for external Codec */ - }; - }; - }; - }; - sfc@702d2000 { status = "okay"; @@ -436,56 +353,6 @@ }; }; - mvc@702da000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - mvc1_cif_in_ep: endpoint { - remote-endpoint = <&xbar_mvc1_in_ep>; - }; - }; - - mvc1_out_port: port@1 { - reg = <1>; - - mvc1_cif_out_ep: endpoint { - remote-endpoint = <&xbar_mvc1_out_ep>; - }; - }; - }; - }; - - mvc@702da200 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - mvc2_cif_in_ep: endpoint { - remote-endpoint = <&xbar_mvc2_in_ep>; - }; - }; - - mvc2_out_port: port@1 { - reg = <1>; - - mvc2_cif_out_ep: endpoint { - remote-endpoint = <&xbar_mvc2_out_ep>; - }; - }; - }; - }; - amx@702d3000 { status = "okay"; @@ -682,6 +549,81 @@ }; }; + dmic@702d4000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dmic1_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic1_ep>; + }; + }; + + dmic1_port: port@1 { + reg = <1>; + + dmic1_dap_ep: endpoint { + /* Placeholder for external Codec */ + }; + }; + }; + }; + + dmic@702d4100 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dmic2_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic2_ep>; + }; + }; + + dmic2_port: port@1 { + reg = <1>; + + dmic2_dap_ep: endpoint { + /* Placeholder for external Codec */ + }; + }; + }; + }; + + dmic@702d4200 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dmic3_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic3_ep>; + }; + }; + + dmic3_port: port@1 { + reg = <1>; + + dmic3_dap_ep: endpoint { + /* Placeholder for external Codec */ + }; + }; + }; + }; + processing-engine@702d8000 { status = "okay"; @@ -732,6 +674,56 @@ }; }; + mvc@702da000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mvc1_cif_in_ep: endpoint { + remote-endpoint = <&xbar_mvc1_in_ep>; + }; + }; + + mvc1_out_port: port@1 { + reg = <1>; + + mvc1_cif_out_ep: endpoint { + remote-endpoint = <&xbar_mvc1_out_ep>; + }; + }; + }; + }; + + mvc@702da200 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mvc2_cif_in_ep: endpoint { + remote-endpoint = <&xbar_mvc2_in_ep>; + }; + }; + + mvc2_out_port: port@1 { + reg = <1>; + + mvc2_cif_out_ep: endpoint { + remote-endpoint = <&xbar_mvc2_out_ep>; + }; + }; + }; + }; + amixer@702dbb00 { status = "okay"; @@ -1335,6 +1327,14 @@ }; }; }; + + dma-controller@702e2000 { + status = "okay"; + }; + + interrupt-controller@702f9000 { + status = "okay"; + }; }; sound { diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2595.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2595.dtsi index 6ae292da7294..65181da730fa 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2595.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2595.dtsi @@ -1,4 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 + +#include <dt-bindings/pinctrl/pinctrl-tegra.h> + / { model = "NVIDIA Tegra210 P2595 I/O board"; compatible = "nvidia,p2595", "nvidia,tegra210"; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi index dd9a17922fe5..b4a1108c2dd7 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi @@ -1,5 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 + +#include <dt-bindings/gpio/tegra-gpio.h> #include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/pinctrl-tegra.h> / { model = "NVIDIA Tegra210 P2597 I/O board"; @@ -1667,7 +1670,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_cam_1v2: regulator-vdd-cam-1v8 { + vdd_cam_1v2: regulator-vdd-cam-1v2 { compatible = "regulator-fixed"; regulator-name = "vdd-cam-1v2"; regulator-min-microvolt = <1200000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi index 8e657b10569d..1f263fd32a7a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi @@ -1342,7 +1342,35 @@ pinctrl-names = "default"; pinctrl-0 = <&max77620_default>; - max77620_default: pinmux@0 { + fps { + #address-cells = <1>; + #size-cells = <0>; + + fps0 { + reg = <0>; + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; + }; + + fps1 { + reg = <1>; + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; + maxim,device-state-on-disabled-event = <MAX77620_FPS_INACTIVE_STATE_SLEEP>; + }; + + fps2 { + reg = <2>; + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; + }; + }; + + hog-0 { + gpio-hog; + output-high; + gpios = <2 GPIO_ACTIVE_HIGH>, + <7 GPIO_ACTIVE_HIGH>; + }; + + max77620_default: pinmux { gpio0 { pins = "gpio0"; function = "gpio"; @@ -1383,34 +1411,6 @@ }; }; - hog-0 { - gpio-hog; - output-high; - gpios = <2 GPIO_ACTIVE_HIGH>, - <7 GPIO_ACTIVE_HIGH>; - }; - - fps { - #address-cells = <1>; - #size-cells = <0>; - - fps0 { - reg = <0>; - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; - }; - - fps1 { - reg = <1>; - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; - maxim,device-state-on-disabled-event = <MAX77620_FPS_INACTIVE_STATE_SLEEP>; - }; - - fps2 { - reg = <2>; - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; - }; - }; - regulators { in-ldo0-1-supply = <&max77620_sd2>; in-ldo7-8-supply = <&max77620_sd2>; @@ -1592,20 +1592,6 @@ #clock-cells = <0>; }; - gpio-keys { - compatible = "gpio-keys"; - status = "okay"; - - key-power { - debounce-interval = <30>; - gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; - label = "Power"; - linux,code = <KEY_POWER>; - wakeup-event-action = <EV_ACT_ASSERTED>; - wakeup-source; - }; - }; - cpus { cpu@0 { enable-method = "psci"; @@ -1630,6 +1616,20 @@ }; }; + gpio-keys { + compatible = "gpio-keys"; + status = "okay"; + + key-power { + debounce-interval = <30>; + gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; + label = "Power"; + linux,code = <KEY_POWER>; + wakeup-event-action = <EV_ACT_ASSERTED>; + wakeup-source; + }; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index 2041371ea7ff..c9f488e14f37 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -186,6 +186,22 @@ pinctrl-names = "default"; pinctrl-0 = <&max77620_default>; + fps { + fps0 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; + maxim,suspend-fps-time-period-us = <5120>; + }; + + fps1 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; + maxim,suspend-fps-time-period-us = <5120>; + }; + + fps2 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; + }; + }; + max77620_default: pinmux { gpio0 { pins = "gpio0"; @@ -231,22 +247,6 @@ }; }; - fps { - fps0 { - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; - maxim,suspend-fps-time-period-us = <5120>; - }; - - fps1 { - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; - maxim,suspend-fps-time-period-us = <5120>; - }; - - fps2 { - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; - }; - }; - regulators { in-ldo0-1-supply = <&vdd_pre>; in-ldo2-supply = <&vdd_3v3_sys>; @@ -611,14 +611,6 @@ aconnect@702c0000 { status = "okay"; - dma-controller@702e2000 { - status = "okay"; - }; - - interrupt-controller@702f9000 { - status = "okay"; - }; - ahub@702d0800 { status = "okay"; @@ -678,56 +670,6 @@ }; }; - dmic@702d4000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dmic1_cif_ep: endpoint { - remote-endpoint = <&xbar_dmic1_ep>; - }; - }; - - dmic1_port: port@1 { - reg = <1>; - - dmic1_dap_ep: endpoint { - /* Placeholder for external Codec */ - }; - }; - }; - }; - - dmic@702d4100 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dmic2_cif_ep: endpoint { - remote-endpoint = <&xbar_dmic2_ep>; - }; - }; - - dmic2_port: port@1 { - reg = <1>; - - dmic2_dap_ep: endpoint { - /* Placeholder for external Codec */ - }; - }; - }; - }; - sfc@702d2000 { status = "okay"; @@ -828,56 +770,6 @@ }; }; - mvc@702da000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - mvc1_cif_in_ep: endpoint { - remote-endpoint = <&xbar_mvc1_in_ep>; - }; - }; - - mvc1_out_port: port@1 { - reg = <1>; - - mvc1_cif_out_ep: endpoint { - remote-endpoint = <&xbar_mvc1_out_ep>; - }; - }; - }; - }; - - mvc@702da200 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - mvc2_cif_in_ep: endpoint { - remote-endpoint = <&xbar_mvc2_in_ep>; - }; - }; - - mvc2_out_port: port@1 { - reg = <1>; - - mvc2_cif_out_ep: endpoint { - remote-endpoint = <&xbar_mvc2_out_ep>; - }; - }; - }; - }; - amx@702d3000 { status = "okay"; @@ -1074,6 +966,56 @@ }; }; + dmic@702d4000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dmic1_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic1_ep>; + }; + }; + + dmic1_port: port@1 { + reg = <1>; + + dmic1_dap_ep: endpoint { + /* Placeholder for external Codec */ + }; + }; + }; + }; + + dmic@702d4100 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dmic2_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic2_ep>; + }; + }; + + dmic2_port: port@1 { + reg = <1>; + + dmic2_dap_ep: endpoint { + /* Placeholder for external Codec */ + }; + }; + }; + }; + processing-engine@702d8000 { status = "okay"; @@ -1124,6 +1066,56 @@ }; }; + mvc@702da000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mvc1_cif_in_ep: endpoint { + remote-endpoint = <&xbar_mvc1_in_ep>; + }; + }; + + mvc1_out_port: port@1 { + reg = <1>; + + mvc1_cif_out_ep: endpoint { + remote-endpoint = <&xbar_mvc1_out_ep>; + }; + }; + }; + }; + + mvc@702da200 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mvc2_cif_in_ep: endpoint { + remote-endpoint = <&xbar_mvc2_in_ep>; + }; + }; + + mvc2_out_port: port@1 { + reg = <1>; + + mvc2_cif_out_ep: endpoint { + remote-endpoint = <&xbar_mvc2_out_ep>; + }; + }; + }; + }; + amixer@702dbb00 { status = "okay"; @@ -1695,6 +1687,14 @@ }; }; }; + + dma-controller@702e2000 { + status = "okay"; + }; + + interrupt-controller@702f9000 { + status = "okay"; + }; }; spi@70410000 { @@ -1739,69 +1739,17 @@ }; }; - fan: pwm-fan { - compatible = "pwm-fan"; - pwms = <&pwm 3 45334>; - - cooling-levels = <0 64 128 255>; - #cooling-cells = <2>; - }; - - thermal-zones { - cpu-thermal { - trips { - cpu_trip_critical: critical { - temperature = <96500>; - hysteresis = <0>; - type = "critical"; - }; - - cpu_trip_hot: hot { - temperature = <70000>; - hysteresis = <2000>; - type = "hot"; - }; - - cpu_trip_active: active { - temperature = <50000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_trip_passive: passive { - temperature = <30000>; - hysteresis = <2000>; - type = "passive"; - }; - }; - - cooling-maps { - cpu-critical { - cooling-device = <&fan 3 3>; - trip = <&cpu_trip_critical>; - }; - - cpu-hot { - cooling-device = <&fan 2 2>; - trip = <&cpu_trip_hot>; - }; - - cpu-active { - cooling-device = <&fan 1 1>; - trip = <&cpu_trip_active>; - }; - - cpu-passive { - cooling-device = <&fan 0 0>; - trip = <&cpu_trip_passive>; - }; - }; - }; - }; - gpio-keys { compatible = "gpio-keys"; + key-force-recovery { + label = "Force Recovery"; + gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>; + linux,input-type = <EV_KEY>; + linux,code = <BTN_1>; + debounce-interval = <30>; + }; + key-power { label = "Power"; gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_LOW>; @@ -1811,14 +1759,6 @@ wakeup-event-action = <EV_ACT_ASSERTED>; wakeup-source; }; - - key-force-recovery { - label = "Force Recovery"; - gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>; - linux,input-type = <EV_KEY>; - linux,code = <BTN_1>; - debounce-interval = <30>; - }; }; psci { @@ -1826,6 +1766,14 @@ method = "smc"; }; + fan: pwm-fan { + compatible = "pwm-fan"; + pwms = <&pwm 3 45334>; + + cooling-levels = <0 64 128 255>; + #cooling-cells = <2>; + }; + vdd_5v0_sys: regulator-vdd-5v0-sys { compatible = "regulator-fixed"; @@ -1986,4 +1934,56 @@ label = "NVIDIA Jetson Nano APE"; }; + + thermal-zones { + cpu-thermal { + trips { + cpu_trip_critical: critical { + temperature = <96500>; + hysteresis = <0>; + type = "critical"; + }; + + cpu_trip_hot: hot { + temperature = <70000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpu_trip_active: active { + temperature = <50000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_trip_passive: passive { + temperature = <30000>; + hysteresis = <2000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu-critical { + cooling-device = <&fan 3 3>; + trip = <&cpu_trip_critical>; + }; + + cpu-hot { + cooling-device = <&fan 2 2>; + trip = <&cpu_trip_hot>; + }; + + cpu-active { + cooling-device = <&fan 1 1>; + trip = <&cpu_trip_active>; + }; + + cpu-passive { + cooling-device = <&fan 0 0>; + trip = <&cpu_trip_passive>; + }; + }; + }; + }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts index 7c569695b705..d7d7c63e62e2 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts @@ -1389,6 +1389,23 @@ pinctrl-names = "default"; pinctrl-0 = <&max77620_default>; + fps { + fps0 { + maxim,shutdown-fps-time-period-us = <5120>; + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; + }; + + fps1 { + maxim,shutdown-fps-time-period-us = <5120>; + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; + maxim,device-state-on-disabled-event = <MAX77620_FPS_INACTIVE_STATE_SLEEP>; + }; + + fps2 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; + }; + }; + max77620_default: pinmux { gpio0_1_2_7 { pins = "gpio0", "gpio1", "gpio2", "gpio7"; @@ -1409,32 +1426,15 @@ maxim,active-fps-power-down-slot = <2>; }; - gpio5_6 { - pins = "gpio5", "gpio6"; - function = "gpio"; - drive-push-pull = <1>; - }; - gpio4 { pins = "gpio4"; function = "32k-out1"; }; - }; - - fps { - fps0 { - maxim,shutdown-fps-time-period-us = <5120>; - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; - }; - - fps1 { - maxim,shutdown-fps-time-period-us = <5120>; - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; - maxim,device-state-on-disabled-event = <MAX77620_FPS_INACTIVE_STATE_SLEEP>; - }; - fps2 { - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; + gpio5_6 { + pins = "gpio5", "gpio6"; + function = "gpio"; + drive-push-pull = <1>; }; }; @@ -1800,6 +1800,18 @@ wakeup-source; }; + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEDOWN>; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(M, 4) GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + }; + switch-lid { label = "Lid"; gpios = <&gpio TEGRA_GPIO(B, 4) GPIO_ACTIVE_LOW>; @@ -1815,18 +1827,6 @@ linux,code = <SW_TABLET_MODE>; wakeup-source; }; - - key-volume-down { - label = "Volume Down"; - gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; - linux,code = <KEY_VOLUMEDOWN>; - }; - - key-volume-up { - label = "Volume Up"; - gpios = <&gpio TEGRA_GPIO(M, 4) GPIO_ACTIVE_LOW>; - linux,code = <KEY_VOLUMEUP>; - }; }; max98357a { diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index bc0cacb20d7a..980565bf02c9 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -555,19 +555,19 @@ reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */ <0x0 0x70003000 0x0 0x294>; /* Mux registers */ - sdmmc1_3v3_drv: pinmux-sdmmc1-3v3-drv { + sdmmc1_1v8_drv: pinmux-sdmmc1-1v8-drv { sdmmc1 { nvidia,pins = "drive_sdmmc1"; - nvidia,pull-down-strength = <0x8>; - nvidia,pull-up-strength = <0x8>; + nvidia,pull-down-strength = <0x4>; + nvidia,pull-up-strength = <0x3>; }; }; - sdmmc1_1v8_drv: pinmux-sdmmc1-1v8-drv { + sdmmc1_3v3_drv: pinmux-sdmmc1-3v3-drv { sdmmc1 { nvidia,pins = "drive_sdmmc1"; - nvidia,pull-down-strength = <0x4>; - nvidia,pull-up-strength = <0x3>; + nvidia,pull-down-strength = <0x8>; + nvidia,pull-up-strength = <0x8>; }; }; @@ -579,19 +579,19 @@ }; }; - sdmmc3_3v3_drv: pinmux-sdmmc3-3v3-drv { + sdmmc3_1v8_drv: pinmux-sdmmc3-1v8-drv { sdmmc3 { nvidia,pins = "drive_sdmmc3"; - nvidia,pull-down-strength = <0x8>; - nvidia,pull-up-strength = <0x8>; + nvidia,pull-down-strength = <0x4>; + nvidia,pull-up-strength = <0x3>; }; }; - sdmmc3_1v8_drv: pinmux-sdmmc3-1v8-drv { + sdmmc3_3v3_drv: pinmux-sdmmc3-3v3-drv { sdmmc3 { nvidia,pins = "drive_sdmmc3"; - nvidia,pull-down-strength = <0x4>; - nvidia,pull-up-strength = <0x3>; + nvidia,pull-down-strength = <0x8>; + nvidia,pull-up-strength = <0x8>; }; }; @@ -852,6 +852,38 @@ #interrupt-cells = <2>; interrupt-controller; + pinmux { + pex_dpd_disable: pex-dpd-disable { + pins = "pex-bias", "pex-clk1", "pex-clk2"; + low-power-disable; + }; + + pex_dpd_enable: pex-dpd-enable { + pins = "pex-bias", "pex-clk1", "pex-clk2"; + low-power-enable; + }; + + sdmmc1_1v8: sdmmc1-1v8 { + pins = "sdmmc1"; + power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; + }; + + sdmmc1_3v3: sdmmc1-3v3 { + pins = "sdmmc1"; + power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; + }; + + sdmmc3_1v8: sdmmc3-1v8 { + pins = "sdmmc3"; + power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; + }; + + sdmmc3_3v3: sdmmc3-3v3 { + pins = "sdmmc3"; + power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; + }; + }; + powergates { pd_audio: aud { clocks = <&tegra_car TEGRA210_CLK_APE>, @@ -881,21 +913,12 @@ #power-domain-cells = <0>; }; - pd_xusbss: xusba { - clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; - resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; - #power-domain-cells = <0>; - }; - - pd_xusbdev: xusbb { - clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>; - resets = <&tegra_car 95>; - #power-domain-cells = <0>; - }; - - pd_xusbhost: xusbc { - clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>; - resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>; + pd_venc: venc { + clocks = <&tegra_car TEGRA210_CLK_VI>, + <&tegra_car TEGRA210_CLK_CSI>; + resets = <&mc TEGRA210_MC_RESET_VI>, + <&tegra_car 20>, + <&tegra_car 52>; #power-domain-cells = <0>; }; @@ -907,45 +930,22 @@ #power-domain-cells = <0>; }; - pd_venc: venc { - clocks = <&tegra_car TEGRA210_CLK_VI>, - <&tegra_car TEGRA210_CLK_CSI>; - resets = <&mc TEGRA210_MC_RESET_VI>, - <&tegra_car 20>, - <&tegra_car 52>; + pd_xusbss: xusba { + clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; + resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; #power-domain-cells = <0>; }; - }; - - pinmux { - sdmmc1_3v3: sdmmc1-3v3 { - pins = "sdmmc1"; - power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; - }; - - sdmmc1_1v8: sdmmc1-1v8 { - pins = "sdmmc1"; - power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; - }; - sdmmc3_3v3: sdmmc3-3v3 { - pins = "sdmmc3"; - power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; - }; - - sdmmc3_1v8: sdmmc3-1v8 { - pins = "sdmmc3"; - power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; - }; - - pex_dpd_disable: pex-dpd-disable { - pins = "pex-bias", "pex-clk1", "pex-clk2"; - low-power-disable; + pd_xusbdev: xusbb { + clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>; + resets = <&tegra_car 95>; + #power-domain-cells = <0>; }; - pex_dpd_enable: pex-dpd-enable { - pins = "pex-bias", "pex-clk1", "pex-clk2"; - low-power-enable; + pd_xusbhost: xusbc { + clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>; + resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>; + #power-domain-cells = <0>; }; }; }; @@ -1388,50 +1388,6 @@ ranges = <0x702c0000 0x0 0x702c0000 0x00040000>; status = "disabled"; - adma: dma-controller@702e2000 { - compatible = "nvidia,tegra210-adma"; - reg = <0x702e2000 0x2000>; - interrupt-parent = <&agic>; - interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; - clock-names = "d_audio"; - status = "disabled"; - }; - - agic: interrupt-controller@702f9000 { - compatible = "nvidia,tegra210-agic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x702f9000 0x1000>, - <0x702fa000 0x2000>; - interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; - clocks = <&tegra_car TEGRA210_CLK_APE>; - clock-names = "clk"; - status = "disabled"; - }; - tegra_ahub: ahub@702d0800 { compatible = "nvidia,tegra210-ahub"; reg = <0x702d0800 0x800>; @@ -1620,42 +1576,6 @@ status = "disabled"; }; - tegra_dmic1: dmic@702d4000 { - compatible = "nvidia,tegra210-dmic"; - reg = <0x702d4000 0x100>; - clocks = <&tegra_car TEGRA210_CLK_DMIC1>; - clock-names = "dmic"; - assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC1>; - assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; - assigned-clock-rates = <3072000>; - sound-name-prefix = "DMIC1"; - status = "disabled"; - }; - - tegra_dmic2: dmic@702d4100 { - compatible = "nvidia,tegra210-dmic"; - reg = <0x702d4100 0x100>; - clocks = <&tegra_car TEGRA210_CLK_DMIC2>; - clock-names = "dmic"; - assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC2>; - assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; - assigned-clock-rates = <3072000>; - sound-name-prefix = "DMIC2"; - status = "disabled"; - }; - - tegra_dmic3: dmic@702d4200 { - compatible = "nvidia,tegra210-dmic"; - reg = <0x702d4200 0x100>; - clocks = <&tegra_car TEGRA210_CLK_DMIC3>; - clock-names = "dmic"; - assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC3>; - assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; - assigned-clock-rates = <3072000>; - sound-name-prefix = "DMIC3"; - status = "disabled"; - }; - tegra_sfc1: sfc@702d2000 { compatible = "nvidia,tegra210-sfc"; reg = <0x702d2000 0x200>; @@ -1684,20 +1604,6 @@ status = "disabled"; }; - tegra_mvc1: mvc@702da000 { - compatible = "nvidia,tegra210-mvc"; - reg = <0x702da000 0x200>; - sound-name-prefix = "MVC1"; - status = "disabled"; - }; - - tegra_mvc2: mvc@702da200 { - compatible = "nvidia,tegra210-mvc"; - reg = <0x702da200 0x200>; - sound-name-prefix = "MVC2"; - status = "disabled"; - }; - tegra_amx1: amx@702d3000 { compatible = "nvidia,tegra210-amx"; reg = <0x702d3000 0x100>; @@ -1726,6 +1632,42 @@ status = "disabled"; }; + tegra_dmic1: dmic@702d4000 { + compatible = "nvidia,tegra210-dmic"; + reg = <0x702d4000 0x100>; + clocks = <&tegra_car TEGRA210_CLK_DMIC1>; + clock-names = "dmic"; + assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC1>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC1"; + status = "disabled"; + }; + + tegra_dmic2: dmic@702d4100 { + compatible = "nvidia,tegra210-dmic"; + reg = <0x702d4100 0x100>; + clocks = <&tegra_car TEGRA210_CLK_DMIC2>; + clock-names = "dmic"; + assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC2>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC2"; + status = "disabled"; + }; + + tegra_dmic3: dmic@702d4200 { + compatible = "nvidia,tegra210-dmic"; + reg = <0x702d4200 0x100>; + clocks = <&tegra_car TEGRA210_CLK_DMIC3>; + clock-names = "dmic"; + assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC3>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC3"; + status = "disabled"; + }; + tegra_ope1: processing-engine@702d8000 { compatible = "nvidia,tegra210-ope"; reg = <0x702d8000 0x100>; @@ -1766,6 +1708,20 @@ }; }; + tegra_mvc1: mvc@702da000 { + compatible = "nvidia,tegra210-mvc"; + reg = <0x702da000 0x200>; + sound-name-prefix = "MVC1"; + status = "disabled"; + }; + + tegra_mvc2: mvc@702da200 { + compatible = "nvidia,tegra210-mvc"; + reg = <0x702da200 0x200>; + sound-name-prefix = "MVC2"; + status = "disabled"; + }; + tegra_amixer: amixer@702dbb00 { compatible = "nvidia,tegra210-amixer"; reg = <0x702dbb00 0x800>; @@ -1856,6 +1812,50 @@ }; }; }; + + adma: dma-controller@702e2000 { + compatible = "nvidia,tegra210-adma"; + reg = <0x702e2000 0x2000>; + interrupt-parent = <&agic>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; + clock-names = "d_audio"; + status = "disabled"; + }; + + agic: interrupt-controller@702f9000 { + compatible = "nvidia,tegra210-agic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x702f9000 0x1000>, + <0x702fa000 0x2000>; + interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&tegra_car TEGRA210_CLK_APE>; + clock-names = "clk"; + status = "disabled"; + }; }; spi@70410000 { diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi index 8b86ea9cb50c..2378da324273 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi @@ -6,42 +6,23 @@ model = "NVIDIA Jetson AGX Orin"; compatible = "nvidia,p3701-0000", "nvidia,tegra234"; - vdd_1v8_ls: regulator-vdd-1v8-ls { - compatible = "regulator-fixed"; - regulator-name = "VDD_1V8_LS"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vdd_1v8_ao: regulator-vdd-1v8-ao { - compatible = "regulator-fixed"; - regulator-name = "VDD_1V8_AO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; + bus@0 { + i2c@3160000 { + status = "okay"; - vdd_3v3_pcie: regulator-vdd-3v3-pcie { - compatible = "regulator-fixed"; - regulator-name = "VDD_3V3_PCIE"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio TEGRA234_MAIN_GPIO(Z, 2) GPIO_ACTIVE_HIGH>; - regulator-boot-on; - enable-active-high; - }; + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; - vdd_12v_pcie: regulator-vdd-12v-pcie { - compatible = "regulator-fixed"; - regulator-name = "VDD_12V_PCIE"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - gpio = <&gpio TEGRA234_MAIN_GPIO(A, 1) GPIO_ACTIVE_LOW>; - regulator-boot-on; - }; + label = "module"; + vcc-supply = <&vdd_1v8_hs>; + address-width = <8>; + pagesize = <8>; + size = <256>; + read-only; + }; + }; - bus@0 { spi@3270000 { status = "okay"; @@ -67,6 +48,29 @@ non-removable; }; + padctl@3520000 { + vclamp-usb-supply = <&vdd_1v8_ao>; + avdd-usb-supply = <&vdd_3v3_ao>; + + ports { + usb2-0 { + vbus-supply = <&vdd_5v0_sys>; + }; + + usb2-1 { + vbus-supply = <&vdd_5v0_sys>; + }; + + usb2-2 { + vbus-supply = <&vdd_5v0_sys>; + }; + + usb2-3 { + vbus-supply = <&vdd_5v0_sys>; + }; + }; + }; + rtc@c2a0000 { status = "okay"; }; @@ -75,4 +79,64 @@ nvidia,invert-interrupt; }; }; + + vdd_5v0_sys: regulator-vdd-5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "VIN_SYS_5V0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_1v8_ls: regulator-vdd-1v8-ls { + compatible = "regulator-fixed"; + regulator-name = "VDD_1V8_LS"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vdd_1v8_hs: regulator-vdd-1v8-hs { + compatible = "regulator-fixed"; + regulator-name = "VDD_1V8_HS"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vdd_1v8_ao: regulator-vdd-1v8-ao { + compatible = "regulator-fixed"; + regulator-name = "VDD_1V8_AO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vdd_3v3_ao: regulator-vdd-3v3-ao { + compatible = "regulator-fixed"; + regulator-name = "VDD_3V3_AO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_3v3_pcie: regulator-vdd-3v3-pcie { + compatible = "regulator-fixed"; + regulator-name = "VDD_3V3_PCIE"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio TEGRA234_MAIN_GPIO(Z, 2) GPIO_ACTIVE_HIGH>; + regulator-boot-on; + enable-active-high; + }; + + vdd_12v_pcie: regulator-vdd-12v-pcie { + compatible = "regulator-fixed"; + regulator-name = "VDD_12V_PCIE"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&gpio TEGRA234_MAIN_GPIO(A, 1) GPIO_ACTIVE_LOW>; + regulator-boot-on; + }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts index 96aa2267b06d..8a9747855d6b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts @@ -17,6 +17,11 @@ serial1 = &uarta; }; + chosen { + bootargs = "console=ttyTCU0,115200n8"; + stdout-path = "serial0:115200n8"; + }; + bus@0 { aconnect@2900000 { status = "okay"; @@ -24,867 +29,6 @@ ahub@2900800 { status = "okay"; - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0x0>; - - xbar_admaif0: endpoint { - remote-endpoint = <&admaif0>; - }; - }; - - port@1 { - reg = <0x1>; - - xbar_admaif1: endpoint { - remote-endpoint = <&admaif1>; - }; - }; - - port@2 { - reg = <0x2>; - - xbar_admaif2: endpoint { - remote-endpoint = <&admaif2>; - }; - }; - - port@3 { - reg = <0x3>; - - xbar_admaif3: endpoint { - remote-endpoint = <&admaif3>; - }; - }; - - port@4 { - reg = <0x4>; - - xbar_admaif4: endpoint { - remote-endpoint = <&admaif4>; - }; - }; - - port@5 { - reg = <0x5>; - - xbar_admaif5: endpoint { - remote-endpoint = <&admaif5>; - }; - }; - - port@6 { - reg = <0x6>; - - xbar_admaif6: endpoint { - remote-endpoint = <&admaif6>; - }; - }; - - port@7 { - reg = <0x7>; - - xbar_admaif7: endpoint { - remote-endpoint = <&admaif7>; - }; - }; - - port@8 { - reg = <0x8>; - - xbar_admaif8: endpoint { - remote-endpoint = <&admaif8>; - }; - }; - - port@9 { - reg = <0x9>; - - xbar_admaif9: endpoint { - remote-endpoint = <&admaif9>; - }; - }; - - port@a { - reg = <0xa>; - - xbar_admaif10: endpoint { - remote-endpoint = <&admaif10>; - }; - }; - - port@b { - reg = <0xb>; - - xbar_admaif11: endpoint { - remote-endpoint = <&admaif11>; - }; - }; - - port@c { - reg = <0xc>; - - xbar_admaif12: endpoint { - remote-endpoint = <&admaif12>; - }; - }; - - port@d { - reg = <0xd>; - - xbar_admaif13: endpoint { - remote-endpoint = <&admaif13>; - }; - }; - - port@e { - reg = <0xe>; - - xbar_admaif14: endpoint { - remote-endpoint = <&admaif14>; - }; - }; - - port@f { - reg = <0xf>; - - xbar_admaif15: endpoint { - remote-endpoint = <&admaif15>; - }; - }; - - port@10 { - reg = <0x10>; - - xbar_admaif16: endpoint { - remote-endpoint = <&admaif16>; - }; - }; - - port@11 { - reg = <0x11>; - - xbar_admaif17: endpoint { - remote-endpoint = <&admaif17>; - }; - }; - - port@12 { - reg = <0x12>; - - xbar_admaif18: endpoint { - remote-endpoint = <&admaif18>; - }; - }; - - port@13 { - reg = <0x13>; - - xbar_admaif19: endpoint { - remote-endpoint = <&admaif19>; - }; - }; - - xbar_i2s1_port: port@14 { - reg = <0x14>; - - xbar_i2s1: endpoint { - remote-endpoint = <&i2s1_cif>; - }; - }; - - xbar_i2s2_port: port@15 { - reg = <0x15>; - - xbar_i2s2: endpoint { - remote-endpoint = <&i2s2_cif>; - }; - }; - - xbar_i2s4_port: port@17 { - reg = <0x17>; - - xbar_i2s4: endpoint { - remote-endpoint = <&i2s4_cif>; - }; - }; - - xbar_i2s6_port: port@19 { - reg = <0x19>; - - xbar_i2s6: endpoint { - remote-endpoint = <&i2s6_cif>; - }; - }; - - xbar_dmic3_port: port@1c { - reg = <0x1c>; - - xbar_dmic3: endpoint { - remote-endpoint = <&dmic3_cif>; - }; - }; - - xbar_sfc1_in_port: port@20 { - reg = <0x20>; - - xbar_sfc1_in: endpoint { - remote-endpoint = <&sfc1_cif_in>; - }; - }; - - port@21 { - reg = <0x21>; - - xbar_sfc1_out: endpoint { - remote-endpoint = <&sfc1_cif_out>; - }; - }; - - xbar_sfc2_in_port: port@22 { - reg = <0x22>; - - xbar_sfc2_in: endpoint { - remote-endpoint = <&sfc2_cif_in>; - }; - }; - - port@23 { - reg = <0x23>; - - xbar_sfc2_out: endpoint { - remote-endpoint = <&sfc2_cif_out>; - }; - }; - - xbar_sfc3_in_port: port@24 { - reg = <0x24>; - - xbar_sfc3_in: endpoint { - remote-endpoint = <&sfc3_cif_in>; - }; - }; - - port@25 { - reg = <0x25>; - - xbar_sfc3_out: endpoint { - remote-endpoint = <&sfc3_cif_out>; - }; - }; - - xbar_sfc4_in_port: port@26 { - reg = <0x26>; - - xbar_sfc4_in: endpoint { - remote-endpoint = <&sfc4_cif_in>; - }; - }; - - port@27 { - reg = <0x27>; - - xbar_sfc4_out: endpoint { - remote-endpoint = <&sfc4_cif_out>; - }; - }; - - xbar_mvc1_in_port: port@28 { - reg = <0x28>; - - xbar_mvc1_in: endpoint { - remote-endpoint = <&mvc1_cif_in>; - }; - }; - - port@29 { - reg = <0x29>; - - xbar_mvc1_out: endpoint { - remote-endpoint = <&mvc1_cif_out>; - }; - }; - - xbar_mvc2_in_port: port@2a { - reg = <0x2a>; - - xbar_mvc2_in: endpoint { - remote-endpoint = <&mvc2_cif_in>; - }; - }; - - port@2b { - reg = <0x2b>; - - xbar_mvc2_out: endpoint { - remote-endpoint = <&mvc2_cif_out>; - }; - }; - - xbar_amx1_in1_port: port@2c { - reg = <0x2c>; - - xbar_amx1_in1: endpoint { - remote-endpoint = <&amx1_in1>; - }; - }; - - xbar_amx1_in2_port: port@2d { - reg = <0x2d>; - - xbar_amx1_in2: endpoint { - remote-endpoint = <&amx1_in2>; - }; - }; - - xbar_amx1_in3_port: port@2e { - reg = <0x2e>; - - xbar_amx1_in3: endpoint { - remote-endpoint = <&amx1_in3>; - }; - }; - - xbar_amx1_in4_port: port@2f { - reg = <0x2f>; - - xbar_amx1_in4: endpoint { - remote-endpoint = <&amx1_in4>; - }; - }; - - port@30 { - reg = <0x30>; - - xbar_amx1_out: endpoint { - remote-endpoint = <&amx1_out>; - }; - }; - - xbar_amx2_in1_port: port@31 { - reg = <0x31>; - - xbar_amx2_in1: endpoint { - remote-endpoint = <&amx2_in1>; - }; - }; - - xbar_amx2_in2_port: port@32 { - reg = <0x32>; - - xbar_amx2_in2: endpoint { - remote-endpoint = <&amx2_in2>; - }; - }; - - xbar_amx2_in3_port: port@33 { - reg = <0x33>; - - xbar_amx2_in3: endpoint { - remote-endpoint = <&amx2_in3>; - }; - }; - - xbar_amx2_in4_port: port@34 { - reg = <0x34>; - - xbar_amx2_in4: endpoint { - remote-endpoint = <&amx2_in4>; - }; - }; - - port@35 { - reg = <0x35>; - - xbar_amx2_out: endpoint { - remote-endpoint = <&amx2_out>; - }; - }; - - xbar_amx3_in1_port: port@36 { - reg = <0x36>; - - xbar_amx3_in1: endpoint { - remote-endpoint = <&amx3_in1>; - }; - }; - - xbar_amx3_in2_port: port@37 { - reg = <0x37>; - - xbar_amx3_in2: endpoint { - remote-endpoint = <&amx3_in2>; - }; - }; - - xbar_amx3_in3_port: port@38 { - reg = <0x38>; - - xbar_amx3_in3: endpoint { - remote-endpoint = <&amx3_in3>; - }; - }; - - xbar_amx3_in4_port: port@39 { - reg = <0x39>; - - xbar_amx3_in4: endpoint { - remote-endpoint = <&amx3_in4>; - }; - }; - - port@3a { - reg = <0x3a>; - - xbar_amx3_out: endpoint { - remote-endpoint = <&amx3_out>; - }; - }; - - xbar_amx4_in1_port: port@3b { - reg = <0x3b>; - - xbar_amx4_in1: endpoint { - remote-endpoint = <&amx4_in1>; - }; - }; - - xbar_amx4_in2_port: port@3c { - reg = <0x3c>; - - xbar_amx4_in2: endpoint { - remote-endpoint = <&amx4_in2>; - }; - }; - - xbar_amx4_in3_port: port@3d { - reg = <0x3d>; - - xbar_amx4_in3: endpoint { - remote-endpoint = <&amx4_in3>; - }; - }; - - xbar_amx4_in4_port: port@3e { - reg = <0x3e>; - - xbar_amx4_in4: endpoint { - remote-endpoint = <&amx4_in4>; - }; - }; - - port@3f { - reg = <0x3f>; - - xbar_amx4_out: endpoint { - remote-endpoint = <&amx4_out>; - }; - }; - - xbar_adx1_in_port: port@40 { - reg = <0x40>; - - xbar_adx1_in: endpoint { - remote-endpoint = <&adx1_in>; - }; - }; - - port@41 { - reg = <0x41>; - - xbar_adx1_out1: endpoint { - remote-endpoint = <&adx1_out1>; - }; - }; - - port@42 { - reg = <0x42>; - - xbar_adx1_out2: endpoint { - remote-endpoint = <&adx1_out2>; - }; - }; - - port@43 { - reg = <0x43>; - - xbar_adx1_out3: endpoint { - remote-endpoint = <&adx1_out3>; - }; - }; - - port@44 { - reg = <0x44>; - - xbar_adx1_out4: endpoint { - remote-endpoint = <&adx1_out4>; - }; - }; - - xbar_adx2_in_port: port@45 { - reg = <0x45>; - - xbar_adx2_in: endpoint { - remote-endpoint = <&adx2_in>; - }; - }; - - port@46 { - reg = <0x46>; - - xbar_adx2_out1: endpoint { - remote-endpoint = <&adx2_out1>; - }; - }; - - port@47 { - reg = <0x47>; - - xbar_adx2_out2: endpoint { - remote-endpoint = <&adx2_out2>; - }; - }; - - port@48 { - reg = <0x48>; - - xbar_adx2_out3: endpoint { - remote-endpoint = <&adx2_out3>; - }; - }; - - port@49 { - reg = <0x49>; - - xbar_adx2_out4: endpoint { - remote-endpoint = <&adx2_out4>; - }; - }; - - xbar_adx3_in_port: port@4a { - reg = <0x4a>; - - xbar_adx3_in: endpoint { - remote-endpoint = <&adx3_in>; - }; - }; - - port@4b { - reg = <0x4b>; - - xbar_adx3_out1: endpoint { - remote-endpoint = <&adx3_out1>; - }; - }; - - port@4c { - reg = <0x4c>; - - xbar_adx3_out2: endpoint { - remote-endpoint = <&adx3_out2>; - }; - }; - - port@4d { - reg = <0x4d>; - - xbar_adx3_out3: endpoint { - remote-endpoint = <&adx3_out3>; - }; - }; - - port@4e { - reg = <0x4e>; - - xbar_adx3_out4: endpoint { - remote-endpoint = <&adx3_out4>; - }; - }; - - xbar_adx4_in_port: port@4f { - reg = <0x4f>; - - xbar_adx4_in: endpoint { - remote-endpoint = <&adx4_in>; - }; - }; - - port@50 { - reg = <0x50>; - - xbar_adx4_out1: endpoint { - remote-endpoint = <&adx4_out1>; - }; - }; - - port@51 { - reg = <0x51>; - - xbar_adx4_out2: endpoint { - remote-endpoint = <&adx4_out2>; - }; - }; - - port@52 { - reg = <0x52>; - - xbar_adx4_out3: endpoint { - remote-endpoint = <&adx4_out3>; - }; - }; - - port@53 { - reg = <0x53>; - - xbar_adx4_out4: endpoint { - remote-endpoint = <&adx4_out4>; - }; - }; - - xbar_mix_in1_port: port@54 { - reg = <0x54>; - - xbar_mix_in1: endpoint { - remote-endpoint = <&mix_in1>; - }; - }; - - xbar_mix_in2_port: port@55 { - reg = <0x55>; - - xbar_mix_in2: endpoint { - remote-endpoint = <&mix_in2>; - }; - }; - - xbar_mix_in3_port: port@56 { - reg = <0x56>; - - xbar_mix_in3: endpoint { - remote-endpoint = <&mix_in3>; - }; - }; - - xbar_mix_in4_port: port@57 { - reg = <0x57>; - - xbar_mix_in4: endpoint { - remote-endpoint = <&mix_in4>; - }; - }; - - xbar_mix_in5_port: port@58 { - reg = <0x58>; - - xbar_mix_in5: endpoint { - remote-endpoint = <&mix_in5>; - }; - }; - - xbar_mix_in6_port: port@59 { - reg = <0x59>; - - xbar_mix_in6: endpoint { - remote-endpoint = <&mix_in6>; - }; - }; - - xbar_mix_in7_port: port@5a { - reg = <0x5a>; - - xbar_mix_in7: endpoint { - remote-endpoint = <&mix_in7>; - }; - }; - - xbar_mix_in8_port: port@5b { - reg = <0x5b>; - - xbar_mix_in8: endpoint { - remote-endpoint = <&mix_in8>; - }; - }; - - xbar_mix_in9_port: port@5c { - reg = <0x5c>; - - xbar_mix_in9: endpoint { - remote-endpoint = <&mix_in9>; - }; - }; - - xbar_mix_in10_port: port@5d { - reg = <0x5d>; - - xbar_mix_in10: endpoint { - remote-endpoint = <&mix_in10>; - }; - }; - - port@5e { - reg = <0x5e>; - - xbar_mix_out1: endpoint { - remote-endpoint = <&mix_out1>; - }; - }; - - port@5f { - reg = <0x5f>; - - xbar_mix_out2: endpoint { - remote-endpoint = <&mix_out2>; - }; - }; - - port@60 { - reg = <0x60>; - - xbar_mix_out3: endpoint { - remote-endpoint = <&mix_out3>; - }; - }; - - port@61 { - reg = <0x61>; - - xbar_mix_out4: endpoint { - remote-endpoint = <&mix_out4>; - }; - }; - - port@62 { - reg = <0x62>; - - xbar_mix_out5: endpoint { - remote-endpoint = <&mix_out5>; - }; - }; - - xbar_asrc_in1_port: port@63 { - reg = <0x63>; - - xbar_asrc_in1_ep: endpoint { - remote-endpoint = <&asrc_in1_ep>; - }; - }; - - port@64 { - reg = <0x64>; - - xbar_asrc_out1_ep: endpoint { - remote-endpoint = <&asrc_out1_ep>; - }; - }; - - xbar_asrc_in2_port: port@65 { - reg = <0x65>; - - xbar_asrc_in2_ep: endpoint { - remote-endpoint = <&asrc_in2_ep>; - }; - }; - - port@66 { - reg = <0x66>; - - xbar_asrc_out2_ep: endpoint { - remote-endpoint = <&asrc_out2_ep>; - }; - }; - - xbar_asrc_in3_port: port@67 { - reg = <0x67>; - - xbar_asrc_in3_ep: endpoint { - remote-endpoint = <&asrc_in3_ep>; - }; - }; - - port@68 { - reg = <0x68>; - - xbar_asrc_out3_ep: endpoint { - remote-endpoint = <&asrc_out3_ep>; - }; - }; - - xbar_asrc_in4_port: port@69 { - reg = <0x69>; - - xbar_asrc_in4_ep: endpoint { - remote-endpoint = <&asrc_in4_ep>; - }; - }; - - port@6a { - reg = <0x6a>; - - xbar_asrc_out4_ep: endpoint { - remote-endpoint = <&asrc_out4_ep>; - }; - }; - - xbar_asrc_in5_port: port@6b { - reg = <0x6b>; - - xbar_asrc_in5_ep: endpoint { - remote-endpoint = <&asrc_in5_ep>; - }; - }; - - port@6c { - reg = <0x6c>; - - xbar_asrc_out5_ep: endpoint { - remote-endpoint = <&asrc_out5_ep>; - }; - }; - - xbar_asrc_in6_port: port@6d { - reg = <0x6d>; - - xbar_asrc_in6_ep: endpoint { - remote-endpoint = <&asrc_in6_ep>; - }; - }; - - port@6e { - reg = <0x6e>; - - xbar_asrc_out6_ep: endpoint { - remote-endpoint = <&asrc_out6_ep>; - }; - }; - - xbar_asrc_in7_port: port@6f { - reg = <0x6f>; - - xbar_asrc_in7_ep: endpoint { - remote-endpoint = <&asrc_in7_ep>; - }; - }; - - xbar_ope1_in_port: port@70 { - reg = <0x70>; - - xbar_ope1_in_ep: endpoint { - remote-endpoint = <&ope1_cif_in_ep>; - }; - }; - - port@71 { - reg = <0x71>; - - xbar_ope1_out_ep: endpoint { - remote-endpoint = <&ope1_cif_out_ep>; - }; - }; - }; - i2s@2901000 { status = "okay"; @@ -1991,6 +1135,867 @@ }; }; }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + xbar_admaif0: endpoint { + remote-endpoint = <&admaif0>; + }; + }; + + port@1 { + reg = <0x1>; + + xbar_admaif1: endpoint { + remote-endpoint = <&admaif1>; + }; + }; + + port@2 { + reg = <0x2>; + + xbar_admaif2: endpoint { + remote-endpoint = <&admaif2>; + }; + }; + + port@3 { + reg = <0x3>; + + xbar_admaif3: endpoint { + remote-endpoint = <&admaif3>; + }; + }; + + port@4 { + reg = <0x4>; + + xbar_admaif4: endpoint { + remote-endpoint = <&admaif4>; + }; + }; + + port@5 { + reg = <0x5>; + + xbar_admaif5: endpoint { + remote-endpoint = <&admaif5>; + }; + }; + + port@6 { + reg = <0x6>; + + xbar_admaif6: endpoint { + remote-endpoint = <&admaif6>; + }; + }; + + port@7 { + reg = <0x7>; + + xbar_admaif7: endpoint { + remote-endpoint = <&admaif7>; + }; + }; + + port@8 { + reg = <0x8>; + + xbar_admaif8: endpoint { + remote-endpoint = <&admaif8>; + }; + }; + + port@9 { + reg = <0x9>; + + xbar_admaif9: endpoint { + remote-endpoint = <&admaif9>; + }; + }; + + port@a { + reg = <0xa>; + + xbar_admaif10: endpoint { + remote-endpoint = <&admaif10>; + }; + }; + + port@b { + reg = <0xb>; + + xbar_admaif11: endpoint { + remote-endpoint = <&admaif11>; + }; + }; + + port@c { + reg = <0xc>; + + xbar_admaif12: endpoint { + remote-endpoint = <&admaif12>; + }; + }; + + port@d { + reg = <0xd>; + + xbar_admaif13: endpoint { + remote-endpoint = <&admaif13>; + }; + }; + + port@e { + reg = <0xe>; + + xbar_admaif14: endpoint { + remote-endpoint = <&admaif14>; + }; + }; + + port@f { + reg = <0xf>; + + xbar_admaif15: endpoint { + remote-endpoint = <&admaif15>; + }; + }; + + port@10 { + reg = <0x10>; + + xbar_admaif16: endpoint { + remote-endpoint = <&admaif16>; + }; + }; + + port@11 { + reg = <0x11>; + + xbar_admaif17: endpoint { + remote-endpoint = <&admaif17>; + }; + }; + + port@12 { + reg = <0x12>; + + xbar_admaif18: endpoint { + remote-endpoint = <&admaif18>; + }; + }; + + port@13 { + reg = <0x13>; + + xbar_admaif19: endpoint { + remote-endpoint = <&admaif19>; + }; + }; + + xbar_i2s1_port: port@14 { + reg = <0x14>; + + xbar_i2s1: endpoint { + remote-endpoint = <&i2s1_cif>; + }; + }; + + xbar_i2s2_port: port@15 { + reg = <0x15>; + + xbar_i2s2: endpoint { + remote-endpoint = <&i2s2_cif>; + }; + }; + + xbar_i2s4_port: port@17 { + reg = <0x17>; + + xbar_i2s4: endpoint { + remote-endpoint = <&i2s4_cif>; + }; + }; + + xbar_i2s6_port: port@19 { + reg = <0x19>; + + xbar_i2s6: endpoint { + remote-endpoint = <&i2s6_cif>; + }; + }; + + xbar_dmic3_port: port@1c { + reg = <0x1c>; + + xbar_dmic3: endpoint { + remote-endpoint = <&dmic3_cif>; + }; + }; + + xbar_sfc1_in_port: port@20 { + reg = <0x20>; + + xbar_sfc1_in: endpoint { + remote-endpoint = <&sfc1_cif_in>; + }; + }; + + port@21 { + reg = <0x21>; + + xbar_sfc1_out: endpoint { + remote-endpoint = <&sfc1_cif_out>; + }; + }; + + xbar_sfc2_in_port: port@22 { + reg = <0x22>; + + xbar_sfc2_in: endpoint { + remote-endpoint = <&sfc2_cif_in>; + }; + }; + + port@23 { + reg = <0x23>; + + xbar_sfc2_out: endpoint { + remote-endpoint = <&sfc2_cif_out>; + }; + }; + + xbar_sfc3_in_port: port@24 { + reg = <0x24>; + + xbar_sfc3_in: endpoint { + remote-endpoint = <&sfc3_cif_in>; + }; + }; + + port@25 { + reg = <0x25>; + + xbar_sfc3_out: endpoint { + remote-endpoint = <&sfc3_cif_out>; + }; + }; + + xbar_sfc4_in_port: port@26 { + reg = <0x26>; + + xbar_sfc4_in: endpoint { + remote-endpoint = <&sfc4_cif_in>; + }; + }; + + port@27 { + reg = <0x27>; + + xbar_sfc4_out: endpoint { + remote-endpoint = <&sfc4_cif_out>; + }; + }; + + xbar_mvc1_in_port: port@28 { + reg = <0x28>; + + xbar_mvc1_in: endpoint { + remote-endpoint = <&mvc1_cif_in>; + }; + }; + + port@29 { + reg = <0x29>; + + xbar_mvc1_out: endpoint { + remote-endpoint = <&mvc1_cif_out>; + }; + }; + + xbar_mvc2_in_port: port@2a { + reg = <0x2a>; + + xbar_mvc2_in: endpoint { + remote-endpoint = <&mvc2_cif_in>; + }; + }; + + port@2b { + reg = <0x2b>; + + xbar_mvc2_out: endpoint { + remote-endpoint = <&mvc2_cif_out>; + }; + }; + + xbar_amx1_in1_port: port@2c { + reg = <0x2c>; + + xbar_amx1_in1: endpoint { + remote-endpoint = <&amx1_in1>; + }; + }; + + xbar_amx1_in2_port: port@2d { + reg = <0x2d>; + + xbar_amx1_in2: endpoint { + remote-endpoint = <&amx1_in2>; + }; + }; + + xbar_amx1_in3_port: port@2e { + reg = <0x2e>; + + xbar_amx1_in3: endpoint { + remote-endpoint = <&amx1_in3>; + }; + }; + + xbar_amx1_in4_port: port@2f { + reg = <0x2f>; + + xbar_amx1_in4: endpoint { + remote-endpoint = <&amx1_in4>; + }; + }; + + port@30 { + reg = <0x30>; + + xbar_amx1_out: endpoint { + remote-endpoint = <&amx1_out>; + }; + }; + + xbar_amx2_in1_port: port@31 { + reg = <0x31>; + + xbar_amx2_in1: endpoint { + remote-endpoint = <&amx2_in1>; + }; + }; + + xbar_amx2_in2_port: port@32 { + reg = <0x32>; + + xbar_amx2_in2: endpoint { + remote-endpoint = <&amx2_in2>; + }; + }; + + xbar_amx2_in3_port: port@33 { + reg = <0x33>; + + xbar_amx2_in3: endpoint { + remote-endpoint = <&amx2_in3>; + }; + }; + + xbar_amx2_in4_port: port@34 { + reg = <0x34>; + + xbar_amx2_in4: endpoint { + remote-endpoint = <&amx2_in4>; + }; + }; + + port@35 { + reg = <0x35>; + + xbar_amx2_out: endpoint { + remote-endpoint = <&amx2_out>; + }; + }; + + xbar_amx3_in1_port: port@36 { + reg = <0x36>; + + xbar_amx3_in1: endpoint { + remote-endpoint = <&amx3_in1>; + }; + }; + + xbar_amx3_in2_port: port@37 { + reg = <0x37>; + + xbar_amx3_in2: endpoint { + remote-endpoint = <&amx3_in2>; + }; + }; + + xbar_amx3_in3_port: port@38 { + reg = <0x38>; + + xbar_amx3_in3: endpoint { + remote-endpoint = <&amx3_in3>; + }; + }; + + xbar_amx3_in4_port: port@39 { + reg = <0x39>; + + xbar_amx3_in4: endpoint { + remote-endpoint = <&amx3_in4>; + }; + }; + + port@3a { + reg = <0x3a>; + + xbar_amx3_out: endpoint { + remote-endpoint = <&amx3_out>; + }; + }; + + xbar_amx4_in1_port: port@3b { + reg = <0x3b>; + + xbar_amx4_in1: endpoint { + remote-endpoint = <&amx4_in1>; + }; + }; + + xbar_amx4_in2_port: port@3c { + reg = <0x3c>; + + xbar_amx4_in2: endpoint { + remote-endpoint = <&amx4_in2>; + }; + }; + + xbar_amx4_in3_port: port@3d { + reg = <0x3d>; + + xbar_amx4_in3: endpoint { + remote-endpoint = <&amx4_in3>; + }; + }; + + xbar_amx4_in4_port: port@3e { + reg = <0x3e>; + + xbar_amx4_in4: endpoint { + remote-endpoint = <&amx4_in4>; + }; + }; + + port@3f { + reg = <0x3f>; + + xbar_amx4_out: endpoint { + remote-endpoint = <&amx4_out>; + }; + }; + + xbar_adx1_in_port: port@40 { + reg = <0x40>; + + xbar_adx1_in: endpoint { + remote-endpoint = <&adx1_in>; + }; + }; + + port@41 { + reg = <0x41>; + + xbar_adx1_out1: endpoint { + remote-endpoint = <&adx1_out1>; + }; + }; + + port@42 { + reg = <0x42>; + + xbar_adx1_out2: endpoint { + remote-endpoint = <&adx1_out2>; + }; + }; + + port@43 { + reg = <0x43>; + + xbar_adx1_out3: endpoint { + remote-endpoint = <&adx1_out3>; + }; + }; + + port@44 { + reg = <0x44>; + + xbar_adx1_out4: endpoint { + remote-endpoint = <&adx1_out4>; + }; + }; + + xbar_adx2_in_port: port@45 { + reg = <0x45>; + + xbar_adx2_in: endpoint { + remote-endpoint = <&adx2_in>; + }; + }; + + port@46 { + reg = <0x46>; + + xbar_adx2_out1: endpoint { + remote-endpoint = <&adx2_out1>; + }; + }; + + port@47 { + reg = <0x47>; + + xbar_adx2_out2: endpoint { + remote-endpoint = <&adx2_out2>; + }; + }; + + port@48 { + reg = <0x48>; + + xbar_adx2_out3: endpoint { + remote-endpoint = <&adx2_out3>; + }; + }; + + port@49 { + reg = <0x49>; + + xbar_adx2_out4: endpoint { + remote-endpoint = <&adx2_out4>; + }; + }; + + xbar_adx3_in_port: port@4a { + reg = <0x4a>; + + xbar_adx3_in: endpoint { + remote-endpoint = <&adx3_in>; + }; + }; + + port@4b { + reg = <0x4b>; + + xbar_adx3_out1: endpoint { + remote-endpoint = <&adx3_out1>; + }; + }; + + port@4c { + reg = <0x4c>; + + xbar_adx3_out2: endpoint { + remote-endpoint = <&adx3_out2>; + }; + }; + + port@4d { + reg = <0x4d>; + + xbar_adx3_out3: endpoint { + remote-endpoint = <&adx3_out3>; + }; + }; + + port@4e { + reg = <0x4e>; + + xbar_adx3_out4: endpoint { + remote-endpoint = <&adx3_out4>; + }; + }; + + xbar_adx4_in_port: port@4f { + reg = <0x4f>; + + xbar_adx4_in: endpoint { + remote-endpoint = <&adx4_in>; + }; + }; + + port@50 { + reg = <0x50>; + + xbar_adx4_out1: endpoint { + remote-endpoint = <&adx4_out1>; + }; + }; + + port@51 { + reg = <0x51>; + + xbar_adx4_out2: endpoint { + remote-endpoint = <&adx4_out2>; + }; + }; + + port@52 { + reg = <0x52>; + + xbar_adx4_out3: endpoint { + remote-endpoint = <&adx4_out3>; + }; + }; + + port@53 { + reg = <0x53>; + + xbar_adx4_out4: endpoint { + remote-endpoint = <&adx4_out4>; + }; + }; + + xbar_mix_in1_port: port@54 { + reg = <0x54>; + + xbar_mix_in1: endpoint { + remote-endpoint = <&mix_in1>; + }; + }; + + xbar_mix_in2_port: port@55 { + reg = <0x55>; + + xbar_mix_in2: endpoint { + remote-endpoint = <&mix_in2>; + }; + }; + + xbar_mix_in3_port: port@56 { + reg = <0x56>; + + xbar_mix_in3: endpoint { + remote-endpoint = <&mix_in3>; + }; + }; + + xbar_mix_in4_port: port@57 { + reg = <0x57>; + + xbar_mix_in4: endpoint { + remote-endpoint = <&mix_in4>; + }; + }; + + xbar_mix_in5_port: port@58 { + reg = <0x58>; + + xbar_mix_in5: endpoint { + remote-endpoint = <&mix_in5>; + }; + }; + + xbar_mix_in6_port: port@59 { + reg = <0x59>; + + xbar_mix_in6: endpoint { + remote-endpoint = <&mix_in6>; + }; + }; + + xbar_mix_in7_port: port@5a { + reg = <0x5a>; + + xbar_mix_in7: endpoint { + remote-endpoint = <&mix_in7>; + }; + }; + + xbar_mix_in8_port: port@5b { + reg = <0x5b>; + + xbar_mix_in8: endpoint { + remote-endpoint = <&mix_in8>; + }; + }; + + xbar_mix_in9_port: port@5c { + reg = <0x5c>; + + xbar_mix_in9: endpoint { + remote-endpoint = <&mix_in9>; + }; + }; + + xbar_mix_in10_port: port@5d { + reg = <0x5d>; + + xbar_mix_in10: endpoint { + remote-endpoint = <&mix_in10>; + }; + }; + + port@5e { + reg = <0x5e>; + + xbar_mix_out1: endpoint { + remote-endpoint = <&mix_out1>; + }; + }; + + port@5f { + reg = <0x5f>; + + xbar_mix_out2: endpoint { + remote-endpoint = <&mix_out2>; + }; + }; + + port@60 { + reg = <0x60>; + + xbar_mix_out3: endpoint { + remote-endpoint = <&mix_out3>; + }; + }; + + port@61 { + reg = <0x61>; + + xbar_mix_out4: endpoint { + remote-endpoint = <&mix_out4>; + }; + }; + + port@62 { + reg = <0x62>; + + xbar_mix_out5: endpoint { + remote-endpoint = <&mix_out5>; + }; + }; + + xbar_asrc_in1_port: port@63 { + reg = <0x63>; + + xbar_asrc_in1_ep: endpoint { + remote-endpoint = <&asrc_in1_ep>; + }; + }; + + port@64 { + reg = <0x64>; + + xbar_asrc_out1_ep: endpoint { + remote-endpoint = <&asrc_out1_ep>; + }; + }; + + xbar_asrc_in2_port: port@65 { + reg = <0x65>; + + xbar_asrc_in2_ep: endpoint { + remote-endpoint = <&asrc_in2_ep>; + }; + }; + + port@66 { + reg = <0x66>; + + xbar_asrc_out2_ep: endpoint { + remote-endpoint = <&asrc_out2_ep>; + }; + }; + + xbar_asrc_in3_port: port@67 { + reg = <0x67>; + + xbar_asrc_in3_ep: endpoint { + remote-endpoint = <&asrc_in3_ep>; + }; + }; + + port@68 { + reg = <0x68>; + + xbar_asrc_out3_ep: endpoint { + remote-endpoint = <&asrc_out3_ep>; + }; + }; + + xbar_asrc_in4_port: port@69 { + reg = <0x69>; + + xbar_asrc_in4_ep: endpoint { + remote-endpoint = <&asrc_in4_ep>; + }; + }; + + port@6a { + reg = <0x6a>; + + xbar_asrc_out4_ep: endpoint { + remote-endpoint = <&asrc_out4_ep>; + }; + }; + + xbar_asrc_in5_port: port@6b { + reg = <0x6b>; + + xbar_asrc_in5_ep: endpoint { + remote-endpoint = <&asrc_in5_ep>; + }; + }; + + port@6c { + reg = <0x6c>; + + xbar_asrc_out5_ep: endpoint { + remote-endpoint = <&asrc_out5_ep>; + }; + }; + + xbar_asrc_in6_port: port@6d { + reg = <0x6d>; + + xbar_asrc_in6_ep: endpoint { + remote-endpoint = <&asrc_in6_ep>; + }; + }; + + port@6e { + reg = <0x6e>; + + xbar_asrc_out6_ep: endpoint { + remote-endpoint = <&asrc_out6_ep>; + }; + }; + + xbar_asrc_in7_port: port@6f { + reg = <0x6f>; + + xbar_asrc_in7_ep: endpoint { + remote-endpoint = <&asrc_in7_ep>; + }; + }; + + xbar_ope1_in_port: port@70 { + reg = <0x70>; + + xbar_ope1_in_ep: endpoint { + remote-endpoint = <&ope1_cif_in_ep>; + }; + }; + + port@71 { + reg = <0x71>; + + xbar_ope1_out_ep: endpoint { + remote-endpoint = <&ope1_cif_out_ep>; + }; + }; + }; }; dma-controller@2930000 { @@ -2022,14 +2027,100 @@ nvidia,model = "NVIDIA Jetson AGX Orin HDA"; status = "okay"; }; - }; - chosen { - bootargs = "console=ttyTCU0,115200n8"; - stdout-path = "serial0:115200n8"; - }; + padctl@3520000 { + status = "okay"; + + pads { + usb2 { + lanes { + usb2-0 { + status = "okay"; + }; + + usb2-1 { + status = "okay"; + }; + + usb2-2 { + status = "okay"; + }; + + usb2-3 { + status = "okay"; + }; + }; + }; + + usb3 { + lanes { + usb3-0 { + status = "okay"; + }; + + usb3-1 { + status = "okay"; + }; + + usb3-2 { + status = "okay"; + }; + }; + }; + }; + + ports { + usb2-0 { + mode = "host"; + status = "okay"; + }; + + usb2-1 { + mode = "host"; + status = "okay"; + }; + + usb2-2 { + mode = "host"; + status = "okay"; + }; + + usb2-3 { + mode = "host"; + status = "okay"; + }; + + usb3-0 { + nvidia,usb2-companion = <1>; + status = "okay"; + }; + + usb3-1 { + nvidia,usb2-companion = <0>; + status = "okay"; + }; + + usb3-2 { + nvidia,usb2-companion = <3>; + status = "okay"; + }; + }; + }; + + usb@3610000 { + status = "okay"; + + phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>, + <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-1}>, + <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-2}>, + <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-3}>, + <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-0}>, + <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>, + <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-2}>; + phy-names = "usb2-0", "usb2-1", "usb2-2", "usb2-3", + "usb3-0", "usb3-1", "usb3-2"; + }; - bus@0 { ethernet@6800000 { status = "okay"; @@ -2048,6 +2139,57 @@ }; }; }; + + pcie@14100000 { + status = "okay"; + + vddio-pex-ctl-supply = <&vdd_1v8_ao>; + + phys = <&p2u_hsio_3>; + phy-names = "p2u-0"; + }; + + pcie@14160000 { + status = "okay"; + + vddio-pex-ctl-supply = <&vdd_1v8_ao>; + + phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>, + <&p2u_hsio_7>; + phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3"; + }; + + pcie@141a0000 { + status = "okay"; + + vddio-pex-ctl-supply = <&vdd_1v8_ls>; + vpcie3v3-supply = <&vdd_3v3_pcie>; + vpcie12v-supply = <&vdd_12v_pcie>; + + phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, + <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, + <&p2u_nvhs_6>, <&p2u_nvhs_7>; + phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", + "p2u-5", "p2u-6", "p2u-7"; + }; + + pcie-ep@141a0000 { + status = "disabled"; + + vddio-pex-ctl-supply = <&vdd_1v8_ls>; + + reset-gpios = <&gpio TEGRA234_MAIN_GPIO(AF, 1) GPIO_ACTIVE_LOW>; + + nvidia,refclk-select-gpios = <&gpio_aon + TEGRA234_AON_GPIO(AA, 4) + GPIO_ACTIVE_HIGH>; + + phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, + <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, + <&p2u_nvhs_6>, <&p2u_nvhs_7>; + phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", + "p2u-5", "p2u-6", "p2u-7"; + }; }; gpio-keys { @@ -2078,6 +2220,14 @@ }; }; + pwm-fan { + compatible = "pwm-fan"; + pwms = <&pwm3 0 45334>; + + cooling-levels = <0 95 178 255>; + #cooling-cells = <2>; + }; + serial { status = "okay"; }; @@ -2144,63 +2294,4 @@ label = "NVIDIA Jetson AGX Orin APE"; }; - - pcie@14100000 { - status = "okay"; - - vddio-pex-ctl-supply = <&vdd_1v8_ao>; - - phys = <&p2u_hsio_3>; - phy-names = "p2u-0"; - }; - - pcie@14160000 { - status = "okay"; - - vddio-pex-ctl-supply = <&vdd_1v8_ao>; - - phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>, - <&p2u_hsio_7>; - phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3"; - }; - - pcie@141a0000 { - status = "okay"; - - vddio-pex-ctl-supply = <&vdd_1v8_ls>; - vpcie3v3-supply = <&vdd_3v3_pcie>; - vpcie12v-supply = <&vdd_12v_pcie>; - - phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, - <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, - <&p2u_nvhs_6>, <&p2u_nvhs_7>; - phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", - "p2u-5", "p2u-6", "p2u-7"; - }; - - pcie-ep@141a0000 { - status = "disabled"; - - vddio-pex-ctl-supply = <&vdd_1v8_ls>; - - reset-gpios = <&gpio TEGRA234_MAIN_GPIO(AF, 1) GPIO_ACTIVE_LOW>; - - nvidia,refclk-select-gpios = <&gpio_aon - TEGRA234_AON_GPIO(AA, 4) - GPIO_ACTIVE_HIGH>; - - phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, - <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, - <&p2u_nvhs_6>, <&p2u_nvhs_7>; - phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", - "p2u-5", "p2u-6", "p2u-7"; - }; - - pwm-fan { - compatible = "pwm-fan"; - pwms = <&pwm3 0 45334>; - - cooling-levels = <0 95 178 255>; - #cooling-cells = <2>; - }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000.dtsi index e76894574d32..022a5408d869 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000.dtsi @@ -4,6 +4,22 @@ compatible = "nvidia,p3737-0000"; bus@0 { + i2c@3160000 { + status = "okay"; + + eeprom@56 { + compatible = "atmel,24c02"; + reg = <0x56>; + + label = "system"; + vcc-supply = <&vdd_1v8_sys>; + address-width = <8>; + pagesize = <8>; + size = <256>; + read-only; + }; + }; + pwm@3280000 { status = "okay"; }; @@ -16,4 +32,12 @@ status = "okay"; }; }; + + vdd_1v8_sys: regulator-vdd-1v8-sys { + compatible = "regulator-fixed"; + regulator-name = "VDD_1V8_SYS"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index eaf05ee9acd1..8fe8eda7654d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -5,9 +5,9 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/mailbox/tegra186-hsp.h> #include <dt-bindings/memory/tegra234-mc.h> +#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> #include <dt-bindings/power/tegra234-powergate.h> #include <dt-bindings/reset/tegra234-reset.h> -#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> / { compatible = "nvidia,tegra234"; @@ -17,15 +17,103 @@ bus@0 { compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x0 0x40000000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0x0 0x0 0x40000000>; + + misc@100000 { + compatible = "nvidia,tegra234-misc"; + reg = <0x0 0x00100000 0x0 0xf000>, + <0x0 0x0010f000 0x0 0x1000>; + status = "okay"; + }; + + timer@2080000 { + compatible = "nvidia,tegra234-timer"; + reg = <0x0 0x02080000 0x0 0x00121000>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; + status = "okay"; + }; + + gpio: gpio@2200000 { + compatible = "nvidia,tegra234-gpio"; + reg-names = "security", "gpio"; + reg = <0x0 0x02200000 0x0 0x10000>, + <0x0 0x02210000 0x0 0x10000>; + interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <2>; + interrupt-controller; + #gpio-cells = <2>; + gpio-controller; + }; gpcdma: dma-controller@2600000 { compatible = "nvidia,tegra234-gpcdma", "nvidia,tegra186-gpcdma"; - reg = <0x2600000 0x210000>; + reg = <0x0 0x2600000 0x0 0x210000>; resets = <&bpmp TEGRA234_RESET_GPCDMA>; reset-names = "gpcdma"; interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, @@ -73,27 +161,29 @@ <&bpmp TEGRA234_CLK_APB2APE>; clock-names = "ape", "apb2ape"; power-domains = <&bpmp TEGRA234_POWER_DOMAIN_AUD>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x02900000 0x02900000 0x200000>; status = "disabled"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x02900000 0x0 0x02900000 0x0 0x200000>; + tegra_ahub: ahub@2900800 { compatible = "nvidia,tegra234-ahub"; - reg = <0x02900800 0x800>; + reg = <0x0 0x02900800 0x0 0x800>; clocks = <&bpmp TEGRA234_CLK_AHUB>; clock-names = "ahub"; assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>; assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x02900800 0x02900800 0x11800>; status = "disabled"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>; + tegra_i2s1: i2s@2901000 { compatible = "nvidia,tegra234-i2s", "nvidia,tegra210-i2s"; - reg = <0x2901000 0x100>; + reg = <0x0 0x2901000 0x0 0x100>; clocks = <&bpmp TEGRA234_CLK_I2S1>, <&bpmp TEGRA234_CLK_I2S1_SYNC_INPUT>; clock-names = "i2s", "sync_input"; @@ -107,7 +197,7 @@ tegra_i2s2: i2s@2901100 { compatible = "nvidia,tegra234-i2s", "nvidia,tegra210-i2s"; - reg = <0x2901100 0x100>; + reg = <0x0 0x2901100 0x0 0x100>; clocks = <&bpmp TEGRA234_CLK_I2S2>, <&bpmp TEGRA234_CLK_I2S2_SYNC_INPUT>; clock-names = "i2s", "sync_input"; @@ -121,7 +211,7 @@ tegra_i2s3: i2s@2901200 { compatible = "nvidia,tegra234-i2s", "nvidia,tegra210-i2s"; - reg = <0x2901200 0x100>; + reg = <0x0 0x2901200 0x0 0x100>; clocks = <&bpmp TEGRA234_CLK_I2S3>, <&bpmp TEGRA234_CLK_I2S3_SYNC_INPUT>; clock-names = "i2s", "sync_input"; @@ -135,7 +225,7 @@ tegra_i2s4: i2s@2901300 { compatible = "nvidia,tegra234-i2s", "nvidia,tegra210-i2s"; - reg = <0x2901300 0x100>; + reg = <0x0 0x2901300 0x0 0x100>; clocks = <&bpmp TEGRA234_CLK_I2S4>, <&bpmp TEGRA234_CLK_I2S4_SYNC_INPUT>; clock-names = "i2s", "sync_input"; @@ -149,7 +239,7 @@ tegra_i2s5: i2s@2901400 { compatible = "nvidia,tegra234-i2s", "nvidia,tegra210-i2s"; - reg = <0x2901400 0x100>; + reg = <0x0 0x2901400 0x0 0x100>; clocks = <&bpmp TEGRA234_CLK_I2S5>, <&bpmp TEGRA234_CLK_I2S5_SYNC_INPUT>; clock-names = "i2s", "sync_input"; @@ -163,7 +253,7 @@ tegra_i2s6: i2s@2901500 { compatible = "nvidia,tegra234-i2s", "nvidia,tegra210-i2s"; - reg = <0x2901500 0x100>; + reg = <0x0 0x2901500 0x0 0x100>; clocks = <&bpmp TEGRA234_CLK_I2S6>, <&bpmp TEGRA234_CLK_I2S6_SYNC_INPUT>; clock-names = "i2s", "sync_input"; @@ -177,7 +267,7 @@ tegra_sfc1: sfc@2902000 { compatible = "nvidia,tegra234-sfc", "nvidia,tegra210-sfc"; - reg = <0x2902000 0x200>; + reg = <0x0 0x2902000 0x0 0x200>; sound-name-prefix = "SFC1"; status = "disabled"; }; @@ -185,7 +275,7 @@ tegra_sfc2: sfc@2902200 { compatible = "nvidia,tegra234-sfc", "nvidia,tegra210-sfc"; - reg = <0x2902200 0x200>; + reg = <0x0 0x2902200 0x0 0x200>; sound-name-prefix = "SFC2"; status = "disabled"; }; @@ -193,7 +283,7 @@ tegra_sfc3: sfc@2902400 { compatible = "nvidia,tegra234-sfc", "nvidia,tegra210-sfc"; - reg = <0x2902400 0x200>; + reg = <0x0 0x2902400 0x0 0x200>; sound-name-prefix = "SFC3"; status = "disabled"; }; @@ -201,7 +291,7 @@ tegra_sfc4: sfc@2902600 { compatible = "nvidia,tegra234-sfc", "nvidia,tegra210-sfc"; - reg = <0x2902600 0x200>; + reg = <0x0 0x2902600 0x0 0x200>; sound-name-prefix = "SFC4"; status = "disabled"; }; @@ -209,7 +299,7 @@ tegra_amx1: amx@2903000 { compatible = "nvidia,tegra234-amx", "nvidia,tegra194-amx"; - reg = <0x2903000 0x100>; + reg = <0x0 0x2903000 0x0 0x100>; sound-name-prefix = "AMX1"; status = "disabled"; }; @@ -217,7 +307,7 @@ tegra_amx2: amx@2903100 { compatible = "nvidia,tegra234-amx", "nvidia,tegra194-amx"; - reg = <0x2903100 0x100>; + reg = <0x0 0x2903100 0x0 0x100>; sound-name-prefix = "AMX2"; status = "disabled"; }; @@ -225,7 +315,7 @@ tegra_amx3: amx@2903200 { compatible = "nvidia,tegra234-amx", "nvidia,tegra194-amx"; - reg = <0x2903200 0x100>; + reg = <0x0 0x2903200 0x0 0x100>; sound-name-prefix = "AMX3"; status = "disabled"; }; @@ -233,7 +323,7 @@ tegra_amx4: amx@2903300 { compatible = "nvidia,tegra234-amx", "nvidia,tegra194-amx"; - reg = <0x2903300 0x100>; + reg = <0x0 0x2903300 0x0 0x100>; sound-name-prefix = "AMX4"; status = "disabled"; }; @@ -241,7 +331,7 @@ tegra_adx1: adx@2903800 { compatible = "nvidia,tegra234-adx", "nvidia,tegra210-adx"; - reg = <0x2903800 0x100>; + reg = <0x0 0x2903800 0x0 0x100>; sound-name-prefix = "ADX1"; status = "disabled"; }; @@ -249,7 +339,7 @@ tegra_adx2: adx@2903900 { compatible = "nvidia,tegra234-adx", "nvidia,tegra210-adx"; - reg = <0x2903900 0x100>; + reg = <0x0 0x2903900 0x0 0x100>; sound-name-prefix = "ADX2"; status = "disabled"; }; @@ -257,7 +347,7 @@ tegra_adx3: adx@2903a00 { compatible = "nvidia,tegra234-adx", "nvidia,tegra210-adx"; - reg = <0x2903a00 0x100>; + reg = <0x0 0x2903a00 0x0 0x100>; sound-name-prefix = "ADX3"; status = "disabled"; }; @@ -265,7 +355,7 @@ tegra_adx4: adx@2903b00 { compatible = "nvidia,tegra234-adx", "nvidia,tegra210-adx"; - reg = <0x2903b00 0x100>; + reg = <0x0 0x2903b00 0x0 0x100>; sound-name-prefix = "ADX4"; status = "disabled"; }; @@ -274,7 +364,7 @@ tegra_dmic1: dmic@2904000 { compatible = "nvidia,tegra234-dmic", "nvidia,tegra210-dmic"; - reg = <0x2904000 0x100>; + reg = <0x0 0x2904000 0x0 0x100>; clocks = <&bpmp TEGRA234_CLK_DMIC1>; clock-names = "dmic"; assigned-clocks = <&bpmp TEGRA234_CLK_DMIC1>; @@ -287,7 +377,7 @@ tegra_dmic2: dmic@2904100 { compatible = "nvidia,tegra234-dmic", "nvidia,tegra210-dmic"; - reg = <0x2904100 0x100>; + reg = <0x0 0x2904100 0x0 0x100>; clocks = <&bpmp TEGRA234_CLK_DMIC2>; clock-names = "dmic"; assigned-clocks = <&bpmp TEGRA234_CLK_DMIC2>; @@ -300,7 +390,7 @@ tegra_dmic3: dmic@2904200 { compatible = "nvidia,tegra234-dmic", "nvidia,tegra210-dmic"; - reg = <0x2904200 0x100>; + reg = <0x0 0x2904200 0x0 0x100>; clocks = <&bpmp TEGRA234_CLK_DMIC3>; clock-names = "dmic"; assigned-clocks = <&bpmp TEGRA234_CLK_DMIC3>; @@ -313,7 +403,7 @@ tegra_dmic4: dmic@2904300 { compatible = "nvidia,tegra234-dmic", "nvidia,tegra210-dmic"; - reg = <0x2904300 0x100>; + reg = <0x0 0x2904300 0x0 0x100>; clocks = <&bpmp TEGRA234_CLK_DMIC4>; clock-names = "dmic"; assigned-clocks = <&bpmp TEGRA234_CLK_DMIC4>; @@ -326,7 +416,7 @@ tegra_dspk1: dspk@2905000 { compatible = "nvidia,tegra234-dspk", "nvidia,tegra186-dspk"; - reg = <0x2905000 0x100>; + reg = <0x0 0x2905000 0x0 0x100>; clocks = <&bpmp TEGRA234_CLK_DSPK1>; clock-names = "dspk"; assigned-clocks = <&bpmp TEGRA234_CLK_DSPK1>; @@ -339,7 +429,7 @@ tegra_dspk2: dspk@2905100 { compatible = "nvidia,tegra234-dspk", "nvidia,tegra186-dspk"; - reg = <0x2905100 0x100>; + reg = <0x0 0x2905100 0x0 0x100>; clocks = <&bpmp TEGRA234_CLK_DSPK2>; clock-names = "dspk"; assigned-clocks = <&bpmp TEGRA234_CLK_DSPK2>; @@ -352,30 +442,31 @@ tegra_ope1: processing-engine@2908000 { compatible = "nvidia,tegra234-ope", "nvidia,tegra210-ope"; - reg = <0x2908000 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges; + reg = <0x0 0x2908000 0x0 0x100>; sound-name-prefix = "OPE1"; status = "disabled"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + equalizer@2908100 { compatible = "nvidia,tegra234-peq", "nvidia,tegra210-peq"; - reg = <0x2908100 0x100>; + reg = <0x0 0x2908100 0x0 0x100>; }; dynamic-range-compressor@2908200 { compatible = "nvidia,tegra234-mbdrc", "nvidia,tegra210-mbdrc"; - reg = <0x2908200 0x200>; + reg = <0x0 0x2908200 0x0 0x200>; }; }; tegra_mvc1: mvc@290a000 { compatible = "nvidia,tegra234-mvc", "nvidia,tegra210-mvc"; - reg = <0x290a000 0x200>; + reg = <0x0 0x290a000 0x0 0x200>; sound-name-prefix = "MVC1"; status = "disabled"; }; @@ -383,7 +474,7 @@ tegra_mvc2: mvc@290a200 { compatible = "nvidia,tegra234-mvc", "nvidia,tegra210-mvc"; - reg = <0x290a200 0x200>; + reg = <0x0 0x290a200 0x0 0x200>; sound-name-prefix = "MVC2"; status = "disabled"; }; @@ -391,7 +482,7 @@ tegra_amixer: amixer@290bb00 { compatible = "nvidia,tegra234-amixer", "nvidia,tegra210-amixer"; - reg = <0x290bb00 0x800>; + reg = <0x0 0x290bb00 0x0 0x800>; sound-name-prefix = "MIXER1"; status = "disabled"; }; @@ -399,7 +490,7 @@ tegra_admaif: admaif@290f000 { compatible = "nvidia,tegra234-admaif", "nvidia,tegra186-admaif"; - reg = <0x0290f000 0x1000>; + reg = <0x0 0x0290f000 0x0 0x1000>; dmas = <&adma 1>, <&adma 1>, <&adma 2>, <&adma 2>, <&adma 3>, <&adma 3>, @@ -450,7 +541,7 @@ tegra_asrc: asrc@2910000 { compatible = "nvidia,tegra234-asrc", "nvidia,tegra186-asrc"; - reg = <0x2910000 0x2000>; + reg = <0x0 0x2910000 0x0 0x2000>; sound-name-prefix = "ASRC1"; status = "disabled"; }; @@ -459,7 +550,7 @@ adma: dma-controller@2930000 { compatible = "nvidia,tegra234-adma", "nvidia,tegra186-adma"; - reg = <0x02930000 0x20000>; + reg = <0x0 0x02930000 0x0 0x20000>; interrupt-parent = <&agic>; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, @@ -504,8 +595,8 @@ "nvidia,tegra210-agic"; #interrupt-cells = <3>; interrupt-controller; - reg = <0x02a41000 0x1000>, - <0x02a42000 0x2000>; + reg = <0x0 0x02a41000 0x0 0x1000>, + <0x0 0x02a42000 0x0 0x2000>; interrupts = <GIC_SPI 145 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; @@ -515,214 +606,26 @@ }; }; - misc@100000 { - compatible = "nvidia,tegra234-misc"; - reg = <0x00100000 0xf000>, - <0x0010f000 0x1000>; - status = "okay"; - }; - - timer@2080000 { - compatible = "nvidia,tegra234-timer"; - reg = <0x02080000 0x00121000>; - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; - status = "okay"; - }; - - host1x@13e00000 { - compatible = "nvidia,tegra234-host1x"; - reg = <0x13e00000 0x10000>, - <0x13e10000 0x10000>, - <0x13e40000 0x10000>; - reg-names = "common", "hypervisor", "vm"; - interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "syncpt0", "syncpt1", "syncpt2", "syncpt3", "syncpt4", - "syncpt5", "syncpt6", "syncpt7", "host1x"; - clocks = <&bpmp TEGRA234_CLK_HOST1X>; - clock-names = "host1x"; - - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0x14800000 0x14800000 0x02000000>; - interconnects = <&mc TEGRA234_MEMORY_CLIENT_HOST1XDMAR &emc>; - interconnect-names = "dma-mem"; - iommus = <&smmu_niso1 TEGRA234_SID_HOST1X>; - - /* Context isolation domains */ - iommu-map = <0 &smmu_niso0 TEGRA234_SID_HOST1X_CTX0 1>, - <1 &smmu_niso0 TEGRA234_SID_HOST1X_CTX1 1>, - <2 &smmu_niso0 TEGRA234_SID_HOST1X_CTX2 1>, - <3 &smmu_niso0 TEGRA234_SID_HOST1X_CTX3 1>, - <4 &smmu_niso0 TEGRA234_SID_HOST1X_CTX4 1>, - <5 &smmu_niso0 TEGRA234_SID_HOST1X_CTX5 1>, - <6 &smmu_niso0 TEGRA234_SID_HOST1X_CTX6 1>, - <7 &smmu_niso0 TEGRA234_SID_HOST1X_CTX7 1>, - <8 &smmu_niso1 TEGRA234_SID_HOST1X_CTX0 1>, - <9 &smmu_niso1 TEGRA234_SID_HOST1X_CTX1 1>, - <10 &smmu_niso1 TEGRA234_SID_HOST1X_CTX2 1>, - <11 &smmu_niso1 TEGRA234_SID_HOST1X_CTX3 1>, - <12 &smmu_niso1 TEGRA234_SID_HOST1X_CTX4 1>, - <13 &smmu_niso1 TEGRA234_SID_HOST1X_CTX5 1>, - <14 &smmu_niso1 TEGRA234_SID_HOST1X_CTX6 1>, - <15 &smmu_niso1 TEGRA234_SID_HOST1X_CTX7 1>; - - vic@15340000 { - compatible = "nvidia,tegra234-vic"; - reg = <0x15340000 0x00040000>; - interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&bpmp TEGRA234_CLK_VIC>; - clock-names = "vic"; - resets = <&bpmp TEGRA234_RESET_VIC>; - reset-names = "vic"; - - power-domains = <&bpmp TEGRA234_POWER_DOMAIN_VIC>; - interconnects = <&mc TEGRA234_MEMORY_CLIENT_VICSRD &emc>, - <&mc TEGRA234_MEMORY_CLIENT_VICSWR &emc>; - interconnect-names = "dma-mem", "write"; - iommus = <&smmu_niso1 TEGRA234_SID_VIC>; - dma-coherent; - }; - - nvdec@15480000 { - compatible = "nvidia,tegra234-nvdec"; - reg = <0x15480000 0x00040000>; - clocks = <&bpmp TEGRA234_CLK_NVDEC>, - <&bpmp TEGRA234_CLK_FUSE>, - <&bpmp TEGRA234_CLK_TSEC_PKA>; - clock-names = "nvdec", "fuse", "tsec_pka"; - resets = <&bpmp TEGRA234_RESET_NVDEC>; - reset-names = "nvdec"; - power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>; - interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>, - <&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>; - interconnect-names = "dma-mem", "write"; - iommus = <&smmu_niso1 TEGRA234_SID_NVDEC>; - dma-coherent; - - nvidia,memory-controller = <&mc>; - - /* - * Placeholder values that firmware needs to update with the real - * offsets parsed from the microcode headers. - */ - nvidia,bl-manifest-offset = <0>; - nvidia,bl-data-offset = <0>; - nvidia,bl-code-offset = <0>; - nvidia,os-manifest-offset = <0>; - nvidia,os-data-offset = <0>; - nvidia,os-code-offset = <0>; - - /* - * Firmware needs to set this to "okay" once the above values have - * been updated. - */ - status = "disabled"; - }; - }; - - gpio: gpio@2200000 { - compatible = "nvidia,tegra234-gpio"; - reg-names = "security", "gpio"; - reg = <0x02200000 0x10000>, - <0x02210000 0x10000>; - interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; - #interrupt-cells = <2>; - interrupt-controller; - #gpio-cells = <2>; - gpio-controller; - }; - mc: memory-controller@2c00000 { compatible = "nvidia,tegra234-mc"; - reg = <0x02c00000 0x10000>, /* MC-SID */ - <0x02c10000 0x10000>, /* MC Broadcast*/ - <0x02c20000 0x10000>, /* MC0 */ - <0x02c30000 0x10000>, /* MC1 */ - <0x02c40000 0x10000>, /* MC2 */ - <0x02c50000 0x10000>, /* MC3 */ - <0x02b80000 0x10000>, /* MC4 */ - <0x02b90000 0x10000>, /* MC5 */ - <0x02ba0000 0x10000>, /* MC6 */ - <0x02bb0000 0x10000>, /* MC7 */ - <0x01700000 0x10000>, /* MC8 */ - <0x01710000 0x10000>, /* MC9 */ - <0x01720000 0x10000>, /* MC10 */ - <0x01730000 0x10000>, /* MC11 */ - <0x01740000 0x10000>, /* MC12 */ - <0x01750000 0x10000>, /* MC13 */ - <0x01760000 0x10000>, /* MC14 */ - <0x01770000 0x10000>; /* MC15 */ + reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ + <0x0 0x02c10000 0x0 0x10000>, /* MC Broadcast*/ + <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ + <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ + <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ + <0x0 0x02c50000 0x0 0x10000>, /* MC3 */ + <0x0 0x02b80000 0x0 0x10000>, /* MC4 */ + <0x0 0x02b90000 0x0 0x10000>, /* MC5 */ + <0x0 0x02ba0000 0x0 0x10000>, /* MC6 */ + <0x0 0x02bb0000 0x0 0x10000>, /* MC7 */ + <0x0 0x01700000 0x0 0x10000>, /* MC8 */ + <0x0 0x01710000 0x0 0x10000>, /* MC9 */ + <0x0 0x01720000 0x0 0x10000>, /* MC10 */ + <0x0 0x01730000 0x0 0x10000>, /* MC11 */ + <0x0 0x01740000 0x0 0x10000>, /* MC12 */ + <0x0 0x01750000 0x0 0x10000>, /* MC13 */ + <0x0 0x01760000 0x0 0x10000>, /* MC14 */ + <0x0 0x01770000 0x0 0x10000>; /* MC15 */ reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14", "ch15"; @@ -732,10 +635,9 @@ #address-cells = <2>; #size-cells = <2>; - - ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, - <0x02b80000 0x0 0x02b80000 0x0 0x040000>, - <0x02c00000 0x0 0x02c00000 0x0 0x100000>; + ranges = <0x0 0x01700000 0x0 0x01700000 0x0 0x100000>, + <0x0 0x02b80000 0x0 0x02b80000 0x0 0x040000>, + <0x0 0x02c00000 0x0 0x02c00000 0x0 0x100000>; /* * Bit 39 of addresses passing through the memory @@ -752,7 +654,7 @@ * * Limit the DMA range for memory clients to [38:0]. */ - dma-ranges = <0x0 0x0 0x0 0x80 0x0>; + dma-ranges = <0x0 0x0 0x0 0x0 0x80 0x0>; emc: external-memory-controller@2c60000 { compatible = "nvidia,tegra234-emc"; @@ -771,7 +673,7 @@ uarta: serial@3100000 { compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; - reg = <0x03100000 0x10000>; + reg = <0x0 0x03100000 0x0 0x10000>; interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA234_CLK_UARTA>; clock-names = "serial"; @@ -782,9 +684,11 @@ gen1_i2c: i2c@3160000 { compatible = "nvidia,tegra194-i2c"; - reg = <0x3160000 0x100>; + reg = <0x0 0x3160000 0x0 0x100>; status = "disabled"; interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; clock-frequency = <400000>; clocks = <&bpmp TEGRA234_CLK_I2C1 &bpmp TEGRA234_CLK_PLLP_OUT0>; @@ -793,16 +697,16 @@ clock-names = "div-clk", "parent"; resets = <&bpmp TEGRA234_RESET_I2C1>; reset-names = "i2c"; - iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; - dma-coherent; dmas = <&gpcdma 21>, <&gpcdma 21>; dma-names = "rx", "tx"; }; cam_i2c: i2c@3180000 { compatible = "nvidia,tegra194-i2c"; - reg = <0x3180000 0x100>; + reg = <0x0 0x3180000 0x0 0x100>; interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; clock-frequency = <400000>; clocks = <&bpmp TEGRA234_CLK_I2C3 @@ -812,16 +716,16 @@ clock-names = "div-clk", "parent"; resets = <&bpmp TEGRA234_RESET_I2C3>; reset-names = "i2c"; - iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; - dma-coherent; dmas = <&gpcdma 23>, <&gpcdma 23>; dma-names = "rx", "tx"; }; dp_aux_ch1_i2c: i2c@3190000 { compatible = "nvidia,tegra194-i2c"; - reg = <0x3190000 0x100>; + reg = <0x0 0x3190000 0x0 0x100>; interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; clock-frequency = <100000>; clocks = <&bpmp TEGRA234_CLK_I2C4 @@ -831,16 +735,16 @@ clock-names = "div-clk", "parent"; resets = <&bpmp TEGRA234_RESET_I2C4>; reset-names = "i2c"; - iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; - dma-coherent; dmas = <&gpcdma 26>, <&gpcdma 26>; dma-names = "rx", "tx"; }; dp_aux_ch0_i2c: i2c@31b0000 { compatible = "nvidia,tegra194-i2c"; - reg = <0x31b0000 0x100>; + reg = <0x0 0x31b0000 0x0 0x100>; interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; clock-frequency = <100000>; clocks = <&bpmp TEGRA234_CLK_I2C6 @@ -850,16 +754,16 @@ clock-names = "div-clk", "parent"; resets = <&bpmp TEGRA234_RESET_I2C6>; reset-names = "i2c"; - iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; - dma-coherent; dmas = <&gpcdma 30>, <&gpcdma 30>; dma-names = "rx", "tx"; }; dp_aux_ch2_i2c: i2c@31c0000 { compatible = "nvidia,tegra194-i2c"; - reg = <0x31c0000 0x100>; + reg = <0x0 0x31c0000 0x0 0x100>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; clock-frequency = <100000>; clocks = <&bpmp TEGRA234_CLK_I2C7 @@ -869,23 +773,23 @@ clock-names = "div-clk", "parent"; resets = <&bpmp TEGRA234_RESET_I2C7>; reset-names = "i2c"; - iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; - dma-coherent; dmas = <&gpcdma 27>, <&gpcdma 27>; dma-names = "rx", "tx"; }; uarti: serial@31d0000 { compatible = "arm,sbsa-uart"; - reg = <0x31d0000 0x10000>; + reg = <0x0 0x31d0000 0x0 0x10000>; interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; dp_aux_ch3_i2c: i2c@31e0000 { compatible = "nvidia,tegra194-i2c"; - reg = <0x31e0000 0x100>; + reg = <0x0 0x31e0000 0x0 0x100>; interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; clock-frequency = <100000>; clocks = <&bpmp TEGRA234_CLK_I2C9 @@ -895,15 +799,13 @@ clock-names = "div-clk", "parent"; resets = <&bpmp TEGRA234_RESET_I2C9>; reset-names = "i2c"; - iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; - dma-coherent; dmas = <&gpcdma 31>, <&gpcdma 31>; dma-names = "rx", "tx"; }; spi@3270000 { compatible = "nvidia,tegra234-qspi"; - reg = <0x3270000 0x1000>; + reg = <0x0 0x3270000 0x0 0x1000>; interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; @@ -916,7 +818,7 @@ pwm1: pwm@3280000 { compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; - reg = <0x3280000 0x10000>; + reg = <0x0 0x3280000 0x0 0x10000>; clocks = <&bpmp TEGRA234_CLK_PWM1>; resets = <&bpmp TEGRA234_RESET_PWM1>; reset-names = "pwm"; @@ -926,7 +828,7 @@ pwm2: pwm@3290000 { compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; - reg = <0x3290000 0x10000>; + reg = <0x0 0x3290000 0x0 0x10000>; clocks = <&bpmp TEGRA234_CLK_PWM2>; resets = <&bpmp TEGRA234_RESET_PWM2>; reset-names = "pwm"; @@ -936,7 +838,7 @@ pwm3: pwm@32a0000 { compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; - reg = <0x32a0000 0x10000>; + reg = <0x0 0x32a0000 0x0 0x10000>; clocks = <&bpmp TEGRA234_CLK_PWM3>; resets = <&bpmp TEGRA234_RESET_PWM3>; reset-names = "pwm"; @@ -946,7 +848,7 @@ pwm5: pwm@32c0000 { compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; - reg = <0x32c0000 0x10000>; + reg = <0x0 0x32c0000 0x0 0x10000>; clocks = <&bpmp TEGRA234_CLK_PWM5>; resets = <&bpmp TEGRA234_RESET_PWM5>; reset-names = "pwm"; @@ -956,7 +858,7 @@ pwm6: pwm@32d0000 { compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; - reg = <0x32d0000 0x10000>; + reg = <0x0 0x32d0000 0x0 0x10000>; clocks = <&bpmp TEGRA234_CLK_PWM6>; resets = <&bpmp TEGRA234_RESET_PWM6>; reset-names = "pwm"; @@ -966,7 +868,7 @@ pwm7: pwm@32e0000 { compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; - reg = <0x32e0000 0x10000>; + reg = <0x0 0x32e0000 0x0 0x10000>; clocks = <&bpmp TEGRA234_CLK_PWM7>; resets = <&bpmp TEGRA234_RESET_PWM7>; reset-names = "pwm"; @@ -976,7 +878,7 @@ pwm8: pwm@32f0000 { compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; - reg = <0x32f0000 0x10000>; + reg = <0x0 0x32f0000 0x0 0x10000>; clocks = <&bpmp TEGRA234_CLK_PWM8>; resets = <&bpmp TEGRA234_RESET_PWM8>; reset-names = "pwm"; @@ -986,7 +888,7 @@ spi@3300000 { compatible = "nvidia,tegra234-qspi"; - reg = <0x3300000 0x1000>; + reg = <0x0 0x3300000 0x0 0x1000>; interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; @@ -999,7 +901,7 @@ mmc@3400000 { compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; - reg = <0x03400000 0x20000>; + reg = <0x0 0x03400000 0x0 0x20000>; interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA234_CLK_SDMMC1>, <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; @@ -1034,7 +936,7 @@ mmc@3460000 { compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; - reg = <0x03460000 0x20000>; + reg = <0x0 0x03460000 0x0 0x20000>; interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA234_CLK_SDMMC4>, <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; @@ -1063,7 +965,7 @@ hda@3510000 { compatible = "nvidia,tegra234-hda"; - reg = <0x3510000 0x10000>; + reg = <0x0 0x3510000 0x0 0x10000>; interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA234_CLK_AZA_BIT>, <&bpmp TEGRA234_CLK_AZA_2XBIT>; @@ -1079,16 +981,184 @@ status = "disabled"; }; + xusb_padctl: padctl@3520000 { + compatible = "nvidia,tegra234-xusb-padctl"; + reg = <0x0 0x03520000 0x0 0x20000>, + <0x0 0x03540000 0x0 0x10000>; + reg-names = "padctl", "ao"; + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; + + resets = <&bpmp TEGRA234_RESET_XUSB_PADCTL>; + reset-names = "padctl"; + + status = "disabled"; + + pads { + usb2 { + clocks = <&bpmp TEGRA234_CLK_USB2_TRK>; + clock-names = "trk"; + + lanes { + usb2-0 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb2-1 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb2-2 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb2-3 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + }; + }; + + usb3 { + lanes { + usb3-0 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb3-1 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb3-2 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb3-3 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + }; + }; + }; + + ports { + usb2-0 { + status = "disabled"; + }; + + usb2-1 { + status = "disabled"; + }; + + usb2-2 { + status = "disabled"; + }; + + usb2-3 { + status = "disabled"; + }; + + usb3-0 { + status = "disabled"; + }; + + usb3-1 { + status = "disabled"; + }; + + usb3-2 { + status = "disabled"; + }; + + usb3-3 { + status = "disabled"; + }; + }; + }; + + usb@3550000 { + compatible = "nvidia,tegra234-xudc"; + reg = <0x0 0x03550000 0x0 0x8000>, + <0x0 0x03558000 0x0 0x8000>; + reg-names = "base", "fpci"; + interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_DEV>, + <&bpmp TEGRA234_CLK_XUSB_CORE_SS>, + <&bpmp TEGRA234_CLK_XUSB_SS>, + <&bpmp TEGRA234_CLK_XUSB_FS>; + clock-names = "dev", "ss", "ss_src", "fs_src"; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_DEVR &emc>, + <&mc TEGRA234_MEMORY_CLIENT_XUSB_DEVW &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu_niso1 TEGRA234_SID_XUSB_DEV>; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBB>, + <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>; + power-domain-names = "dev", "ss"; + nvidia,xusb-padctl = <&xusb_padctl>; + dma-coherent; + status = "disabled"; + }; + + usb@3610000 { + compatible = "nvidia,tegra234-xusb"; + reg = <0x0 0x03610000 0x0 0x40000>, + <0x0 0x03600000 0x0 0x10000>, + <0x0 0x03650000 0x0 0x10000>; + reg-names = "hcd", "fpci", "bar2"; + + interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_HOST>, + <&bpmp TEGRA234_CLK_XUSB_FALCON>, + <&bpmp TEGRA234_CLK_XUSB_CORE_SS>, + <&bpmp TEGRA234_CLK_XUSB_SS>, + <&bpmp TEGRA234_CLK_CLK_M>, + <&bpmp TEGRA234_CLK_XUSB_FS>, + <&bpmp TEGRA234_CLK_UTMIP_PLL>, + <&bpmp TEGRA234_CLK_CLK_M>, + <&bpmp TEGRA234_CLK_PLLE>; + clock-names = "xusb_host", "xusb_falcon_src", + "xusb_ss", "xusb_ss_src", "xusb_hs_src", + "xusb_fs_src", "pll_u_480m", "clk_m", + "pll_e"; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTR &emc>, + <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTW &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu_niso1 TEGRA234_SID_XUSB_HOST>; + + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBC>, + <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>; + power-domain-names = "xusb_host", "xusb_ss"; + + nvidia,xusb-padctl = <&xusb_padctl>; + dma-coherent; + status = "disabled"; + }; + fuse@3810000 { compatible = "nvidia,tegra234-efuse"; - reg = <0x03810000 0x10000>; + reg = <0x0 0x03810000 0x0 0x10000>; clocks = <&bpmp TEGRA234_CLK_FUSE>; clock-names = "fuse"; }; hsp_top0: hsp@3c00000 { compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; - reg = <0x03c00000 0xa0000>; + reg = <0x0 0x03c00000 0x0 0xa0000>; interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, @@ -1106,7 +1176,7 @@ p2u_hsio_0: phy@3e00000 { compatible = "nvidia,tegra234-p2u"; - reg = <0x03e00000 0x10000>; + reg = <0x0 0x03e00000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1114,7 +1184,7 @@ p2u_hsio_1: phy@3e10000 { compatible = "nvidia,tegra234-p2u"; - reg = <0x03e10000 0x10000>; + reg = <0x0 0x03e10000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1122,7 +1192,7 @@ p2u_hsio_2: phy@3e20000 { compatible = "nvidia,tegra234-p2u"; - reg = <0x03e20000 0x10000>; + reg = <0x0 0x03e20000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1130,7 +1200,7 @@ p2u_hsio_3: phy@3e30000 { compatible = "nvidia,tegra234-p2u"; - reg = <0x03e30000 0x10000>; + reg = <0x0 0x03e30000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1138,7 +1208,7 @@ p2u_hsio_4: phy@3e40000 { compatible = "nvidia,tegra234-p2u"; - reg = <0x03e40000 0x10000>; + reg = <0x0 0x03e40000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1146,7 +1216,7 @@ p2u_hsio_5: phy@3e50000 { compatible = "nvidia,tegra234-p2u"; - reg = <0x03e50000 0x10000>; + reg = <0x0 0x03e50000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1154,7 +1224,7 @@ p2u_hsio_6: phy@3e60000 { compatible = "nvidia,tegra234-p2u"; - reg = <0x03e60000 0x10000>; + reg = <0x0 0x03e60000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1162,7 +1232,7 @@ p2u_hsio_7: phy@3e70000 { compatible = "nvidia,tegra234-p2u"; - reg = <0x03e70000 0x10000>; + reg = <0x0 0x03e70000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1170,7 +1240,7 @@ p2u_nvhs_0: phy@3e90000 { compatible = "nvidia,tegra234-p2u"; - reg = <0x03e90000 0x10000>; + reg = <0x0 0x03e90000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1178,7 +1248,7 @@ p2u_nvhs_1: phy@3ea0000 { compatible = "nvidia,tegra234-p2u"; - reg = <0x03ea0000 0x10000>; + reg = <0x0 0x03ea0000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1186,7 +1256,7 @@ p2u_nvhs_2: phy@3eb0000 { compatible = "nvidia,tegra234-p2u"; - reg = <0x03eb0000 0x10000>; + reg = <0x0 0x03eb0000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1194,7 +1264,7 @@ p2u_nvhs_3: phy@3ec0000 { compatible = "nvidia,tegra234-p2u"; - reg = <0x03ec0000 0x10000>; + reg = <0x0 0x03ec0000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1202,7 +1272,7 @@ p2u_nvhs_4: phy@3ed0000 { compatible = "nvidia,tegra234-p2u"; - reg = <0x03ed0000 0x10000>; + reg = <0x0 0x03ed0000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1210,7 +1280,7 @@ p2u_nvhs_5: phy@3ee0000 { compatible = "nvidia,tegra234-p2u"; - reg = <0x03ee0000 0x10000>; + reg = <0x0 0x03ee0000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1218,7 +1288,7 @@ p2u_nvhs_6: phy@3ef0000 { compatible = "nvidia,tegra234-p2u"; - reg = <0x03ef0000 0x10000>; + reg = <0x0 0x03ef0000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1226,7 +1296,7 @@ p2u_nvhs_7: phy@3f00000 { compatible = "nvidia,tegra234-p2u"; - reg = <0x03f00000 0x10000>; + reg = <0x0 0x03f00000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1234,7 +1304,7 @@ p2u_gbe_0: phy@3f20000 { compatible = "nvidia,tegra234-p2u"; - reg = <0x03f20000 0x10000>; + reg = <0x0 0x03f20000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1242,7 +1312,7 @@ p2u_gbe_1: phy@3f30000 { compatible = "nvidia,tegra234-p2u"; - reg = <0x03f30000 0x10000>; + reg = <0x0 0x03f30000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1250,7 +1320,7 @@ p2u_gbe_2: phy@3f40000 { compatible = "nvidia,tegra234-p2u"; - reg = <0x03f40000 0x10000>; + reg = <0x0 0x03f40000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1258,7 +1328,7 @@ p2u_gbe_3: phy@3f50000 { compatible = "nvidia,tegra234-p2u"; - reg = <0x03f50000 0x10000>; + reg = <0x0 0x03f50000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1266,7 +1336,7 @@ p2u_gbe_4: phy@3f60000 { compatible = "nvidia,tegra234-p2u"; - reg = <0x03f60000 0x10000>; + reg = <0x0 0x03f60000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1274,7 +1344,7 @@ p2u_gbe_5: phy@3f70000 { compatible = "nvidia,tegra234-p2u"; - reg = <0x03f70000 0x10000>; + reg = <0x0 0x03f70000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1282,7 +1352,7 @@ p2u_gbe_6: phy@3f80000 { compatible = "nvidia,tegra234-p2u"; - reg = <0x03f80000 0x10000>; + reg = <0x0 0x03f80000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1290,7 +1360,7 @@ p2u_gbe_7: phy@3f90000 { compatible = "nvidia,tegra234-p2u"; - reg = <0x03f90000 0x10000>; + reg = <0x0 0x03f90000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1298,9 +1368,9 @@ ethernet@6800000 { compatible = "nvidia,tegra234-mgbe"; - reg = <0x06800000 0x10000>, - <0x06810000 0x10000>, - <0x068a0000 0x10000>; + reg = <0x0 0x06800000 0x0 0x10000>, + <0x0 0x06810000 0x0 0x10000>, + <0x0 0x068a0000 0x0 0x10000>; reg-names = "hypervisor", "mac", "xpcs"; interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "common"; @@ -1332,9 +1402,9 @@ ethernet@6900000 { compatible = "nvidia,tegra234-mgbe"; - reg = <0x06900000 0x10000>, - <0x06910000 0x10000>, - <0x069a0000 0x10000>; + reg = <0x0 0x06900000 0x0 0x10000>, + <0x0 0x06910000 0x0 0x10000>, + <0x0 0x069a0000 0x0 0x10000>; reg-names = "hypervisor", "mac", "xpcs"; interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "common"; @@ -1366,9 +1436,9 @@ ethernet@6a00000 { compatible = "nvidia,tegra234-mgbe"; - reg = <0x06a00000 0x10000>, - <0x06a10000 0x10000>, - <0x06aa0000 0x10000>; + reg = <0x0 0x06a00000 0x0 0x10000>, + <0x0 0x06a10000 0x0 0x10000>, + <0x0 0x06aa0000 0x0 0x10000>; reg-names = "hypervisor", "mac", "xpcs"; interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "common"; @@ -1400,9 +1470,9 @@ ethernet@6b00000 { compatible = "nvidia,tegra234-mgbe"; - reg = <0x06b00000 0x10000>, - <0x06b10000 0x10000>, - <0x06ba0000 0x10000>; + reg = <0x0 0x06b00000 0x0 0x10000>, + <0x0 0x06b10000 0x0 0x10000>, + <0x0 0x06ba0000 0x0 0x10000>; reg-names = "hypervisor", "mac", "xpcs"; interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "common"; @@ -1434,8 +1504,8 @@ smmu_niso1: iommu@8000000 { compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; - reg = <0x8000000 0x1000000>, - <0x7000000 0x1000000>; + reg = <0x0 0x8000000 0x0 0x1000000>, + <0x0 0x7000000 0x0 0x1000000>; interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, @@ -1576,21 +1646,21 @@ sce-fabric@b600000 { compatible = "nvidia,tegra234-sce-fabric"; - reg = <0xb600000 0x40000>; + reg = <0x0 0xb600000 0x0 0x40000>; interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; status = "okay"; }; rce-fabric@be00000 { compatible = "nvidia,tegra234-rce-fabric"; - reg = <0xbe00000 0x40000>; + reg = <0x0 0xbe00000 0x0 0x40000>; interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; status = "okay"; }; hsp_aon: hsp@c150000 { compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; - reg = <0x0c150000 0x90000>; + reg = <0x0 0x0c150000 0x0 0x90000>; interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, @@ -1605,8 +1675,10 @@ gen2_i2c: i2c@c240000 { compatible = "nvidia,tegra194-i2c"; - reg = <0xc240000 0x100>; + reg = <0x0 0xc240000 0x0 0x100>; interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; clock-frequency = <100000>; clocks = <&bpmp TEGRA234_CLK_I2C2 @@ -1616,16 +1688,16 @@ assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; resets = <&bpmp TEGRA234_RESET_I2C2>; reset-names = "i2c"; - iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; - dma-coherent; dmas = <&gpcdma 22>, <&gpcdma 22>; dma-names = "rx", "tx"; }; gen8_i2c: i2c@c250000 { compatible = "nvidia,tegra194-i2c"; - reg = <0xc250000 0x100>; + reg = <0x0 0xc250000 0x0 0x100>; interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; clock-frequency = <400000>; clocks = <&bpmp TEGRA234_CLK_I2C8 @@ -1635,15 +1707,13 @@ assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; resets = <&bpmp TEGRA234_RESET_I2C8>; reset-names = "i2c"; - iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; - dma-coherent; dmas = <&gpcdma 0>, <&gpcdma 0>; dma-names = "rx", "tx"; }; rtc@c2a0000 { compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc"; - reg = <0x0c2a0000 0x10000>; + reg = <0x0 0x0c2a0000 0x0 0x10000>; interrupt-parent = <&pmc>; interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA234_CLK_CLK_32K>; @@ -1654,8 +1724,8 @@ gpio_aon: gpio@c2f0000 { compatible = "nvidia,tegra234-gpio-aon"; reg-names = "security", "gpio"; - reg = <0x0c2f0000 0x1000>, - <0x0c2f1000 0x1000>; + reg = <0x0 0x0c2f0000 0x0 0x1000>, + <0x0 0x0c2f1000 0x0 0x1000>; interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, @@ -1668,7 +1738,7 @@ pwm4: pwm@c340000 { compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; - reg = <0xc340000 0x10000>; + reg = <0x0 0xc340000 0x0 0x10000>; clocks = <&bpmp TEGRA234_CLK_PWM4>; resets = <&bpmp TEGRA234_RESET_PWM4>; reset-names = "pwm"; @@ -1678,28 +1748,23 @@ pmc: pmc@c360000 { compatible = "nvidia,tegra234-pmc"; - reg = <0x0c360000 0x10000>, - <0x0c370000 0x10000>, - <0x0c380000 0x10000>, - <0x0c390000 0x10000>, - <0x0c3a0000 0x10000>; + reg = <0x0 0x0c360000 0x0 0x10000>, + <0x0 0x0c370000 0x0 0x10000>, + <0x0 0x0c380000 0x0 0x10000>, + <0x0 0x0c390000 0x0 0x10000>, + <0x0 0x0c3a0000 0x0 0x10000>; reg-names = "pmc", "wake", "aotag", "scratch", "misc"; #interrupt-cells = <2>; interrupt-controller; - sdmmc1_3v3: sdmmc1-3v3 { - pins = "sdmmc1-hv"; - power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; - }; - sdmmc1_1v8: sdmmc1-1v8 { pins = "sdmmc1-hv"; power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; }; - sdmmc3_3v3: sdmmc3-3v3 { - pins = "sdmmc3-hv"; + sdmmc1_3v3: sdmmc1-3v3 { + pins = "sdmmc1-hv"; power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; }; @@ -1707,33 +1772,45 @@ pins = "sdmmc3-hv"; power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; }; + + sdmmc3_3v3: sdmmc3-3v3 { + pins = "sdmmc3-hv"; + power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; + }; }; aon-fabric@c600000 { compatible = "nvidia,tegra234-aon-fabric"; - reg = <0xc600000 0x40000>; + reg = <0x0 0xc600000 0x0 0x40000>; interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; status = "okay"; }; bpmp-fabric@d600000 { compatible = "nvidia,tegra234-bpmp-fabric"; - reg = <0xd600000 0x40000>; + reg = <0x0 0xd600000 0x0 0x40000>; interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; status = "okay"; }; dce-fabric@de00000 { compatible = "nvidia,tegra234-sce-fabric"; - reg = <0xde00000 0x40000>; + reg = <0x0 0xde00000 0x0 0x40000>; interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>; status = "okay"; }; + ccplex@e000000 { + compatible = "nvidia,tegra234-ccplex-cluster"; + reg = <0x0 0x0e000000 0x0 0x5ffff>; + nvidia,bpmp = <&bpmp>; + status = "okay"; + }; + gic: interrupt-controller@f400000 { compatible = "arm,gic-v3"; - reg = <0x0f400000 0x010000>, /* GICD */ - <0x0f440000 0x200000>; /* GICR */ + reg = <0x0 0x0f400000 0x0 0x010000>, /* GICD */ + <0x0 0x0f440000 0x0 0x200000>; /* GICR */ interrupt-parent = <&gic>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; @@ -1744,7 +1821,7 @@ smmu_iso: iommu@10000000 { compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; - reg = <0x10000000 0x1000000>; + reg = <0x0 0x10000000 0x0 0x1000000>; interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, @@ -1884,8 +1961,8 @@ smmu_niso0: iommu@12000000 { compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; - reg = <0x12000000 0x1000000>, - <0x11000000 0x1000000>; + reg = <0x0 0x12000000 0x0 0x1000000>, + <0x0 0x11000000 0x0 0x1000000>; interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, @@ -2026,771 +2103,867 @@ cbb-fabric@13a00000 { compatible = "nvidia,tegra234-cbb-fabric"; - reg = <0x13a00000 0x400000>; + reg = <0x0 0x13a00000 0x0 0x400000>; interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; status = "okay"; }; - }; - ccplex@e000000 { - compatible = "nvidia,tegra234-ccplex-cluster"; - reg = <0x0 0x0e000000 0x0 0x5ffff>; - nvidia,bpmp = <&bpmp>; - status = "okay"; - }; + host1x@13e00000 { + compatible = "nvidia,tegra234-host1x"; + reg = <0x0 0x13e00000 0x0 0x10000>, + <0x0 0x13e10000 0x0 0x10000>, + <0x0 0x13e40000 0x0 0x10000>; + reg-names = "common", "hypervisor", "vm"; + interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "syncpt0", "syncpt1", "syncpt2", "syncpt3", "syncpt4", + "syncpt5", "syncpt6", "syncpt7", "host1x"; + clocks = <&bpmp TEGRA234_CLK_HOST1X>; + clock-names = "host1x"; - pcie@140a0000 { - compatible = "nvidia,tegra234-pcie"; - power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CA>; - reg = <0x00 0x140a0000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x2a000000 0x0 0x00040000>, /* configuration space (256K) */ - <0x00 0x2a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x2a080000 0x0 0x00040000>, /* DBI reg space (256K) */ - <0x35 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ - reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <4>; - num-viewport = <8>; - linux,pci-domain = <8>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x14800000 0x0 0x14800000 0x0 0x02000000>; + + interconnects = <&mc TEGRA234_MEMORY_CLIENT_HOST1XDMAR &emc>; + interconnect-names = "dma-mem"; + iommus = <&smmu_niso1 TEGRA234_SID_HOST1X>; + dma-coherent; + + /* Context isolation domains */ + iommu-map = <0 &smmu_niso0 TEGRA234_SID_HOST1X_CTX0 1>, + <1 &smmu_niso0 TEGRA234_SID_HOST1X_CTX1 1>, + <2 &smmu_niso0 TEGRA234_SID_HOST1X_CTX2 1>, + <3 &smmu_niso0 TEGRA234_SID_HOST1X_CTX3 1>, + <4 &smmu_niso0 TEGRA234_SID_HOST1X_CTX4 1>, + <5 &smmu_niso0 TEGRA234_SID_HOST1X_CTX5 1>, + <6 &smmu_niso0 TEGRA234_SID_HOST1X_CTX6 1>, + <7 &smmu_niso0 TEGRA234_SID_HOST1X_CTX7 1>, + <8 &smmu_niso1 TEGRA234_SID_HOST1X_CTX0 1>, + <9 &smmu_niso1 TEGRA234_SID_HOST1X_CTX1 1>, + <10 &smmu_niso1 TEGRA234_SID_HOST1X_CTX2 1>, + <11 &smmu_niso1 TEGRA234_SID_HOST1X_CTX3 1>, + <12 &smmu_niso1 TEGRA234_SID_HOST1X_CTX4 1>, + <13 &smmu_niso1 TEGRA234_SID_HOST1X_CTX5 1>, + <14 &smmu_niso1 TEGRA234_SID_HOST1X_CTX6 1>, + <15 &smmu_niso1 TEGRA234_SID_HOST1X_CTX7 1>; + + vic@15340000 { + compatible = "nvidia,tegra234-vic"; + reg = <0x0 0x15340000 0x0 0x00040000>; + interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bpmp TEGRA234_CLK_VIC>; + clock-names = "vic"; + resets = <&bpmp TEGRA234_RESET_VIC>; + reset-names = "vic"; + + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_VIC>; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_VICSRD &emc>, + <&mc TEGRA234_MEMORY_CLIENT_VICSWR &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu_niso1 TEGRA234_SID_VIC>; + dma-coherent; + }; + + nvdec@15480000 { + compatible = "nvidia,tegra234-nvdec"; + reg = <0x0 0x15480000 0x0 0x00040000>; + clocks = <&bpmp TEGRA234_CLK_NVDEC>, + <&bpmp TEGRA234_CLK_FUSE>, + <&bpmp TEGRA234_CLK_TSEC_PKA>; + clock-names = "nvdec", "fuse", "tsec_pka"; + resets = <&bpmp TEGRA234_RESET_NVDEC>; + reset-names = "nvdec"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>, + <&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu_niso1 TEGRA234_SID_NVDEC>; + dma-coherent; - clocks = <&bpmp TEGRA234_CLK_PEX2_C8_CORE>; - clock-names = "core"; + nvidia,memory-controller = <&mc>; - resets = <&bpmp TEGRA234_RESET_PEX2_CORE_8_APB>, - <&bpmp TEGRA234_RESET_PEX2_CORE_8>; - reset-names = "apb", "core"; + /* + * Placeholder values that firmware needs to update with the real + * offsets parsed from the microcode headers. + */ + nvidia,bl-manifest-offset = <0>; + nvidia,bl-data-offset = <0>; + nvidia,bl-code-offset = <0>; + nvidia,os-manifest-offset = <0>; + nvidia,os-data-offset = <0>; + nvidia,os-code-offset = <0>; - interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ - <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ - interrupt-names = "intr", "msi"; + /* + * Firmware needs to set this to "okay" once the above values have + * been updated. + */ + status = "disabled"; + }; + }; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + pcie@140a0000 { + compatible = "nvidia,tegra234-pcie"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CA>; + reg = <0x00 0x140a0000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x2a000000 0x0 0x00040000>, /* configuration space (256K) */ + <0x00 0x2a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x2a080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x35 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; - nvidia,bpmp = <&bpmp 8>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + num-viewport = <8>; + linux,pci-domain = <8>; - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; + clocks = <&bpmp TEGRA234_CLK_PEX2_C8_CORE>; + clock-names = "core"; - bus-range = <0x0 0xff>; + resets = <&bpmp TEGRA234_RESET_PEX2_CORE_8_APB>, + <&bpmp TEGRA234_RESET_PEX2_CORE_8>; + reset-names = "apb", "core"; - ranges = <0x43000000 0x32 0x40000000 0x32 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ - <0x02000000 0x0 0x40000000 0x35 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ - <0x01000000 0x0 0x2a100000 0x00 0x2a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; - interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE8AR &emc>, - <&mc TEGRA234_MEMORY_CLIENT_PCIE8AW &emc>; - interconnect-names = "dma-mem", "write"; - iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE8 0x1000>; - iommu-map-mask = <0x0>; - dma-coherent; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; + nvidia,bpmp = <&bpmp 8>; - pcie@140c0000 { - compatible = "nvidia,tegra234-pcie"; - power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CB>; - reg = <0x00 0x140c0000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x2c000000 0x0 0x00040000>, /* configuration space (256K) */ - <0x00 0x2c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x2c080000 0x0 0x00040000>, /* DBI reg space (256K) */ - <0x38 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ - reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <4>; - num-viewport = <8>; - linux,pci-domain = <9>; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; + + bus-range = <0x0 0xff>; - clocks = <&bpmp TEGRA234_CLK_PEX2_C9_CORE>; - clock-names = "core"; + ranges = <0x43000000 0x32 0x40000000 0x32 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ + <0x02000000 0x0 0x40000000 0x35 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ + <0x01000000 0x0 0x2a100000 0x00 0x2a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ + + interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE8AR &emc>, + <&mc TEGRA234_MEMORY_CLIENT_PCIE8AW &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE8 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; - resets = <&bpmp TEGRA234_RESET_PEX2_CORE_9_APB>, - <&bpmp TEGRA234_RESET_PEX2_CORE_9>; - reset-names = "apb", "core"; + status = "disabled"; + }; - interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ - <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ - interrupt-names = "intr", "msi"; + pcie@140c0000 { + compatible = "nvidia,tegra234-pcie"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CB>; + reg = <0x00 0x140c0000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x2c000000 0x0 0x00040000>, /* configuration space (256K) */ + <0x00 0x2c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x2c080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x38 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + num-viewport = <8>; + linux,pci-domain = <9>; - nvidia,bpmp = <&bpmp 9>; + clocks = <&bpmp TEGRA234_CLK_PEX2_C9_CORE>; + clock-names = "core"; - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; + resets = <&bpmp TEGRA234_RESET_PEX2_CORE_9_APB>, + <&bpmp TEGRA234_RESET_PEX2_CORE_9>; + reset-names = "apb", "core"; - bus-range = <0x0 0xff>; + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; - ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xc0000000>, /* prefetchable memory (11264 MB) */ - <0x02000000 0x0 0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ - <0x01000000 0x0 0x2c100000 0x00 0x2c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; - interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE9AR &emc>, - <&mc TEGRA234_MEMORY_CLIENT_PCIE9AW &emc>; - interconnect-names = "dma-mem", "write"; - iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE9 0x1000>; - iommu-map-mask = <0x0>; - dma-coherent; + nvidia,bpmp = <&bpmp 9>; - status = "disabled"; - }; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; - pcie@140e0000 { - compatible = "nvidia,tegra234-pcie"; - power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; - reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x2e000000 0x0 0x00040000>, /* configuration space (256K) */ - <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x2e080000 0x0 0x00040000>, /* DBI reg space (256K) */ - <0x3b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ - reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <4>; - num-viewport = <8>; - linux,pci-domain = <10>; + bus-range = <0x0 0xff>; - clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; - clock-names = "core"; + ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xc0000000>, /* prefetchable memory (11264 MB) */ + <0x02000000 0x0 0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ + <0x01000000 0x0 0x2c100000 0x00 0x2c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ - resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, - <&bpmp TEGRA234_RESET_PEX2_CORE_10>; - reset-names = "apb", "core"; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE9AR &emc>, + <&mc TEGRA234_MEMORY_CLIENT_PCIE9AW &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE9 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; - interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ - <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ - interrupt-names = "intr", "msi"; + status = "disabled"; + }; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; + pcie@140e0000 { + compatible = "nvidia,tegra234-pcie"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; + reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x2e000000 0x0 0x00040000>, /* configuration space (256K) */ + <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x2e080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x3b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; - nvidia,bpmp = <&bpmp 10>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + num-viewport = <8>; + linux,pci-domain = <10>; - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; + clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; + clock-names = "core"; - bus-range = <0x0 0xff>; + resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, + <&bpmp TEGRA234_RESET_PEX2_CORE_10>; + reset-names = "apb", "core"; - ranges = <0x43000000 0x38 0x40000000 0x38 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ - <0x02000000 0x0 0x40000000 0x3b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ - <0x01000000 0x0 0x2e100000 0x00 0x2e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ + interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; - interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, - <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; - interconnect-names = "dma-mem", "write"; - iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>; - iommu-map-mask = <0x0>; - dma-coherent; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; + nvidia,bpmp = <&bpmp 10>; - pcie@14100000 { - compatible = "nvidia,tegra234-pcie"; - power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; - reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ - <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x30080000 0x0 0x00040000>, /* DBI reg space (256K) */ - <0x20 0xb0000000 0x0 0x10000000>; /* ECAM (256MB) */ - reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <1>; - num-viewport = <8>; - linux,pci-domain = <1>; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; - clocks = <&bpmp TEGRA234_CLK_PEX0_C1_CORE>; - clock-names = "core"; + bus-range = <0x0 0xff>; - resets = <&bpmp TEGRA234_RESET_PEX0_CORE_1_APB>, - <&bpmp TEGRA234_RESET_PEX0_CORE_1>; - reset-names = "apb", "core"; + ranges = <0x43000000 0x38 0x40000000 0x38 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ + <0x02000000 0x0 0x40000000 0x3b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ + <0x01000000 0x0 0x2e100000 0x00 0x2e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ - interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ - <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ - interrupt-names = "intr", "msi"; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, + <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; - nvidia,bpmp = <&bpmp 1>; + pcie-ep@140e0000 { + compatible = "nvidia,tegra234-pcie-ep"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; + reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x2e080000 0x0 0x00040000>, /* DBI space (256K) */ + <0x38 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ + reg-names = "appl", "atu_dma", "dbi", "addr_space"; - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; + num-lanes = <4>; - bus-range = <0x0 0xff>; + clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; + clock-names = "core"; - ranges = <0x43000000 0x20 0x80000000 0x20 0x80000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ - <0x02000000 0x0 0x40000000 0x20 0xa8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ - <0x01000000 0x0 0x30100000 0x00 0x30100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ + resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, + <&bpmp TEGRA234_RESET_PEX2_CORE_10>; + reset-names = "apb", "core"; - interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE1R &emc>, - <&mc TEGRA234_MEMORY_CLIENT_PCIE1W &emc>; - interconnect-names = "dma-mem", "write"; - iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE1 0x1000>; - iommu-map-mask = <0x0>; - dma-coherent; + interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ + interrupt-names = "intr"; - status = "disabled"; - }; + nvidia,bpmp = <&bpmp 10>; - pcie@14120000 { - compatible = "nvidia,tegra234-pcie"; - power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; - reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ - <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x32080000 0x0 0x00040000>, /* DBI reg space (256K) */ - <0x20 0xf0000000 0x0 0x10000000>; /* ECAM (256MB) */ - reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <1>; - num-viewport = <8>; - linux,pci-domain = <2>; + nvidia,enable-ext-refclk; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; - clocks = <&bpmp TEGRA234_CLK_PEX0_C2_CORE>; - clock-names = "core"; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, + <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; - resets = <&bpmp TEGRA234_RESET_PEX0_CORE_2_APB>, - <&bpmp TEGRA234_RESET_PEX0_CORE_2>; - reset-names = "apb", "core"; + status = "disabled"; + }; - interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ - <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ - interrupt-names = "intr", "msi"; + pcie@14100000 { + compatible = "nvidia,tegra234-pcie"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; + reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ + <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x30080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x20 0xb0000000 0x0 0x10000000>; /* ECAM (256MB) */ + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <1>; + num-viewport = <8>; + linux,pci-domain = <1>; - nvidia,bpmp = <&bpmp 2>; + clocks = <&bpmp TEGRA234_CLK_PEX0_C1_CORE>; + clock-names = "core"; - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; + resets = <&bpmp TEGRA234_RESET_PEX0_CORE_1_APB>, + <&bpmp TEGRA234_RESET_PEX0_CORE_1>; + reset-names = "apb", "core"; - bus-range = <0x0 0xff>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; - ranges = <0x43000000 0x20 0xc0000000 0x20 0xc0000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ - <0x02000000 0x0 0x40000000 0x20 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ - <0x01000000 0x0 0x32100000 0x00 0x32100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; - interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE2AR &emc>, - <&mc TEGRA234_MEMORY_CLIENT_PCIE2AW &emc>; - interconnect-names = "dma-mem", "write"; - iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE2 0x1000>; - iommu-map-mask = <0x0>; - dma-coherent; + nvidia,bpmp = <&bpmp 1>; - status = "disabled"; - }; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; - pcie@14140000 { - compatible = "nvidia,tegra234-pcie"; - power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; - reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ - <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x34080000 0x0 0x00040000>, /* DBI reg space (256K) */ - <0x21 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ - reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <1>; - num-viewport = <8>; - linux,pci-domain = <3>; + bus-range = <0x0 0xff>; - clocks = <&bpmp TEGRA234_CLK_PEX0_C3_CORE>; - clock-names = "core"; + ranges = <0x43000000 0x20 0x80000000 0x20 0x80000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ + <0x02000000 0x0 0x40000000 0x20 0xa8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ + <0x01000000 0x0 0x30100000 0x00 0x30100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ - resets = <&bpmp TEGRA234_RESET_PEX0_CORE_3_APB>, - <&bpmp TEGRA234_RESET_PEX0_CORE_3>; - reset-names = "apb", "core"; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE1R &emc>, + <&mc TEGRA234_MEMORY_CLIENT_PCIE1W &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE1 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; - interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ - <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ - interrupt-names = "intr", "msi"; + status = "disabled"; + }; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + pcie@14120000 { + compatible = "nvidia,tegra234-pcie"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; + reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ + <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x32080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x20 0xf0000000 0x0 0x10000000>; /* ECAM (256MB) */ + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; - nvidia,bpmp = <&bpmp 3>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <1>; + num-viewport = <8>; + linux,pci-domain = <2>; - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; + clocks = <&bpmp TEGRA234_CLK_PEX0_C2_CORE>; + clock-names = "core"; - bus-range = <0x0 0xff>; + resets = <&bpmp TEGRA234_RESET_PEX0_CORE_2_APB>, + <&bpmp TEGRA234_RESET_PEX0_CORE_2>; + reset-names = "apb", "core"; - ranges = <0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ - <0x02000000 0x0 0x40000000 0x21 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ - <0x01000000 0x0 0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; - interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE3R &emc>, - <&mc TEGRA234_MEMORY_CLIENT_PCIE3W &emc>; - interconnect-names = "dma-mem", "write"; - iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE3 0x1000>; - iommu-map-mask = <0x0>; - dma-coherent; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; + nvidia,bpmp = <&bpmp 2>; - pcie@14160000 { - compatible = "nvidia,tegra234-pcie"; - power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>; - reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ - <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ - <0x24 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ - reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <4>; - num-viewport = <8>; - linux,pci-domain = <4>; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; - clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>; - clock-names = "core"; + bus-range = <0x0 0xff>; - resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>, - <&bpmp TEGRA234_RESET_PEX0_CORE_4>; - reset-names = "apb", "core"; + ranges = <0x43000000 0x20 0xc0000000 0x20 0xc0000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ + <0x02000000 0x0 0x40000000 0x20 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ + <0x01000000 0x0 0x32100000 0x00 0x32100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ - interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ - <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ - interrupt-names = "intr", "msi"; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE2AR &emc>, + <&mc TEGRA234_MEMORY_CLIENT_PCIE2AW &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE2 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; - nvidia,bpmp = <&bpmp 4>; + pcie@14140000 { + compatible = "nvidia,tegra234-pcie"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; + reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ + <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x34080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x21 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <1>; + num-viewport = <8>; + linux,pci-domain = <3>; - bus-range = <0x0 0xff>; + clocks = <&bpmp TEGRA234_CLK_PEX0_C3_CORE>; + clock-names = "core"; - ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ - <0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ - <0x01000000 0x0 0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ + resets = <&bpmp TEGRA234_RESET_PEX0_CORE_3_APB>, + <&bpmp TEGRA234_RESET_PEX0_CORE_3>; + reset-names = "apb", "core"; - interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>, - <&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>; - interconnect-names = "dma-mem", "write"; - iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE4 0x1000>; - iommu-map-mask = <0x0>; - dma-coherent; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; - status = "disabled"; - }; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; - pcie@14180000 { - compatible = "nvidia,tegra234-pcie"; - power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BA>; - reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ - <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ - <0x27 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ - reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <4>; - num-viewport = <8>; - linux,pci-domain = <0>; + nvidia,bpmp = <&bpmp 3>; - clocks = <&bpmp TEGRA234_CLK_PEX0_C0_CORE>; - clock-names = "core"; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; - resets = <&bpmp TEGRA234_RESET_PEX0_CORE_0_APB>, - <&bpmp TEGRA234_RESET_PEX0_CORE_0>; - reset-names = "apb", "core"; + bus-range = <0x0 0xff>; - interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ - <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ - interrupt-names = "intr", "msi"; + ranges = <0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ + <0x02000000 0x0 0x40000000 0x21 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ + <0x01000000 0x0 0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE3R &emc>, + <&mc TEGRA234_MEMORY_CLIENT_PCIE3W &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE3 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; - nvidia,bpmp = <&bpmp 0>; + status = "disabled"; + }; - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; + pcie@14160000 { + compatible = "nvidia,tegra234-pcie"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>; + reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ + <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x24 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; - bus-range = <0x0 0xff>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + num-viewport = <8>; + linux,pci-domain = <4>; - ranges = <0x43000000 0x24 0x40000000 0x24 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ - <0x02000000 0x0 0x40000000 0x27 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ - <0x01000000 0x0 0x38100000 0x00 0x38100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ + clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>; + clock-names = "core"; - interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE0R &emc>, - <&mc TEGRA234_MEMORY_CLIENT_PCIE0W &emc>; - interconnect-names = "dma-mem", "write"; - iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE0 0x1000>; - iommu-map-mask = <0x0>; - dma-coherent; + resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>, + <&bpmp TEGRA234_RESET_PEX0_CORE_4>; + reset-names = "apb", "core"; - status = "disabled"; - }; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; - pcie@141a0000 { - compatible = "nvidia,tegra234-pcie"; - power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; - reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ - <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ - <0x2b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ - reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <8>; - num-viewport = <8>; - linux,pci-domain = <5>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; - clock-names = "core"; + nvidia,bpmp = <&bpmp 4>; - resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, - <&bpmp TEGRA234_RESET_PEX1_CORE_5>; - reset-names = "apb", "core"; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; - interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ - <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ - interrupt-names = "intr", "msi"; + bus-range = <0x0 0xff>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ + <0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ + <0x01000000 0x0 0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ - nvidia,bpmp = <&bpmp 5>; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>, + <&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE4 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; + status = "disabled"; + }; - bus-range = <0x0 0xff>; + pcie@14180000 { + compatible = "nvidia,tegra234-pcie"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BA>; + reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ + <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x27 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; - ranges = <0x43000000 0x28 0x00000000 0x28 0x00000000 0x3 0x28000000>, /* prefetchable memory (12928 MB) */ - <0x02000000 0x0 0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ - <0x01000000 0x0 0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + num-viewport = <8>; + linux,pci-domain = <0>; - interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, - <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; - interconnect-names = "dma-mem", "write"; - iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>; - iommu-map-mask = <0x0>; - dma-coherent; + clocks = <&bpmp TEGRA234_CLK_PEX0_C0_CORE>; + clock-names = "core"; - status = "disabled"; - }; + resets = <&bpmp TEGRA234_RESET_PEX0_CORE_0_APB>, + <&bpmp TEGRA234_RESET_PEX0_CORE_0>; + reset-names = "apb", "core"; - pcie@141c0000 { - compatible = "nvidia,tegra234-pcie"; - power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; - reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x3c000000 0x0 0x00040000>, /* configuration space (256K) */ - <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x3c080000 0x0 0x00040000>, /* DBI reg space (256K) */ - <0x2e 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ - reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <4>; - num-viewport = <8>; - linux,pci-domain = <6>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; - clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; - clock-names = "core"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; - resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, - <&bpmp TEGRA234_RESET_PEX1_CORE_6>; - reset-names = "apb", "core"; + nvidia,bpmp = <&bpmp 0>; - interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ - <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ - interrupt-names = "intr", "msi"; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; + bus-range = <0x0 0xff>; - nvidia,bpmp = <&bpmp 6>; + ranges = <0x43000000 0x24 0x40000000 0x24 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ + <0x02000000 0x0 0x40000000 0x27 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ + <0x01000000 0x0 0x38100000 0x00 0x38100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE0R &emc>, + <&mc TEGRA234_MEMORY_CLIENT_PCIE0W &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE0 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; - bus-range = <0x0 0xff>; + status = "disabled"; + }; - ranges = <0x43000000 0x2b 0x40000000 0x2b 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ - <0x02000000 0x0 0x40000000 0x2e 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ - <0x01000000 0x0 0x3c100000 0x00 0x3c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ + pcie@141a0000 { + compatible = "nvidia,tegra234-pcie"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; + reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ + <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x2b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; - interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, - <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; - interconnect-names = "dma-mem", "write"; - iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>; - iommu-map-mask = <0x0>; - dma-coherent; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <8>; + num-viewport = <8>; + linux,pci-domain = <5>; - status = "disabled"; - }; + clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; + clock-names = "core"; - pcie@141e0000 { - compatible = "nvidia,tegra234-pcie"; - power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; - reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x3e000000 0x0 0x00040000>, /* configuration space (256K) */ - <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x3e080000 0x0 0x00040000>, /* DBI reg space (256K) */ - <0x32 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ - reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <8>; - num-viewport = <8>; - linux,pci-domain = <7>; + resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, + <&bpmp TEGRA234_RESET_PEX1_CORE_5>; + reset-names = "apb", "core"; - clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; - clock-names = "core"; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; - resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, - <&bpmp TEGRA234_RESET_PEX2_CORE_7>; - reset-names = "apb", "core"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; - interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ - <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ - interrupt-names = "intr", "msi"; + nvidia,bpmp = <&bpmp 5>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; - nvidia,bpmp = <&bpmp 7>; + bus-range = <0x0 0xff>; - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; + ranges = <0x43000000 0x28 0x00000000 0x28 0x00000000 0x3 0x28000000>, /* prefetchable memory (12928 MB) */ + <0x02000000 0x0 0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ + <0x01000000 0x0 0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ - bus-range = <0x0 0xff>; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, + <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; - ranges = <0x43000000 0x30 0x00000000 0x30 0x00000000 0x2 0x28000000>, /* prefetchable memory (8832 MB) */ - <0x02000000 0x0 0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ - <0x01000000 0x0 0x3e100000 0x00 0x3e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ + status = "disabled"; + }; - interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, - <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; - interconnect-names = "dma-mem", "write"; - iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>; - iommu-map-mask = <0x0>; - dma-coherent; + pcie-ep@141a0000 { + compatible = "nvidia,tegra234-pcie-ep"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; + reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ + reg-names = "appl", "atu_dma", "dbi", "addr_space"; - status = "disabled"; - }; + num-lanes = <8>; - pcie-ep@141a0000 { - compatible = "nvidia,tegra234-pcie-ep"; - power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; - reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ - <0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ - reg-names = "appl", "atu_dma", "dbi", "addr_space"; + clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; + clock-names = "core"; - num-lanes = <8>; + resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, + <&bpmp TEGRA234_RESET_PEX1_CORE_5>; + reset-names = "apb", "core"; - clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; - clock-names = "core"; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ + interrupt-names = "intr"; - resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, - <&bpmp TEGRA234_RESET_PEX1_CORE_5>; - reset-names = "apb", "core"; + nvidia,bpmp = <&bpmp 5>; - interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ - interrupt-names = "intr"; + nvidia,enable-ext-refclk; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; - nvidia,bpmp = <&bpmp 5>; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, + <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; - nvidia,enable-ext-refclk; - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; + status = "disabled"; + }; - interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, - <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; - interconnect-names = "dma-mem", "write"; - iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>; - iommu-map-mask = <0x0>; - dma-coherent; + pcie@141c0000 { + compatible = "nvidia,tegra234-pcie"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; + reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x3c000000 0x0 0x00040000>, /* configuration space (256K) */ + <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x3c080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x2e 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; - status = "disabled"; - }; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + num-viewport = <8>; + linux,pci-domain = <6>; - pcie-ep@141c0000{ - compatible = "nvidia,tegra234-pcie-ep"; - power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; - reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x3c080000 0x0 0x00040000>, /* DBI space (256K) */ - <0x2b 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ - reg-names = "appl", "atu_dma", "dbi", "addr_space"; + clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; + clock-names = "core"; - num-lanes = <4>; + resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, + <&bpmp TEGRA234_RESET_PEX1_CORE_6>; + reset-names = "apb", "core"; - clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; - clock-names = "core"; + interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; - resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, - <&bpmp TEGRA234_RESET_PEX1_CORE_6>; - reset-names = "apb", "core"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; - interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ - interrupt-names = "intr"; + nvidia,bpmp = <&bpmp 6>; - nvidia,bpmp = <&bpmp 6>; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; - nvidia,enable-ext-refclk; - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; + bus-range = <0x0 0xff>; - interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, - <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; - interconnect-names = "dma-mem", "write"; - iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>; - iommu-map-mask = <0x0>; - dma-coherent; + ranges = <0x43000000 0x2b 0x40000000 0x2b 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ + <0x02000000 0x0 0x40000000 0x2e 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ + <0x01000000 0x0 0x3c100000 0x00 0x3c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ - status = "disabled"; - }; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, + <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; - pcie-ep@141e0000{ - compatible = "nvidia,tegra234-pcie-ep"; - power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; - reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x3e080000 0x0 0x00040000>, /* DBI space (256K) */ - <0x2e 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ - reg-names = "appl", "atu_dma", "dbi", "addr_space"; + status = "disabled"; + }; - num-lanes = <8>; + pcie-ep@141c0000 { + compatible = "nvidia,tegra234-pcie-ep"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; + reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x3c080000 0x0 0x00040000>, /* DBI space (256K) */ + <0x2b 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ + reg-names = "appl", "atu_dma", "dbi", "addr_space"; - clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; - clock-names = "core"; + num-lanes = <4>; - resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, - <&bpmp TEGRA234_RESET_PEX2_CORE_7>; - reset-names = "apb", "core"; + clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; + clock-names = "core"; - interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ - interrupt-names = "intr"; + resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, + <&bpmp TEGRA234_RESET_PEX1_CORE_6>; + reset-names = "apb", "core"; - nvidia,bpmp = <&bpmp 7>; + interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ + interrupt-names = "intr"; - nvidia,enable-ext-refclk; - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; + nvidia,bpmp = <&bpmp 6>; - interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, - <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; - interconnect-names = "dma-mem", "write"; - iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>; - iommu-map-mask = <0x0>; - dma-coherent; + nvidia,enable-ext-refclk; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; - status = "disabled"; - }; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, + <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; - pcie-ep@140e0000{ - compatible = "nvidia,tegra234-pcie-ep"; - power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; - reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x2e080000 0x0 0x00040000>, /* DBI space (256K) */ - <0x38 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ - reg-names = "appl", "atu_dma", "dbi", "addr_space"; + status = "disabled"; + }; - num-lanes = <4>; + pcie@141e0000 { + compatible = "nvidia,tegra234-pcie"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; + reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x3e000000 0x0 0x00040000>, /* configuration space (256K) */ + <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x3e080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x32 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; - clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; - clock-names = "core"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <8>; + num-viewport = <8>; + linux,pci-domain = <7>; - resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, - <&bpmp TEGRA234_RESET_PEX2_CORE_10>; - reset-names = "apb", "core"; + clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; + clock-names = "core"; - interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ - interrupt-names = "intr"; + resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, + <&bpmp TEGRA234_RESET_PEX2_CORE_7>; + reset-names = "apb", "core"; - nvidia,bpmp = <&bpmp 10>; + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; - nvidia,enable-ext-refclk; - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; - interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, - <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; - interconnect-names = "dma-mem", "write"; - iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>; - iommu-map-mask = <0x0>; - dma-coherent; + nvidia,bpmp = <&bpmp 7>; - status = "disabled"; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; + + bus-range = <0x0 0xff>; + + ranges = <0x43000000 0x30 0x00000000 0x30 0x00000000 0x2 0x28000000>, /* prefetchable memory (8832 MB) */ + <0x02000000 0x0 0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ + <0x01000000 0x0 0x3e100000 0x00 0x3e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ + + interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, + <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; + + status = "disabled"; + }; + + pcie-ep@141e0000 { + compatible = "nvidia,tegra234-pcie-ep"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; + reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x3e080000 0x0 0x00040000>, /* DBI space (256K) */ + <0x2e 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ + reg-names = "appl", "atu_dma", "dbi", "addr_space"; + + num-lanes = <8>; + + clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; + clock-names = "core"; + + resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, + <&bpmp TEGRA234_RESET_PEX2_CORE_7>; + reset-names = "apb", "core"; + + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ + interrupt-names = "intr"; + + nvidia,bpmp = <&bpmp 7>; + + nvidia,enable-ext-refclk; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; + + interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, + <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; + + status = "disabled"; + }; }; sram@40000000 { compatible = "nvidia,tegra234-sysram", "mmio-sram"; reg = <0x0 0x40000000 0x0 0x80000>; + #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x40000000 0x80000>; + no-memory-wc; cpu_bpmp_tx: sram@70000 { diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 3e79496292e7..b0423ca3e79f 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -7,8 +7,10 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c1.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c2.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8916-acer-a1-724.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-asus-z00l.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8916-gplus-fl8005a.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-huawei-g7.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8150.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8910.dtb @@ -18,9 +20,17 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a5u-eur.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-e5.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-e7.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-grandmax.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-gt510.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-gt58.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-j5.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-j5x.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-serranove.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-wingtech-wt88047.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8953-motorola-potter.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8953-xiaomi-daisy.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8953-xiaomi-mido.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8953-xiaomi-tissot.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8953-xiaomi-vince.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8956-sony-xperia-loire-kugo.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8956-sony-xperia-loire-suzu.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8992-lg-bullhead-rev-10.dtb @@ -121,17 +131,21 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-villager-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-villager-r1-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-zombie.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-zombie-lte.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-zombie-nvme.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-zombie-nvme-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp2.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-crd-r3.dtb dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-crd.dtb dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-lenovo-thinkpad-x13s.dtb dtb-$(CONFIG_ARCH_QCOM) += sda660-inforce-ifc6560.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm450-motorola-ali.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-ganges-kirin.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-discovery.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-pioneer.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-voyager.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm632-fairphone-fp3.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm632-motorola-ocean.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm636-sony-xperia-ganges-mermaid.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm660-xiaomi-lavender.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm670-google-sargo.dtb @@ -156,6 +170,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-shift-axolotl.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-samsung-w737.dtb dtb-$(CONFIG_ARCH_QCOM) += sm4250-oneplus-billie2.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm6115p-lenovo-j606f.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6125-sony-xperia-seine-pdx201.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6350-sony-xperia-lena-pdx213.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6375-sony-xperia-murray-pdx225.dtb @@ -178,3 +193,4 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8450-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8450-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx223.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx224.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8550-mtp.dtb diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts index ef5b39ba1238..c52d79a55d80 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts @@ -169,10 +169,6 @@ }; }; -&blsp_dma { - status = "okay"; -}; - &blsp_i2c2 { /* On Low speed expansion */ status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 5d453f11acd9..d32c9b2515ee 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -87,6 +87,12 @@ }; }; + firmware { + scm { + compatible = "qcom,scm-ipq6018", "qcom,scm"; + }; + }; + cpu_opp_table: opp-table-cpu { compatible = "operating-points-v2"; opp-shared; @@ -96,26 +102,31 @@ opp-microvolt = <725000>; clock-latency-ns = <200000>; }; + opp-1056000000 { opp-hz = /bits/ 64 <1056000000>; opp-microvolt = <787500>; clock-latency-ns = <200000>; }; + opp-1320000000 { opp-hz = /bits/ 64 <1320000000>; opp-microvolt = <862500>; clock-latency-ns = <200000>; }; + opp-1440000000 { opp-hz = /bits/ 64 <1440000000>; opp-microvolt = <925000>; clock-latency-ns = <200000>; }; + opp-1608000000 { opp-hz = /bits/ 64 <1608000000>; opp-microvolt = <987500>; clock-latency-ns = <200000>; }; + opp-1800000000 { opp-hz = /bits/ 64 <1800000000>; opp-microvolt = <1062500>; @@ -123,16 +134,9 @@ }; }; - firmware { - scm { - compatible = "qcom,scm-ipq6018", "qcom,scm"; - }; - }; - pmuv8: pmu { compatible = "arm,cortex-a53-pmu"; - interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | - IRQ_TYPE_LEVEL_HIGH)>; + interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; psci: psci { @@ -146,7 +150,7 @@ ranges; rpm_msg_ram: memory@60000 { - reg = <0x0 0x60000 0x0 0x6000>; + reg = <0x0 0x00060000 0x0 0x6000>; no-map; }; @@ -166,6 +170,28 @@ }; }; + rpm-glink { + compatible = "qcom,glink-rpm"; + interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + + rpm_requests: glink-channel { + compatible = "qcom,rpm-ipq6018"; + qcom,glink-channels = "rpm_requests"; + + regulators { + compatible = "qcom,rpm-mp5496-regulators"; + + ipq6018_s2: s2 { + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1062500>; + regulator-always-on; + }; + }; + }; + }; + smem { compatible = "qcom,smem"; memory-region = <&smem_region>; @@ -179,9 +205,105 @@ dma-ranges; compatible = "simple-bus"; + qusb_phy_1: qusb@59000 { + compatible = "qcom,ipq6018-qusb2-phy"; + reg = <0x0 0x00059000 0x0 0x180>; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, + <&xo>; + clock-names = "cfg_ahb", "ref"; + + resets = <&gcc GCC_QUSB2_1_PHY_BCR>; + status = "disabled"; + }; + + ssphy_0: ssphy@78000 { + compatible = "qcom,ipq6018-qmp-usb3-phy"; + reg = <0x0 0x00078000 0x0 0x1c4>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_USB0_AUX_CLK>, + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, <&xo>; + clock-names = "aux", "cfg_ahb", "ref"; + + resets = <&gcc GCC_USB0_PHY_BCR>, + <&gcc GCC_USB3PHY_0_PHY_BCR>; + reset-names = "phy","common"; + status = "disabled"; + + usb0_ssphy: phy@78200 { + reg = <0x0 0x00078200 0x0 0x130>, /* Tx */ + <0x0 0x00078400 0x0 0x200>, /* Rx */ + <0x0 0x00078800 0x0 0x1f8>, /* PCS */ + <0x0 0x00078600 0x0 0x044>; /* PCS misc */ + #phy-cells = <0>; + #clock-cells = <0>; + clocks = <&gcc GCC_USB0_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "gcc_usb0_pipe_clk_src"; + }; + }; + + qusb_phy_0: qusb@79000 { + compatible = "qcom,ipq6018-qusb2-phy"; + reg = <0x0 0x00079000 0x0 0x180>; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, + <&xo>; + clock-names = "cfg_ahb", "ref"; + + resets = <&gcc GCC_QUSB2_0_PHY_BCR>; + status = "disabled"; + }; + + pcie_phy: phy@84000 { + compatible = "qcom,ipq6018-qmp-pcie-phy"; + reg = <0x0 0x00084000 0x0 0x1bc>; /* Serdes PLL */ + status = "disabled"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_PCIE0_AUX_CLK>, + <&gcc GCC_PCIE0_AHB_CLK>; + clock-names = "aux", "cfg_ahb"; + + resets = <&gcc GCC_PCIE0_PHY_BCR>, + <&gcc GCC_PCIE0PHY_PHY_BCR>; + reset-names = "phy", + "common"; + + pcie_phy0: phy@84200 { + reg = <0x0 0x00084200 0x0 0x16c>, /* Serdes Tx */ + <0x0 0x00084400 0x0 0x200>, /* Serdes Rx */ + <0x0 0x00084800 0x0 0x1f0>, /* PCS: Lane0, COM, PCIE */ + <0x0 0x00084c00 0x0 0xf4>; /* pcs_misc */ + #phy-cells = <0>; + + clocks = <&gcc GCC_PCIE0_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "gcc_pcie0_pipe_clk_src"; + #clock-cells = <0>; + }; + }; + + mdio: mdio@90000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,ipq6018-mdio", "qcom,ipq4019-mdio"; + reg = <0x0 0x00090000 0x0 0x64>; + clocks = <&gcc GCC_MDIO_AHB_CLK>; + clock-names = "gcc_mdio_ahb_clk"; + status = "disabled"; + }; + prng: qrng@e1000 { compatible = "qcom,prng-ee"; - reg = <0x0 0xe3000 0x0 0x1000>; + reg = <0x0 0x000e3000 0x0 0x1000>; clocks = <&gcc GCC_PRNG_AHB_CLK>; clock-names = "core"; }; @@ -201,8 +323,8 @@ compatible = "qcom,crypto-v5.1"; reg = <0x0 0x0073a000 0x0 0x6000>; clocks = <&gcc GCC_CRYPTO_AHB_CLK>, - <&gcc GCC_CRYPTO_AXI_CLK>, - <&gcc GCC_CRYPTO_CLK>; + <&gcc GCC_CRYPTO_AXI_CLK>, + <&gcc GCC_CRYPTO_CLK>; clock-names = "iface", "bus", "core"; dmas = <&cryptobam 2>, <&cryptobam 3>; dma-names = "rx", "tx"; @@ -257,6 +379,41 @@ reg = <0x0 0x01937000 0x0 0x21000>; }; + usb2: usb@70f8800 { + compatible = "qcom,ipq6018-dwc3", "qcom,dwc3"; + reg = <0x0 0x070f8800 0x0 0x400>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clocks = <&gcc GCC_USB1_MASTER_CLK>, + <&gcc GCC_USB1_SLEEP_CLK>, + <&gcc GCC_USB1_MOCK_UTMI_CLK>; + clock-names = "core", + "sleep", + "mock_utmi"; + + assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>, + <&gcc GCC_USB1_MOCK_UTMI_CLK>; + assigned-clock-rates = <133330000>, + <24000000>; + resets = <&gcc GCC_USB1_BCR>; + status = "disabled"; + + dwc_1: usb@7000000 { + compatible = "snps,dwc3"; + reg = <0x0 0x07000000 0x0 0xcd00>; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + phys = <&qusb_phy_1>; + phy-names = "usb2-phy"; + tx-fifo-resize; + snps,is-utmi-l1-suspend; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + dr_mode = "host"; + }; + }; + blsp_dma: dma-controller@7884000 { compatible = "qcom,bam-v1.7.0"; reg = <0x0 0x07884000 0x0 0x2b000>; @@ -272,7 +429,7 @@ reg = <0x0 0x078b1000 0x0 0x200>; interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; + <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; status = "disabled"; }; @@ -285,7 +442,7 @@ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; spi-max-frequency = <50000000>; clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; + <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; dmas = <&blsp_dma 12>, <&blsp_dma 13>; dma-names = "tx", "rx"; @@ -300,7 +457,7 @@ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; spi-max-frequency = <50000000>; clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; + <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; dmas = <&blsp_dma 14>, <&blsp_dma 15>; dma-names = "tx", "rx"; @@ -358,24 +515,67 @@ clock-names = "core", "aon"; dmas = <&qpic_bam 0>, - <&qpic_bam 1>, - <&qpic_bam 2>; + <&qpic_bam 1>, + <&qpic_bam 2>; dma-names = "tx", "rx", "cmd"; pinctrl-0 = <&qpic_pins>; pinctrl-names = "default"; status = "disabled"; }; + usb3: usb@8af8800 { + compatible = "qcom,ipq6018-dwc3", "qcom,dwc3"; + reg = <0x0 0x08af8800 0x0 0x400>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, + <&gcc GCC_USB0_MASTER_CLK>, + <&gcc GCC_USB0_SLEEP_CLK>, + <&gcc GCC_USB0_MOCK_UTMI_CLK>; + clock-names = "cfg_noc", + "core", + "sleep", + "mock_utmi"; + + assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, + <&gcc GCC_USB0_MASTER_CLK>, + <&gcc GCC_USB0_MOCK_UTMI_CLK>; + assigned-clock-rates = <133330000>, + <133330000>, + <20000000>; + + resets = <&gcc GCC_USB0_BCR>; + status = "disabled"; + + dwc_0: usb@8a00000 { + compatible = "snps,dwc3"; + reg = <0x0 0x08a00000 0x0 0xcd00>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + phys = <&qusb_phy_0>, <&usb0_ssphy>; + phy-names = "usb2-phy", "usb3-phy"; + clocks = <&xo>; + clock-names = "ref"; + tx-fifo-resize; + snps,is-utmi-l1-suspend; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + dr_mode = "host"; + }; + }; + intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; #address-cells = <2>; #size-cells = <2>; interrupt-controller; #interrupt-cells = <0x3>; - reg = <0x0 0x0b000000 0x0 0x1000>, /*GICD*/ - <0x0 0x0b002000 0x0 0x1000>, /*GICC*/ - <0x0 0x0b001000 0x0 0x1000>, /*GICH*/ - <0x0 0x0b004000 0x0 0x1000>; /*GICV*/ + reg = <0x0 0x0b000000 0x0 0x1000>, /*GICD*/ + <0x0 0x0b002000 0x0 0x1000>, /*GICC*/ + <0x0 0x0b001000 0x0 0x1000>, /*GICH*/ + <0x0 0x0b004000 0x0 0x1000>; /*GICV*/ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; ranges = <0 0 0 0xb00a000 0 0xffd>; @@ -386,107 +586,6 @@ }; }; - pcie_phy: phy@84000 { - compatible = "qcom,ipq6018-qmp-pcie-phy"; - reg = <0x0 0x84000 0x0 0x1bc>; /* Serdes PLL */ - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&gcc GCC_PCIE0_AUX_CLK>, - <&gcc GCC_PCIE0_AHB_CLK>; - clock-names = "aux", "cfg_ahb"; - - resets = <&gcc GCC_PCIE0_PHY_BCR>, - <&gcc GCC_PCIE0PHY_PHY_BCR>; - reset-names = "phy", - "common"; - - pcie_phy0: phy@84200 { - reg = <0x0 0x84200 0x0 0x16c>, /* Serdes Tx */ - <0x0 0x84400 0x0 0x200>, /* Serdes Rx */ - <0x0 0x84800 0x0 0x1f0>, /* PCS: Lane0, COM, PCIE */ - <0x0 0x84c00 0x0 0xf4>; /* pcs_misc */ - #phy-cells = <0>; - - clocks = <&gcc GCC_PCIE0_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "gcc_pcie0_pipe_clk_src"; - #clock-cells = <0>; - }; - }; - - pcie0: pci@20000000 { - compatible = "qcom,pcie-ipq6018"; - reg = <0x0 0x20000000 0x0 0xf1d>, - <0x0 0x20000f20 0x0 0xa8>, - <0x0 0x20001000 0x0 0x1000>, - <0x0 0x80000 0x0 0x4000>, - <0x0 0x20100000 0x0 0x1000>; - reg-names = "dbi", "elbi", "atu", "parf", "config"; - - device_type = "pci"; - linux,pci-domain = <0>; - bus-range = <0x00 0xff>; - num-lanes = <1>; - max-link-speed = <3>; - #address-cells = <3>; - #size-cells = <2>; - - phys = <&pcie_phy0>; - phy-names = "pciephy"; - - ranges = <0x81000000 0 0x20200000 0 0x20200000 - 0 0x10000>, /* downstream I/O */ - <0x82000000 0 0x20220000 0 0x20220000 - 0 0xfde0000>; /* non-prefetchable memory */ - - interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "msi"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 75 - IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 78 - IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 79 - IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 83 - IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - - clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, - <&gcc GCC_PCIE0_AXI_M_CLK>, - <&gcc GCC_PCIE0_AXI_S_CLK>, - <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, - <&gcc PCIE0_RCHNG_CLK>; - clock-names = "iface", - "axi_m", - "axi_s", - "axi_bridge", - "rchng"; - - resets = <&gcc GCC_PCIE0_PIPE_ARES>, - <&gcc GCC_PCIE0_SLEEP_ARES>, - <&gcc GCC_PCIE0_CORE_STICKY_ARES>, - <&gcc GCC_PCIE0_AXI_MASTER_ARES>, - <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, - <&gcc GCC_PCIE0_AHB_ARES>, - <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>, - <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>; - reset-names = "pipe", - "sleep", - "sticky", - "axi_m", - "axi_s", - "ahb", - "axi_m_sticky", - "axi_s_sticky"; - - status = "disabled"; - }; - watchdog@b017000 { compatible = "qcom,kpss-wdt"; interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; @@ -619,147 +718,68 @@ }; }; - mdio: mdio@90000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "qcom,ipq6018-mdio", "qcom,ipq4019-mdio"; - reg = <0x0 0x90000 0x0 0x64>; - clocks = <&gcc GCC_MDIO_AHB_CLK>; - clock-names = "gcc_mdio_ahb_clk"; - status = "disabled"; - }; - - qusb_phy_1: qusb@59000 { - compatible = "qcom,ipq6018-qusb2-phy"; - reg = <0x0 0x059000 0x0 0x180>; - #phy-cells = <0>; - - clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, - <&xo>; - clock-names = "cfg_ahb", "ref"; - - resets = <&gcc GCC_QUSB2_1_PHY_BCR>; - status = "disabled"; - }; - - usb2: usb@70f8800 { - compatible = "qcom,ipq6018-dwc3", "qcom,dwc3"; - reg = <0x0 0x070F8800 0x0 0x400>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - clocks = <&gcc GCC_USB1_MASTER_CLK>, - <&gcc GCC_USB1_SLEEP_CLK>, - <&gcc GCC_USB1_MOCK_UTMI_CLK>; - clock-names = "core", - "sleep", - "mock_utmi"; - - assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>, - <&gcc GCC_USB1_MOCK_UTMI_CLK>; - assigned-clock-rates = <133330000>, - <24000000>; - resets = <&gcc GCC_USB1_BCR>; - status = "disabled"; - - dwc_1: usb@7000000 { - compatible = "snps,dwc3"; - reg = <0x0 0x7000000 0x0 0xcd00>; - interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; - phys = <&qusb_phy_1>; - phy-names = "usb2-phy"; - tx-fifo-resize; - snps,is-utmi-l1-suspend; - snps,hird-threshold = /bits/ 8 <0x0>; - snps,dis_u2_susphy_quirk; - snps,dis_u3_susphy_quirk; - dr_mode = "host"; - }; - }; + pcie0: pci@20000000 { + compatible = "qcom,pcie-ipq6018"; + reg = <0x0 0x20000000 0x0 0xf1d>, + <0x0 0x20000f20 0x0 0xa8>, + <0x0 0x20001000 0x0 0x1000>, + <0x0 0x80000 0x0 0x4000>, + <0x0 0x20100000 0x0 0x1000>; + reg-names = "dbi", "elbi", "atu", "parf", "config"; - ssphy_0: ssphy@78000 { - compatible = "qcom,ipq6018-qmp-usb3-phy"; - reg = <0x0 0x78000 0x0 0x1C4>; - #address-cells = <2>; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + max-link-speed = <3>; + #address-cells = <3>; #size-cells = <2>; - ranges; - - clocks = <&gcc GCC_USB0_AUX_CLK>, - <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, <&xo>; - clock-names = "aux", "cfg_ahb", "ref"; - resets = <&gcc GCC_USB0_PHY_BCR>, - <&gcc GCC_USB3PHY_0_PHY_BCR>; - reset-names = "phy","common"; - status = "disabled"; - - usb0_ssphy: phy@78200 { - reg = <0x0 0x00078200 0x0 0x130>, /* Tx */ - <0x0 0x00078400 0x0 0x200>, /* Rx */ - <0x0 0x00078800 0x0 0x1F8>, /* PCS */ - <0x0 0x00078600 0x0 0x044>; /* PCS misc */ - #phy-cells = <0>; - #clock-cells = <0>; - clocks = <&gcc GCC_USB0_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "gcc_usb0_pipe_clk_src"; - }; - }; - - qusb_phy_0: qusb@79000 { - compatible = "qcom,ipq6018-qusb2-phy"; - reg = <0x0 0x079000 0x0 0x180>; - #phy-cells = <0>; + phys = <&pcie_phy0>; + phy-names = "pciephy"; - clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, - <&xo>; - clock-names = "cfg_ahb", "ref"; + ranges = <0x81000000 0 0x20200000 0 0x20200000 0 0x10000>, + <0x82000000 0 0x20220000 0 0x20220000 0 0xfde0000>; - resets = <&gcc GCC_QUSB2_0_PHY_BCR>; - status = "disabled"; - }; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi"; - usb3: usb@8af8800 { - compatible = "qcom,ipq6018-dwc3", "qcom,dwc3"; - reg = <0x0 0x8AF8800 0x0 0x400>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 78 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 79 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 83 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, - <&gcc GCC_USB0_MASTER_CLK>, - <&gcc GCC_USB0_SLEEP_CLK>, - <&gcc GCC_USB0_MOCK_UTMI_CLK>; - clock-names = "cfg_noc", - "core", - "sleep", - "mock_utmi"; + clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, + <&gcc GCC_PCIE0_AXI_M_CLK>, + <&gcc GCC_PCIE0_AXI_S_CLK>, + <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, + <&gcc PCIE0_RCHNG_CLK>; + clock-names = "iface", + "axi_m", + "axi_s", + "axi_bridge", + "rchng"; - assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, - <&gcc GCC_USB0_MASTER_CLK>, - <&gcc GCC_USB0_MOCK_UTMI_CLK>; - assigned-clock-rates = <133330000>, - <133330000>, - <20000000>; + resets = <&gcc GCC_PCIE0_PIPE_ARES>, + <&gcc GCC_PCIE0_SLEEP_ARES>, + <&gcc GCC_PCIE0_CORE_STICKY_ARES>, + <&gcc GCC_PCIE0_AXI_MASTER_ARES>, + <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, + <&gcc GCC_PCIE0_AHB_ARES>, + <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>, + <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>; + reset-names = "pipe", + "sleep", + "sticky", + "axi_m", + "axi_s", + "ahb", + "axi_m_sticky", + "axi_s_sticky"; - resets = <&gcc GCC_USB0_BCR>; status = "disabled"; - - dwc_0: usb@8a00000 { - compatible = "snps,dwc3"; - reg = <0x0 0x8A00000 0x0 0xcd00>; - interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; - phys = <&qusb_phy_0>, <&usb0_ssphy>; - phy-names = "usb2-phy", "usb3-phy"; - clocks = <&xo>; - clock-names = "ref"; - tx-fifo-resize; - snps,is-utmi-l1-suspend; - snps,hird-threshold = /bits/ 8 <0x0>; - snps,dis_u2_susphy_quirk; - snps,dis_u3_susphy_quirk; - dr_mode = "host"; - }; }; }; @@ -794,26 +814,4 @@ #interrupt-cells = <2>; }; }; - - rpm-glink { - compatible = "qcom,glink-rpm"; - interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; - qcom,rpm-msg-ram = <&rpm_msg_ram>; - mboxes = <&apcs_glb 0>; - - rpm_requests: glink-channel { - compatible = "qcom,rpm-ipq6018"; - qcom,glink-channels = "rpm_requests"; - - regulators { - compatible = "qcom,rpm-mp5496-regulators"; - - ipq6018_s2: s2 { - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1062500>; - regulator-always-on; - }; - }; - }; - }; }; diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 4e51d8e3df04..0e3d1d906a22 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -137,7 +137,7 @@ #clock-cells = <0>; clocks = <&gcc GCC_USB1_PIPE_CLK>; clock-names = "pipe0"; - clock-output-names = "gcc_usb1_pipe_clk_src"; + clock-output-names = "usb3phy_1_cc_pipe_clk"; }; }; @@ -180,7 +180,7 @@ #clock-cells = <0>; clocks = <&gcc GCC_USB0_PIPE_CLK>; clock-names = "pipe0"; - clock-output-names = "gcc_usb0_pipe_clk_src"; + clock-output-names = "usb3phy_0_cc_pipe_clk"; }; }; @@ -197,9 +197,9 @@ status = "disabled"; }; - pcie_qmp0: phy@86000 { - compatible = "qcom,ipq8074-qmp-pcie-phy"; - reg = <0x00086000 0x1c4>; + pcie_qmp0: phy@84000 { + compatible = "qcom,ipq8074-qmp-gen3-pcie-phy"; + reg = <0x00084000 0x1bc>; #address-cells = <1>; #size-cells = <1>; ranges; @@ -213,15 +213,16 @@ "common"; status = "disabled"; - pcie_phy0: phy@86200 { - reg = <0x86200 0x16c>, - <0x86400 0x200>, - <0x86800 0x4f4>; + pcie_phy0: phy@84200 { + reg = <0x84200 0x16c>, + <0x84400 0x200>, + <0x84800 0x1f0>, + <0x84c00 0xf4>; #phy-cells = <0>; #clock-cells = <0>; clocks = <&gcc GCC_PCIE0_PIPE_CLK>; clock-names = "pipe0"; - clock-output-names = "pcie_0_pipe_clk"; + clock-output-names = "pcie20_phy0_pipe_clk"; }; }; @@ -242,19 +243,19 @@ status = "disabled"; pcie_phy1: phy@8e200 { - reg = <0x8e200 0x16c>, + reg = <0x8e200 0x130>, <0x8e400 0x200>, - <0x8e800 0x4f4>; + <0x8e800 0x1f8>; #phy-cells = <0>; #clock-cells = <0>; clocks = <&gcc GCC_PCIE1_PIPE_CLK>; clock-names = "pipe0"; - clock-output-names = "pcie_1_pipe_clk"; + clock-output-names = "pcie20_phy1_pipe_clk"; }; }; mdio: mdio@90000 { - compatible = "qcom,ipq4019-mdio"; + compatible = "qcom,ipq8074-mdio", "qcom,ipq4019-mdio"; reg = <0x00090000 0x64>; #address-cells = <1>; #size-cells = <0>; @@ -765,6 +766,7 @@ linux,pci-domain = <1>; bus-range = <0x00 0xff>; num-lanes = <1>; + max-link-speed = <2>; #address-cells = <3>; #size-cells = <2>; @@ -772,9 +774,9 @@ phy-names = "pciephy"; ranges = <0x81000000 0 0x10200000 0x10200000 - 0 0x100000 /* downstream I/O */ - 0x82000000 0 0x10300000 0x10300000 - 0 0xd00000>; /* non-prefetchable memory */ + 0 0x10000>, /* downstream I/O */ + <0x82000000 0 0x10220000 0x10220000 + 0 0xfde0000>; /* non-prefetchable memory */ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "msi"; @@ -817,16 +819,18 @@ }; pcie0: pci@20000000 { - compatible = "qcom,pcie-ipq8074"; + compatible = "qcom,pcie-ipq8074-gen3"; reg = <0x20000000 0xf1d>, <0x20000f20 0xa8>, - <0x00080000 0x2000>, + <0x20001000 0x1000>, + <0x00080000 0x4000>, <0x20100000 0x1000>; - reg-names = "dbi", "elbi", "parf", "config"; + reg-names = "dbi", "elbi", "atu", "parf", "config"; device_type = "pci"; linux,pci-domain = <0>; bus-range = <0x00 0xff>; num-lanes = <1>; + max-link-speed = <3>; #address-cells = <3>; #size-cells = <2>; @@ -834,9 +838,9 @@ phy-names = "pciephy"; ranges = <0x81000000 0 0x20200000 0x20200000 - 0 0x100000 /* downstream I/O */ - 0x82000000 0 0x20300000 0x20300000 - 0 0xd00000>; /* non-prefetchable memory */ + 0 0x10000>, /* downstream I/O */ + <0x82000000 0 0x20220000 0x20220000 + 0 0xfde0000>; /* non-prefetchable memory */ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "msi"; @@ -854,28 +858,30 @@ clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, <&gcc GCC_PCIE0_AXI_M_CLK>, <&gcc GCC_PCIE0_AXI_S_CLK>, - <&gcc GCC_PCIE0_AHB_CLK>, - <&gcc GCC_PCIE0_AUX_CLK>; - + <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, + <&gcc GCC_PCIE0_RCHNG_CLK>; clock-names = "iface", "axi_m", "axi_s", - "ahb", - "aux"; + "axi_bridge", + "rchng"; + resets = <&gcc GCC_PCIE0_PIPE_ARES>, <&gcc GCC_PCIE0_SLEEP_ARES>, <&gcc GCC_PCIE0_CORE_STICKY_ARES>, <&gcc GCC_PCIE0_AXI_MASTER_ARES>, <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, <&gcc GCC_PCIE0_AHB_ARES>, - <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>; + <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>, + <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>; reset-names = "pipe", "sleep", "sticky", "axi_m", "axi_s", "ahb", - "axi_m_sticky"; + "axi_m_sticky", + "axi_s_sticky"; status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts b/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts new file mode 100644 index 000000000000..ed3fa7b3575b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts @@ -0,0 +1,295 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "msm8916-pm8916.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/* + * NOTE: The original firmware from Acer can only boot 32-bit kernels. + * To boot this device tree using arm64 it is necessary to flash 64-bit + * TZ/HYP firmware (e.g. taken from the DragonBoard 410c). + * See https://wiki.postmarketos.org/wiki/Acer_Iconia_Talk_S_(acer-a1-724) + * for suggested installation instructions. + */ + +/ { + model = "Acer Iconia Talk S A1-724"; + compatible = "acer,a1-724", "qcom,msm8916"; + chassis-type = "tablet"; + + aliases { + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_default>; + + label = "GPIO Buttons"; + + button-volume-up { + label = "Volume Up"; + gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + }; + }; + + usb_id: usb-id { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&msmgpio 110 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_id_default>; + }; +}; + +&blsp_i2c2 { + status = "okay"; + + accelerometer@10 { + compatible = "bosch,bmc150_accel"; + reg = <0x10>; + interrupt-parent = <&msmgpio>; + interrupts = <115 IRQ_TYPE_EDGE_RISING>; + + vdd-supply = <&pm8916_l17>; + vddio-supply = <&pm8916_l6>; + + pinctrl-names = "default"; + pinctrl-0 = <&accel_int_default>; + + mount-matrix = "0", "-1", "0", + "-1", "0", "0", + "0", "0", "1"; + }; + + magnetometer@12 { + compatible = "bosch,bmc150_magn"; + reg = <0x12>; + + vdd-supply = <&pm8916_l17>; + vddio-supply = <&pm8916_l6>; + }; +}; + +&blsp_i2c5 { + status = "okay"; + + touchscreen@38 { + /* Actually ft5446 */ + compatible = "edt,edt-ft5406"; + reg = <0x38>; + + interrupt-parent = <&msmgpio>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; + + reset-gpios = <&msmgpio 12 GPIO_ACTIVE_LOW>; + + vcc-supply = <&pm8916_l16>; + iovcc-supply = <&pm8916_l6>; + + touchscreen-size-x = <720>; + touchscreen-size-y = <1280>; + + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen_default>; + }; +}; + +&blsp1_uart2 { + status = "okay"; +}; + +&pm8916_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; +}; + +&pm8916_vib { + status = "okay"; +}; + +&pronto { + status = "okay"; +}; + +&sdhc_1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; + + status = "okay"; +}; + +&sdhc_2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; + + cd-gpios = <&msmgpio 38 GPIO_ACTIVE_HIGH>; + + status = "okay"; +}; + +&usb { + extcon = <&usb_id>, <&usb_id>; + status = "okay"; +}; + +&usb_hs_phy { + extcon = <&usb_id>; +}; + +&smd_rpm_regulators { + vdd_l1_l2_l3-supply = <&pm8916_s3>; + vdd_l4_l5_l6-supply = <&pm8916_s4>; + vdd_l7-supply = <&pm8916_s4>; + + s3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + }; + + s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2100000>; + }; + + l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + l4 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l8 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2900000>; + }; + + l9 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + l10 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2800000>; + }; + + l11 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-system-load = <200000>; + regulator-allow-set-load; + }; + + l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + l13 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + + l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l16 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + }; + + l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + l18 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; +}; + +&msmgpio { + accel_int_default: accel-int-default-state { + pins = "gpio115"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + gpio_keys_default: gpio-keys-default-state { + pins = "gpio107"; + function = "gpio"; + + drive-strength = <2>; + bias-pull-up; + }; + + touchscreen_default: touchscreen-default-state { + reset-pins { + pins = "gpio12"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + touchscreen-pins { + pins = "gpio13"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + usb_id_default: usb-id-default-state { + pins = "gpio110"; + function = "gpio"; + + drive-strength = <8>; + bias-pull-up; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts b/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts new file mode 100644 index 000000000000..a0e520edde02 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts @@ -0,0 +1,299 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "msm8916-pm8916.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> + +/ { + model = "GPLUS FL8005A"; + compatible = "gplus,fl8005a", "qcom,msm8916"; + chassis-type = "tablet"; + + aliases { + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0"; + }; + + flash-led-controller { + /* Actually qcom,leds-gpio-flash */ + compatible = "sgmicro,sgm3140"; + enable-gpios = <&msmgpio 31 GPIO_ACTIVE_HIGH>; + flash-gpios = <&msmgpio 32 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&camera_flash_default>; + pinctrl-names = "default"; + + flash_led: led { + function = LED_FUNCTION_FLASH; + color = <LED_COLOR_ID_WHITE>; + flash-max-timeout-us = <250000>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&gpio_keys_default>; + pinctrl-names = "default"; + + button-volume-up { + label = "Volume Up"; + gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + pinctrl-0 = <&gpio_leds_default>; + pinctrl-names = "default"; + + led-red { + function = LED_FUNCTION_CHARGING; + color = <LED_COLOR_ID_RED>; + gpios = <&msmgpio 117 GPIO_ACTIVE_HIGH>; + retain-state-suspended; + }; + + led-green { + function = LED_FUNCTION_CHARGING; + color = <LED_COLOR_ID_GREEN>; + gpios = <&msmgpio 118 GPIO_ACTIVE_HIGH>; + retain-state-suspended; + }; + }; + + usb_id: usb-id { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&msmgpio 110 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&usb_id_default>; + pinctrl-names = "default"; + }; +}; + +&blsp_i2c5 { + status = "okay"; + + touchscreen@38 { + /* Actually ft5402 */ + compatible = "edt,edt-ft5406"; + reg = <0x38>; + + interrupt-parent = <&msmgpio>; + interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + + reset-gpios = <&msmgpio 12 GPIO_ACTIVE_LOW>; + + vcc-supply = <&pm8916_l17>; + iovcc-supply = <&pm8916_l6>; + + touchscreen-size-x = <800>; + touchscreen-size-y = <500>; + touchscreen-inverted-x; + touchscreen-swapped-x-y; + + pinctrl-0 = <&touchscreen_default>; + pinctrl-names = "default"; + }; +}; + +&blsp1_uart2 { + status = "okay"; +}; + +&pm8916_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; +}; + +&pm8916_vib { + status = "okay"; +}; + +&pronto { + status = "okay"; +}; + +&sdhc_1 { + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; + pinctrl-names = "default", "sleep"; + + status = "okay"; +}; + +&sdhc_2 { + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; + pinctrl-names = "default", "sleep"; + + cd-gpios = <&msmgpio 38 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +&usb { + extcon = <&usb_id>, <&usb_id>; + status = "okay"; +}; + +&usb_hs_phy { + extcon = <&usb_id>; +}; + +&smd_rpm_regulators { + vdd_l1_l2_l3-supply = <&pm8916_s3>; + vdd_l4_l5_l6-supply = <&pm8916_s4>; + vdd_l7-supply = <&pm8916_s4>; + + s3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + }; + + s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2100000>; + }; + + l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + l4 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l8 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2900000>; + }; + + l9 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + l10 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2800000>; + }; + + l11 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-system-load = <200000>; + regulator-allow-set-load; + }; + + l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + l13 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + + l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + l18 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; +}; + +&msmgpio { + camera_flash_default: camera-flash-default-state { + pins = "gpio31", "gpio32"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + gpio_keys_default: gpio-keys-default-state { + pins = "gpio107"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + gpio_leds_default: gpio-led-default-state { + pins = "gpio117", "gpio118"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + touchscreen_default: touchscreen-default-state { + reset-pins { + pins = "gpio12"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + touchscreen-pins { + pins = "gpio13"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + usb_id_default: usb-id-default-state { + pins = "gpio110"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi index d600916a0e55..a2ed7bdbf528 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi @@ -434,7 +434,7 @@ bias-pull-down; }; - motor_en_default: motor-en-default-stae { + motor_en_default: motor-en-default-state { pins = "gpio76"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-grandmax.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-grandmax.dts index a3d572d851ef..4cbd68b89448 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-grandmax.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-grandmax.dts @@ -29,8 +29,12 @@ gpio-leds { compatible = "gpio-leds"; - keyled { + led-keyled { + function = LED_FUNCTION_KBD_BACKLIGHT; + color = <LED_COLOR_ID_WHITE>; + gpios = <&msmgpio 60 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; pinctrl-0 = <&gpio_leds_default>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi new file mode 100644 index 000000000000..d920b7247d82 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi @@ -0,0 +1,296 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "msm8916-pm8916.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + aliases { + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0"; + }; + + reserved-memory { + /* Additional memory used by Samsung firmware modifications */ + tz-apps@85500000 { + reg = <0x0 0x85500000 0x0 0xb00000>; + no-map; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&gpio_keys_default>; + pinctrl-names = "default"; + + label = "GPIO Buttons"; + + volume-up-button { + label = "Volume Up"; + gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + }; + + home-button { + label = "Home"; + gpios = <&msmgpio 109 GPIO_ACTIVE_LOW>; + linux,code = <KEY_HOMEPAGE>; + }; + }; + + gpio-hall-sensor { + compatible = "gpio-keys"; + + pinctrl-0 = <&gpio_hall_sensor_default>; + pinctrl-names = "default"; + + label = "GPIO Hall Effect Sensor"; + + hall-sensor-switch { + label = "Hall Effect Sensor"; + gpios = <&msmgpio 52 GPIO_ACTIVE_LOW>; + linux,input-type = <EV_SW>; + linux,code = <SW_LID>; + linux,can-disable; + }; + }; +}; + +&blsp_i2c4 { + status = "okay"; + + fuelgauge@36 { + compatible = "maxim,max77849-battery"; + reg = <0x36>; + + maxim,rsns-microohm = <10000>; + maxim,over-heat-temp = <600>; + maxim,over-volt = <4400>; + + interrupt-parent = <&msmgpio>; + interrupts = <121 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-0 = <&fuelgauge_int_default>; + pinctrl-names = "default"; + }; +}; + +&blsp_i2c2 { + status = "okay"; + + light-sensor@10 { + compatible = "capella,cm3323"; + reg = <0x10>; + }; + + accelerometer@1d { + compatible = "st,lis2hh12"; + reg = <0x1d>; + + vdd-supply = <&pm8916_l17>; + vddio-supply = <&pm8916_l5>; + + interrupt-parent = <&msmgpio>; + interrupts = <115 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "INT1"; + + st,drdy-int-pin = <1>; + mount-matrix = "0", "1", "0", + "-1", "0", "0", + "0", "0", "1"; + + pinctrl-0 = <&accel_int_default>; + pinctrl-names = "default"; + }; +}; + +&blsp1_uart2 { + status = "okay"; +}; + +&pm8916_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; +}; + +/* FIXME: Replace with MAX77849 MUIC when driver is available */ +&pm8916_usbin { + status = "okay"; +}; + +&pronto { + status = "okay"; + + iris { + compatible = "qcom,wcn3660b"; + }; +}; + +&sdhc_1 { + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; + pinctrl-names = "default", "sleep"; + + status = "okay"; +}; + +&sdhc_2 { + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + pinctrl-names = "default", "sleep"; + + cd-gpios = <&msmgpio 38 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +&usb { + dr_mode = "peripheral"; + extcon = <&pm8916_usbin>; + + status = "okay"; +}; + +&usb_hs_phy { + extcon = <&pm8916_usbin>; +}; + +&smd_rpm_regulators { + vdd_l1_l2_l3-supply = <&pm8916_s3>; + vdd_l4_l5_l6-supply = <&pm8916_s4>; + vdd_l7-supply = <&pm8916_s4>; + + s3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + }; + + s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2100000>; + }; + + l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + l4 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l8 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2900000>; + }; + + l9 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + l10 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2800000>; + }; + + l11 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-system-load = <200000>; + regulator-allow-set-load; + }; + + l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + l13 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + + l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + l18 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; +}; + +&msmgpio { + accel_int_default: accel-int-default-state { + pins = "gpio115"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + fuelgauge_int_default: fuelgauge-int-default-state { + pins = "gpio121"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + gpio_keys_default: gpio-keys-default-state { + pins = "gpio107", "gpio109"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + gpio_hall_sensor_default: gpio-hall-sensor-default-state { + pins = "gpio52"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-gt510.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-gt510.dts new file mode 100644 index 000000000000..607a5dc8a534 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-gt510.dts @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "msm8916-samsung-gt5-common.dtsi" + +/ { + model = "Samsung Galaxy Tab A 9.7 (2015)"; + compatible = "samsung,gt510", "qcom,msm8916"; + chassis-type = "tablet"; + + clk_pwm: pwm { + compatible = "clk-pwm"; + #pwm-cells = <2>; + + clocks = <&gcc GCC_GP2_CLK>; + + pinctrl-0 = <&motor_pwm_default>; + pinctrl-names = "default"; + }; + + reg_motor_vdd: regulator-motor-vdd { + compatible = "regulator-fixed"; + regulator-name = "motor_vdd"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + gpio = <&msmgpio 76 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&motor_en_default>; + pinctrl-names = "default"; + }; + + reg_tsp_1p8v: regulator-tsp-1p8v { + compatible = "regulator-fixed"; + regulator-name = "tsp_1p8v"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&msmgpio 73 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&tsp_en_default>; + pinctrl-names = "default"; + }; + + reg_tsp_3p3v: regulator-tsp-3p3v { + compatible = "regulator-fixed"; + regulator-name = "tsp_3p3v"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&msmgpio 73 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vibrator { + compatible = "pwm-vibrator"; + + pwms = <&clk_pwm 0 100000>; + pwm-names = "enable"; + + vcc-supply = <®_motor_vdd>; + }; +}; + +&blsp_i2c5 { + status = "okay"; + + touchscreen@4a { + compatible = "atmel,maxtouch"; + reg = <0x4a>; + interrupt-parent = <&msmgpio>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <®_tsp_1p8v>; + vdda-supply = <®_tsp_3p3v>; + + reset-gpios = <&msmgpio 114 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&tsp_int_rst_default>; + pinctrl-names = "default"; + }; +}; + +&msmgpio { + motor_en_default: motor-en-default-state { + pins = "gpio76"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + motor_pwm_default: motor-pwm-default-state { + pins = "gpio50"; + function = "gcc_gp2_clk_a"; + }; + + tsp_en_default: tsp-en-default-state { + pins = "gpio73"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + tsp_int_rst_default: tsp-int-rst-default-state { + pins = "gpio13", "gpio114"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-gt58.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-gt58.dts new file mode 100644 index 000000000000..5d6f8383306b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-gt58.dts @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "msm8916-samsung-gt5-common.dtsi" + +/ { + model = "Samsung Galaxy Tab A 8.0 (2015)"; + compatible = "samsung,gt58", "qcom,msm8916"; + chassis-type = "tablet"; + + reg_vdd_tsp: regulator-vdd-tsp { + compatible = "regulator-fixed"; + regulator-name = "vdd_tsp"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&msmgpio 73 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <®_tsp_en_default>; + pinctrl-names = "default"; + }; + + vibrator { + compatible = "gpio-vibrator"; + enable-gpios = <&msmgpio 76 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&vibrator_en_default>; + pinctrl-names = "default"; + }; +}; + +&blsp_i2c5 { + status = "okay"; + + touchscreen@20 { + compatible = "zinitix,bt532"; + reg = <0x20>; + interrupt-parent = <&msmgpio>; + interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + + touchscreen-size-x = <768>; + touchscreen-size-y = <1024>; + + vcca-supply = <®_vdd_tsp>; + vdd-supply = <&pm8916_l6>; + + pinctrl-0 = <&tsp_int_default>; + pinctrl-names = "default"; + }; +}; + +&msmgpio { + reg_tsp_en_default: reg-tsp-en-default-state { + pins = "gpio73"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + tsp_int_default: tsp-int-default-state { + pins = "gpio13"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + vibrator_en_default: vibrator-en-default-state { + pins = "gpio76"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi new file mode 100644 index 000000000000..f3b81b6f0a2f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi @@ -0,0 +1,262 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include "msm8916-pm8916.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + aliases { + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0"; + }; + + reserved-memory { + /* Additional memory used by Samsung firmware modifications */ + tz-apps@85500000 { + reg = <0x0 0x85500000 0x0 0xb00000>; + no-map; + }; + }; + + gpio_hall_sensor: gpio-hall-sensor { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_hall_sensor_default>; + + label = "GPIO Hall Effect Sensor"; + + event-hall-sensor { + label = "Hall Effect Sensor"; + gpios = <&msmgpio 52 GPIO_ACTIVE_LOW>; + linux,input-type = <EV_SW>; + linux,code = <SW_LID>; + linux,can-disable; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_default>; + + label = "GPIO Buttons"; + + button-volume-up { + label = "Volume Up"; + gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + }; + + button-home { + label = "Home Key"; + gpios = <&msmgpio 109 GPIO_ACTIVE_LOW>; + linux,code = <KEY_HOMEPAGE>; + }; + }; + + i2c_muic: i2c-muic { + compatible = "i2c-gpio"; + sda-gpios = <&msmgpio 105 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&msmgpio 106 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + + pinctrl-names = "default"; + pinctrl-0 = <&muic_i2c_default>; + + #address-cells = <1>; + #size-cells = <0>; + + muic: extcon@25 { + compatible = "siliconmitus,sm5703-muic"; + reg = <0x25>; + + interrupt-parent = <&msmgpio>; + interrupts = <12 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-names = "default"; + pinctrl-0 = <&muic_int_default>; + }; + }; +}; + +&blsp1_uart2 { + status = "okay"; +}; + +&pm8916_resin { + status = "okay"; + linux,code = <KEY_VOLUMEDOWN>; +}; + +&pronto { + status = "okay"; +}; + +&sdhc_1 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; +}; + +&sdhc_2 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + + cd-gpios = <&msmgpio 38 GPIO_ACTIVE_LOW>; +}; + +&usb { + extcon = <&muic>, <&muic>; + status = "okay"; +}; + +&usb_hs_phy { + extcon = <&muic>; +}; + +&smd_rpm_regulators { + vdd_l1_l2_l3-supply = <&pm8916_s3>; + vdd_l4_l5_l6-supply = <&pm8916_s4>; + vdd_l7-supply = <&pm8916_s4>; + + s3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + }; + + s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2100000>; + }; + + l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + l4 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l8 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2900000>; + }; + + l9 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + l10 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2800000>; + }; + + l11 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + regulator-system-load = <200000>; + }; + + l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + l13 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + + l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l17 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + l18 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; +}; + +&msmgpio { + gpio_hall_sensor_default: gpio-hall-sensor-default-state { + pins = "gpio52"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + gpio_keys_default: gpio-keys-default-state { + pins = "gpio107", "gpio109"; + function = "gpio"; + + drive-strength = <2>; + bias-pull-up; + }; + + muic_i2c_default: muic-i2c-default-state { + pins = "gpio105", "gpio106"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + muic_int_default: muic-int-default-state { + pins = "gpio12"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts index 7ac49a021563..0a32d33e9778 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts @@ -2,208 +2,14 @@ /dts-v1/; -#include "msm8916-pm8916.dtsi" -#include <dt-bindings/gpio/gpio.h> +#include "msm8916-samsung-j5-common.dtsi" / { model = "Samsung Galaxy J5 (2015)"; compatible = "samsung,j5", "qcom,msm8916"; chassis-type = "handset"; - - aliases { - serial0 = &blsp1_uart2; - }; - - chosen { - stdout-path = "serial0"; - }; - - reserved-memory { - /* Additional memory used by Samsung firmware modifications */ - tz-apps@85500000 { - reg = <0x0 0x85500000 0x0 0xb00000>; - no-map; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_default>; - - label = "GPIO Buttons"; - - button-volume-up { - label = "Volume Up"; - gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; - linux,code = <KEY_VOLUMEUP>; - }; - - button-home { - label = "Home Key"; - gpios = <&msmgpio 109 GPIO_ACTIVE_LOW>; - linux,code = <KEY_HOMEPAGE>; - }; - }; -}; - -&blsp1_uart2 { - status = "okay"; -}; - -&pm8916_resin { - status = "okay"; - linux,code = <KEY_VOLUMEDOWN>; -}; - -/* FIXME: Replace with SM5703 MUIC when driver is available */ -&pm8916_usbin { - status = "okay"; -}; - -&pronto { - status = "okay"; -}; - -&sdhc_1 { - status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; - pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; -}; - -&sdhc_2 { - status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; - - cd-gpios = <&msmgpio 38 GPIO_ACTIVE_LOW>; -}; - -&usb { - status = "okay"; - dr_mode = "peripheral"; - extcon = <&pm8916_usbin>; }; &usb_hs_phy { - extcon = <&pm8916_usbin>; qcom,init-seq = /bits/ 8 <0x1 0x19 0x2 0x0b>; }; - -&smd_rpm_regulators { - vdd_l1_l2_l3-supply = <&pm8916_s3>; - vdd_l4_l5_l6-supply = <&pm8916_s4>; - vdd_l7-supply = <&pm8916_s4>; - - s3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1300000>; - }; - - s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2100000>; - }; - - l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l4 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l8 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2900000>; - }; - - l9 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - l10 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2800000>; - }; - - l11 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - regulator-allow-set-load; - regulator-system-load = <200000>; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l13 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l16 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l17 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - l18 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; -}; - -&msmgpio { - gpio_keys_default: gpio-keys-default-state { - pins = "gpio107", "gpio109"; - function = "gpio"; - - drive-strength = <2>; - bias-pull-up; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5x.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5x.dts new file mode 100644 index 000000000000..7e1326cc13c5 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5x.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "msm8916-samsung-j5-common.dtsi" + +/ { + model = "Samsung Galaxy J5 (2016)"; + compatible = "samsung,j5x", "qcom,msm8916"; + chassis-type = "handset"; +}; + +&muic { + interrupts = <121 IRQ_TYPE_EDGE_FALLING>; +}; + +&muic_int_default { + pins = "gpio121"; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 2ca8e977fc2a..0733c2f4f379 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -442,11 +442,70 @@ reg = <0x0005c000 0x1000>; #address-cells = <1>; #size-cells = <1>; - tsens_caldata: caldata@d0 { - reg = <0xd0 0x8>; + + tsens_base1: base1@d0 { + reg = <0xd0 0x1>; + bits = <0 7>; + }; + + tsens_s0_p1: s0-p1@d0 { + reg = <0xd0 0x2>; + bits = <7 5>; + }; + + tsens_s0_p2: s0-p2@d1 { + reg = <0xd1 0x2>; + bits = <4 5>; }; - tsens_calsel: calsel@ec { - reg = <0xec 0x4>; + + tsens_s1_p1: s1-p1@d2 { + reg = <0xd2 0x1>; + bits = <1 5>; + }; + tsens_s1_p2: s1-p2@d2 { + reg = <0xd2 0x2>; + bits = <6 5>; + }; + tsens_s2_p1: s2-p1@d3 { + reg = <0xd3 0x1>; + bits = <3 5>; + }; + + tsens_s2_p2: s2-p2@d4 { + reg = <0xd4 0x1>; + bits = <0 5>; + }; + + // no tsens with hw_id 3 + + tsens_s4_p1: s4-p1@d4 { + reg = <0xd4 0x2>; + bits = <5 5>; + }; + + tsens_s4_p2: s4-p2@d5 { + reg = <0xd5 0x1>; + bits = <2 5>; + }; + + tsens_s5_p1: s5-p1@d5 { + reg = <0xd5 0x2>; + bits = <7 5>; + }; + + tsens_s5_p2: s5-p2@d6 { + reg = <0xd6 0x2>; + bits = <4 5>; + }; + + tsens_base2: base2@d7 { + reg = <0xd7 0x1>; + bits = <1 7>; + }; + + tsens_mode: mode@ec { + reg = <0xef 0x1>; + bits = <5 3>; }; }; @@ -473,8 +532,22 @@ compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1"; reg = <0x004a9000 0x1000>, /* TM */ <0x004a8000 0x1000>; /* SROT */ - nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; - nvmem-cell-names = "calib", "calib_sel"; + + // no hw_id 3 + nvmem-cells = <&tsens_mode>, + <&tsens_base1>, <&tsens_base2>, + <&tsens_s0_p1>, <&tsens_s0_p2>, + <&tsens_s1_p1>, <&tsens_s1_p2>, + <&tsens_s2_p1>, <&tsens_s2_p2>, + <&tsens_s4_p1>, <&tsens_s4_p2>, + <&tsens_s5_p1>, <&tsens_s5_p2>; + nvmem-cell-names = "mode", + "base1", "base2", + "s0_p1", "s0_p2", + "s1_p1", "s1_p2", + "s2_p1", "s2_p2", + "s4_p1", "s4_p2", + "s5_p1", "s5_p2"; #qcom,sensors = <5>; interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "uplow"; @@ -963,7 +1036,7 @@ reg = <0x01937000 0x30000>; }; - mdss: mdss@1a00000 { + mdss: display-subsystem@1a00000 { status = "disabled"; compatible = "qcom,mdss"; reg = <0x01a00000 0x1000>, @@ -988,8 +1061,8 @@ #size-cells = <1>; ranges; - mdp: mdp@1a01000 { - compatible = "qcom,mdp5"; + mdp: display-controller@1a01000 { + compatible = "qcom,msm8916-mdp5", "qcom,mdp5"; reg = <0x01a01000 0x89000>; reg-names = "mdp_phys"; @@ -1021,7 +1094,8 @@ }; dsi0: dsi@1a98000 { - compatible = "qcom,mdss-dsi-ctrl"; + compatible = "qcom,msm8916-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; reg = <0x01a98000 0x25c>; reg-names = "dsi_ctrl"; @@ -1167,7 +1241,7 @@ }; cci: cci@1b0c000 { - compatible = "qcom,msm8916-cci"; + compatible = "qcom,msm8916-cci", "qcom,msm8226-cci"; #address-cells = <1>; #size-cells = <0>; reg = <0x01b0c000 0x1000>; @@ -1521,7 +1595,6 @@ clock-names = "bam_clk"; #dma-cells = <1>; qcom,ee = <0>; - status = "disabled"; }; blsp1_uart1: serial@78af000 { @@ -1559,6 +1632,8 @@ clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; + dmas = <&blsp_dma 4>, <&blsp_dma 5>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c1_default>; pinctrl-1 = <&i2c1_sleep>; @@ -1591,6 +1666,8 @@ clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; + dmas = <&blsp_dma 6>, <&blsp_dma 7>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c2_default>; pinctrl-1 = <&i2c2_sleep>; @@ -1623,6 +1700,8 @@ clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; + dmas = <&blsp_dma 8>, <&blsp_dma 9>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c3_default>; pinctrl-1 = <&i2c3_sleep>; @@ -1655,6 +1734,8 @@ clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; + dmas = <&blsp_dma 10>, <&blsp_dma 11>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c4_default>; pinctrl-1 = <&i2c4_sleep>; @@ -1687,6 +1768,8 @@ clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; + dmas = <&blsp_dma 12>, <&blsp_dma 13>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c5_default>; pinctrl-1 = <&i2c5_sleep>; @@ -1719,6 +1802,8 @@ clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; + dmas = <&blsp_dma 14>, <&blsp_dma 15>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c6_default>; pinctrl-1 = <&i2c6_sleep>; @@ -1998,7 +2083,7 @@ hysteresis = <2000>; type = "passive"; }; - cpu0_1_crit: cpu_crit { + cpu0_1_crit: cpu-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -2028,7 +2113,7 @@ hysteresis = <2000>; type = "passive"; }; - cpu2_3_crit: cpu_crit { + cpu2_3_crit: cpu-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -2058,7 +2143,7 @@ hysteresis = <2000>; type = "passive"; }; - gpu_crit: gpu_crit { + gpu_crit: gpu-crit { temperature = <95000>; hysteresis = <2000>; type = "critical"; diff --git a/arch/arm64/boot/dts/qcom/msm8953-motorola-potter.dts b/arch/arm64/boot/dts/qcom/msm8953-motorola-potter.dts new file mode 100644 index 000000000000..711d84dad9d7 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8953-motorola-potter.dts @@ -0,0 +1,305 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Sireesh Kodali + */ +/dts-v1/; + +#include "msm8953.dtsi" +#include "pm8953.dtsi" +#include "pmi8950.dtsi" + +/delete-node/ &cont_splash_mem; +/delete-node/ &qseecom_mem; + +/ { + model = "Motorola G5 Plus"; + compatible = "motorola,potter", "qcom,msm8953"; + chassis-type = "handset"; + qcom,msm-id = <293 0>; + qcom,board-id = <0x46 0x83a0>; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer@90001000 { + compatible = "simple-framebuffer"; + reg = <0 0x90001000 0 (2220 * 1920 * 3)>; + + width = <1080>; + height = <1920>; + stride = <(1080 * 3)>; + format = "r8g8b8"; + + power-domains = <&gcc MDSS_GDSC>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_BYTE0_CLK>, + <&gcc GCC_MDSS_PCLK0_CLK>, + <&gcc GCC_MDSS_ESC0_CLK>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_key_default>; + + key-volume-up { + label = "Volume Up"; + gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + }; + }; + + reserved-memory { + qseecom_mem: qseecom@84300000 { + reg = <0x0 0x84300000 0x0 0x2000000>; + no-map; + }; + + cont_splash_mem: cont-splash@90001000 { + reg = <0x0 0x90001000 0x0 (1080 * 1920 * 3)>; + no-map; + }; + + reserved@aefd2000 { + reg = <0x0 0xaefd2000 0x0 0x2e000>; + no-map; + }; + + reserved@eefe4000 { + reg = <0x0 0xeefe4000 0x0 0x1c000>; + no-map; + }; + + ramoops@ef000000 { + compatible = "ramoops"; + reg = <0x0 0xef000000 0x0 0x80000>; + console-size = <0x40000>; + ftrace-size = <0>; + record-size = <0x3f800>; + pmsg-size = <0x800>; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-always-on; + regulator-boot-on; + }; +}; + +&hsusb_phy { + vdd-supply = <&pm8953_l3>; + vdda-pll-supply = <&pm8953_l7>; + vdda-phy-dpdm-supply = <&pm8953_l13>; + + status = "okay"; +}; + +&i2c_3 { + status = "okay"; + + touchscreen@20 { + reg = <0x20>; + compatible = "syna,rmi4-i2c"; + + interrupt-parent = <&tlmm>; + interrupts = <65 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-names = "default"; + pinctrl-0 = <&ts_reset>; + + vdd-supply = <&pm8953_l22>; + vio-supply = <&pm8953_l6>; + + syna,reset-delay-ms = <200>; + syna,startup-delay-ms = <500>; + }; +}; + +&pm8953_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; +}; + +&pmi8950_wled { + qcom,current-limit-microamp = <25000>; + qcom,num-strings = <3>; + qcom,external-pfet; + qcom,cabc; + + status = "okay"; +}; + +&rpm_requests { + regulators { + compatible = "qcom,rpm-pm8953-regulators"; + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3-supply = <&vph_pwr>; + vdd_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + vdd_s7-supply = <&vph_pwr>; + vdd_l1-supply = <&pm8953_s3>; + vdd_l2_l3-supply = <&pm8953_s3>; + vdd_l4_l5_l6_l7_l16_l19-supply = <&pm8953_s4>; + vdd_l8_l11_l12_l13_l14_l15-supply = <&vph_pwr>; + vdd_l9_l10_l17_l18_l22-supply = <&vph_pwr>; + + pm8953_s1: s1 { + regulator-min-microvolt = <863000>; + regulator-max-microvolt = <1152000>; + }; + + pm8953_s3: s3 { + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1224000>; + }; + + pm8953_s4: s4 { + regulator-min-microvolt = <1896000>; + regulator-max-microvolt = <2048000>; + }; + + pm8953_l1: l1 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + }; + + pm8953_l2: l2 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + pm8953_l3: l3 { + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <925000>; + regulator-allow-set-load; + }; + + pm8953_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8953_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + pm8953_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + }; + + pm8953_l8: l8 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + }; + + pm8953_l9: l9 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + + pm8953_l10: l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8953_l11: l11 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3000000>; + }; + + pm8953_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + }; + + pm8953_l13: l13 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3125000>; + }; + + pm8953_l15: l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8953_l16: l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8953_l17: l17 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3000000>; + }; + + pm8953_l19: l19 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + }; + + pm8953_l22: l22 { + regulator-always-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2850000>; + }; + + pm8953_l23: l23 { + regulator-min-microvolt = <975000>; + regulator-max-microvolt = <1225000>; + }; + }; +}; + +&sdhc_1 { + vmmc-supply = <&pm8953_l8>; + vqmmc-supply = <&pm8953_l5>; + + status = "okay"; +}; + +&sdhc_2 { + vmmc-supply = <&pm8953_l11>; + vqmmc-supply = <&pm8953_l12>; + + cd-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_off>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <1 2>, <96 4>, <111 1>, <126 1>; + + ts_reset: ts-reset-state { + pins = "gpio64"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; +}; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + dr_mode = "peripheral"; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8953-xiaomi-daisy.dts b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-daisy.dts new file mode 100644 index 000000000000..1d672e608653 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-daisy.dts @@ -0,0 +1,325 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Alejandro Tafalla + */ +/dts-v1/; + +#include "msm8953.dtsi" +#include "pm8953.dtsi" +#include "pmi8950.dtsi" + +/delete-node/ &adsp_fw_mem; +/delete-node/ &qseecom_mem; +/delete-node/ &wcnss_fw_mem; + +/ { + model = "Xiaomi Mi A2 Lite"; + compatible = "xiaomi,daisy", "qcom,msm8953"; + chassis-type = "handset"; + qcom,msm-id = <293 0>; + qcom,board-id= <0x1000b 0x9>; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer@90001000 { + compatible = "simple-framebuffer"; + reg = <0 0x90001000 0 (1920 * 2280 * 3)>; + + width = <1080>; + height = <2280>; + stride = <(1080 * 3)>; + format = "r8g8b8"; + + power-domains = <&gcc MDSS_GDSC>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_BYTE0_CLK>, + <&gcc GCC_MDSS_PCLK0_CLK>, + <&gcc GCC_MDSS_ESC0_CLK>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_key_default>; + + key-volume-up { + label = "Volume Up"; + gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + }; + }; + + reserved-memory { + qseecom_mem: qseecom@84a00000 { + reg = <0x0 0x84a00000 0x0 0x1900000>; + no-map; + }; + + adsp_fw_mem: adsp@8d600000 { + reg = <0x0 0x8d600000 0x0 0x1200000>; + no-map; + }; + + wcnss_fw_mem: wcnss@8e800000 { + reg = <0x0 0x8e800000 0x0 0x700000>; + no-map; + }; + }; + + /* + * We bitbang on &i2c_4 because BLSP is protected by TZ as sensors are + * normally proxied via ADSP firmware. GPIOs aren't protected. + */ + i2c-sensors { + compatible = "i2c-gpio"; + sda-gpios = <&tlmm 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&tlmm 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + + imu@6a { + compatible = "st,lsm6dsl"; + reg = <0x6a>; + vdd-supply = <&pm8953_l10>; + vddio-supply = <&pm8953_l6>; + mount-matrix = "-1", "0", "0", + "0", "-1", "0", + "0", "0", "1"; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-always-on; + regulator-boot-on; + }; +}; + +&hsusb_phy { + vdd-supply = <&pm8953_l3>; + vdda-pll-supply = <&pm8953_l7>; + vdda-phy-dpdm-supply = <&pm8953_l13>; + + status = "okay"; +}; + +&i2c_2 { + status = "okay"; + + speaker_codec: audio-codec@3a { + compatible = "maxim,max98927"; + reg = <0x3a>; + + reset-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>; + + vmon-slot-no = <1>; + imon-slot-no = <1>; + interleave_mode = <0>; + + #sound-dai-cells = <0>; + }; +}; + +&i2c_3 { + status = "okay"; + + touchscreen@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + + interrupt-parent = <&tlmm>; + interrupts = <65 IRQ_TYPE_EDGE_FALLING>; + + reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>; + + vcc-supply = <&pm8953_l10>; + + touchscreen-size-x = <1080>; + touchscreen-size-y = <2280>; + }; +}; + +&pm8953_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; +}; + +&pmi8950_wled { + qcom,current-limit-microamp = <20000>; + qcom,num-strings = <2>; + + status = "okay"; +}; + +&rpm_requests { + regulators { + compatible = "qcom,rpm-pm8953-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3-supply = <&vph_pwr>; + vdd_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + vdd_s7-supply = <&vph_pwr>; + vdd_l1-supply = <&pm8953_s3>; + vdd_l2_l3-supply = <&pm8953_s3>; + vdd_l4_l5_l6_l7_l16_l19-supply = <&pm8953_s4>; + vdd_l8_l11_l12_l13_l14_l15-supply = <&vph_pwr>; + vdd_l9_l10_l17_l18_l22-supply = <&vph_pwr>; + + pm8953_s1: s1 { + regulator-min-microvolt = <863000>; + regulator-max-microvolt = <1152000>; + }; + + pm8953_s3: s3 { + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1224000>; + }; + + pm8953_s4: s4 { + regulator-min-microvolt = <1896000>; + regulator-max-microvolt = <2048000>; + }; + + pm8953_l1: l1 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + }; + + pm8953_l2: l2 { + regulator-min-microvolt = <975000>; + regulator-max-microvolt = <1225000>; + }; + + pm8953_l3: l3 { + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <925000>; + regulator-allow-set-load; + }; + + pm8953_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8953_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + pm8953_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + }; + + pm8953_l8: l8 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + }; + + pm8953_l9: l9 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + + pm8953_l10: l10 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + pm8953_l11: l11 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + }; + + pm8953_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8953_l13: l13 { + regulator-min-microvolt = <3125000>; + regulator-max-microvolt = <3125000>; + }; + + pm8953_l16: l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8953_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8953_l19: l19 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + }; + + pm8953_l22: l22 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + pm8953_l23: l23 { + regulator-min-microvolt = <975000>; + regulator-max-microvolt = <1225000>; + }; + }; +}; + +&sdhc_1 { + vmmc-supply = <&pm8953_l8>; + vqmmc-supply = <&pm8953_l5>; + + status = "okay"; +}; + +&sdhc_2 { + vmmc-supply = <&pm8953_l11>; + vqmmc-supply = <&pm8953_l12>; + + cd-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>, <16 4>, <135 4>; +}; + +&uart_0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart_console_active>; + + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + dr_mode = "peripheral"; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8953-xiaomi-mido.dts b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-mido.dts new file mode 100644 index 000000000000..ed95d09cedb1 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-mido.dts @@ -0,0 +1,329 @@ +// SPDX-License-Identifier: BSD-3-Clause +/dts-v1/; + +#include "msm8953.dtsi" +#include "pm8953.dtsi" +#include "pmi8950.dtsi" +#include <dt-bindings/leds/common.h> + +/delete-node/ &cont_splash_mem; +/delete-node/ &qseecom_mem; + +/ { + model = "Xiaomi Redmi Note 4X"; + compatible = "xiaomi,mido", "qcom,msm8953"; + chassis-type = "handset"; + qcom,msm-id = <293 0>; + qcom,board-id = <11 0>; + + aliases { + mmc0 = &sdhc_1; + mmc1 = &sdhc_2; + }; + + speaker_amp: audio-amplifier { + compatible = "awinic,aw8738"; + mode-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + awinic,mode = <5>; + sound-name-prefix = "Speaker Amp"; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer@90001000 { + compatible = "simple-framebuffer"; + reg = <0 0x90001000 0 (1920 * 1080 * 3)>; + + width = <1080>; + height = <1920>; + stride = <(1080 * 3)>; + format = "r8g8b8"; + + power-domains = <&gcc MDSS_GDSC>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_BYTE0_CLK>, + <&gcc GCC_MDSS_PCLK0_CLK>, + <&gcc GCC_MDSS_ESC0_CLK>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_key_default>; + + key-volume-up { + label = "Volume Up"; + gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + }; + }; + + reserved-memory { + qseecom_mem: qseecom@84a00000 { + reg = <0x0 0x84a00000 0x0 0x1900000>; + no-map; + }; + + cont_splash_mem: cont-splash@90001000 { + reg = <0x0 0x90001000 0x0 (1080 * 1920 * 3)>; + no-map; + }; + + ramoops@9ff00000 { + compatible = "ramoops"; + reg = <0x0 0x9ff00000 0x0 0x00100000>; + console-size = <0x100000>; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&hsusb_phy { + vdd-supply = <&pm8953_l3>; + vdda-pll-supply = <&pm8953_l7>; + vdda-phy-dpdm-supply = <&pm8953_l13>; + + status = "okay"; +}; + +&i2c_2 { + status = "okay"; + + led-controller@45 { + compatible = "awinic,aw2013"; + reg = <0x45>; + + vcc-supply = <&pm8953_l10>; + + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_INDICATOR; + led-max-microamp = <5000>; + }; + + led@1 { + reg = <1>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_INDICATOR; + led-max-microamp = <5000>; + }; + + led@2 { + reg = <2>; + color = <LED_COLOR_ID_BLUE>; + function = LED_FUNCTION_INDICATOR; + led-max-microamp = <5000>; + }; + }; +}; + +&i2c_3 { + status = "okay"; + + touchscreen@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + + interrupt-parent = <&tlmm>; + interrupts = <65 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_active>; + + reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>; + + vcc-supply = <&pm8953_l10>; + + touchscreen-size-x = <1080>; + touchscreen-size-y = <1920>; + }; +}; + +&pm8953_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; +}; + +&rpm_requests { + regulators { + compatible = "qcom,rpm-pm8953-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3-supply = <&vph_pwr>; + vdd_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + vdd_s7-supply = <&vph_pwr>; + vdd_l1-supply = <&pm8953_s3>; + vdd_l2_l3-supply = <&pm8953_s3>; + vdd_l4_l5_l6_l7_l16_l19-supply = <&pm8953_s4>; + vdd_l8_l11_l12_l13_l14_l15-supply = <&vph_pwr>; + vdd_l9_l10_l17_l18_l22-supply = <&vph_pwr>; + vdd_l23-supply = <&pm8953_s3>; + + pm8953_s1: s1 { + regulator-min-microvolt = <863000>; + regulator-max-microvolt = <1152000>; + }; + + pm8953_s3: s3 { + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1224000>; + }; + + pm8953_s4: s4 { + regulator-min-microvolt = <1896000>; + regulator-max-microvolt = <2048000>; + }; + + pm8953_l1: l1 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + }; + + pm8953_l2: l2 { + regulator-min-microvolt = <975000>; + regulator-max-microvolt = <1225000>; + }; + + pm8953_l3: l3 { + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <925000>; + regulator-allow-set-load; + }; + + pm8953_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8953_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + pm8953_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + }; + + pm8953_l8: l8 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + }; + + pm8953_l9: l9 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + + pm8953_l10: l10 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + pm8953_l11: l11 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + }; + + pm8953_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8953_l13: l13 { + regulator-min-microvolt = <3125000>; + regulator-max-microvolt = <3125000>; + }; + + pm8953_l16: l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8953_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8953_l19: l19 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + }; + + pm8953_l22: l22 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + pm8953_l23: l23 { + regulator-min-microvolt = <975000>; + regulator-max-microvolt = <1225000>; + }; + }; +}; + +&sdhc_1 { + vmmc-supply = <&pm8953_l8>; + vqmmc-supply = <&pm8953_l5>; + + status = "okay"; +}; + +&sdhc_2 { + vmmc-supply = <&pm8953_l11>; + vqmmc-supply = <&pm8953_l12>; + + cd-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>, <135 4>; + + ts_int_active: ts-int-active-state { + pins = "gpio65"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; +}; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + dr_mode = "peripheral"; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8953-xiaomi-tissot.dts b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-tissot.dts new file mode 100644 index 000000000000..831d3a42b583 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-tissot.dts @@ -0,0 +1,325 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Danila Tikhonov <JIaxyga@protonmail.com> + * Copyright (c) 2022, Anton Bambura <jenneron@protonmail.com> + */ +/dts-v1/; + +#include "msm8953.dtsi" +#include "pm8953.dtsi" +#include "pmi8950.dtsi" +#include <dt-bindings/leds/common.h> + +/delete-node/ &adsp_fw_mem; +/delete-node/ &qseecom_mem; +/delete-node/ &wcnss_fw_mem; + +/ { + model = "Xiaomi Mi A1"; + compatible = "xiaomi,tissot", "qcom,msm8953"; + chassis-type = "handset"; + qcom,msm-id = <293 0>; + qcom,board-id = <0x1000b 0x00>; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_key_default>, <&gpio_hall_sensor_default>; + + event-hall-sensor { + label = "Hall Effect Sensor"; + gpios = <&tlmm 44 GPIO_ACTIVE_LOW>; + linux,input-type = <EV_SW>; + linux,code = <SW_LID>; + linux,can-disable; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + }; + }; + + reserved-memory { + qseecom_mem: qseecom@84a00000 { + reg = <0x0 0x84a00000 0x0 0x1900000>; + no-map; + }; + + adsp_fw_mem: adsp@8d600000 { + reg = <0x0 0x8d600000 0x0 0x1200000>; + no-map; + }; + + wcnss_fw_mem: wcnss@8e800000 { + reg = <0x0 0x8e800000 0x0 0x700000>; + no-map; + }; + + ramoops@9ff00000 { + compatible = "ramoops"; + reg = <0x0 0x9ff00000 0x0 0x00100000>; + record-size = <0x1000>; + console-size = <0x80000>; + ftrace-size = <0x1000>; + pmsg-size = <0x8000>; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-always-on; + regulator-boot-on; + }; +}; + +&hsusb_phy { + vdd-supply = <&pm8953_l3>; + vdda-pll-supply = <&pm8953_l7>; + vdda-phy-dpdm-supply = <&pm8953_l13>; + + status = "okay"; +}; + +&i2c_2 { + status = "okay"; + + max98927_codec: audio-codec@3a { + compatible = "maxim,max98927"; + reg = <0x3a>; + + reset-gpios = <&tlmm 86 GPIO_ACTIVE_LOW>; + + vmon-slot-no = <1>; + imon-slot-no = <1>; + + #sound-dai-cells = <1>; + }; + + led-controller@45 { + compatible = "awinic,aw2013"; + reg = <0x45>; + + vcc-supply = <&pm8953_l10>; + + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + led-max-microamp = <5000>; + function = LED_FUNCTION_INDICATOR; + color = <LED_COLOR_ID_WHITE>; + }; + }; +}; + +&i2c_3 { + status = "okay"; + + touchscreen@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + + interrupt-parent = <&tlmm>; + interrupts = <65 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_default>; + + reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>; + + vcc-supply = <&pm8953_l10>; + + touchscreen-size-x = <1080>; + touchscreen-size-y = <1920>; + }; +}; + +&pm8953_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; +}; + +&pmi8950_wled { + qcom,num-strings = <2>; + qcom,external-pfet; + qcom,cabc; + + status = "okay"; +}; + +&rpm_requests { + regulators { + compatible = "qcom,rpm-pm8953-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3-supply = <&vph_pwr>; + vdd_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + vdd_s7-supply = <&vph_pwr>; + vdd_l1-supply = <&pm8953_s3>; + vdd_l2_l3-supply = <&pm8953_s3>; + vdd_l4_l5_l6_l7_l16_l19-supply = <&pm8953_s4>; + vdd_l8_l11_l12_l13_l14_l15-supply = <&vph_pwr>; + vdd_l9_l10_l17_l18_l22-supply = <&vph_pwr>; + + pm8953_s1: s1 { + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <1156000>; + }; + + pm8953_s3: s3 { + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1224000>; + }; + + pm8953_s4: s4 { + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <2050000>; + }; + + pm8953_l1: l1 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + pm8953_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1225000>; + }; + + pm8953_l3: l3 { + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <925000>; + }; + + pm8953_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8953_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8953_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + }; + + pm8953_l8: l8 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + }; + + pm8953_l9: l9 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + pm8953_l10:l10 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8953_l11: l11 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + }; + + pm8953_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8953_l13: l13 { + regulator-min-microvolt = <3125000>; + regulator-max-microvolt = <3125000>; + }; + + pm8953_l16: l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8953_l17: l17 { + regulator-min-microvolt = <2750000>; + regulator-max-microvolt = <2850000>; + }; + + pm8953_l19: l19 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + }; + + pm8953_l22: l22 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + pm8953_l23: l23 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1225000>; + }; + }; +}; + +&sdhc_1 { + vmmc-supply = <&pm8953_l8>; + vqmmc-supply = <&pm8953_l5>; + + status = "okay"; +}; + +&sdhc_2 { + vmmc-supply = <&pm8953_l11>; + vqmmc-supply = <&pm8953_l12>; + + cd-gpios = <&tlmm 133 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>, <16 4>, <135 4>; + + gpio_hall_sensor_default: gpio-hall-sensor-state { + pins = "gpio44"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + ts_int_default: ts-int-default-state { + pins = "gpio65"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; +}; + +&uart_0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart_console_active>; + + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + dr_mode = "peripheral"; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8953-xiaomi-vince.dts b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-vince.dts new file mode 100644 index 000000000000..b5be55034fd3 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-vince.dts @@ -0,0 +1,361 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Eugene Lepshy <fekz115@gmail.com> + * Copyright (c) 2022, Gianluca Boiano <morf3089@gmail.com> + */ +/dts-v1/; + +#include "msm8953.dtsi" +#include "pm8953.dtsi" +#include "pmi8950.dtsi" +#include <dt-bindings/leds/common.h> + +/delete-node/ &adsp_fw_mem; +/delete-node/ &cont_splash_mem; +/delete-node/ &qseecom_mem; +/delete-node/ &wcnss_fw_mem; + +/ { + model = "Xiaomi Redmi 5 Plus"; + compatible = "xiaomi,vince", "qcom,msm8953"; + chassis-type = "handset"; + qcom,msm-id = <293 0>; + qcom,board-id= <0x1000b 0x08>; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_key_default>; + + key-volume-up { + label = "volume_up"; + linux,code = <KEY_VOLUMEUP>; + gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; + }; + }; + + reserved-memory { + qseecom_mem: qseecom@84a00000 { + reg = <0x0 0x84a00000 0x0 0x1900000>; + no-map; + }; + + cont_splash_mem: cont-splash@90001000 { + reg = <0x0 0x90001000 0x0 (1080 * 2160 * 3)>; + no-map; + }; + + adsp_fw_mem: adsp@8d600000 { + reg = <0x0 0x8d600000 0x0 0x1200000>; + no-map; + }; + + wcnss_fw_mem: wcnss@8e800000 { + reg = <0x0 0x8e800000 0x0 0x700000>; + no-map; + }; + + ramoops@9ff00000 { + compatible = "ramoops"; + reg = <0x0 0x9ff00000 0x0 0x100000>; + record-size = <0x1000>; + console-size = <0x80000>; + ftrace-size = <0x1000>; + pmsg-size = <0x8000>; + }; + }; + + /* + * We bitbang on &i2c_4 because BLSP is protected by TZ as sensors are + * normally proxied via ADSP firmware. GPIOs aren't protected. + */ + i2c-sensors { + compatible = "i2c-gpio"; + sda-gpios = <&tlmm 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&tlmm 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + + imu@6a { + compatible = "st,lsm6dsl"; + reg = <0x6a>; + vdd-supply = <&pm8953_l10>; + vddio-supply = <&pm8953_l6>; + mount-matrix = "1", "0", "0", + "0", "-1", "0", + "0", "0", "1"; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-always-on; + regulator-boot-on; + }; +}; + +&hsusb_phy { + vdd-supply = <&pm8953_l3>; + vdda-pll-supply = <&pm8953_l7>; + vdda-phy-dpdm-supply = <&pm8953_l13>; + + status = "okay"; +}; + +&i2c_2 { + status = "okay"; + + led-controller@45 { + compatible = "awinic,aw2013"; + reg = <0x45>; + + vcc-supply = <&pm8953_l10>; + + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + led-max-microamp = <5000>; + function = LED_FUNCTION_INDICATOR; + color = <LED_COLOR_ID_WHITE>; + }; + }; +}; + +&i2c_3 { + status = "okay"; + + touchscreen@20 { + reg = <0x20>; + compatible = "syna,rmi4-i2c"; + interrupts-parent = <&tlmm>; + interrupts-extended = <&tlmm 65 IRQ_TYPE_EDGE_FALLING>; + + #address-cells = <1>; + #size-cells = <0>; + + vdd-supply = <&pm8953_l10>; + vio-supply = <&pm8953_l6>; + + pinctrl-names = "init", "suspend"; + pinctrl-0 = <&ts_reset_active &ts_int_active>; + pinctrl-1 = <&ts_reset_suspend &ts_int_suspend>; + syna,reset-delay-ms = <200>; + syna,startup-delay-ms = <500>; + + rmi4-f01@1 { + reg = <0x01>; + syna,nosleep-mode = <1>; + }; + + rmi4-f12@12 { + reg = <0x12>; + syna,rezero-wait-ms = <20>; + syna,sensor-type = <1>; + touchscreen-x-mm = <68>; + touchscreen-y-mm = <122>; + }; + }; +}; + +&pm8953_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; +}; + +&pmi8950_wled { + qcom,current-limit-microamp = <20000>; + qcom,ovp-millivolt = <29600>; + qcom,num-strings = <2>; + qcom,external-pfet; + qcom,cabc; + + status = "okay"; +}; + +&rpm_requests { + regulators { + compatible = "qcom,rpm-pm8953-regulators"; + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3-supply = <&vph_pwr>; + vdd_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + vdd_s7-supply = <&vph_pwr>; + vdd_l1-supply = <&pm8953_s3>; + vdd_l2_l3-supply = <&pm8953_s3>; + vdd_l4_l5_l6_l7_l16_l19-supply = <&pm8953_s4>; + vdd_l8_l11_l12_l13_l14_l15-supply = <&vph_pwr>; + vdd_l9_l10_l17_l18_l22-supply = <&vph_pwr>; + + pm8953_s1: s1 { + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <1156000>; + }; + + pm8953_s3: s3 { + regulator-min-microvolt = <984000>; + regulator-max-microvolt = <1224000>; + }; + + pm8953_s4: s4 { + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <2050000>; + }; + + pm8953_l1: l1 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + }; + + pm8953_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1225000>; + }; + + pm8953_l3: l3 { + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <925000>; + }; + + pm8953_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8953_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8953_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + }; + + pm8953_l8: l8 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + }; + + pm8953_l9: l9 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + + pm8953_l10: l10 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8953_l11: l11 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + }; + + pm8953_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8953_l13: l13 { + regulator-min-microvolt = <3125000>; + regulator-max-microvolt = <3125000>; + }; + + pm8953_l16: l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8953_l17: l17 { + regulator-min-microvolt = <2750000>; + regulator-max-microvolt = <2850000>; + }; + + pm8953_l19: l19 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1380000>; + }; + + pm8953_l22: l22 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + pm8953_l23: l23 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1225000>; + }; + }; +}; + +&sdhc_1 { + vmmc-supply = <&pm8953_l8>; + vqmmc-supply = <&pm8953_l5>; + + status = "okay"; +}; + +&sdhc_2 { + vmmc-supply = <&pm8953_l11>; + vqmmc-supply = <&pm8953_l12>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>, <16 4>, <135 4>; + + ts_reset_active: ts-reset-active-state { + pins = "gpio64"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + ts_reset_suspend: ts-reset-suspend-state { + pins = "gpio64"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + ts_int_active: ts-int-active-state { + pins = "gpio65"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + ts_int_suspend: ts-int-suspend-state { + pins = "gpio65"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; +}; + +&uart_0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart_console_active>; + + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + dr_mode = "peripheral"; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index 32349174c4bd..4e17bc9f8167 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -42,13 +42,6 @@ capacity-dmips-mhz = <1024>; next-level-cache = <&L2_0>; #cooling-cells = <2>; - - l1-icache { - compatible = "cache"; - }; - l1-dcache { - compatible = "cache"; - }; }; CPU1: cpu@1 { @@ -59,13 +52,6 @@ capacity-dmips-mhz = <1024>; next-level-cache = <&L2_0>; #cooling-cells = <2>; - - l1-icache { - compatible = "cache"; - }; - l1-dcache { - compatible = "cache"; - }; }; CPU2: cpu@2 { @@ -76,13 +62,6 @@ capacity-dmips-mhz = <1024>; next-level-cache = <&L2_0>; #cooling-cells = <2>; - - l1-icache { - compatible = "cache"; - }; - l1-dcache { - compatible = "cache"; - }; }; CPU3: cpu@3 { @@ -93,13 +72,6 @@ capacity-dmips-mhz = <1024>; next-level-cache = <&L2_0>; #cooling-cells = <2>; - - l1-icache { - compatible = "cache"; - }; - l1-dcache { - compatible = "cache"; - }; }; CPU4: cpu@100 { @@ -110,13 +82,6 @@ capacity-dmips-mhz = <1024>; next-level-cache = <&L2_1>; #cooling-cells = <2>; - - l1-icache { - compatible = "cache"; - }; - l1-dcache { - compatible = "cache"; - }; }; CPU5: cpu@101 { @@ -127,13 +92,6 @@ capacity-dmips-mhz = <1024>; next-level-cache = <&L2_1>; #cooling-cells = <2>; - - l1-icache { - compatible = "cache"; - }; - l1-dcache { - compatible = "cache"; - }; }; CPU6: cpu@102 { @@ -144,13 +102,6 @@ capacity-dmips-mhz = <1024>; next-level-cache = <&L2_1>; #cooling-cells = <2>; - - l1-icache { - compatible = "cache"; - }; - l1-dcache { - compatible = "cache"; - }; }; CPU7: cpu@103 { @@ -161,13 +112,6 @@ capacity-dmips-mhz = <1024>; next-level-cache = <&L2_1>; #cooling-cells = <2>; - - l1-icache { - compatible = "cache"; - }; - l1-dcache { - compatible = "cache"; - }; }; cpu-map { @@ -202,12 +146,12 @@ }; }; - L2_0: l2-cache_0 { + L2_0: l2-cache-0 { compatible = "cache"; cache-level = <2>; }; - L2_1: l2-cache_1 { + L2_1: l2-cache-1 { compatible = "cache"; cache-level = <2>; }; @@ -245,18 +189,18 @@ #size-cells = <2>; ranges; - zap_shader_region: memory@81800000 { + zap_shader_region: zap@81800000 { compatible = "shared-dma-pool"; reg = <0x0 0x81800000 0x0 0x2000>; no-map; }; - memory@85b00000 { + qseecom_mem: qseecom@85b00000 { reg = <0x0 0x85b00000 0x0 0x800000>; no-map; }; - smem_mem: memory@86300000 { + smem_mem: smem@86300000 { compatible = "qcom,smem"; reg = <0x0 0x86300000 0x0 0x100000>; qcom,rpm-msg-ram = <&rpm_msg_ram>; @@ -264,47 +208,47 @@ no-map; }; - memory@86400000 { + reserved@86400000 { reg = <0x0 0x86400000 0x0 0x400000>; no-map; }; - mpss_mem: memory@86c00000 { + mpss_mem: mpss@86c00000 { reg = <0x0 0x86c00000 0x0 0x6a00000>; no-map; }; - adsp_fw_mem: memory@8d600000 { + adsp_fw_mem: adsp@8d600000 { reg = <0x0 0x8d600000 0x0 0x1100000>; no-map; }; - wcnss_fw_mem: memory@8e700000 { + wcnss_fw_mem: wcnss@8e700000 { reg = <0x0 0x8e700000 0x0 0x700000>; no-map; }; - memory@90000000 { + dfps_data_mem: dfps-data@90000000 { reg = <0 0x90000000 0 0x1000>; no-map; }; - memory@90001000 { + cont_splash_mem: cont-splash@90001000 { reg = <0x0 0x90001000 0x0 0x13ff000>; no-map; }; - venus_mem: memory@91400000 { + venus_mem: venus@91400000 { reg = <0x0 0x91400000 0x0 0x700000>; no-map; }; - mba_mem: memory@92000000 { + mba_mem: mba@92000000 { reg = <0x0 0x92000000 0x0 0x100000>; no-map; }; - memory@f2d00000 { + rmtfs@f2d00000 { compatible = "qcom,rmtfs-mem"; reg = <0x0 0xf2d00000 0x0 0x180000>; no-map; @@ -726,7 +670,7 @@ reg = <0x193f044 0x4>; }; - mdss: mdss@1a00000 { + mdss: display-subsystem@1a00000 { compatible = "qcom,mdss"; reg = <0x1a00000 0x1000>, @@ -755,7 +699,7 @@ status = "disabled"; - mdp: mdp@1a01000 { + mdp: display-controller@1a01000 { compatible = "qcom,msm8953-mdp5", "qcom,mdp5"; reg = <0x1a01000 0x89000>; reg-names = "mdp_phys"; @@ -797,7 +741,7 @@ }; dsi0: dsi@1a94000 { - compatible = "qcom,mdss-dsi-ctrl"; + compatible = "qcom,msm8953-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0x1a94000 0x400>; reg-names = "dsi_ctrl"; @@ -867,7 +811,7 @@ }; dsi1: dsi@1a96000 { - compatible = "qcom,mdss-dsi-ctrl"; + compatible = "qcom,msm8953-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0x1a96000 0x400>; reg-names = "dsi_ctrl"; diff --git a/arch/arm64/boot/dts/qcom/msm8956.dtsi b/arch/arm64/boot/dts/qcom/msm8956.dtsi index e432512d8716..668e05185c21 100644 --- a/arch/arm64/boot/dts/qcom/msm8956.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8956.dtsi @@ -12,6 +12,10 @@ interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; }; +&tsens { + compatible = "qcom,msm8956-tsens", "qcom,tsens-v1"; +}; + /* * You might be wondering.. why is it so empty out there? * Well, the SoCs are almost identical. diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi index 05dcb30b0779..2d360d05aa5e 100644 --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi @@ -481,8 +481,129 @@ #address-cells = <1>; #size-cells = <1>; - tsens_caldata: caldata@218 { - reg = <0x218 0x18>; + tsens_base1: base1@218 { + reg = <0x218 1>; + bits = <0 8>; + }; + + tsens_s0_p1: s0-p1@219 { + reg = <0x219 0x1>; + bits = <0 6>; + }; + + tsens_s0_p2: s0-p2@219 { + reg = <0x219 0x2>; + bits = <6 6>; + }; + + tsens_s1_p1: s1-p1@21a { + reg = <0x21a 0x2>; + bits = <4 6>; + }; + + tsens_s1_p2: s1-p2@21b { + reg = <0x21b 0x1>; + bits = <2 6>; + }; + + tsens_s2_p1: s2-p1@21c { + reg = <0x21c 0x1>; + bits = <0 6>; + }; + + tsens_s2_p2: s2-p2@21c { + reg = <0x21c 0x2>; + bits = <6 6>; + }; + + tsens_s3_p1: s3-p1@21d { + reg = <0x21d 0x2>; + bits = <4 6>; + }; + + tsens_s3_p2: s3-p2@21e { + reg = <0x21e 0x1>; + bits = <2 6>; + }; + + tsens_base2: base2@220 { + reg = <0x220 1>; + bits = <0 8>; + }; + + tsens_s4_p1: s4-p1@221 { + reg = <0x221 0x1>; + bits = <0 6>; + }; + + tsens_s4_p2: s4-p2@221 { + reg = <0x221 0x2>; + bits = <6 6>; + }; + + tsens_s5_p1: s5-p1@222 { + reg = <0x222 0x2>; + bits = <4 6>; + }; + + tsens_s5_p2: s5-p2@223 { + reg = <0x224 0x1>; + bits = <2 6>; + }; + + tsens_s6_p1: s6-p1@224 { + reg = <0x224 0x1>; + bits = <0 6>; + }; + + tsens_s6_p2: s6-p2@224 { + reg = <0x224 0x2>; + bits = <6 6>; + }; + + tsens_s7_p1: s7-p1@225 { + reg = <0x225 0x2>; + bits = <4 6>; + }; + + tsens_s7_p2: s7-p2@226 { + reg = <0x226 0x2>; + bits = <2 6>; + }; + + tsens_mode: mode@228 { + reg = <0x228 1>; + bits = <0 3>; + }; + + tsens_s8_p1: s8-p1@228 { + reg = <0x228 0x2>; + bits = <3 6>; + }; + + tsens_s8_p2: s8-p2@229 { + reg = <0x229 0x1>; + bits = <1 6>; + }; + + tsens_s9_p1: s9-p1@229 { + reg = <0x229 0x2>; + bits = <7 6>; + }; + + tsens_s9_p2: s9-p2@22a { + reg = <0x22a 0x2>; + bits = <5 6>; + }; + + tsens_s10_p1: s10-p1@22b { + reg = <0x22b 0x2>; + bits = <3 6>; + }; + + tsens_s10_p2: s10-p2@22c { + reg = <0x22c 0x1>; + bits = <1 6>; }; }; @@ -492,8 +613,32 @@ <0x004a8000 0x1000>; /* SROT */ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "uplow"; - nvmem-cells = <&tsens_caldata>; - nvmem-cell-names = "calib"; + nvmem-cells = <&tsens_mode>, + <&tsens_base1>, <&tsens_base2>, + <&tsens_s0_p1>, <&tsens_s0_p2>, + <&tsens_s1_p1>, <&tsens_s1_p2>, + <&tsens_s2_p1>, <&tsens_s2_p2>, + <&tsens_s3_p1>, <&tsens_s3_p2>, + <&tsens_s4_p1>, <&tsens_s4_p2>, + <&tsens_s5_p1>, <&tsens_s5_p2>, + <&tsens_s6_p1>, <&tsens_s6_p2>, + <&tsens_s7_p1>, <&tsens_s7_p2>, + <&tsens_s8_p1>, <&tsens_s8_p2>, + <&tsens_s9_p1>, <&tsens_s9_p2>, + <&tsens_s10_p1>, <&tsens_s10_p2>; + nvmem-cell-names = "mode", + "base1", "base2", + "s0_p1", "s0_p2", + "s1_p1", "s1_p2", + "s2_p1", "s2_p2", + "s3_p1", "s3_p2", + "s4_p1", "s4_p2", + "s5_p1", "s5_p2", + "s6_p1", "s6_p2", + "s7_p1", "s7_p2", + "s8_p1", "s8_p2", + "s9_p1", "s9_p2", + "s10_p1", "s10_p2"; #qcom,sensors = <11>; #thermal-sensor-cells = <1>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi b/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi index 87c90e93667f..4bceb362a5c0 100644 --- a/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi @@ -2,7 +2,8 @@ /* * Copyright (c) 2015, LGE Inc. All rights reserved. * Copyright (c) 2016, The Linux Foundation. All rights reserved. - * Copyright (c) 2021, Petr Vorel <petr.vorel@gmail.com> + * Copyright (c) 2021-2022, Petr Vorel <petr.vorel@gmail.com> + * Copyright (c) 2022, Dominik Kobinski <dominikkobinski314@gmail.com> */ /dts-v1/; @@ -14,6 +15,9 @@ /* cont_splash_mem has different memory mapping */ /delete-node/ &cont_splash_mem; +/* disabled on downstream, conflicts with cont_splash_mem */ +/delete-node/ &dfps_data_mem; + / { model = "LG Nexus 5X"; compatible = "lg,bullhead", "qcom,msm8992"; @@ -48,7 +52,12 @@ }; cont_splash_mem: memory@3400000 { - reg = <0 0x03400000 0 0x1200000>; + reg = <0 0x03400000 0 0xc00000>; + no-map; + }; + + removed_region: reserved@5000000 { + reg = <0 0x05000000 0 0x2200000>; no-map; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts b/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts index b242c272d2af..fcca1ba94da6 100644 --- a/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts +++ b/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts @@ -11,6 +11,12 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/gpio-keys.h> +/delete-node/ &adsp_mem; +/delete-node/ &audio_mem; +/delete-node/ &mpss_mem; +/delete-node/ &peripheral_region; +/delete-node/ &rmtfs_mem; + / { model = "Xiaomi Mi 4C"; compatible = "xiaomi,libra", "qcom,msm8992"; @@ -70,25 +76,67 @@ #size-cells = <2>; ranges; - /* This is for getting crash logs using Android downstream kernels */ - ramoops@dfc00000 { - compatible = "ramoops"; - reg = <0x0 0xdfc00000 0x0 0x40000>; - console-size = <0x10000>; - record-size = <0x10000>; - ftrace-size = <0x10000>; - pmsg-size = <0x20000>; + memory_hole: hole@6400000 { + reg = <0 0x06400000 0 0x600000>; + no-map; + }; + + memory_hole2: hole2@6c00000 { + reg = <0 0x06c00000 0 0x2400000>; + no-map; + }; + + mpss_mem: mpss@9000000 { + reg = <0 0x09000000 0 0x5a00000>; + no-map; + }; + + tzapp: tzapp@ea00000 { + reg = <0 0x0ea00000 0 0x1900000>; + no-map; + }; + + mdm_rfsa_mem: mdm-rfsa@ca0b0000 { + reg = <0 0xca0b0000 0 0x10000>; + no-map; + }; + + rmtfs_mem: rmtfs@ca100000 { + compatible = "qcom,rmtfs-mem"; + reg = <0 0xca100000 0 0x180000>; + no-map; + + qcom,client-id = <1>; }; - modem_region: modem_region@9000000 { - reg = <0x0 0x9000000 0x0 0x5a00000>; + audio_mem: audio@cb400000 { + reg = <0 0xcb000000 0 0x400000>; + no-mem; + }; + + qseecom_mem: qseecom@cb400000 { + reg = <0 0xcb400000 0 0x1c00000>; + no-mem; + }; + + adsp_rfsa_mem: adsp-rfsa@cd000000 { + reg = <0 0xcd000000 0 0x10000>; no-map; }; - tzapp: modem_region@ea00000 { - reg = <0x0 0xea00000 0x0 0x1900000>; + sensor_rfsa_mem: sensor-rfsa@cd010000 { + reg = <0 0xcd010000 0 0x10000>; no-map; }; + + ramoops@dfc00000 { + compatible = "ramoops"; + reg = <0 0xdfc00000 0 0x40000>; + console-size = <0x10000>; + record-size = <0x10000>; + ftrace-size = <0x10000>; + pmsg-size = <0x20000>; + }; }; }; @@ -130,11 +178,6 @@ status = "okay"; }; -&peripheral_region { - reg = <0x0 0x7400000 0x0 0x1c00000>; - no-map; -}; - &pm8994_spmi_regulators { VDD_APC0: s8 { regulator-min-microvolt = <680000>; diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi index 10adb4986ef1..02fc3795dbfd 100644 --- a/arch/arm64/boot/dts/qcom/msm8992.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi @@ -37,10 +37,6 @@ compatible = "qcom,rpmcc-msm8992", "qcom,rpmcc"; }; -&tcsr_mutex { - compatible = "qcom,sfpb-mutex"; -}; - &timer { interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, diff --git a/arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts b/arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts index 85abff0e9b3f..7b0f62144c3e 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts +++ b/arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts @@ -9,9 +9,6 @@ #include "msm8994.dtsi" -/* Angler's firmware does not report where the memory is allocated */ -/delete-node/ &cont_splash_mem; - / { model = "Huawei Nexus 6P"; compatible = "huawei,angler", "qcom,msm8994"; @@ -28,6 +25,22 @@ chosen { stdout-path = "serial0:115200n8"; }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + tzapp_mem: tzapp@4800000 { + reg = <0 0x04800000 0 0x1900000>; + no-map; + }; + + removed_region: reserved@6300000 { + reg = <0 0x06300000 0 0xD00000>; + no-map; + }; + }; }; &blsp1_uart2 { diff --git a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi index 9b67f0d3820c..4520a7e86d5b 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi @@ -127,98 +127,98 @@ */ uefi_mem: memory@200000 { - reg = <0 0x200000 0 0x100000>; + reg = <0 0x00200000 0 0x100000>; no-map; }; mppark_mem: memory@300000 { - reg = <0 0x300000 0 0x80000>; + reg = <0 0x00300000 0 0x80000>; no-map; }; fbpt_mem: memory@380000 { - reg = <0 0x380000 0 0x1000>; + reg = <0 0x00380000 0 0x1000>; no-map; }; dbg2_mem: memory@381000 { - reg = <0 0x381000 0 0x4000>; + reg = <0 0x00381000 0 0x4000>; no-map; }; capsule_mem: memory@385000 { - reg = <0 0x385000 0 0x1000>; + reg = <0 0x00385000 0 0x1000>; no-map; }; tpmctrl_mem: memory@386000 { - reg = <0 0x386000 0 0x3000>; + reg = <0 0x00386000 0 0x3000>; no-map; }; uefiinfo_mem: memory@389000 { - reg = <0 0x389000 0 0x1000>; + reg = <0 0x00389000 0 0x1000>; no-map; }; reset_mem: memory@389000 { - reg = <0 0x389000 0 0x1000>; + reg = <0 0x00389000 0 0x1000>; no-map; }; resuncached_mem: memory@38e000 { - reg = <0 0x38e000 0 0x72000>; + reg = <0 0x0038e000 0 0x72000>; no-map; }; disp_mem: memory@400000 { - reg = <0 0x400000 0 0x800000>; + reg = <0 0x00400000 0 0x800000>; no-map; }; uefistack_mem: memory@c00000 { - reg = <0 0xc00000 0 0x40000>; + reg = <0 0x00c00000 0 0x40000>; no-map; }; cpuvect_mem: memory@c40000 { - reg = <0 0xc40000 0 0x10000>; + reg = <0 0x00c40000 0 0x10000>; no-map; }; rescached_mem: memory@400000 { - reg = <0 0xc50000 0 0xb0000>; + reg = <0 0x00c50000 0 0xb0000>; no-map; }; tzapps_mem: memory@6500000 { - reg = <0 0x6500000 0 0x500000>; + reg = <0 0x06500000 0 0x500000>; no-map; }; smem_mem: memory@6a00000 { - reg = <0 0x6a00000 0 0x200000>; + reg = <0 0x06a00000 0 0x200000>; no-map; }; hyp_mem: memory@6c00000 { - reg = <0 0x6c00000 0 0x100000>; + reg = <0 0x06c00000 0 0x100000>; no-map; }; tz_mem: memory@6d00000 { - reg = <0 0x6d00000 0 0x160000>; + reg = <0 0x06d00000 0 0x160000>; no-map; }; rfsa_adsp_mem: memory@6e60000 { - reg = <0 0x6e60000 0 0x10000>; + reg = <0 0x06e60000 0 0x10000>; no-map; }; rfsa_mpss_mem: memory@6e70000 { compatible = "qcom,rmtfs-mem"; - reg = <0 0x6e70000 0 0x10000>; + reg = <0 0x06e70000 0 0x10000>; no-map; qcom,client-id = <1>; @@ -229,7 +229,7 @@ * MPSS_EFS / SBL */ mba_mem: memory@6e80000 { - reg = <0 0x6e80000 0 0x180000>; + reg = <0 0x06e80000 0 0x180000>; no-map; }; @@ -239,33 +239,33 @@ */ mpss_mem: memory@7000000 { - reg = <0 0x7000000 0 0x5a00000>; + reg = <0 0x07000000 0 0x5a00000>; no-map; }; adsp_mem: memory@ca00000 { - reg = <0 0xca00000 0 0x1800000>; + reg = <0 0x0ca00000 0 0x1800000>; no-map; }; venus_mem: memory@e200000 { - reg = <0 0xe200000 0 0x500000>; + reg = <0 0x0e200000 0 0x500000>; no-map; }; pil_metadata_mem: memory@e700000 { - reg = <0 0xe700000 0 0x4000>; + reg = <0 0x0e700000 0 0x4000>; no-map; }; memory@e704000 { - reg = <0 0xe704000 0 0x7fc000>; + reg = <0 0x0e704000 0 0x7fc000>; no-map; }; /* Peripheral Image loader region end */ cnss_mem: memory@ef00000 { - reg = <0 0xef00000 0 0x300000>; + reg = <0 0x0ef00000 0 0x300000>; no-map; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi index f3d153c34918..3ceb86b06209 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi @@ -163,7 +163,7 @@ * mainline Linux. */ &cont_splash_mem { - reg = <0 0x3401000 0 0x2200000>; + reg = <0 0x03401000 0 0x2200000>; }; &pmi8994_spmi_regulators { diff --git a/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi index 20f5c103c63b..2994337c6046 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi @@ -179,7 +179,6 @@ }; &dsi0_phy { - vdda-supply = <&vreg_l2a_1p25>; vcca-supply = <&vreg_l28a_0p925>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi index dec361b93cce..7f4d493a55ff 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi @@ -24,11 +24,7 @@ qcom,board-id = <8 0>; chosen { - /* - * Due to an unknown-for-a-few-years regression, - * SDHCI only works on MSM8996 in PIO (lame) mode. - */ - bootargs = "sdhci.debug_quirks=0x40 sdhci.debug_quirks2=0x4 maxcpus=2"; + bootargs = "maxcpus=2"; }; reserved-memory { @@ -104,8 +100,8 @@ }; &blsp1_i2c3 { - status = "okay"; clock-frequency = <355000>; + status = "okay"; tof_sensor: vl53l0x@29 { compatible = "st,vl53l0x"; @@ -118,15 +114,15 @@ }; &blsp2_i2c5 { - status = "okay"; clock-frequency = <355000>; + status = "okay"; /* FUSB301 USB-C controller */ }; &blsp2_i2c6 { - status = "okay"; clock-frequency = <355000>; + status = "okay"; synaptics@2c { compatible = "syna,rmi4-i2c"; @@ -183,11 +179,10 @@ }; &hsusb_phy1 { - status = "okay"; - vdd-supply = <&pm8994_l28>; vdda-pll-supply = <&pm8994_l12>; vdda-phy-dpdm-supply = <&pm8994_l24>; + status = "okay"; }; &mmcc { @@ -195,18 +190,17 @@ }; &pcie0 { - status = "okay"; perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; vddpe-3v3-supply = <&wlan_en>; vdda-supply = <&pm8994_l28>; + status = "okay"; }; &pcie_phy { - status = "okay"; - vdda-phy-supply = <&pm8994_l28>; vdda-pll-supply = <&pm8994_l12>; + status = "okay"; }; &pm8994_gpios { @@ -478,8 +472,8 @@ }; &pm8994_resin { - status = "okay"; linux,code = <KEY_VOLUMEUP>; + status = "okay"; }; &pmi8994_gpios { @@ -623,9 +617,9 @@ }; &pmi8994_wled { - status = "okay"; default-brightness = <512>; qcom,num-strings = <3>; + status = "okay"; }; &rpm_requests { @@ -825,21 +819,18 @@ }; &sdhc1 { - /* eMMC doesn't seem to cooperate even in PIO mode.. */ - status = "disabled"; - vmmc-supply = <&pm8994_l20>; vqmmc-supply = <&pm8994_s4>; mmc-hs400-1_8v; mmc-hs200-1_8v; + status = "okay"; }; &sdhc2 { - status = "okay"; - cd-gpios = <&tlmm 40 GPIO_ACTIVE_HIGH>; vmmc-supply = <&pm8994_l21>; vqmmc-supply = <&pm8994_l13>; + status = "okay"; }; &tlmm { @@ -943,18 +934,15 @@ }; }; -/* - * For reasons that are currently unknown (but probably related to fusb301), USB takes about - * 6 minutes to wake up (nothing interesting in kernel logs), but then it works as it should. - */ &usb3 { - status = "okay"; qcom,select-utmi-as-pipe-clk; + status = "okay"; }; &usb3_dwc3 { extcon = <&usb3_id>; dr_mode = "peripheral"; + maximum-speed = "high-speed"; phys = <&hsusb_phy1>; phy-names = "usb2-phy"; snps,hird-threshold = /bits/ 8 <0>; diff --git a/arch/arm64/boot/dts/qcom/msm8996-v3.0.dtsi b/arch/arm64/boot/dts/qcom/msm8996-v3.0.dtsi index 5728583af41e..929bdcd45d02 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-v3.0.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-v3.0.dtsi @@ -19,7 +19,7 @@ * features get enabled upstream. */ -gpu_opp_table_3_0: gpu-opp-table-30 { +gpu_opp_table_3_0: opp-table-gpu30 { compatible = "operating-points-v2"; opp-624000000 { diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts index d8734913482f..100123d51494 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts @@ -54,7 +54,7 @@ reg = <0x30>; #address-cells = <1>; #size-cells = <0>; - enable-gpio = <&pm8994_gpios 7 1>; + enable-gpios = <&pm8994_gpios 7 1>; clock-mode = /bits/8 <2>; label = "button-backlight"; @@ -62,14 +62,14 @@ reg = <0>; chan-name = "button-backlight"; led-cur = /bits/ 8 <0x32>; - max-cur = /bits/ 8 <0xC8>; + max-cur = /bits/ 8 <0xc8>; }; led@1 { reg = <0>; chan-name = "button-backlight1"; led-cur = /bits/ 8 <0x32>; - max-cur = /bits/ 8 <0xC8>; + max-cur = /bits/ 8 <0xc8>; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index d31464204f69..55180586f7b6 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -462,6 +462,12 @@ reg = <0x0 0x91500000 0x0 0x200000>; no-map; }; + + mdata_mem: mpss-metadata { + alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>; + size = <0x0 0x4000>; + no-map; + }; }; rpm-glink { @@ -720,7 +726,9 @@ <&pciephy_1>, <&pciephy_2>, <&ssusb_phy_0>, - <0>, <0>, <0>; + <&ufsphy_lane 0>, + <&ufsphy_lane 1>, + <&ufsphy_lane 2>; clock-names = "cxo", "cxo2", "sleep_clk", @@ -830,9 +838,11 @@ compatible = "qcom,msm8996-a2noc"; reg = <0x00583000 0x7000>; #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; + clock-names = "bus", "bus_a", "aggre2_ufs_axi", "ufs_axi"; clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>, - <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>; + <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>, + <&gcc GCC_AGGRE2_UFS_AXI_CLK>, + <&gcc GCC_UFS_AXI_CLK>; }; mnoc: interconnect@5a4000 { @@ -904,7 +914,7 @@ <825000000>; }; - mdss: mdss@900000 { + mdss: display-subsystem@900000 { compatible = "qcom,mdss"; reg = <0x00900000 0x1000>, @@ -930,8 +940,8 @@ status = "disabled"; - mdp: mdp@901000 { - compatible = "qcom,mdp5"; + mdp: display-controller@901000 { + compatible = "qcom,msm8996-mdp5", "qcom,mdp5"; reg = <0x00901000 0x90000>; reg-names = "mdp_phys"; @@ -989,7 +999,8 @@ }; dsi0: dsi@994000 { - compatible = "qcom,mdss-dsi-ctrl"; + compatible = "qcom,msm8996-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; reg = <0x00994000 0x400>; reg-names = "dsi_ctrl"; @@ -1056,7 +1067,8 @@ }; dsi1: dsi@996000 { - compatible = "qcom,mdss-dsi-ctrl"; + compatible = "qcom,msm8996-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; reg = <0x00996000 0x400>; reg-names = "dsi_ctrl"; @@ -1246,23 +1258,23 @@ }; opp-510000000 { opp-hz = /bits/ 64 <510000000>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; opp-401800000 { opp-hz = /bits/ 64 <401800000>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; opp-315000000 { opp-hz = /bits/ 64 <315000000>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; opp-214000000 { opp-hz = /bits/ 64 <214000000>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; opp-133000000 { opp-hz = /bits/ 64 <133000000>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; }; @@ -1814,7 +1826,7 @@ #interrupt-cells = <4>; }; - agnoc@0 { + bus@0 { power-domains = <&gcc AGGRE0_NOC_GDSC>; compatible = "simple-pm-bus"; #address-cells = <1>; @@ -2048,6 +2060,7 @@ reg = <0x627400 0x12c>, <0x627600 0x200>, <0x627c00 0x1b4>; + #clock-cells = <1>; #phy-cells = <0>; }; }; @@ -2458,6 +2471,10 @@ memory-region = <&mpss_mem>; }; + metadata { + memory-region = <&mdata_mem>; + }; + smd-edge { interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; @@ -2940,8 +2957,8 @@ compatible = "qcom,msm8996-apcc"; reg = <0x06400000 0x90000>; - clock-names = "xo"; - clocks = <&rpmcc RPM_SMD_BB_CLK1>; + clock-names = "xo", "sys_apcs_aux"; + clocks = <&rpmcc RPM_SMD_BB_CLK1>, <&apcs_glb>; #clock-cells = <1>; }; @@ -3288,7 +3305,7 @@ status = "disabled"; }; - blsp2_spi6: spi@75ba000{ + blsp2_spi6: spi@75ba000 { compatible = "qcom,spi-qup-v2.2.1"; reg = <0x075ba000 0x600>; interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; @@ -3356,7 +3373,7 @@ slim_msm: slim-ngd@91c0000 { compatible = "qcom,slim-ngd-v1.5.0"; - reg = <0x091c0000 0x2C000>; + reg = <0x091c0000 0x2c000>; interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>; dmas = <&slimbam 3>, <&slimbam 4>; dma-names = "rx", "tx"; @@ -3426,8 +3443,7 @@ mboxes = <&apcs_glb 8>; qcom,smd-edge = <1>; qcom,remote-pid = <2>; - #address-cells = <1>; - #size-cells = <0>; + apr { power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>; compatible = "qcom,apr-v2"; @@ -3485,6 +3501,7 @@ reg = <0x09820000 0x1000>; #mbox-cells = <1>; + #clock-cells = <0>; }; timer@9840000 { @@ -3580,7 +3597,7 @@ type = "passive"; }; - cpu0_crit: cpu_crit { + cpu0_crit: cpu-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -3601,7 +3618,7 @@ type = "passive"; }; - cpu1_crit: cpu_crit { + cpu1_crit: cpu-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -3622,7 +3639,7 @@ type = "passive"; }; - cpu2_crit: cpu_crit { + cpu2_crit: cpu-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -3643,7 +3660,7 @@ type = "passive"; }; - cpu3_crit: cpu_crit { + cpu3_crit: cpu-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; diff --git a/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts b/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts index 310f7a2df1e8..5aad9f05780a 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts @@ -113,7 +113,7 @@ <&cam_snapshot_pin_a>; button-vol-up { label = "Volume Up"; - gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; + gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>; linux,input-type = <EV_KEY>; linux,code = <KEY_VOLUMEUP>; gpio-key,wakeup; @@ -122,7 +122,7 @@ button-camera-snapshot { label = "Camera Snapshot"; - gpios = <&pm8998_gpio 7 GPIO_ACTIVE_LOW>; + gpios = <&pm8998_gpios 7 GPIO_ACTIVE_LOW>; linux,input-type = <EV_KEY>; linux,code = <KEY_CAMERA>; debounce-interval = <15>; @@ -130,7 +130,7 @@ button-camera-focus { label = "Camera Focus"; - gpios = <&pm8998_gpio 8 GPIO_ACTIVE_LOW>; + gpios = <&pm8998_gpios 8 GPIO_ACTIVE_LOW>; linux,input-type = <EV_KEY>; linux,code = <KEY_CAMERA_FOCUS>; debounce-interval = <15>; @@ -249,7 +249,7 @@ reg = <0x14>; interrupt-parent = <&tlmm>; interrupts = <125 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>; + reset-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>; AVDD28-supply = <&vreg_l28_3p0>; VDDIO-supply = <&ts_vio_vreg>; pinctrl-names = "active"; @@ -338,7 +338,7 @@ }; }; -&pm8998_gpio { +&pm8998_gpios { vol_up_pin_a: vol-up-active-state { pins = "gpio6"; function = "normal"; @@ -364,14 +364,9 @@ }; }; -&pm8998_pon { - resin { - compatible = "qcom,pm8941-resin"; - interrupts = <GIC_SPI 0x8 1 IRQ_TYPE_EDGE_BOTH>; - bias-pull-up; - debounce = <15625>; - linux,code = <KEY_VOLUMEDOWN>; - }; +&pm8998_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; }; &qusb2phy { diff --git a/arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dts b/arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dts index 9fb1fb9b8529..d36b36af49d0 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dts @@ -23,7 +23,7 @@ pinctrl-0 = <&button_backlight_default>; led-keypad-backlight { - gpios = <&pmi8998_gpio 5 GPIO_ACTIVE_HIGH>; + gpios = <&pmi8998_gpios 5 GPIO_ACTIVE_HIGH>; color = <LED_COLOR_ID_WHITE>; function = LED_FUNCTION_KBD_BACKLIGHT; default-state = "off"; @@ -31,7 +31,7 @@ }; }; -&pmi8998_gpio { +&pmi8998_gpios { button_backlight_default: button-backlight-state { pins = "gpio5"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi index 7d4a67d07501..ce03c7c239e5 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi @@ -92,7 +92,7 @@ button-vol-down { label = "Volume down"; - gpios = <&pm8998_gpio 5 GPIO_ACTIVE_LOW>; + gpios = <&pm8998_gpios 5 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEDOWN>; debounce-interval = <15>; wakeup-source; @@ -100,7 +100,7 @@ button-vol-up { label = "Volume up"; - gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; + gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; debounce-interval = <15>; wakeup-source; @@ -269,7 +269,7 @@ }; }; -&pm8998_gpio { +&pm8998_gpios { vol_keys_default: vol-keys-state { pins = "gpio5", "gpio6"; function = "normal"; diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts index 20fe0394a3c1..1868ad649415 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts @@ -20,7 +20,7 @@ regulator-max-microvolt = <1350000>; startup-delay-us = <0>; enable-active-high; - gpio = <&pmi8998_gpio 10 GPIO_ACTIVE_HIGH>; + gpio = <&pmi8998_gpios 10 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&disp_dvdd_en>; }; @@ -37,7 +37,7 @@ qcom,soft-start-us = <200>; }; -&pmi8998_gpio { +&pmi8998_gpios { disp_dvdd_en: disp-dvdd-en-active-state { pins = "gpio10"; function = "normal"; diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi index 5da87baa2b23..820414758888 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi @@ -25,7 +25,7 @@ pinctrl-names = "default"; clocks = <&rpmcc RPM_SMD_DIV_CLK1>; #clock-cells = <0>; - enable-gpios = <&pm8998_gpio 13 GPIO_ACTIVE_HIGH>; + enable-gpios = <&pm8998_gpios 13 GPIO_ACTIVE_HIGH>; }; }; @@ -65,7 +65,7 @@ regulator-name = "cam_vio_vreg"; startup-delay-us = <0>; enable-active-high; - gpio = <&pmi8998_gpio 1 GPIO_ACTIVE_HIGH>; + gpio = <&pmi8998_gpios 1 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&cam_vio_default>; vin-supply = <&vreg_lvs1a_1p8>; @@ -103,7 +103,7 @@ <&cam_snapshot_pin_a>; button-vol-down { label = "Volume Down"; - gpios = <&pm8998_gpio 5 GPIO_ACTIVE_LOW>; + gpios = <&pm8998_gpios 5 GPIO_ACTIVE_LOW>; linux,input-type = <EV_KEY>; linux,code = <KEY_VOLUMEDOWN>; gpio-key,wakeup; @@ -112,7 +112,7 @@ button-camera-snapshot { label = "Camera Snapshot"; - gpios = <&pm8998_gpio 7 GPIO_ACTIVE_LOW>; + gpios = <&pm8998_gpios 7 GPIO_ACTIVE_LOW>; linux,input-type = <EV_KEY>; linux,code = <KEY_CAMERA>; debounce-interval = <15>; @@ -120,7 +120,7 @@ button-camera-focus { label = "Camera Focus"; - gpios = <&pm8998_gpio 8 GPIO_ACTIVE_LOW>; + gpios = <&pm8998_gpios 8 GPIO_ACTIVE_LOW>; linux,input-type = <EV_KEY>; linux,code = <KEY_CAMERA_FOCUS>; debounce-interval = <15>; @@ -187,7 +187,7 @@ vibrator { compatible = "gpio-vibrator"; - enable-gpios = <&pmi8998_gpio 5 GPIO_ACTIVE_HIGH>; + enable-gpios = <&pmi8998_gpios 5 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&vib_default>; }; @@ -303,7 +303,7 @@ }; }; -&pm8998_gpio { +&pm8998_gpios { vol_down_pin_a: vol-down-active-state { pins = "gpio5"; function = PMIC_GPIO_FUNC_NORMAL; @@ -335,7 +335,7 @@ }; }; -&pmi8998_gpio { +&pmi8998_gpios { cam_vio_default: cam-vio-active-state { pins = "gpio1"; function = PMIC_GPIO_FUNC_NORMAL; @@ -357,14 +357,9 @@ }; }; -&pm8998_pon { - resin { - compatible = "qcom,pm8941-resin"; - interrupts = <GIC_SPI 0x8 1 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = <KEY_VOLUMEUP>; - }; +&pm8998_resin { + linux,code = <KEY_VOLUMEUP>; + status = "okay"; }; &qusb2phy { diff --git a/arch/arm64/boot/dts/qcom/msm8998-xiaomi-sagit.dts b/arch/arm64/boot/dts/qcom/msm8998-xiaomi-sagit.dts index b1aac7311ef9..7956b151c7a4 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-xiaomi-sagit.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-xiaomi-sagit.dts @@ -133,7 +133,7 @@ key-vol-up { label = "Volume up"; - gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; + gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; debounce-interval = <15>; wakeup-source; @@ -278,7 +278,7 @@ }; }; -&pm8998_gpio { +&pm8998_gpios { vol_up_key_default: vol-up-key-default-state { pins = "gpio6"; function = "normal"; diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 539382dab0ad..8bc1c59127e5 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -108,6 +108,12 @@ reg = <0x0 0x95700000 0x0 0x100000>; no-map; }; + + mdata_mem: mpss-metadata { + alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>; + size = <0x0 0x4000>; + no-map; + }; }; clocks { @@ -465,7 +471,7 @@ type = "passive"; }; - cpu0_crit: cpu_crit { + cpu0_crit: cpu-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -486,7 +492,7 @@ type = "passive"; }; - cpu1_crit: cpu_crit { + cpu1_crit: cpu-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -507,7 +513,7 @@ type = "passive"; }; - cpu2_crit: cpu_crit { + cpu2_crit: cpu-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -528,7 +534,7 @@ type = "passive"; }; - cpu3_crit: cpu_crit { + cpu3_crit: cpu-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -549,7 +555,7 @@ type = "passive"; }; - cpu4_crit: cpu_crit { + cpu4_crit: cpu-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -570,7 +576,7 @@ type = "passive"; }; - cpu5_crit: cpu_crit { + cpu5_crit: cpu-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -591,7 +597,7 @@ type = "passive"; }; - cpu6_crit: cpu_crit { + cpu6_crit: cpu-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -612,7 +618,7 @@ type = "passive"; }; - cpu7_crit: cpu_crit { + cpu7_crit: cpu-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -808,7 +814,7 @@ reg = <0x00100000 0xb0000>; clock-names = "xo", "sleep_clk"; - clocks = <&xo>, <&sleep_clk>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; /* * The hypervisor typically configures the memory region where these clocks @@ -1357,6 +1363,10 @@ memory-region = <&mpss_mem>; }; + metadata { + memory-region = <&mdata_mem>; + }; + glink-edge { interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>; label = "modem"; @@ -1394,43 +1404,43 @@ opp-710000097 { opp-hz = /bits/ 64 <710000097>; opp-level = <RPM_SMD_LEVEL_TURBO>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; opp-670000048 { opp-hz = /bits/ 64 <670000048>; opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; opp-596000097 { opp-hz = /bits/ 64 <596000097>; opp-level = <RPM_SMD_LEVEL_NOM>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; opp-515000097 { opp-hz = /bits/ 64 <515000097>; opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; opp-414000000 { opp-hz = /bits/ 64 <414000000>; opp-level = <RPM_SMD_LEVEL_SVS>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; opp-342000000 { opp-hz = /bits/ 64 <342000000>; opp-level = <RPM_SMD_LEVEL_LOW_SVS>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; opp-257000000 { opp-hz = /bits/ 64 <257000000>; opp-level = <RPM_SMD_LEVEL_MIN_SVS>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; }; }; @@ -2088,7 +2098,7 @@ clock-names = "iface", "core", "xo"; clocks = <&gcc GCC_SDCC2_AHB_CLK>, <&gcc GCC_SDCC2_APPS_CLK>, - <&xo>; + <&rpmcc RPM_SMD_XO_CLK_SRC>; bus-width = <4>; status = "disabled"; }; @@ -2398,8 +2408,7 @@ "dsi1byte", "hdmipll", "dplink", - "dpvco", - "core_bi_pll_test_se"; + "dpvco"; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GCC_MMSS_GPLL0_CLK>, <0>, @@ -2408,7 +2417,6 @@ <0>, <0>, <0>, - <0>, <0>; }; diff --git a/arch/arm64/boot/dts/qcom/pm6125.dtsi b/arch/arm64/boot/dts/qcom/pm6125.dtsi index 1c8ccda26ffb..59092a551a16 100644 --- a/arch/arm64/boot/dts/qcom/pm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6125.dtsi @@ -136,11 +136,11 @@ status = "disabled"; }; - pm6125_gpio: gpio@c000 { + pm6125_gpios: gpio@c000 { compatible = "qcom,pm6125-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; - gpio-ranges = <&pm6125_gpio 0 0 9>; + gpio-ranges = <&pm6125_gpios 0 0 9>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/pm6150.dtsi b/arch/arm64/boot/dts/qcom/pm6150.dtsi index 3d91fb405ca2..2e6afa296141 100644 --- a/arch/arm64/boot/dts/qcom/pm6150.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6150.dtsi @@ -88,11 +88,11 @@ status = "disabled"; }; - pm6150_gpio: gpio@c000 { + pm6150_gpios: gpio@c000 { compatible = "qcom,pm6150-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; - gpio-ranges = <&pm6150_gpio 0 0 10>; + gpio-ranges = <&pm6150_gpios 0 0 10>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/pm6150l.dtsi b/arch/arm64/boot/dts/qcom/pm6150l.dtsi index 90aac61ad264..6f7aa67501e2 100644 --- a/arch/arm64/boot/dts/qcom/pm6150l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6150l.dtsi @@ -95,11 +95,11 @@ status = "disabled"; }; - pm6150l_gpio: gpio@c000 { + pm6150l_gpios: gpio@c000 { compatible = "qcom,pm6150l-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; - gpio-ranges = <&pm6150l_gpio 0 0 12>; + gpio-ranges = <&pm6150l_gpios 0 0 12>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; @@ -112,6 +112,12 @@ #address-cells = <1>; #size-cells = <0>; + pm6150l_flash: led-controller@d300 { + compatible = "qcom,pm6150l-flash-led", "qcom,spmi-flash-led"; + reg = <0xd300>; + status = "disabled"; + }; + pm6150l_wled: leds@d800 { compatible = "qcom,pm6150l-wled"; reg = <0xd800>, <0xd900>; diff --git a/arch/arm64/boot/dts/qcom/pm7250b.dtsi b/arch/arm64/boot/dts/qcom/pm7250b.dtsi index 61f7a6345150..d709d955a2f5 100644 --- a/arch/arm64/boot/dts/qcom/pm7250b.dtsi +++ b/arch/arm64/boot/dts/qcom/pm7250b.dtsi @@ -110,6 +110,14 @@ label = "chg_mid"; }; + adc-chan@4b { + reg = <ADC5_BAT_ID_100K_PU>; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,ratiometric; + label = "bat_id"; + }; + adc-chan@83 { reg = <ADC5_VPH_PWR>; qcom,pre-scaling = <1 3>; diff --git a/arch/arm64/boot/dts/qcom/pm8005.dtsi b/arch/arm64/boot/dts/qcom/pm8005.dtsi index 8d4b081b4e9d..0f0ab2da8305 100644 --- a/arch/arm64/boot/dts/qcom/pm8005.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8005.dtsi @@ -11,11 +11,11 @@ #address-cells = <1>; #size-cells = <0>; - pm8005_gpio: gpio@c000 { + pm8005_gpios: gpio@c000 { compatible = "qcom,pm8005-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; - gpio-ranges = <&pm8005_gpio 0 0 4>; + gpio-ranges = <&pm8005_gpios 0 0 4>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/pm8010.dtsi b/arch/arm64/boot/dts/qcom/pm8010.dtsi new file mode 100644 index 000000000000..0ea641e12209 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm8010.dtsi @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Linaro Limited + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/spmi/spmi.h> + +/ { + thermal-zones { + pm8010-m-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pm8010_m_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + + pm8010-n-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pm8010_n_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + }; +}; + + +&spmi_bus { + pm8010_m: pmic@c { + compatible = "qcom,pm8010", "qcom,spmi-pmic"; + reg = <0xc SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8010_m_temp_alarm: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0xc 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + }; + + pm8010_n: pmic@d { + compatible = "qcom,pm8010", "qcom,spmi-pmic"; + reg = <0xd SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8010_n_temp_alarm: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0xd 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pm8150.dtsi b/arch/arm64/boot/dts/qcom/pm8150.dtsi index 574fa95a2871..db90c55fa2cf 100644 --- a/arch/arm64/boot/dts/qcom/pm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150.dtsi @@ -121,7 +121,7 @@ rtc@6000 { compatible = "qcom,pm8941-rtc"; - reg = <0x6000>; + reg = <0x6000>, <0x6100>; reg-names = "rtc", "alarm"; interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; }; diff --git a/arch/arm64/boot/dts/qcom/pm8550.dtsi b/arch/arm64/boot/dts/qcom/pm8550.dtsi new file mode 100644 index 000000000000..46396ec1a330 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm8550.dtsi @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Linaro Limited + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/spmi/spmi.h> + +/ { + thermal-zones { + pm8550-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pm8550_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + }; +}; + + +&spmi_bus { + pm8550: pmic@1 { + compatible = "qcom,pm8550", "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8550_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm8550_gpios: gpio@8800 { + compatible = "qcom,pm8550-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pm8550_gpios 0 0 12>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pm8550b.dtsi b/arch/arm64/boot/dts/qcom/pm8550b.dtsi new file mode 100644 index 000000000000..16bcfb64d735 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm8550b.dtsi @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Linaro Limited + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/spmi/spmi.h> + +/ { + thermal-zones { + pm8550b-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pm8550b_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + }; +}; + + +&spmi_bus { + pm8550b: pmic@7 { + compatible = "qcom,pm8550", "qcom,spmi-pmic"; + reg = <0x7 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8550b_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x7 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm8550b_gpios: gpio@8800 { + compatible = "qcom,pm8550b-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pm8550b_gpios 0 0 12>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pm8550ve.dtsi b/arch/arm64/boot/dts/qcom/pm8550ve.dtsi new file mode 100644 index 000000000000..c47646a467be --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm8550ve.dtsi @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Linaro Limited + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/spmi/spmi.h> + +/ { + thermal-zones { + pm8550ve-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pm8550ve_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + }; +}; + + +&spmi_bus { + pm8550ve: pmic@5 { + compatible = "qcom,pm8550", "qcom,spmi-pmic"; + reg = <0x5 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8550ve_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x5 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm8550ve_gpios: gpio@8800 { + compatible = "qcom,pm8550ve-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pm8550ve_gpios 0 0 8>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pm8550vs.dtsi b/arch/arm64/boot/dts/qcom/pm8550vs.dtsi new file mode 100644 index 000000000000..97b1c18aa7d8 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm8550vs.dtsi @@ -0,0 +1,194 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Linaro Limited + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/spmi/spmi.h> + +/ { + thermal-zones { + pm8550vs-c-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pm8550vs_c_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + + pm8550vs-d-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pm8550vs_d_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + + pm8550vs-e-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pm8550vs_e_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + + pm8550vs-g-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pm8550vs_g_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + }; +}; + + +&spmi_bus { + pm8550vs_c: pmic@2 { + compatible = "qcom,pm8550", "qcom,spmi-pmic"; + reg = <0x2 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8550vs_c_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm8550vs_c_gpios: gpio@8800 { + compatible = "qcom,pm8550vs-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pm8550vs_c_gpios 0 0 6>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pm8550vs_d: pmic@3 { + compatible = "qcom,pm8550", "qcom,spmi-pmic"; + reg = <0x3 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8550vs_d_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm8550vs_d_gpios: gpio@8800 { + compatible = "qcom,pm8550vs-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pm8550vs_d_gpios 0 0 6>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pm8550vs_e: pmic@4 { + compatible = "qcom,pm8550", "qcom,spmi-pmic"; + reg = <0x4 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8550vs_e_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm8550vs_e_gpios: gpio@8800 { + compatible = "qcom,pm8550vs-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pm8550vs_e_gpios 0 0 6>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pm8550vs_g: pmic@6 { + compatible = "qcom,pm8550", "qcom,spmi-pmic"; + reg = <0x6 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8550vs_g_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x6 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm8550vs_g_gpios: gpio@8800 { + compatible = "qcom,pm8550vs-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pm8550vs_g_gpios 0 0 6>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pm8916.dtsi b/arch/arm64/boot/dts/qcom/pm8916.dtsi index 08f9ca006e72..e2a6b66d8847 100644 --- a/arch/arm64/boot/dts/qcom/pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8916.dtsi @@ -93,7 +93,8 @@ rtc@6000 { compatible = "qcom,pm8941-rtc"; - reg = <0x6000>; + reg = <0x6000>, <0x6100>; + reg-names = "rtc", "alarm"; interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; }; diff --git a/arch/arm64/boot/dts/qcom/pm8950.dtsi b/arch/arm64/boot/dts/qcom/pm8950.dtsi index 07c3896bd36f..5ec38b7e335a 100644 --- a/arch/arm64/boot/dts/qcom/pm8950.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8950.dtsi @@ -126,7 +126,7 @@ rtc@6000 { compatible = "qcom,pm8941-rtc"; - reg = <0x6000>; + reg = <0x6000>, <0x6100>; reg-names = "rtc", "alarm"; interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; }; @@ -141,11 +141,11 @@ #interrupt-cells = <2>; }; - pm8950_gpio: gpio@c000 { + pm8950_gpios: gpio@c000 { compatible = "qcom,pm8950-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; - gpio-ranges = <&pm8950_gpio 0 0 8>; + gpio-ranges = <&pm8950_gpios 0 0 8>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/pm8998.dtsi b/arch/arm64/boot/dts/qcom/pm8998.dtsi index 6a5854333b2b..adbba9f4089a 100644 --- a/arch/arm64/boot/dts/qcom/pm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8998.dtsi @@ -109,11 +109,11 @@ interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; }; - pm8998_gpio: gpio@c000 { + pm8998_gpios: gpio@c000 { compatible = "qcom,pm8998-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; - gpio-ranges = <&pm8998_gpio 0 0 26>; + gpio-ranges = <&pm8998_gpios 0 0 26>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/pmi8950.dtsi b/arch/arm64/boot/dts/qcom/pmi8950.dtsi index 32d27e2187e3..4891be3cd68a 100644 --- a/arch/arm64/boot/dts/qcom/pmi8950.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi8950.dtsi @@ -47,7 +47,7 @@ adc-chan@a { reg = <VADC_REF_1250MV>; qcom,pre-scaling = <1 1>; - label = "ref_1250v"; + label = "ref_1250mv"; }; adc-chan@d { @@ -67,11 +67,11 @@ #interrupt-cells = <2>; }; - pmi8950_gpio: gpio@c000 { + pmi8950_gpios: gpio@c000 { compatible = "qcom,pmi8950-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; - gpio-ranges = <&pmi8950_gpio 0 0 2>; + gpio-ranges = <&pmi8950_gpios 0 0 2>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/pmi8998.dtsi b/arch/arm64/boot/dts/qcom/pmi8998.dtsi index cd1caeae8281..ffe587f281d8 100644 --- a/arch/arm64/boot/dts/qcom/pmi8998.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi8998.dtsi @@ -9,11 +9,11 @@ #address-cells = <1>; #size-cells = <0>; - pmi8998_gpio: gpio@c000 { + pmi8998_gpios: gpio@c000 { compatible = "qcom,pmi8998-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; - gpio-ranges = <&pmi8998_gpio 0 0 14>; + gpio-ranges = <&pmi8998_gpios 0 0 14>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/pmk8550.dtsi b/arch/arm64/boot/dts/qcom/pmk8550.dtsi new file mode 100644 index 000000000000..47213d05bf92 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmk8550.dtsi @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Linaro Limited + */ + +#include <dt-bindings/input/input.h> +#include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/spmi/spmi.h> + +&spmi_bus { + pmk8550: pmic@0 { + compatible = "qcom,pm8550", "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmk8550_pon: pon@1300 { + compatible = "qcom,pm8998-pon"; + reg = <0x1300>, <0x800>; + reg-names = "hlos", "pbs"; + + pon_pwrkey: pwrkey { + compatible = "qcom,pmk8350-pwrkey"; + interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>; + linux,code = <KEY_POWER>; + status = "disabled"; + }; + + pon_resin: resin { + compatible = "qcom,pmk8350-resin"; + interrupts = <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>; + status = "disabled"; + }; + }; + + pmk8550_rtc: rtc@6100 { + compatible = "qcom,pmk8350-rtc"; + reg = <0x6100>, <0x6200>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + }; + + pmk8550_gpios: gpio@8800 { + compatible = "qcom,pmk8550-gpio", "qcom,spmi-gpio"; + reg = <0xb800>; + gpio-controller; + gpio-ranges = <&pmk8550_gpios 0 0 6>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi b/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi index 20c5d60c8c2c..ee1e428d3a6e 100644 --- a/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi +++ b/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi @@ -108,7 +108,7 @@ pmm8155au_1_rtc: rtc@6000 { compatible = "qcom,pm8941-rtc"; - reg = <0x6000>; + reg = <0x6000>, <0x6100>; reg-names = "rtc", "alarm"; interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; diff --git a/arch/arm64/boot/dts/qcom/pmp8074.dtsi b/arch/arm64/boot/dts/qcom/pmp8074.dtsi index ceb2e6358b3d..580684411d74 100644 --- a/arch/arm64/boot/dts/qcom/pmp8074.dtsi +++ b/arch/arm64/boot/dts/qcom/pmp8074.dtsi @@ -74,7 +74,7 @@ pmp8074_rtc: rtc@6000 { compatible = "qcom,pm8941-rtc"; - reg = <0x6000>; + reg = <0x6000>, <0x6100>; reg-names = "rtc", "alarm"; interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; allow-set-time; diff --git a/arch/arm64/boot/dts/qcom/pmr735d.dtsi b/arch/arm64/boot/dts/qcom/pmr735d.dtsi new file mode 100644 index 000000000000..41fb664a10b3 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmr735d.dtsi @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Linaro Limited + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/spmi/spmi.h> + +/ { + thermal-zones { + pmr735d-k-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pmr735d_k_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + + pmr735d-l-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pmr735d_l_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + }; +}; + + +&spmi_bus { + pmr735d_k: pmic@a { + compatible = "qcom,pmr735d", "qcom,spmi-pmic"; + reg = <0xa SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmr735d_k_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0xa 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmr735d_k_gpios: gpio@8800 { + compatible = "qcom,pmr735d-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmr735d_k_gpios 0 0 2>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmr735d_l: pmic@b { + compatible = "qcom,pmr735d", "qcom,spmi-pmic"; + reg = <0xb SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmr735d_l_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0xb 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmr735d_l_gpios: gpio@8800 { + compatible = "qcom,pmr735d-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmr735d_l_gpios 0 0 2>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pms405.dtsi b/arch/arm64/boot/dts/qcom/pms405.dtsi index ffe9e33808d0..22edb47c6a84 100644 --- a/arch/arm64/boot/dts/qcom/pms405.dtsi +++ b/arch/arm64/boot/dts/qcom/pms405.dtsi @@ -125,7 +125,7 @@ rtc@6000 { compatible = "qcom,pm8941-rtc"; - reg = <0x6000>; + reg = <0x6000>, <0x6100>; reg-names = "rtc", "alarm"; interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; }; diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index a5324eecb50a..9c9890cf1b10 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -230,6 +230,8 @@ rpmcc: clock-controller { compatible = "qcom,rpmcc-qcs404", "qcom,rpmcc"; #clock-cells = <1>; + clocks = <&xo_board>; + clock-names = "xo"; }; rpmpd: power-controller { @@ -366,13 +368,126 @@ reg = <0x000a4000 0x1000>; #address-cells = <1>; #size-cells = <1>; - tsens_caldata: caldata@d0 { - reg = <0x1f8 0x14>; - }; cpr_efuse_speedbin: speedbin@13c { reg = <0x13c 0x4>; bits = <2 3>; }; + + tsens_s0_p1: s0-p1@1f8 { + reg = <0x1f8 0x1>; + bits = <0 6>; + }; + + tsens_s0_p2: s0-p2@1f8 { + reg = <0x1f8 0x2>; + bits = <6 6>; + }; + + tsens_s1_p1: s1-p1@1f9 { + reg = <0x1f9 0x2>; + bits = <4 6>; + }; + + tsens_s1_p2: s1-p2@1fa { + reg = <0x1fa 0x1>; + bits = <2 6>; + }; + + tsens_s2_p1: s2-p1@1fb { + reg = <0x1fb 0x1>; + bits = <0 6>; + }; + + tsens_s2_p2: s2-p2@1fb { + reg = <0x1fb 0x2>; + bits = <6 6>; + }; + + tsens_s3_p1: s3-p1@1fc { + reg = <0x1fc 0x2>; + bits = <4 6>; + }; + + tsens_s3_p2: s3-p2@1fd { + reg = <0x1fd 0x1>; + bits = <2 6>; + }; + + tsens_s4_p1: s4-p1@1fe { + reg = <0x1fe 0x1>; + bits = <0 6>; + }; + + tsens_s4_p2: s4-p2@1fe { + reg = <0x1fe 0x2>; + bits = <6 6>; + }; + + tsens_s5_p1: s5-p1@200 { + reg = <0x200 0x1>; + bits = <0 6>; + }; + + tsens_s5_p2: s5-p2@200 { + reg = <0x200 0x2>; + bits = <6 6>; + }; + + tsens_s6_p1: s6-p1@201 { + reg = <0x201 0x2>; + bits = <4 6>; + }; + + tsens_s6_p2: s6-p2@202 { + reg = <0x202 0x1>; + bits = <2 6>; + }; + + tsens_s7_p1: s7-p1@203 { + reg = <0x203 0x1>; + bits = <0 6>; + }; + + tsens_s7_p2: s7-p2@203 { + reg = <0x203 0x2>; + bits = <6 6>; + }; + + tsens_s8_p1: s8-p1@204 { + reg = <0x204 0x2>; + bits = <4 6>; + }; + + tsens_s8_p2: s8-p2@205 { + reg = <0x205 0x1>; + bits = <2 6>; + }; + + tsens_s9_p1: s9-p1@206 { + reg = <0x206 0x1>; + bits = <0 6>; + }; + + tsens_s9_p2: s9-p2@206 { + reg = <0x206 0x2>; + bits = <6 6>; + }; + + tsens_mode: mode@208 { + reg = <0x208 1>; + bits = <0 3>; + }; + + tsens_base1: base1@208 { + reg = <0x208 2>; + bits = <3 8>; + }; + + tsens_base2: base2@208 { + reg = <0x209 2>; + bits = <3 8>; + }; + cpr_efuse_quot_offset1: qoffset1@231 { reg = <0x231 0x4>; bits = <4 7>; @@ -447,8 +562,30 @@ compatible = "qcom,qcs404-tsens", "qcom,tsens-v1"; reg = <0x004a9000 0x1000>, /* TM */ <0x004a8000 0x1000>; /* SROT */ - nvmem-cells = <&tsens_caldata>; - nvmem-cell-names = "calib"; + nvmem-cells = <&tsens_mode>, + <&tsens_base1>, <&tsens_base2>, + <&tsens_s0_p1>, <&tsens_s0_p2>, + <&tsens_s1_p1>, <&tsens_s1_p2>, + <&tsens_s2_p1>, <&tsens_s2_p2>, + <&tsens_s3_p1>, <&tsens_s3_p2>, + <&tsens_s4_p1>, <&tsens_s4_p2>, + <&tsens_s5_p1>, <&tsens_s5_p2>, + <&tsens_s6_p1>, <&tsens_s6_p2>, + <&tsens_s7_p1>, <&tsens_s7_p2>, + <&tsens_s8_p1>, <&tsens_s8_p2>, + <&tsens_s9_p1>, <&tsens_s9_p2>; + nvmem-cell-names = "mode", + "base1", "base2", + "s0_p1", "s0_p2", + "s1_p1", "s1_p2", + "s2_p1", "s2_p2", + "s3_p1", "s3_p2", + "s4_p1", "s4_p2", + "s5_p1", "s5_p2", + "s6_p1", "s6_p2", + "s7_p1", "s7_p2", + "s8_p1", "s8_p2", + "s9_p1", "s9_p2"; #qcom,sensors = <10>; interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "uplow"; @@ -485,27 +622,31 @@ interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; - clocks = <&xo_board>, - <&gcc GCC_CDSP_CFG_AHB_CLK>, - <&gcc GCC_CDSP_TBU_CLK>, - <&gcc GCC_BIMC_CDSP_CLK>, - <&turingcc TURING_WRAPPER_AON_CLK>, - <&turingcc TURING_Q6SS_AHBS_AON_CLK>, - <&turingcc TURING_Q6SS_AHBM_AON_CLK>, - <&turingcc TURING_Q6SS_Q6_AXIM_CLK>; - clock-names = "xo", - "sway", - "tbu", - "bimc", - "ahb_aon", - "q6ss_slave", - "q6ss_master", - "q6_axim"; - - resets = <&gcc GCC_CDSP_RESTART>; - reset-names = "restart"; - - qcom,halt-regs = <&tcsr 0x19004>; + clocks = <&xo_board>; + clock-names = "xo"; + + /* + * If the node was using the PIL binding, then include properties: + * clocks = <&xo_board>, + * <&gcc GCC_CDSP_CFG_AHB_CLK>, + * <&gcc GCC_CDSP_TBU_CLK>, + * <&gcc GCC_BIMC_CDSP_CLK>, + * <&turingcc TURING_WRAPPER_AON_CLK>, + * <&turingcc TURING_Q6SS_AHBS_AON_CLK>, + * <&turingcc TURING_Q6SS_AHBM_AON_CLK>, + * <&turingcc TURING_Q6SS_Q6_AXIM_CLK>; + * clock-names = "xo", + * "sway", + * "tbu", + * "bimc", + * "ahb_aon", + * "q6ss_slave", + * "q6ss_master", + * "q6_axim"; + * resets = <&gcc GCC_CDSP_RESTART>; + * reset-names = "restart"; + * qcom,halt-regs = <&tcsr 0x19004>; + */ memory-region = <&cdsp_fw_mem>; @@ -729,6 +870,14 @@ reg = <0x01800000 0x80000>; #clock-cells = <1>; #reset-cells = <1>; + #power-domain-cells = <1>; + + clocks = <&xo_board>, + <&sleep_clk>, + <&pcie_phy>, + <0>, + <0>, + <0>; assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>; assigned-clock-rates = <19200000>; @@ -806,10 +955,11 @@ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, - <&gcc 21>; + <&gcc GCC_PCIE_0_PIPE_ARES>; reset-names = "phy", "pipe"; clock-output-names = "pcie_0_pipe_clk"; + #clock-cells = <0>; #phy-cells = <0>; status = "disabled"; @@ -1336,12 +1486,12 @@ <&gcc GCC_PCIE_0_SLV_AXI_CLK>; clock-names = "iface", "aux", "master_bus", "slave_bus"; - resets = <&gcc 18>, - <&gcc 17>, - <&gcc 15>, - <&gcc 19>, + resets = <&gcc GCC_PCIE_0_AXI_MASTER_ARES>, + <&gcc GCC_PCIE_0_AXI_SLAVE_ARES>, + <&gcc GCC_PCIE_0_AXI_MASTER_STICKY_ARES>, + <&gcc GCC_PCIE_0_CORE_STICKY_ARES>, <&gcc GCC_PCIE_0_BCR>, - <&gcc 16>; + <&gcc GCC_PCIE_0_AHB_ARES>; reset-names = "axi_m", "axi_s", "axi_m_sticky", @@ -1502,7 +1652,7 @@ hysteresis = <2000>; type = "passive"; }; - cluster_crit: cluster_crit { + cluster_crit: cluster-crit { temperature = <120000>; hysteresis = <2000>; type = "critical"; @@ -1536,7 +1686,7 @@ hysteresis = <2000>; type = "passive"; }; - cpu0_crit: cpu_crit { + cpu0_crit: cpu-crit { temperature = <120000>; hysteresis = <2000>; type = "critical"; @@ -1570,7 +1720,7 @@ hysteresis = <2000>; type = "passive"; }; - cpu1_crit: cpu_crit { + cpu1_crit: cpu-crit { temperature = <120000>; hysteresis = <2000>; type = "critical"; @@ -1604,7 +1754,7 @@ hysteresis = <2000>; type = "passive"; }; - cpu2_crit: cpu_crit { + cpu2_crit: cpu-crit { temperature = <120000>; hysteresis = <2000>; type = "critical"; @@ -1638,7 +1788,7 @@ hysteresis = <2000>; type = "passive"; }; - cpu3_crit: cpu_crit { + cpu3_crit: cpu-crit { temperature = <120000>; hysteresis = <2000>; type = "critical"; diff --git a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts index f41dcc379dce..eafdfbbf40b9 100644 --- a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts @@ -23,7 +23,7 @@ stdout-path = "serial0:115200n8"; }; - vreg_3p3: vreg_3p3_regulator { + vreg_3p3: vreg-3p3-regulator { compatible = "regulator-fixed"; regulator-name = "vreg_3p3"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts index 84cb6f3eeb56..bb4270e8f551 100644 --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts @@ -11,18 +11,103 @@ #include <dt-bindings/spmi/spmi.h> #include "sa8540p.dtsi" +#include "sa8540p-pmics.dtsi" / { model = "Qualcomm SA8295P ADP"; compatible = "qcom,sa8295p-adp", "qcom,sa8540p"; aliases { - serial0 = &qup2_uart17; + serial0 = &uart17; }; chosen { stdout-path = "serial0:115200n8"; }; + + dp2-connector { + compatible = "dp-connector"; + label = "DP2"; + type = "mini"; + + hpd-gpios = <&tlmm 20 GPIO_ACTIVE_HIGH>; + + port { + dp2_connector_in: endpoint { + remote-endpoint = <&mdss1_dp0_phy_out>; + }; + }; + }; + + dp3-connector { + compatible = "dp-connector"; + label = "DP3"; + type = "mini"; + + hpd-gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>; + + port { + dp3_connector_in: endpoint { + remote-endpoint = <&mdss1_dp1_phy_out>; + }; + }; + }; + + edp0-connector { + compatible = "dp-connector"; + label = "EDP0"; + type = "mini"; + + hpd-gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>; + + port { + edp0_connector_in: endpoint { + remote-endpoint = <&mdss0_dp2_phy_out>; + }; + }; + }; + + edp1-connector { + compatible = "dp-connector"; + label = "EDP1"; + type = "mini"; + + hpd-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>; + + port { + edp1_connector_in: endpoint { + remote-endpoint = <&mdss0_dp3_phy_out>; + }; + }; + }; + + edp2-connector { + compatible = "dp-connector"; + label = "EDP2"; + type = "mini"; + + hpd-gpios = <&tlmm 7 GPIO_ACTIVE_HIGH>; + + port { + edp2_connector_in: endpoint { + remote-endpoint = <&mdss1_dp2_phy_out>; + }; + }; + }; + + edp3-connector { + compatible = "dp-connector"; + label = "EDP3"; + type = "mini"; + + hpd-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>; + + port { + edp3_connector_in: endpoint { + remote-endpoint = <&mdss1_dp3_phy_out>; + }; + }; + }; }; &apps_rsc { @@ -159,13 +244,168 @@ vreg_l8g: ldo8 { regulator-name = "vreg_l8g"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; + + vreg_l11g: ldo11 { + regulator-name = "vreg_l11g"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; +}; + +&dispcc0 { + status = "okay"; +}; + +&dispcc1 { + status = "okay"; +}; + +&mdss0 { + status = "okay"; +}; + +&mdss0_dp2 { + data-lanes = <0 1 2 3>; + + status = "okay"; + + ports { + port@1 { + reg = <1>; + mdss0_dp2_phy_out: endpoint { + remote-endpoint = <&edp0_connector_in>; + }; + }; }; }; +&mdss0_dp2_phy { + vdda-phy-supply = <&vreg_l8g>; + vdda-pll-supply = <&vreg_l3g>; + + status = "okay"; +}; + +&mdss0_dp3 { + data-lanes = <0 1 2 3>; + + status = "okay"; + + ports { + port@1 { + reg = <1>; + mdss0_dp3_phy_out: endpoint { + remote-endpoint = <&edp1_connector_in>; + }; + }; + }; +}; + +&mdss0_dp3_phy { + vdda-phy-supply = <&vreg_l8g>; + vdda-pll-supply = <&vreg_l3g>; + + status = "okay"; +}; + +&mdss1 { + status = "okay"; +}; + +&mdss1_dp0 { + data-lanes = <0 1 2 3>; + + status = "okay"; + + ports { + port@1 { + reg = <1>; + mdss1_dp0_phy_out: endpoint { + remote-endpoint = <&dp2_connector_in>; + }; + }; + }; +}; + +&mdss1_dp0_phy { + vdda-phy-supply = <&vreg_l11g>; + vdda-pll-supply = <&vreg_l3g>; + + status = "okay"; +}; + +&mdss1_dp1 { + data-lanes = <0 1 2 3>; + + status = "okay"; + + ports { + port@1 { + reg = <1>; + mdss1_dp1_phy_out: endpoint { + remote-endpoint = <&dp3_connector_in>; + }; + }; + }; +}; + +&mdss1_dp1_phy { + vdda-phy-supply = <&vreg_l11g>; + vdda-pll-supply = <&vreg_l3g>; + + status = "okay"; +}; + +&mdss1_dp2 { + data-lanes = <0 1 2 3>; + + status = "okay"; + + ports { + port@1 { + reg = <1>; + mdss1_dp2_phy_out: endpoint { + remote-endpoint = <&edp2_connector_in>; + }; + }; + }; +}; + +&mdss1_dp2_phy { + vdda-phy-supply = <&vreg_l11g>; + vdda-pll-supply = <&vreg_l3g>; + + status = "okay"; +}; + +&mdss1_dp3 { + data-lanes = <0 1 2 3>; + + status = "okay"; + + ports { + port@1 { + reg = <1>; + mdss1_dp3_phy_out: endpoint { + remote-endpoint = <&edp3_connector_in>; + }; + }; + }; +}; + +&mdss1_dp3_phy { + vdda-phy-supply = <&vreg_l11g>; + vdda-pll-supply = <&vreg_l3g>; + + status = "okay"; +}; + &pcie2a { perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; @@ -240,11 +480,6 @@ status = "okay"; }; -&qup2_uart17 { - compatible = "qcom,geni-debug-uart"; - status = "okay"; -}; - &remoteproc_adsp { firmware-name = "qcom/sa8540p/adsp.mbn"; status = "okay"; @@ -260,82 +495,9 @@ status = "okay"; }; -&spmi_bus { - pm8450a: pmic@0 { - compatible = "qcom,pm8150", "qcom,spmi-pmic"; - reg = <0x0 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - rtc@6000 { - compatible = "qcom,pm8941-rtc"; - reg = <0x6000>; - reg-names = "rtc", "alarm"; - interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; - wakeup-source; - }; - - pm8450a_gpios: gpio@c000 { - compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio"; - reg = <0xc000>; - gpio-controller; - gpio-ranges = <&pm8450a_gpios 0 0 10>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - pm8450c: pmic@4 { - compatible = "qcom,pm8150", "qcom,spmi-pmic"; - reg = <0x4 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pm8450c_gpios: gpio@c000 { - compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio"; - reg = <0xc000>; - gpio-controller; - gpio-ranges = <&pm8450c_gpios 0 0 10>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - pm8450e: pmic@8 { - compatible = "qcom,pm8150", "qcom,spmi-pmic"; - reg = <0x8 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pm8450e_gpios: gpio@c000 { - compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio"; - reg = <0xc000>; - gpio-controller; - gpio-ranges = <&pm8450e_gpios 0 0 10>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - pm8450g: pmic@c { - compatible = "qcom,pm8150", "qcom,spmi-pmic"; - reg = <0xc SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pm8450g_gpios: gpio@c000 { - compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio"; - reg = <0xc000>; - gpio-controller; - gpio-ranges = <&pm8450g_gpios 0 0 10>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; +&uart17 { + compatible = "qcom,geni-debug-uart"; + status = "okay"; }; &ufs_mem_hc { diff --git a/arch/arm64/boot/dts/qcom/pm8450a.dtsi b/arch/arm64/boot/dts/qcom/sa8540p-pmics.dtsi index 34fc72896761..1221be89b3de 100644 --- a/arch/arm64/boot/dts/qcom/pm8450a.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8540p-pmics.dtsi @@ -4,71 +4,80 @@ * Copyright (c) 2022, Linaro Limited */ +#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/spmi/spmi.h> &spmi_bus { - pm8450a: pmic@0 { + pmm8540a: pmic@0 { compatible = "qcom,pm8150", "qcom,spmi-pmic"; reg = <0x0 SPMI_USID>; #address-cells = <1>; #size-cells = <0>; - pm8450a_gpios: gpio@c000 { + rtc@6000 { + compatible = "qcom,pm8941-rtc"; + reg = <0x6000>, <0x6100>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; + wakeup-source; + }; + + pmm8540a_gpios: gpio@c000 { compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; - gpio-ranges = <&pm8450a_gpios 0 0 10>; + gpio-ranges = <&pmm8540a_gpios 0 0 10>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; }; - pm8450c: pmic@4 { + pmm8540c: pmic@4 { compatible = "qcom,pm8150", "qcom,spmi-pmic"; reg = <0x4 SPMI_USID>; #address-cells = <1>; #size-cells = <0>; - pm8450c_gpios: gpio@c000 { + pmm8540c_gpios: gpio@c000 { compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; - gpio-ranges = <&pm8450c_gpios 0 0 10>; + gpio-ranges = <&pmm8540c_gpios 0 0 10>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; }; - pm8450e: pmic@8 { + pmm8540e: pmic@8 { compatible = "qcom,pm8150", "qcom,spmi-pmic"; reg = <0x8 SPMI_USID>; #address-cells = <1>; #size-cells = <0>; - pm8450e_gpios: gpio@c000 { + pmm8540e_gpios: gpio@c000 { compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; - gpio-ranges = <&pm8450e_gpios 0 0 10>; + gpio-ranges = <&pmm8540e_gpios 0 0 10>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; }; - pm8450g: pmic@c { + pmm8540g: pmic@c { compatible = "qcom,pm8150", "qcom,spmi-pmic"; reg = <0xc SPMI_USID>; #address-cells = <1>; #size-cells = <0>; - pm8450g_gpios: gpio@c000 { + pmm8540g_gpios: gpio@c000 { compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; - gpio-ranges = <&pm8450g_gpios 0 0 10>; + gpio-ranges = <&pmm8540g_gpios 0 0 10>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts index 6c547f1b13dc..eacc1764255b 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts @@ -10,14 +10,19 @@ #include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include "sa8540p.dtsi" -#include "pm8450a.dtsi" +#include "sa8540p-pmics.dtsi" / { model = "Qualcomm SA8540P Ride"; compatible = "qcom,sa8540p-ride", "qcom,sa8540p"; aliases { - serial0 = &qup2_uart17; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c12 = &i2c12; + i2c15 = &i2c15; + i2c18 = &i2c18; + serial0 = &uart17; }; chosen { @@ -146,6 +151,62 @@ }; }; +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_default>; + + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_default>; + + status = "okay"; +}; + +&i2c12 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c12_default>; + + status = "okay"; +}; + +&i2c15 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c15_default>; + + status = "okay"; +}; + +&i2c18 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c18_default>; + + status = "okay"; +}; + +&pcie2a { + ranges = <0x01000000 0x0 0x3c200000 0x0 0x3c200000 0x0 0x100000>, + <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>, + <0x03000000 0x5 0x00000000 0x5 0x00000000 0x1 0x00000000>; + + perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie2a_default>; + + status = "okay"; +}; + +&pcie2a_phy { + vdda-phy-supply = <&vreg_l11a>; + vdda-pll-supply = <&vreg_l3a>; + + status = "okay"; +}; + &pcie3a { ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x20000000>, @@ -167,12 +228,15 @@ status = "okay"; }; -&qup2 { +&qup0 { status = "okay"; }; -&qup2_uart17 { - compatible = "qcom,geni-debug-uart"; +&qup1 { + status = "okay"; +}; + +&qup2 { status = "okay"; }; @@ -186,29 +250,9 @@ status = "okay"; }; -&tlmm { - pcie3a_default: pcie3a-default-state { - perst-pins { - pins = "gpio151"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - clkreq-pins { - pins = "gpio150"; - function = "pcie3a_clkreq"; - drive-strength = <2>; - bias-pull-up; - }; - - wake-pins { - pins = "gpio56"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; +&uart17 { + compatible = "qcom,geni-debug-uart"; + status = "okay"; }; &ufs_mem_hc { @@ -268,3 +312,88 @@ &xo_board_clk { clock-frequency = <38400000>; }; + +/* PINCTRL */ + +&tlmm { + i2c0_default: i2c0-default-state { + pins = "gpio135", "gpio136"; + function = "qup15"; + drive-strength = <2>; + bias-pull-up; + }; + + i2c1_default: i2c1-default-state { + pins = "gpio158", "gpio159"; + function = "qup15"; + drive-strength = <2>; + bias-pull-up; + }; + + i2c12_default: i2c12-default-state { + pins = "gpio0", "gpio1"; + function = "qup15"; + drive-strength = <2>; + bias-pull-up; + }; + + i2c15_default: i2c15-default-state { + pins = "gpio36", "gpio37"; + function = "qup15"; + drive-strength = <2>; + bias-pull-up; + }; + + i2c18_default: i2c18-default-state { + pins = "gpio66", "gpio67"; + function = "qup18"; + drive-strength = <2>; + bias-pull-up; + }; + + pcie2a_default: pcie2a-default-state { + perst-pins { + pins = "gpio143"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq-pins { + pins = "gpio142"; + function = "pcie2a_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + wake-pins { + pins = "gpio145"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie3a_default: pcie3a-default-state { + perst-pins { + pins = "gpio151"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq-pins { + pins = "gpio150"; + function = "pcie3a_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + wake-pins { + pins = "gpio56"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sa8540p.dtsi b/arch/arm64/boot/dts/qcom/sa8540p.dtsi index a88452c20d05..4a990fda8fc3 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8540p.dtsi @@ -10,7 +10,7 @@ /delete-node/ &cpu4_opp_table; / { - cpu0_opp_table: cpu0-opp-table { + cpu0_opp_table: opp-table-cpu0 { compatible = "operating-points-v2"; opp-shared; @@ -92,7 +92,7 @@ }; }; - cpu4_opp_table: cpu4-opp-table { + cpu4_opp_table: opp-table-cpu4 { compatible = "operating-points-v2"; opp-shared; diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts index 70fd9ff8dfa2..774f9d45f051 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts @@ -80,6 +80,12 @@ reg = <0x0 0x94400000 0x0 0x200000>; no-map; }; + + mdata_mem: mpss-metadata { + alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>; + size = <0x0 0x4000>; + no-map; + }; }; }; @@ -304,7 +310,7 @@ pinctrl-names = "default"; pinctrl-0 = <&disp_pins>; - reset-gpios = <&pm6150l_gpio 3 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pm6150l_gpios 3 GPIO_ACTIVE_HIGH>; ports { #address-cells = <1>; @@ -370,8 +376,26 @@ &remoteproc_mpss { status = "okay"; compatible = "qcom,sc7180-mss-pil"; + reg = <0 0x04080000 0 0x4040>, <0 0x04180000 0 0x48>; + reg-names = "qdsp6", "rmb"; + + clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, + <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, + <&gcc GCC_MSS_NAV_AXI_CLK>, + <&gcc GCC_MSS_SNOC_AXI_CLK>, + <&gcc GCC_MSS_MFAB_AXIS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "bus", "nav", "snoc_axi", "mnoc_axi", "xo"; + iommus = <&apps_smmu 0x461 0x0>, <&apps_smmu 0x444 0x3>; - memory-region = <&mba_mem &mpss_mem>; + memory-region = <&mba_mem>, <&mpss_mem>, <&mdata_mem>; + + resets = <&aoss_reset AOSS_CC_MSS_RESTART>, + <&pdc_reset PDC_MODEM_SYNC_RESET>; + reset-names = "mss_restart", "pdc_reset"; + + qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>; + qcom,spare-regs = <&tcsr_regs_2 0xb3e4>; }; &sdhc_1 { @@ -467,7 +491,7 @@ /* PINCTRL - additions to nodes defined in sc7180.dtsi */ -&pm6150l_gpio { +&pm6150l_gpios { disp_pins: disp-state { pinconf { pins = "gpio3"; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi index d3cf64c16dcd..b3ba23a88a0b 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi @@ -85,6 +85,24 @@ }; }; +/* + * ADDITIONS TO FIXED REGULATORS DEFINED IN PARENT DEVICE TREE FILES + * + * Sort order matches the order in the parent files (parents before children). + */ + +&pp3300_dx_edp { + /* + * The atna33xc20 really likes to be power cycled to keep it from + * getting in a bad state. This is the reason that the touchscreen + * rail and eDP rails are separate from each other on homestar (but + * not other trogdor devices) Make sure it starts "off" at bootup. + */ + /delete-property/ regulator-boot-on; +}; + +/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */ + ap_ts_pen_1v8: &i2c4 { status = "okay"; clock-frequency = <400000>; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi index fd4b71203754..bffcbd141bd7 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi @@ -19,12 +19,11 @@ }; &ipa { - status = "okay"; - /* * Trogdor doesn't have QHEE (Qualcomm's EL2 blob), so the * modem needs to cover certain init steps (GSI init), and * the AP needs to wait for it. */ - modem-init; + qcom,gsi-loader = "modem"; + status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-parade-ps8640.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-parade-ps8640.dtsi index ebd6765e2afa..5aa7949b5328 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-parade-ps8640.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-parade-ps8640.dtsi @@ -26,6 +26,26 @@ }; }; +/* + * ADDITIONS TO FIXED REGULATORS DEFINED IN PARENT DEVICE TREE FILES + * + * Sort order matches the order in the parent files (parents before children). + */ + +&pp3300_dx_edp { + off-on-delay-us = <500000>; + + /* + * It's nicer to start with this regulator enabled. The + * bootloader may have left it on and it's nice not to cause an + * extra power cycle of the touchscreen and eDP panel at bootup. + * This should help speed bootup because we have off-on-delay-us. + */ + regulator-boot-on; +}; + +/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */ + &dsi0_out { remote-endpoint = <&ps8640_in>; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel360.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel360.dtsi index 5702325d0c7b..bc4f3b6c6634 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel360.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel360.dtsi @@ -14,6 +14,25 @@ realtek,dmic-clk-rate-hz = <2048000>; }; +ap_ts_pen_1v8: &i2c4 { + clock-frequency = <400000>; + status = "okay"; + + ap_ts: touchscreen@10 { + compatible = "elan,ekth3915", "elan,ekth3500"; + reg = <0x10>; + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_l>, <&ts_reset_l>; + + interrupt-parent = <&tlmm>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + + vcc33-supply = <&pp3300_ts>; + vccio-supply = <&pp1800_l10a>; + reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>; + }; +}; + &keyboard_controller { function-row-physmap = < MATRIX_KEY(0x00, 0x02, 0) /* T1 */ @@ -48,3 +67,7 @@ compatible = "google,sc7180-trogdor"; model = "sc7180-rt5682s-max98357a-1mic"; }; + +&wifi { + qcom,ath10k-calibration-variant = "GO_PAZQUEL360"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi index 65333709e529..e52b8776755d 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi @@ -7,6 +7,26 @@ #include <dt-bindings/gpio/gpio.h> +/* + * ADDITIONS TO FIXED REGULATORS DEFINED IN PARENT DEVICE TREE FILES + * + * Sort order matches the order in the parent files (parents before children). + */ + +&pp3300_dx_edp { + off-on-delay-us = <500000>; + + /* + * It's nicer to start with this regulator enabled. The + * bootloader may have left it on and it's nice not to cause an + * extra power cycle of the touchscreen and eDP panel at bootup. + * This should help speed bootup because we have off-on-delay-us. + */ + regulator-boot-on; +}; + +/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */ + &dsi0_out { remote-endpoint = <&sn65dsi86_in>; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index f1defb94d670..dcb179b2a3fb 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -81,6 +81,12 @@ reg = <0x0 0x94400000 0x0 0x200000>; no-map; }; + + mdata_mem: mpss-metadata { + alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>; + size = <0x0 0x4000>; + no-map; + }; }; aliases { @@ -788,18 +794,18 @@ hp_i2c: &i2c9 { #address-cells = <1>; #size-cells = <0>; - mi2s@0 { + dai-link@0 { reg = <MI2S_PRIMARY>; qcom,playback-sd-lines = <1>; qcom,capture-sd-lines = <0>; }; - secondary_mi2s: mi2s@1 { + secondary_mi2s: dai-link@1 { reg = <MI2S_SECONDARY>; qcom,playback-sd-lines = <0>; }; - hdmi@5 { + dai-link@5 { reg = <LPASS_DP_RX>; }; }; @@ -816,7 +822,11 @@ hp_i2c: &i2c9 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&dp_hot_plug_det>; +}; + +&mdss_dp_out { data-lanes = <0 1>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000>; }; &pm6150_adc { @@ -853,12 +863,30 @@ hp_i2c: &i2c9 { &remoteproc_mpss { status = "okay"; compatible = "qcom,sc7180-mss-pil"; + reg = <0 0x04080000 0 0x4040>, <0 0x04180000 0 0x48>; + reg-names = "qdsp6", "rmb"; + + clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, + <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, + <&gcc GCC_MSS_NAV_AXI_CLK>, + <&gcc GCC_MSS_SNOC_AXI_CLK>, + <&gcc GCC_MSS_MFAB_AXIS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "bus", "nav", "snoc_axi", "mnoc_axi", "xo"; + iommus = <&apps_smmu 0x461 0x0>, <&apps_smmu 0x444 0x3>; - memory-region = <&mba_mem &mpss_mem>; + memory-region = <&mba_mem>, <&mpss_mem>, <&mdata_mem>; /* This gets overridden for SKUs with LTE support. */ firmware-name = "qcom/sc7180-trogdor/modem-nolte/mba.mbn", "qcom/sc7180-trogdor/modem-nolte/qdsp6sw.mbn"; + + resets = <&aoss_reset AOSS_CC_MSS_RESTART>, + <&pdc_reset PDC_MODEM_SYNC_RESET>; + reset-names = "mss_restart", "pdc_reset"; + + qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>; + qcom,spare-regs = <&tcsr_regs_2 0xb3e4>; }; &sdhc_1 { @@ -1141,11 +1169,11 @@ ap_spi_fp: &spi10 { /* PINCTRL - board-specific pinctrl */ -&pm6150_gpio { +&pm6150_gpios { status = "disabled"; /* No GPIOs are connected */ }; -&pm6150l_gpio { +&pm6150l_gpios { gpio-line-names = "AP_SUSPEND", "", "", @@ -1376,7 +1404,15 @@ ap_spi_fp: &spi10 { pins = "gpio8"; function = "gpio"; bias-disable; - drive-strength = <2>; + + /* + * The reset GPIO to the touchscreen takes almost 2ms to drop + * at the default drive strength. When we bump it up to 8mA it + * falls in under 500us. We want this to be fast since the Elan + * datasheet (and any drivers written based on it) talk about using + * a 500 us reset pulse. + */ + drive-strength = <8>; }; sdc1_on: sdc1-on-state { diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index f71cf21a8dd8..ebfa21e9ed8a 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -27,8 +27,6 @@ #address-cells = <2>; #size-cells = <2>; - chosen { }; - aliases { mmc1 = &sdhc_1; mmc2 = &sdhc_2; @@ -54,6 +52,8 @@ spi11 = &spi11; }; + chosen { }; + clocks { xo_board: xo-board { compatible = "fixed-clock"; @@ -68,62 +68,6 @@ }; }; - reserved_memory: reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - hyp_mem: memory@80000000 { - reg = <0x0 0x80000000 0x0 0x600000>; - no-map; - }; - - xbl_mem: memory@80600000 { - reg = <0x0 0x80600000 0x0 0x200000>; - no-map; - }; - - aop_mem: memory@80800000 { - reg = <0x0 0x80800000 0x0 0x20000>; - no-map; - }; - - aop_cmd_db_mem: memory@80820000 { - reg = <0x0 0x80820000 0x0 0x20000>; - compatible = "qcom,cmd-db"; - no-map; - }; - - sec_apps_mem: memory@808ff000 { - reg = <0x0 0x808ff000 0x0 0x1000>; - no-map; - }; - - smem_mem: memory@80900000 { - reg = <0x0 0x80900000 0x0 0x200000>; - no-map; - }; - - tz_mem: memory@80b00000 { - reg = <0x0 0x80b00000 0x0 0x3900000>; - no-map; - }; - - ipa_fw_mem: memory@8b700000 { - reg = <0 0x8b700000 0 0x10000>; - no-map; - }; - - rmtfs_mem: memory@94600000 { - compatible = "qcom,rmtfs-mem"; - reg = <0x0 0x94600000 0x0 0x200000>; - no-map; - - qcom,client-id = <1>; - qcom,vmid = <15>; - }; - }; - cpus { #address-cells = <2>; #size-cells = <0>; @@ -146,9 +90,11 @@ qcom,freq-domain = <&cpufreq_hw 0>; L2_0: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; L3_0: l3-cache { compatible = "cache"; + cache-level = <3>; }; }; }; @@ -171,6 +117,7 @@ qcom,freq-domain = <&cpufreq_hw 0>; L2_100: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -193,6 +140,7 @@ qcom,freq-domain = <&cpufreq_hw 0>; L2_200: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -215,6 +163,7 @@ qcom,freq-domain = <&cpufreq_hw 0>; L2_300: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -237,6 +186,7 @@ qcom,freq-domain = <&cpufreq_hw 0>; L2_400: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -259,6 +209,7 @@ qcom,freq-domain = <&cpufreq_hw 0>; L2_500: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -281,6 +232,7 @@ qcom,freq-domain = <&cpufreq_hw 1>; L2_600: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -303,6 +255,7 @@ qcom,freq-domain = <&cpufreq_hw 1>; L2_700: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -398,6 +351,18 @@ }; }; + firmware { + scm { + compatible = "qcom,scm-sc7180", "qcom,scm"; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0 0x80000000 0 0>; + }; + cpu0_opp_table: opp-table-cpu0 { compatible = "operating-points-v2"; opp-shared; @@ -538,10 +503,42 @@ }; }; - memory@80000000 { - device_type = "memory"; - /* We expect the bootloader to fill in the size */ - reg = <0 0x80000000 0 0>; + qspi_opp_table: opp-table-qspi { + compatible = "operating-points-v2"; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-150000000 { + opp-hz = /bits/ 64 <150000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + + qup_opp_table: opp-table-qup { + compatible = "operating-points-v2"; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-128000000 { + opp-hz = /bits/ 64 <128000000>; + required-opps = <&rpmhpd_opp_nom>; + }; }; pmu { @@ -549,9 +546,64 @@ interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; }; - firmware { - scm { - compatible = "qcom,scm-sc7180", "qcom,scm"; + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: memory@80000000 { + reg = <0x0 0x80000000 0x0 0x600000>; + no-map; + }; + + xbl_mem: memory@80600000 { + reg = <0x0 0x80600000 0x0 0x200000>; + no-map; + }; + + aop_mem: memory@80800000 { + reg = <0x0 0x80800000 0x0 0x20000>; + no-map; + }; + + aop_cmd_db_mem: memory@80820000 { + reg = <0x0 0x80820000 0x0 0x20000>; + compatible = "qcom,cmd-db"; + no-map; + }; + + sec_apps_mem: memory@808ff000 { + reg = <0x0 0x808ff000 0x0 0x1000>; + no-map; + }; + + smem_mem: memory@80900000 { + reg = <0x0 0x80900000 0x0 0x200000>; + no-map; + }; + + tz_mem: memory@80b00000 { + reg = <0x0 0x80b00000 0x0 0x3900000>; + no-map; + }; + + ipa_fw_mem: memory@8b700000 { + reg = <0 0x8b700000 0 0x10000>; + no-map; + }; + + rmtfs_mem: memory@94600000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0 0x94600000 0x0 0x200000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = <15>; }; }; @@ -640,11 +692,6 @@ }; }; - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - soc: soc@0 { #address-cells = <2>; #size-cells = <2>; @@ -690,8 +737,8 @@ sdhc_1: mmc@7c4000 { compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; - reg = <0 0x7c4000 0 0x1000>, - <0 0x07c5000 0 0x1000>; + reg = <0 0x007c4000 0 0x1000>, + <0 0x007c5000 0 0x1000>; reg-names = "hc", "cqhci"; iommus = <&apps_smmu 0x60 0x0>; @@ -739,25 +786,6 @@ }; }; - qup_opp_table: opp-table-qup { - compatible = "operating-points-v2"; - - opp-75000000 { - opp-hz = /bits/ 64 <75000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-128000000 { - opp-hz = /bits/ 64 <128000000>; - required-opps = <&rpmhpd_opp_nom>; - }; - }; - qupv3_id_0: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; reg = <0 0x008c0000 0 0x6000>; @@ -1421,9 +1449,9 @@ iommus = <&apps_smmu 0x440 0x0>, <&apps_smmu 0x442 0x0>; - reg = <0 0x1e40000 0 0x7000>, - <0 0x1e47000 0 0x2000>, - <0 0x1e04000 0 0x2c000>; + reg = <0 0x01e40000 0 0x7000>, + <0 0x01e47000 0 0x2000>, + <0 0x01e04000 0 0x2c000>; reg-names = "ipa-reg", "ipa-shared", "gsi"; @@ -1929,8 +1957,7 @@ remoteproc_mpss: remoteproc@4080000 { compatible = "qcom,sc7180-mpss-pas"; - reg = <0 0x04080000 0 0x4040>, <0 0x04180000 0 0x48>; - reg-names = "qdsp6", "rmb"; + reg = <0 0x04080000 0 0x4040>; interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, @@ -1941,14 +1968,8 @@ interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack", "shutdown-ack"; - clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, - <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, - <&gcc GCC_MSS_NAV_AXI_CLK>, - <&gcc GCC_MSS_SNOC_AXI_CLK>, - <&gcc GCC_MSS_MFAB_AXIS_CLK>, - <&rpmhcc RPMH_CXO_CLK>; - clock-names = "iface", "bus", "nav", "snoc_axi", - "mnoc_axi", "xo"; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; power-domains = <&rpmhpd SC7180_CX>, <&rpmhpd SC7180_MX>, @@ -1962,13 +1983,6 @@ qcom,smem-states = <&modem_smp2p_out 0>; qcom,smem-state-names = "stop"; - resets = <&aoss_reset AOSS_CC_MSS_RESTART>, - <&pdc_reset PDC_MODEM_SYNC_RESET>; - reset-names = "mss_restart", "pdc_reset"; - - qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>; - qcom,spare-regs = <&tcsr_regs_2 0xb3e4>; - status = "disabled"; glink-edge { @@ -2123,6 +2137,12 @@ #power-domain-cells = <1>; }; + dma@10a2000 { + compatible = "qcom,sc7180-dcc", "qcom,dcc"; + reg = <0x0 0x010a2000 0x0 0x1000>, + <0x0 0x010ae000 0x0 0x2000>; + }; + stm@6002000 { compatible = "arm,coresight-stm", "arm,primecell"; reg = <0 0x06002000 0 0x1000>, @@ -2655,25 +2675,6 @@ }; }; - qspi_opp_table: opp-table-qspi { - compatible = "operating-points-v2"; - - opp-75000000 { - opp-hz = /bits/ 64 <75000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-150000000 { - opp-hz = /bits/ 64 <150000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - required-opps = <&rpmhpd_opp_nom>; - }; - }; - qspi: spi@88dc000 { compatible = "qcom,sc7180-qspi", "qcom,qspi-v1"; reg = <0 0x088dc000 0 0x600>; @@ -2921,7 +2922,7 @@ #power-domain-cells = <1>; }; - mdss: mdss@ae00000 { + mdss: display-subsystem@ae00000 { compatible = "qcom,sc7180-mdss"; reg = <0 0x0ae00000 0 0x1000>; reg-names = "mdss"; @@ -3022,7 +3023,8 @@ }; dsi0: dsi@ae94000 { - compatible = "qcom,mdss-dsi-ctrl"; + compatible = "qcom,sc7180-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; reg = <0 0x0ae94000 0 0x400>; reg-names = "dsi_ctrl"; @@ -3116,11 +3118,11 @@ compatible = "qcom,sc7180-dp"; status = "disabled"; - reg = <0 0xae90000 0 0x200>, - <0 0xae90200 0 0x200>, - <0 0xae90400 0 0xc00>, - <0 0xae91000 0 0x400>, - <0 0xae91400 0 0x400>; + reg = <0 0x0ae90000 0 0x200>, + <0 0x0ae90200 0 0x200>, + <0 0x0ae90400 0 0xc00>, + <0 0x0ae91000 0 0x400>, + <0 0x0ae91400 0 0x400>; interrupt-parent = <&mdss>; interrupts = <12>; @@ -3155,7 +3157,7 @@ port@1 { reg = <1>; - dp_out: endpoint { }; + mdss_dp_out: endpoint { }; }; }; @@ -3248,7 +3250,7 @@ #reset-cells = <1>; }; - aoss_qmp: power-controller@c300000 { + aoss_qmp: power-management@c300000 { compatible = "qcom,sc7180-aoss-qmp", "qcom,aoss-qmp"; reg = <0 0x0c300000 0 0x400>; interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; @@ -3274,8 +3276,8 @@ interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; qcom,ee = <0>; qcom,channel = <0>; - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <0>; interrupt-controller; #interrupt-cells = <4>; cell-index = <0>; @@ -3417,7 +3419,7 @@ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; }; - timer@17c20000{ + timer@17c20000 { #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0 0x20000000>; @@ -3625,6 +3627,7 @@ <&apps_smmu 0x1032 0>; power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; + required-opps = <&rpmhpd_opp_nom>; status = "disabled"; @@ -3655,6 +3658,8 @@ clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "iface", "bi_tcxo"; + power-domains = <&rpmhpd SC7180_CX>; + #clock-cells = <1>; #power-domain-cells = <1>; }; @@ -3681,7 +3686,7 @@ type = "passive"; }; - cpu0_crit: cpu_crit { + cpu0_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -3730,7 +3735,7 @@ type = "passive"; }; - cpu1_crit: cpu_crit { + cpu1_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -3779,7 +3784,7 @@ type = "passive"; }; - cpu2_crit: cpu_crit { + cpu2_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -3828,7 +3833,7 @@ type = "passive"; }; - cpu3_crit: cpu_crit { + cpu3_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -3877,7 +3882,7 @@ type = "passive"; }; - cpu4_crit: cpu_crit { + cpu4_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -3926,7 +3931,7 @@ type = "passive"; }; - cpu5_crit: cpu_crit { + cpu5_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -3975,7 +3980,7 @@ type = "passive"; }; - cpu6_crit: cpu_crit { + cpu6_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -4016,7 +4021,7 @@ type = "passive"; }; - cpu7_crit: cpu_crit { + cpu7_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -4057,7 +4062,7 @@ type = "passive"; }; - cpu8_crit: cpu_crit { + cpu8_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -4098,7 +4103,7 @@ type = "passive"; }; - cpu9_crit: cpu_crit { + cpu9_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -4132,7 +4137,7 @@ type = "hot"; }; - aoss0_crit: aoss0_crit { + aoss0_crit: aoss0-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -4152,7 +4157,7 @@ hysteresis = <2000>; type = "hot"; }; - cpuss0_crit: cluster0_crit { + cpuss0_crit: cluster0-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -4172,7 +4177,7 @@ hysteresis = <2000>; type = "hot"; }; - cpuss1_crit: cluster0_crit { + cpuss1_crit: cluster0-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -4193,7 +4198,7 @@ type = "passive"; }; - gpuss0_crit: gpuss0_crit { + gpuss0_crit: gpuss0-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -4221,7 +4226,7 @@ type = "passive"; }; - gpuss1_crit: gpuss1_crit { + gpuss1_crit: gpuss1-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -4249,7 +4254,7 @@ type = "hot"; }; - aoss1_crit: aoss1_crit { + aoss1_crit: aoss1-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -4270,7 +4275,7 @@ type = "hot"; }; - cwlan_crit: cwlan_crit { + cwlan_crit: cwlan-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -4291,7 +4296,7 @@ type = "hot"; }; - audio_crit: audio_crit { + audio_crit: audio-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -4312,7 +4317,7 @@ type = "hot"; }; - ddr_crit: ddr_crit { + ddr_crit: ddr-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -4333,7 +4338,7 @@ type = "hot"; }; - q6_hvx_crit: q6_hvx_crit { + q6_hvx_crit: q6-hvx-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -4354,7 +4359,7 @@ type = "hot"; }; - camera_crit: camera_crit { + camera_crit: camera-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -4375,7 +4380,7 @@ type = "hot"; }; - mdm_crit: mdm_crit { + mdm_crit: mdm-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -4396,7 +4401,7 @@ type = "hot"; }; - mdm_dsp_crit: mdm_dsp_crit { + mdm_dsp_crit: mdm-dsp-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -4417,7 +4422,7 @@ type = "hot"; }; - npu_crit: npu_crit { + npu_crit: npu-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -4438,7 +4443,7 @@ type = "hot"; }; - video_crit: video_crit { + video_crit: video-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682.dtsi index af685bc35e10..69e7aa7b2f6c 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682.dtsi @@ -33,10 +33,23 @@ }; dai-link@1 { - link-name = "ALC5682"; + link-name = "DisplayPort"; reg = <1>; cpu { + sound-dai = <&lpass_cpu LPASS_DP_RX>; + }; + + codec { + sound-dai = <&mdss_dp>; + }; + }; + + dai-link@2 { + link-name = "ALC5682"; + reg = <2>; + + cpu { sound-dai = <&lpass_cpu MI2S_PRIMARY>; }; @@ -92,6 +105,10 @@ hp_i2c: &i2c2 { reg = <MI2S_SECONDARY>; qcom,playback-sd-lines = <0>; }; + + dai-link@5 { + reg = <LPASS_DP_RX>; + }; }; /* PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES */ diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-lte-sku.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-lte-sku.dtsi index ad66e5e9db4e..95505549adcc 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-lte-sku.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-lte-sku.dtsi @@ -17,16 +17,44 @@ reg = <0x0 0x9c700000 0x0 0x200000>; no-map; }; + + mdata_mem: mpss-metadata { + alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>; + size = <0x0 0x4000>; + no-map; + }; }; }; +&ipa { + qcom,gsi-loader = "modem"; + status = "okay"; +}; + &remoteproc_mpss { compatible = "qcom,sc7280-mss-pil"; + + clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, + <&gcc GCC_MSS_OFFLINE_AXI_CLK>, + <&gcc GCC_MSS_SNOC_AXI_CLK>, + <&rpmhcc RPMH_PKA_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "offline", "snoc_axi", "pka", "xo"; + iommus = <&apps_smmu 0x124 0x0>, <&apps_smmu 0x488 0x7>; interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; - memory-region = <&mba_mem>, <&mpss_mem>; + memory-region = <&mba_mem>, <&mpss_mem>, <&mdata_mem>; firmware-name = "qcom/sc7280-herobrine/modem/mba.mbn", "qcom/sc7280-herobrine/modem/qdsp6sw.mbn"; + + resets = <&aoss_reset AOSS_CC_MSS_RESTART>, + <&pdc_reset PDC_MODEM_SYNC_RESET>; + reset-names = "mss_restart", "pdc_reset"; + + qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x8000 0x13000>; + qcom,ext-regs = <&tcsr_2 0x10000 0x10004 &tcsr_1 0x6004 0x6008>; + qcom,qaccept-regs = <&tcsr_1 0x3030 0x3040 0x3020>; + status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-nvme-sku.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-nvme-sku.dtsi new file mode 100644 index 000000000000..1aed02297f44 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-nvme-sku.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Herobrine dts fragment for NVMe SKUs + * + * Copyright 2022 Google LLC. + */ + +&pcie1 { + status = "okay"; +}; + +&pcie1_phy { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-zombie-nvme-lte.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-zombie-nvme-lte.dts new file mode 100644 index 000000000000..e1fcacdccd51 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-zombie-nvme-lte.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Zombie board device tree source + * + * Copyright 2022 Google LLC. + */ + +/dts-v1/; + +#include "sc7280-herobrine-zombie.dtsi" +#include "sc7280-herobrine-lte-sku.dtsi" +#include "sc7280-herobrine-nvme-sku.dtsi" + +/ { + model = "Google Zombie with LTE and NVMe"; + compatible = "google,zombie-sku514", "qcom,sc7280"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-zombie-nvme.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-zombie-nvme.dts new file mode 100644 index 000000000000..e3d52c560363 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-zombie-nvme.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Zombie board device tree source + * + * Copyright 2022 Google LLC. + */ + +/dts-v1/; + +#include "sc7280-herobrine-zombie.dtsi" +#include "sc7280-herobrine-wifi-sku.dtsi" +#include "sc7280-herobrine-nvme-sku.dtsi" + +/ { + model = "Google Zombie with NVMe"; + compatible = "google,zombie-sku2","google,zombie-sku3","google,zombie-sku515", "qcom,sc7280"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-zombie.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-zombie.dtsi index 7fc0b6bfc0d6..64deaaabac0f 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-zombie.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-zombie.dtsi @@ -60,17 +60,7 @@ ap_tp_i2c: &i2c0 { status = "okay"; }; -/* For nvme */ -&pcie1 { - status = "okay"; -}; - -/* For nvme */ -&pcie1_phy { - status = "okay"; -}; - -&pm8350c_pwm_backlight{ +&pm8350c_pwm_backlight { /* Set the PWM period to 200 microseconds (5kHz duty cycle) */ pwms = <&pm8350c_pwm 3 200000>; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi index 27f479ff9d80..d21f73bf0873 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -442,7 +442,11 @@ ap_i2c_tpm: &i2c14 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&dp_hot_plug_det>; +}; + +&mdss_dp_out { data-lanes = <0 1>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; &mdss_mdp { diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index f7efb9966afd..43e61a1aa779 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -19,6 +19,7 @@ aliases { bluetooth0 = &bluetooth; serial1 = &uart7; + wifi0 = &wifi; }; max98360a: audio-codec-0 { @@ -376,11 +377,6 @@ status = "okay"; }; -&ipa { - status = "okay"; - modem-init; -}; - &lpass_cpu { status = "okay"; @@ -736,6 +732,7 @@ &tlmm { amp_en: amp-en-state { pins = "gpio63"; + function = "gpio"; bias-pull-down; drive-strength = <2>; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi index df49564ae6dc..cd6ee84b36fd 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi @@ -336,11 +336,6 @@ /* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */ -&ipa { - status = "okay"; - modem-init; -}; - &lpass_va_macro { vdd-micb-supply = <&vreg_bob>; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 0adf13399e64..bdcb74925313 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -166,7 +166,7 @@ CPU0: cpu@0 { device_type = "cpu"; - compatible = "arm,kryo"; + compatible = "qcom,kryo"; reg = <0x0 0x0>; enable-method = "psci"; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 @@ -180,16 +180,18 @@ #cooling-cells = <2>; L2_0: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; L3_0: l3-cache { compatible = "cache"; + cache-level = <3>; }; }; }; CPU1: cpu@100 { device_type = "cpu"; - compatible = "arm,kryo"; + compatible = "qcom,kryo"; reg = <0x0 0x100>; enable-method = "psci"; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 @@ -203,13 +205,14 @@ #cooling-cells = <2>; L2_100: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; CPU2: cpu@200 { device_type = "cpu"; - compatible = "arm,kryo"; + compatible = "qcom,kryo"; reg = <0x0 0x200>; enable-method = "psci"; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 @@ -223,13 +226,14 @@ #cooling-cells = <2>; L2_200: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; CPU3: cpu@300 { device_type = "cpu"; - compatible = "arm,kryo"; + compatible = "qcom,kryo"; reg = <0x0 0x300>; enable-method = "psci"; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 @@ -243,13 +247,14 @@ #cooling-cells = <2>; L2_300: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; CPU4: cpu@400 { device_type = "cpu"; - compatible = "arm,kryo"; + compatible = "qcom,kryo"; reg = <0x0 0x400>; enable-method = "psci"; cpu-idle-states = <&BIG_CPU_SLEEP_0 @@ -263,13 +268,14 @@ #cooling-cells = <2>; L2_400: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; CPU5: cpu@500 { device_type = "cpu"; - compatible = "arm,kryo"; + compatible = "qcom,kryo"; reg = <0x0 0x500>; enable-method = "psci"; cpu-idle-states = <&BIG_CPU_SLEEP_0 @@ -283,13 +289,14 @@ #cooling-cells = <2>; L2_500: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; CPU6: cpu@600 { device_type = "cpu"; - compatible = "arm,kryo"; + compatible = "qcom,kryo"; reg = <0x0 0x600>; enable-method = "psci"; cpu-idle-states = <&BIG_CPU_SLEEP_0 @@ -303,13 +310,14 @@ #cooling-cells = <2>; L2_600: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; CPU7: cpu@700 { device_type = "cpu"; - compatible = "arm,kryo"; + compatible = "qcom,kryo"; reg = <0x0 0x700>; enable-method = "psci"; cpu-idle-states = <&BIG_CPU_SLEEP_0 @@ -323,6 +331,7 @@ #cooling-cells = <2>; L2_700: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -2171,9 +2180,9 @@ iommus = <&apps_smmu 0x480 0x0>, <&apps_smmu 0x482 0x0>; - reg = <0 0x1e40000 0 0x8000>, - <0 0x1e50000 0 0x4ad0>, - <0 0x1e04000 0 0x23000>; + reg = <0 0x01e40000 0 0x8000>, + <0 0x01e50000 0 0x4ad0>, + <0 0x01e04000 0 0x23000>; reg-names = "ipa-reg", "ipa-shared", "gsi"; @@ -2455,7 +2464,7 @@ lpass_hm: clock-controller@3c00000 { compatible = "qcom,sc7280-lpasshm"; - reg = <0 0x3c00000 0 0x28>; + reg = <0 0x03c00000 0 0x28>; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "bi_tcxo"; #clock-cells = <1>; @@ -2661,6 +2670,12 @@ #power-domain-cells = <1>; }; + dma@117f000 { + compatible = "qcom,sc7280-dcc", "qcom,dcc"; + reg = <0x0 0x0117f000 0x0 0x1000>, + <0x0 0x01112000 0x0 0x6000>; + }; + adreno_smmu: iommu@3da0000 { compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; reg = <0 0x03da0000 0 0x20000>; @@ -2711,12 +2726,8 @@ interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack", "shutdown-ack"; - clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, - <&gcc GCC_MSS_OFFLINE_AXI_CLK>, - <&gcc GCC_MSS_SNOC_AXI_CLK>, - <&rpmhcc RPMH_PKA_CLK>, - <&rpmhcc RPMH_CXO_CLK>; - clock-names = "iface", "offline", "snoc_axi", "pka", "xo"; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; power-domains = <&rpmhpd SC7280_CX>, <&rpmhpd SC7280_MSS>; @@ -2729,14 +2740,6 @@ qcom,smem-states = <&modem_smp2p_out 0>; qcom,smem-state-names = "stop"; - resets = <&aoss_reset AOSS_CC_MSS_RESTART>, - <&pdc_reset PDC_MODEM_SYNC_RESET>; - reset-names = "mss_restart", "pdc_reset"; - - qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x8000 0x13000>; - qcom,ext-regs = <&tcsr_2 0x10000 0x10004 &tcsr_1 0x6004 0x6008>; - qcom,qaccept-regs = <&tcsr_1 0x3030 0x3040 0x3020>; - status = "disabled"; glink-edge { @@ -3489,7 +3492,7 @@ pmu@9091000 { compatible = "qcom,sc7280-llcc-bwmon"; - reg = <0 0x9091000 0 0x1000>; + reg = <0 0x09091000 0 0x1000>; interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; @@ -3571,7 +3574,7 @@ }; gem_noc: interconnect@9100000 { - reg = <0 0x9100000 0 0xe2200>; + reg = <0 0x09100000 0 0xe2200>; compatible = "qcom,sc7280-gem-noc"; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; @@ -3586,8 +3589,8 @@ eud: eud@88e0000 { compatible = "qcom,sc7280-eud","qcom,eud"; - reg = <0 0x88e0000 0 0x2000>, - <0 0x88e2000 0 0x1000>; + reg = <0 0x088e0000 0 0x2000>, + <0 0x088e2000 0 0x1000>; interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>; ports { port@0 { @@ -3750,7 +3753,7 @@ videocc: clock-controller@aaf0000 { compatible = "qcom,sc7280-videocc"; - reg = <0 0xaaf0000 0 0x10000>; + reg = <0 0x0aaf0000 0 0x10000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>; clock-names = "bi_tcxo", "bi_tcxo_ao"; @@ -3773,7 +3776,7 @@ dispcc: clock-controller@af00000 { compatible = "qcom,sc7280-dispcc"; - reg = <0 0xaf00000 0 0x20000>; + reg = <0 0x0af00000 0 0x20000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_DISP_GPLL0_CLK_SRC>, <&mdss_dsi_phy 0>, @@ -3906,7 +3909,8 @@ }; mdss_dsi: dsi@ae94000 { - compatible = "qcom,mdss-dsi-ctrl"; + compatible = "qcom,sc7280-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; reg = <0 0x0ae94000 0 0x400>; reg-names = "dsi_ctrl"; @@ -4001,10 +4005,10 @@ pinctrl-names = "default"; pinctrl-0 = <&edp_hot_plug_det>; - reg = <0 0xaea0000 0 0x200>, - <0 0xaea0200 0 0x200>, - <0 0xaea0400 0 0xc00>, - <0 0xaea1000 0 0x400>; + reg = <0 0x0aea0000 0 0x200>, + <0 0x0aea0200 0 0x200>, + <0 0x0aea0400 0 0xc00>, + <0 0x0aea1000 0 0x400>; interrupt-parent = <&mdss>; interrupts = <14>; @@ -4076,10 +4080,10 @@ mdss_edp_phy: phy@aec2a00 { compatible = "qcom,sc7280-edp-phy"; - reg = <0 0xaec2a00 0 0x19c>, - <0 0xaec2200 0 0xa0>, - <0 0xaec2600 0 0xa0>, - <0 0xaec2000 0 0x1c0>; + reg = <0 0x0aec2a00 0 0x19c>, + <0 0x0aec2200 0 0xa0>, + <0 0x0aec2600 0 0xa0>, + <0 0x0aec2000 0 0x1c0>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_EDP_CLKREF_EN>; @@ -4095,11 +4099,11 @@ mdss_dp: displayport-controller@ae90000 { compatible = "qcom,sc7280-dp"; - reg = <0 0xae90000 0 0x200>, - <0 0xae90200 0 0x200>, - <0 0xae90400 0 0xc00>, - <0 0xae91000 0 0x400>, - <0 0xae91400 0 0x400>; + reg = <0 0x0ae90000 0 0x200>, + <0 0x0ae90200 0 0x200>, + <0 0x0ae90400 0 0xc00>, + <0 0x0ae91000 0 0x400>, + <0 0x0ae91400 0 0x400>; interrupt-parent = <&mdss>; interrupts = <12>; @@ -4140,7 +4144,7 @@ port@1 { reg = <1>; - dp_out: endpoint { }; + mdss_dp_out: endpoint { }; }; }; @@ -4217,7 +4221,7 @@ #reset-cells = <1>; }; - aoss_qmp: power-controller@c300000 { + aoss_qmp: power-management@c300000 { compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp"; reg = <0 0x0c300000 0 0x400>; interrupts-extended = <&ipcc IPCC_CLIENT_AOP @@ -4246,8 +4250,8 @@ interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; qcom,ee = <0>; qcom,channel = <0>; - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <0>; interrupt-controller; #interrupt-cells = <4>; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts index 551768f97729..20c629172477 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -17,10 +17,12 @@ compatible = "qcom,sc8280xp-crd", "qcom,sc8280xp"; aliases { - serial0 = &qup2_uart17; + i2c4 = &i2c4; + i2c21 = &i2c21; + serial0 = &uart17; }; - backlight { + backlight: backlight { compatible = "pwm-backlight"; pwms = <&pmc8280c_lpg 3 1000000>; enable-gpios = <&pmc8280_1_gpios 8 GPIO_ACTIVE_HIGH>; @@ -34,6 +36,22 @@ stdout-path = "serial0:115200n8"; }; + vreg_edp_3p3: regulator-edp-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_EDP_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 25 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&edp_reg_en>; + + regulator-boot-on; + }; + vreg_edp_bl: regulator-edp-bl { compatible = "regulator-fixed"; @@ -112,6 +130,15 @@ regulator-boot-on; }; + + reserved-memory { + linux,cma { + compatible = "shared-dma-pool"; + size = <0x0 0x8000000>; + reusable; + linux,cma-default; + }; + }; }; &apps_rsc { @@ -134,7 +161,6 @@ regulator-max-microvolt = <1200000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; regulator-boot-on; - regulator-always-on; }; vreg_l4b: ldo4 { @@ -228,80 +254,60 @@ }; }; -&pcie2a { - perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; - - vddpe-3v3-supply = <&vreg_nvme>; - - pinctrl-names = "default"; - pinctrl-0 = <&pcie2a_default>; - +&dispcc0 { status = "okay"; }; -&pcie2a_phy { - vdda-phy-supply = <&vreg_l6d>; - vdda-pll-supply = <&vreg_l4d>; - +&mdss0 { status = "okay"; }; -&pcie3a { - perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; - - vddpe-3v3-supply = <&vreg_wwan>; - - pinctrl-names = "default"; - pinctrl-0 = <&pcie3a_default>; - - status = "okay"; -}; +&mdss0_dp3 { + compatible = "qcom,sc8280xp-edp"; -&pcie3a_phy { - vdda-phy-supply = <&vreg_l6d>; - vdda-pll-supply = <&vreg_l4d>; + data-lanes = <0 1 2 3>; status = "okay"; -}; -&pcie4 { - perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; + aux-bus { + panel { + compatible = "edp-panel"; + power-supply = <&vreg_edp_3p3>; - vddpe-3v3-supply = <&vreg_wlan>; + backlight = <&backlight>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie4_default>; - - status = "okay"; -}; - -&pcie4_phy { - vdda-phy-supply = <&vreg_l6d>; - vdda-pll-supply = <&vreg_l4d>; - - status = "okay"; -}; + ports { + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss0_dp3_out>; + }; + }; + }; + }; + }; -&pmc8280c_lpg { - status = "okay"; + ports { + port@1 { + reg = <1>; + mdss0_dp3_out: endpoint { + remote-endpoint = <&edp_panel_in>; + }; + }; + }; }; -&pmk8280_pon_pwrkey { - status = "okay"; -}; +&mdss0_dp3_phy { + vdda-phy-supply = <&vreg_l6b>; + vdda-pll-supply = <&vreg_l3b>; -&qup0 { status = "okay"; }; -&qup0_i2c4 { +&i2c4 { clock-frequency = <400000>; pinctrl-names = "default"; - pinctrl-0 = <&qup0_i2c4_default>; + pinctrl-0 = <&i2c4_default>; status = "okay"; @@ -318,19 +324,11 @@ }; }; -&qup1 { - status = "okay"; -}; - -&qup2 { - status = "okay"; -}; - -&qup2_i2c5 { +&i2c21 { clock-frequency = <400000>; pinctrl-names = "default"; - pinctrl-0 = <&qup2_i2c5_default>; + pinctrl-0 = <&i2c21_default>; status = "okay"; @@ -363,12 +361,83 @@ }; }; -&qup2_uart17 { - compatible = "qcom,geni-debug-uart"; +&pcie2a { + perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; + + vddpe-3v3-supply = <&vreg_nvme>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie2a_default>; + + status = "okay"; +}; + +&pcie2a_phy { + vdda-phy-supply = <&vreg_l6d>; + vdda-pll-supply = <&vreg_l4d>; status = "okay"; }; +&pcie3a { + perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; + + vddpe-3v3-supply = <&vreg_wwan>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie3a_default>; + + status = "okay"; +}; + +&pcie3a_phy { + vdda-phy-supply = <&vreg_l6d>; + vdda-pll-supply = <&vreg_l4d>; + + status = "okay"; +}; + +&pcie4 { + perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; + + vddpe-3v3-supply = <&vreg_wlan>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie4_default>; + + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l6d>; + vdda-pll-supply = <&vreg_l4d>; + + status = "okay"; +}; + +&pmc8280c_lpg { + status = "okay"; +}; + +&pmk8280_pon_pwrkey { + status = "okay"; +}; + +&qup0 { + status = "okay"; +}; + +&qup1 { + status = "okay"; +}; + +&qup2 { + status = "okay"; +}; + &remoteproc_adsp { firmware-name = "qcom/sc8280xp/qcadsp8280.mbn"; @@ -381,6 +450,12 @@ status = "okay"; }; +&uart17 { + compatible = "qcom,geni-debug-uart"; + + status = "okay"; +}; + &ufs_mem_hc { reset-gpios = <&tlmm 228 GPIO_ACTIVE_LOW>; @@ -494,6 +569,27 @@ &tlmm { gpio-reserved-ranges = <74 6>, <83 4>, <125 2>, <128 2>, <154 7>; + edp_reg_en: edp-reg-en-state { + pins = "gpio25"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + i2c4_default: i2c4-default-state { + pins = "gpio171", "gpio172"; + function = "qup4"; + drive-strength = <16>; + bias-disable; + }; + + i2c21_default: i2c21-default-state { + pins = "gpio81", "gpio82"; + function = "qup21"; + drive-strength = <16>; + bias-disable; + }; + kybd_default: kybd-default-state { disable-pins { pins = "gpio102"; @@ -590,22 +686,6 @@ }; }; - qup0_i2c4_default: qup0-i2c4-default-state { - pins = "gpio171", "gpio172"; - function = "qup4"; - - bias-disable; - drive-strength = <16>; - }; - - qup2_i2c5_default: qup2-i2c5-default-state { - pins = "gpio81", "gpio82"; - function = "qup21"; - - bias-disable; - drive-strength = <16>; - }; - tpad_default: tpad-default-state { int-n-pins { pins = "gpio182"; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 568c6be1ceaa..f936b020a71d 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -21,7 +21,38 @@ model = "Lenovo ThinkPad X13s"; compatible = "lenovo,thinkpad-x13s", "qcom,sc8280xp"; - backlight { + aliases { + i2c4 = &i2c4; + i2c21 = &i2c21; + }; + + wcd938x: audio-codec { + compatible = "qcom,wcd9380-codec"; + + pinctrl-names = "default"; + pinctrl-0 = <&wcd_default>; + + reset-gpios = <&tlmm 106 GPIO_ACTIVE_LOW>; + + vdd-buck-supply = <&vreg_s10b>; + vdd-rxtx-supply = <&vreg_s10b>; + vdd-io-supply = <&vreg_s10b>; + vdd-mic-bias-supply = <&vreg_bob>; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + #sound-dai-cells = <1>; + }; + + backlight: backlight { compatible = "pwm-backlight"; pwms = <&pmc8280c_lpg 3 1000000>; enable-gpios = <&pmc8280_1_gpios 8 GPIO_ACTIVE_HIGH>; @@ -31,52 +62,6 @@ pinctrl-0 = <&edp_bl_en>, <&edp_bl_pwm>; }; - thermal-zones { - skin-temp-thermal { - polling-delay-passive = <250>; - polling-delay = <0>; - thermal-sensors = <&pmk8280_adc_tm 5>; - - trips { - skin_temp_alert0: trip-point0 { - temperature = <55000>; - hysteresis = <1000>; - type = "passive"; - }; - - skin_temp_alert1: trip-point1 { - temperature = <58000>; - hysteresis = <1000>; - type = "passive"; - }; - - skin-temp-crit { - temperature = <73000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&skin_temp_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - - map1 { - trip = <&skin_temp_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - gpio-keys { compatible = "gpio-keys"; @@ -92,6 +77,22 @@ }; }; + vreg_edp_3p3: regulator-edp-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VCC3LCD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 25 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&edp_reg_en>; + + regulator-boot-on; + }; + vreg_edp_bl: regulator-edp-bl { compatible = "regulator-fixed"; @@ -141,6 +142,16 @@ regulator-boot-on; }; + vreg_vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + + regulator-name = "VPH_VCC3R9"; + regulator-min-microvolt = <3900000>; + regulator-max-microvolt = <3900000>; + + regulator-always-on; + }; + vreg_wlan: regulator-wlan { compatible = "regulator-fixed"; @@ -172,6 +183,61 @@ regulator-boot-on; }; + + reserved-memory { + linux,cma { + compatible = "shared-dma-pool"; + size = <0x0 0x8000000>; + reusable; + linux,cma-default; + }; + }; + + thermal-zones { + skin-temp-thermal { + polling-delay-passive = <250>; + polling-delay = <0>; + thermal-sensors = <&pmk8280_adc_tm 5>; + + trips { + skin_temp_alert0: trip-point0 { + temperature = <55000>; + hysteresis = <1000>; + type = "passive"; + }; + + skin_temp_alert1: trip-point1 { + temperature = <58000>; + hysteresis = <1000>; + type = "passive"; + }; + + skin-temp-crit { + temperature = <73000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&skin_temp_alert0>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + + map1 { + trip = <&skin_temp_alert1>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; }; &apps_rsc { @@ -181,6 +247,13 @@ vdd-l3-l5-supply = <&vreg_s11b>; + vreg_s10b: smps10 { + regulator-name = "vreg_s10b"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + vreg_s11b: smps11 { regulator-name = "vreg_s11b"; regulator-min-microvolt = <1272000>; @@ -188,6 +261,13 @@ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; + vreg_s12b: smps12 { + regulator-name = "vreg_s12b"; + regulator-min-microvolt = <984000>; + regulator-max-microvolt = <984000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + vreg_l3b: ldo3 { regulator-name = "vreg_l3b"; regulator-min-microvolt = <1200000>; @@ -209,13 +289,13 @@ regulator-max-microvolt = <880000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; regulator-boot-on; - regulator-always-on; /* FIXME: VDD_A_EDP_0_0P9 */ }; }; pmc8280c-rpmh-regulators { compatible = "qcom,pm8350c-rpmh-regulators"; qcom,pmic-id = "c"; + vdd-bob-supply = <&vreg_vph_pwr>; vreg_l1c: ldo1 { regulator-name = "vreg_l1c"; @@ -237,6 +317,13 @@ regulator-max-microvolt = <3072000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; + + vreg_bob: bob { + regulator-name = "vreg_bob"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + }; }; pmc8280-2-rpmh-regulators { @@ -282,6 +369,130 @@ }; }; +&dispcc0 { + status = "okay"; +}; + +&mdss0 { + status = "okay"; +}; + +&mdss0_dp3 { + compatible = "qcom,sc8280xp-edp"; + + data-lanes = <0 1 2 3>; + + status = "okay"; + + aux-bus { + panel { + compatible = "edp-panel"; + + backlight = <&backlight>; + power-supply = <&vreg_edp_3p3>; + + ports { + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss0_dp3_out>; + }; + }; + }; + }; + }; + + ports { + port@1 { + reg = <1>; + mdss0_dp3_out: endpoint { + remote-endpoint = <&edp_panel_in>; + }; + }; + }; +}; + +&mdss0_dp3_phy { + vdda-phy-supply = <&vreg_l6b>; + vdda-pll-supply = <&vreg_l3b>; + + status = "okay"; +}; + +&i2c4 { + clock-frequency = <400000>; + + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_default>; + + status = "okay"; + + /* FIXME: verify */ + touchscreen@10 { + compatible = "hid-over-i2c"; + reg = <0x10>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 175 IRQ_TYPE_LEVEL_LOW>; + vdd-supply = <&vreg_misc_3p3>; + + pinctrl-names = "default"; + pinctrl-0 = <&ts0_default>; + }; +}; + +&i2c21 { + clock-frequency = <400000>; + + pinctrl-names = "default"; + pinctrl-0 = <&i2c21_default>; + + status = "okay"; + + touchpad@15 { + compatible = "hid-over-i2c"; + reg = <0x15>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 182 IRQ_TYPE_LEVEL_LOW>; + vdd-supply = <&vreg_misc_3p3>; + + pinctrl-names = "default"; + pinctrl-0 = <&tpad_default>; + + wakeup-source; + + status = "disabled"; + }; + + touchpad@2c { + compatible = "hid-over-i2c"; + reg = <0x2c>; + + hid-descr-addr = <0x20>; + interrupts-extended = <&tlmm 182 IRQ_TYPE_LEVEL_LOW>; + vdd-supply = <&vreg_misc_3p3>; + + pinctrl-names = "default"; + pinctrl-0 = <&tpad_default>; + + wakeup-source; + }; + + keyboard@68 { + compatible = "hid-over-i2c"; + reg = <0x68>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>; + vdd-supply = <&vreg_misc_3p3>; + + pinctrl-names = "default"; + pinctrl-0 = <&kybd_default>; + + wakeup-source; + }; +}; + &pcie2a { perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; @@ -501,98 +712,157 @@ status = "okay"; }; -&qup0_i2c4 { - clock-frequency = <400000>; - - pinctrl-names = "default"; - pinctrl-0 = <&qup0_i2c4_default>; - +&qup1 { status = "okay"; +}; - /* FIXME: verify */ - touchscreen@10 { - compatible = "hid-over-i2c"; - reg = <0x10>; +&qup2 { + status = "okay"; +}; - hid-descr-addr = <0x1>; - interrupts-extended = <&tlmm 175 IRQ_TYPE_LEVEL_LOW>; - vdd-supply = <&vreg_misc_3p3>; +&remoteproc_adsp { + firmware-name = "qcom/sc8280xp/LENOVO/21BX/qcadsp8280.mbn"; - pinctrl-names = "default"; - pinctrl-0 = <&ts0_default>; - }; + status = "okay"; }; -&qup1 { +&remoteproc_nsp0 { + firmware-name = "qcom/sc8280xp/LENOVO/21BX/qccdsp8280.mbn"; + status = "okay"; }; -&qup2 { +&rxmacro { status = "okay"; }; -&qup2_i2c5 { - clock-frequency = <400000>; +&sound { + compatible = "qcom,sc8280xp-sndcard"; + model = "SC8280XP-LENOVO-X13S"; + audio-routing = + "SpkrLeft IN", "WSA_SPK1 OUT", + "SpkrRight IN", "WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC2", "MIC BIAS2", + "VA DMIC0", "MIC BIAS1", + "VA DMIC1", "MIC BIAS1", + "VA DMIC2", "MIC BIAS3", + "TX DMIC0", "MIC BIAS1", + "TX DMIC1", "MIC BIAS2", + "TX DMIC2", "MIC BIAS3", + "TX SWR_ADC1", "ADC2_OUTPUT"; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; - pinctrl-names = "default"; - pinctrl-0 = <&qup2_i2c5_default>; + codec { + sound-dai = <&wcd938x 0>, <&swr1 0>, <&rxmacro 0>; + }; - status = "okay"; + platform { + sound-dai = <&q6apm>; + }; + }; - touchpad@15 { - compatible = "hid-over-i2c"; - reg = <0x15>; + wcd-capture-dai-link { + link-name = "WCD Capture"; + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; - hid-descr-addr = <0x1>; - interrupts-extended = <&tlmm 182 IRQ_TYPE_LEVEL_LOW>; - vdd-supply = <&vreg_misc_3p3>; + codec { + sound-dai = <&wcd938x 1>, <&swr2 0>, <&txmacro 0>; + }; - pinctrl-names = "default"; - pinctrl-0 = <&tpad_default>; + platform { + sound-dai = <&q6apm>; + }; + }; - wakeup-source; + wsa-dai-link { + link-name = "WSA Playback"; + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; - status = "disabled"; - }; + codec { + sound-dai = <&left_spkr>, <&right_spkr>, <&swr0 0>, <&wsamacro 0>; + }; - touchpad@2c { - compatible = "hid-over-i2c"; - reg = <0x2c>; + platform { + sound-dai = <&q6apm>; + }; + }; - hid-descr-addr = <0x20>; - interrupts-extended = <&tlmm 182 IRQ_TYPE_LEVEL_LOW>; - vdd-supply = <&vreg_misc_3p3>; + va-dai-link { + link-name = "VA Capture"; + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; - pinctrl-names = "default"; - pinctrl-0 = <&tpad_default>; + platform { + sound-dai = <&q6apm>; + }; - wakeup-source; + codec { + sound-dai = <&vamacro 0>; + }; }; +}; - keyboard@68 { - compatible = "hid-over-i2c"; - reg = <0x68>; - - hid-descr-addr = <0x1>; - interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>; - vdd-supply = <&vreg_misc_3p3>; +&swr0 { + status = "okay"; + left_spkr: wsa8830-left@0,1 { + compatible = "sdw10217020200"; + reg = <0 1>; pinctrl-names = "default"; - pinctrl-0 = <&kybd_default>; + pinctrl-0 = <&spkr_1_sd_n_default>; + powerdown-gpios = <&tlmm 178 GPIO_ACTIVE_LOW>; + #thermal-sensor-cells = <0>; + sound-name-prefix = "SpkrLeft"; + #sound-dai-cells = <0>; + vdd-supply = <&vreg_s10b>; + }; - wakeup-source; + right_spkr: wsa8830-right@0,2 { + compatible = "sdw10217020200"; + reg = <0 2>; + pinctrl-names = "default"; + pinctrl-0 = <&spkr_2_sd_n_default>; + powerdown-gpios = <&tlmm 179 GPIO_ACTIVE_LOW>; + #thermal-sensor-cells = <0>; + sound-name-prefix = "SpkrRight"; + #sound-dai-cells = <0>; + vdd-supply = <&vreg_s10b>; }; }; -&remoteproc_adsp { - firmware-name = "qcom/sc8280xp/LENOVO/21BX/qcadsp8280.mbn"; - +&swr1 { status = "okay"; + + wcd_rx: wcd9380-rx@0,4 { + compatible = "sdw20217010d00"; + reg = <0 4>; + qcom,rx-port-mapping = <1 2 3 4 5>; + }; }; -&remoteproc_nsp0 { - firmware-name = "qcom/sc8280xp/LENOVO/21BX/qccdsp8280.mbn"; +&swr2 { + status = "okay"; + wcd_tx: wcd9380-tx@0,3 { + compatible = "sdw20217010d00"; + reg = <0 3>; + qcom,tx-port-mapping = <1 1 2 3>; + }; +}; + +&txmacro { status = "okay"; }; @@ -644,12 +914,31 @@ status = "okay"; }; +&vamacro { + pinctrl-0 = <&dmic01_default>, <&dmic02_default>; + pinctrl-names = "default"; + + vdd-micb-supply = <&vreg_s10b>; + + qcom,dmic-sample-rate = <600000>; + + status = "okay"; +}; + +&wsamacro { + status = "okay"; +}; + &xo_board_clk { clock-frequency = <38400000>; }; /* PINCTRL */ +&lpass_tlmm { + status = "okay"; +}; + &pmc8280_1_gpios { edp_bl_en: edp-bl-en-state { pins = "gpio8"; @@ -691,6 +980,13 @@ &tlmm { gpio-reserved-ranges = <70 2>, <74 6>, <83 4>, <125 2>, <128 2>, <154 7>; + edp_reg_en: edp-reg-en-state { + pins = "gpio25"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + hall_int_n_default: hall-int-n-state { pins = "gpio107"; function = "gpio"; @@ -698,6 +994,20 @@ bias-disable; }; + i2c4_default: i2c4-default-state { + pins = "gpio171", "gpio172"; + function = "qup4"; + drive-strength = <16>; + bias-disable; + }; + + i2c21_default: i2c21-default-state { + pins = "gpio81", "gpio82"; + function = "qup21"; + drive-strength = <16>; + bias-disable; + }; + kybd_default: kybd-default-state { disable-pins { pins = "gpio102"; @@ -794,18 +1104,24 @@ }; }; - qup0_i2c4_default: qup0-i2c4-default-state { - pins = "gpio171", "gpio172"; - function = "qup4"; - bias-disable; - drive-strength = <16>; + spkr_1_sd_n_default: spkr-1-sd-n-default-state { + perst-n-pins { + pins = "gpio178"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; }; - qup2_i2c5_default: qup2-i2c5-default-state { - pins = "gpio81", "gpio82"; - function = "qup21"; - bias-disable; - drive-strength = <16>; + spkr_2_sd_n_default: spkr-2-sd-n-default-state { + perst-n-pins { + pins = "gpio179"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; }; tpad_default: tpad-default-state { @@ -830,4 +1146,12 @@ drive-strength = <16>; }; }; + + wcd_default: wcd-default-state { + reset-pins { + pins = "gpio106"; + function = "gpio"; + bias-disable; + }; + }; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 109c9d2b684d..fa2d0d7d1367 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -4,14 +4,18 @@ * Copyright (c) 2022, Linaro Limited */ +#include <dt-bindings/clock/qcom,dispcc-sc8280xp.h> #include <dt-bindings/clock/qcom,gcc-sc8280xp.h> #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/interconnect/qcom,osm-l3.h> #include <dt-bindings/interconnect/qcom,sc8280xp.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/mailbox/qcom-ipcc.h> +#include <dt-bindings/phy/phy-qcom-qmp.h> #include <dt-bindings/power/qcom-rpmpd.h> +#include <dt-bindings/soc/qcom,gpr.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> +#include <dt-bindings/sound/qcom,q6afe.h> #include <dt-bindings/thermal/thermal.h> / { @@ -33,186 +37,6 @@ }; }; - cpu0_opp_table: cpu0-opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-peak-kBps = <(300000 * 32)>; - }; - opp-403200000 { - opp-hz = /bits/ 64 <403200000>; - opp-peak-kBps = <(384000 * 32)>; - }; - opp-499200000 { - opp-hz = /bits/ 64 <499200000>; - opp-peak-kBps = <(480000 * 32)>; - }; - opp-595200000 { - opp-hz = /bits/ 64 <595200000>; - opp-peak-kBps = <(576000 * 32)>; - }; - opp-691200000 { - opp-hz = /bits/ 64 <691200000>; - opp-peak-kBps = <(672000 * 32)>; - }; - opp-806400000 { - opp-hz = /bits/ 64 <806400000>; - opp-peak-kBps = <(768000 * 32)>; - }; - opp-902400000 { - opp-hz = /bits/ 64 <902400000>; - opp-peak-kBps = <(864000 * 32)>; - }; - opp-1017600000 { - opp-hz = /bits/ 64 <1017600000>; - opp-peak-kBps = <(960000 * 32)>; - }; - opp-1113600000 { - opp-hz = /bits/ 64 <1113600000>; - opp-peak-kBps = <(1075200 * 32)>; - }; - opp-1209600000 { - opp-hz = /bits/ 64 <1209600000>; - opp-peak-kBps = <(1171200 * 32)>; - }; - opp-1324800000 { - opp-hz = /bits/ 64 <1324800000>; - opp-peak-kBps = <(1267200 * 32)>; - }; - opp-1440000000 { - opp-hz = /bits/ 64 <1440000000>; - opp-peak-kBps = <(1363200 * 32)>; - }; - opp-1555200000 { - opp-hz = /bits/ 64 <1555200000>; - opp-peak-kBps = <(1536000 * 32)>; - }; - opp-1670400000 { - opp-hz = /bits/ 64 <1670400000>; - opp-peak-kBps = <(1612800 * 32)>; - }; - opp-1785600000 { - opp-hz = /bits/ 64 <1785600000>; - opp-peak-kBps = <(1689600 * 32)>; - }; - opp-1881600000 { - opp-hz = /bits/ 64 <1881600000>; - opp-peak-kBps = <(1689600 * 32)>; - }; - opp-1996800000 { - opp-hz = /bits/ 64 <1996800000>; - opp-peak-kBps = <(1689600 * 32)>; - }; - opp-2112000000 { - opp-hz = /bits/ 64 <2112000000>; - opp-peak-kBps = <(1689600 * 32)>; - }; - opp-2227200000 { - opp-hz = /bits/ 64 <2227200000>; - opp-peak-kBps = <(1689600 * 32)>; - }; - opp-2342400000 { - opp-hz = /bits/ 64 <2342400000>; - opp-peak-kBps = <(1689600 * 32)>; - }; - opp-2438400000 { - opp-hz = /bits/ 64 <2438400000>; - opp-peak-kBps = <(1689600 * 32)>; - }; - }; - - cpu4_opp_table: cpu4-opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-825600000 { - opp-hz = /bits/ 64 <825600000>; - opp-peak-kBps = <(768000 * 32)>; - }; - opp-940800000 { - opp-hz = /bits/ 64 <940800000>; - opp-peak-kBps = <(864000 * 32)>; - }; - opp-1056000000 { - opp-hz = /bits/ 64 <1056000000>; - opp-peak-kBps = <(960000 * 32)>; - }; - opp-1171200000 { - opp-hz = /bits/ 64 <1171200000>; - opp-peak-kBps = <(1171200 * 32)>; - }; - opp-1286400000 { - opp-hz = /bits/ 64 <1286400000>; - opp-peak-kBps = <(1267200 * 32)>; - }; - opp-1401600000 { - opp-hz = /bits/ 64 <1401600000>; - opp-peak-kBps = <(1363200 * 32)>; - }; - opp-1516800000 { - opp-hz = /bits/ 64 <1516800000>; - opp-peak-kBps = <(1459200 * 32)>; - }; - opp-1632000000 { - opp-hz = /bits/ 64 <1632000000>; - opp-peak-kBps = <(1612800 * 32)>; - }; - opp-1747200000 { - opp-hz = /bits/ 64 <1747200000>; - opp-peak-kBps = <(1689600 * 32)>; - }; - opp-1862400000 { - opp-hz = /bits/ 64 <1862400000>; - opp-peak-kBps = <(1689600 * 32)>; - }; - opp-1977600000 { - opp-hz = /bits/ 64 <1977600000>; - opp-peak-kBps = <(1689600 * 32)>; - }; - opp-2073600000 { - opp-hz = /bits/ 64 <2073600000>; - opp-peak-kBps = <(1689600 * 32)>; - }; - opp-2169600000 { - opp-hz = /bits/ 64 <2169600000>; - opp-peak-kBps = <(1689600 * 32)>; - }; - opp-2284800000 { - opp-hz = /bits/ 64 <2284800000>; - opp-peak-kBps = <(1689600 * 32)>; - }; - opp-2400000000 { - opp-hz = /bits/ 64 <2400000000>; - opp-peak-kBps = <(1689600 * 32)>; - }; - opp-2496000000 { - opp-hz = /bits/ 64 <2496000000>; - opp-peak-kBps = <(1689600 * 32)>; - }; - opp-2592000000 { - opp-hz = /bits/ 64 <2592000000>; - opp-peak-kBps = <(1689600 * 32)>; - }; - opp-2688000000 { - opp-hz = /bits/ 64 <2688000000>; - opp-peak-kBps = <(1689600 * 32)>; - }; - opp-2803200000 { - opp-hz = /bits/ 64 <2803200000>; - opp-peak-kBps = <(1689600 * 32)>; - }; - opp-2899200000 { - opp-hz = /bits/ 64 <2899200000>; - opp-peak-kBps = <(1689600 * 32)>; - }; - opp-2995200000 { - opp-hz = /bits/ 64 <2995200000>; - opp-peak-kBps = <(1689600 * 32)>; - }; - }; - cpus { #address-cells = <2>; #size-cells = <0>; @@ -232,9 +56,11 @@ #cooling-cells = <2>; L2_0: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; L3_0: l3-cache { compatible = "cache"; + cache-level = <3>; }; }; }; @@ -254,6 +80,7 @@ #cooling-cells = <2>; L2_100: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -273,6 +100,7 @@ #cooling-cells = <2>; L2_200: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -292,6 +120,7 @@ #cooling-cells = <2>; L2_300: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -311,6 +140,7 @@ #cooling-cells = <2>; L2_400: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -330,6 +160,7 @@ #cooling-cells = <2>; L2_500: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -349,6 +180,7 @@ #cooling-cells = <2>; L2_600: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -368,6 +200,7 @@ #cooling-cells = <2>; L2_700: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -528,6 +361,200 @@ reg = <0x0 0x80000000 0x0 0x0>; }; + cpu0_opp_table: opp-table-cpu0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-peak-kBps = <(300000 * 32)>; + }; + opp-403200000 { + opp-hz = /bits/ 64 <403200000>; + opp-peak-kBps = <(384000 * 32)>; + }; + opp-499200000 { + opp-hz = /bits/ 64 <499200000>; + opp-peak-kBps = <(480000 * 32)>; + }; + opp-595200000 { + opp-hz = /bits/ 64 <595200000>; + opp-peak-kBps = <(576000 * 32)>; + }; + opp-691200000 { + opp-hz = /bits/ 64 <691200000>; + opp-peak-kBps = <(672000 * 32)>; + }; + opp-806400000 { + opp-hz = /bits/ 64 <806400000>; + opp-peak-kBps = <(768000 * 32)>; + }; + opp-902400000 { + opp-hz = /bits/ 64 <902400000>; + opp-peak-kBps = <(864000 * 32)>; + }; + opp-1017600000 { + opp-hz = /bits/ 64 <1017600000>; + opp-peak-kBps = <(960000 * 32)>; + }; + opp-1113600000 { + opp-hz = /bits/ 64 <1113600000>; + opp-peak-kBps = <(1075200 * 32)>; + }; + opp-1209600000 { + opp-hz = /bits/ 64 <1209600000>; + opp-peak-kBps = <(1171200 * 32)>; + }; + opp-1324800000 { + opp-hz = /bits/ 64 <1324800000>; + opp-peak-kBps = <(1267200 * 32)>; + }; + opp-1440000000 { + opp-hz = /bits/ 64 <1440000000>; + opp-peak-kBps = <(1363200 * 32)>; + }; + opp-1555200000 { + opp-hz = /bits/ 64 <1555200000>; + opp-peak-kBps = <(1536000 * 32)>; + }; + opp-1670400000 { + opp-hz = /bits/ 64 <1670400000>; + opp-peak-kBps = <(1612800 * 32)>; + }; + opp-1785600000 { + opp-hz = /bits/ 64 <1785600000>; + opp-peak-kBps = <(1689600 * 32)>; + }; + opp-1881600000 { + opp-hz = /bits/ 64 <1881600000>; + opp-peak-kBps = <(1689600 * 32)>; + }; + opp-1996800000 { + opp-hz = /bits/ 64 <1996800000>; + opp-peak-kBps = <(1689600 * 32)>; + }; + opp-2112000000 { + opp-hz = /bits/ 64 <2112000000>; + opp-peak-kBps = <(1689600 * 32)>; + }; + opp-2227200000 { + opp-hz = /bits/ 64 <2227200000>; + opp-peak-kBps = <(1689600 * 32)>; + }; + opp-2342400000 { + opp-hz = /bits/ 64 <2342400000>; + opp-peak-kBps = <(1689600 * 32)>; + }; + opp-2438400000 { + opp-hz = /bits/ 64 <2438400000>; + opp-peak-kBps = <(1689600 * 32)>; + }; + }; + + cpu4_opp_table: opp-table-cpu4 { + compatible = "operating-points-v2"; + opp-shared; + + opp-825600000 { + opp-hz = /bits/ 64 <825600000>; + opp-peak-kBps = <(768000 * 32)>; + }; + opp-940800000 { + opp-hz = /bits/ 64 <940800000>; + opp-peak-kBps = <(864000 * 32)>; + }; + opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-peak-kBps = <(960000 * 32)>; + }; + opp-1171200000 { + opp-hz = /bits/ 64 <1171200000>; + opp-peak-kBps = <(1171200 * 32)>; + }; + opp-1286400000 { + opp-hz = /bits/ 64 <1286400000>; + opp-peak-kBps = <(1267200 * 32)>; + }; + opp-1401600000 { + opp-hz = /bits/ 64 <1401600000>; + opp-peak-kBps = <(1363200 * 32)>; + }; + opp-1516800000 { + opp-hz = /bits/ 64 <1516800000>; + opp-peak-kBps = <(1459200 * 32)>; + }; + opp-1632000000 { + opp-hz = /bits/ 64 <1632000000>; + opp-peak-kBps = <(1612800 * 32)>; + }; + opp-1747200000 { + opp-hz = /bits/ 64 <1747200000>; + opp-peak-kBps = <(1689600 * 32)>; + }; + opp-1862400000 { + opp-hz = /bits/ 64 <1862400000>; + opp-peak-kBps = <(1689600 * 32)>; + }; + opp-1977600000 { + opp-hz = /bits/ 64 <1977600000>; + opp-peak-kBps = <(1689600 * 32)>; + }; + opp-2073600000 { + opp-hz = /bits/ 64 <2073600000>; + opp-peak-kBps = <(1689600 * 32)>; + }; + opp-2169600000 { + opp-hz = /bits/ 64 <2169600000>; + opp-peak-kBps = <(1689600 * 32)>; + }; + opp-2284800000 { + opp-hz = /bits/ 64 <2284800000>; + opp-peak-kBps = <(1689600 * 32)>; + }; + opp-2400000000 { + opp-hz = /bits/ 64 <2400000000>; + opp-peak-kBps = <(1689600 * 32)>; + }; + opp-2496000000 { + opp-hz = /bits/ 64 <2496000000>; + opp-peak-kBps = <(1689600 * 32)>; + }; + opp-2592000000 { + opp-hz = /bits/ 64 <2592000000>; + opp-peak-kBps = <(1689600 * 32)>; + }; + opp-2688000000 { + opp-hz = /bits/ 64 <2688000000>; + opp-peak-kBps = <(1689600 * 32)>; + }; + opp-2803200000 { + opp-hz = /bits/ 64 <2803200000>; + opp-peak-kBps = <(1689600 * 32)>; + }; + opp-2899200000 { + opp-hz = /bits/ 64 <2899200000>; + opp-peak-kBps = <(1689600 * 32)>; + }; + opp-2995200000 { + opp-hz = /bits/ 64 <2995200000>; + opp-peak-kBps = <(1689600 * 32)>; + }; + }; + + qup_opp_table_100mhz: opp-table-qup100mhz { + compatible = "operating-points-v2"; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + }; + pmu { compatible = "arm,armv8-pmuv3"; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; @@ -537,74 +564,60 @@ compatible = "arm,psci-1.0"; method = "smc"; - CPU_PD0: cpu0 { + CPU_PD0: power-domain-cpu0 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; - CPU_PD1: cpu1 { + CPU_PD1: power-domain-cpu1 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; - CPU_PD2: cpu2 { + CPU_PD2: power-domain-cpu2 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; - CPU_PD3: cpu3 { + CPU_PD3: power-domain-cpu3 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; - CPU_PD4: cpu4 { + CPU_PD4: power-domain-cpu4 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&BIG_CPU_SLEEP_0>; }; - CPU_PD5: cpu5 { + CPU_PD5: power-domain-cpu5 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&BIG_CPU_SLEEP_0>; }; - CPU_PD6: cpu6 { + CPU_PD6: power-domain-cpu6 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&BIG_CPU_SLEEP_0>; }; - CPU_PD7: cpu7 { + CPU_PD7: power-domain-cpu7 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&BIG_CPU_SLEEP_0>; }; - CLUSTER_PD: cpu-cluster0 { + CLUSTER_PD: power-domain-cpu-cluster0 { #power-domain-cells = <0>; domain-idle-states = <&CLUSTER_SLEEP_0>; }; }; - qup_opp_table_100mhz: qup-100mhz-opp-table { - compatible = "operating-points-v2"; - - opp-75000000 { - opp-hz = /bits/ 64 <75000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - }; - reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -762,7 +775,7 @@ <0>, <0>, <0>, - <&usb_0_ssphy>, + <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, <0>, <0>, <0>, @@ -770,7 +783,7 @@ <0>, <0>, <0>, - <&usb_1_ssphy>, + <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, <0>, <0>, <0>, @@ -813,7 +826,71 @@ status = "disabled"; - qup2_uart17: serial@884000 { + i2c16: i2c@880000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00880000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + spi16: spi@880000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00880000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + i2c17: i2c@884000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00884000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + spi17: spi@884000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00884000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + uart17: serial@884000 { compatible = "qcom,geni-uart"; reg = <0 0x00884000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; @@ -827,7 +904,103 @@ status = "disabled"; }; - qup2_i2c5: i2c@894000 { + i2c18: i2c@888000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00888000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + spi18: spi@888000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00888000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + i2c19: i2c@88c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x0088c000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + spi19: spi@88c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x0088c000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + i2c20: i2c@890000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00890000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + spi20: spi@890000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00890000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + i2c21: i2c@894000 { compatible = "qcom,geni-i2c"; reg = <0 0x00894000 0 0x4000>; clock-names = "se"; @@ -842,6 +1015,86 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; + + spi21: spi@894000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00894000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + i2c22: i2c@898000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00898000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + spi22: spi@898000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00898000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + i2c23: i2c@89c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x0089c000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + spi23: spi@89c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x0089c000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; }; qup0: geniqup@9c0000 { @@ -858,7 +1111,135 @@ status = "disabled"; - qup0_i2c4: i2c@990000 { + i2c0: i2c@980000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00980000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + spi0: spi@980000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00980000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + i2c1: i2c@984000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00984000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + spi1: spi@984000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00984000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + i2c2: i2c@988000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00988000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + spi2: spi@988000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00988000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + i2c3: i2c@98c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x0098c000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + spi3: spi@98c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x0098c000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + i2c4: i2c@990000 { compatible = "qcom,geni-i2c"; reg = <0 0x00990000 0 0x4000>; clock-names = "se"; @@ -873,6 +1254,118 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; + + spi4: spi@990000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00990000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + i2c5: i2c@994000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00994000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + spi5: spi@994000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00994000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + i2c6: i2c@998000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00998000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + spi6: spi@998000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00998000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + i2c7: i2c@99c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x0099c000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + spi7: spi@99c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x0099c000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; }; qup1: geniqup@ac0000 { @@ -888,6 +1381,269 @@ ranges; status = "disabled"; + + i2c8: i2c@a80000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a80000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + spi8: spi@a80000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a80000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + i2c9: i2c@a84000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a84000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + spi9: spi@a84000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a84000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + i2c10: i2c@a88000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a88000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + spi10: spi@a88000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a88000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + i2c11: i2c@a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a8c000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + spi11: spi@a8c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a8c000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + i2c12: i2c@a90000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a90000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + spi12: spi@a90000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a90000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + i2c13: i2c@a94000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a94000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + spi13: spi@a94000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a94000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + i2c14: i2c@a98000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a98000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + spi14: spi@a98000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a98000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + i2c15: i2c@a9c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a9c000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + spi15: spi@a9c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a9c000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + }; + + rng: rng@10d3000 { + compatible = "qcom,prng-ee"; + reg = <0 0x010d3000 0 0x1000>; + clocks = <&rpmhcc RPMH_HWKM_CLK>; + clock-names = "core"; }; pcie4: pcie@1c00000 { @@ -1670,45 +2426,396 @@ label = "lpass"; qcom,remote-pid = <2>; + + gpr { + compatible = "qcom,gpr"; + qcom,glink-channels = "adsp_apps"; + qcom,domain = <GPR_DOMAIN_ID_ADSP>; + qcom,intents = <512 20>; + #address-cells = <1>; + #size-cells = <0>; + + q6apm: service@1 { + compatible = "qcom,q6apm"; + reg = <GPR_APM_MODULE_IID>; + #sound-dai-cells = <0>; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + q6apmdai: dais { + compatible = "qcom,q6apm-dais"; + iommus = <&apps_smmu 0x0c01 0x0>; + }; + + q6apmbedai: bedais { + compatible = "qcom,q6apm-lpass-dais"; + #sound-dai-cells = <1>; + }; + }; + + q6prm: service@2 { + compatible = "qcom,q6prm"; + reg = <GPR_PRM_MODULE_IID>; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + q6prmcc: clock-controller { + compatible = "qcom,q6prm-lpass-clocks"; + #clock-cells = <2>; + }; + }; + }; }; }; - usb_0_qmpphy: phy-wrapper@88ec000 { - compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; - reg = <0 0x088ec000 0 0x1e4>, - <0 0x088eb000 0 0x40>, - <0 0x088ed000 0 0x1c8>; + rxmacro: rxmacro@3200000 { + compatible = "qcom,sc8280xp-lpass-rx-macro"; + reg = <0 0x03200000 0 0x1000>; + clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&vamacro>; + clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; + assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + assigned-clock-rates = <19200000>, <19200000>; + + clock-output-names = "mclk"; + #clock-cells = <0>; + #sound-dai-cells = <1>; + + pinctrl-names = "default"; + pinctrl-0 = <&rx_swr_default>; + + status = "disabled"; + }; + + /* RX */ + swr1: soundwire-controller@3210000 { + compatible = "qcom,soundwire-v1.6.0"; + reg = <0 0x03210000 0 0x2000>; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rxmacro>; + clock-names = "iface"; + label = "RX"; + + qcom,din-ports = <0>; + qcom,dout-ports = <5>; + + qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; + qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>; + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>; + qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; + qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; + qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; + qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; + qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; + + #sound-dai-cells = <1>; #address-cells = <2>; - #size-cells = <2>; - ranges; + #size-cells = <0>; + + status = "disabled"; + }; + + txmacro: txmacro@3220000 { + compatible = "qcom,sc8280xp-lpass-tx-macro"; + reg = <0 0x03220000 0 0x1000>; + pinctrl-names = "default"; + pinctrl-0 = <&tx_swr_default>; + clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&vamacro>; + + clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; + assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + assigned-clock-rates = <19200000>, <19200000>; + clock-output-names = "mclk"; + + #clock-cells = <0>; + #sound-dai-cells = <1>; + + status = "disabled"; + }; + + wsamacro: codec@3240000 { + compatible = "qcom,sc8280xp-lpass-wsa-macro"; + reg = <0 0x03240000 0 0x1000>; + clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&vamacro>; + clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; + assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + assigned-clock-rates = <19200000>, <19200000>; + + #clock-cells = <0>; + clock-output-names = "mclk"; + #sound-dai-cells = <1>; + + pinctrl-names = "default"; + pinctrl-0 = <&wsa_swr_default>; + + status = "disabled"; + }; + + /* WSA */ + swr0: soundwire-controller@3250000 { + reg = <0 0x03250000 0 0x2000>; + compatible = "qcom,soundwire-v1.6.0"; + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&wsamacro>; + clock-names = "iface"; + + qcom,din-ports = <2>; + qcom,dout-ports = <6>; + + qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; + qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; + qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; + qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + + #sound-dai-cells = <1>; + #address-cells = <2>; + #size-cells = <0>; + + status = "disabled"; + }; + + /* TX */ + swr2: soundwire-controller@3330000 { + compatible = "qcom,soundwire-v1.6.0"; + reg = <0 0x03330000 0 0x2000>; + interrupts-extended = <&intc GIC_SPI 959 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "core", "wake"; + + clocks = <&vamacro>; + clock-names = "iface"; + label = "TX"; + #sound-dai-cells = <1>; + #address-cells = <2>; + #size-cells = <0>; + + qcom,din-ports = <4>; + qcom,dout-ports = <0>; + qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03 0x03>; + qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02 0x01>; + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; + qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; + qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; + qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; + qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff 0xff>; + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; + qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00 0x00>; + + status = "disabled"; + }; + + vamacro: codec@3370000 { + compatible = "qcom,sc8280xp-lpass-va-macro"; + reg = <0 0x03370000 0 0x1000>; + clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "mclk", "macro", "dcodec", "npl"; + assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + assigned-clock-rates = <19200000>; + + #clock-cells = <0>; + clock-output-names = "fsgen"; + #sound-dai-cells = <1>; + + status = "disabled"; + }; + + lpass_tlmm: pinctrl@33c0000 { + compatible = "qcom,sc8280xp-lpass-lpi-pinctrl"; + reg = <0 0x33c0000 0x0 0x20000>, + <0 0x3550000 0x0 0x10000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 18>; + + clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", "audio"; + + status = "disabled"; + + tx_swr_default: tx-swr-default-state { + clk-pins { + pins = "gpio0"; + function = "swr_tx_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio1", "gpio2"; + function = "swr_tx_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + + rx_swr_default: rx-swr-default-state { + clk-pins { + pins = "gpio3"; + function = "swr_rx_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio4", "gpio5"; + function = "swr_rx_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + + dmic01_default: dmic01-default-state { + clk-pins { + pins = "gpio6"; + function = "dmic1_clk"; + drive-strength = <8>; + output-high; + }; + + data-pins { + pins = "gpio7"; + function = "dmic1_data"; + drive-strength = <8>; + input-enable; + }; + }; + + dmic01_sleep: dmic01-sleep-state { + clk-pins { + pins = "gpio6"; + function = "dmic1_clk"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + data-pins { + pins = "gpio7"; + function = "dmic1_data"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + }; + + dmic02_default: dmic02-default-state { + clk-pins { + pins = "gpio8"; + function = "dmic2_clk"; + drive-strength = <8>; + output-high; + }; + + data-pins { + pins = "gpio9"; + function = "dmic2_data"; + drive-strength = <8>; + input-enable; + }; + }; + + dmic02_sleep: dmic02-sleep-state { + clk-pins { + pins = "gpio8"; + function = "dmic2_clk"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + data-pins { + pins = "gpio9"; + function = "dmic2_data"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + }; + + wsa_swr_default: wsa-swr-default-state { + clk-pins { + pins = "gpio10"; + function = "wsa_swr_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio11"; + function = "wsa_swr_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + + }; + }; + + wsa2_swr_default: wsa2-swr-default-state { + clk-pins { + pins = "gpio15"; + function = "wsa2_swr_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio16"; + function = "wsa2_swr_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + }; + + usb_0_qmpphy: phy@88eb000 { + compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; + reg = <0 0x088eb000 0 0x4000>; clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, - <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_USB4_EUD_CLKREF_CLK>, - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; - clock-names = "aux", "ref_clk_src", "ref", "com_aux"; + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "aux", "ref", "com_aux", "usb3_pipe"; + + power-domains = <&gcc USB30_PRIM_GDSC>; resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, - <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; + <&gcc GCC_USB4_DP_PHY_PRIM_BCR>; reset-names = "phy", "common"; - power-domains = <&gcc USB30_PRIM_GDSC>; + #clock-cells = <1>; + #phy-cells = <1>; status = "disabled"; - - usb_0_ssphy: usb3-phy@88eb400 { - reg = <0 0x088eb400 0 0x100>, - <0 0x088eb600 0 0x3ec>, - <0 0x088ec400 0 0x364>, - <0 0x088eba00 0 0x100>, - <0 0x088ebc00 0 0x3ec>, - <0 0x088ec200 0 0x18>; - #phy-cells = <0>; - #clock-cells = <0>; - clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb0_phy_pipe_clk_src"; - }; }; usb_1_hsphy: phy@8902000 { @@ -1725,47 +2832,67 @@ status = "disabled"; }; - usb_1_qmpphy: phy-wrapper@8904000 { + usb_1_qmpphy: phy@8903000 { compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; - reg = <0 0x08904000 0 0x1e4>, - <0 0x08903000 0 0x40>, - <0 0x08905000 0 0x1c8>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + reg = <0 0x08903000 0 0x4000>; clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, - <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_USB4_CLKREF_CLK>, - <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; - clock-names = "aux", "ref_clk_src", "ref", "com_aux"; + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; + clock-names = "aux", "ref", "com_aux", "usb3_pipe"; + + power-domains = <&gcc USB30_SEC_GDSC>; resets = <&gcc GCC_USB3_PHY_SEC_BCR>, <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>; reset-names = "phy", "common"; - power-domains = <&gcc USB30_SEC_GDSC>; + #clock-cells = <1>; + #phy-cells = <1>; status = "disabled"; + }; - usb_1_ssphy: usb3-phy@8903400 { - reg = <0 0x08903400 0 0x100>, - <0 0x08903600 0 0x3ec>, - <0 0x08904400 0 0x364>, - <0 0x08903a00 0 0x100>, - <0 0x08903c00 0 0x3ec>, - <0 0x08904200 0 0x18>; - #phy-cells = <0>; - #clock-cells = <0>; - clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb1_phy_pipe_clk_src"; - }; + mdss1_dp0_phy: phy@8909a00 { + compatible = "qcom,sc8280xp-dp-phy"; + reg = <0 0x08909a00 0 0x19c>, + <0 0x08909200 0 0xec>, + <0 0x08909600 0 0xec>, + <0 0x08909000 0 0x1c8>; + + clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc1 DISP_CC_MDSS_AHB_CLK>; + clock-names = "aux", "cfg_ahb"; + power-domains = <&rpmhpd SC8280XP_MX>; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + mdss1_dp1_phy: phy@890ca00 { + compatible = "qcom,sc8280xp-dp-phy"; + reg = <0 0x0890ca00 0 0x19c>, + <0 0x0890c200 0 0xec>, + <0 0x0890c600 0 0xec>, + <0 0x0890c000 0 0x1c8>; + + clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>, + <&dispcc1 DISP_CC_MDSS_AHB_CLK>; + clock-names = "aux", "cfg_ahb"; + power-domains = <&rpmhpd SC8280XP_MX>; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; }; pmu@9091000 { compatible = "qcom,sc8280xp-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; - reg = <0 0x9091000 0 0x1000>; + reg = <0 0x09091000 0 0x1000>; interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; @@ -1894,6 +3021,7 @@ "ss_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; + required-opps = <&rpmhpd_opp_nom>; resets = <&gcc GCC_USB30_PRIM_BCR>; @@ -1910,7 +3038,7 @@ reg = <0 0x0a600000 0 0xcd00>; interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; iommus = <&apps_smmu 0x820 0x0>; - phys = <&usb_0_hsphy>, <&usb_0_ssphy>; + phys = <&usb_0_hsphy>, <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; }; }; @@ -1948,6 +3076,7 @@ "ss_phy_irq"; power-domains = <&gcc USB30_SEC_GDSC>; + required-opps = <&rpmhpd_opp_nom>; resets = <&gcc GCC_USB30_SEC_BCR>; @@ -1964,11 +3093,319 @@ reg = <0 0x0a800000 0 0xcd00>; interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>; iommus = <&apps_smmu 0x860 0x0>; - phys = <&usb_1_hsphy>, <&usb_1_ssphy>; + phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; }; }; + mdss0: display-subsystem@ae00000 { + compatible = "qcom,sc8280xp-mdss"; + reg = <0 0x0ae00000 0 0x1000>; + reg-names = "mdss"; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&dispcc0 DISP_CC_MDSS_AHB_CLK>, + <&dispcc0 DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", + "ahb", + "core"; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, + <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + iommus = <&apps_smmu 0x1000 0x402>; + power-domains = <&dispcc0 MDSS_GDSC>; + resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>; + + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + mdss0_mdp: display-controller@ae01000 { + compatible = "qcom,sc8280xp-dpu"; + reg = <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc0 DISP_CC_MDSS_AHB_CLK>, + <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc0 DISP_CC_MDSS_MDP_CLK>, + <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + interrupt-parent = <&mdss0>; + interrupts = <0>; + power-domains = <&rpmhpd SC8280XP_MMCX>; + + assigned-clocks = <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + operating-points-v2 = <&mdss0_mdp_opp_table>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@5 { + reg = <5>; + mdss0_intf5_out: endpoint { + remote-endpoint = <&mdss0_dp3_in>; + }; + }; + + port@6 { + reg = <6>; + mdss0_intf6_out: endpoint { + remote-endpoint = <&mdss0_dp2_in>; + }; + }; + }; + + mdss0_mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_turbo_l1>; + }; + }; + }; + + mdss0_dp2: displayport-controller@ae9a000 { + compatible = "qcom,sc8280xp-dp"; + reg = <0 0xae9a000 0 0x200>, + <0 0xae9a200 0 0x200>, + <0 0xae9a400 0 0x600>, + <0 0xae9b000 0 0x400>; + + clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, + <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>, + <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK>, + <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, + <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; + clock-names = "core_iface", "core_aux", + "ctrl_link", + "ctrl_link_iface", "stream_pixel"; + interrupt-parent = <&mdss0>; + interrupts = <14>; + phys = <&mdss0_dp2_phy>; + phy-names = "dp"; + power-domains = <&rpmhpd SC8280XP_MMCX>; + + assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, + <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>; + operating-points-v2 = <&mdss0_dp2_opp_table>; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss0_dp2_in: endpoint { + remote-endpoint = <&mdss0_intf6_out>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + + mdss0_dp2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss0_dp3: displayport-controller@aea0000 { + compatible = "qcom,sc8280xp-dp"; + reg = <0 0xaea0000 0 0x200>, + <0 0xaea0200 0 0x200>, + <0 0xaea0400 0 0x600>, + <0 0xaea1000 0 0x400>; + + clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, + <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>, + <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK>, + <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, + <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; + clock-names = "core_iface", "core_aux", + "ctrl_link", + "ctrl_link_iface", "stream_pixel"; + interrupt-parent = <&mdss0>; + interrupts = <15>; + phys = <&mdss0_dp3_phy>; + phy-names = "dp"; + power-domains = <&rpmhpd SC8280XP_MMCX>; + + assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, + <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 1>; + operating-points-v2 = <&mdss0_dp3_opp_table>; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss0_dp3_in: endpoint { + remote-endpoint = <&mdss0_intf5_out>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + + mdss0_dp3_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + }; + + mdss0_dp2_phy: phy@aec2a00 { + compatible = "qcom,sc8280xp-dp-phy"; + reg = <0 0x0aec2a00 0 0x19c>, + <0 0x0aec2200 0 0xec>, + <0 0x0aec2600 0 0xec>, + <0 0x0aec2000 0 0x1c8>; + + clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>, + <&dispcc0 DISP_CC_MDSS_AHB_CLK>; + clock-names = "aux", "cfg_ahb"; + power-domains = <&rpmhpd SC8280XP_MX>; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + mdss0_dp3_phy: phy@aec5a00 { + compatible = "qcom,sc8280xp-dp-phy"; + reg = <0 0x0aec5a00 0 0x19c>, + <0 0x0aec5200 0 0xec>, + <0 0x0aec5600 0 0xec>, + <0 0x0aec5000 0 0x1c8>; + + clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>, + <&dispcc0 DISP_CC_MDSS_AHB_CLK>; + clock-names = "aux", "cfg_ahb"; + power-domains = <&rpmhpd SC8280XP_MX>; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + dispcc0: clock-controller@af00000 { + compatible = "qcom,sc8280xp-dispcc0"; + reg = <0 0x0af00000 0 0x20000>; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>, + <&mdss0_dp2_phy 0>, + <&mdss0_dp2_phy 1>, + <&mdss0_dp3_phy 0>, + <&mdss0_dp3_phy 1>, + <0>, + <0>, + <0>, + <0>; + power-domains = <&rpmhpd SC8280XP_MMCX>; + + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + + status = "disabled"; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sc8280xp-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; @@ -2056,7 +3493,7 @@ #thermal-sensor-cells = <1>; }; - aoss_qmp: power-controller@c300000 { + aoss_qmp: power-management@c300000 { compatible = "qcom,sc8280xp-aoss-qmp", "qcom,aoss-qmp"; reg = <0 0x0c300000 0 0x400>; interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; @@ -2082,8 +3519,8 @@ interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; qcom,ee = <0>; qcom,channel = <0>; - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <0>; interrupt-controller; #interrupt-cells = <4>; }; @@ -2591,6 +4028,475 @@ qcom,remote-pid = <12>; }; }; + + mdss1: display-subsystem@22000000 { + compatible = "qcom,sc8280xp-mdss"; + reg = <0 0x22000000 0 0x1000>; + reg-names = "mdss"; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&dispcc1 DISP_CC_MDSS_AHB_CLK>, + <&dispcc1 DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", + "ahb", + "core"; + interconnects = <&mmss_noc MASTER_MDP_CORE1_0 0 &mc_virt SLAVE_EBI1 0>, + <&mmss_noc MASTER_MDP_CORE1_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + interrupts = <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>; + + iommus = <&apps_smmu 0x1800 0x402>; + power-domains = <&dispcc1 MDSS_GDSC>; + resets = <&dispcc1 DISP_CC_MDSS_CORE_BCR>; + + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + mdss1_mdp: display-controller@22001000 { + compatible = "qcom,sc8280xp-dpu"; + reg = <0 0x22001000 0 0x8f000>, + <0 0x220b0000 0 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc1 DISP_CC_MDSS_AHB_CLK>, + <&dispcc1 DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc1 DISP_CC_MDSS_MDP_CLK>, + <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + interrupt-parent = <&mdss1>; + interrupts = <0>; + power-domains = <&rpmhpd SC8280XP_MMCX>; + + assigned-clocks = <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + operating-points-v2 = <&mdss1_mdp_opp_table>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss1_intf0_out: endpoint { + remote-endpoint = <&mdss1_dp0_in>; + }; + }; + + port@4 { + reg = <4>; + mdss1_intf4_out: endpoint { + remote-endpoint = <&mdss1_dp1_in>; + }; + }; + + port@5 { + reg = <5>; + mdss1_intf5_out: endpoint { + remote-endpoint = <&mdss1_dp3_in>; + }; + }; + + port@6 { + reg = <6>; + mdss1_intf6_out: endpoint { + remote-endpoint = <&mdss1_dp2_in>; + }; + }; + }; + + mdss1_mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_turbo_l1>; + }; + }; + }; + + mdss1_dp0: displayport-controller@22090000 { + compatible = "qcom,sc8280xp-dp"; + reg = <0 0x22090000 0 0x200>, + <0 0x22090200 0 0x200>, + <0 0x22090400 0 0x600>, + <0 0x22091000 0 0x400>; + + clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + clock-names = "core_iface", "core_aux", + "ctrl_link", + "ctrl_link_iface", "stream_pixel"; + interrupt-parent = <&mdss1>; + interrupts = <12>; + phys = <&mdss1_dp0_phy>; + phy-names = "dp"; + power-domains = <&rpmhpd SC8280XP_MMCX>; + + assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>; + operating-points-v2 = <&mdss1_dp0_opp_table>; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss1_dp0_in: endpoint { + remote-endpoint = <&mdss1_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + + mdss1_dp0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + + }; + + mdss1_dp1: displayport-controller@22098000 { + compatible = "qcom,sc8280xp-dp"; + reg = <0 0x22098000 0 0x200>, + <0 0x22098200 0 0x200>, + <0 0x22098400 0 0x600>, + <0 0x22099000 0 0x400>; + + clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; + clock-names = "core_iface", "core_aux", + "ctrl_link", + "ctrl_link_iface", "stream_pixel"; + interrupt-parent = <&mdss1>; + interrupts = <13>; + phys = <&mdss1_dp1_phy>; + phy-names = "dp"; + power-domains = <&rpmhpd SC8280XP_MMCX>; + + assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, + <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>; + operating-points-v2 = <&mdss1_dp1_opp_table>; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss1_dp1_in: endpoint { + remote-endpoint = <&mdss1_intf4_out>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + + mdss1_dp1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss1_dp2: displayport-controller@2209a000 { + compatible = "qcom,sc8280xp-dp"; + reg = <0 0x2209a000 0 0x200>, + <0 0x2209a200 0 0x200>, + <0 0x2209a400 0 0x600>, + <0 0x2209b000 0 0x400>; + + clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; + clock-names = "core_iface", "core_aux", + "ctrl_link", + "ctrl_link_iface", "stream_pixel"; + interrupt-parent = <&mdss1>; + interrupts = <14>; + phys = <&mdss1_dp2_phy>; + phy-names = "dp"; + power-domains = <&rpmhpd SC8280XP_MMCX>; + + assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, + <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&mdss1_dp2_phy 0>, <&mdss1_dp2_phy 1>; + operating-points-v2 = <&mdss1_dp2_opp_table>; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss1_dp2_in: endpoint { + remote-endpoint = <&mdss1_intf6_out>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + + mdss1_dp2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss1_dp3: displayport-controller@220a0000 { + compatible = "qcom,sc8280xp-dp"; + reg = <0 0x220a0000 0 0x200>, + <0 0x220a0200 0 0x200>, + <0 0x220a0400 0 0x600>, + <0 0x220a1000 0 0x400>; + + clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; + clock-names = "core_iface", "core_aux", + "ctrl_link", + "ctrl_link_iface", "stream_pixel"; + interrupt-parent = <&mdss1>; + interrupts = <15>; + phys = <&mdss1_dp3_phy>; + phy-names = "dp"; + power-domains = <&rpmhpd SC8280XP_MMCX>; + + assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, + <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&mdss1_dp3_phy 0>, <&mdss1_dp3_phy 1>; + operating-points-v2 = <&mdss1_dp3_opp_table>; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss1_dp3_in: endpoint { + remote-endpoint = <&mdss1_intf5_out>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + + mdss1_dp3_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + }; + + mdss1_dp2_phy: phy@220c2a00 { + compatible = "qcom,sc8280xp-dp-phy"; + reg = <0 0x220c2a00 0 0x19c>, + <0 0x220c2200 0 0xec>, + <0 0x220c2600 0 0xec>, + <0 0x220c2000 0 0x1c8>; + + clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>, + <&dispcc1 DISP_CC_MDSS_AHB_CLK>; + clock-names = "aux", "cfg_ahb"; + power-domains = <&rpmhpd SC8280XP_MX>; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + mdss1_dp3_phy: phy@220c5a00 { + compatible = "qcom,sc8280xp-dp-phy"; + reg = <0 0x220c5a00 0 0x19c>, + <0 0x220c5200 0 0xec>, + <0 0x220c5600 0 0xec>, + <0 0x220c5000 0 0x1c8>; + + clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>, + <&dispcc1 DISP_CC_MDSS_AHB_CLK>; + clock-names = "aux", "cfg_ahb"; + power-domains = <&rpmhpd SC8280XP_MX>; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + dispcc1: clock-controller@22100000 { + compatible = "qcom,sc8280xp-dispcc1"; + reg = <0 0x22100000 0 0x20000>; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <0>, + <&mdss1_dp0_phy 0>, + <&mdss1_dp0_phy 1>, + <&mdss1_dp1_phy 0>, + <&mdss1_dp1_phy 1>, + <&mdss1_dp2_phy 0>, + <&mdss1_dp2_phy 1>, + <&mdss1_dp3_phy 0>, + <&mdss1_dp3_phy 1>, + <0>, + <0>, + <0>, + <0>; + power-domains = <&rpmhpd SC8280XP_MMCX>; + + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + + status = "disabled"; + }; + }; + + sound: sound { }; thermal-zones { diff --git a/arch/arm64/boot/dts/qcom/sdm450-motorola-ali.dts b/arch/arm64/boot/dts/qcom/sdm450-motorola-ali.dts new file mode 100644 index 000000000000..362be5719dd2 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm450-motorola-ali.dts @@ -0,0 +1,252 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Julian Braha <julianbraha@gmail.com> + */ +/dts-v1/; + +#include "msm8953.dtsi" +#include "pm8953.dtsi" +#include "pmi8950.dtsi" + +/delete-node/ &qseecom_mem; + +/ { + model = "Motorola Moto G6"; + compatible = "motorola,ali", "qcom,sdm450"; + chassis-type = "handset"; + qcom,msm-id = <338 0>; + qcom,board-id = <0x43 0xc200>; + + gpio-keys { + compatible = "gpio-keys"; + + key-volume-up { + label = "volume_up"; + gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + }; + }; + + reserved-memory { + qseecom_mem: qseecom@84300000 { + reg = <0x0 0x84300000 0x0 0x2000000>; + no-map; + }; + + ramoops@ef000000 { + compatible = "ramoops"; + reg = <0x0 0xef000000 0x0 0xc0000>; + console-size = <0x40000>; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-always-on; + regulator-boot-on; + }; +}; + +&hsusb_phy { + vdd-supply = <&pm8953_l3>; + vdda-pll-supply = <&pm8953_l7>; + vdda-phy-dpdm-supply = <&pm8953_l13>; + + status = "okay"; +}; + +&i2c_3 { + status = "okay"; + + touchscreen@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + interrupt-parent = <&tlmm>; + interrupts = <65 IRQ_TYPE_EDGE_FALLING>; + vcc-supply = <&pm8953_l10>; + + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + + reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>; + touchscreen-size-x = <1080>; + touchscreen-size-y = <2160>; + }; +}; + +&pm8953_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; +}; + +&pmi8950_wled { + qcom,num-strings = <3>; + qcom,external-pfet; + qcom,cabc; + + status = "okay"; +}; + +&rpm_requests { + regulators { + compatible = "qcom,rpm-pm8953-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3-supply = <&vph_pwr>; + vdd_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + vdd_s7-supply = <&vph_pwr>; + vdd_l1-supply = <&pm8953_s3>; + vdd_l2_l3-supply = <&pm8953_s3>; + vdd_l4_l5_l6_l7_l16_l19-supply = <&pm8953_s4>; + vdd_l8_l11_l12_l13_l14_l15-supply = <&vph_pwr>; + vdd_l9_l10_l17_l18_l22-supply = <&vph_pwr>; + + pm8953_s1: s1 { + regulator-min-microvolt = <795000>; + regulator-max-microvolt = <1081000>; + }; + + pm8953_s3: s3 { + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1224000>; + }; + + pm8953_s4: s4 { + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <2050000>; + }; + + pm8953_l1: l1 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + }; + + pm8953_l2: l2 { + regulator-min-microvolt = <975000>; + regulator-max-microvolt = <1225000>; + }; + + pm8953_l3: l3 { + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <925000>; + }; + + pm8953_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8953_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8953_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + }; + + pm8953_l8: l8 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + }; + + pm8953_l9: l9 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + + pm8953_l10: l10 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8953_l11: l11 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + }; + + pm8953_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8953_l13: l13 { + regulator-min-microvolt = <3125000>; + regulator-max-microvolt = <3125000>; + }; + + pm8953_l16: l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8953_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8953_l19: l19 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + }; + + pm8953_l22: l22 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2850000>; + }; + + pm8953_l23: l23 { + regulator-min-microvolt = <975000>; + regulator-max-microvolt = <1225000>; + }; + }; +}; + +&sdhc_1 { + vmmc-supply = <&pm8953_l8>; + vqmmc-supply = <&pm8953_l5>; + + status = "okay"; +}; + +&sdhc_2 { + vmmc-supply = <&pm8953_l11>; + vqmmc-supply = <&pm8953_l12>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_off>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <95 5>, <111 1>, <126 1>; + + ts_int_active: ts-int-active-state { + pins = "gpio65"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + ts_reset_active: ts-reset-active-state { + pins = "gpio64"; + function = "gpio"; + drive-strength = <0x08>; + bias-pull-up; + }; +}; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + dr_mode = "peripheral"; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-ganges-kirin.dts b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-ganges-kirin.dts index 71b448978e88..9425b2d9536e 100644 --- a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-ganges-kirin.dts +++ b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-ganges-kirin.dts @@ -21,6 +21,11 @@ }; }; +/* Reserve a bigger chunk of RAM for the higher-res display */ +&cont_splash_mem { + reg = <0 0x9d400000 0 (2520 * 1080 * 4)>; +}; + /* Ganges devices feature a Novatek touchscreen instead. */ /delete-node/ &touchscreen; /delete-node/ &vreg_l18a_1v8; diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi index 3d2b08d551d0..e52580acd5c8 100644 --- a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi @@ -57,7 +57,7 @@ regulator-boot-on; }; - cam_vdig_imx300_219_vreg: cam_vdig_imx300_219_vreg { + cam_vdig_imx300_219_vreg: cam-vdig-imx300-219-regulator { compatible = "regulator-fixed"; regulator-name = "cam_vdig_imx300_219_vreg"; startup-delay-us = <0>; @@ -67,7 +67,7 @@ pinctrl-0 = <&cam_vdig_default>; }; - cam_vana_front_vreg: cam_vana_front_vreg { + cam_vana_front_vreg: cam-vana-front-regulator { compatible = "regulator-fixed"; regulator-name = "cam_vana_front_vreg"; startup-delay-us = <0>; @@ -77,7 +77,7 @@ pinctrl-0 = <&imx219_vana_default>; }; - cam_vana_rear_vreg: cam_vana_rear_vreg { + cam_vana_rear_vreg: cam-vana-rear-regulator { compatible = "regulator-fixed"; regulator-name = "cam_vana_rear_vreg"; startup-delay-us = <0>; @@ -133,15 +133,20 @@ status = "okay"; }; - debug_region@ffb00000 { + debug@ffb00000 { reg = <0x00 0xffb00000 0x00 0x100000>; no-map; }; - removed_region@85800000 { + reserved@85800000 { reg = <0x00 0x85800000 0x00 0x3700000>; no-map; }; + + cont_splash_mem: splash@9d400000 { + reg = <0 0x9d400000 0 (1920 * 1080 * 4)>; + no-map; + }; }; /* diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 13e6a4fbba27..5827cda270a0 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -678,7 +678,7 @@ mnoc: interconnect@1745000 { compatible = "qcom,sdm660-mnoc"; - reg = <0x01745000 0xA010>; + reg = <0x01745000 0xa010>; #interconnect-cells = <1>; clock-names = "bus", "bus_a", "iface"; clocks = <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>, @@ -1044,43 +1044,43 @@ opp-hz = /bits/ 64 <775000000>; opp-level = <RPM_SMD_LEVEL_TURBO>; opp-peak-kBps = <5412000>; - opp-supported-hw = <0xA2>; + opp-supported-hw = <0xa2>; }; opp-647000000 { opp-hz = /bits/ 64 <647000000>; opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; opp-peak-kBps = <4068000>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; opp-588000000 { opp-hz = /bits/ 64 <588000000>; opp-level = <RPM_SMD_LEVEL_NOM>; opp-peak-kBps = <3072000>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; opp-465000000 { opp-hz = /bits/ 64 <465000000>; opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; opp-peak-kBps = <2724000>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; opp-370000000 { opp-hz = /bits/ 64 <370000000>; opp-level = <RPM_SMD_LEVEL_SVS>; opp-peak-kBps = <2188000>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; opp-240000000 { opp-hz = /bits/ 64 <240000000>; opp-level = <RPM_SMD_LEVEL_LOW_SVS>; opp-peak-kBps = <1648000>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; opp-160000000 { opp-hz = /bits/ 64 <160000000>; opp-level = <RPM_SMD_LEVEL_MIN_SVS>; opp-peak-kBps = <1200000>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; }; }; @@ -1470,7 +1470,7 @@ }; }; - mdss: mdss@c900000 { + mdss: display-subsystem@c900000 { compatible = "qcom,mdss"; reg = <0x0c900000 0x1000>, <0x0c9b0000 0x1040>; @@ -1497,8 +1497,8 @@ ranges; status = "disabled"; - mdp: mdp@c901000 { - compatible = "qcom,mdp5"; + mdp: display-controller@c901000 { + compatible = "qcom,sdm630-mdp5", "qcom,mdp5"; reg = <0x0c901000 0x89000>; reg-names = "mdp_phys"; @@ -1572,7 +1572,8 @@ }; dsi0: dsi@c994000 { - compatible = "qcom,mdss-dsi-ctrl"; + compatible = "qcom,sdm660-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; reg = <0x0c994000 0x400>; reg-names = "dsi_ctrl"; @@ -2409,7 +2410,7 @@ type = "passive"; }; - cpu0_crit: cpu_crit { + cpu0_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -2430,7 +2431,7 @@ type = "passive"; }; - cpu1_crit: cpu_crit { + cpu1_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -2451,7 +2452,7 @@ type = "passive"; }; - cpu2_crit: cpu_crit { + cpu2_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -2472,7 +2473,7 @@ type = "passive"; }; - cpu3_crit: cpu_crit { + cpu3_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -2499,7 +2500,7 @@ type = "passive"; }; - pwr_cluster_crit: cpu_crit { + pwr_cluster_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; diff --git a/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts b/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts index 3fb513cad0a9..70e683b7e4fc 100644 --- a/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts +++ b/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts @@ -63,6 +63,21 @@ }; }; +&i2c_5 { + status = "okay"; + + nfc@28 { + compatible = "nxp,nq310", "nxp,nxp-nci-i2c"; + reg = <0x28>; + + interrupt-parent = <&tlmm>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; + + enable-gpios = <&tlmm 16 GPIO_ACTIVE_HIGH>; + firmware-gpios = <&tlmm 62 GPIO_ACTIVE_HIGH>; + }; +}; + &pm8953_resin { status = "okay"; linux,code = <KEY_VOLUMEDOWN>; diff --git a/arch/arm64/boot/dts/qcom/sdm632-motorola-ocean.dts b/arch/arm64/boot/dts/qcom/sdm632-motorola-ocean.dts new file mode 100644 index 000000000000..c82d6e628d2c --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm632-motorola-ocean.dts @@ -0,0 +1,291 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Gabriela David + */ +/dts-v1/; + +#include "sdm632.dtsi" +#include "pm8953.dtsi" +#include <dt-bindings/leds/common.h> + +/delete-node/ &cont_splash_mem; +/delete-node/ &qseecom_mem; + +/ { + model = "Motorola G7 Power"; + compatible = "motorola,ocean", "qcom,sdm632"; + chassis-type = "handset"; + qcom,msm-id = <349 0>; + qcom,board-id = <0x141 0xc100>; + qcom,pmic-id = <0x10016 0x25 0x00 0x00>; + + backlight: backlight { + compatible = "led-backlight"; + leds = <&led>; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer@90001000 { + compatible = "simple-framebuffer"; + reg = <0 0x90001000 0 (720 * 1520 * 3)>; + + width = <720>; + height = <1520>; + stride = <(720 * 3)>; + format = "r8g8b8"; + + power-domains = <&gcc MDSS_GDSC>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_BYTE0_CLK>, + <&gcc GCC_MDSS_PCLK0_CLK>, + <&gcc GCC_MDSS_ESC0_CLK>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_key_default>; + + key-volume-up { + label = "Volume Up"; + gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + }; + }; + + reserved-memory { + qseecom_mem: qseecom@84300000 { + reg = <0x0 0x84300000 0x0 0x2000000>; + no-map; + }; + + cont_splash_mem: cont-splash@90001000 { + reg = <0x0 0x90001000 0x0 (720 * 1520 * 3)>; + no-map; + }; + + reserved@eefa1800 { + reg = <0x00 0xeefa1800 0x00 0x5e800>; + no-map; + }; + + ramoops@ef000000 { + compatible = "ramoops"; + reg = <0x0 0xef000000 0x0 0xbf800>; + console-size = <0x40000>; + pmsg-size = <0x40000>; + record-size = <0x3f800>; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-always-on; + regulator-boot-on; + }; +}; + +&hsusb_phy { + vdd-supply = <&pm8953_l3>; + vdda-pll-supply = <&pm8953_l7>; + vdda-phy-dpdm-supply = <&pm8953_l13>; + + status = "okay"; +}; + +&i2c_3 { + status = "okay"; + + touchscreen@41 { + compatible = "ilitek,ili2117"; + reg = <0x41>; + + interrupt-parent = <&tlmm>; + interrupts = <65 IRQ_TYPE_EDGE_FALLING>; + + touchscreen-inverted-x; + }; +}; + +&i2c_5 { + status = "okay"; + + led-controller@36 { + compatible = "ti,lm3697"; + reg = <0x36>; + + #address-cells = <1>; + #size-cells = <0>; + + led: led@1 { + reg = <1>; + default-trigger = "backlight"; + function = LED_FUNCTION_BACKLIGHT; + led-sources = <0 1 2>; + }; + }; +}; + +&pm8953_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; +}; + +&rpm_requests { + regulators { + compatible = "qcom,rpm-pm8953-regulators"; + + vdd_l1-supply = <&pm8953_s3>; + vdd_l2_l3-supply = <&pm8953_s3>; + vdd_l4_l5_l6_l7_l16_l19-supply = <&pm8953_s4>; + vdd_l8_l11_l12_l13_l14_l15-supply = <&vph_pwr>; + vdd_l9_l10_l17_l18_l22-supply = <&vph_pwr>; + + pm8953_s3: s3 { + regulator-min-microvolt = <984000>; + regulator-max-microvolt = <1240000>; + }; + + pm8953_s4: s4 { + regulator-min-microvolt = <1036000>; + regulator-max-microvolt = <2040000>; + }; + + pm8953_l1: l1 { + regulator-min-microvolt = <975000>; + regulator-max-microvolt = <1050000>; + }; + + pm8953_l2: l2 { + regulator-min-microvolt = <975000>; + regulator-max-microvolt = <1175000>; + }; + + pm8953_l3: l3 { + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <925000>; + regulator-allow-set-load; + }; + + pm8953_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8953_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8953_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + }; + + pm8953_l8: l8 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + }; + + pm8953_l9: l9 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + + pm8953_l10: l10 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3000000>; + }; + + pm8953_l11: l11 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + }; + + pm8953_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8953_l13: l13 { + regulator-min-microvolt = <3125000>; + regulator-max-microvolt = <3125000>; + }; + + pm8953_l16: l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8953_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8953_l18: l18 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2700000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8953_l19: l19 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + }; + + pm8953_l22: l22 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + pm8953_l23: l23 { + regulator-min-microvolt = <975000>; + regulator-max-microvolt = <1225000>; + }; + }; +}; + +&sdhc_1 { + vmmc-supply = <&pm8953_l8>; + vqmmc-supply = <&pm8953_l5>; + + status = "okay"; +}; + +&sdhc_2 { + vmmc-supply = <&pm8953_l11>; + vqmmc-supply = <&pm8953_l12>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <96 4>; +}; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + dr_mode = "peripheral"; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm660.dtsi b/arch/arm64/boot/dts/qcom/sdm660.dtsi index d52123cb5cd3..f0f27fc12c18 100644 --- a/arch/arm64/boot/dts/qcom/sdm660.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm660.dtsi @@ -37,35 +37,35 @@ opp-hz = /bits/ 64 <700000000>; opp-level = <RPM_SMD_LEVEL_TURBO>; opp-peak-kBps = <5184000>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; opp-647000000 { opp-hz = /bits/ 64 <647000000>; opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; opp-peak-kBps = <4068000>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; opp-588000000 { opp-hz = /bits/ 64 <588000000>; opp-level = <RPM_SMD_LEVEL_NOM>; opp-peak-kBps = <3072000>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; opp-465000000 { opp-hz = /bits/ 64 <465000000>; opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; opp-peak-kBps = <2724000>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; opp-370000000 { opp-hz = /bits/ 64 <370000000>; opp-level = <RPM_SMD_LEVEL_SVS>; opp-peak-kBps = <2188000>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; */ @@ -73,14 +73,14 @@ opp-hz = /bits/ 64 <266000000>; opp-level = <RPM_SMD_LEVEL_LOW_SVS>; opp-peak-kBps = <1648000>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; opp-160000000 { opp-hz = /bits/ 64 <160000000>; opp-level = <RPM_SMD_LEVEL_MIN_SVS>; opp-peak-kBps = <1200000>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; }; }; @@ -142,6 +142,8 @@ }; &mdp { + compatible = "qcom,sdm660-mdp5", "qcom,mdp5"; + ports { port@1 { reg = <1>; @@ -154,7 +156,8 @@ &mdss { dsi1: dsi@c996000 { - compatible = "qcom,mdss-dsi-ctrl"; + compatible = "qcom,sdm660-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; reg = <0x0c996000 0x400>; reg-names = "dsi_ctrl"; diff --git a/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts index cf2ae540db12..e3e61b9d1b9d 100644 --- a/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts +++ b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts @@ -256,6 +256,7 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-enable-ramp-delay = <250>; + regulator-always-on; }; vreg_l9a_1p8: ldo9 { diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index 47363fde64ac..ec9946e5f08d 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -401,6 +401,18 @@ #power-domain-cells = <1>; }; + qfprom: qfprom@784000 { + compatible = "qcom,sdm670-qfprom", "qcom,qfprom"; + reg = <0 0x00784000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + qusb2_hstx_trim: hstx-trim@1eb { + reg = <0x1eb 0x1>; + bits = <1 4>; + }; + }; + sdhc_1: mmc@7c4000 { compatible = "qcom,sdm670-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x007c4000 0 0x1000>, @@ -928,6 +940,8 @@ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + nvmem-cells = <&qusb2_hstx_trim>; + status = "disabled"; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi index ca676e04687b..a78075155310 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi @@ -756,8 +756,8 @@ ap_ts_i2c: &i2c14 { }; &ipa { + qcom,gsi-loader = "modem"; status = "okay"; - modem-init; }; &lpasscc { @@ -995,108 +995,73 @@ ap_ts_i2c: &i2c14 { /* PINCTRL - additions to nodes defined in sdm845.dtsi */ &qspi_cs0 { - pinconf { - pins = "gpio90"; - bias-disable; - }; + bias-disable; }; &qspi_clk { - pinconf { - pins = "gpio95"; - bias-disable; - }; + bias-disable; }; &qspi_data01 { - pinconf { - pins = "gpio91", "gpio92"; - - /* High-Z when no transfers; nice to park the lines */ - bias-pull-up; - }; + /* High-Z when no transfers; nice to park the lines */ + bias-pull-up; }; &qup_i2c3_default { - pinconf { - pins = "gpio41", "gpio42"; - drive-strength = <2>; + drive-strength = <2>; - /* Has external pullup */ - bias-disable; - }; + /* Has external pullup */ + bias-disable; }; &qup_i2c11_default { - pinconf { - pins = "gpio31", "gpio32"; - drive-strength = <2>; + drive-strength = <2>; - /* Has external pullup */ - bias-disable; - }; + /* Has external pullup */ + bias-disable; }; &qup_i2c12_default { - pinconf { - pins = "gpio49", "gpio50"; - drive-strength = <2>; + drive-strength = <2>; - /* Has external pullup */ - bias-disable; - }; + /* Has external pullup */ + bias-disable; }; &qup_i2c14_default { - pinconf { - pins = "gpio33", "gpio34"; - drive-strength = <2>; + drive-strength = <2>; - /* Has external pullup */ - bias-disable; - }; + /* Has external pullup */ + bias-disable; }; &qup_spi0_default { - pinconf { - pins = "gpio0", "gpio1", "gpio2", "gpio3"; - drive-strength = <2>; - bias-disable; - }; + drive-strength = <2>; + bias-disable; }; &qup_spi5_default { - pinconf { - pins = "gpio85", "gpio86", "gpio87", "gpio88"; - drive-strength = <2>; - bias-disable; - }; + drive-strength = <2>; + bias-disable; }; &qup_spi10_default { - pinconf { - pins = "gpio53", "gpio54", "gpio55", "gpio56"; - drive-strength = <2>; - bias-disable; - }; + drive-strength = <2>; + bias-disable; }; -&qup_uart9_default { - pinconf-tx { - pins = "gpio4"; - drive-strength = <2>; - bias-disable; - }; +&qup_uart9_rx { + drive-strength = <2>; + bias-pull-up; +}; - pinconf-rx { - pins = "gpio5"; - drive-strength = <2>; - bias-pull-up; - }; +&qup_uart9_tx { + drive-strength = <2>; + bias-disable; }; /* PINCTRL - board-specific pinctrl */ -&pm8005_gpio { +&pm8005_gpios { gpio-line-names = "", "", "SLB", @@ -1130,7 +1095,7 @@ ap_ts_i2c: &i2c14 { }; }; -&pm8998_gpio { +&pm8998_gpios { gpio-line-names = "", "", "SW_CTRL", @@ -1180,243 +1145,153 @@ ap_ts_i2c: &i2c14 { output-low; }; - ap_edp_bklten: ap-edp-bklten { - pinmux { - pins = "gpio37"; - function = "gpio"; - }; - - pinconf { - pins = "gpio37"; - drive-strength = <2>; - bias-disable; - }; + ap_edp_bklten: ap-edp-bklten-state { + pins = "gpio37"; + function = "gpio"; + drive-strength = <2>; + bias-disable; }; - bios_flash_wp_r_l: bios-flash-wp-r-l { - pinmux { - pins = "gpio128"; - function = "gpio"; - input-enable; - }; - - pinconf { - pins = "gpio128"; - bias-disable; - }; + bios_flash_wp_r_l: bios-flash-wp-r-l-state { + pins = "gpio128"; + function = "gpio"; + input-enable; + bias-disable; }; - ec_ap_int_l: ec-ap-int-l { - pinmux { - pins = "gpio122"; - function = "gpio"; - input-enable; - }; - - pinconf { - pins = "gpio122"; - bias-pull-up; - }; + ec_ap_int_l: ec-ap-int-l-state { + pins = "gpio122"; + function = "gpio"; + input-enable; + bias-pull-up; }; - edp_brij_en: edp-brij-en { - pinmux { - pins = "gpio102"; - function = "gpio"; - }; - - pinconf { - pins = "gpio102"; - drive-strength = <2>; - bias-disable; - }; + edp_brij_en: edp-brij-en-state { + pins = "gpio102"; + function = "gpio"; + drive-strength = <2>; + bias-disable; }; - edp_brij_irq: edp-brij-irq { - pinmux { - pins = "gpio10"; - function = "gpio"; - }; - - pinconf { - pins = "gpio10"; - drive-strength = <2>; - bias-pull-down; - }; + edp_brij_irq: edp-brij-irq-state { + pins = "gpio10"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; }; - en_pp3300_dx_edp: en-pp3300-dx-edp { - pinmux { - pins = "gpio43"; - function = "gpio"; - }; - - pinconf { - pins = "gpio43"; - drive-strength = <2>; - bias-disable; - }; + en_pp3300_dx_edp: en-pp3300-dx-edp-state { + pins = "gpio43"; + function = "gpio"; + drive-strength = <2>; + bias-disable; }; - h1_ap_int_odl: h1-ap-int-odl { - pinmux { - pins = "gpio129"; - function = "gpio"; - input-enable; - }; - - pinconf { - pins = "gpio129"; - bias-pull-up; - }; + h1_ap_int_odl: h1-ap-int-odl-state { + pins = "gpio129"; + function = "gpio"; + input-enable; + bias-pull-up; }; - pen_eject_odl: pen-eject-odl { - pinmux { - pins = "gpio119"; - function = "gpio"; - bias-pull-up; - }; + pen_eject_odl: pen-eject-odl-state { + pins = "gpio119"; + function = "gpio"; + bias-pull-up; }; - pen_irq_l: pen-irq-l { - pinmux { - pins = "gpio24"; - function = "gpio"; - }; + pen_irq_l: pen-irq-l-state { + pins = "gpio24"; + function = "gpio"; - pinconf { - pins = "gpio24"; - - /* Has external pullup */ - bias-disable; - }; + /* Has external pullup */ + bias-disable; }; - pen_pdct_l: pen-pdct-l { - pinmux { - pins = "gpio63"; - function = "gpio"; - }; - - pinconf { - pins = "gpio63"; + pen_pdct_l: pen-pdct-l-state { + pins = "gpio63"; + function = "gpio"; - /* Has external pullup */ - bias-disable; - }; + /* Has external pullup */ + bias-disable; }; - pen_rst_l: pen-rst-l { - pinmux { - pins = "gpio23"; - function = "gpio"; - }; - - pinconf { - pins = "gpio23"; - bias-disable; - drive-strength = <2>; + pen_rst_l: pen-rst-l-state { + pins = "gpio23"; + function = "gpio"; + bias-disable; + drive-strength = <2>; - /* - * The pen driver doesn't currently support - * driving this reset line. By specifying - * output-high here we're relying on the fact - * that this pin has a default pulldown at boot - * (which makes sure the pen was in reset if it - * was powered) and then we set it high here to - * take it out of reset. Better would be if the - * pen driver could control this and we could - * remove "output-high" here. - */ - output-high; - }; + /* + * The pen driver doesn't currently support + * driving this reset line. By specifying + * output-high here we're relying on the fact + * that this pin has a default pulldown at boot + * (which makes sure the pen was in reset if it + * was powered) and then we set it high here to + * take it out of reset. Better would be if the + * pen driver could control this and we could + * remove "output-high" here. + */ + output-high; }; - sdc2_clk: sdc2-clk { - pinconf { - pins = "sdc2_clk"; - bias-disable; + sdc2_clk: sdc2-clk-state { + pins = "sdc2_clk"; + bias-disable; - /* - * It seems that mmc_test reports errors if drive - * strength is not 16. - */ - drive-strength = <16>; - }; + /* + * It seems that mmc_test reports errors if drive + * strength is not 16. + */ + drive-strength = <16>; }; - sdc2_cmd: sdc2-cmd { - pinconf { - pins = "sdc2_cmd"; - bias-pull-up; - drive-strength = <16>; - }; + sdc2_cmd: sdc2-cmd-state { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <16>; }; - sdc2_data: sdc2-data { - pinconf { - pins = "sdc2_data"; - bias-pull-up; - drive-strength = <16>; - }; + sdc2_data: sdc2-data-state { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <16>; }; - sd_cd_odl: sd-cd-odl { - pinmux { - pins = "gpio44"; - function = "gpio"; - }; - - pinconf { - pins = "gpio44"; - bias-pull-up; - }; + sd_cd_odl: sd-cd-odl-state { + pins = "gpio44"; + function = "gpio"; + bias-pull-up; }; - ts_int_l: ts-int-l { - pinmux { - pins = "gpio125"; - function = "gpio"; - }; - - pinconf { - pins = "gpio125"; - bias-pull-up; - }; + ts_int_l: ts-int-l-state { + pins = "gpio125"; + function = "gpio"; + bias-pull-up; }; - ts_reset_l: ts-reset-l { - pinmux { - pins = "gpio118"; - function = "gpio"; - }; - - pinconf { - pins = "gpio118"; - bias-disable; - drive-strength = <2>; - }; + ts_reset_l: ts-reset-l-state { + pins = "gpio118"; + function = "gpio"; + bias-disable; + drive-strength = <2>; }; - ap_suspend_l_assert: ap_suspend_l_assert { - config { - pins = "gpio126"; - function = "gpio"; - bias-disable; - drive-strength = <2>; - output-low; - }; + ap_suspend_l_assert: ap-suspend-l-assert-state { + pins = "gpio126"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + output-low; }; - ap_suspend_l_deassert: ap_suspend_l_deassert { - config { - pins = "gpio126"; - function = "gpio"; - bias-disable; - drive-strength = <2>; - output-high; - }; + ap_suspend_l_deassert: ap-suspend-l-deassert-state { + pins = "gpio126"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + output-high; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index f41c6d600ea8..6b355589edb3 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -54,7 +54,7 @@ key-vol-up { label = "Volume Up"; linux,code = <KEY_VOLUMEUP>; - gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; + gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>; }; }; @@ -65,7 +65,7 @@ label = "green:user4"; function = LED_FUNCTION_INDICATOR; color = <LED_COLOR_ID_GREEN>; - gpios = <&pm8998_gpio 13 GPIO_ACTIVE_HIGH>; + gpios = <&pm8998_gpios 13 GPIO_ACTIVE_HIGH>; linux,default-trigger = "panic-indicator"; default-state = "off"; }; @@ -74,7 +74,7 @@ label = "yellow:wlan"; function = LED_FUNCTION_WLAN; color = <LED_COLOR_ID_YELLOW>; - gpios = <&pm8998_gpio 9 GPIO_ACTIVE_HIGH>; + gpios = <&pm8998_gpios 9 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0tx"; default-state = "off"; }; @@ -83,7 +83,7 @@ label = "blue:bt"; function = LED_FUNCTION_BLUETOOTH; color = <LED_COLOR_ID_BLUE>; - gpios = <&pm8998_gpio 5 GPIO_ACTIVE_HIGH>; + gpios = <&pm8998_gpios 5 GPIO_ACTIVE_HIGH>; linux,default-trigger = "bluetooth-power"; default-state = "off"; }; @@ -142,32 +142,32 @@ */ }; - cam0_dvdd_1v2: reg_cam0_dvdd_1v2 { + cam0_dvdd_1v2: cam0-dvdd-1v2-regulator { compatible = "regulator-fixed"; regulator-name = "CAM0_DVDD_1V2"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; enable-active-high; - gpio = <&pm8998_gpio 12 GPIO_ACTIVE_HIGH>; + gpio = <&pm8998_gpios 12 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&cam0_dvdd_1v2_en_default>; vin-supply = <&vbat>; }; - cam0_avdd_2v8: reg_cam0_avdd_2v8 { + cam0_avdd_2v8: cam0-avdd-2v8-regulator { compatible = "regulator-fixed"; regulator-name = "CAM0_AVDD_2V8"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; enable-active-high; - gpio = <&pm8998_gpio 10 GPIO_ACTIVE_HIGH>; + gpio = <&pm8998_gpios 10 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&cam0_avdd_2v8_en_default>; vin-supply = <&vbat>; }; /* This regulator is enabled when the VREG_LVS1A_1P8 trace is enabled */ - cam3_avdd_2v8: reg_cam3_avdd_2v8 { + cam3_avdd_2v8: cam3-avdd-2v8-regulator { compatible = "regulator-fixed"; regulator-name = "CAM3_AVDD_2V8"; regulator-min-microvolt = <2800000>; @@ -506,14 +506,12 @@ &i2c11 { /* On Low speed expansion */ clock-frequency = <100000>; - label = "LS-I2C1"; status = "okay"; }; &i2c14 { /* On Low speed expansion */ clock-frequency = <100000>; - label = "LS-I2C0"; status = "okay"; }; @@ -559,7 +557,7 @@ vdda-pll-supply = <&vreg_l26a_1p2>; }; -&pm8998_gpio { +&pm8998_gpios { gpio-line-names = "NC", "NC", @@ -615,14 +613,9 @@ }; }; -&pm8998_pon { - resin { - compatible = "qcom,pm8941-resin"; - interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = <KEY_VOLUMEDOWN>; - }; +&pm8998_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; }; &pmi8998_lpg { @@ -830,8 +823,8 @@ }; &tlmm { - cam0_default: cam0_default { - rst { + cam0_default: cam0-default-state { + rst-pins { pins = "gpio9"; function = "gpio"; @@ -839,7 +832,7 @@ bias-disable; }; - mclk0 { + mclk0-pins { pins = "gpio13"; function = "cam_mclk"; @@ -848,8 +841,8 @@ }; }; - cam3_default: cam3_default { - rst { + cam3_default: cam3-default-state { + rst-pins { function = "gpio"; pins = "gpio21"; @@ -857,7 +850,7 @@ bias-disable; }; - mclk3 { + mclk3-pins { function = "cam_mclk"; pins = "gpio16"; @@ -866,7 +859,7 @@ }; }; - dsi_sw_sel: dsi-sw-sel { + dsi_sw_sel: dsi-sw-sel-state { pins = "gpio120"; function = "gpio"; @@ -875,20 +868,20 @@ output-high; }; - lt9611_irq_pin: lt9611-irq { + lt9611_irq_pin: lt9611-irq-state { pins = "gpio84"; function = "gpio"; bias-disable; }; - pcie0_default_state: pcie0-default { - clkreq { + pcie0_default_state: pcie0-default-state { + clkreq-pins { pins = "gpio36"; function = "pci_e0"; bias-pull-up; }; - reset-n { + reset-n-pins { pins = "gpio35"; function = "gpio"; @@ -897,7 +890,7 @@ bias-pull-down; }; - wake-n { + wake-n-pins { pins = "gpio37"; function = "gpio"; @@ -906,7 +899,7 @@ }; }; - pcie0_pwren_state: pcie0-pwren { + pcie0_pwren_state: pcie0-pwren-state { pins = "gpio90"; function = "gpio"; @@ -914,8 +907,8 @@ bias-disable; }; - pcie1_default_state: pcie1-default { - perst-n { + pcie1_default_state: pcie1-default-state { + perst-n-pins { pins = "gpio102"; function = "gpio"; @@ -923,13 +916,13 @@ bias-disable; }; - clkreq { + clkreq-pins { pins = "gpio103"; function = "pci_e1"; bias-pull-up; }; - wake-n { + wake-n-pins { pins = "gpio11"; function = "gpio"; @@ -937,7 +930,7 @@ bias-pull-up; }; - reset-n { + reset-n-pins { pins = "gpio75"; function = "gpio"; @@ -947,8 +940,8 @@ }; }; - sdc2_default_state: sdc2-default { - clk { + sdc2_default_state: sdc2-default-state { + clk-pins { pins = "sdc2_clk"; bias-disable; @@ -959,27 +952,27 @@ drive-strength = <16>; }; - cmd { + cmd-pins { pins = "sdc2_cmd"; bias-pull-up; drive-strength = <10>; }; - data { + data-pins { pins = "sdc2_data"; bias-pull-up; drive-strength = <10>; }; }; - sdc2_card_det_n: sd-card-det-n { + sdc2_card_det_n: sd-card-det-n-state { pins = "gpio126"; function = "gpio"; bias-pull-up; }; - wcd_intr_default: wcd_intr_default { - pins = <54>; + wcd_intr_default: wcd-intr-default-state { + pins = "gpio54"; function = "gpio"; input-enable; @@ -990,6 +983,8 @@ &uart3 { label = "LS-UART0"; + pinctrl-0 = <&qup_uart3_4pin>; + status = "disabled"; }; @@ -1135,49 +1130,30 @@ /* PINCTRL - additions to nodes defined in sdm845.dtsi */ &qup_spi2_default { - pinconf { - pins = "gpio27", "gpio28", "gpio29", "gpio30"; - drive-strength = <16>; - }; -}; - -&qup_uart3_default { - pinmux { - pins = "gpio41", "gpio42", "gpio43", "gpio44"; - function = "qup3"; - }; + drive-strength = <16>; }; &qup_i2c10_default { - pinconf { - pins = "gpio55", "gpio56"; - drive-strength = <2>; - bias-disable; - }; + drive-strength = <2>; + bias-disable; }; -&qup_uart9_default { - pinconf-tx { - pins = "gpio4"; - drive-strength = <2>; - bias-disable; - }; +&qup_uart9_rx { + drive-strength = <2>; + bias-pull-up; +}; - pinconf-rx { - pins = "gpio5"; - drive-strength = <2>; - bias-pull-up; - }; +&qup_uart9_tx { + drive-strength = <2>; + bias-disable; }; -&pm8998_gpio { +&pm8998_gpios { }; /* PINCTRL - additions to nodes defined in sdm845.dtsi */ &qup_spi0_default { - config { - drive-strength = <6>; - bias-disable; - }; + drive-strength = <6>; + bias-disable; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi index 1eb423e4be24..36f291d4d691 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi @@ -132,7 +132,7 @@ key-vol-up { label = "Volume up"; linux,code = <KEY_VOLUMEUP>; - gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; + gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>; }; }; @@ -474,22 +474,17 @@ }; &ipa { + qcom,gsi-loader = "modem"; status = "okay"; - modem-init; }; &mss_pil { status = "okay"; }; -&pm8998_pon { - resin { - compatible = "qcom,pm8941-resin"; - interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = <KEY_VOLUMEDOWN>; - }; +&pm8998_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; }; &sdhc_2 { @@ -558,52 +553,40 @@ &tlmm { gpio-reserved-ranges = <28 4>, <81 4>; - sdc2_clk: sdc2-clk { - pinconf { - pins = "sdc2_clk"; - bias-disable; - - /* - * It seems that mmc_test reports errors if drive - * strength is not 16 on clk, cmd, and data pins. - * - * TODO: copy-pasted from mtp, try other values - * on these devices. - */ - drive-strength = <16>; - }; + sdc2_clk: sdc2-clk-state { + pins = "sdc2_clk"; + bias-disable; + + /* + * It seems that mmc_test reports errors if drive + * strength is not 16 on clk, cmd, and data pins. + * + * TODO: copy-pasted from mtp, try other values + * on these devices. + */ + drive-strength = <16>; }; - sdc2_cmd: sdc2-cmd { - pinconf { - pins = "sdc2_cmd"; - bias-pull-up; - drive-strength = <16>; - }; + sdc2_cmd: sdc2-cmd-state { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <16>; }; - sdc2_data: sdc2-data { - pinconf { - pins = "sdc2_data"; - bias-pull-up; - drive-strength = <16>; - }; + sdc2_data: sdc2-data-state { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <16>; }; - sd_card_det_n: sd-card-det-n { - pinmux { - pins = "gpio126"; - function = "gpio"; - }; - - pinconf { - pins = "gpio126"; - bias-pull-up; - }; + sd_card_det_n: sd-card-det-n-state { + pins = "gpio126"; + function = "gpio"; + bias-pull-up; }; }; -&pm8998_gpio { +&pm8998_gpios { vol_up_pin_a: vol-up-active-state { pins = "gpio6"; function = "normal"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dts b/arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dts index 7d967a104b3e..a12723310c8b 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dts @@ -58,7 +58,7 @@ }; &tlmm { - thinq_key_default: thinq-key-default { + thinq_key_default: thinq-key-default-state { pins = "gpio89"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts index de2d10e0315a..482f43fe0151 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts @@ -518,8 +518,9 @@ }; &ipa { - status = "okay"; + qcom,gsi-loader = "self"; memory-region = <&ipa_fw_mem>; + status = "okay"; }; &mdss { @@ -719,68 +720,49 @@ /* PINCTRL - additions to nodes defined in sdm845.dtsi */ &qup_i2c10_default { - pinconf { - pins = "gpio55", "gpio56"; - drive-strength = <2>; - bias-disable; - }; + drive-strength = <2>; + bias-disable; }; -&qup_uart9_default { - pinconf-tx { - pins = "gpio4"; - drive-strength = <2>; - bias-disable; - }; +&qup_uart9_rx { + drive-strength = <2>; + bias-pull-up; +}; - pinconf-rx { - pins = "gpio5"; - drive-strength = <2>; - bias-pull-up; - }; +&qup_uart9_tx { + drive-strength = <2>; + bias-disable; }; &tlmm { gpio-reserved-ranges = <0 4>, <81 4>; - sdc2_clk: sdc2-clk { - pinconf { - pins = "sdc2_clk"; - bias-disable; + sdc2_clk: sdc2-clk-state { + pins = "sdc2_clk"; + bias-disable; - /* - * It seems that mmc_test reports errors if drive - * strength is not 16 on clk, cmd, and data pins. - */ - drive-strength = <16>; - }; + /* + * It seems that mmc_test reports errors if drive + * strength is not 16 on clk, cmd, and data pins. + */ + drive-strength = <16>; }; - sdc2_cmd: sdc2-cmd { - pinconf { - pins = "sdc2_cmd"; - bias-pull-up; - drive-strength = <16>; - }; + sdc2_cmd: sdc2-cmd-state { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <16>; }; - sdc2_data: sdc2-data { - pinconf { - pins = "sdc2_data"; - bias-pull-up; - drive-strength = <16>; - }; + sdc2_data: sdc2-data-state { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <16>; }; - sd_card_det_n: sd-card-det-n { - pinmux { - pins = "gpio126"; - function = "gpio"; - }; - - pinconf { - pins = "gpio126"; - bias-pull-up; - }; + sd_card_det_n: sd-card-det-n-state { + pins = "gpio126"; + function = "gpio"; + bias-pull-up; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index 42cf4dd5ea28..548e34632de2 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -37,14 +37,14 @@ key-vol-down { label = "Volume down"; linux,code = <KEY_VOLUMEDOWN>; - gpios = <&pm8998_gpio 5 GPIO_ACTIVE_LOW>; + gpios = <&pm8998_gpios 5 GPIO_ACTIVE_LOW>; debounce-interval = <15>; }; key-vol-up { label = "Volume up"; linux,code = <KEY_VOLUMEUP>; - gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; + gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>; debounce-interval = <15>; }; }; @@ -424,10 +424,10 @@ }; &ipa { - status = "okay"; - + qcom,gsi-loader = "self"; memory-region = <&ipa_fw_mem>; firmware-name = "qcom/sdm845/oneplus6/ipa_fws.mbn"; + status = "okay"; }; &mdss { @@ -440,7 +440,7 @@ firmware-name = "qcom/sdm845/oneplus6/mba.mbn", "qcom/sdm845/oneplus6/modem.mbn"; }; -&pm8998_gpio { +&pm8998_gpios { volume_down_gpio: pm8998-gpio5-state { pinconf { pins = "gpio5"; @@ -474,35 +474,24 @@ status = "okay"; }; -&qup_i2c12_default { - mux { - pins = "gpio49", "gpio50"; - function = "qup12"; - drive-strength = <2>; - bias-disable; - }; +&qup_i2c10_default { + drive-strength = <2>; + bias-disable; }; -&qup_i2c10_default { - pinconf { - pins = "gpio55", "gpio56"; - drive-strength = <2>; - bias-disable; - }; +&qup_i2c12_default { + drive-strength = <2>; + bias-disable; }; -&qup_uart9_default { - pinconf-tx { - pins = "gpio4"; - drive-strength = <2>; - bias-disable; - }; +&qup_uart9_rx { + drive-strength = <2>; + bias-pull-up; +}; - pinconf-rx { - pins = "gpio5"; - drive-strength = <2>; - bias-pull-up; - }; +&qup_uart9_tx { + drive-strength = <2>; + bias-disable; }; &uart6 { @@ -588,51 +577,41 @@ &tlmm { gpio-reserved-ranges = <0 4>, <81 4>; - tri_state_key_default: tri_state_key_default { - mux { - pins = "gpio40", "gpio42", "gpio26"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; + tri_state_key_default: tri-state-key-default-state { + pins = "gpio40", "gpio42", "gpio26"; + function = "gpio"; + drive-strength = <2>; + bias-disable; }; - ts_default_pins: ts-int { - mux { - pins = "gpio99", "gpio125"; - function = "gpio"; - drive-strength = <16>; - bias-pull-up; - }; + ts_default_pins: ts-int-state { + pins = "gpio99", "gpio125"; + function = "gpio"; + drive-strength = <16>; + bias-pull-up; }; - panel_reset_pins: panel-reset { - mux { - pins = "gpio6", "gpio25", "gpio26"; - function = "gpio"; - drive-strength = <8>; - bias-disable; - }; + panel_reset_pins: panel-reset-state { + pins = "gpio6", "gpio25", "gpio26"; + function = "gpio"; + drive-strength = <8>; + bias-disable; }; - panel_te_pin: panel-te { - mux { - pins = "gpio10"; - function = "mdp_vsync"; - drive-strength = <2>; - bias-disable; - input-enable; - }; + panel_te_pin: panel-te-state { + pins = "gpio10"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-disable; + input-enable; }; - panel_esd_pin: panel-esd { - mux { - pins = "gpio30"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - input-enable; - }; + panel_esd_pin: panel-esd-state { + pins = "gpio30"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + input-enable; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts index bb77ccfdc68c..5d0509f61fe8 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts @@ -54,7 +54,7 @@ key-vol-up { label = "volume_up"; linux,code = <KEY_VOLUMEUP>; - gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; + gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>; debounce-interval = <15>; }; }; @@ -495,10 +495,10 @@ }; &ipa { - status = "okay"; - + qcom,gsi-loader = "self"; memory-region = <&ipa_fw_mem>; firmware-name = "qcom/sdm845/axolotl/ipa_fws.mbn"; + status = "okay"; }; &mdss { @@ -510,7 +510,7 @@ firmware-name = "qcom/sdm845/axolotl/mba.mbn", "qcom/sdm845/axolotl/modem.mbn"; }; -&pm8998_gpio { +&pm8998_gpios { volume_up_gpio: pm8998-gpio6-state { pinconf { pins = "gpio6"; @@ -522,14 +522,9 @@ }; }; -&pm8998_pon { - volume_down_resin: resin { - compatible = "qcom,pm8941-resin"; - interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = <KEY_VOLUMEDOWN>; - }; +&pm8998_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; }; &pmi8998_lpg { @@ -559,18 +554,14 @@ }; }; -&qup_uart9_default { - pinconf-rx { - pins = "gpio5"; - drive-strength = <2>; - bias-pull-up; - }; +&qup_uart9_rx { + drive-strength = <2>; + bias-pull-up; +}; - pinconf-tx { - pins = "gpio4"; - drive-strength = <2>; - bias-disable; - }; +&qup_uart9_tx { + drive-strength = <2>; + bias-disable; }; &qupv3_id_0 { @@ -584,110 +575,62 @@ &tlmm { gpio-reserved-ranges = <0 4>, <81 4>; - sde_dsi_active: sde-dsi-active { - mux { - pins = "gpio6", "gpio11"; - function = "gpio"; - }; - - config { - pins = "gpio6", "gpio11"; - drive-strength = <8>; - bias-disable; - }; + sde_dsi_active: sde-dsi-active-state { + pins = "gpio6", "gpio11"; + function = "gpio"; + drive-strength = <8>; + bias-disable; }; - sde_dsi_suspend: sde-dsi-suspend { - mux { - pins = "gpio6", "gpio11"; - function = "gpio"; - }; - - config { - pins = "gpio6", "gpio11"; - drive-strength = <2>; - bias-pull-down; - }; + sde_dsi_suspend: sde-dsi-suspend-state { + pins = "gpio6", "gpio11"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; }; - sde_te_active: sde-te-active { - mux { - pins = "gpio10"; - function = "mdp_vsync"; - }; - - config { - pins = "gpio10"; - drive-strength = <2>; - bias-pull-down; - }; + sde_te_active: sde-te-active-state { + pins = "gpio10"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; }; - sde_te_suspend: sde-te-suspend { - mux { - pins = "gpio10"; - function = "mdp_vsync"; - }; - - config { - pins = "gpio10"; - drive-strength = <2>; - bias-pull-down; - }; + sde_te_suspend: sde-te-suspend-state { + pins = "gpio10"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; }; - ts_int_active: ts-int-active { - mux { - pins = "gpio125"; - function = "gpio"; - }; - - config { - pins = "gpio125"; - drive-strength = <8>; - bias-pull-up; - input-enable; - }; + ts_int_active: ts-int-active-state { + pins = "gpio125"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + input-enable; }; - ts_int_suspend: ts-int-suspend { - mux { - pins = "gpio125"; - function = "gpio"; - }; - - config { - pins = "gpio125"; - drive-strength = <2>; - bias-pull-down; - input-enable; - }; + ts_int_suspend: ts-int-suspend-state { + pins = "gpio125"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + input-enable; }; - ts_reset_active: ts-reset-active { - mux { - pins = "gpio99"; - function = "gpio"; - }; - - config { - pins = "gpio99"; - drive-strength = <8>; - bias-pull-up; - }; + ts_reset_active: ts-reset-active-state { + pins = "gpio99"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; }; - ts_reset_suspend: ts-reset-suspend { - mux { - pins = "gpio99"; - function = "gpio"; - }; - - config { - pins = "gpio99"; - drive-strength = <2>; - bias-pull-down; - }; + ts_reset_suspend: ts-reset-suspend-state { + pins = "gpio99"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi index 87dd0fc36747..85ff0a0789ea 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi @@ -4,6 +4,7 @@ */ #include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> #include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include "sdm845.dtsi" #include "pm8005.dtsi" @@ -17,14 +18,43 @@ gpio-keys { compatible = "gpio-keys"; - /* Neither Camera Focus, nor Camera Shutter seem to work... */ + pinctrl-0 = <&focus_n &snapshot_n &vol_down_n &vol_up_n>; + pinctrl-names = "default"; - key-vol-down { - label = "volume_down"; - gpios = <&pm8998_gpio 5 GPIO_ACTIVE_LOW>; + key-camera-focus { + label = "Camera Focus"; + gpios = <&pm8998_gpios 2 GPIO_ACTIVE_LOW>; + linux,code = <KEY_CAMERA_FOCUS>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + + key-camera-snapshot { + label = "Camera Snapshot"; + gpios = <&pm8998_gpios 7 GPIO_ACTIVE_LOW>; + linux,code = <KEY_CAMERA>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&pm8998_gpios 5 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEDOWN>; debounce-interval = <15>; - gpio-key,wakeup; + linux,can-disable; + wakeup-source; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; }; }; @@ -358,6 +388,40 @@ /* AMS TCS3490 RGB+IR color sensor @ 72 */ }; +&pm8998_gpios { + focus_n: focus-n-state { + pins = "gpio2"; + function = PMIC_GPIO_FUNC_NORMAL; + power-source = <0>; + bias-pull-up; + input-enable; + }; + + vol_down_n: vol-down-n-state { + pins = "gpio5"; + function = PMIC_GPIO_FUNC_NORMAL; + power-source = <0>; + bias-pull-up; + input-enable; + }; + + vol_up_n: vol-up-n-state { + pins = "gpio6"; + function = PMIC_GPIO_FUNC_NORMAL; + power-source = <0>; + bias-pull-up; + input-enable; + }; + + snapshot_n: snapshot-n-state { + pins = "gpio7"; + function = PMIC_GPIO_FUNC_NORMAL; + power-source = <0>; + bias-pull-up; + input-enable; + }; +}; + &qupv3_id_0 { status = "okay"; }; @@ -383,19 +447,19 @@ gpio-reserved-ranges = <0 4>, <81 4>; sdc2_default_state: sdc2-default-state { - clk { + clk-pins { pins = "sdc2_clk"; drive-strength = <16>; bias-disable; }; - cmd { + cmd-pins { pins = "sdc2_cmd"; drive-strength = <10>; bias-pull-up; }; - data { + data-pins { pins = "sdc2_data"; drive-strength = <10>; bias-pull-up; diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi index eb6b2b676eca..31ec5ff0a63d 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi @@ -46,7 +46,7 @@ key-vol-up { label = "Volume Up"; linux,code = <KEY_VOLUMEUP>; - gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; + gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>; }; }; @@ -299,12 +299,13 @@ }; &ipa { - status = "okay"; + qcom,gsi-loader = "self"; memory-region = <&ipa_fw_mem>; firmware-name = "qcom/sdm845/beryllium/ipa_fws.mbn"; + status = "okay"; }; -&pm8998_gpio { +&pm8998_gpios { vol_up_pin_a: vol-up-active-state { pins = "gpio6"; function = "normal"; @@ -325,14 +326,9 @@ qcom,cabc; }; -&pm8998_pon { - resin { - compatible = "qcom,pm8941-resin"; - interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = <KEY_VOLUMEDOWN>; - }; +&pm8998_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; }; &pmi8998_rradc { @@ -445,34 +441,34 @@ &tlmm { gpio-reserved-ranges = <0 4>, <81 4>; - sdc2_default_state: sdc2-default { - clk { + sdc2_default_state: sdc2-default-state { + clk-pins { pins = "sdc2_clk"; bias-disable; drive-strength = <16>; }; - cmd { + cmd-pins { pins = "sdc2_cmd"; bias-pull-up; drive-strength = <10>; }; - data { + data-pins { pins = "sdc2_data"; bias-pull-up; drive-strength = <10>; }; }; - sdc2_card_det_n: sd-card-det-n { + sdc2_card_det_n: sd-card-det-n-state { pins = "gpio126"; function = "gpio"; bias-pull-up; }; - wcd_intr_default: wcd_intr_default { - pins = <54>; + wcd_intr_default: wcd-intr-default-state { + pins = "gpio54"; function = "gpio"; input-enable; @@ -546,7 +542,7 @@ firmware-name = "qcom/sdm845/beryllium/venus.mbn"; }; -&wcd9340{ +&wcd9340 { pinctrl-0 = <&wcd_intr_default>; pinctrl-names = "default"; clock-names = "extclk"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts index 38ba809a95cd..8b42efbf1996 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts @@ -55,7 +55,7 @@ key-vol-up { label = "Volume Up"; linux,code = <KEY_VOLUMEUP>; - gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; + gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>; debounce-interval = <15>; }; }; @@ -449,6 +449,7 @@ }; &ipa { + qcom,gsi-loader = "self"; memory-region = <&ipa_fw_mem>; firmware-name = "qcom/sdm845/polaris/ipa_fws.mbn"; status = "okay"; @@ -518,7 +519,7 @@ status = "okay"; }; -&pm8998_gpio { +&pm8998_gpios { volume_up_gpio: pm8998-gpio6-state { pinconf { qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; @@ -530,14 +531,9 @@ }; }; -&pm8998_pon { - resin { - interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; - compatible = "qcom,pm8941-resin"; - linux,code = <KEY_VOLUMEDOWN>; - debounce = <15625>; - bias-pull-up; - }; +&pm8998_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; }; &q6afedai { @@ -570,24 +566,21 @@ }; &qup_i2c14_default { - pinconf { - pins = "gpio33", "gpio34"; - drive-strength = <2>; - bias-disable; - }; + drive-strength = <2>; + bias-disable; }; &tlmm { gpio-reserved-ranges = <0 4>, <81 4>; - ts_reset_default: ts-reset-default { + ts_reset_default: ts-reset-default-state { pins = "gpio99"; function = "gpio"; drive-strength = <16>; output-high; }; - ts_int_default: ts-int-default { + ts_int_default: ts-int-default-state { pins = "gpio125"; function = "gpio"; bias-pull-down; @@ -595,14 +588,14 @@ input-enable; }; - ts_reset_sleep: ts-reset-sleep { + ts_reset_sleep: ts-reset-sleep-state { pins = "gpio99"; function = "gpio"; bias-disable; drive-strength = <2>; }; - ts_int_sleep: ts-int-sleep { + ts_int_sleep: ts-int-sleep-state { pins = "gpio125"; function = "gpio"; bias-pull-down; @@ -610,21 +603,21 @@ input-enable; }; - sde_dsi_active: sde-dsi-active { + sde_dsi_active: sde-dsi-active-state { pins = "gpio6", "gpio10"; function = "gpio"; drive-strength = <8>; bias-disable; }; - sde_dsi_suspend: sde-dsi-suspend { + sde_dsi_suspend: sde-dsi-suspend-state { pins = "gpio6", "gpio10"; function = "gpio"; drive-strength = <2>; bias-pull-down; }; - wcd_intr_default: wcd-intr-default { + wcd_intr_default: wcd-intr-default-state { pins = "gpio54"; function = "gpio"; input-enable; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 65032b94b46d..9ffc0fe07c21 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -69,122 +69,18 @@ chosen { }; - memory@80000000 { - device_type = "memory"; - /* We expect the bootloader to fill in the size */ - reg = <0 0x80000000 0 0>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - hyp_mem: hyp-mem@85700000 { - reg = <0 0x85700000 0 0x600000>; - no-map; - }; - - xbl_mem: xbl-mem@85e00000 { - reg = <0 0x85e00000 0 0x100000>; - no-map; - }; - - aop_mem: aop-mem@85fc0000 { - reg = <0 0x85fc0000 0 0x20000>; - no-map; - }; - - aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 { - compatible = "qcom,cmd-db"; - reg = <0x0 0x85fe0000 0 0x20000>; - no-map; - }; - - smem@86000000 { - compatible = "qcom,smem"; - reg = <0x0 0x86000000 0 0x200000>; - no-map; - hwlocks = <&tcsr_mutex 3>; - }; - - tz_mem: tz@86200000 { - reg = <0 0x86200000 0 0x2d00000>; - no-map; - }; - - rmtfs_mem: rmtfs@88f00000 { - compatible = "qcom,rmtfs-mem"; - reg = <0 0x88f00000 0 0x200000>; - no-map; - - qcom,client-id = <1>; - qcom,vmid = <15>; - }; - - qseecom_mem: qseecom@8ab00000 { - reg = <0 0x8ab00000 0 0x1400000>; - no-map; - }; - - camera_mem: camera-mem@8bf00000 { - reg = <0 0x8bf00000 0 0x500000>; - no-map; - }; - - ipa_fw_mem: ipa-fw@8c400000 { - reg = <0 0x8c400000 0 0x10000>; - no-map; - }; - - ipa_gsi_mem: ipa-gsi@8c410000 { - reg = <0 0x8c410000 0 0x5000>; - no-map; - }; - - gpu_mem: gpu@8c415000 { - reg = <0 0x8c415000 0 0x2000>; - no-map; - }; - - adsp_mem: adsp@8c500000 { - reg = <0 0x8c500000 0 0x1a00000>; - no-map; - }; - - wlan_msa_mem: wlan-msa@8df00000 { - reg = <0 0x8df00000 0 0x100000>; - no-map; - }; - - mpss_region: mpss@8e000000 { - reg = <0 0x8e000000 0 0x7800000>; - no-map; - }; - - venus_mem: venus@95800000 { - reg = <0 0x95800000 0 0x500000>; - no-map; - }; - - cdsp_mem: cdsp@95d00000 { - reg = <0 0x95d00000 0 0x800000>; - no-map; - }; - - mba_region: mba@96500000 { - reg = <0 0x96500000 0 0x200000>; - no-map; - }; - - slpi_mem: slpi@96700000 { - reg = <0 0x96700000 0 0x1400000>; - no-map; + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <38400000>; + clock-output-names = "xo_board"; }; - spss_mem: spss@97b00000 { - reg = <0 0x97b00000 0 0x100000>; - no-map; + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32764>; }; }; @@ -209,9 +105,11 @@ next-level-cache = <&L2_0>; L2_0: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; L3_0: l3-cache { compatible = "cache"; + cache-level = <3>; }; }; }; @@ -233,6 +131,7 @@ next-level-cache = <&L2_100>; L2_100: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -254,6 +153,7 @@ next-level-cache = <&L2_200>; L2_200: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -275,6 +175,7 @@ next-level-cache = <&L2_300>; L2_300: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -296,6 +197,7 @@ next-level-cache = <&L2_400>; L2_400: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -317,6 +219,7 @@ next-level-cache = <&L2_500>; L2_500: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -338,6 +241,7 @@ next-level-cache = <&L2_600>; L2_600: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -359,6 +263,7 @@ next-level-cache = <&L2_700>; L2_700: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -436,6 +341,18 @@ }; }; + firmware { + scm { + compatible = "qcom,scm-sdm845", "qcom,scm"; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0 0x80000000 0 0>; + }; + cpu0_opp_table: opp-table-cpu0 { compatible = "operating-points-v2"; opp-shared; @@ -696,37 +613,262 @@ }; }; + dsi_opp_table: opp-table-dsi { + compatible = "operating-points-v2"; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-180000000 { + opp-hz = /bits/ 64 <180000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-275000000 { + opp-hz = /bits/ 64 <275000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-328580000 { + opp-hz = /bits/ 64 <328580000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + + qspi_opp_table: opp-table-qspi { + compatible = "operating-points-v2"; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-150000000 { + opp-hz = /bits/ 64 <150000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + + qup_opp_table: opp-table-qup { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-128000000 { + opp-hz = /bits/ 64 <128000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + pmu { compatible = "arm,armv8-pmuv3"; interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; }; - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, - <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, - <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, - <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; - }; + psci: psci { + compatible = "arm,psci-1.0"; + method = "smc"; - clocks { - xo_board: xo-board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <38400000>; - clock-output-names = "xo_board"; + CPU_PD0: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; - sleep_clk: sleep-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32764>; + CPU_PD1: power-domain-cpu1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD2: power-domain-cpu2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD3: power-domain-cpu3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD4: power-domain-cpu4 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD5: power-domain-cpu5 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD6: power-domain-cpu6 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD7: power-domain-cpu7 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CLUSTER_PD: power-domain-cluster { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_SLEEP_0>; }; }; - firmware { - scm { - compatible = "qcom,scm-sdm845", "qcom,scm"; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: hyp-mem@85700000 { + reg = <0 0x85700000 0 0x600000>; + no-map; + }; + + xbl_mem: xbl-mem@85e00000 { + reg = <0 0x85e00000 0 0x100000>; + no-map; + }; + + aop_mem: aop-mem@85fc0000 { + reg = <0 0x85fc0000 0 0x20000>; + no-map; + }; + + aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 { + compatible = "qcom,cmd-db"; + reg = <0x0 0x85fe0000 0 0x20000>; + no-map; + }; + + smem@86000000 { + compatible = "qcom,smem"; + reg = <0x0 0x86000000 0 0x200000>; + no-map; + hwlocks = <&tcsr_mutex 3>; + }; + + tz_mem: tz@86200000 { + reg = <0 0x86200000 0 0x2d00000>; + no-map; + }; + + rmtfs_mem: rmtfs@88f00000 { + compatible = "qcom,rmtfs-mem"; + reg = <0 0x88f00000 0 0x200000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = <15>; + }; + + qseecom_mem: qseecom@8ab00000 { + reg = <0 0x8ab00000 0 0x1400000>; + no-map; + }; + + camera_mem: camera-mem@8bf00000 { + reg = <0 0x8bf00000 0 0x500000>; + no-map; + }; + + ipa_fw_mem: ipa-fw@8c400000 { + reg = <0 0x8c400000 0 0x10000>; + no-map; + }; + + ipa_gsi_mem: ipa-gsi@8c410000 { + reg = <0 0x8c410000 0 0x5000>; + no-map; + }; + + gpu_mem: gpu@8c415000 { + reg = <0 0x8c415000 0 0x2000>; + no-map; + }; + + adsp_mem: adsp@8c500000 { + reg = <0 0x8c500000 0 0x1a00000>; + no-map; + }; + + wlan_msa_mem: wlan-msa@8df00000 { + reg = <0 0x8df00000 0 0x100000>; + no-map; + }; + + mpss_region: mpss@8e000000 { + reg = <0 0x8e000000 0 0x7800000>; + no-map; + }; + + venus_mem: venus@95800000 { + reg = <0 0x95800000 0 0x500000>; + no-map; + }; + + cdsp_mem: cdsp@95d00000 { + reg = <0 0x95d00000 0 0x800000>; + no-map; + }; + + mba_region: mba@96500000 { + reg = <0 0x96500000 0 0x200000>; + no-map; + }; + + slpi_mem: slpi@96700000 { + reg = <0 0x96700000 0 0x1400000>; + no-map; + }; + + spss_mem: spss@97b00000 { + reg = <0 0x97b00000 0 0x100000>; + no-map; + }; + + mdata_mem: mpss-metadata { + alloc-ranges = <0 0xa0000000 0 0x20000000>; + size = <0 0x4000>; + no-map; }; }; @@ -1018,64 +1160,6 @@ }; }; - psci: psci { - compatible = "arm,psci-1.0"; - method = "smc"; - - CPU_PD0: power-domain-cpu0 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; - }; - - CPU_PD1: power-domain-cpu1 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; - }; - - CPU_PD2: power-domain-cpu2 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; - }; - - CPU_PD3: power-domain-cpu3 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; - }; - - CPU_PD4: power-domain-cpu4 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; - }; - - CPU_PD5: power-domain-cpu5 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; - }; - - CPU_PD6: power-domain-cpu6 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; - }; - - CPU_PD7: power-domain-cpu7 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; - }; - - CLUSTER_PD: power-domain-cluster { - #power-domain-cells = <0>; - domain-idle-states = <&CLUSTER_SLEEP_0>; - }; - }; - soc: soc@0 { #address-cells = <2>; #size-cells = <2>; @@ -1125,30 +1209,6 @@ clock-names = "core"; }; - qup_opp_table: opp-table-qup { - compatible = "operating-points-v2"; - - opp-50000000 { - opp-hz = /bits/ 64 <50000000>; - required-opps = <&rpmhpd_opp_min_svs>; - }; - - opp-75000000 { - opp-hz = /bits/ 64 <75000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-128000000 { - opp-hz = /bits/ 64 <128000000>; - required-opps = <&rpmhpd_opp_nom>; - }; - }; - gpi_dma0: dma-controller@800000 { #dma-cells = <3>; compatible = "qcom,sdm845-gpi-dma"; @@ -1636,7 +1696,7 @@ }; }; - gpi_dma1: dma-controller@0xa00000 { + gpi_dma1: dma-controller@a00000 { #dma-cells = <3>; compatible = "qcom,sdm845-gpi-dma"; reg = <0 0x00a00000 0 0x60000>; @@ -2137,6 +2197,12 @@ interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; }; + dma@10a2000 { + compatible = "qcom,sdm845-dcc", "qcom,dcc"; + reg = <0x0 0x010a2000 0x0 0x1000>, + <0x0 0x010ae000 0x0 0x2000>; + }; + pmu@114a000 { compatible = "qcom,sdm845-llcc-bwmon"; reg = <0 0x0114a000 0 0x1000>; @@ -2585,9 +2651,9 @@ iommus = <&apps_smmu 0x720 0x0>, <&apps_smmu 0x722 0x0>; - reg = <0 0x1e40000 0 0x7000>, - <0 0x1e47000 0 0x2000>, - <0 0x1e04000 0 0x2c000>; + reg = <0 0x01e40000 0 0x7000>, + <0 0x01e47000 0 0x2000>, + <0 0x01e04000 0 0x2c000>; reg-names = "ipa-reg", "ipa-shared", "gsi"; @@ -2641,7 +2707,7 @@ gpio-ranges = <&tlmm 0 0 151>; wakeup-parent = <&pdc_intc>; - cci0_default: cci0-default { + cci0_default: cci0-default-state { /* SDA, SCL */ pins = "gpio17", "gpio18"; function = "cci_i2c"; @@ -2650,7 +2716,7 @@ drive-strength = <2>; /* 2 mA */ }; - cci0_sleep: cci0-sleep { + cci0_sleep: cci0-sleep-state { /* SDA, SCL */ pins = "gpio17", "gpio18"; function = "cci_i2c"; @@ -2659,7 +2725,7 @@ bias-pull-down; }; - cci1_default: cci1-default { + cci1_default: cci1-default-state { /* SDA, SCL */ pins = "gpio19", "gpio20"; function = "cci_i2c"; @@ -2668,7 +2734,7 @@ drive-strength = <2>; /* 2 mA */ }; - cci1_sleep: cci1-sleep { + cci1_sleep: cci1-sleep-state { /* SDA, SCL */ pins = "gpio19", "gpio20"; function = "cci_i2c"; @@ -2677,556 +2743,495 @@ bias-pull-down; }; - qspi_clk: qspi-clk { - pinmux { - pins = "gpio95"; - function = "qspi_clk"; - }; + qspi_clk: qspi-clk-state { + pins = "gpio95"; + function = "qspi_clk"; }; - qspi_cs0: qspi-cs0 { - pinmux { - pins = "gpio90"; - function = "qspi_cs"; - }; + qspi_cs0: qspi-cs0-state { + pins = "gpio90"; + function = "qspi_cs"; }; - qspi_cs1: qspi-cs1 { - pinmux { - pins = "gpio89"; - function = "qspi_cs"; - }; + qspi_cs1: qspi-cs1-state { + pins = "gpio89"; + function = "qspi_cs"; }; - qspi_data01: qspi-data01 { - pinmux-data { - pins = "gpio91", "gpio92"; - function = "qspi_data"; - }; + qspi_data01: qspi-data01-state { + pins = "gpio91", "gpio92"; + function = "qspi_data"; }; - qspi_data12: qspi-data12 { - pinmux-data { - pins = "gpio93", "gpio94"; - function = "qspi_data"; - }; + qspi_data12: qspi-data12-state { + pins = "gpio93", "gpio94"; + function = "qspi_data"; }; - qup_i2c0_default: qup-i2c0-default { - pinmux { - pins = "gpio0", "gpio1"; - function = "qup0"; - }; + qup_i2c0_default: qup-i2c0-default-state { + pins = "gpio0", "gpio1"; + function = "qup0"; }; - qup_i2c1_default: qup-i2c1-default { - pinmux { - pins = "gpio17", "gpio18"; - function = "qup1"; - }; + qup_i2c1_default: qup-i2c1-default-state { + pins = "gpio17", "gpio18"; + function = "qup1"; }; - qup_i2c2_default: qup-i2c2-default { - pinmux { - pins = "gpio27", "gpio28"; - function = "qup2"; - }; + qup_i2c2_default: qup-i2c2-default-state { + pins = "gpio27", "gpio28"; + function = "qup2"; }; - qup_i2c3_default: qup-i2c3-default { - pinmux { - pins = "gpio41", "gpio42"; - function = "qup3"; - }; + qup_i2c3_default: qup-i2c3-default-state { + pins = "gpio41", "gpio42"; + function = "qup3"; }; - qup_i2c4_default: qup-i2c4-default { - pinmux { - pins = "gpio89", "gpio90"; - function = "qup4"; - }; + qup_i2c4_default: qup-i2c4-default-state { + pins = "gpio89", "gpio90"; + function = "qup4"; }; - qup_i2c5_default: qup-i2c5-default { - pinmux { - pins = "gpio85", "gpio86"; - function = "qup5"; - }; + qup_i2c5_default: qup-i2c5-default-state { + pins = "gpio85", "gpio86"; + function = "qup5"; }; - qup_i2c6_default: qup-i2c6-default { - pinmux { - pins = "gpio45", "gpio46"; - function = "qup6"; - }; + qup_i2c6_default: qup-i2c6-default-state { + pins = "gpio45", "gpio46"; + function = "qup6"; }; - qup_i2c7_default: qup-i2c7-default { - pinmux { - pins = "gpio93", "gpio94"; - function = "qup7"; - }; + qup_i2c7_default: qup-i2c7-default-state { + pins = "gpio93", "gpio94"; + function = "qup7"; }; - qup_i2c8_default: qup-i2c8-default { - pinmux { - pins = "gpio65", "gpio66"; - function = "qup8"; - }; + qup_i2c8_default: qup-i2c8-default-state { + pins = "gpio65", "gpio66"; + function = "qup8"; }; - qup_i2c9_default: qup-i2c9-default { - pinmux { - pins = "gpio6", "gpio7"; - function = "qup9"; - }; + qup_i2c9_default: qup-i2c9-default-state { + pins = "gpio6", "gpio7"; + function = "qup9"; }; - qup_i2c10_default: qup-i2c10-default { - pinmux { - pins = "gpio55", "gpio56"; - function = "qup10"; - }; + qup_i2c10_default: qup-i2c10-default-state { + pins = "gpio55", "gpio56"; + function = "qup10"; }; - qup_i2c11_default: qup-i2c11-default { - pinmux { - pins = "gpio31", "gpio32"; - function = "qup11"; - }; + qup_i2c11_default: qup-i2c11-default-state { + pins = "gpio31", "gpio32"; + function = "qup11"; }; - qup_i2c12_default: qup-i2c12-default { - pinmux { - pins = "gpio49", "gpio50"; - function = "qup12"; - }; + qup_i2c12_default: qup-i2c12-default-state { + pins = "gpio49", "gpio50"; + function = "qup12"; }; - qup_i2c13_default: qup-i2c13-default { - pinmux { - pins = "gpio105", "gpio106"; - function = "qup13"; - }; + qup_i2c13_default: qup-i2c13-default-state { + pins = "gpio105", "gpio106"; + function = "qup13"; }; - qup_i2c14_default: qup-i2c14-default { - pinmux { - pins = "gpio33", "gpio34"; - function = "qup14"; - }; + qup_i2c14_default: qup-i2c14-default-state { + pins = "gpio33", "gpio34"; + function = "qup14"; }; - qup_i2c15_default: qup-i2c15-default { - pinmux { - pins = "gpio81", "gpio82"; - function = "qup15"; - }; + qup_i2c15_default: qup-i2c15-default-state { + pins = "gpio81", "gpio82"; + function = "qup15"; }; - qup_spi0_default: qup-spi0-default { - pinmux { - pins = "gpio0", "gpio1", - "gpio2", "gpio3"; - function = "qup0"; - }; + qup_spi0_default: qup-spi0-default-state { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "qup0"; + }; - config { - pins = "gpio0", "gpio1", - "gpio2", "gpio3"; - drive-strength = <6>; - bias-disable; - }; + qup_spi1_default: qup-spi1-default-state { + pins = "gpio17", "gpio18", "gpio19", "gpio20"; + function = "qup1"; }; - qup_spi1_default: qup-spi1-default { - pinmux { - pins = "gpio17", "gpio18", - "gpio19", "gpio20"; - function = "qup1"; - }; + qup_spi2_default: qup-spi2-default-state { + pins = "gpio27", "gpio28", "gpio29", "gpio30"; + function = "qup2"; }; - qup_spi2_default: qup-spi2-default { - pinmux { - pins = "gpio27", "gpio28", - "gpio29", "gpio30"; - function = "qup2"; - }; + qup_spi3_default: qup-spi3-default-state { + pins = "gpio41", "gpio42", "gpio43", "gpio44"; + function = "qup3"; }; - qup_spi3_default: qup-spi3-default { - pinmux { - pins = "gpio41", "gpio42", - "gpio43", "gpio44"; - function = "qup3"; - }; + qup_spi4_default: qup-spi4-default-state { + pins = "gpio89", "gpio90", "gpio91", "gpio92"; + function = "qup4"; }; - qup_spi4_default: qup-spi4-default { - pinmux { - pins = "gpio89", "gpio90", - "gpio91", "gpio92"; - function = "qup4"; - }; + qup_spi5_default: qup-spi5-default-state { + pins = "gpio85", "gpio86", "gpio87", "gpio88"; + function = "qup5"; }; - qup_spi5_default: qup-spi5-default { - pinmux { - pins = "gpio85", "gpio86", - "gpio87", "gpio88"; - function = "qup5"; - }; + qup_spi6_default: qup-spi6-default-state { + pins = "gpio45", "gpio46", "gpio47", "gpio48"; + function = "qup6"; }; - qup_spi6_default: qup-spi6-default { - pinmux { - pins = "gpio45", "gpio46", - "gpio47", "gpio48"; - function = "qup6"; - }; + qup_spi7_default: qup-spi7-default-state { + pins = "gpio93", "gpio94", "gpio95", "gpio96"; + function = "qup7"; }; - qup_spi7_default: qup-spi7-default { - pinmux { - pins = "gpio93", "gpio94", - "gpio95", "gpio96"; - function = "qup7"; - }; + qup_spi8_default: qup-spi8-default-state { + pins = "gpio65", "gpio66", "gpio67", "gpio68"; + function = "qup8"; }; - qup_spi8_default: qup-spi8-default { - pinmux { - pins = "gpio65", "gpio66", - "gpio67", "gpio68"; - function = "qup8"; - }; + qup_spi9_default: qup-spi9-default-state { + pins = "gpio6", "gpio7", "gpio4", "gpio5"; + function = "qup9"; }; - qup_spi9_default: qup-spi9-default { - pinmux { - pins = "gpio6", "gpio7", - "gpio4", "gpio5"; - function = "qup9"; - }; + qup_spi10_default: qup-spi10-default-state { + pins = "gpio55", "gpio56", "gpio53", "gpio54"; + function = "qup10"; }; - qup_spi10_default: qup-spi10-default { - pinmux { - pins = "gpio55", "gpio56", - "gpio53", "gpio54"; - function = "qup10"; - }; + qup_spi11_default: qup-spi11-default-state { + pins = "gpio31", "gpio32", "gpio33", "gpio34"; + function = "qup11"; }; - qup_spi11_default: qup-spi11-default { - pinmux { - pins = "gpio31", "gpio32", - "gpio33", "gpio34"; - function = "qup11"; - }; + qup_spi12_default: qup-spi12-default-state { + pins = "gpio49", "gpio50", "gpio51", "gpio52"; + function = "qup12"; }; - qup_spi12_default: qup-spi12-default { - pinmux { - pins = "gpio49", "gpio50", - "gpio51", "gpio52"; - function = "qup12"; - }; + qup_spi13_default: qup-spi13-default-state { + pins = "gpio105", "gpio106", "gpio107", "gpio108"; + function = "qup13"; }; - qup_spi13_default: qup-spi13-default { - pinmux { - pins = "gpio105", "gpio106", - "gpio107", "gpio108"; - function = "qup13"; - }; + qup_spi14_default: qup-spi14-default-state { + pins = "gpio33", "gpio34", "gpio31", "gpio32"; + function = "qup14"; }; - qup_spi14_default: qup-spi14-default { - pinmux { - pins = "gpio33", "gpio34", - "gpio31", "gpio32"; - function = "qup14"; - }; + qup_spi15_default: qup-spi15-default-state { + pins = "gpio81", "gpio82", "gpio83", "gpio84"; + function = "qup15"; }; - qup_spi15_default: qup-spi15-default { - pinmux { - pins = "gpio81", "gpio82", - "gpio83", "gpio84"; - function = "qup15"; + qup_uart0_default: qup-uart0-default-state { + qup_uart0_tx: tx-pins { + pins = "gpio2"; + function = "qup0"; }; - }; - qup_uart0_default: qup-uart0-default { - pinmux { - pins = "gpio2", "gpio3"; + qup_uart0_rx: rx-pins { + pins = "gpio3"; function = "qup0"; }; }; - qup_uart1_default: qup-uart1-default { - pinmux { - pins = "gpio19", "gpio20"; + qup_uart1_default: qup-uart1-default-state { + qup_uart1_tx: tx-pins { + pins = "gpio19"; + function = "qup1"; + }; + + qup_uart1_rx: rx-pins { + pins = "gpio20"; function = "qup1"; }; }; - qup_uart2_default: qup-uart2-default { - pinmux { - pins = "gpio29", "gpio30"; + qup_uart2_default: qup-uart2-default-state { + qup_uart2_tx: tx-pins { + pins = "gpio29"; function = "qup2"; }; + + qup_uart2_rx: rx-pins { + pins = "gpio30"; + function = "qup2"; + }; + }; + + qup_uart3_default: qup-uart3-default-state { + qup_uart3_tx: tx-pins { + pins = "gpio43"; + function = "qup3"; + }; + + qup_uart3_rx: rx-pins { + pins = "gpio44"; + function = "qup3"; + }; }; - qup_uart3_default: qup-uart3-default { - pinmux { - pins = "gpio43", "gpio44"; + qup_uart3_4pin: qup-uart3-4pin-state { + qup_uart3_4pin_cts: cts-pins { + pins = "gpio41"; + function = "qup3"; + }; + + qup_uart3_4pin_rts_tx: rts-tx-pins { + pins = "gpio42", "gpio43"; + function = "qup3"; + }; + + qup_uart3_4pin_rx: rx-pins { + pins = "gpio44"; function = "qup3"; }; }; - qup_uart4_default: qup-uart4-default { - pinmux { - pins = "gpio91", "gpio92"; + qup_uart4_default: qup-uart4-default-state { + qup_uart4_tx: tx-pins { + pins = "gpio91"; + function = "qup4"; + }; + + qup_uart4_rx: rx-pins { + pins = "gpio92"; function = "qup4"; }; }; - qup_uart5_default: qup-uart5-default { - pinmux { - pins = "gpio87", "gpio88"; + qup_uart5_default: qup-uart5-default-state { + qup_uart5_tx: tx-pins { + pins = "gpio87"; + function = "qup5"; + }; + + qup_uart5_rx: rx-pins { + pins = "gpio88"; function = "qup5"; }; }; - qup_uart6_default: qup-uart6-default { - pinmux { - pins = "gpio47", "gpio48"; + qup_uart6_default: qup-uart6-default-state { + qup_uart6_tx: tx-pins { + pins = "gpio47"; + function = "qup6"; + }; + + qup_uart6_rx: rx-pins { + pins = "gpio48"; function = "qup6"; }; }; qup_uart6_4pin: qup-uart6-4pin-state { - - cts-pins { + qup_uart6_4pin_cts: cts-pins { pins = "gpio45"; function = "qup6"; bias-pull-down; }; - rts-tx-pins { + qup_uart6_4pin_rts_tx: rts-tx-pins { pins = "gpio46", "gpio47"; function = "qup6"; drive-strength = <2>; bias-disable; }; - rx-pins { + qup_uart6_4pin_rx: rx-pins { pins = "gpio48"; function = "qup6"; bias-pull-up; }; }; - qup_uart7_default: qup-uart7-default { - pinmux { - pins = "gpio95", "gpio96"; + qup_uart7_default: qup-uart7-default-state { + qup_uart7_tx: tx-pins { + pins = "gpio95"; function = "qup7"; }; - }; - - qup_uart8_default: qup-uart8-default { - pinmux { - pins = "gpio67", "gpio68"; - function = "qup8"; - }; - }; - qup_uart9_default: qup-uart9-default { - pinmux { - pins = "gpio4", "gpio5"; - function = "qup9"; + qup_uart7_rx: rx-pins { + pins = "gpio96"; + function = "qup7"; }; }; - qup_uart10_default: qup-uart10-default { - pinmux { - pins = "gpio53", "gpio54"; - function = "qup10"; + qup_uart8_default: qup-uart8-default-state { + qup_uart8_tx: tx-pins { + pins = "gpio67"; + function = "qup8"; }; - }; - qup_uart11_default: qup-uart11-default { - pinmux { - pins = "gpio33", "gpio34"; - function = "qup11"; + qup_uart8_rx: rx-pins { + pins = "gpio68"; + function = "qup8"; }; }; - qup_uart12_default: qup-uart12-default { - pinmux { - pins = "gpio51", "gpio52"; - function = "qup12"; + qup_uart9_default: qup-uart9-default-state { + qup_uart9_tx: tx-pins { + pins = "gpio4"; + function = "qup9"; }; - }; - qup_uart13_default: qup-uart13-default { - pinmux { - pins = "gpio107", "gpio108"; - function = "qup13"; + qup_uart9_rx: rx-pins { + pins = "gpio5"; + function = "qup9"; }; }; - qup_uart14_default: qup-uart14-default { - pinmux { - pins = "gpio31", "gpio32"; - function = "qup14"; + qup_uart10_default: qup-uart10-default-state { + qup_uart10_tx: tx-pins { + pins = "gpio53"; + function = "qup10"; }; - }; - qup_uart15_default: qup-uart15-default { - pinmux { - pins = "gpio83", "gpio84"; - function = "qup15"; + qup_uart10_rx: rx-pins { + pins = "gpio54"; + function = "qup10"; }; }; - quat_mi2s_sleep: quat_mi2s_sleep { - mux { - pins = "gpio58", "gpio59"; - function = "gpio"; + qup_uart11_default: qup-uart11-default-state { + qup_uart11_tx: tx-pins { + pins = "gpio33"; + function = "qup11"; }; - config { - pins = "gpio58", "gpio59"; - drive-strength = <2>; - bias-pull-down; - input-enable; + qup_uart11_rx: rx-pins { + pins = "gpio34"; + function = "qup11"; }; }; - quat_mi2s_active: quat_mi2s_active { - mux { - pins = "gpio58", "gpio59"; - function = "qua_mi2s"; + qup_uart12_default: qup-uart12-default-state { + qup_uart12_tx: tx-pins { + pins = "gpio51"; + function = "qup0"; }; - config { - pins = "gpio58", "gpio59"; - drive-strength = <8>; - bias-disable; - output-high; + qup_uart12_rx: rx-pins { + pins = "gpio52"; + function = "qup0"; }; }; - quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep { - mux { - pins = "gpio60"; - function = "gpio"; + qup_uart13_default: qup-uart13-default-state { + qup_uart13_tx: tx-pins { + pins = "gpio107"; + function = "qup13"; }; - config { - pins = "gpio60"; - drive-strength = <2>; - bias-pull-down; - input-enable; + qup_uart13_rx: rx-pins { + pins = "gpio108"; + function = "qup13"; }; }; - quat_mi2s_sd0_active: quat_mi2s_sd0_active { - mux { - pins = "gpio60"; - function = "qua_mi2s"; + qup_uart14_default: qup-uart14-default-state { + qup_uart14_tx: tx-pins { + pins = "gpio31"; + function = "qup14"; }; - config { - pins = "gpio60"; - drive-strength = <8>; - bias-disable; + qup_uart14_rx: rx-pins { + pins = "gpio32"; + function = "qup14"; }; }; - quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep { - mux { - pins = "gpio61"; - function = "gpio"; + qup_uart15_default: qup-uart15-default-state { + qup_uart15_tx: tx-pins { + pins = "gpio83"; + function = "qup15"; }; - config { - pins = "gpio61"; - drive-strength = <2>; - bias-pull-down; - input-enable; + qup_uart15_rx: rx-pins { + pins = "gpio84"; + function = "qup15"; }; }; - quat_mi2s_sd1_active: quat_mi2s_sd1_active { - mux { - pins = "gpio61"; - function = "qua_mi2s"; - }; + quat_mi2s_sleep: quat-mi2s-sleep-state { + pins = "gpio58", "gpio59"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; - config { - pins = "gpio61"; - drive-strength = <8>; - bias-disable; - }; + quat_mi2s_active: quat-mi2s-active-state { + pins = "gpio58", "gpio59"; + function = "qua_mi2s"; + drive-strength = <8>; + bias-disable; + output-high; }; - quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep { - mux { - pins = "gpio62"; - function = "gpio"; - }; + quat_mi2s_sd0_sleep: quat-mi2s-sd0-sleep-state { + pins = "gpio60"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; - config { - pins = "gpio62"; - drive-strength = <2>; - bias-pull-down; - input-enable; - }; + quat_mi2s_sd0_active: quat-mi2s-sd0-active-state { + pins = "gpio60"; + function = "qua_mi2s"; + drive-strength = <8>; + bias-disable; }; - quat_mi2s_sd2_active: quat_mi2s_sd2_active { - mux { - pins = "gpio62"; - function = "qua_mi2s"; - }; + quat_mi2s_sd1_sleep: quat-mi2s-sd1-sleep-state { + pins = "gpio61"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; - config { - pins = "gpio62"; - drive-strength = <8>; - bias-disable; - }; + quat_mi2s_sd1_active: quat-mi2s-sd1-active-state { + pins = "gpio61"; + function = "qua_mi2s"; + drive-strength = <8>; + bias-disable; }; - quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep { - mux { - pins = "gpio63"; - function = "gpio"; - }; + quat_mi2s_sd2_sleep: quat-mi2s-sd2-sleep-state { + pins = "gpio62"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; - config { - pins = "gpio63"; - drive-strength = <2>; - bias-pull-down; - input-enable; - }; + quat_mi2s_sd2_active: quat-mi2s-sd2-active-state { + pins = "gpio62"; + function = "qua_mi2s"; + drive-strength = <8>; + bias-disable; }; - quat_mi2s_sd3_active: quat_mi2s_sd3_active { - mux { - pins = "gpio63"; - function = "qua_mi2s"; - }; + quat_mi2s_sd3_sleep: quat-mi2s-sd3-sleep-state { + pins = "gpio63"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; - config { - pins = "gpio63"; - drive-strength = <8>; - bias-disable; - }; + quat_mi2s_sd3_active: quat-mi2s-sd3-active-state { + pins = "gpio63"; + function = "qua_mi2s"; + drive-strength = <8>; + bias-disable; }; }; @@ -3283,6 +3288,10 @@ memory-region = <&mpss_region>; }; + metadata { + memory-region = <&mdata_mem>; + }; + glink-edge { interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; label = "modem"; @@ -3807,30 +3816,6 @@ }; }; - qspi_opp_table: opp-table-qspi { - compatible = "operating-points-v2"; - - opp-19200000 { - opp-hz = /bits/ 64 <19200000>; - required-opps = <&rpmhpd_opp_min_svs>; - }; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-150000000 { - opp-hz = /bits/ 64 <150000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - required-opps = <&rpmhpd_opp_nom>; - }; - }; - qspi: spi@88df000 { compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; reg = <0 0x088df000 0 0x600>; @@ -3903,17 +3888,15 @@ qcom,dout-ports = <6>; qcom,din-ports = <2>; - qcom,ports-sinterval-low =/bits/ 8 <0x07 0x1F 0x3F 0x7 0x1F 0x3F 0x0F 0x0F>; - qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0C 0x6 0x12 0x0D 0x07 0x0A >; - qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1F 0x00 0x00 0x1F 0x00 0x00>; + qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x7 0x1f 0x3f 0x0f 0x0f>; + qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x6 0x12 0x0d 0x07 0x0a>; + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1f 0x00 0x00 0x1f 0x00 0x00>; #sound-dai-cells = <1>; clocks = <&wcd9340>; clock-names = "iface"; #address-cells = <2>; #size-cells = <0>; - - }; }; }; @@ -3943,9 +3926,6 @@ #interrupt-cells = <1>; }; - sound: sound { - }; - usb_1_hsphy: phy@88e2000 { compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy"; reg = <0 0x088e2000 0 0x400>; @@ -4239,16 +4219,16 @@ camss: camss@a00000 { compatible = "qcom,sdm845-camss"; - reg = <0 0xacb3000 0 0x1000>, - <0 0xacba000 0 0x1000>, - <0 0xacc8000 0 0x1000>, - <0 0xac65000 0 0x1000>, - <0 0xac66000 0 0x1000>, - <0 0xac67000 0 0x1000>, - <0 0xac68000 0 0x1000>, - <0 0xacaf000 0 0x4000>, - <0 0xacb6000 0 0x4000>, - <0 0xacc4000 0 0x4000>; + reg = <0 0x0acb3000 0 0x1000>, + <0 0x0acba000 0 0x1000>, + <0 0x0acc8000 0 0x1000>, + <0 0x0ac65000 0 0x1000>, + <0 0x0ac66000 0 0x1000>, + <0 0x0ac67000 0 0x1000>, + <0 0x0ac68000 0 0x1000>, + <0 0x0acaf000 0 0x4000>, + <0 0x0acb6000 0 0x4000>, + <0 0x0acc4000 0 0x4000>; reg-names = "csid0", "csid1", "csid2", @@ -4388,7 +4368,7 @@ }; cci: cci@ac4a000 { - compatible = "qcom,sdm845-cci"; + compatible = "qcom,sdm845-cci", "qcom,msm8996-cci"; #address-cells = <1>; #size-cells = <0>; @@ -4444,36 +4424,7 @@ clock-names = "bi_tcxo"; }; - dsi_opp_table: opp-table-dsi { - compatible = "operating-points-v2"; - - opp-19200000 { - opp-hz = /bits/ 64 <19200000>; - required-opps = <&rpmhpd_opp_min_svs>; - }; - - opp-180000000 { - opp-hz = /bits/ 64 <180000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-275000000 { - opp-hz = /bits/ 64 <275000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-328580000 { - opp-hz = /bits/ 64 <328580000>; - required-opps = <&rpmhpd_opp_svs_l1>; - }; - - opp-358000000 { - opp-hz = /bits/ 64 <358000000>; - required-opps = <&rpmhpd_opp_nom>; - }; - }; - - mdss: mdss@ae00000 { + mdss: display-subsystem@ae00000 { compatible = "qcom,sdm845-mdss"; reg = <0 0x0ae00000 0 0x1000>; reg-names = "mdss"; @@ -4577,11 +4528,11 @@ status = "disabled"; compatible = "qcom,sdm845-dp"; - reg = <0 0xae90000 0 0x200>, - <0 0xae90200 0 0x200>, - <0 0xae90400 0 0x600>, - <0 0xae90a00 0 0x600>, - <0 0xae91000 0 0x600>; + reg = <0 0x0ae90000 0 0x200>, + <0 0x0ae90200 0 0x200>, + <0 0x0ae90400 0 0x600>, + <0 0x0ae90a00 0 0x600>, + <0 0x0ae91000 0 0x600>; interrupt-parent = <&mdss>; interrupts = <12>; @@ -4593,7 +4544,6 @@ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", "stream_pixel"; - #clock-cells = <1>; assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; @@ -4619,7 +4569,7 @@ }; }; - dp_opp_table: dp-opp-table { + dp_opp_table: opp-table { compatible = "operating-points-v2"; opp-162000000 { @@ -4645,7 +4595,8 @@ }; dsi0: dsi@ae94000 { - compatible = "qcom,mdss-dsi-ctrl"; + compatible = "qcom,sdm845-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; reg = <0 0x0ae94000 0 0x400>; reg-names = "dsi_ctrl"; @@ -4716,7 +4667,8 @@ }; dsi1: dsi@ae96000 { - compatible = "qcom,mdss-dsi-ctrl"; + compatible = "qcom,sdm845-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; reg = <0 0x0ae96000 0 0x400>; reg-names = "dsi_ctrl"; @@ -4790,7 +4742,7 @@ gpu: gpu@5000000 { compatible = "qcom,adreno-630.2", "qcom,adreno"; - reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>; + reg = <0 0x05000000 0 0x40000>, <0 0x509e000 0 0x10>; reg-names = "kgsl_3d0_reg_memory", "cx_mem"; /* @@ -4860,7 +4812,7 @@ adreno_smmu: iommu@5040000 { compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; - reg = <0 0x5040000 0 0x10000>; + reg = <0 0x05040000 0 0x10000>; #iommu-cells = <1>; #global-interrupts = <2>; interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, @@ -4883,9 +4835,9 @@ gmu: gmu@506a000 { compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu"; - reg = <0 0x506a000 0 0x30000>, - <0 0xb280000 0 0x10000>, - <0 0xb480000 0 0x10000>; + reg = <0 0x0506a000 0 0x30000>, + <0 0x0b280000 0 0x10000>, + <0 0x0b480000 0 0x10000>; reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, @@ -4992,7 +4944,7 @@ #reset-cells = <1>; }; - aoss_qmp: power-controller@c300000 { + aoss_qmp: power-management@c300000 { compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp"; reg = <0 0x0c300000 0 0x400>; interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; @@ -5365,6 +5317,9 @@ }; }; + sound: sound { + }; + thermal-zones { cpu0-thermal { polling-delay-passive = <250>; @@ -5385,7 +5340,7 @@ type = "passive"; }; - cpu0_crit: cpu_crit { + cpu0_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -5412,7 +5367,7 @@ type = "passive"; }; - cpu1_crit: cpu_crit { + cpu1_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -5439,7 +5394,7 @@ type = "passive"; }; - cpu2_crit: cpu_crit { + cpu2_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -5466,7 +5421,7 @@ type = "passive"; }; - cpu3_crit: cpu_crit { + cpu3_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -5493,7 +5448,7 @@ type = "passive"; }; - cpu4_crit: cpu_crit { + cpu4_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -5520,7 +5475,7 @@ type = "passive"; }; - cpu5_crit: cpu_crit { + cpu5_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -5547,7 +5502,7 @@ type = "passive"; }; - cpu6_crit: cpu_crit { + cpu6_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -5574,7 +5529,7 @@ type = "passive"; }; - cpu7_crit: cpu_crit { + cpu7_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -5787,4 +5742,12 @@ }; }; }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; + }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index f32b7445f7c9..7038a0f7c06e 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -94,7 +94,7 @@ }; &adsp_pas { - firmware-name = "qcom/LENOVO/81JL/qcadsp850.mbn"; + firmware-name = "qcom/sdm850/LENOVO/81JL/qcadsp850.mbn"; status = "okay"; }; @@ -306,7 +306,7 @@ }; &cdsp_pas { - firmware-name = "qcom/LENOVO/81JL/qccdsp850.mbn"; + firmware-name = "qcom/sdm850/LENOVO/81JL/qccdsp850.mbn"; status = "okay"; }; @@ -345,7 +345,7 @@ status = "okay"; zap-shader { memory-region = <&gpu_mem>; - firmware-name = "qcom/LENOVO/81JL/qcdxkmsuc850.mbn"; + firmware-name = "qcom/sdm850/LENOVO/81JL/qcdxkmsuc850.mbn"; }; }; @@ -465,8 +465,9 @@ }; &ipa { - status = "okay"; + qcom,gsi-loader = "self"; memory-region = <&ipa_fw_mem>; + status = "okay"; }; &mdss { @@ -475,45 +476,17 @@ &mss_pil { status = "okay"; - firmware-name = "qcom/LENOVO/81JL/qcdsp1v2850.mbn", "qcom/LENOVO/81JL/qcdsp2850.mbn"; + firmware-name = "qcom/sdm850/LENOVO/81JL/qcdsp1v2850.mbn", "qcom/sdm850/LENOVO/81JL/qcdsp2850.mbn"; }; &qup_i2c10_default { - pinconf { - pins = "gpio55", "gpio56"; - drive-strength = <2>; - bias-disable; - }; + drive-strength = <2>; + bias-disable; }; &qup_i2c12_default { - pinmux { - drive-strength = <2>; - bias-disable; - }; -}; - -&qup_uart6_default { - pinmux { - pins = "gpio45", "gpio46", "gpio47", "gpio48"; - function = "qup6"; - }; - - cts { - pins = "gpio45"; - bias-pull-down; - }; - - rts-tx { - pins = "gpio46", "gpio47"; - drive-strength = <2>; - bias-disable; - }; - - rx { - pins = "gpio48"; - bias-pull-up; - }; + drive-strength = <2>; + bias-disable; }; &qupv3_id_0 { @@ -621,13 +594,14 @@ &tlmm { gpio-reserved-ranges = <0 4>, <81 4>; - sn65dsi86_pin_active: sn65dsi86-enable { + sn65dsi86_pin_active: sn65dsi86-enable-state { pins = "gpio96"; + function = "gpio"; drive-strength = <2>; bias-disable; }; - i2c3_hid_active: i2c2-hid-active { + i2c3_hid_active: i2c2-hid-active-state { pins = "gpio37"; function = "gpio"; @@ -636,7 +610,7 @@ drive-strength = <2>; }; - i2c5_hid_active: i2c5-hid-active { + i2c5_hid_active: i2c5-hid-active-state { pins = "gpio125"; function = "gpio"; @@ -645,7 +619,7 @@ drive-strength = <2>; }; - i2c11_hid_active: i2c11-hid-active { + i2c11_hid_active: i2c11-hid-active-state { pins = "gpio92"; function = "gpio"; @@ -654,7 +628,7 @@ drive-strength = <2>; }; - wcd_intr_default: wcd_intr_default { + wcd_intr_default: wcd-intr-default-state { pins = "gpio54"; function = "gpio"; @@ -663,7 +637,7 @@ drive-strength = <2>; }; - lid_pin_active: lid-pin { + lid_pin_active: lid-pin-state { pins = "gpio124"; function = "gpio"; @@ -671,7 +645,7 @@ bias-disable; }; - mode_pin_active: mode-pin { + mode_pin_active: mode-pin-state { pins = "gpio95"; function = "gpio"; @@ -681,6 +655,8 @@ }; &uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart6_4pin>; status = "okay"; bluetooth { @@ -766,10 +742,11 @@ }; &venus { + firmware-name = "qcom/sdm850/LENOVO/81JL/qcvss850.mbn"; status = "okay"; }; -&wcd9340{ +&wcd9340 { pinctrl-0 = <&wcd_intr_default>; pinctrl-names = "default"; clock-names = "extclk"; diff --git a/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts b/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts index daca1e0ad62a..6e361fe184f5 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts @@ -383,9 +383,10 @@ }; &ipa { - status = "okay"; + qcom,gsi-loader = "self"; memory-region = <&ipa_fw_mem>; firmware-name = "qcom/sdm850/samsung/w737/ipa_fws.elf"; + status = "okay"; }; /* No idea why it causes an SError when enabled */ @@ -399,49 +400,18 @@ }; &qup_i2c10_default { - pinconf { - pins = "gpio55", "gpio56"; - drive-strength = <2>; - bias-disable; - }; + drive-strength = <2>; + bias-disable; }; &qup_i2c11_default { - pinconf { - pins = "gpio31", "gpio32"; - drive-strength = <2>; - bias-disable; - }; + drive-strength = <2>; + bias-disable; }; &qup_i2c12_default { - pinmux { - drive-strength = <2>; - bias-disable; - }; -}; - -&qup_uart6_default { - pinmux { - pins = "gpio45", "gpio46", "gpio47", "gpio48"; - function = "qup6"; - }; - - cts { - pins = "gpio45"; - bias-pull-down; - }; - - rts-tx { - pins = "gpio46", "gpio47"; - drive-strength = <2>; - bias-disable; - }; - - rx { - pins = "gpio48"; - bias-pull-up; - }; + drive-strength = <2>; + bias-disable; }; &qupv3_id_0 { @@ -549,59 +519,41 @@ &tlmm { gpio-reserved-ranges = <0 6>, <85 4>; - pen_irq_l: pen-irq-l { - pinmux { - pins = "gpio119"; - function = "gpio"; - }; - - pinconf { - pins = "gpio119"; - bias-disable; - }; + pen_irq_l: pen-irq-l-state { + pins = "gpio119"; + function = "gpio"; + bias-disable; }; - pen_pdct_l: pen-pdct-l { - pinmux { - pins = "gpio124"; - function = "gpio"; - }; - - pinconf { - pins = "gpio124"; - bias-disable; - drive-strength = <2>; - output-high; - }; + pen_pdct_l: pen-pdct-l-state { + pins = "gpio124"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + output-high; }; - pen_rst_l: pen-rst-l { - pinmux { - pins = "gpio21"; - function = "gpio"; - }; - - pinconf { - pins = "gpio21"; - bias-disable; - drive-strength = <2>; - - /* - * The pen driver doesn't currently support - * driving this reset line. By specifying - * output-high here we're relying on the fact - * that this pin has a default pulldown at boot - * (which makes sure the pen was in reset if it - * was powered) and then we set it high here to - * take it out of reset. Better would be if the - * pen driver could control this and we could - * remove "output-high" here. - */ - output-high; - }; + pen_rst_l: pen-rst-l-state { + pins = "gpio21"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + + /* + * The pen driver doesn't currently support + * driving this reset line. By specifying + * output-high here we're relying on the fact + * that this pin has a default pulldown at boot + * (which makes sure the pen was in reset if it + * was powered) and then we set it high here to + * take it out of reset. Better would be if the + * pen driver could control this and we could + * remove "output-high" here. + */ + output-high; }; - wcd_intr_default: wcd_intr_default { + wcd_intr_default: wcd-intr-default-state { pins = "gpio54"; function = "gpio"; @@ -612,6 +564,8 @@ }; &uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart6_4pin>; status = "okay"; bluetooth { @@ -701,7 +655,7 @@ firmware-name = "qcom/sdm850/samsung/w737/qcvss850.mbn"; }; -&wcd9340{ +&wcd9340 { pinctrl-0 = <&wcd_intr_default>; pinctrl-names = "default"; clock-names = "extclk"; diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 572bf04adf90..50cb8a82ecd5 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -296,6 +296,8 @@ rpmcc: clock-controller { compatible = "qcom,rpmcc-sm6115", "qcom,rpmcc"; + clocks = <&xo_board>; + clock-names = "xo"; #clock-cells = <1>; }; @@ -648,7 +650,7 @@ clocks = <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>, - <&xo_board>, + <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GCC_SDCC1_ICE_CORE_CLK>; clock-names = "iface", "core", "xo", "ice"; @@ -669,7 +671,9 @@ <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC2_AHB_CLK>, <&gcc GCC_SDCC2_APPS_CLK>, <&xo_board>; + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "iface", "core", "xo"; pinctrl-0 = <&sdc2_state_on>; @@ -704,6 +708,7 @@ ufs_mem_hc: ufs@4804000 { compatible = "qcom,sm6115-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; reg = <0x04804000 0x3000>, <0x04810000 0x8000>; + reg-names = "std", "ice"; interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; phys = <&ufs_mem_phy_lanes>; phy-names = "ufsphy"; @@ -736,10 +741,10 @@ <0 0>, <0 0>, <37500000 150000000>, - <75000000 300000000>, <0 0>, <0 0>, - <0 0>; + <0 0>, + <75000000 300000000>; status = "disabled"; }; @@ -759,9 +764,9 @@ status = "disabled"; ufs_mem_phy_lanes: phy@4807400 { - reg = <0x4807400 0x098>, - <0x4807600 0x130>, - <0x4807c00 0x16c>; + reg = <0x04807400 0x098>, + <0x04807600 0x130>, + <0x04807c00 0x16c>; #phy-cells = <0>; }; }; @@ -1232,6 +1237,618 @@ #power-domain-cells = <1>; }; + stm@8002000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0x08002000 0x1000>, + <0x0e280000 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + + out-ports { + port { + stm_out: endpoint { + remote-endpoint = <&funnel_in0_in>; + }; + }; + }; + }; + + cti0: cti@8010000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x08010000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + }; + + cti1: cti@8011000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x08011000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + }; + + cti2: cti@8012000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x08012000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + }; + + cti3: cti@8013000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x08013000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + }; + + cti4: cti@8014000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x08014000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + }; + + cti5: cti@8015000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x08015000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + }; + + cti6: cti@8016000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x08016000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + }; + + cti7: cti@8017000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x08017000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + }; + + cti8: cti@8018000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x08018000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + }; + + cti9: cti@8019000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x08019000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + }; + + cti10: cti@801a000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0801a000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + }; + + cti11: cti@801b000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0801b000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + }; + + cti12: cti@801c000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0801c000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + }; + + cti13: cti@801d000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0801d000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + }; + + cti14: cti@801e000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0801e000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + }; + + cti15: cti@801f000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0801f000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + }; + + replicator@8046000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x08046000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + + out-ports { + port { + replicator_out: endpoint { + remote-endpoint = <&etr_in>; + }; + }; + }; + + in-ports { + port { + replicator_in: endpoint { + remote-endpoint = <&etf_out>; + }; + }; + }; + }; + + etf@8047000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x08047000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + + in-ports { + port { + etf_in: endpoint { + remote-endpoint = <&merge_funnel_out>; + }; + }; + }; + + out-ports { + port { + etf_out: endpoint { + remote-endpoint = <&replicator_in>; + }; + }; + }; + }; + + etr@8048000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x08048000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + + in-ports { + port { + etr_in: endpoint { + remote-endpoint = <&replicator_out>; + }; + }; + }; + }; + + funnel@8041000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x08041000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + + out-ports { + port { + funnel_in0_out: endpoint { + remote-endpoint = <&merge_funnel_in0>; + }; + }; + }; + + in-ports { + port { + funnel_in0_in: endpoint { + remote-endpoint = <&stm_out>; + }; + }; + }; + }; + + funnel@8042000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x08042000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + + out-ports { + port { + funnel_in1_out: endpoint { + remote-endpoint = <&merge_funnel_in1>; + }; + }; + }; + + in-ports { + port { + funnel_in1_in: endpoint { + remote-endpoint = <&funnel_apss1_out>; + }; + }; + }; + }; + + funnel@8045000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x08045000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + + out-ports { + port { + merge_funnel_out: endpoint { + remote-endpoint = <&etf_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + merge_funnel_in0: endpoint { + remote-endpoint = <&funnel_in0_out>; + }; + }; + + port@1 { + reg = <1>; + merge_funnel_in1: endpoint { + remote-endpoint = <&funnel_in1_out>; + }; + }; + }; + }; + + etm@9040000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x09040000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + cpu = <&CPU0>; + + status = "disabled"; + + out-ports { + port { + etm0_out: endpoint { + remote-endpoint = <&funnel_apss0_in0>; + }; + }; + }; + }; + + etm@9140000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x09140000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + cpu = <&CPU1>; + + status = "disabled"; + + out-ports { + port { + etm1_out: endpoint { + remote-endpoint = <&funnel_apss0_in1>; + }; + }; + }; + }; + + etm@9240000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x09240000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + cpu = <&CPU2>; + + status = "disabled"; + + out-ports { + port { + etm2_out: endpoint { + remote-endpoint = <&funnel_apss0_in2>; + }; + }; + }; + }; + + etm@9340000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x09340000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + cpu = <&CPU3>; + + status = "disabled"; + + out-ports { + port { + etm3_out: endpoint { + remote-endpoint = <&funnel_apss0_in3>; + }; + }; + }; + }; + + etm@9440000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x09440000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + cpu = <&CPU4>; + + status = "disabled"; + + out-ports { + port { + etm4_out: endpoint { + remote-endpoint = <&funnel_apss0_in4>; + }; + }; + }; + }; + + etm@9540000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x09540000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + cpu = <&CPU5>; + + status = "disabled"; + + out-ports { + port { + etm5_out: endpoint { + remote-endpoint = <&funnel_apss0_in5>; + }; + }; + }; + }; + + etm@9640000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x09640000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + cpu = <&CPU6>; + + status = "disabled"; + + out-ports { + port { + etm6_out: endpoint { + remote-endpoint = <&funnel_apss0_in6>; + }; + }; + }; + }; + + etm@9740000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x09740000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + cpu = <&CPU7>; + + status = "disabled"; + + out-ports { + port { + etm7_out: endpoint { + remote-endpoint = <&funnel_apss0_in7>; + }; + }; + }; + }; + + funnel@9800000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x09800000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + + out-ports { + port { + funnel_apss0_out: endpoint { + remote-endpoint = <&funnel_apss1_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_apss0_in0: endpoint { + remote-endpoint = <&etm0_out>; + }; + }; + + port@1 { + reg = <1>; + funnel_apss0_in1: endpoint { + remote-endpoint = <&etm1_out>; + }; + }; + + port@2 { + reg = <2>; + funnel_apss0_in2: endpoint { + remote-endpoint = <&etm2_out>; + }; + }; + + port@3 { + reg = <3>; + funnel_apss0_in3: endpoint { + remote-endpoint = <&etm3_out>; + }; + }; + + port@4 { + reg = <4>; + funnel_apss0_in4: endpoint { + remote-endpoint = <&etm4_out>; + }; + }; + + port@5 { + reg = <5>; + funnel_apss0_in5: endpoint { + remote-endpoint = <&etm5_out>; + }; + }; + + port@6 { + reg = <6>; + funnel_apss0_in6: endpoint { + remote-endpoint = <&etm6_out>; + }; + }; + + port@7 { + reg = <7>; + funnel_apss0_in7: endpoint { + remote-endpoint = <&etm7_out>; + }; + }; + }; + }; + + funnel@9810000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x09810000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + + out-ports { + port { + funnel_apss1_out: endpoint { + remote-endpoint = <&funnel_in1_in>; + }; + }; + }; + + in-ports { + port { + funnel_apss1_in: endpoint { + remote-endpoint = <&funnel_apss0_out>; + }; + }; + }; + }; + apps_smmu: iommu@c600000 { compatible = "qcom,sm6115-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg = <0x0c600000 0x80000>; @@ -1415,6 +2032,370 @@ }; }; + thermal-zones { + mapss-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 0>; + + trips { + trip-point0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cdsp-hvx-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 1>; + + trips { + trip-point0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + wlan-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 2>; + + trips { + trip-point0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + camera-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 3>; + + trips { + trip-point0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + video-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 4>; + + trips { + trip-point0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 5>; + + trips { + trip-point0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cpu4-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 6>; + + trips { + cpu4_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu5-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 7>; + + trips { + cpu5_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu6-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 8>; + + trips { + cpu6_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu7-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 9>; + + trips { + cpu7_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu45-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 10>; + + trips { + cpu45_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu45_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu45_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu67-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 11>; + + trips { + cpu67_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu67_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu67_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu0123-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 12>; + + trips { + cpu0123_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu0123_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu0123_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + modem0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 13>; + + trips { + trip-point0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + display-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 14>; + + trips { + trip-point0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + gpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 15>; + + trips { + trip-point0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, diff --git a/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts b/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts new file mode 100644 index 000000000000..4ce2d905d70e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts @@ -0,0 +1,289 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2022 Linaro Limited + */ + +/dts-v1/; + +#include "sm6115.dtsi" +#include "pm6125.dtsi" + +/ { + model = "Lenovo Tab P11"; + compatible = "lenovo,j606f", "qcom,sm6115p", "qcom,sm6115"; + chassis-type = "tablet"; + + /* required for bootloader to select correct board */ + qcom,msm-id = <445 0x10000>, <420 0x10000>; + qcom,board-id = <34 3>; + + aliases { + mmc0 = &sdhc_2; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer0: framebuffer@5c000000 { + compatible = "simple-framebuffer"; + reg = <0 0x5c000000 0 (2000 * 1200 * 4)>; + width = <1200>; + height = <2000>; + stride = <(1200 * 4)>; + format = "a8r8g8b8"; + clocks = <&gcc GCC_DISP_HF_AXI_CLK>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&vol_up_n>; + + key-volume-up { + label = "Volume Up"; + linux,code = <KEY_VOLUMEUP>; + gpios = <&pm6125_gpios 5 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + gpio-key,wakeup; + }; + }; +}; + +&dispcc { + /* HACK: disable until a panel driver is ready to retain simplefb */ + status = "disabled"; +}; + +&pm6125_gpios { + vol_up_n: vol-up-n-state { + pins = "gpio5"; + function = "normal"; + power-source = <0>; + bias-pull-up; + input-enable; + }; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; +}; + +&rpm_requests { + regulators-0 { + compatible = "qcom,rpm-pm6125-regulators"; + + pm6125_s6: s6 { + regulator-min-microvolt = <304000>; + regulator-max-microvolt = <1456000>; + }; + + pm6125_s7: s7 { + regulator-min-microvolt = <1280000>; + regulator-max-microvolt = <2080000>; + }; + + pm6125_s8: s8 { + regulator-min-microvolt = <1064000>; + regulator-max-microvolt = <1304000>; + }; + + pm6125_l1: l1 { + regulator-min-microvolt = <952000>; + regulator-max-microvolt = <1152000>; + }; + + pm6125_l4: l4 { + regulator-min-microvolt = <488000>; + regulator-max-microvolt = <1000000>; + }; + + pm6125_l5: l5 { + regulator-min-microvolt = <1648000>; + /* 3.056V capped to 2.96V for SDHCI */ + regulator-max-microvolt = <2960000>; + regulator-allow-set-load; + /* Broken hw, this one can't be turned off or SDHCI will break! */ + regulator-always-on; + }; + + pm6125_l6: l6 { + regulator-min-microvolt = <576000>; + regulator-max-microvolt = <656000>; + }; + + pm6125_l7: l7 { + /* 1.2V-1.304V fixed at 1.256V for SDHCI bias */ + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1256000>; + /* + * TODO: SDHCI seems to also work with this one turned off, however + * there exists a possibility that it may not work with some very + * specific SDCard types, perhaps validating this against a wide + * range of models could rule that out, saving some power would + * certainly be nice.. + */ + regulator-always-on; + }; + + pm6125_l8: l8 { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <728000>; + }; + + pm6125_l9: l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + }; + + pm6125_l10: l10 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1904000>; + }; + + pm6125_l11: l11 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1952000>; + }; + + pm6125_l12: l12 { + regulator-min-microvolt = <1624000>; + regulator-max-microvolt = <1984000>; + }; + + pm6125_l13: l13 { + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <1952000>; + }; + + pm6125_l14: l14 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1904000>; + }; + + pm6125_l15: l15 { + regulator-min-microvolt = <2920000>; + regulator-max-microvolt = <3232000>; + }; + + pm6125_l16: l16 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1904000>; + }; + + pm6125_l17: l17 { + regulator-min-microvolt = <1152000>; + regulator-max-microvolt = <1384000>; + }; + + pm6125_l18: l18 { + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1312000>; + }; + + pm6125_l19: l19 { + regulator-min-microvolt = <1624000>; + regulator-max-microvolt = <3304000>; + }; + + pm6125_l20: l20 { + regulator-min-microvolt = <1624000>; + regulator-max-microvolt = <3304000>; + }; + + pm6125_l21: l21 { + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3600000>; + }; + + pm6125_l22: l22 { + regulator-min-microvolt = <2952000>; + /* 3.304V capped to 2.96V for SDHCI */ + regulator-max-microvolt = <2960000>; + regulator-allow-set-load; + /* Broken hw, this one can't be turned off or SDHCI will break! */ + regulator-always-on; + }; + + pm6125_l23: l23 { + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3400000>; + }; + + pm6125_l24: l24 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <3600000>; + }; + }; +}; + +&sdhc_2 { + cd-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_state_on &sdc2_gate_pin>; + pinctrl-1 = <&sdc2_state_off>; + vmmc-supply = <&pm6125_l22>; + vqmmc-supply = <&pm6125_l5>; + no-sdio; + no-mmc; + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32764>; +}; + +&tlmm { + gpio-reserved-ranges = <14 4>; + + /* + * This is a wholly undocumented pin (other than a single vague "pwr-gpios" reference) + * that needs to be toggled for the SD Card slot to work properly.. + */ + sdc2_gate_pin: sdc2-gate-state { + pins = "gpio45"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + output-high; + }; +}; + +&ufs_mem_hc { + vcc-supply = <&pm6125_l24>; + vcc-max-microamp = <600000>; + vccq2-supply = <&pm6125_l11>; + vccq2-max-microamp = <600000>; + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&pm6125_l4>; + vdda-pll-supply = <&pm6125_l12>; + vddp-ref-clk-supply = <&pm6125_l18>; + status = "okay"; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_hsphy { + vdd-supply = <&pm6125_l4>; + vdda-pll-supply = <&pm6125_l12>; + vdda-phy-dpdm-supply = <&pm6125_l15>; + status = "okay"; +}; + +&xo_board { + clock-frequency = <19200000>; +}; diff --git a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts index 0de6c5b7f742..b22b3f9a910d 100644 --- a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts +++ b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts @@ -20,6 +20,11 @@ compatible = "sony,pdx201", "qcom,sm6125"; chassis-type = "handset"; + aliases { + mmc0 = &sdhc_1; /* SDC1 eMMC slot */ + mmc1 = &sdhc_2; /* SDC2 SD card slot */ + }; + chosen { #address-cells = <2>; #size-cells = <2>; @@ -41,21 +46,22 @@ }; gpio-keys { - status = "okay"; compatible = "gpio-keys"; - autorepeat; - key-vol-dn { + pinctrl-0 = <&vol_down_n>; + pinctrl-names = "default"; + + key-volume-down { label = "Volume Down"; gpios = <&tlmm 47 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; linux,code = <KEY_VOLUMEDOWN>; - gpio-key,wakeup; debounce-interval = <15>; + linux,can-disable; + wakeup-source; }; }; - reserved_memory { + reserved-memory { #address-cells = <2>; #size-cells = <2>; debug_mem: memory@ffb00000 { @@ -141,10 +147,38 @@ }; }; +&gpi_dma0 { + status = "okay"; +}; + &hsusb_phy1 { + vdd-supply = <&pm6125_l7>; + vdda-pll-supply = <&pm6125_l10>; + vdda-phy-dpdm-supply = <&pm6125_l15>; status = "okay"; }; +&i2c1 { + clock-frequency = <400000>; + status = "okay"; + + /* NXP PN553 NFC @ 28 */ +}; + +&i2c2 { + clock-frequency = <400000>; + status = "okay"; + + /* Samsung touchscreen @ 48 */ +}; + +&i2c3 { + clock-frequency = <1000000>; + status = "okay"; + + /* Cirrus Logic CS35L41 boosted audio amplifier @ 40 */ +}; + &pm6125_adc { pinctrl-names = "default"; pinctrl-0 = <&camera_flash_therm &emmc_ufs_therm &rf_pa1_therm>; @@ -217,7 +251,7 @@ }; }; -&pm6125_gpio { +&pm6125_gpios { camera_flash_therm: camera-flash-therm-state { pins = "gpio3"; function = PMIC_GPIO_FUNC_NORMAL; @@ -246,6 +280,153 @@ linux,code = <KEY_VOLUMEUP>; }; +&rpm_requests { + regulators-0 { + compatible = "qcom,rpm-pm6125-regulators"; + + vdd_l2_l3_l4-supply = <&pm6125_l7>; + vdd_l5_l15_l19_l20_l21_l22-supply = <&pm6125_l10>; + + /* + * S3/S4 is VDD_CX + * S5 is VDD_MX/WCSS_MX + */ + + pm6125_s6: s6 { + regulator-min-microvolt = <936000>; + regulator-max-microvolt = <1422000>; + }; + + pm6125_l1: l1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1256000>; + }; + + pm6125_l2: l2 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1056000>; + }; + + pm6125_l3: l3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1064000>; + }; + + pm6125_l4: l4 { + regulator-min-microvolt = <872000>; + regulator-max-microvolt = <976000>; + }; + + pm6125_l5: l5 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + }; + + pm6125_l6: l6 { + regulator-min-microvolt = <576000>; + regulator-max-microvolt = <656000>; + }; + + pm6125_l7: l7 { + regulator-min-microvolt = <872000>; + regulator-max-microvolt = <976000>; + }; + + pm6125_l8: l8 { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <728000>; + }; + + pm6125_l9: l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1896000>; + }; + + pm6125_l10: l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1896000>; + }; + + pm6125_l11: l11 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-allow-set-load; + }; + + pm6125_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1996000>; + }; + + pm6125_l13: l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1832000>; + }; + + pm6125_l14: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1904000>; + }; + + pm6125_l15: l15 { + regulator-min-microvolt = <3104000>; + regulator-max-microvolt = <3232000>; + }; + + pm6125_l16: l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1904000>; + }; + + pm6125_l17: l17 { + regulator-min-microvolt = <1248000>; + regulator-max-microvolt = <1304000>; + }; + + pm6125_l18: l18 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1264000>; + }; + + pm6125_l19: l19 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <2952000>; + }; + + pm6125_l20: l20 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <2952000>; + }; + + pm6125_l21: l21 { + regulator-min-microvolt = <2600000>; + regulator-max-microvolt = <2856000>; + }; + + pm6125_l22: l22 { + regulator-min-microvolt = <2944000>; + regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + }; + + pm6125_l23: l23 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3400000>; + }; + + pm6125_l24: l24 { + regulator-min-microvolt = <2944000>; + regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + }; + }; +}; + +&qupv3_id_0 { + status = "okay"; +}; + &sdc2_off_state { sd-cd-pins { pins = "gpio98"; @@ -265,11 +446,30 @@ }; &sdhc_1 { + vmmc-supply = <&pm6125_l24>; + vqmmc-supply = <&pm6125_l11>; + status = "okay"; +}; + +&sdhc_2 { + cd-gpios = <&tlmm 98 GPIO_ACTIVE_HIGH>; + vmmc-supply = <&pm6125_l22>; + vqmmc-supply = <&pm6125_l5>; + no-sdio; + no-mmc; status = "okay"; }; &tlmm { gpio-reserved-ranges = <22 2>, <28 6>; + + vol_down_n: vol-down-n-state { + pins = "gpio47"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + input-enable; + }; }; &usb3 { diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index 7e25a4f85594..65033227718a 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -5,6 +5,7 @@ #include <dt-bindings/clock/qcom,gcc-sm6125.h> #include <dt-bindings/clock/qcom,rpmcc.h> +#include <dt-bindings/dma/qcom-gpi.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/qcom-rpmpd.h> @@ -45,6 +46,7 @@ next-level-cache = <&L2_0>; L2_0: l2-cache { compatible = "cache"; + cache-level = <2>; }; }; @@ -84,6 +86,7 @@ next-level-cache = <&L2_1>; L2_1: l2-cache { compatible = "cache"; + cache-level = <2>; }; }; @@ -425,6 +428,230 @@ bias-pull-up; }; }; + + qup_i2c0_default: qup-i2c0-default-state { + pins = "gpio0", "gpio1"; + function = "qup00"; + drive-strength = <2>; + bias-disable; + }; + + qup_i2c0_sleep: qup-i2c0-sleep-state { + pins = "gpio0", "gpio1"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c1_default: qup-i2c1-default-state { + pins = "gpio4", "gpio5"; + function = "qup01"; + drive-strength = <2>; + bias-disable; + }; + + qup_i2c1_sleep: qup-i2c1-sleep-state { + pins = "gpio4", "gpio5"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c2_default: qup-i2c2-default-state { + pins = "gpio6", "gpio7"; + function = "qup02"; + drive-strength = <2>; + bias-disable; + }; + + qup_i2c2_sleep: qup-i2c2-sleep-state { + pins = "gpio6", "gpio7"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c3_default: qup-i2c3-default-state { + pins = "gpio14", "gpio15"; + function = "qup03"; + drive-strength = <2>; + bias-disable; + }; + + qup_i2c3_sleep: qup-i2c3-sleep-state { + pins = "gpio14", "gpio15"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c4_default: qup-i2c4-default-state { + pins = "gpio16", "gpio17"; + function = "qup04"; + drive-strength = <2>; + bias-disable; + }; + + qup_i2c4_sleep: qup-i2c4-sleep-state { + pins = "gpio16", "gpio17"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c5_default: qup-i2c5-default-state { + pins = "gpio22", "gpio23"; + function = "qup10"; + drive-strength = <2>; + bias-disable; + }; + + qup_i2c5_sleep: qup-i2c5-sleep-state { + pins = "gpio22", "gpio23"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c6_default: qup-i2c6-default-state { + pins = "gpio30", "gpio31"; + function = "qup11"; + drive-strength = <2>; + bias-disable; + }; + + qup_i2c6_sleep: qup-i2c6-sleep-state { + pins = "gpio30", "gpio31"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c7_default: qup-i2c7-default-state { + pins = "gpio28", "gpio29"; + function = "qup12"; + drive-strength = <2>; + bias-disable; + }; + + qup_i2c7_sleep: qup-i2c7-sleep-state { + pins = "gpio28", "gpio29"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c8_default: qup-i2c8-default-state { + pins = "gpio18", "gpio19"; + function = "qup13"; + drive-strength = <2>; + bias-disable; + }; + + qup_i2c8_sleep: qup-i2c8-sleep-state { + pins = "gpio18", "gpio19"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c9_default: qup-i2c9-default-state { + pins = "gpio10", "gpio11"; + function = "qup14"; + drive-strength = <2>; + bias-disable; + }; + + qup_i2c9_sleep: qup-i2c9-sleep-state { + pins = "gpio10", "gpio11"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi0_default: qup-spi0-default-state { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "qup00"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi0_sleep: qup-spi0-sleep-state { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "gpio"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi2_default: qup-spi2-default-state { + pins = "gpio6", "gpio7", "gpio8", "gpio9"; + function = "qup02"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi2_sleep: qup-spi2-sleep-state { + pins = "gpio6", "gpio7", "gpio8", "gpio9"; + function = "gpio"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi5_default: qup-spi5-default-state { + pins = "gpio22", "gpio23", "gpio24", "gpio25"; + function = "qup10"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi5_sleep: qup-spi5-sleep-state { + pins = "gpio22", "gpio23", "gpio24", "gpio25"; + function = "gpio"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi6_default: qup-spi6-default-state { + pins = "gpio30", "gpio31", "gpio32", "gpio33"; + function = "qup11"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi6_sleep: qup-spi6-sleep-state { + pins = "gpio30", "gpio31", "gpio32", "gpio33"; + function = "gpio"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi8_default: qup-spi8-default-state { + pins = "gpio18", "gpio19", "gpio20", "gpio21"; + function = "qup13"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi8_sleep: qup-spi8-sleep-state { + pins = "gpio18", "gpio19", "gpio20", "gpio21"; + function = "gpio"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi9_default: qup-spi9-default-state { + pins = "gpio10", "gpio11", "gpio12", "gpio13"; + function = "qup14"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi9_sleep: qup-spi9-sleep-state { + pins = "gpio10", "gpio11", "gpio12", "gpio13"; + function = "gpio"; + drive-strength = <6>; + bias-disable; + }; }; gcc: clock-controller@1400000 { @@ -442,9 +669,9 @@ reg = <0x01613000 0x180>; #phy-cells = <0>; - clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, - <&gcc GCC_AHB2PHY_USB_CLK>; - clock-names = "ref", "cfg_ahb"; + clocks = <&gcc GCC_AHB2PHY_USB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "cfg_ahb", "ref"; resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; status = "disabled"; @@ -468,6 +695,7 @@ <&gcc GCC_SDCC1_APPS_CLK>, <&xo_board>; clock-names = "iface", "core", "xo"; + iommus = <&apps_smmu 0x160 0x0>; power-domains = <&rpmpd SM6125_VDDCX>; @@ -494,6 +722,7 @@ <&gcc GCC_SDCC2_APPS_CLK>, <&xo_board>; clock-names = "iface", "core", "xo"; + iommus = <&apps_smmu 0x180 0x0>; pinctrl-0 = <&sdc2_on_state>; pinctrl-1 = <&sdc2_off_state>; @@ -508,6 +737,340 @@ status = "disabled"; }; + gpi_dma0: dma-controller@4a00000 { + compatible = "qcom,sm6125-gpi-dma", "qcom,sdm845-gpi-dma"; + reg = <0x04a00000 0x60000>; + interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; + dma-channels = <8>; + dma-channel-mask = <0x1f>; + iommus = <&apps_smmu 0x136 0x0>; + #dma-cells = <3>; + status = "disabled"; + }; + + qupv3_id_0: geniqup@4ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x04ac0000 0x2000>; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + clock-names = "m-ahb", "s-ahb"; + iommus = <&apps_smmu 0x123 0x0>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + i2c0: i2c@4a80000 { + compatible = "qcom,geni-i2c"; + reg = <0x04a80000 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_i2c0_default>; + pinctrl-1 = <&qup_i2c0_sleep>; + pinctrl-names = "default", "sleep"; + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi0: spi@4a80000 { + compatible = "qcom,geni-spi"; + reg = <0x04a80000 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_spi0_default>; + pinctrl-1 = <&qup_spi0_sleep>; + pinctrl-names = "default", "sleep"; + dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@4a84000 { + compatible = "qcom,geni-i2c"; + reg = <0x04a84000 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_i2c1_default>; + pinctrl-1 = <&qup_i2c1_sleep>; + pinctrl-names = "default", "sleep"; + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@4a88000 { + compatible = "qcom,geni-i2c"; + reg = <0x04a88000 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_i2c2_default>; + pinctrl-1 = <&qup_i2c2_sleep>; + pinctrl-names = "default", "sleep"; + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@4a88000 { + compatible = "qcom,geni-spi"; + reg = <0x04a88000 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_spi2_default>; + pinctrl-1 = <&qup_spi2_sleep>; + pinctrl-names = "default", "sleep"; + dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, + <&gpi_dma0 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@4a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0x04a8c000 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_i2c3_default>; + pinctrl-1 = <&qup_i2c3_sleep>; + pinctrl-names = "default", "sleep"; + dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, + <&gpi_dma0 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@4a90000 { + compatible = "qcom,geni-i2c"; + reg = <0x04a90000 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_i2c4_default>; + pinctrl-1 = <&qup_i2c4_sleep>; + pinctrl-names = "default", "sleep"; + dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, + <&gpi_dma0 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + gpi_dma1: dma-controller@4c00000 { + compatible = "qcom,sm6125-gpi-dma", "qcom,sdm845-gpi-dma"; + reg = <0x04c00000 0x60000>; + interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; + dma-channels = <8>; + dma-channel-mask = <0x0f>; + iommus = <&apps_smmu 0x156 0x0>; + #dma-cells = <3>; + status = "disabled"; + }; + + qupv3_id_1: geniqup@4cc0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x04cc0000 0x2000>; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + clock-names = "m-ahb", "s-ahb"; + iommus = <&apps_smmu 0x143 0x0>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + i2c5: i2c@4c80000 { + compatible = "qcom,geni-i2c"; + reg = <0x04c80000 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_i2c5_default>; + pinctrl-1 = <&qup_i2c5_sleep>; + pinctrl-names = "default", "sleep"; + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi5: spi@4c80000 { + compatible = "qcom,geni-spi"; + reg = <0x04c80000 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_spi5_default>; + pinctrl-1 = <&qup_spi5_sleep>; + pinctrl-names = "default", "sleep"; + dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, + <&gpi_dma1 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c6: i2c@4c84000 { + compatible = "qcom,geni-i2c"; + reg = <0x04c84000 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_i2c6_default>; + pinctrl-1 = <&qup_i2c6_sleep>; + pinctrl-names = "default", "sleep"; + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi6: spi@4c84000 { + compatible = "qcom,geni-spi"; + reg = <0x04c84000 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_spi6_default>; + pinctrl-1 = <&qup_spi6_sleep>; + pinctrl-names = "default", "sleep"; + dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, + <&gpi_dma1 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c7: i2c@4c88000 { + compatible = "qcom,geni-i2c"; + reg = <0x04c88000 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_i2c7_default>; + pinctrl-1 = <&qup_i2c7_sleep>; + pinctrl-names = "default", "sleep"; + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c8: i2c@4c8c000 { + compatible = "qcom,geni-i2c"; + reg = <0x04c8c000 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_i2c8_default>; + pinctrl-1 = <&qup_i2c8_sleep>; + pinctrl-names = "default", "sleep"; + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, + <&gpi_dma1 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi8: spi@4c8c000 { + compatible = "qcom,geni-spi"; + reg = <0x04c8c000 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_spi8_default>; + pinctrl-1 = <&qup_spi8_sleep>; + pinctrl-names = "default", "sleep"; + dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, + <&gpi_dma1 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c9: i2c@4c90000 { + compatible = "qcom,geni-i2c"; + reg = <0x04c90000 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_i2c9_default>; + pinctrl-1 = <&qup_i2c9_sleep>; + pinctrl-names = "default", "sleep"; + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, + <&gpi_dma1 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi9: spi@4c90000 { + compatible = "qcom,geni-spi"; + reg = <0x04c90000 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_spi9_default>; + pinctrl-1 = <&qup_spi9_sleep>; + pinctrl-names = "default", "sleep"; + dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, + <&gpi_dma1 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + usb3: usb@4ef8800 { compatible = "qcom,sm6125-dwc3", "qcom,dwc3"; reg = <0x04ef8800 0x400>; @@ -540,6 +1103,7 @@ compatible = "snps,dwc3"; reg = <0x04e00000 0xcd00>; interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&apps_smmu 0x100 0x0>; phys = <&hsusb_phy1>; phy-names = "usb2-phy"; snps,dis_u2_susphy_quirk; @@ -573,6 +1137,79 @@ cell-index = <0>; }; + apps_smmu: iommu@c600000 { + compatible = "qcom,sm6125-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg = <0xc600000 0x80000>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; + + #global-interrupts = <1>; + #iommu-cells = <2>; + }; + apcs_glb: mailbox@f111000 { compatible = "qcom,sm6125-apcs-hmss-global"; reg = <0x0f111000 0x1000>; diff --git a/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts b/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts index 94f77d376662..4916d0db5b47 100644 --- a/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts +++ b/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts @@ -35,10 +35,10 @@ gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_state>; + pinctrl-0 = <&vol_down_n>; key-volume-down { - label = "volume_down"; + label = "Volume Down"; linux,code = <KEY_VOLUMEDOWN>; gpios = <&pm6350_gpios 2 GPIO_ACTIVE_LOW>; }; @@ -305,14 +305,12 @@ }; &pm6350_gpios { - gpio_keys_state: gpio-keys-state { - key-volume-down-pins { - pins = "gpio2"; - function = PMIC_GPIO_FUNC_NORMAL; - power-source = <0>; - bias-disable; - input-enable; - }; + vol_down_n: vol-down-n-state { + pins = "gpio2"; + function = PMIC_GPIO_FUNC_NORMAL; + power-source = <0>; + bias-disable; + input-enable; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 43324bf291c3..8224adb99948 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -8,6 +8,8 @@ #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/dma/qcom-gpi.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interconnect/qcom,icc.h> +#include <dt-bindings/interconnect/qcom,osm-l3.h> #include <dt-bindings/interconnect/qcom,sm6350.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/mailbox/qcom-ipcc.h> @@ -47,12 +49,18 @@ dynamic-power-coefficient = <100>; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY + &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; L2_0: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; L3_0: l3-cache { compatible = "cache"; + cache-level = <3>; }; }; }; @@ -66,9 +74,14 @@ dynamic-power-coefficient = <100>; next-level-cache = <&L2_100>; qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY + &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; L2_100: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -82,9 +95,14 @@ dynamic-power-coefficient = <100>; next-level-cache = <&L2_200>; qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY + &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; L2_200: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -98,9 +116,14 @@ dynamic-power-coefficient = <100>; next-level-cache = <&L2_300>; qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY + &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; L2_300: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -114,9 +137,14 @@ dynamic-power-coefficient = <100>; next-level-cache = <&L2_400>; qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY + &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; L2_400: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -130,9 +158,14 @@ dynamic-power-coefficient = <100>; next-level-cache = <&L2_500>; qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY + &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; L2_500: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; @@ -147,9 +180,14 @@ dynamic-power-coefficient = <703>; next-level-cache = <&L2_600>; qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu6_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY + &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; L2_600: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -163,9 +201,14 @@ dynamic-power-coefficient = <703>; next-level-cache = <&L2_700>; qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu6_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY + &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; L2_700: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -220,6 +263,112 @@ reg = <0x0 0x80000000 0x0 0x0>; }; + cpu0_opp_table: opp-table-cpu0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + /* DDR: 4-wide, 2 channels, double data rate, L3: 16-wide, 2 channels */ + opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>; + }; + + opp-576000000 { + opp-hz = /bits/ 64 <576000000>; + opp-peak-kBps = <(547000 * 4 * 2 * 2) (556800 * 16 * 2)>; + }; + + opp-768000000 { + opp-hz = /bits/ 64 <768000000>; + opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>; + }; + + opp-1017600000 { + opp-hz = /bits/ 64 <1017600000>; + opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>; + }; + + opp-1248000000 { + opp-hz = /bits/ 64 <1248000000>; + opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>; + }; + + opp-1324800000 { + opp-hz = /bits/ 64 <1324800000>; + opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1286400 * 16 * 2)>; + }; + + opp-1516800000 { + opp-hz = /bits/ 64 <1516800000>; + opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1459200 * 16 * 2)>; + }; + + opp-1612800000 { + opp-hz = /bits/ 64 <1612800000>; + opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; + }; + + opp-1708800000 { + opp-hz = /bits/ 64 <1708800000>; + opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; + }; + }; + + cpu6_opp_table: opp-table-cpu6 { + compatible = "operating-points-v2"; + opp-shared; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>; + }; + + opp-787200000 { + opp-hz = /bits/ 64 <787200000>; + opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>; + }; + + opp-979200000 { + opp-hz = /bits/ 64 <979200000>; + opp-peak-kBps = <(768000 * 4 * 2 * 2) (940800 * 16 * 2)>; + }; + + opp-1036800000 { + opp-hz = /bits/ 64 <1036800000>; + opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>; + }; + + opp-1248000000 { + opp-hz = /bits/ 64 <1248000000>; + opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>; + }; + + opp-1401600000 { + opp-hz = /bits/ 64 <1401600000>; + opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1401600 * 16 * 2)>; + }; + + opp-1555200000 { + opp-hz = /bits/ 64 <1555200000>; + opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; + }; + + opp-1766400000 { + opp-hz = /bits/ 64 <1766400000>; + opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; + }; + + opp-1900800000 { + opp-hz = /bits/ 64 <1900800000>; + opp-peak-kBps = <(1804000 * 4 * 2 * 2) (1459200 * 16 * 2)>; + }; + + opp-2073600000 { + opp-hz = /bits/ 64 <2073600000>; + opp-peak-kBps = <(2092000 * 4 * 2 * 2) (1459200 * 16 * 2)>; + }; + }; + pmu { compatible = "arm,armv8-pmuv3"; interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_LOW>; @@ -342,13 +491,12 @@ }; ramoops: ramoops@ffc00000 { - compatible = "removed-dma-pool", "ramoops"; - reg = <0 0xffc00000 0 0x00100000>; + compatible = "ramoops"; + reg = <0 0xffc00000 0 0x100000>; record-size = <0x1000>; console-size = <0x40000>; - ftrace-size = <0x0>; msg-size = <0x20000 0x20000>; - cc-size = <0x0>; + ecc-size = <16>; no-map; }; @@ -432,7 +580,17 @@ modem_smp2p_in: slave-kernel { qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + ipa_smp2p_out: ipa-ap-to-modem { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + ipa_smp2p_in: ipa-modem-to-ap { + qcom,entry-name = "ipa"; interrupt-controller; #interrupt-cells = <2>; }; @@ -544,7 +702,7 @@ qupv3_id_0: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; - reg = <0x0 0x8c0000 0x0 0x2000>; + reg = <0x0 0x008c0000 0x0 0x2000>; clock-names = "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; @@ -617,7 +775,7 @@ qupv3_id_1: geniqup@9c0000 { compatible = "qcom,geni-se-qup"; - reg = <0x0 0x9c0000 0x0 0x2000>; + reg = <0x0 0x009c0000 0x0 0x2000>; clock-names = "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; @@ -689,7 +847,7 @@ uart9: serial@98c000 { compatible = "qcom,geni-debug-uart"; - reg = <0 0x98c000 0 0x4000>; + reg = <0 0x0098c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; pinctrl-names = "default"; @@ -847,6 +1005,43 @@ }; }; + ipa: ipa@1e40000 { + compatible = "qcom,sm6350-ipa"; + + iommus = <&apps_smmu 0x440 0x0>, + <&apps_smmu 0x442 0x0>; + reg = <0 0x01e40000 0 0x8000>, + <0 0x01e50000 0 0x3000>, + <0 0x01e04000 0 0x23000>; + reg-names = "ipa-reg", + "ipa-shared", + "gsi"; + + interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, + <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ipa", + "gsi", + "ipa-clock-query", + "ipa-setup-ready"; + + clocks = <&rpmhcc RPMH_IPA_CLK>; + clock-names = "core"; + + interconnects = <&aggre2_noc MASTER_IPA 0 &clk_virt SLAVE_EBI_CH0 0>, + <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_OCIMEM 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_IPA_CFG 0>; + interconnect-names = "memory", "imem", "config"; + + qcom,smem-states = <&ipa_smp2p_out 0>, + <&ipa_smp2p_out 1>; + qcom,smem-state-names = "ipa-clock-enabled-valid", + "ipa-clock-enabled"; + + status = "disabled"; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x40000>; @@ -1272,7 +1467,7 @@ #thermal-sensor-cells = <1>; }; - aoss_qmp: power-controller@c300000 { + aoss_qmp: power-management@c300000 { compatible = "qcom,sm6350-aoss-qmp", "qcom,aoss-qmp"; reg = <0 0x0c300000 0 0x1000>; interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP @@ -1284,11 +1479,11 @@ spmi_bus: spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; - reg = <0 0xc440000 0 0x1100>, - <0 0xc600000 0 0x2000000>, - <0 0xe600000 0 0x100000>, - <0 0xe700000 0 0xa0000>, - <0 0xc40a000 0 0x26000>; + reg = <0 0x0c440000 0 0x1100>, + <0 0x0c600000 0 0x2000000>, + <0 0x0e600000 0 0x100000>, + <0 0x0e700000 0 0xa0000>, + <0 0x0c40a000 0 0x26000>; reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; interrupt-names = "periph_irq"; interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; @@ -1670,6 +1865,16 @@ }; }; + osm_l3: interconnect@18321000 { + compatible = "qcom,sm6350-osm-l3", "qcom,osm-l3"; + reg = <0x0 0x18321000 0x0 0x1000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + + #interconnect-cells = <1>; + }; + cpufreq_hw: cpufreq@18323000 { compatible = "qcom,cpufreq-hw"; reg = <0 0x18323000 0 0x1000>, <0 0x18325800 0 0x1000>; diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index 12cf5dbe5bd6..31b88c738510 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -264,55 +264,55 @@ compatible = "arm,psci-1.0"; method = "smc"; - CPU_PD0: cpu0 { + CPU_PD0: power-domain-cpu0 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; - CPU_PD1: cpu1 { + CPU_PD1: power-domain-cpu1 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; - CPU_PD2: cpu2 { + CPU_PD2: power-domain-cpu2 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; - CPU_PD3: cpu3 { + CPU_PD3: power-domain-cpu3 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; - CPU_PD4: cpu4 { + CPU_PD4: power-domain-cpu4 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; - CPU_PD5: cpu5 { + CPU_PD5: power-domain-cpu5 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; - CPU_PD6: cpu6 { + CPU_PD6: power-domain-cpu6 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&BIG_CPU_SLEEP_0>; }; - CPU_PD7: cpu7 { + CPU_PD7: power-domain-cpu7 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&BIG_CPU_SLEEP_0>; }; - CLUSTER_PD: cpu-cluster0 { + CLUSTER_PD: power-domain-cpu-cluster0 { #power-domain-cells = <0>; domain-idle-states = <&CLUSTER_SLEEP_0>; }; diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts index c456e9594ea5..b86a1c6f08be 100644 --- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts +++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts @@ -5,14 +5,20 @@ /dts-v1/; +/* PMK8350 (in reality a PMK8003) is configured to use SID6 instead of 0 */ +#define PMK8350_SID 6 + #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h> #include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> #include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include "sm7225.dtsi" #include "pm6150l.dtsi" #include "pm6350.dtsi" #include "pm7250b.dtsi" +#include "pmk8350.dtsi" / { model = "Fairphone 4"; @@ -362,11 +368,40 @@ }; }; +&ipa { + qcom,gsi-loader = "self"; + memory-region = <&pil_ipa_fw_mem>; + firmware-name = "qcom/sm7225/fairphone4/ipa_fws.mdt"; + status = "okay"; +}; + &mpss { status = "okay"; firmware-name = "qcom/sm7225/fairphone4/modem.mdt"; }; +&pm6150l_flash { + status = "okay"; + + led-0 { + function = LED_FUNCTION_FLASH; + color = <LED_COLOR_ID_YELLOW>; + led-sources = <1>; + led-max-microamp = <180000>; + flash-max-microamp = <1000000>; + flash-max-timeout-us = <1280000>; + }; + + led-1 { + function = LED_FUNCTION_FLASH; + color = <LED_COLOR_ID_WHITE>; + led-sources = <2>; + led-max-microamp = <180000>; + flash-max-microamp = <1000000>; + flash-max-timeout-us = <1280000>; + }; +}; + &pm6150l_wled { status = "okay"; @@ -426,6 +461,20 @@ }; }; +&pmk8350_rtc { + status = "okay"; +}; + +&pmk8350_vadc { + adc-chan@644 { + reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "xo_therm"; + }; +}; + &qupv3_id_1 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm7225.dtsi b/arch/arm64/boot/dts/qcom/sm7225.dtsi index 7b2a002ca7ff..b7b4044e9bb0 100644 --- a/arch/arm64/boot/dts/qcom/sm7225.dtsi +++ b/arch/arm64/boot/dts/qcom/sm7225.dtsi @@ -14,3 +14,22 @@ &CPU5 { compatible = "qcom,kryo570"; }; &CPU6 { compatible = "qcom,kryo570"; }; &CPU7 { compatible = "qcom,kryo570"; }; + +&cpu0_opp_table { + opp-1804800000 { + opp-hz = /bits/ 64 <1804800000>; + opp-peak-kBps = <(1804000 * 4 * 2 * 2) (1459200 * 16 * 2)>; + }; +}; + +&cpu6_opp_table { + opp-2131200000 { + opp-hz = /bits/ 64 <2131200000>; + opp-peak-kBps = <(2092000 * 4 * 2 * 2) (1459200 * 16 * 2)>; + }; + + opp-2208000000 { + opp-hz = /bits/ 64 <2208000000>; + opp-peak-kBps = <(2092000 * 4 * 2 * 2) (1459200 * 16 * 2)>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi b/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi index c958a8b16730..64602748c657 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi @@ -33,9 +33,10 @@ framebuffer: framebuffer@9c000000 { compatible = "simple-framebuffer"; reg = <0 0x9c000000 0 0x2300000>; - width = <1644>; - height = <3840>; - stride = <(1644 * 4)>; + /* Griffin BL initializes in 2.5k mode, not 4k */ + width = <1096>; + height = <2560>; + stride = <(1096 * 4)>; format = "a8r8g8b8"; /* * That's (going to be) a lot of clocks, but it's necessary due @@ -46,6 +47,40 @@ }; }; + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&focus_n &snapshot_n &vol_down_n>; + + key-camera-focus { + label = "Camera Focus"; + linux,code = <KEY_CAMERA_FOCUS>; + gpios = <&pm8150b_gpios 2 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + gpio-key,wakeup; + }; + + key-camera-snapshot { + label = "Camera Snapshot"; + linux,code = <KEY_CAMERA>; + gpios = <&pm8150b_gpios 1 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + gpio-key,wakeup; + }; + + key-vol-down { + label = "Volume Down"; + linux,code = <KEY_VOLUMEDOWN>; + gpios = <&pm8150_gpios 1 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + gpio-key,wakeup; + }; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; @@ -394,8 +429,18 @@ /* Qcom SMB1355 @ c */ /* Qcom SMB1390 @ 10 */ - /* NXP PN553 NFC @ 28 */ /* Qcom FSA4480 USB-C audio switch @ 43 */ + + nfc@28 { + compatible = "nxp,nxp-nci-i2c"; + reg = <0x28>; + + interrupt-parent = <&tlmm>; + interrupts = <47 IRQ_TYPE_EDGE_RISING>; + + enable-gpios = <&tlmm 41 GPIO_ACTIVE_HIGH>; + firmware-gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>; + }; }; &i2c7 { @@ -410,10 +455,43 @@ /* Samsung touchscreen @ 48 */ }; +&pm8150_gpios { + vol_down_n: vol-down-n-state { + pins = "gpio1"; + function = "normal"; + power-source = <0>; + bias-pull-up; + input-enable; + }; +}; + +&pm8150b_gpios { + snapshot_n: snapshot-n-state { + pins = "gpio1"; + function = "normal"; + power-source = <0>; + bias-pull-up; + input-enable; + }; + + focus_n: focus-n-state { + pins = "gpio2"; + function = "normal"; + power-source = <0>; + bias-pull-up; + input-enable; + }; +}; + &pon_pwrkey { status = "okay"; }; +&pon_resin { + linux,code = <KEY_VOLUMEUP>; + status = "okay"; +}; + &qupv3_id_0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index a0c57fb798d3..fd20096cfc6e 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -9,6 +9,7 @@ #include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> #include <dt-bindings/clock/qcom,rpmh.h> +#include <dt-bindings/clock/qcom,dispcc-sm8150.h> #include <dt-bindings/clock/qcom,gcc-sm8150.h> #include <dt-bindings/clock/qcom,gpucc-sm8150.h> #include <dt-bindings/interconnect/qcom,osm-l3.h> @@ -60,9 +61,11 @@ #cooling-cells = <2>; L2_0: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; L3_0: l3-cache { compatible = "cache"; + cache-level = <3>; }; }; }; @@ -84,6 +87,7 @@ #cooling-cells = <2>; L2_100: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; @@ -106,6 +110,7 @@ #cooling-cells = <2>; L2_200: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -127,6 +132,7 @@ #cooling-cells = <2>; L2_300: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -148,6 +154,7 @@ #cooling-cells = <2>; L2_400: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -169,6 +176,7 @@ #cooling-cells = <2>; L2_500: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -190,6 +198,7 @@ #cooling-cells = <2>; L2_600: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -211,6 +220,7 @@ #cooling-cells = <2>; L2_700: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -600,55 +610,55 @@ compatible = "arm,psci-1.0"; method = "smc"; - CPU_PD0: cpu0 { + CPU_PD0: power-domain-cpu0 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; - CPU_PD1: cpu1 { + CPU_PD1: power-domain-cpu1 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; - CPU_PD2: cpu2 { + CPU_PD2: power-domain-cpu2 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; - CPU_PD3: cpu3 { + CPU_PD3: power-domain-cpu3 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; - CPU_PD4: cpu4 { + CPU_PD4: power-domain-cpu4 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&BIG_CPU_SLEEP_0>; }; - CPU_PD5: cpu5 { + CPU_PD5: power-domain-cpu5 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&BIG_CPU_SLEEP_0>; }; - CPU_PD6: cpu6 { + CPU_PD6: power-domain-cpu6 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&BIG_CPU_SLEEP_0>; }; - CPU_PD7: cpu7 { + CPU_PD7: power-domain-cpu7 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&BIG_CPU_SLEEP_0>; }; - CLUSTER_PD: cpu-cluster0 { + CLUSTER_PD: power-domain-cpu-cluster0 { #power-domain-cells = <0>; domain-idle-states = <&CLUSTER_SLEEP_0>; }; @@ -888,7 +898,7 @@ gpi_dma0: dma-controller@800000 { compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; - reg = <0 0x800000 0 0x60000>; + reg = <0 0x00800000 0 0x60000>; interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, @@ -926,7 +936,7 @@ power-domains = <&gcc EMAC_GDSC>; resets = <&gcc GCC_EMAC_BCR>; - iommus = <&apps_smmu 0x3C0 0x0>; + iommus = <&apps_smmu 0x3c0 0x0>; snps,tso; rx-fifo-depth = <4096>; @@ -966,7 +976,7 @@ spi0: spi@880000 { compatible = "qcom,geni-spi"; - reg = <0 0x880000 0 0x4000>; + reg = <0 0x00880000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; @@ -1000,7 +1010,7 @@ spi1: spi@884000 { compatible = "qcom,geni-spi"; - reg = <0 0x884000 0 0x4000>; + reg = <0 0x00884000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; @@ -1034,7 +1044,7 @@ spi2: spi@888000 { compatible = "qcom,geni-spi"; - reg = <0 0x888000 0 0x4000>; + reg = <0 0x00888000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; @@ -1068,7 +1078,7 @@ spi3: spi@88c000 { compatible = "qcom,geni-spi"; - reg = <0 0x88c000 0 0x4000>; + reg = <0 0x0088c000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; @@ -1102,7 +1112,7 @@ spi4: spi@890000 { compatible = "qcom,geni-spi"; - reg = <0 0x890000 0 0x4000>; + reg = <0 0x00890000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; @@ -1136,7 +1146,7 @@ spi5: spi@894000 { compatible = "qcom,geni-spi"; - reg = <0 0x894000 0 0x4000>; + reg = <0 0x00894000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; @@ -1170,7 +1180,7 @@ spi6: spi@898000 { compatible = "qcom,geni-spi"; - reg = <0 0x898000 0 0x4000>; + reg = <0 0x00898000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; @@ -1204,7 +1214,7 @@ spi7: spi@89c000 { compatible = "qcom,geni-spi"; - reg = <0 0x89c000 0 0x4000>; + reg = <0 0x0089c000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; @@ -1223,7 +1233,7 @@ gpi_dma1: dma-controller@a00000 { compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; - reg = <0 0xa00000 0 0x60000>; + reg = <0 0x00a00000 0 0x60000>; interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, @@ -1274,7 +1284,7 @@ spi8: spi@a80000 { compatible = "qcom,geni-spi"; - reg = <0 0xa80000 0 0x4000>; + reg = <0 0x00a80000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; @@ -1308,7 +1318,7 @@ spi9: spi@a84000 { compatible = "qcom,geni-spi"; - reg = <0 0xa84000 0 0x4000>; + reg = <0 0x00a84000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; @@ -1342,7 +1352,7 @@ spi10: spi@a88000 { compatible = "qcom,geni-spi"; - reg = <0 0xa88000 0 0x4000>; + reg = <0 0x00a88000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; @@ -1376,7 +1386,7 @@ spi11: spi@a8c000 { compatible = "qcom,geni-spi"; - reg = <0 0xa8c000 0 0x4000>; + reg = <0 0x00a8c000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; @@ -1419,7 +1429,7 @@ spi12: spi@a90000 { compatible = "qcom,geni-spi"; - reg = <0 0xa90000 0 0x4000>; + reg = <0 0x00a90000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; @@ -1437,7 +1447,7 @@ i2c16: i2c@94000 { compatible = "qcom,geni-i2c"; - reg = <0 0x0094000 0 0x4000>; + reg = <0 0x00094000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, @@ -1453,7 +1463,7 @@ spi16: spi@a94000 { compatible = "qcom,geni-spi"; - reg = <0 0xa94000 0 0x4000>; + reg = <0 0x00a94000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; @@ -1472,7 +1482,7 @@ gpi_dma2: dma-controller@c00000 { compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; - reg = <0 0xc00000 0 0x60000>; + reg = <0 0x00c00000 0 0x60000>; interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, @@ -1524,7 +1534,7 @@ spi17: spi@c80000 { compatible = "qcom,geni-spi"; - reg = <0 0xc80000 0 0x4000>; + reg = <0 0x00c80000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; @@ -1558,7 +1568,7 @@ spi18: spi@c84000 { compatible = "qcom,geni-spi"; - reg = <0 0xc84000 0 0x4000>; + reg = <0 0x00c84000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; @@ -1592,7 +1602,7 @@ spi19: spi@c88000 { compatible = "qcom,geni-spi"; - reg = <0 0xc88000 0 0x4000>; + reg = <0 0x00c88000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; @@ -1626,7 +1636,7 @@ spi13: spi@c8c000 { compatible = "qcom,geni-spi"; - reg = <0 0xc8c000 0 0x4000>; + reg = <0 0x00c8c000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; @@ -1660,7 +1670,7 @@ spi14: spi@c90000 { compatible = "qcom,geni-spi"; - reg = <0 0xc90000 0 0x4000>; + reg = <0 0x00c90000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; @@ -1694,7 +1704,7 @@ spi15: spi@c94000 { compatible = "qcom,geni-spi"; - reg = <0 0xc94000 0 0x4000>; + reg = <0 0x00c94000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; @@ -1767,6 +1777,12 @@ interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; }; + dma@10a2000 { + compatible = "qcom,sm8150-dcc", "qcom,dcc"; + reg = <0x0 0x010a2000 0x0 0x1000>, + <0x0 0x010ad000 0x0 0x3000>; + }; + pcie0: pci@1c00000 { compatible = "qcom,pcie-sm8150", "snps,dw-pcie"; reg = <0 0x01c00000 0 0x3000>, @@ -1851,10 +1867,10 @@ status = "disabled"; pcie0_lane: phy@1c06200 { - reg = <0 0x1c06200 0 0x170>, /* tx */ - <0 0x1c06400 0 0x200>, /* rx */ - <0 0x1c06800 0 0x1f0>, /* pcs */ - <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ + reg = <0 0x01c06200 0 0x170>, /* tx */ + <0 0x01c06400 0 0x200>, /* rx */ + <0 0x01c06800 0 0x1f0>, /* pcs */ + <0 0x01c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; clock-names = "pipe0"; @@ -1950,12 +1966,12 @@ status = "disabled"; pcie1_lane: phy@1c0e200 { - reg = <0 0x1c0e200 0 0x170>, /* tx0 */ - <0 0x1c0e400 0 0x200>, /* rx0 */ - <0 0x1c0ea00 0 0x1f0>, /* pcs */ - <0 0x1c0e600 0 0x170>, /* tx1 */ - <0 0x1c0e800 0 0x200>, /* rx1 */ - <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ + reg = <0 0x01c0e200 0 0x170>, /* tx0 */ + <0 0x01c0e400 0 0x200>, /* rx0 */ + <0 0x01c0ea00 0 0x1f0>, /* pcs */ + <0 0x01c0e600 0 0x170>, /* tx1 */ + <0 0x01c0e800 0 0x200>, /* rx1 */ + <0 0x01c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; clock-names = "pipe0"; @@ -2041,13 +2057,6 @@ }; }; - ipa_virt: interconnect@1e00000 { - compatible = "qcom,sm8150-ipa-virt"; - reg = <0 0x01e00000 0 0x1000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x20000>; @@ -2240,7 +2249,7 @@ }; adreno_smmu: iommu@2ca0000 { - compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; + compatible = "qcom,sm8150-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; reg = <0 0x02ca0000 0 0x10000>; #iommu-cells = <2>; #global-interrupts = <1>; @@ -3579,6 +3588,291 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + mdss: display-subsystem@ae00000 { + compatible = "qcom,sm8150-mdss"; + reg = <0 0x0ae00000 0 0x1000>; + reg-names = "mdss"; + + interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, + <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "nrt_bus", "core"; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x800 0x420>; + + status = "disabled"; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + mdss_mdp: display-controller@ae01000 { + compatible = "qcom,sm8150-dpu"; + reg = <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "iface", "bus", "core", "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SM8150_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&mdss_dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-171428571 { + opp-hz = /bits/ 64 <171428571>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-345000000 { + opp-hz = /bits/ 64 <345000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-460000000 { + opp-hz = /bits/ 64 <460000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_dsi0: dsi@ae94000 { + compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae94000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SM8150_MMCX>; + + phys = <&mdss_dsi0_phy>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi0_out: endpoint { + }; + }; + }; + + dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss_dsi0_phy: phy@ae94400 { + compatible = "qcom,dsi-phy-7nm"; + reg = <0 0x0ae94400 0 0x200>, + <0 0x0ae94600 0 0x280>, + <0 0x0ae94900 0 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + + mdss_dsi1: dsi@ae96000 { + compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae96000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SM8150_MMCX>; + + phys = <&mdss_dsi1_phy>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi1_phy: phy@ae96400 { + compatible = "qcom,dsi-phy-7nm"; + reg = <0 0x0ae96400 0 0x200>, + <0 0x0ae96600 0 0x280>, + <0 0x0ae96900 0 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,sm8150-dispcc"; + reg = <0 0x0af00000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>, + <0>, + <0>; + clock-names = "bi_tcxo", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dsi1_phy_pll_out_byteclk", + "dsi1_phy_pll_out_dsiclk", + "dp_phy_pll_link_clk", + "dp_phy_pll_vco_div_clk"; + power-domains = <&rpmhpd SM8150_MMCX>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sm8150-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x400>; @@ -3589,7 +3883,7 @@ interrupt-controller; }; - aoss_qmp: power-controller@c300000 { + aoss_qmp: power-management@c300000 { compatible = "qcom,sm8150-aoss-qmp", "qcom,aoss-qmp"; reg = <0x0 0x0c300000 0x0 0x400>; interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; @@ -3823,7 +4117,7 @@ reg = <0x0 0x17c20000 0x0 0x1000>; clock-frequency = <19200000>; - frame@17c21000{ + frame@17c21000 { frame-number = <0>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; @@ -4057,7 +4351,7 @@ type = "passive"; }; - cpu0_crit: cpu_crit { + cpu0_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -4101,7 +4395,7 @@ type = "passive"; }; - cpu1_crit: cpu_crit { + cpu1_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -4145,7 +4439,7 @@ type = "passive"; }; - cpu2_crit: cpu_crit { + cpu2_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -4189,7 +4483,7 @@ type = "passive"; }; - cpu3_crit: cpu_crit { + cpu3_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -4233,7 +4527,7 @@ type = "passive"; }; - cpu4_top_crit: cpu_crit { + cpu4_top_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -4277,7 +4571,7 @@ type = "passive"; }; - cpu5_top_crit: cpu_crit { + cpu5_top_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -4321,7 +4615,7 @@ type = "passive"; }; - cpu6_top_crit: cpu_crit { + cpu6_top_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -4365,7 +4659,7 @@ type = "passive"; }; - cpu7_top_crit: cpu_crit { + cpu7_top_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -4409,7 +4703,7 @@ type = "passive"; }; - cpu4_bottom_crit: cpu_crit { + cpu4_bottom_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -4453,7 +4747,7 @@ type = "passive"; }; - cpu5_bottom_crit: cpu_crit { + cpu5_bottom_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -4497,7 +4791,7 @@ type = "passive"; }; - cpu6_bottom_crit: cpu_crit { + cpu6_bottom_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -4541,7 +4835,7 @@ type = "passive"; }; - cpu7_bottom_crit: cpu_crit { + cpu7_bottom_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; diff --git a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts index 3ed8c84e25b8..0991b34a8e49 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts @@ -23,6 +23,29 @@ serial0 = &uart12; }; + wcd938x: audio-codec { + compatible = "qcom,wcd9380-codec"; + + reset-gpios = <&tlmm 32 GPIO_ACTIVE_LOW>; + + vdd-buck-supply = <&vreg_s4a_1p8>; + vdd-rxtx-supply = <&vreg_s4a_1p8>; + vdd-io-supply = <&vreg_s4a_1p8>; + vdd-mic-bias-supply = <&vreg_bob>; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + #sound-dai-cells = <1>; + }; + chosen { stdout-path = "serial0:115200n8"; }; @@ -631,27 +654,6 @@ firmware-name = "qcom/sm8250/slpi.mbn"; }; -&soc { - wcd938x: codec { - compatible = "qcom,wcd9380-codec"; - #sound-dai-cells = <1>; - reset-gpios = <&tlmm 32 GPIO_ACTIVE_LOW>; - vdd-buck-supply = <&vreg_s4a_1p8>; - vdd-rxtx-supply = <&vreg_s4a_1p8>; - vdd-io-supply = <&vreg_s4a_1p8>; - vdd-mic-bias-supply = <&vreg_bob>; - qcom,micbias1-microvolt = <1800000>; - qcom,micbias2-microvolt = <1800000>; - qcom,micbias3-microvolt = <1800000>; - qcom,micbias4-microvolt = <1800000>; - qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; - qcom,mbhc-headset-vthreshold-microvolt = <1700000>; - qcom,mbhc-headphone-vthreshold-microvolt = <50000>; - qcom,rx-device = <&wcd_rx>; - qcom,tx-device = <&wcd_tx>; - }; -}; - &sound { compatible = "qcom,sm8250-sndcard"; model = "SM8250-MTP-WCD9380-WSA8810-VA-DMIC"; diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi index 09a31f707639..e76d0ef5aec9 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi @@ -454,7 +454,7 @@ status = "okay"; clock-frequency = <1000000>; - cs35l41_l: cs35l41@40 { + cs35l41_l: speaker-amp@40 { compatible = "cirrus,cs35l41"; reg = <0x40>; interrupt-parent = <&tlmm>; @@ -469,7 +469,7 @@ #sound-dai-cells = <1>; }; - cs35l41_r: cs35l41@41 { + cs35l41_r: speaker-amp@41 { compatible = "cirrus,cs35l41"; reg = <0x41>; interrupt-parent = <&tlmm>; @@ -522,10 +522,8 @@ clock-frequency = <400000>; /* Qcom SMB1390 @ 10 */ - /* Silicon Labs SI4704 FM Radio Receiver @ 11 */ /* Qcom SMB1390_slave @ 18 */ /* HALO HL6111R Qi charger @ 25 */ - /* Richwave RTC6226 FM Radio Receiver @ 64 */ }; &pcie0 { diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index dab5579946f3..64c08c399ab8 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -110,9 +110,15 @@ #cooling-cells = <2>; L2_0: l2-cache { compatible = "cache"; + cache-level = <2>; + cache-size = <0x20000>; + cache-unified; next-level-cache = <&L3_0>; L3_0: l3-cache { compatible = "cache"; + cache-level = <3>; + cache-size = <0x400000>; + cache-unified; }; }; }; @@ -134,6 +140,9 @@ #cooling-cells = <2>; L2_100: l2-cache { compatible = "cache"; + cache-level = <2>; + cache-size = <0x20000>; + cache-unified; next-level-cache = <&L3_0>; }; }; @@ -155,6 +164,9 @@ #cooling-cells = <2>; L2_200: l2-cache { compatible = "cache"; + cache-level = <2>; + cache-size = <0x20000>; + cache-unified; next-level-cache = <&L3_0>; }; }; @@ -176,6 +188,9 @@ #cooling-cells = <2>; L2_300: l2-cache { compatible = "cache"; + cache-level = <2>; + cache-size = <0x20000>; + cache-unified; next-level-cache = <&L3_0>; }; }; @@ -197,6 +212,9 @@ #cooling-cells = <2>; L2_400: l2-cache { compatible = "cache"; + cache-level = <2>; + cache-size = <0x40000>; + cache-unified; next-level-cache = <&L3_0>; }; }; @@ -218,6 +236,9 @@ #cooling-cells = <2>; L2_500: l2-cache { compatible = "cache"; + cache-level = <2>; + cache-size = <0x40000>; + cache-unified; next-level-cache = <&L3_0>; }; @@ -240,6 +261,9 @@ #cooling-cells = <2>; L2_600: l2-cache { compatible = "cache"; + cache-level = <2>; + cache-size = <0x40000>; + cache-unified; next-level-cache = <&L3_0>; }; }; @@ -261,6 +285,9 @@ #cooling-cells = <2>; L2_700: l2-cache { compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; + cache-unified; next-level-cache = <&L3_0>; }; }; @@ -334,7 +361,6 @@ exit-latency-us = <6562>; min-residency-us = <9987>; local-timer-stop; - status = "disabled"; }; }; }; @@ -651,55 +677,55 @@ compatible = "arm,psci-1.0"; method = "smc"; - CPU_PD0: cpu0 { + CPU_PD0: power-domain-cpu0 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; - CPU_PD1: cpu1 { + CPU_PD1: power-domain-cpu1 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; - CPU_PD2: cpu2 { + CPU_PD2: power-domain-cpu2 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; - CPU_PD3: cpu3 { + CPU_PD3: power-domain-cpu3 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; - CPU_PD4: cpu4 { + CPU_PD4: power-domain-cpu4 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&BIG_CPU_SLEEP_0>; }; - CPU_PD5: cpu5 { + CPU_PD5: power-domain-cpu5 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&BIG_CPU_SLEEP_0>; }; - CPU_PD6: cpu6 { + CPU_PD6: power-domain-cpu6 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&BIG_CPU_SLEEP_0>; }; - CPU_PD7: cpu7 { + CPU_PD7: power-domain-cpu7 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&BIG_CPU_SLEEP_0>; }; - CLUSTER_PD: cpu-cluster0 { + CLUSTER_PD: power-domain-cpu-cluster0 { #power-domain-cells = <0>; domain-idle-states = <&CLUSTER_SLEEP_0>; }; @@ -1887,10 +1913,10 @@ status = "disabled"; pcie0_lane: phy@1c06200 { - reg = <0 0x1c06200 0 0x170>, /* tx */ - <0 0x1c06400 0 0x200>, /* rx */ - <0 0x1c06800 0 0x1f0>, /* pcs */ - <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ + reg = <0 0x01c06200 0 0x170>, /* tx */ + <0 0x01c06400 0 0x200>, /* rx */ + <0 0x01c06800 0 0x1f0>, /* pcs */ + <0 0x01c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; clock-names = "pipe0"; @@ -1993,12 +2019,12 @@ status = "disabled"; pcie1_lane: phy@1c0e200 { - reg = <0 0x1c0e200 0 0x170>, /* tx0 */ - <0 0x1c0e400 0 0x200>, /* rx0 */ - <0 0x1c0ea00 0 0x1f0>, /* pcs */ - <0 0x1c0e600 0 0x170>, /* tx1 */ - <0 0x1c0e800 0 0x200>, /* rx1 */ - <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ + reg = <0 0x01c0e200 0 0x170>, /* tx0 */ + <0 0x01c0e400 0 0x200>, /* rx0 */ + <0 0x01c0ea00 0 0x1f0>, /* pcs */ + <0 0x01c0e600 0 0x170>, /* tx1 */ + <0 0x01c0e800 0 0x200>, /* rx1 */ + <0 0x01c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; clock-names = "pipe0"; @@ -2082,7 +2108,7 @@ pcie2_phy: phy@1c16000 { compatible = "qcom,sm8250-qmp-modem-pcie-phy"; - reg = <0 0x1c16000 0 0x1c0>; + reg = <0 0x01c16000 0 0x1c0>; #address-cells = <2>; #size-cells = <2>; ranges; @@ -2101,12 +2127,12 @@ status = "disabled"; pcie2_lane: phy@1c16200 { - reg = <0 0x1c16200 0 0x170>, /* tx0 */ - <0 0x1c16400 0 0x200>, /* rx0 */ - <0 0x1c16a00 0 0x1f0>, /* pcs */ - <0 0x1c16600 0 0x170>, /* tx1 */ - <0 0x1c16800 0 0x200>, /* rx1 */ - <0 0x1c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ + reg = <0 0x01c16200 0 0x170>, /* tx0 */ + <0 0x01c16400 0 0x200>, /* rx0 */ + <0 0x01c16a00 0 0x1f0>, /* pcs */ + <0 0x01c16600 0 0x170>, /* tx1 */ + <0 0x01c16800 0 0x200>, /* rx1 */ + <0 0x01c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; clock-names = "pipe0"; @@ -2189,13 +2215,6 @@ }; }; - ipa_virt: interconnect@1e00000 { - compatible = "qcom,sm8250-ipa-virt"; - reg = <0 0x01e00000 0 0x1000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x40000>; @@ -2215,7 +2234,6 @@ clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen"; #clock-cells = <0>; - clock-frequency = <9600000>; clock-output-names = "mclk"; #sound-dai-cells = <1>; @@ -2263,7 +2281,6 @@ clock-names = "mclk", "macro", "dcodec"; #clock-cells = <0>; - clock-frequency = <9600000>; clock-output-names = "fsgen"; #sound-dai-cells = <1>; }; @@ -2284,7 +2301,6 @@ clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; #clock-cells = <0>; - clock-frequency = <9600000>; clock-output-names = "mclk"; #sound-dai-cells = <1>; }; @@ -2300,15 +2316,15 @@ qcom,din-ports = <0>; qcom,dout-ports = <5>; - qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1F 0x1F 0x07 0x00>; - qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>; - qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>; - qcom,ports-hstart = /bits/ 8 <0xFF 0x03 0xFF 0xFF 0xFF>; - qcom,ports-hstop = /bits/ 8 <0xFF 0x06 0xFF 0xFF 0xFF>; - qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xFF 0xFF>; - qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0x00 0x01 0xFF 0xFF>; + qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; + qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>; + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; + qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; + qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; + qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; + qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; - qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0x00>; + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; #sound-dai-cells = <1>; #address-cells = <2>; @@ -2331,10 +2347,7 @@ clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; #clock-cells = <0>; - clock-frequency = <9600000>; clock-output-names = "mclk"; - #address-cells = <2>; - #size-cells = <2>; #sound-dai-cells = <1>; }; @@ -2352,15 +2365,15 @@ qcom,din-ports = <5>; qcom,dout-ports = <0>; - qcom,ports-sinterval-low = /bits/ 8 <0xFF 0x01 0x01 0x03 0x03>; - qcom,ports-offset1 = /bits/ 8 <0xFF 0x01 0x00 0x02 0x00>; - qcom,ports-offset2 = /bits/ 8 <0xFF 0x00 0x00 0x00 0x00>; - qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; - qcom,ports-hstart = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; - qcom,ports-hstop = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; - qcom,ports-word-length = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; - qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; - qcom,ports-lane-control = /bits/ 8 <0xFF 0x00 0x01 0x00 0x01>; + qcom,ports-sinterval-low = /bits/ 8 <0xff 0x01 0x01 0x03 0x03>; + qcom,ports-offset1 = /bits/ 8 <0xff 0x01 0x00 0x02 0x00>; + qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x00 0x00 0x00>; + qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; + qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; + qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; + qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; + qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x01 0x00 0x01>; #sound-dai-cells = <1>; #address-cells = <2>; #size-cells = <0>; @@ -2376,7 +2389,7 @@ clock-names = "core", "audio", "bus"; }; - lpass_tlmm: pinctrl@33c0000{ + lpass_tlmm: pinctrl@33c0000 { compatible = "qcom,sm8250-lpass-lpi-pinctrl"; reg = <0 0x033c0000 0x0 0x20000>, <0 0x03550000 0x0 0x10000>; @@ -3323,9 +3336,6 @@ }; }; - sound: sound { - }; - usb_1_hsphy: phy@88e3000 { compatible = "qcom,sm8250-usb-hs-phy", "qcom,usb-snps-hs-7nm-phy"; @@ -3676,7 +3686,7 @@ }; cci0: cci@ac4f000 { - compatible = "qcom,sm8250-cci"; + compatible = "qcom,sm8250-cci", "qcom,msm8996-cci"; #address-cells = <1>; #size-cells = <0>; @@ -3717,7 +3727,7 @@ }; cci1: cci@ac50000 { - compatible = "qcom,sm8250-cci"; + compatible = "qcom,sm8250-cci", "qcom,msm8996-cci"; #address-cells = <1>; #size-cells = <0>; @@ -3761,16 +3771,16 @@ compatible = "qcom,sm8250-camss"; status = "disabled"; - reg = <0 0xac6a000 0 0x2000>, - <0 0xac6c000 0 0x2000>, - <0 0xac6e000 0 0x1000>, - <0 0xac70000 0 0x1000>, - <0 0xac72000 0 0x1000>, - <0 0xac74000 0 0x1000>, - <0 0xacb4000 0 0xd000>, - <0 0xacc3000 0 0xd000>, - <0 0xacd9000 0 0x2200>, - <0 0xacdb200 0 0x2200>; + reg = <0 0x0ac6a000 0 0x2000>, + <0 0x0ac6c000 0 0x2000>, + <0 0x0ac6e000 0 0x1000>, + <0 0x0ac70000 0 0x1000>, + <0 0x0ac72000 0 0x1000>, + <0 0x0ac74000 0 0x1000>, + <0 0x0acb4000 0 0xd000>, + <0 0x0acc3000 0 0xd000>, + <0 0x0acd9000 0 0x2200>, + <0 0x0acdb200 0 0x2200>; reg-names = "csiphy0", "csiphy1", "csiphy2", @@ -3955,7 +3965,7 @@ #power-domain-cells = <1>; }; - mdss: mdss@ae00000 { + mdss: display-subsystem@ae00000 { compatible = "qcom,sm8250-mdss"; reg = <0 0x0ae00000 0 0x1000>; reg-names = "mdss"; @@ -4050,7 +4060,8 @@ }; dsi0: dsi@ae94000 { - compatible = "qcom,mdss-dsi-ctrl"; + compatible = "qcom,sm8250-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; reg = <0 0x0ae94000 0 0x400>; reg-names = "dsi_ctrl"; @@ -4141,7 +4152,8 @@ }; dsi1: dsi@ae96000 { - compatible = "qcom,mdss-dsi-ctrl"; + compatible = "qcom,sm8250-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; reg = <0 0x0ae96000 0 0x400>; reg-names = "dsi_ctrl"; @@ -4269,7 +4281,7 @@ #thermal-sensor-cells = <1>; }; - aoss_qmp: power-controller@c300000 { + aoss_qmp: power-management@c300000 { compatible = "qcom,sm8250-aoss-qmp", "qcom,aoss-qmp"; reg = <0 0x0c300000 0 0x400>; interrupts-extended = <&ipcc IPCC_CLIENT_AOP @@ -5468,6 +5480,9 @@ }; }; + sound: sound { + }; + timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 @@ -5500,7 +5515,7 @@ type = "passive"; }; - cpu0_crit: cpu_crit { + cpu0_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -5544,7 +5559,7 @@ type = "passive"; }; - cpu1_crit: cpu_crit { + cpu1_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -5588,7 +5603,7 @@ type = "passive"; }; - cpu2_crit: cpu_crit { + cpu2_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -5632,7 +5647,7 @@ type = "passive"; }; - cpu3_crit: cpu_crit { + cpu3_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -5676,7 +5691,7 @@ type = "passive"; }; - cpu4_top_crit: cpu_crit { + cpu4_top_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -5720,7 +5735,7 @@ type = "passive"; }; - cpu5_top_crit: cpu_crit { + cpu5_top_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -5764,7 +5779,7 @@ type = "passive"; }; - cpu6_top_crit: cpu_crit { + cpu6_top_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -5808,7 +5823,7 @@ type = "passive"; }; - cpu7_top_crit: cpu_crit { + cpu7_top_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -5852,7 +5867,7 @@ type = "passive"; }; - cpu4_bottom_crit: cpu_crit { + cpu4_bottom_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -5896,7 +5911,7 @@ type = "passive"; }; - cpu5_bottom_crit: cpu_crit { + cpu5_bottom_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -5940,7 +5955,7 @@ type = "passive"; }; - cpu6_bottom_crit: cpu_crit { + cpu6_bottom_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -5984,7 +5999,7 @@ type = "passive"; }; - cpu7_bottom_crit: cpu_crit { + cpu7_bottom_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts index 26a608144886..5a4c4ea4d122 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts @@ -20,6 +20,17 @@ stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <<9611_out>; + }; + }; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; @@ -29,6 +40,31 @@ regulator-always-on; regulator-boot-on; }; + + lt9611_1v2: lt9611-1v2-regulator { + compatible = "regulator-fixed"; + regulator-name = "LT9611_1V2"; + + vin-supply = <&vph_pwr>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&tlmm 49 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; + + lt9611_3v3: lt9611-3v3-regulator { + compatible = "regulator-fixed"; + regulator-name = "LT9611_3V3"; + + vin-supply = <&vreg_bob>; + gpio = <&tlmm 47 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + }; }; &adsp { @@ -221,19 +257,127 @@ firmware-name = "qcom/sm8350/cdsp.mbn"; }; +&dispcc { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&vreg_l6b_1p2>; + status = "okay"; + + ports { + port@1 { + endpoint { + remote-endpoint = <<9611_a>; + data-lanes = <0 1 2 3>; + }; + }; + }; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vreg_l5b_0p88>; + status = "okay"; +}; + &gpi_dma1 { status = "okay"; }; +&i2c15 { + clock-frequency = <400000>; + status = "okay"; + + lt9611_codec: hdmi-bridge@2b { + compatible = "lontium,lt9611uxc"; + reg = <0x2b>; + + interrupts-extended = <&tlmm 50 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>; + + vdd-supply = <<9611_1v2>; + vcc-supply = <<9611_3v3>; + + pinctrl-names = "default"; + pinctrl-0 = <<9611_state>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lt9611_a: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@2 { + reg = <2>; + + lt9611_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; +}; + +&mdss { + status = "okay"; +}; + +&mdss_mdp { + status = "okay"; +}; + &mpss { status = "okay"; firmware-name = "qcom/sm8350/modem.mbn"; }; +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_default_state>; + + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l5b_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; + + status = "okay"; +}; + +&pcie1 { + perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_default_state>; + + status = "okay"; +}; + +&pcie1_phy { + status = "okay"; + vdda-phy-supply = <&vreg_l5b_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; +}; + &qupv3_id_0 { status = "okay"; }; +&qupv3_id_2 { + status = "okay"; +}; + &slpi { status = "okay"; firmware-name = "qcom/sm8350/slpi.mbn"; @@ -241,6 +385,258 @@ &tlmm { gpio-reserved-ranges = <52 8>; + + gpio-line-names = + "APPS_I2C_SDA", /* GPIO_0 */ + "APPS_I2C_SCL", + "FSA_INT_N", + "USER_LED3_EN", + "SMBUS_SDA_1P8", + "SMBUS_SCL_1P8", + "2M2_3P3_EN", + "ALERT_DUAL_M2_N", + "EXP_UART_CTS", + "EXP_UART_RFR", + "EXP_UART_TX", /* GPIO_10 */ + "EXP_UART_RX", + "NC", + "NC", + "RCM_MARKER1", + "WSA0_EN", + "CAM1_RESET_N", + "CAM0_RESET_N", + "DEBUG_UART_TX", + "DEBUG_UART_RX", + "TS_I2C_SDA", /* GPIO_20 */ + "TS_I2C_SCL", + "TS_RESET_N", + "TS_INT_N", + "DISP0_RESET_N", + "DISP1_RESET_N", + "ETH_RESET", + "RCM_MARKER2", + "CAM_DC_MIPI_MUX_EN", + "CAM_DC_MIPI_MUX_SEL", + "AFC_PHY_TA_D_PLUS", /* GPIO_30 */ + "AFC_PHY_TA_D_MINUS", + "PM8008_1_IRQ", + "PM8008_1_RESET_N", + "PM8008_2_IRQ", + "PM8008_2_RESET_N", + "CAM_DC_I3C_SDA", + "CAM_DC_I3C_SCL", + "FP_INT_N", + "FP_WUHB_INT_N", + "SMB_SPMI_DATA", /* GPIO_40 */ + "SMB_SPMI_CLK", + "USB_HUB_RESET", + "FORCE_USB_BOOT", + "LRF_IRQ", + "NC", + "IMU2_INT", + "HDMI_3P3_EN", + "HDMI_RSTN", + "HDMI_1P2_EN", + "HDMI_INT", /* GPIO_50 */ + "USB1_ID", + "FP_SPI_MISO", + "FP_SPI_MOSI", + "FP_SPI_CLK", + "FP_SPI_CS_N", + "NFC_ESE_SPI_MISO", + "NFC_ESE_SPI_MOSI", + "NFC_ESE_SPI_CLK", + "NFC_ESE_SPI_CS", + "NFC_I2C_SDA", /* GPIO_60 */ + "NFC_I2C_SCLC", + "NFC_EN", + "NFC_CLK_REQ", + "HST_WLAN_EN", + "HST_BT_EN", + "HST_SW_CTRL", + "NC", + "HST_BT_UART_CTS", + "HST_BT_UART_RFR", + "HST_BT_UART_TX", /* GPIO_70 */ + "HST_BT_UART_RX", + "CAM_DC_SPI0_MISO", + "CAM_DC_SPI0_MOSI", + "CAM_DC_SPI0_CLK", + "CAM_DC_SPI0_CS_N", + "CAM_DC_SPI1_MISO", + "CAM_DC_SPI1_MOSI", + "CAM_DC_SPI1_CLK", + "CAM_DC_SPI1_CS_N", + "HALL_INT_N", /* GPIO_80 */ + "USB_PHY_PS", + "MDP_VSYNC_P", + "MDP_VSYNC_S", + "ETH_3P3_EN", + "RADAR_INT", + "NFC_DWL_REQ", + "SM_GPIO_87", + "WCD_RESET_N", + "ALSP_INT_N", + "PRESS_INT", /* GPIO_90 */ + "SAR_INT_N", + "SD_CARD_DET_N", + "NC", + "PCIE0_RESET_N", + "PCIE0_CLK_REQ_N", + "PCIE0_WAKE_N", + "PCIE1_RESET_N", + "PCIE1_CLK_REQ_N", + "PCIE1_WAKE_N", + "CAM_MCLK0", /* GPIO_100 */ + "CAM_MCLK1", + "CAM_MCLK2", + "CAM_MCLK3", + "CAM_MCLK4", + "CAM_MCLK5", + "CAM2_RESET_N", + "CCI_I2C0_SDA", + "CCI_I2C0_SCL", + "CCI_I2C1_SDA", + "CCI_I2C1_SCL", /* GPIO_110 */ + "CCI_I2C2_SDA", + "CCI_I2C2_SCL", + "CCI_I2C3_SDA", + "CCI_I2C3_SCL", + "CAM5_RESET_N", + "CAM4_RESET_N", + "CAM3_RESET_N", + "IMU1_INT", + "MAG_INT_N", + "MI2S2_I2S_SCK", /* GPIO_120 */ + "MI2S2_I2S_DAT0", + "MI2S2_I2S_WS", + "HIFI_DAC_I2S_MCLK", + "MI2S2_I2S_DAT1", + "HIFI_DAC_I2S_SCK", + "HIFI_DAC_I2S_DAT0", + "NC", + "HIFI_DAC_I2S_WS", + "HST_BT_WLAN_SLIMBUS_CLK", + "HST_BT_WLAN_SLIMBUS_DAT0", /* GPIO_130 */ + "BT_LED_EN", + "WLAN_LED_EN", + "NC", + "NC", + "NC", + "UIM2_PRESENT", + "NC", + "NC", + "NC", + "UIM1_PRESENT", /* GPIO_140 */ + "NC", + "SM_RFFE0_DATA", + "NC", + "SM_RFFE1_DATA", + "SM_MSS_GRFC4", + "SM_MSS_GRFC5", + "SM_MSS_GRFC6", + "SM_MSS_GRFC7", + "SM_RFFE4_CLK", + "SM_RFFE4_DATA", /* GPIO_150 */ + "WLAN_COEX_UART1_RX", + "WLAN_COEX_UART1_TX", + "HST_SW_CTRL", + "DSI0_STATUS", + "DSI1_STATUS", + "APPS_PBL_BOOT_SPEED_1", + "APPS_BOOT_FROM_ROM", + "APPS_PBL_BOOT_SPEED_0", + "QLINK0_REQ", + "QLINK0_EN", /* GPIO_160 */ + "QLINK0_WMSS_RESET_N", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "WCD_SWR_TX_CLK", + "WCD_SWR_TX_DATA0", + "WCD_SWR_TX_DATA1", /* GPIO_170 */ + "WCD_SWR_RX_CLK", + "WCD_SWR_RX_DATA0", + "WCD_SWR_RX_DATA1", + "DMIC01_CLK", + "DMIC01_DATA", + "DMIC23_CLK", + "DMIC23_DATA", + "WSA_SWR_CLK", + "WSA_SWR_DATA", + "DMIC45_CLK", /* GPIO_180 */ + "DMIC45_DATA", + "WCD_SWR_TX_DATA2", + "SENSOR_I3C_SDA", + "SENSOR_I3C_SCL", + "CAM_OIS0_I3C_SDA", + "CAM_OIS0_I3C_SCL", + "IMU_SPI_MISO", + "IMU_SPI_MOSI", + "IMU_SPI_CLK", + "IMU_SPI_CS_N", /* GPIO_190 */ + "MAG_I2C_SDA", + "MAG_I2C_SCL", + "SENSOR_I2C_SDA", + "SENSOR_I2C_SCL", + "RADAR_SPI_MISO", + "RADAR_SPI_MOSI", + "RADAR_SPI_CLK", + "RADAR_SPI_CS_N", + "HST_BLE_UART_TX", + "HST_BLE_UART_RX", /* GPIO_200 */ + "HST_WLAN_UART_TX", + "HST_WLAN_UART_RX"; + + pcie0_default_state: pcie0-default-state { + perst-pins { + pins = "gpio94"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq-pins { + pins = "gpio95"; + function = "pcie0_clkreqn"; + drive-strength = <2>; + bias-pull-up; + }; + + wake-pins { + pins = "gpio96"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie1_default_state: pcie1-default-state { + perst-pins { + pins = "gpio97"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq-pins { + pins = "gpio98"; + function = "pcie1_clkreqn"; + drive-strength = <2>; + bias-pull-up; + }; + + wake-pins { + pins = "gpio99"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; &uart2 { @@ -325,4 +721,20 @@ drive-strength = <2>; output-low; }; + + lt9611_state: lt9611-state { + rst { + pins = "gpio48"; + function = "normal"; + + output-high; + input-disable; + }; + + irq { + pins = "gpio50"; + function = "gpio"; + bias-disable; + }; + }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts b/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts index 9c4cfd995ff2..00f16cde6c4a 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts @@ -290,9 +290,9 @@ }; &ipa { - status = "okay"; - + qcom,gsi-loader = "self"; memory-region = <&pil_ipa_fw_mem>; + status = "okay"; }; &mpss { diff --git a/arch/arm64/boot/dts/qcom/sm8350-mtp.dts b/arch/arm64/boot/dts/qcom/sm8350-mtp.dts index 52cf3045602f..f70e0de0509c 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-mtp.dts @@ -376,7 +376,7 @@ }; &ipa { - status = "okay"; - + qcom,gsi-loader = "self"; memory-region = <&pil_ipa_fw_mem>; + status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx214.dts b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx214.dts index cc650508dc2d..e6824c8c2774 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx214.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx214.dts @@ -17,3 +17,26 @@ height = <2520>; stride = <(1080 * 4)>; }; + +&pm8350b_gpios { + gpio-line-names = "NC", /* GPIO_1 */ + "NC", + "NC", + "NC", + "SNAPSHOT_N", + "NC", + "NC", + "FOCUS_N"; +}; + +&pm8350c_gpios { + gpio-line-names = "FL_STROBE_TRIG_WIDE", /* GPIO_1 */ + "FL_STROBE_TRIG_TELE", + "NC", + "NC", + "NC", + "RGBC_IR_PWR_EN", + "NC", + "NC", + "WIDEC_PWR_EN"; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx215.dts b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx215.dts index c74c973a69d2..c6f402c3ef35 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx215.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx215.dts @@ -12,6 +12,93 @@ compatible = "sony,pdx215-generic", "qcom,sm8350"; }; +&i2c13 { + pmic@75 { + compatible = "dlg,slg51000"; + reg = <0x75>; + dlg,cs-gpios = <&pm8350b_gpios 1 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&cam_pwr_a_cs>; + + regulators { + slg51000_a_ldo1: ldo1 { + regulator-name = "slg51000_a_ldo1"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3300000>; + }; + + slg51000_a_ldo2: ldo2 { + regulator-name = "slg51000_a_ldo2"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3300000>; + }; + + slg51000_a_ldo3: ldo3 { + regulator-name = "slg51000_a_ldo3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + }; + + slg51000_a_ldo4: ldo4 { + regulator-name = "slg51000_a_ldo4"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + }; + + slg51000_a_ldo5: ldo5 { + regulator-name = "slg51000_a_ldo5"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1200000>; + }; + + slg51000_a_ldo6: ldo6 { + regulator-name = "slg51000_a_ldo6"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1200000>; + }; + + slg51000_a_ldo7: ldo7 { + regulator-name = "slg51000_a_ldo7"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + }; + }; + }; +}; + +&pm8350b_gpios { + gpio-line-names = "CAM_PWR_A_CS", /* GPIO_1 */ + "NC", + "NC", + "NC", + "SNAPSHOT_N", + "CAM_PWR_LD_EN", + "NC", + "FOCUS_N"; + + cam_pwr_a_cs: cam-pwr-a-cs-state { + pins = "gpio1"; + function = "normal"; + qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>; + power-source = <1>; + drive-push-pull; + output-high; + }; +}; + +&pm8350c_gpios { + gpio-line-names = "FL_STROBE_TRIG_WIDE", /* GPIO_1 */ + "FL_STROBE_TRIG_TELE", + "NC", + "WLC_TXPWR_EN", + "NC", + "RGBC_IR_PWR_EN", + "NC", + "NC", + "WIDEC_PWR_EN"; +}; + &tlmm { gpio-line-names = "APPS_I2C_0_SDA", /* GPIO_0 */ "APPS_I2C_0_SCL", diff --git a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi index 1f2d660f8f86..89382ad73133 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> */ +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> #include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include "sm8350.dtsi" #include "pm8350.dtsi" @@ -48,7 +49,35 @@ gpio-keys { compatible = "gpio-keys"; - /* For reasons still unknown, GAssist key and Camera Focus/Shutter don't work.. */ + pinctrl-names = "default"; + pinctrl-0 = <&focus_n &snapshot_n &vol_down_n &g_assist_n>; + + key-camera-focus { + label = "Camera Focus"; + linux,code = <KEY_CAMERA_FOCUS>; + gpios = <&pm8350b_gpios 8 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + + key-camera-snapshot { + label = "Camera Snapshot"; + linux,code = <KEY_CAMERA>; + gpios = <&pm8350b_gpios 5 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + + key-google-assist { + label = "Google Assistant Key"; + gpios = <&pm8350_gpios 9 GPIO_ACTIVE_LOW>; + linux,code = <KEY_LEFTMETA>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; key-vol-down { label = "Volume Down"; @@ -56,7 +85,7 @@ gpios = <&pmk8350_gpios 3 GPIO_ACTIVE_LOW>; debounce-interval = <15>; linux,can-disable; - gpio-key,wakeup; + wakeup-source; }; }; @@ -171,6 +200,8 @@ regulator-max-microvolt = <888000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; }; pm8350_l6: ldo6 { @@ -179,6 +210,8 @@ regulator-max-microvolt = <1208000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; }; pm8350_l7: ldo7 { @@ -187,6 +220,8 @@ regulator-max-microvolt = <3008000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; }; /* L8 - lcx.lvl (ARC) */ @@ -197,6 +232,8 @@ regulator-max-microvolt = <1200000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; }; }; @@ -443,13 +480,6 @@ /* Some subset of SONY IMX663 camera sensor @ 38 */ }; -&i2c2 { - status = "okay"; - clock-frequency = <400000>; - - /* Richwave RTC6226 FM Radio Receiver @ 64 */ -}; - &i2c4 { status = "okay"; clock-frequency = <400000>; @@ -461,7 +491,7 @@ status = "okay"; clock-frequency = <1000000>; - cs35l41_l: cs35l41@40 { + cs35l41_l: speaker-amp@40 { compatible = "cirrus,cs35l41"; reg = <0x40>; interrupt-parent = <&tlmm>; @@ -476,7 +506,7 @@ #sound-dai-cells = <1>; }; - cs35l41_r: cs35l41@41 { + cs35l41_r: speaker-amp@41 { compatible = "cirrus,cs35l41"; reg = <0x41>; interrupt-parent = <&tlmm>; @@ -506,7 +536,6 @@ clock-frequency = <100000>; /* Qualcomm PM8008i/PM8008j (?) @ 8, 9, c, d */ - /* Dialog SLG51000 CMIC @ 75 */ }; &i2c15 { @@ -524,9 +553,10 @@ }; &ipa { - status = "okay"; + qcom,gsi-loader = "self"; memory-region = <&pil_ipa_fw_mem>; firmware-name = "qcom/sm8350/Sony/sagami/ipa_fws.mbn"; + status = "okay"; }; &mpss { @@ -534,6 +564,60 @@ firmware-name = "qcom/sm8350/Sony/sagami/modem.mbn"; }; +&pm8350_gpios { + gpio-line-names = "ASSIGN1_THERM", /* GPIO_1 */ + "LCD_ID", + "SDR_MMW_THERM", + "RF_ID", + "NC", + "FP_LDO_EN", + "SP_ARI_PWR_ALARM", + "NC", + "G_ASSIST_N", + "PM8350_OPTION"; /* GPIO_10 */ + + g_assist_n: g-assist-n-state { + pins = "gpio9"; + function = "normal"; + power-source = <1>; + bias-pull-up; + input-enable; + }; +}; + +&pm8350b_gpios { + snapshot_n: snapshot-n-state { + pins = "gpio5"; + function = "normal"; + power-source = <0>; + bias-pull-up; + input-enable; + }; + + focus_n: focus-n-state { + pins = "gpio8"; + function = "normal"; + power-source = <0>; + input-enable; + bias-pull-up; + }; +}; + +&pmk8350_gpios { + gpio-line-names = "NC", /* GPIO_1 */ + "NC", + "VOL_DOWN_N", + "PMK8350_OPTION"; + + vol_down_n: vol-down-n-state { + pins = "gpio3"; + function = "normal"; + power-source = <0>; + bias-pull-up; + input-enable; + }; +}; + &pmk8350_rtc { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 245dce24ec59..e466dd839065 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2020, Linaro Limited */ +#include <dt-bindings/interconnect/qcom,sm8350.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/qcom,dispcc-sm8350.h> #include <dt-bindings/clock/qcom,gcc-sm8350.h> @@ -37,24 +38,6 @@ clock-frequency = <32000>; #clock-cells = <0>; }; - - ufs_phy_rx_symbol_0_clk: ufs-phy-rx-symbol-0 { - compatible = "fixed-clock"; - clock-frequency = <1000>; - #clock-cells = <0>; - }; - - ufs_phy_rx_symbol_1_clk: ufs-phy-rx-symbol-1 { - compatible = "fixed-clock"; - clock-frequency = <1000>; - #clock-cells = <0>; - }; - - ufs_phy_tx_symbol_0_clk: ufs-phy-tx-symbol-0 { - compatible = "fixed-clock"; - clock-frequency = <1000>; - #clock-cells = <0>; - }; }; cpus { @@ -73,9 +56,11 @@ #cooling-cells = <2>; L2_0: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; L3_0: l3-cache { compatible = "cache"; + cache-level = <3>; }; }; }; @@ -92,6 +77,7 @@ #cooling-cells = <2>; L2_100: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -108,6 +94,7 @@ #cooling-cells = <2>; L2_200: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -124,6 +111,7 @@ #cooling-cells = <2>; L2_300: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -140,6 +128,7 @@ #cooling-cells = <2>; L2_400: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -156,6 +145,7 @@ #cooling-cells = <2>; L2_500: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; @@ -173,6 +163,7 @@ #cooling-cells = <2>; L2_600: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -189,6 +180,7 @@ #cooling-cells = <2>; L2_700: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -288,55 +280,55 @@ compatible = "arm,psci-1.0"; method = "smc"; - CPU_PD0: cpu0 { + CPU_PD0: power-domain-cpu0 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; - CPU_PD1: cpu1 { + CPU_PD1: power-domain-cpu1 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; - CPU_PD2: cpu2 { + CPU_PD2: power-domain-cpu2 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; - CPU_PD3: cpu3 { + CPU_PD3: power-domain-cpu3 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; - CPU_PD4: cpu4 { + CPU_PD4: power-domain-cpu4 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&BIG_CPU_SLEEP_0>; }; - CPU_PD5: cpu5 { + CPU_PD5: power-domain-cpu5 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&BIG_CPU_SLEEP_0>; }; - CPU_PD6: cpu6 { + CPU_PD6: power-domain-cpu6 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&BIG_CPU_SLEEP_0>; }; - CPU_PD7: cpu7 { + CPU_PD7: power-domain-cpu7 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&BIG_CPU_SLEEP_0>; }; - CLUSTER_PD: cpu-cluster0 { + CLUSTER_PD: power-domain-cpu-cluster0 { #power-domain-cells = <0>; domain-idle-states = <&CLUSTER_SLEEP_0>; }; @@ -406,8 +398,10 @@ no-map; }; - smem_mem: memory@80900000 { + smem@80900000 { + compatible = "qcom,smem"; reg = <0x0 0x80900000 0x0 0x200000>; + hwlocks = <&tcsr_mutex 3>; no-map; }; @@ -516,12 +510,6 @@ }; }; - smem: qcom,smem { - compatible = "qcom,smem"; - memory-region = <&smem_mem>; - hwlocks = <&tcsr_mutex 3>; - }; - smp2p-adsp { compatible = "qcom,smp2p"; qcom,smem = <443>, <429>; @@ -656,14 +644,14 @@ "usb3_uni_phy_sec_gcc_usb30_pipe_clk"; clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, + <&pcie0_phy>, + <&pcie1_phy>, <0>, <0>, <0>, - <0>, - <0>, - <&ufs_phy_rx_symbol_0_clk>, - <&ufs_phy_rx_symbol_1_clk>, - <&ufs_phy_tx_symbol_0_clk>, + <&ufs_mem_phy_lanes 0>, + <&ufs_mem_phy_lanes 1>, + <&ufs_mem_phy_lanes 2>, <0>, <0>; }; @@ -1543,56 +1531,234 @@ config_noc: interconnect@1500000 { compatible = "qcom,sm8350-config-noc"; reg = <0 0x01500000 0 0xa580>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; mc_virt: interconnect@1580000 { compatible = "qcom,sm8350-mc-virt"; reg = <0 0x01580000 0 0x1000>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; system_noc: interconnect@1680000 { compatible = "qcom,sm8350-system-noc"; reg = <0 0x01680000 0 0x1c200>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; aggre1_noc: interconnect@16e0000 { compatible = "qcom,sm8350-aggre1-noc"; reg = <0 0x016e0000 0 0x1f180>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; aggre2_noc: interconnect@1700000 { compatible = "qcom,sm8350-aggre2-noc"; reg = <0 0x01700000 0 0x33000>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; mmss_noc: interconnect@1740000 { compatible = "qcom,sm8350-mmss-noc"; reg = <0 0x01740000 0 0x1f080>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; + pcie0: pci@1c00000 { + compatible = "qcom,pcie-sm8350"; + reg = <0 0x01c00000 0 0x3000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60001000 0 0x1000>, + <0 0x60100000 0 0x100000>; + reg-names = "parf", "dbi", "elbi", "atu", "config"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; + + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "tbu", + "ddrss_sf_tbu", + "aggre1", + "aggre0"; + + iommus = <&apps_smmu 0x1c00 0x7f>; + iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, + <0x100 &apps_smmu 0x1c01 0x1>; + + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "pci"; + + power-domains = <&gcc PCIE_0_GDSC>; + + phys = <&pcie0_phy>; + phy-names = "pciephy"; + + status = "disabled"; + }; + + pcie0_phy: phy@1c06000 { + compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy"; + reg = <0 0x01c06000 0 0x2000>; + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_CLKREF_EN>, + <&gcc GCC_PCIE0_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe"; + + resets = <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + #clock-cells = <0>; + clock-output-names = "pcie_0_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + + pcie1: pci@1c08000 { + compatible = "qcom,pcie-sm8350"; + reg = <0 0x01c08000 0 0x3000>, + <0 0x40000000 0 0xf1d>, + <0 0x40000f20 0 0xa8>, + <0 0x40001000 0 0x1000>, + <0 0x40100000 0 0x100000>; + reg-names = "parf", "dbi", "elbi", "atu", "config"; + device_type = "pci"; + linux,pci-domain = <1>; + bus-range = <0x00 0xff>; + num-lanes = <2>; + + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>; + + interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "tbu", + "ddrss_sf_tbu", + "aggre1"; + + iommus = <&apps_smmu 0x1c80 0x7f>; + iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, + <0x100 &apps_smmu 0x1c81 0x1>; + + resets = <&gcc GCC_PCIE_1_BCR>; + reset-names = "pci"; + + power-domains = <&gcc PCIE_1_GDSC>; + + phys = <&pcie1_phy>; + phy-names = "pciephy"; + + status = "disabled"; + }; + + pcie1_phy: phy@1c0f000 { + compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy"; + reg = <0 0x01c0e000 0 0x2000>; + clocks = <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_CLKREF_EN>, + <&gcc GCC_PCIE1_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_1_PIPE_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe"; + + resets = <&gcc GCC_PCIE_1_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + #clock-cells = <0>; + clock-output-names = "pcie_1_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + lpass_ag_noc: interconnect@3c40000 { compatible = "qcom,sm8350-lpass-ag-noc"; reg = <0 0x03c40000 0 0xf080>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; - compute_noc: interconnect@a0c0000{ + compute_noc: interconnect@a0c0000 { compatible = "qcom,sm8350-compute-noc"; reg = <0 0x0a0c0000 0 0xa180>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; @@ -1601,9 +1767,9 @@ iommus = <&apps_smmu 0x5c0 0x0>, <&apps_smmu 0x5c2 0x0>; - reg = <0 0x1e40000 0 0x8000>, - <0 0x1e50000 0 0x4b20>, - <0 0x1e04000 0 0x23000>; + reg = <0 0x01e40000 0 0x8000>, + <0 0x01e50000 0 0x4b20>, + <0 0x01e04000 0 0x23000>; reg-names = "ipa-reg", "ipa-shared", "gsi"; @@ -1620,8 +1786,8 @@ clocks = <&rpmhcc RPMH_IPA_CLK>; clock-names = "core"; - interconnects = <&aggre2_noc MASTER_IPA &mc_virt SLAVE_EBI1>, - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>; + interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; interconnect-names = "memory", "config"; @@ -1661,7 +1827,7 @@ <&rpmhpd SM8350_MSS>; power-domain-names = "cx", "mss"; - interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; + interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; memory-region = <&pil_modem_mem>; @@ -1717,7 +1883,7 @@ #thermal-sensor-cells = <1>; }; - aoss_qmp: power-controller@c300000 { + aoss_qmp: power-management@c300000 { compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp"; reg = <0 0x0c300000 0 0x400>; interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP @@ -1734,11 +1900,11 @@ spmi_bus: spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; - reg = <0x0 0xc440000 0x0 0x1100>, - <0x0 0xc600000 0x0 0x2000000>, - <0x0 0xe600000 0x0 0x100000>, - <0x0 0xe700000 0x0 0xa0000>, - <0x0 0xc40a000 0x0 0x26000>; + reg = <0x0 0x0c440000 0x0 0x1100>, + <0x0 0x0c600000 0x0 0x2000000>, + <0x0 0x0e600000 0x0 0x100000>, + <0x0 0x0e700000 0x0 0xa0000>, + <0x0 0x0c40a000 0x0 0x26000>; reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; interrupt-names = "periph_irq"; interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; @@ -2188,6 +2354,7 @@ <0 0x01d87c00 0 0x200>, <0 0x01d87800 0 0x188>, <0 0x01d87a00 0 0x200>; + #clock-cells = <1>; #phy-cells = <0>; }; }; @@ -2279,7 +2446,7 @@ <&rpmhpd SM8350_MXC>; power-domain-names = "cx", "mxc"; - interconnects = <&compute_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>; + interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; memory-region = <&pil_cdsp_mem>; @@ -2369,7 +2536,7 @@ }; }; - sdhc_2: sdhci@8804000 { + sdhc_2: mmc@8804000 { compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x08804000 0 0x1000>; @@ -2382,8 +2549,8 @@ <&rpmhcc RPMH_CXO_CLK>; clock-names = "iface", "core", "xo"; resets = <&gcc GCC_SDCC2_BCR>; - interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; + interconnects = <&aggre2_noc MASTER_SDCC_2 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_SDCC_2>; interconnect-names = "sdhc-ddr","cpu-sdhc"; iommus = <&apps_smmu 0x4a0 0x0>; power-domains = <&rpmhpd SM8350_CX>; @@ -2500,14 +2667,14 @@ dc_noc: interconnect@90c0000 { compatible = "qcom,sm8350-dc-noc"; reg = <0 0x090c0000 0 0x4200>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; gem_noc: interconnect@9100000 { compatible = "qcom,sm8350-gem-noc"; reg = <0 0x09100000 0 0xb4000>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; @@ -2615,14 +2782,302 @@ }; }; + mdss: display-subsystem@ae00000 { + compatible = "qcom,sm8350-mdss"; + reg = <0 0x0ae00000 0 0x1000>; + reg-names = "mdss"; + + interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, + <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + + power-domains = <&dispcc MDSS_GDSC>; + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "nrt_bus", "core"; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x820 0x402>; + + status = "disabled"; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* TODO: opp-200000000 should work with + * &rpmhpd_opp_low_svs, but one some of + * sm8350_hdk boards reboot using this + * opp. + */ + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-345000000 { + opp-hz = /bits/ 64 <345000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-460000000 { + opp-hz = /bits/ 64 <460000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + + mdss_mdp: display-controller@ae01000 { + compatible = "qcom,sm8350-dpu"; + reg = <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&dpu_opp_table>; + power-domains = <&rpmhpd SM8350_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + }; + }; + + mdss_dsi0: dsi@ae94000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae94000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>; + + operating-points-v2 = <&dsi0_opp_table>; + power-domains = <&rpmhpd SM8350_MMCX>; + + phys = <&mdss_dsi0_phy>; + + status = "disabled"; + + dsi0_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* TODO: opp-187500000 should work with + * &rpmhpd_opp_low_svs, but one some of + * sm8350_hdk boards reboot using this + * opp. + */ + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + mdss_dsi0_phy: phy@ae94400 { + compatible = "qcom,dsi-phy-5nm-8350"; + reg = <0 0x0ae94400 0 0x200>, + <0 0x0ae94600 0 0x280>, + <0 0x0ae94900 0 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + + mdss_dsi1: dsi@ae96000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae96000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>; + + operating-points-v2 = <&dsi1_opp_table>; + power-domains = <&rpmhpd SM8350_MMCX>; + + phys = <&mdss_dsi1_phy>; + + status = "disabled"; + + dsi1_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* TODO: opp-187500000 should work with + * &rpmhpd_opp_low_svs, but one some of + * sm8350_hdk boards reboot using this + * opp. + */ + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + }; + }; + + port@1 { + reg = <1>; + dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi1_phy: phy@ae96400 { + compatible = "qcom,dsi-phy-5nm-8350"; + reg = <0 0x0ae96400 0 0x200>, + <0 0x0ae96600 0 0x280>, + <0 0x0ae96900 0 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + }; + dispcc: clock-controller@af00000 { compatible = "qcom,sm8350-dispcc"; reg = <0 0x0af00000 0 0x10000>; clocks = <&rpmhcc RPMH_CXO_CLK>, - <0>, - <0>, - <0>, - <0>, + <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>, + <0>, <0>, <0>, <0>; clock-names = "bi_tcxo", @@ -2637,7 +3092,6 @@ #power-domain-cells = <1>; power-domains = <&rpmhpd SM8350_MMCX>; - power-domain-names = "mmcx"; }; adsp: remoteproc@17300000 { @@ -2728,7 +3182,7 @@ type = "passive"; }; - cpu0_crit: cpu_crit { + cpu0_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -2772,7 +3226,7 @@ type = "passive"; }; - cpu1_crit: cpu_crit { + cpu1_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -2816,7 +3270,7 @@ type = "passive"; }; - cpu2_crit: cpu_crit { + cpu2_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -2860,7 +3314,7 @@ type = "passive"; }; - cpu3_crit: cpu_crit { + cpu3_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -2904,7 +3358,7 @@ type = "passive"; }; - cpu4_top_crit: cpu_crit { + cpu4_top_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -2948,7 +3402,7 @@ type = "passive"; }; - cpu5_top_crit: cpu_crit { + cpu5_top_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -2992,7 +3446,7 @@ type = "passive"; }; - cpu6_top_crit: cpu_crit { + cpu6_top_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -3036,7 +3490,7 @@ type = "passive"; }; - cpu7_top_crit: cpu_crit { + cpu7_top_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -3080,7 +3534,7 @@ type = "passive"; }; - cpu4_bottom_crit: cpu_crit { + cpu4_bottom_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -3124,7 +3578,7 @@ type = "passive"; }; - cpu5_bottom_crit: cpu_crit { + cpu5_bottom_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -3168,7 +3622,7 @@ type = "passive"; }; - cpu6_bottom_crit: cpu_crit { + cpu6_bottom_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -3212,7 +3666,7 @@ type = "passive"; }; - cpu7_bottom_crit: cpu_crit { + cpu7_bottom_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index 4de3e1f1c39c..5bdc2c1159ae 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -8,6 +8,13 @@ #include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> #include "sm8450.dtsi" +#include "pm8350.dtsi" +#include "pm8350b.dtsi" +#include "pm8350c.dtsi" +#include "pm8450.dtsi" +#include "pmk8350.dtsi" +#include "pmr735a.dtsi" +#include "pmr735b.dtsi" / { model = "Qualcomm Technologies, Inc. SM8450 HDK"; @@ -17,10 +24,69 @@ serial0 = &uart7; }; + wcd938x: audio-codec { + compatible = "qcom,wcd9380-codec"; + + pinctrl-names = "default"; + pinctrl-0 = <&wcd_default>; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + reset-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>; + + vdd-buck-supply = <&vreg_s10b_1p8>; + vdd-rxtx-supply = <&vreg_s10b_1p8>; + vdd-io-supply = <&vreg_s10b_1p8>; + vdd-mic-bias-supply = <&vreg_bob>; + + #sound-dai-cells = <1>; + }; + chosen { stdout-path = "serial0:115200n8"; }; + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_connector_out: endpoint { + remote-endpoint = <<9611_out>; + }; + }; + }; + + lt9611_1v2: lt9611-vdd12-regulator { + compatible = "regulator-fixed"; + regulator-name = "LT9611_1V2"; + + vin-supply = <&vph_pwr>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&tlmm 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + lt9611_3v3: lt9611-3v3-regulator { + compatible = "regulator-fixed"; + regulator-name = "LT9611_3V3"; + + vin-supply = <&vreg_bob>; + gpio = <&tlmm 109 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; @@ -350,6 +416,74 @@ }; }; +&dispcc { + status = "okay"; +}; + +&i2c9 { + clock-frequency = <400000>; + status = "okay"; + + lt9611_codec: hdmi-bridge@2b { + compatible = "lontium,lt9611uxc"; + reg = <0x2b>; + + interrupts-extended = <&tlmm 44 IRQ_TYPE_EDGE_FALLING>; + + reset-gpios = <&tlmm 107 GPIO_ACTIVE_HIGH>; + + vdd-supply = <<9611_1v2>; + vcc-supply = <<9611_3v3>; + + pinctrl-names = "default"; + pinctrl-0 = <<9611_irq_pin <9611_rst_pin>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lt9611_a: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + + port@2 { + reg = <2>; + + lt9611_out: endpoint { + remote-endpoint = <&hdmi_connector_out>; + }; + }; + }; + }; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&vreg_l6b_1p2>; + status = "okay"; +}; + +&mdss_dsi0_out { + remote-endpoint = <<9611_a>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vreg_l5b_0p88>; + status = "okay"; +}; + +&mdss_mdp { + status = "okay"; +}; + &pcie0 { status = "okay"; max-link-speed = <2>; @@ -395,6 +529,10 @@ status = "okay"; }; +&qupv3_id_1 { + status = "okay"; +}; + &sdhc_2 { cd-gpios = <&tlmm 92 GPIO_ACTIVE_HIGH>; pinctrl-names = "default", "sleep"; @@ -407,33 +545,6 @@ status = "okay"; }; -&soc { - wcd938x: codec { - compatible = "qcom,wcd9380-codec"; - - pinctrl-names = "default"; - pinctrl-0 = <&wcd_default>; - - qcom,micbias1-microvolt = <1800000>; - qcom,micbias2-microvolt = <1800000>; - qcom,micbias3-microvolt = <1800000>; - qcom,micbias4-microvolt = <1800000>; - qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; - qcom,mbhc-headset-vthreshold-microvolt = <1700000>; - qcom,mbhc-headphone-vthreshold-microvolt = <50000>; - qcom,rx-device = <&wcd_rx>; - qcom,tx-device = <&wcd_tx>; - - reset-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>; - #sound-dai-cells = <1>; - - vdd-buck-supply = <&vreg_s10b_1p8>; - vdd-rxtx-supply = <&vreg_s10b_1p8>; - vdd-io-supply = <&vreg_s10b_1p8>; - vdd-mic-bias-supply = <&vreg_bob>; - }; -}; - &sound { compatible = "qcom,sm8450-sndcard"; model = "SM8450-HDK"; @@ -516,6 +627,8 @@ }; &swr0 { + status = "okay"; + left_spkr: speaker@0,1 { compatible = "sdw10217020200"; reg = <0 1>; @@ -564,6 +677,18 @@ &tlmm { gpio-reserved-ranges = <28 4>, <36 4>; + lt9611_irq_pin: lt9611-irq-state { + pins = "gpio44"; + function = "gpio"; + bias-disable; + }; + + lt9611_rst_pin: lt9611-rst-state { + pins = "gpio107"; + function = "gpio"; + output-high; + }; + sdc2_card_det_n: sd-card-det-n-state { pins = "gpio92"; function = "gpio"; @@ -622,6 +747,8 @@ pinctrl-names = "default"; vdd-micb-supply = <&vreg_s10b_1p8>; qcom,dmic-sample-rate = <600000>; + + status = "okay"; }; &tlmm { diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts index ee62514fff68..134ffdfc2c63 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -7,6 +7,13 @@ #include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include "sm8450.dtsi" +#include "pm8350.dtsi" +#include "pm8350b.dtsi" +#include "pm8350c.dtsi" +#include "pm8450.dtsi" +#include "pmk8350.dtsi" +#include "pmr735a.dtsi" +#include "pmr735b.dtsi" / { model = "Qualcomm Technologies, Inc. SM8450 QRD"; diff --git a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx223.dts b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx223.dts index b83500316a81..daf2f91f356e 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx223.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx223.dts @@ -11,6 +11,67 @@ / { model = "Sony Xperia 1 IV"; compatible = "sony,pdx223", "qcom,sm8450"; + + imx316_lvdd_regulator: imx316-lvdd-regulator { + compatible = "regulator-fixed"; + regulator-name = "imx316_lvdd_regulator"; + gpio = <&pm8350b_gpios 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&cam_pwr_ld_en>; + }; + + tcs3490_vdd_regulator: rgbcir-vdd-regulator { + compatible = "regulator-fixed"; + regulator-name = "tcs3490_vdd_regulator"; + gpio = <&pm8350c_gpios 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&rgbc_ir_pwr_en>; + }; +}; + +&pm8350b_gpios { + gpio-line-names = "CAM_PWR_A_CS", /* GPIO_1 */ + "NC", + "NC", + "NC", + "SNAPSHOT_N", + "CAM_PWR_LD_EN", + "NC", + "FOCUS_N"; + + cam_pwr_ld_en: cam-pwr-ld-en-state { + pins = "gpio6"; + function = "normal"; + qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>; + power-source = <0>; + drive-push-pull; + output-low; + }; +}; + +&pm8350c_gpios { + gpio-line-names = "FL_STROBE_TRIG_WIDE", /* GPIO_1 */ + "FL_STROBE_TRIG_TELE", + "WLC_ID", + "WLC_TXPWR_EN", + "NC", + "RGBC_IR_PWR_EN", + "NC", + "NC", + "WIDEC_PWR_EN"; + + rgbc_ir_pwr_en: rgbc-ir-pwr-en-state { + pins = "gpio6"; + function = "normal"; + qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>; + power-source = <1>; + drive-push-pull; + output-low; + }; }; &tlmm { diff --git a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx224.dts b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx224.dts index 13c2fc4bccfc..dc4de2d3fe48 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx224.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx224.dts @@ -12,14 +12,40 @@ model = "Sony Xperia 5 IV"; compatible = "sony,pdx224", "qcom,sm8450"; - imx563_vdig_vreg: imx563-vdig-regulator { + imx563_vdig_regulator: imx563-vdig-regulator { compatible = "regulator-fixed"; - regulator-name = "imx563_vdig_vreg"; + regulator-name = "imx563_vdig_regulator"; gpio = <&tlmm 22 GPIO_ACTIVE_HIGH>; enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&uwidec_pwr_en>; }; }; +&pm8350b_gpios { + gpio-line-names = "CAM_PWR_A_CS", /* GPIO_1 */ + "NC", + "NC", + "NC", + "SNAPSHOT_N", + "NC", + "NC", + "FOCUS_N"; +}; + +&pm8350c_gpios { + gpio-line-names = "FL_STROBE_TRIG_WIDE", /* GPIO_1 */ + "FL_STROBE_TRIG_TELE", + "WLC_ID", + "WLC_TXPWR_EN", + "NC", + "NC", /* RGBCIR uses a PMIC vreg, so it's most likely NC. */ + "NC", + "NC", + "WIDEC_PWR_EN"; +}; + &tlmm { gpio-line-names = "TELE_SPI_MISO", /* GPIO_0 */ "TELE_SPI_MOSI", /* SONY says NC, but it only makes sense this way.. */ @@ -231,4 +257,12 @@ "APPS_I2C_0_SCL", "CCI_I2C3_SDA", "CCI_I2C3_SCL"; + + uwidec_pwr_en: uwidec-pwr-en-state { + pins = "gpio22"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi index 38256226d229..53d0ee2dbfa9 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi @@ -3,8 +3,15 @@ * Copyright (c) 2022, Konrad Dybcio <konrad.dybcio@somainline.org> */ +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> #include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include "sm8450.dtsi" +#include "pm8350.dtsi" +#include "pm8350b.dtsi" +#include "pm8350c.dtsi" +#include "pm8450.dtsi" +#include "pmk8350.dtsi" +#include "pmr735a.dtsi" /delete-node/ &adsp_mem; /delete-node/ &rmtfs_mem; @@ -21,6 +28,41 @@ stdout-path = "serial0:115200n8"; }; + gpio-keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&focus_n &snapshot_n &vol_down_n>; + + key-camera-focus { + label = "Camera Focus"; + linux,code = <KEY_CAMERA_FOCUS>; + gpios = <&pm8350b_gpios 8 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + + key-camera-snapshot { + label = "Camera Snapshot"; + linux,code = <KEY_CAMERA>; + gpios = <&pm8350b_gpios 5 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + + key-volume-down { + label = "Volume Down"; + linux,code = <KEY_VOLUMEDOWN>; + gpios = <&pm8350_gpios 6 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + }; + reserved-memory { adsp_mem: memory@85700000 { reg = <0x0 0x85700000 0x0 0x2800000>; @@ -52,11 +94,14 @@ }; /* Sadly, the voltages for these GPIO regulators are unknown. */ - imx650_vana_vreg: imx650-vana-regulator { + imx650_vana_regulator: imx650-vana-regulator { compatible = "regulator-fixed"; - regulator-name = "imx650_vana_vreg"; + regulator-name = "imx650_vana_regulator"; gpio = <&tlmm 23 GPIO_ACTIVE_HIGH>; enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&telec_pwr_en>; }; vph_pwr: vph-pwr-regulator { @@ -456,7 +501,58 @@ clock-frequency = <400000>; status = "okay"; - /* Dialog SLG51000 CMIC @ 75 */ + pmic@75 { + compatible = "dlg,slg51000"; + reg = <0x75>; + dlg,cs-gpios = <&pm8350b_gpios 1 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&cam_pwr_a_cs>; + + regulators { + slg51000_a_ldo1: ldo1 { + regulator-name = "slg51000_a_ldo1"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3300000>; + }; + + slg51000_a_ldo2: ldo2 { + regulator-name = "slg51000_a_ldo2"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3300000>; + }; + + slg51000_a_ldo3: ldo3 { + regulator-name = "slg51000_a_ldo3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + }; + + slg51000_a_ldo4: ldo4 { + regulator-name = "slg51000_a_ldo4"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + }; + + slg51000_a_ldo5: ldo5 { + regulator-name = "slg51000_a_ldo5"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1200000>; + }; + + slg51000_a_ldo6: ldo6 { + regulator-name = "slg51000_a_ldo6"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1200000>; + }; + + slg51000_a_ldo7: ldo7 { + regulator-name = "slg51000_a_ldo7"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + }; + }; + }; }; &i2c9 { @@ -466,13 +562,6 @@ /* NXP SN1X0 NFC @ 28 */ }; -&i2c13 { - clock-frequency = <400000>; - status = "okay"; - - /* Richwave RTC6226 FM Radio Receiver @ 64 */ -}; - &i2c14 { clock-frequency = <1000000>; status = "okay"; @@ -533,6 +622,77 @@ status = "okay"; }; +&pm8350_gpios { + gpio-line-names = "ASSIGN1_THERM", /* GPIO_1 */ + "LCD_ID", + "SDR_MMW_THERM", + "RF_ID", + "NC", + "VOL_DOWN_N", + "NC", + "NC", + "NC", + "PM8350_OPTION"; /* GPIO_10 */ + + vol_down_n: vol-down-n-state { + pins = "gpio6"; + function = "normal"; + power-source = <1>; + bias-pull-up; + input-enable; + }; +}; + +&pm8350b_gpios { + cam_pwr_a_cs: cam-pwr-a-cs-state { + pins = "gpio1"; + function = "normal"; + qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>; + power-source = <1>; + drive-push-pull; + output-high; + }; + + snapshot_n: snapshot-n-state { + pins = "gpio5"; + function = "normal"; + power-source = <0>; + bias-pull-up; + input-enable; + }; + + focus_n: focus-n-state { + pins = "gpio8"; + function = "normal"; + power-source = <0>; + bias-pull-up; + input-enable; + }; +}; + +&pm8450_gpios { + gpio-line-names = "FP_LDO_EN", /* GPIO_1 */ + "", + "", + ""; +}; + +&pmk8350_gpios { + gpio-line-names = "NC", /* GPIO_1 */ + "NC", + "DISP_THERM", + "PMK8350_OPTION"; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = <KEY_VOLUMEUP>; + status = "okay"; +}; + &remoteproc_adsp { firmware-name = "qcom/sm8350/Sony/nagara/adsp.mbn"; status = "okay"; @@ -597,6 +757,14 @@ input-enable; }; + telec_pwr_en: telec-pwr-en-state { + pins = "gpio23"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + sdc2_card_det_n: sd-card-det-n-state { pins = "gpio92"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 570475040d95..d66dcd8fe61f 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -57,9 +57,11 @@ clocks = <&cpufreq_hw 0>; L2_0: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; L3_0: l3-cache { compatible = "cache"; + cache-level = <3>; }; }; }; @@ -77,6 +79,7 @@ clocks = <&cpufreq_hw 0>; L2_100: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -94,6 +97,7 @@ clocks = <&cpufreq_hw 0>; L2_200: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -111,6 +115,7 @@ clocks = <&cpufreq_hw 0>; L2_300: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -128,6 +133,7 @@ clocks = <&cpufreq_hw 1>; L2_400: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -145,6 +151,7 @@ clocks = <&cpufreq_hw 1>; L2_500: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; @@ -163,6 +170,7 @@ clocks = <&cpufreq_hw 1>; L2_600: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -180,6 +188,7 @@ clocks = <&cpufreq_hw 2>; L2_700: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -270,6 +279,7 @@ firmware { scm: scm { compatible = "qcom,scm-sm8450", "qcom,scm"; + qcom,dload-mode = <&tcsr 0x13000>; interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; #reset-cells = <1>; }; @@ -302,55 +312,55 @@ compatible = "arm,psci-1.0"; method = "smc"; - CPU_PD0: cpu0 { + CPU_PD0: power-domain-cpu0 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; - CPU_PD1: cpu1 { + CPU_PD1: power-domain-cpu1 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; - CPU_PD2: cpu2 { + CPU_PD2: power-domain-cpu2 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; - CPU_PD3: cpu3 { + CPU_PD3: power-domain-cpu3 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; - CPU_PD4: cpu4 { + CPU_PD4: power-domain-cpu4 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&BIG_CPU_SLEEP_0>; }; - CPU_PD5: cpu5 { + CPU_PD5: power-domain-cpu5 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&BIG_CPU_SLEEP_0>; }; - CPU_PD6: cpu6 { + CPU_PD6: power-domain-cpu6 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&BIG_CPU_SLEEP_0>; }; - CPU_PD7: cpu7 { + CPU_PD7: power-domain-cpu7 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&BIG_CPU_SLEEP_0>; }; - CLUSTER_PD: cpu-cluster0 { + CLUSTER_PD: power-domain-cpu-cluster0 { #power-domain-cells = <0>; domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>; }; @@ -731,19 +741,29 @@ #reset-cells = <1>; #power-domain-cells = <1>; clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, <&pcie0_lane>, <&pcie1_lane>, - <&sleep_clk>; + <0>, + <&ufs_mem_phy_lanes 0>, + <&ufs_mem_phy_lanes 1>, + <&ufs_mem_phy_lanes 2>, + <0>; clock-names = "bi_tcxo", + "sleep_clk", "pcie_0_pipe_clk", "pcie_1_pipe_clk", - "sleep_clk"; + "pcie_1_phy_aux_clk", + "ufs_phy_rx_symbol_0_clk", + "ufs_phy_rx_symbol_1_clk", + "ufs_phy_tx_symbol_0_clk", + "usb3_phy_wrapper_gcc_usb30_pipe_clk"; }; gpi_dma2: dma-controller@800000 { compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; #dma-cells = <3>; - reg = <0 0x800000 0 0x60000>; + reg = <0 0x00800000 0 0x60000>; interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, @@ -1064,7 +1084,7 @@ gpi_dma0: dma-controller@900000 { compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; #dma-cells = <3>; - reg = <0 0x900000 0 0x60000>; + reg = <0 0x00900000 0 0x60000>; interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, @@ -1345,7 +1365,7 @@ i2c6: i2c@998000 { compatible = "qcom,geni-i2c"; - reg = <0x0 0x998000 0x0 0x4000>; + reg = <0x0 0x00998000 0x0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; pinctrl-names = "default"; @@ -1365,7 +1385,7 @@ spi6: spi@998000 { compatible = "qcom,geni-spi"; - reg = <0x0 0x998000 0x0 0x4000>; + reg = <0x0 0x00998000 0x0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; @@ -1400,7 +1420,7 @@ gpi_dma1: dma-controller@a00000 { compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; #dma-cells = <3>; - reg = <0 0xa00000 0 0x60000>; + reg = <0 0x00a00000 0 0x60000>; interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, @@ -1733,6 +1753,13 @@ ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; + /* + * MSIs for BDF (1:0.0) only works with Device ID 0x5980. + * Hence, the IDs are swapped. + */ + msi-map = <0x0 &gic_its 0x5981 0x1>, + <0x100 &gic_its 0x5980 0x1>; + msi-map-mask = <0xff00>; interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "msi"; #interrupt-cells = <1>; @@ -1810,10 +1837,10 @@ status = "disabled"; pcie0_lane: phy@1c06200 { - reg = <0 0x1c06e00 0 0x200>, /* tx */ - <0 0x1c07000 0 0x200>, /* rx */ - <0 0x1c06200 0 0x200>, /* pcs */ - <0 0x1c06600 0 0x200>; /* pcs_pcie */ + reg = <0 0x01c06e00 0 0x200>, /* tx */ + <0 0x01c07000 0 0x200>, /* rx */ + <0 0x01c06200 0 0x200>, /* pcs */ + <0 0x01c06600 0 0x200>; /* pcs_pcie */ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; clock-names = "pipe0"; @@ -1842,6 +1869,13 @@ ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>, <0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>; + /* + * MSIs for BDF (1:0.0) only works with Device ID 0x5a00. + * Hence, the IDs are swapped. + */ + msi-map = <0x0 &gic_its 0x5a01 0x1>, + <0x100 &gic_its 0x5a00 0x1>; + msi-map-mask = <0xff00>; interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "msi"; #interrupt-cells = <1>; @@ -1917,12 +1951,12 @@ status = "disabled"; pcie1_lane: phy@1c0e000 { - reg = <0 0x1c0e000 0 0x200>, /* tx */ - <0 0x1c0e200 0 0x300>, /* rx */ - <0 0x1c0f200 0 0x200>, /* pcs */ - <0 0x1c0e800 0 0x200>, /* tx */ - <0 0x1c0ea00 0 0x300>, /* rx */ - <0 0x1c0f400 0 0xc00>; /* pcs_pcie */ + reg = <0 0x01c0e000 0 0x200>, /* tx */ + <0 0x01c0e200 0 0x300>, /* rx */ + <0 0x01c0f200 0 0x200>, /* pcs */ + <0 0x01c0e800 0 0x200>, /* tx */ + <0 0x01c0ea00 0 0x300>, /* rx */ + <0 0x01c0f400 0 0xc00>; /* pcs_pcie */ clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; clock-names = "pipe0"; @@ -1986,6 +2020,11 @@ #hwlock-cells = <1>; }; + tcsr: syscon@1fc0000 { + compatible = "qcom,sm8450-tcsr", "syscon"; + reg = <0x0 0x1fc0000 0x0 0x30000>; + }; + usb_1_hsphy: phy@88e3000 { compatible = "qcom,sm8450-usb-hs-phy", "qcom,usb-snps-hs-7nm-phy"; @@ -2143,11 +2182,12 @@ #address-cells = <2>; #size-cells = <0>; #sound-dai-cells = <1>; + status = "disabled"; }; rxmacro: codec@3200000 { compatible = "qcom,sm8450-lpass-rx-macro"; - reg = <0 0x3200000 0 0x1000>; + reg = <0 0x03200000 0 0x1000>; clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, @@ -2168,7 +2208,7 @@ swr1: soundwire-controller@3210000 { compatible = "qcom,soundwire-v1.7.0"; - reg = <0 0x3210000 0 0x2000>; + reg = <0 0x03210000 0 0x2000>; interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rxmacro>; clock-names = "iface"; @@ -2189,11 +2229,12 @@ #address-cells = <2>; #size-cells = <0>; #sound-dai-cells = <1>; + status = "disabled"; }; txmacro: codec@3220000 { compatible = "qcom,sm8450-lpass-tx-macro"; - reg = <0 0x3220000 0 0x1000>; + reg = <0 0x03220000 0 0x1000>; clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, @@ -2256,14 +2297,15 @@ #address-cells = <2>; #size-cells = <0>; #sound-dai-cells = <1>; + status = "disabled"; }; swr2: soundwire-controller@33b0000 { compatible = "qcom,soundwire-v1.7.0"; - reg = <0 0x33b0000 0 0x2000>; + reg = <0 0x033b0000 0 0x2000>; interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "core", "wake"; + interrupt-names = "core", "wakeup"; clocks = <&vamacro>; clock-names = "iface"; @@ -2284,6 +2326,7 @@ #address-cells = <2>; #size-cells = <0>; #sound-dai-cells = <1>; + status = "disabled"; }; vamacro: codec@33f0000 { @@ -2300,6 +2343,7 @@ #clock-cells = <0>; clock-output-names = "fsgen"; #sound-dai-cells = <1>; + status = "disabled"; }; remoteproc_adsp: remoteproc@30000000 { @@ -2554,8 +2598,8 @@ }; cci0: cci@ac15000 { - compatible = "qcom,sm8450-cci"; - reg = <0 0xac15000 0 0x1000>; + compatible = "qcom,sm8450-cci", "qcom,msm8996-cci"; + reg = <0 0x0ac15000 0 0x1000>; interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; power-domains = <&camcc TITAN_TOP_GDSC>; @@ -2593,8 +2637,8 @@ }; cci1: cci@ac16000 { - compatible = "qcom,sm8450-cci"; - reg = <0 0xac16000 0 0x1000>; + compatible = "qcom,sm8450-cci", "qcom,msm8996-cci"; + reg = <0 0x0ac16000 0 0x1000>; interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; power-domains = <&camcc TITAN_TOP_GDSC>; @@ -2646,6 +2690,281 @@ status = "disabled"; }; + mdss: display-subsystem@ae00000 { + compatible = "qcom,sm8450-mdss"; + reg = <0 0x0ae00000 0 0x1000>; + reg-names = "mdss"; + + /* same path used twice */ + interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>, + <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x2800 0x402>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + mdss_mdp: display-controller@ae01000 { + compatible = "qcom,sm8450-dpu"; + reg = <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SM8450_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&mdss_dsi1_in>; + }; + }; + + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-172000000 { + opp-hz = /bits/ 64 <172000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-325000000 { + opp-hz = /bits/ 64 <325000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_dsi0: dsi@ae94000 { + compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae94000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + + operating-points-v2 = <&mdss_dsi_opp_table>; + power-domains = <&rpmhpd SM8450_MMCX>; + + phys = <&mdss_dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi0_out: endpoint { + }; + }; + }; + + mdss_dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss_dsi0_phy: phy@ae94400 { + compatible = "qcom,dsi-phy-5nm-8450"; + reg = <0 0x0ae94400 0 0x200>, + <0 0x0ae94600 0 0x280>, + <0 0x0ae94900 0 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + + mdss_dsi1: dsi@ae96000 { + compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae96000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; + + operating-points-v2 = <&mdss_dsi_opp_table>; + power-domains = <&rpmhpd SM8450_MMCX>; + + phys = <&mdss_dsi1_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi1_phy: phy@ae96400 { + compatible = "qcom,dsi-phy-5nm-8450"; + reg = <0 0x0ae96400 0 0x200>, + <0 0x0ae96600 0 0x280>, + <0 0x0ae96900 0 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + }; + dispcc: clock-controller@af00000 { compatible = "qcom,sm8450-dispcc"; reg = <0 0x0af00000 0 0x20000>; @@ -2653,10 +2972,10 @@ <&rpmhcc RPMH_CXO_CLK_A>, <&gcc GCC_DISP_AHB_CLK>, <&sleep_clk>, - <0>, /* dsi0 */ - <0>, - <0>, /* dsi1 */ - <0>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>, <0>, /* dp0 */ <0>, <0>, /* dp1 */ @@ -2705,7 +3024,7 @@ #thermal-sensor-cells = <1>; }; - aoss_qmp: power-controller@c300000 { + aoss_qmp: power-management@c300000 { compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp"; reg = <0 0x0c300000 0 0x400>; interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP @@ -2715,6 +3034,28 @@ #clock-cells = <0>; }; + spmi_bus: spmi@c400000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0 0x0c400000 0 0x00003000>, + <0 0x0c500000 0 0x00400000>, + <0 0x0c440000 0 0x00080000>, + <0 0x0c4c0000 0 0x00010000>, + <0 0x0c42d000 0 0x00010000>; + reg-names = "core", + "chnls", + "obsrvr", + "intr", + "cnfg"; + interrupt-names = "periph_irq"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + qcom,ee = <0>; + qcom,channel = <0>; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + }; + ipcc: mailbox@ed18000 { compatible = "qcom,sm8450-ipcc", "qcom,ipcc"; reg = <0 0x0ed18000 0 0x1000>; @@ -3235,10 +3576,10 @@ }; - lpass_tlmm: pinctrl@3440000{ + lpass_tlmm: pinctrl@3440000 { compatible = "qcom,sm8450-lpass-lpi-pinctrl"; - reg = <0 0x3440000 0x0 0x20000>, - <0 0x34d0000 0x0 0x10000>; + reg = <0 0x03440000 0x0 0x20000>, + <0 0x034d0000 0x0 0x10000>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&lpass_tlmm 0 0 23>; @@ -3580,35 +3921,39 @@ opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; }; - rpmhpd_opp_low_svs: opp3 { + rpmhpd_opp_low_svs_d1: opp3 { + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; + }; + + rpmhpd_opp_low_svs: opp4 { opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; }; - rpmhpd_opp_svs: opp4 { + rpmhpd_opp_svs: opp5 { opp-level = <RPMH_REGULATOR_LEVEL_SVS>; }; - rpmhpd_opp_svs_l1: opp5 { + rpmhpd_opp_svs_l1: opp6 { opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; }; - rpmhpd_opp_nom: opp6 { + rpmhpd_opp_nom: opp7 { opp-level = <RPMH_REGULATOR_LEVEL_NOM>; }; - rpmhpd_opp_nom_l1: opp7 { + rpmhpd_opp_nom_l1: opp8 { opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; }; - rpmhpd_opp_nom_l2: opp8 { + rpmhpd_opp_nom_l2: opp9 { opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; }; - rpmhpd_opp_turbo: opp9 { + rpmhpd_opp_turbo: opp10 { opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; }; - rpmhpd_opp_turbo_l1: opp10 { + rpmhpd_opp_turbo_l1: opp11 { opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; }; }; @@ -3720,6 +4065,7 @@ <0 0x01d87c00 0 0x200>, <0 0x01d87800 0 0x188>, <0 0x01d87a00 0 0x200>; + #clock-cells = <1>; #phy-cells = <0>; }; }; @@ -3825,7 +4171,7 @@ lpass_ag_noc: interconnect@3c40000 { compatible = "qcom,sm8450-lpass-ag-noc"; - reg = <0 0x3c40000 0 0x17200>; + reg = <0 0x03c40000 0 0x17200>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; @@ -3953,7 +4299,7 @@ type = "passive"; }; - cpu4_top_crit: cpu_crit { + cpu4_top_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -3979,7 +4325,7 @@ type = "passive"; }; - cpu4_bottom_crit: cpu_crit { + cpu4_bottom_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -4005,7 +4351,7 @@ type = "passive"; }; - cpu5_top_crit: cpu_crit { + cpu5_top_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -4031,7 +4377,7 @@ type = "passive"; }; - cpu5_bottom_crit: cpu_crit { + cpu5_bottom_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -4057,7 +4403,7 @@ type = "passive"; }; - cpu6_top_crit: cpu_crit { + cpu6_top_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -4083,7 +4429,7 @@ type = "passive"; }; - cpu6_bottom_crit: cpu_crit { + cpu6_bottom_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -4109,7 +4455,7 @@ type = "passive"; }; - cpu7_top_crit: cpu_crit { + cpu7_top_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -4135,7 +4481,7 @@ type = "passive"; }; - cpu7_middle_crit: cpu_crit { + cpu7_middle_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -4161,7 +4507,7 @@ type = "passive"; }; - cpu7_bottom_crit: cpu_crit { + cpu7_bottom_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -4193,7 +4539,7 @@ type = "passive"; }; - gpu0_tj_cfg: tj_cfg { + gpu0_tj_cfg: tj-cfg { temperature = <95000>; hysteresis = <5000>; type = "passive"; @@ -4225,7 +4571,7 @@ type = "passive"; }; - gpu1_tj_cfg: tj_cfg { + gpu1_tj_cfg: tj-cfg { temperature = <95000>; hysteresis = <5000>; type = "passive"; @@ -4271,7 +4617,7 @@ type = "passive"; }; - cpu0_crit: cpu_crit { + cpu0_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -4297,7 +4643,7 @@ type = "passive"; }; - cpu1_crit: cpu_crit { + cpu1_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -4323,7 +4669,7 @@ type = "passive"; }; - cpu2_crit: cpu_crit { + cpu2_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -4349,7 +4695,7 @@ type = "passive"; }; - cpu3_crit: cpu_crit { + cpu3_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts new file mode 100644 index 000000000000..725d3bc3ee72 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -0,0 +1,568 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Linaro Limited + */ + +/dts-v1/; + +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> +#include "sm8550.dtsi" +#include "pm8010.dtsi" +#include "pm8550.dtsi" +#include "pm8550b.dtsi" +#include "pm8550ve.dtsi" +#include "pm8550vs.dtsi" +#include "pmk8550.dtsi" +#include "pmr735d.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM8550 MTP"; + compatible = "qcom,sm8550-mtp", "qcom,sm8550"; + + aliases { + serial0 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-bob1-supply = <&vph_pwr>; + vdd-bob2-supply = <&vph_pwr>; + vdd-l2-l13-l14-supply = <&vreg_bob1>; + vdd-l3-supply = <&vreg_s4g_1p3>; + vdd-l6-l16-supply = <&vreg_bob1>; + vdd-l6-l7-supply = <&vreg_bob1>; + vdd-l8-l9-supply = <&vreg_bob1>; + vdd-l11-supply = <&vreg_s4g_1p3>; + vdd-l12-supply = <&vreg_s6g_1p8>; + vdd-l15-supply = <&vreg_s6g_1p8>; + vdd-l17-supply = <&vreg_bob2>; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2720000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name = "vreg_l1b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l5b_3p1: ldo5 { + regulator-name = "vreg_l5b_3p1"; + regulator-min-microvolt = <3104000>; + regulator-max-microvolt = <3104000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name = "vreg_l6b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7b_1p8: ldo7 { + regulator-name = "vreg_l7b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l8b_1p8: ldo8 { + regulator-name = "vreg_l8b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name = "vreg_l9b_2p9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l11b_1p2: ldo11 { + regulator-name = "vreg_l11b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1504000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l12b_1p8: ldo12 { + regulator-name = "vreg_l12b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name = "vreg_l13b_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l14b_3p2: ldo14 { + regulator-name = "vreg_l14b_3p2"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l16b_2p8: ldo16 { + regulator-name = "vreg_l16b_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name = "vreg_l17b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-l3-supply = <&vreg_s4e_0p9>; + + vreg_l3c_0p91: ldo3 { + regulator-name = "vreg_l3c_0p9"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-2 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "d"; + + vdd-l1-supply = <&vreg_s4e_0p9>; + + vreg_l1d_0p88: ldo1 { + regulator-name = "vreg_l1d_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-3 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-l1-supply = <&vreg_s4e_0p9>; + vdd-l2-supply = <&vreg_s4e_0p9>; + vdd-l3-supply = <&vreg_s4g_1p3>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + + vreg_s4e_0p9: smps4 { + regulator-name = "vreg_s4e_0p9"; + regulator-min-microvolt = <904000>; + regulator-max-microvolt = <984000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s5e_1p1: smps5 { + regulator-name = "vreg_s5e_1p1"; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1120000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1e_0p88: ldo1 { + regulator-name = "vreg_l1e_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2e_0p9: ldo2 { + regulator-name = "vreg_l2e_0p9"; + regulator-min-microvolt = <904000>; + regulator-max-microvolt = <970000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name = "vreg_l3e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-4 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "f"; + + vdd-l1-supply = <&vreg_s4e_0p9>; + vdd-l2-supply = <&vreg_s4e_0p9>; + vdd-l3-supply = <&vreg_s4e_0p9>; + vdd-s4-supply = <&vph_pwr>; + + vreg_s4f_0p5: smps4 { + regulator-name = "vreg_s4f_0p5"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <700000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1f_0p9: ldo1 { + regulator-name = "vreg_l1f_0p9"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2f_0p88: ldo2 { + regulator-name = "vreg_l2f_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3f_0p91: ldo3 { + regulator-name = "vreg_l3f_0p91"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-5 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "g"; + + vdd-l1-supply = <&vreg_s4g_1p3>; + vdd-l2-supply = <&vreg_s4g_1p3>; + vdd-l3-supply = <&vreg_s4g_1p3>; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + + vreg_s1g_1p2: smps1 { + regulator-name = "vreg_s1g_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s2g_0p8: smps2 { + regulator-name = "vreg_s2g_0p8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s3g_0p7: smps3 { + regulator-name = "vreg_s3g_0p7"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1004000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s4g_1p3: smps4 { + regulator-name = "vreg_s4g_1p3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1352000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s5g_0p8: smps5 { + regulator-name = "vreg_s5g_0p8"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1004000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s6g_1p8: smps6 { + regulator-name = "vreg_s6g_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1g_1p2: ldo1 { + regulator-name = "vreg_l1g_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2g_1p2: ldo2 { + regulator-name = "vreg_l2g_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3g_1p2: ldo3 { + regulator-name = "vreg_l3g_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; +}; + +&dispcc { + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&vreg_l3e_1p2>; + status = "okay"; + + panel@0 { + compatible = "visionox,vtdr6130"; + reg = <0>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sde_dsi_active>, <&sde_te_active>; + pinctrl-1 = <&sde_dsi_suspend>, <&sde_te_suspend>; + + vddio-supply = <&vreg_l12b_1p8>; + vci-supply = <&vreg_l13b_3p0>; + vdd-supply = <&vreg_l11b_1p2>; + + reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>; + + port { + panel0_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint = <&panel0_in>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vreg_l1e_0p88>; + status = "okay"; +}; + +&mdss_mdp { + status = "okay"; +}; + +&pcie_1_phy_aux_clk { + clock-frequency = <1000>; +}; + +&pcie0 { + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l1e_0p88>; + vdda-pll-supply = <&vreg_l3e_1p2>; + status = "okay"; +}; + +&pcie1 { + wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; + perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcie1_phy { + vdda-phy-supply = <&vreg_l3c_0p91>; + vdda-pll-supply = <&vreg_l3e_1p2>; + vdda-qref-supply = <&vreg_l1e_0p88>; + status = "okay"; +}; + +&pm8550_gpios { + sdc2_card_det_n: sdc2-card-det-state { + pins = "gpio12"; + function = "normal"; + input-enable; + output-disable; + bias-pull-up; + power-source = <1>; /* 1.8 V */ + }; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/sm8550/adsp.mbn", + "qcom/sm8550/adsp_dtb.mbn"; + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/sm8550/cdsp.mbn", + "qcom/sm8550/cdsp_dtb.mbn"; + status = "okay"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/sm8550/modem.mbn", + "qcom/sm8550/modem_dtb.mbn"; + status = "okay"; +}; + +&sdhc_2 { + cd-gpios = <&pm8550_gpios 12 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_default &sdc2_card_det_n>; + pinctrl-1 = <&sdc2_sleep &sdc2_card_det_n>; + vmmc-supply = <&vreg_l9b_2p9>; + vqmmc-supply = <&vreg_l8b_1p8>; + bus-width = <4>; + no-sdio; + no-mmc; + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&tlmm { + gpio-reserved-ranges = <32 8>; + + sde_dsi_active: sde-dsi-active-state { + pins = "gpio133"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + sde_dsi_suspend: sde-dsi-suspend-state { + pins = "gpio133"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + sde_te_active: sde-te-active-state { + pins = "gpio86"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; + + sde_te_suspend: sde-te-suspend-state { + pins = "gpio86"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; +}; + +&uart7 { + status = "okay"; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>; + vcc-supply = <&vreg_l17b_2p5>; + vcc-max-microamp = <1300000>; + vccq-supply = <&vreg_l1g_1p2>; + vccq-max-microamp = <1200000>; + vccq2-supply = <&vreg_l3g_1p2>; + vccq2-max-microamp = <100>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l1d_0p88>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_1_hsphy { + vdd-supply = <&vreg_l1e_0p88>; + vdda12-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&usb_dp_qmpphy { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3f_0p91>; + + status = "okay"; +}; + +&xo_board { + clock-frequency = <76800000>; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi new file mode 100644 index 000000000000..6ff135191ee0 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -0,0 +1,4755 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Linaro Limited + */ + +#include <dt-bindings/clock/qcom,rpmh.h> +#include <dt-bindings/clock/qcom,sm8550-gcc.h> +#include <dt-bindings/clock/qcom,sm8550-tcsr.h> +#include <dt-bindings/clock/qcom,sm8550-dispcc.h> +#include <dt-bindings/dma/qcom-gpi.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interconnect/qcom,sm8550-rpmh.h> +#include <dt-bindings/mailbox/qcom-ipcc.h> +#include <dt-bindings/power/qcom-rpmpd.h> +#include <dt-bindings/soc/qcom,rpmh-rsc.h> +#include <dt-bindings/phy/phy-qcom-qmp.h> +#include <dt-bindings/thermal/thermal.h> + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + bi_tcxo_div2: bi-tcxo-div2-clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-mult = <1>; + clock-div = <2>; + }; + + bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&rpmhcc RPMH_CXO_CLK_A>; + clock-mult = <1>; + clock-div = <2>; + }; + + pcie_1_phy_aux_clk: pcie-1-phy-aux-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0 0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + #cooling-cells = <2>; + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + L3_0: l3-cache { + compatible = "cache"; + cache-level = <3>; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0 0x100>; + enable-method = "psci"; + next-level-cache = <&L2_100>; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + #cooling-cells = <2>; + L2_100: l2-cache { + compatible = "cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0 0x200>; + enable-method = "psci"; + next-level-cache = <&L2_200>; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + #cooling-cells = <2>; + L2_200: l2-cache { + compatible = "cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0 0x300>; + enable-method = "psci"; + next-level-cache = <&L2_300>; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; + capacity-dmips-mhz = <1792>; + dynamic-power-coefficient = <270>; + #cooling-cells = <2>; + L2_300: l2-cache { + compatible = "cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0 0x400>; + enable-method = "psci"; + next-level-cache = <&L2_400>; + power-domains = <&CPU_PD4>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; + capacity-dmips-mhz = <1792>; + dynamic-power-coefficient = <270>; + #cooling-cells = <2>; + L2_400: l2-cache { + compatible = "cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0 0x500>; + enable-method = "psci"; + next-level-cache = <&L2_500>; + power-domains = <&CPU_PD5>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; + capacity-dmips-mhz = <1792>; + dynamic-power-coefficient = <270>; + #cooling-cells = <2>; + L2_500: l2-cache { + compatible = "cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0 0x600>; + enable-method = "psci"; + next-level-cache = <&L2_600>; + power-domains = <&CPU_PD6>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; + capacity-dmips-mhz = <1792>; + dynamic-power-coefficient = <270>; + #cooling-cells = <2>; + L2_600: l2-cache { + compatible = "cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0 0x700>; + enable-method = "psci"; + next-level-cache = <&L2_700>; + power-domains = <&CPU_PD7>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 2>; + capacity-dmips-mhz = <1894>; + dynamic-power-coefficient = <588>; + #cooling-cells = <2>; + L2_700: l2-cache { + compatible = "cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + + core4 { + cpu = <&CPU4>; + }; + + core5 { + cpu = <&CPU5>; + }; + + core6 { + cpu = <&CPU6>; + }; + + core7 { + cpu = <&CPU7>; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + idle-state-name = "silver-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <800>; + exit-latency-us = <750>; + min-residency-us = <4090>; + local-timer-stop; + }; + + BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + idle-state-name = "gold-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <600>; + exit-latency-us = <1550>; + min-residency-us = <4791>; + local-timer-stop; + }; + }; + + domain-idle-states { + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x41000044>; + entry-latency-us = <1050>; + exit-latency-us = <2500>; + min-residency-us = <5309>; + }; + + CLUSTER_SLEEP_1: cluster-sleep-1 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x4100c344>; + entry-latency-us = <2700>; + exit-latency-us = <3500>; + min-residency-us = <13959>; + }; + }; + }; + + firmware { + scm: scm { + compatible = "qcom,scm-sm8550", "qcom,scm"; + interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; + }; + }; + + clk_virt: interconnect-0 { + compatible = "qcom,sm8550-clk-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mc_virt: interconnect-1 { + compatible = "qcom,sm8550-mc-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + memory@a0000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0 0xa0000000 0 0>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + CPU_PD0: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD1: power-domain-cpu1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD2: power-domain-cpu2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD3: power-domain-cpu3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD4: power-domain-cpu4 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD5: power-domain-cpu5 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD6: power-domain-cpu6 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD7: power-domain-cpu7 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CLUSTER_PD: power-domain-cluster { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>; + }; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: hyp-region@80000000 { + reg = <0 0x80000000 0 0xa00000>; + no-map; + }; + + cpusys_vm_mem: cpusys-vm-region@80a00000 { + reg = <0 0x80a00000 0 0x400000>; + no-map; + }; + + hyp_tags_mem: hyp-tags-region@80e00000 { + reg = <0 0x80e00000 0 0x3d0000>; + no-map; + }; + + xbl_sc_mem: xbl-sc-region@d8100000 { + reg = <0 0xd8100000 0 0x40000>; + no-map; + }; + + + hyp_tags_reserved_mem: hyp-tags-reserved-region@811d0000 { + reg = <0 0x811d0000 0 0x30000>; + no-map; + }; + + /* merged xbl_dt_log, xbl_ramdump, aop_image */ + xbl_dt_log_merged_mem: xbl-dt-log-merged-region@81a00000 { + reg = <0 0x81a00000 0 0x260000>; + no-map; + }; + + aop_cmd_db_mem: aop-cmd-db-region@81c60000 { + compatible = "qcom,cmd-db"; + reg = <0 0x81c60000 0 0x20000>; + no-map; + }; + + /* merged aop_config, tme_crash_dump, tme_log, uefi_log */ + aop_config_merged_mem: aop-config-merged-region@81c80000 { + reg = <0 0x81c80000 0 0x74000>; + no-map; + }; + + /* secdata region can be reused by apps */ + smem: smem@81d00000 { + compatible = "qcom,smem"; + reg = <0 0x81d00000 0 0x200000>; + hwlocks = <&tcsr_mutex 3>; + no-map; + }; + + adsp_mhi_mem: adsp-mhi-region@81f00000 { + reg = <0 0x81f00000 0 0x20000>; + no-map; + }; + + global_sync_mem: global-sync-region@82600000 { + reg = <0 0x82600000 0 0x100000>; + no-map; + }; + + tz_stat_mem: tz-stat-region@82700000 { + reg = <0 0x82700000 0 0x100000>; + no-map; + }; + + cdsp_secure_heap_mem: cdsp-secure-heap-region@82800000 { + reg = <0 0x82800000 0 0x4600000>; + no-map; + }; + + mpss_mem: mpss-region@8a800000 { + reg = <0 0x8a800000 0 0x10800000>; + no-map; + }; + + q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 { + reg = <0 0x9b000000 0 0x80000>; + no-map; + }; + + ipa_fw_mem: ipa-fw-region@9b080000 { + reg = <0 0x9b080000 0 0x10000>; + no-map; + }; + + ipa_gsi_mem: ipa-gsi-region@9b090000 { + reg = <0 0x9b090000 0 0xa000>; + no-map; + }; + + gpu_micro_code_mem: gpu-micro-code-region@9b09a000 { + reg = <0 0x9b09a000 0 0x2000>; + no-map; + }; + + spss_region_mem: spss-region@9b100000 { + reg = <0 0x9b100000 0 0x180000>; + no-map; + }; + + /* First part of the "SPU secure shared memory" region */ + spu_tz_shared_mem: spu-tz-shared-region@9b280000 { + reg = <0 0x9b280000 0 0x60000>; + no-map; + }; + + /* Second part of the "SPU secure shared memory" region */ + spu_modem_shared_mem: spu-modem-shared-region@9b2e0000 { + reg = <0 0x9b2e0000 0 0x20000>; + no-map; + }; + + camera_mem: camera-region@9b300000 { + reg = <0 0x9b300000 0 0x800000>; + no-map; + }; + + video_mem: video-region@9bb00000 { + reg = <0 0x9bb00000 0 0x700000>; + no-map; + }; + + cvp_mem: cvp-region@9c200000 { + reg = <0 0x9c200000 0 0x700000>; + no-map; + }; + + cdsp_mem: cdsp-region@9c900000 { + reg = <0 0x9c900000 0 0x2000000>; + no-map; + }; + + q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9e900000 { + reg = <0 0x9e900000 0 0x80000>; + no-map; + }; + + q6_adsp_dtb_mem: q6-adsp-dtb-region@9e980000 { + reg = <0 0x9e980000 0 0x80000>; + no-map; + }; + + adspslpi_mem: adspslpi-region@9ea00000 { + reg = <0 0x9ea00000 0 0x4080000>; + no-map; + }; + + /* uefi region can be reused by apps */ + + /* Linux kernel image is loaded at 0xa8000000 */ + + rmtfs_mem: rmtfs-region@d4a80000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0 0xd4a80000 0x0 0x280000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = <15>; + }; + + mpss_dsm_mem: mpss-dsm-region@d4d00000 { + reg = <0 0xd4d00000 0 0x3300000>; + no-map; + }; + + tz_reserved_mem: tz-reserved-region@d8000000 { + reg = <0 0xd8000000 0 0x100000>; + no-map; + }; + + cpucp_fw_mem: cpucp-fw-region@d8140000 { + reg = <0 0xd8140000 0 0x1c0000>; + no-map; + }; + + qtee_mem: qtee-region@d8300000 { + reg = <0 0xd8300000 0 0x500000>; + no-map; + }; + + ta_mem: ta-region@d8800000 { + reg = <0 0xd8800000 0 0x8a00000>; + no-map; + }; + + tz_tags_mem: tz-tags-region@e1200000 { + reg = <0 0xe1200000 0 0x2740000>; + no-map; + }; + + hwfence_shbuf: hwfence-shbuf-region@e6440000 { + reg = <0 0xe6440000 0 0x279000>; + no-map; + }; + + trust_ui_vm_mem: trust-ui-vm-region@f3600000 { + reg = <0 0xf3600000 0 0x4aee000>; + no-map; + }; + + trust_ui_vm_dump: trust-ui-vm-dump-region@f80ee000 { + reg = <0 0xf80ee000 0 0x1000>; + no-map; + }; + + trust_ui_vm_qrtr: trust-ui-vm-qrt-region@f80ef000 { + reg = <0 0xf80ef000 0 0x9000>; + no-map; + }; + + trust_ui_vm_vblk0_ring: trust-ui-vm-vblk0-ring-region@f80f8000 { + reg = <0 0xf80f8000 0 0x4000>; + no-map; + }; + + trust_ui_vm_vblk1_ring: trust-ui-vm-vblk1-ring-region@f80fc000 { + reg = <0 0xf80fc000 0 0x4000>; + no-map; + }; + + trust_ui_vm_swiotlb: trust-ui-vm-swiotlb-region@f8100000 { + reg = <0 0xf8100000 0 0x100000>; + no-map; + }; + + oem_vm_mem: oem-vm-region@f8400000 { + reg = <0 0xf8400000 0 0x4800000>; + no-map; + }; + + oem_vm_vblk0_ring: oem-vm-vblk0-ring-region@fcc00000 { + reg = <0 0xfcc00000 0 0x4000>; + no-map; + }; + + oem_vm_swiotlb: oem-vm-swiotlb-region@fcc04000 { + reg = <0 0xfcc04000 0 0x100000>; + no-map; + }; + + hyp_ext_tags_mem: hyp-ext-tags-region@fce00000 { + reg = <0 0xfce00000 0 0x2900000>; + no-map; + }; + + hyp_ext_reserved_mem: hyp-ext-reserved-region@ff700000 { + reg = <0 0xff700000 0 0x100000>; + no-map; + }; + }; + + smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + smp2p_adsp_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_adsp_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-cdsp { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + smp2p_cdsp_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_cdsp_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-modem { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupts-extended = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + smp2p_modem_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_modem_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + ipa_smp2p_out: ipa-ap-to-modem { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + ipa_smp2p_in: ipa-modem-to-ap { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + soc: soc@0 { + compatible = "simple-bus"; + ranges = <0 0 0 0 0x10 0>; + dma-ranges = <0 0 0 0 0x10 0>; + + #address-cells = <2>; + #size-cells = <2>; + + gcc: clock-controller@100000 { + compatible = "qcom,sm8550-gcc"; + reg = <0 0x00100000 0 0x1f4200>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clocks = <&bi_tcxo_div2>, <&sleep_clk>, + <&pcie0_phy>, + <&pcie1_phy>, + <&pcie_1_phy_aux_clk>, + <&ufs_mem_phy 0>, + <&ufs_mem_phy 1>, + <&ufs_mem_phy 2>, + <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; + }; + + ipcc: mailbox@408000 { + compatible = "qcom,sm8550-ipcc", "qcom,ipcc"; + reg = <0 0x00408000 0 0x1000>; + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + + gpi_dma2: dma-controller@800000 { + compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; + #dma-cells = <3>; + reg = <0 0x00800000 0 0x60000>; + interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; + dma-channels = <12>; + dma-channel-mask = <0x3e>; + iommus = <&apps_smmu 0x436 0>; + status = "disabled"; + }; + + qupv3_id_1: geniqup@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0 0x008c0000 0 0x2000>; + ranges; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + iommus = <&apps_smmu 0x423 0>; + #address-cells = <2>; + #size-cells = <2>; + status = "disabled"; + + i2c8: i2c@880000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00880000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c8_data_clk>; + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, + <&gpi_dma2 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi8: spi@880000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00880000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, + <&gpi_dma2 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c9: i2c@884000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00884000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c9_data_clk>; + interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, + <&gpi_dma2 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi9: spi@884000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00884000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, + <&gpi_dma2 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c10: i2c@888000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00888000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c10_data_clk>; + interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, + <&gpi_dma2 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi10: spi@888000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00888000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, + <&gpi_dma2 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c11: i2c@88c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x0088c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c11_data_clk>; + interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, + <&gpi_dma2 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi11: spi@88c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x0088c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, + <&gpi_dma2 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c12: i2c@890000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00890000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c12_data_clk>; + interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, + <&gpi_dma2 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi12: spi@890000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00890000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, + <&gpi_dma2 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c13: i2c@894000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00894000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c13_data_clk>; + interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, + <&gpi_dma2 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi13: spi@894000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00894000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, + <&gpi_dma2 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c15: i2c@89c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x0089c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c15_data_clk>; + interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, + <&gpi_dma2 1 7 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi15: spi@89c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x0089c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, + <&gpi_dma2 1 7 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + i2c_master_hub_0: geniqup@9c0000 { + compatible = "qcom,geni-se-i2c-master-hub"; + reg = <0x0 0x009c0000 0x0 0x2000>; + clock-names = "s-ahb"; + clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + i2c_hub_0: i2c@980000 { + compatible = "qcom,geni-i2c-master-hub"; + reg = <0x0 0x00980000 0x0 0x4000>; + clock-names = "se", "core"; + clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&hub_i2c0_data_clk>; + interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c_hub_1: i2c@984000 { + compatible = "qcom,geni-i2c-master-hub"; + reg = <0x0 0x00984000 0x0 0x4000>; + clock-names = "se", "core"; + clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&hub_i2c1_data_clk>; + interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c_hub_2: i2c@988000 { + compatible = "qcom,geni-i2c-master-hub"; + reg = <0x0 0x00988000 0x0 0x4000>; + clock-names = "se", "core"; + clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&hub_i2c2_data_clk>; + interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c_hub_3: i2c@98c000 { + compatible = "qcom,geni-i2c-master-hub"; + reg = <0x0 0x0098c000 0x0 0x4000>; + clock-names = "se", "core"; + clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&hub_i2c3_data_clk>; + interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c_hub_4: i2c@990000 { + compatible = "qcom,geni-i2c-master-hub"; + reg = <0x0 0x00990000 0x0 0x4000>; + clock-names = "se", "core"; + clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&hub_i2c4_data_clk>; + interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c_hub_5: i2c@994000 { + compatible = "qcom,geni-i2c-master-hub"; + reg = <0 0x00994000 0 0x4000>; + clock-names = "se", "core"; + clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&hub_i2c5_data_clk>; + interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c_hub_6: i2c@998000 { + compatible = "qcom,geni-i2c-master-hub"; + reg = <0 0x00998000 0 0x4000>; + clock-names = "se", "core"; + clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&hub_i2c6_data_clk>; + interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c_hub_7: i2c@99c000 { + compatible = "qcom,geni-i2c-master-hub"; + reg = <0 0x0099c000 0 0x4000>; + clock-names = "se", "core"; + clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&hub_i2c7_data_clk>; + interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c_hub_8: i2c@9a0000 { + compatible = "qcom,geni-i2c-master-hub"; + reg = <0 0x009a0000 0 0x4000>; + clock-names = "se", "core"; + clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&hub_i2c8_data_clk>; + interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c_hub_9: i2c@9a4000 { + compatible = "qcom,geni-i2c-master-hub"; + reg = <0 0x009a4000 0 0x4000>; + clock-names = "se", "core"; + clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&hub_i2c9_data_clk>; + interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + }; + + gpi_dma1: dma-controller@a00000 { + compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; + #dma-cells = <3>; + reg = <0 0x00a00000 0 0x60000>; + interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; + dma-channels = <12>; + dma-channel-mask = <0x1e>; + iommus = <&apps_smmu 0xb6 0>; + status = "disabled"; + }; + + qupv3_id_0: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0 0x00ac0000 0 0x2000>; + ranges; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + iommus = <&apps_smmu 0xa3 0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>; + interconnect-names = "qup-core"; + #address-cells = <2>; + #size-cells = <2>; + status = "disabled"; + + i2c0: i2c@a80000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a80000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c0_data_clk>; + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi0: spi@a80000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a80000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, + <&gpi_dma1 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@a84000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a84000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c1_data_clk>; + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi1: spi@a84000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a84000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, + <&gpi_dma1 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@a88000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a88000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c2_data_clk>; + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi2: spi@a88000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a88000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, + <&gpi_dma1 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a8c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c3_data_clk>; + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, + <&gpi_dma1 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi3: spi@a8c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a8c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, + <&gpi_dma1 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@a90000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a90000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c4_data_clk>; + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, + <&gpi_dma1 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi4: spi@a90000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a90000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, + <&gpi_dma1 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@a94000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a94000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c5_data_clk>; + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, + <&gpi_dma1 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi5: spi@a94000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a94000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, + <&gpi_dma1 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c6: i2c@a98000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a98000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c6_data_clk>; + interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, + <&gpi_dma1 1 6 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi6: spi@a98000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a98000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, + <&gpi_dma1 1 6 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart7: serial@a9c000 { + compatible = "qcom,geni-debug-uart"; + reg = <0 0x00a9c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart7_default>; + interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; + interconnect-names = "qup-core", "qup-config"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + cnoc_main: interconnect@1500000 { + compatible = "qcom,sm8550-cnoc-main"; + reg = <0 0x01500000 0 0x13080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + config_noc: interconnect@1600000 { + compatible = "qcom,sm8550-config-noc"; + reg = <0 0x01600000 0 0x6200>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system_noc: interconnect@1680000 { + compatible = "qcom,sm8550-system-noc"; + reg = <0 0x01680000 0 0x1d080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + pcie_noc: interconnect@16c0000 { + compatible = "qcom,sm8550-pcie-anoc"; + reg = <0 0x016c0000 0 0x12200>; + #interconnect-cells = <2>; + clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, + <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@16e0000 { + compatible = "qcom,sm8550-aggre1-noc"; + reg = <0 0x016e0000 0 0x14400>; + #interconnect-cells = <2>; + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre2_noc: interconnect@1700000 { + compatible = "qcom,sm8550-aggre2-noc"; + reg = <0 0x01700000 0 0x1e400>; + #interconnect-cells = <2>; + clocks = <&rpmhcc RPMH_IPA_CLK>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mmss_noc: interconnect@1780000 { + compatible = "qcom,sm8550-mmss-noc"; + reg = <0 0x01780000 0 0x5b800>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + pcie0: pci@1c00000 { + device_type = "pci"; + compatible = "qcom,pcie-sm8550"; + reg = <0 0x01c00000 0 0x3000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60001000 0 0x1000>, + <0 0x60100000 0 0x100000>; + reg-names = "parf", "dbi", "elbi", "atu", "config"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; + bus-range = <0x00 0xff>; + + dma-coherent; + + linux,pci-domain = <0>; + num-lanes = <2>; + + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>; + clock-names = "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ddrss_sf_tbu", + "aggre0"; + + interconnect-names = "pcie-mem"; + interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>; + + iommus = <&apps_smmu 0x1400 0x7f>; + iommu-map = <0x0 &apps_smmu 0x1400 0x1>, + <0x100 &apps_smmu 0x1401 0x1>; + + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "pci"; + + power-domains = <&gcc PCIE_0_GDSC>; + + phys = <&pcie0_phy>; + phy-names = "pciephy"; + + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_default_state>; + + status = "disabled"; + }; + + pcie0_phy: phy@1c06000 { + compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy"; + reg = <0 0x01c06000 0 0x2000>; + + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&tcsr TCSR_PCIE_0_CLKREF_EN>, + <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "rchng", + "pipe"; + + resets = <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + power-domains = <&gcc PCIE_0_PHY_GDSC>; + + #clock-cells = <0>; + clock-output-names = "pcie0_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + + pcie1: pci@1c08000 { + device_type = "pci"; + compatible = "qcom,pcie-sm8550"; + reg = <0x0 0x01c08000 0x0 0x3000>, + <0x0 0x40000000 0x0 0xf1d>, + <0x0 0x40000f20 0x0 0xa8>, + <0x0 0x40001000 0x0 0x1000>, + <0x0 0x40100000 0x0 0x100000>; + reg-names = "parf", "dbi", "elbi", "atu", "config"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>; + bus-range = <0x00 0xff>; + + dma-coherent; + + linux,pci-domain = <1>; + num-lanes = <2>; + + interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, + <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, + <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; + clock-names = "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ddrss_sf_tbu", + "aggre1", + "cnoc_pcie_sf_axi"; + + assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; + assigned-clock-rates = <19200000>; + + interconnect-names = "pcie-mem"; + interconnects = <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>; + + iommus = <&apps_smmu 0x1480 0x7f>; + iommu-map = <0x0 &apps_smmu 0x1480 0x1>, + <0x100 &apps_smmu 0x1481 0x1>; + + resets = <&gcc GCC_PCIE_1_BCR>, + <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; + reset-names = "pci", + "pcie_1_link_down_reset"; + + power-domains = <&gcc PCIE_1_GDSC>; + + phys = <&pcie1_phy>; + phy-names = "pciephy"; + + perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; + enable-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_default_state>; + + status = "disabled"; + }; + + pcie1_phy: phy@1c0e000 { + compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy"; + reg = <0x0 0x01c0e000 0x0 0x2000>; + + clocks = <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&tcsr TCSR_PCIE_1_CLKREF_EN>, + <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_1_PIPE_CLK>, + <&gcc GCC_PCIE_1_PHY_AUX_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "rchng", + "pipe", "aux_phy"; + + resets = <&gcc GCC_PCIE_1_PHY_BCR>, + <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>; + reset-names = "phy", "nocsr"; + + assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + power-domains = <&gcc PCIE_1_PHY_GDSC>; + + #clock-cells = <0>; + clock-output-names = "pcie1_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + + cryptobam: dma-controller@1dc4000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x0 0x01dc4000 0x0 0x28000>; + interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + qcom,ee = <0>; + qcom,controlled-remotely; + iommus = <&apps_smmu 0x480 0x0>, + <&apps_smmu 0x481 0x0>; + interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "memory"; + }; + + crypto: crypto@1de0000 { + compatible = "qcom,sm8550-qce"; + reg = <0x0 0x01dfa000 0x0 0x6000>; + dmas = <&cryptobam 4>, <&cryptobam 5>; + dma-names = "rx", "tx"; + iommus = <&apps_smmu 0x480 0x0>, + <&apps_smmu 0x481 0x0>; + interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "memory"; + }; + + ufs_mem_phy: phy@1d80000 { + compatible = "qcom,sm8550-qmp-ufs-phy"; + reg = <0x0 0x01d80000 0x0 0x2000>; + clocks = <&tcsr TCSR_UFS_CLKREF_EN>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + clock-names = "ref", "ref_aux"; + + power-domains = <&gcc UFS_MEM_PHY_GDSC>; + + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + ufs_mem_hc: ufs@1d84000 { + compatible = "qcom,sm8550-ufshc", "qcom,ufshc", + "jedec,ufs-2.0"; + reg = <0x0 0x01d84000 0x0 0x3000>; + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; + phys = <&ufs_mem_phy>; + phy-names = "ufsphy"; + lanes-per-direction = <2>; + #reset-cells = <1>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + power-domains = <&gcc UFS_PHY_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + iommus = <&apps_smmu 0x60 0x0>; + + interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; + + interconnect-names = "ufs-ddr", "cpu-ufs"; + clock-names = "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&tcsr TCSR_UFS_PAD_CLKREF_EN>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + freq-table-hz = + <75000000 300000000>, + <0 0>, + <0 0>, + <75000000 300000000>, + <100000000 403000000>, + <0 0>, + <0 0>, + <0 0>; + status = "disabled"; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0 0x01f40000 0 0x20000>; + #hwlock-cells = <1>; + }; + + tcsr: clock-controller@1fc0000 { + compatible = "qcom,sm8550-tcsr", "syscon"; + reg = <0 0x01fc0000 0 0x30000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + remoteproc_mpss: remoteproc@4080000 { + compatible = "qcom,sm8550-mpss-pas"; + reg = <0x0 0x04080000 0x0 0x4040>; + + interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", + "stop-ack", "shutdown-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd SM8550_CX>, + <&rpmhpd SM8550_MSS>; + power-domain-names = "cx", "mss"; + + interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; + + memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, <&mpss_dsm_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_modem_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + label = "mpss"; + qcom,remote-pid = <1>; + }; + }; + + lpass_lpiaon_noc: interconnect@7400000 { + compatible = "qcom,sm8550-lpass-lpiaon-noc"; + reg = <0 0x07400000 0 0x19080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + lpass_lpicx_noc: interconnect@7430000 { + compatible = "qcom,sm8550-lpass-lpicx-noc"; + reg = <0 0x07430000 0 0x3a200>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + lpass_ag_noc: interconnect@7e40000 { + compatible = "qcom,sm8550-lpass-ag-noc"; + reg = <0 0x07e40000 0 0xe080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + sdhc_2: mmc@8804000 { + compatible = "qcom,sm8550-sdhci", "qcom,sdhci-msm-v5"; + reg = <0 0x08804000 0 0x1000>; + + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "core", "xo"; + iommus = <&apps_smmu 0x540 0>; + qcom,dll-config = <0x0007642c>; + qcom,ddr-config = <0x80040868>; + power-domains = <&rpmhpd SM8550_CX>; + operating-points-v2 = <&sdhc2_opp_table>; + + interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; + interconnect-names = "sdhc-ddr", "cpu-sdhc"; + bus-width = <4>; + dma-coherent; + + /* Forbid SDR104/SDR50 - broken hw! */ + sdhci-caps-mask = <0x3 0>; + + status = "disabled"; + + sdhc2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss: display-subsystem@ae00000 { + compatible = "qcom,sm8550-mdss"; + reg = <0 0x0ae00000 0 0x1000>; + reg-names = "mdss"; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + + power-domains = <&dispcc MDSS_GDSC>; + + interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>, + <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + + iommus = <&apps_smmu 0x1c00 0x2>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + mdss_mdp: display-controller@ae01000 { + compatible = "qcom,sm8550-dpu"; + reg = <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>; + reg-names = "mdp", "vbif"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + power-domains = <&rpmhpd SM8550_MMCX>; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&mdss_dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-325000000 { + opp-hz = /bits/ 64 <325000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-514000000 { + opp-hz = /bits/ 64 <514000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_dsi0: dsi@ae94000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae94000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + power-domains = <&rpmhpd SM8550_MMCX>; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + + operating-points-v2 = <&mdss_dsi_opp_table>; + + phys = <&mdss_dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi0_out: endpoint { + }; + }; + }; + + mdss_dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss_dsi0_phy: phy@ae95000 { + compatible = "qcom,sm8550-dsi-phy-4nm"; + reg = <0 0x0ae95000 0 0x200>, + <0 0x0ae95200 0 0x280>, + <0 0x0ae95500 0 0x400>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + mdss_dsi1: dsi@ae96000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae96000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + power-domains = <&rpmhpd SM8550_MMCX>; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; + + operating-points-v2 = <&mdss_dsi_opp_table>; + + phys = <&mdss_dsi1_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi1_phy: phy@ae97000 { + compatible = "qcom,sm8550-dsi-phy-4nm"; + reg = <0 0x0ae97000 0 0x200>, + <0 0x0ae97200 0 0x280>, + <0 0x0ae97500 0 0x400>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,sm8550-dispcc"; + reg = <0 0x0af00000 0 0x20000>; + clocks = <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&gcc GCC_DISP_AHB_CLK>, + <&sleep_clk>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>, + <0>, /* dp0 */ + <0>, + <0>, /* dp1 */ + <0>, + <0>, /* dp2 */ + <0>, + <0>, /* dp3 */ + <0>; + power-domains = <&rpmhpd SM8550_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + status = "disabled"; + }; + + usb_1_hsphy: phy@88e3000 { + compatible = "qcom,sm8550-snps-eusb2-phy"; + reg = <0x0 0x088e3000 0x0 0x154>; + #phy-cells = <0>; + + clocks = <&tcsr TCSR_USB2_CLKREF_EN>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + + status = "disabled"; + }; + + usb_dp_qmpphy: phy@88e8000 { + compatible = "qcom,sm8550-qmp-usb3-dp-phy"; + reg = <0x0 0x088e8000 0x0 0x3000>; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "aux", "ref", "com_aux", "usb3_pipe"; + + power-domains = <&gcc USB3_PHY_GDSC>; + + resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, + <&gcc GCC_USB3_PHY_PRIM_BCR>; + reset-names = "phy", "common"; + + #clock-cells = <1>; + #phy-cells = <1>; + + status = "disabled"; + }; + + usb_1: usb@a6f8800 { + compatible = "qcom,sm8550-dwc3", "qcom,dwc3"; + reg = <0x0 0x0a6f8800 0x0 0x400>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&tcsr TCSR_USB3_CLKREF_EN>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "xo"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 15 IRQ_TYPE_EDGE_RISING>, + <&pdc 14 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "hs_phy_irq", + "ss_phy_irq", + "dm_hs_phy_irq", + "dp_hs_phy_irq"; + + power-domains = <&gcc USB30_PRIM_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + status = "disabled"; + + usb_1_dwc3: usb@a600000 { + compatible = "snps,dwc3"; + reg = <0x0 0x0a600000 0x0 0xcd00>; + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&apps_smmu 0x40 0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,usb3_lpm_capable; + phys = <&usb_1_hsphy>, + <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,sm8550-pdc", "qcom,pdc"; + reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; + qcom,pdc-ranges = <0 480 94>, <94 609 31>, + <125 63 1>, <126 716 12>, + <138 251 5>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + tsens0: thermal-sensor@c271000 { + compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; + reg = <0 0x0c271000 0 0x1000>, /* TM */ + <0 0x0c222000 0 0x1000>; /* SROT */ + #qcom,sensors = <16>; + interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; + + tsens1: thermal-sensor@c272000 { + compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; + reg = <0 0x0c272000 0 0x1000>, /* TM */ + <0 0x0c223000 0 0x1000>; /* SROT */ + #qcom,sensors = <16>; + interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; + + tsens2: thermal-sensor@c273000 { + compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; + reg = <0 0x0c273000 0 0x1000>, /* TM */ + <0 0x0c224000 0 0x1000>; /* SROT */ + #qcom,sensors = <16>; + interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; + + aoss_qmp: power-controller@c300000 { + compatible = "qcom,sm8550-aoss-qmp", "qcom,aoss-qmp"; + reg = <0 0x0c300000 0 0x400>; + interrupt-parent = <&ipcc>; + interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; + + #clock-cells = <0>; + }; + + sram@c3f0000 { + compatible = "qcom,rpmh-stats"; + reg = <0 0x0c3f0000 0 0x400>; + }; + + spmi_bus: spmi@c400000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0 0x0c400000 0 0x3000>, + <0 0x0c500000 0 0x4000000>, + <0 0x0c440000 0 0x80000>, + <0 0x0c4c0000 0 0x20000>, + <0 0x0c42d000 0 0x4000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + qcom,ee = <0>; + qcom,channel = <0>; + qcom,bus-id = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + + tlmm: pinctrl@f000000 { + compatible = "qcom,sm8550-tlmm"; + reg = <0 0x0f100000 0 0x300000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 211>; + wakeup-parent = <&pdc>; + + hub_i2c0_data_clk: hub-i2c0-data-clk-state { + /* SDA, SCL */ + pins = "gpio16", "gpio17"; + function = "i2chub0_se0"; + drive-strength = <2>; + bias-pull-up; + }; + + hub_i2c1_data_clk: hub-i2c1-data-clk-state { + /* SDA, SCL */ + pins = "gpio18", "gpio19"; + function = "i2chub0_se1"; + drive-strength = <2>; + bias-pull-up; + }; + + hub_i2c2_data_clk: hub-i2c2-data-clk-state { + /* SDA, SCL */ + pins = "gpio20", "gpio21"; + function = "i2chub0_se2"; + drive-strength = <2>; + bias-pull-up; + }; + + hub_i2c3_data_clk: hub-i2c3-data-clk-state { + /* SDA, SCL */ + pins = "gpio22", "gpio23"; + function = "i2chub0_se3"; + drive-strength = <2>; + bias-pull-up; + }; + + hub_i2c4_data_clk: hub-i2c4-data-clk-state { + /* SDA, SCL */ + pins = "gpio4", "gpio5"; + function = "i2chub0_se4"; + drive-strength = <2>; + bias-pull-up; + }; + + hub_i2c5_data_clk: hub-i2c5-data-clk-state { + /* SDA, SCL */ + pins = "gpio6", "gpio7"; + function = "i2chub0_se5"; + drive-strength = <2>; + bias-pull-up; + }; + + hub_i2c6_data_clk: hub-i2c6-data-clk-state { + /* SDA, SCL */ + pins = "gpio8", "gpio9"; + function = "i2chub0_se6"; + drive-strength = <2>; + bias-pull-up; + }; + + hub_i2c7_data_clk: hub-i2c7-data-clk-state { + /* SDA, SCL */ + pins = "gpio10", "gpio11"; + function = "i2chub0_se7"; + drive-strength = <2>; + bias-pull-up; + }; + + hub_i2c8_data_clk: hub-i2c8-data-clk-state { + /* SDA, SCL */ + pins = "gpio206", "gpio207"; + function = "i2chub0_se8"; + drive-strength = <2>; + bias-pull-up; + }; + + hub_i2c9_data_clk: hub-i2c9-data-clk-state { + /* SDA, SCL */ + pins = "gpio84", "gpio85"; + function = "i2chub0_se9"; + drive-strength = <2>; + bias-pull-up; + }; + + pcie0_default_state: pcie0-default-state { + perst-pins { + pins = "gpio94"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq-pins { + pins = "gpio95"; + function = "pcie0_clk_req_n"; + drive-strength = <2>; + bias-pull-up; + }; + + wake-pins { + pins = "gpio96"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie1_default_state: pcie1-default-state { + perst-pins { + pins = "gpio97"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq-pins { + pins = "gpio98"; + function = "pcie1_clk_req_n"; + drive-strength = <2>; + bias-pull-up; + }; + + wake-pins { + pins = "gpio99"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qup_i2c0_data_clk: qup-i2c0-data-clk-state { + /* SDA, SCL */ + pins = "gpio28", "gpio29"; + function = "qup1_se0"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c1_data_clk: qup-i2c1-data-clk-state { + /* SDA, SCL */ + pins = "gpio32", "gpio33"; + function = "qup1_se1"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c2_data_clk: qup-i2c2-data-clk-state { + /* SDA, SCL */ + pins = "gpio36", "gpio37"; + function = "qup1_se2"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c3_data_clk: qup-i2c3-data-clk-state { + /* SDA, SCL */ + pins = "gpio40", "gpio41"; + function = "qup1_se3"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c4_data_clk: qup-i2c4-data-clk-state { + /* SDA, SCL */ + pins = "gpio44", "gpio45"; + function = "qup1_se4"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c5_data_clk: qup-i2c5-data-clk-state { + /* SDA, SCL */ + pins = "gpio52", "gpio53"; + function = "qup1_se5"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c6_data_clk: qup-i2c6-data-clk-state { + /* SDA, SCL */ + pins = "gpio48", "gpio49"; + function = "qup1_se6"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c8_data_clk: qup-i2c8-data-clk-state { + scl-pins { + pins = "gpio57"; + function = "qup2_se0_l1_mira"; + drive-strength = <2>; + bias-pull-up; + }; + + sda-pins { + pins = "gpio56"; + function = "qup2_se0_l0_mira"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qup_i2c9_data_clk: qup-i2c9-data-clk-state { + /* SDA, SCL */ + pins = "gpio60", "gpio61"; + function = "qup2_se1"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c10_data_clk: qup-i2c10-data-clk-state { + /* SDA, SCL */ + pins = "gpio64", "gpio65"; + function = "qup2_se2"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c11_data_clk: qup-i2c11-data-clk-state { + /* SDA, SCL */ + pins = "gpio68", "gpio69"; + function = "qup2_se3"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c12_data_clk: qup-i2c12-data-clk-state { + /* SDA, SCL */ + pins = "gpio2", "gpio3"; + function = "qup2_se4"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c13_data_clk: qup-i2c13-data-clk-state { + /* SDA, SCL */ + pins = "gpio80", "gpio81"; + function = "qup2_se5"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c15_data_clk: qup-i2c15-data-clk-state { + /* SDA, SCL */ + pins = "gpio72", "gpio106"; + function = "qup2_se7"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi0_cs: qup-spi0-cs-state { + cs-pins { + pins = "gpio31"; + function = "qup1_se0"; + }; + }; + + qup_spi0_data_clk: qup-spi0-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio28", "gpio29", "gpio30"; + function = "qup1_se0"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi1_cs: qup-spi1-cs-state { + pins = "gpio35"; + function = "qup1_se1"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi1_data_clk: qup-spi1-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio32", "gpio33", "gpio34"; + function = "qup1_se1"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi2_cs: qup-spi2-cs-state { + pins = "gpio39"; + function = "qup1_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi2_data_clk: qup-spi2-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio36", "gpio37", "gpio38"; + function = "qup1_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi3_cs: qup-spi3-cs-state { + pins = "gpio43"; + function = "qup1_se3"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi3_data_clk: qup-spi3-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio40", "gpio41", "gpio42"; + function = "qup1_se3"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi4_cs: qup-spi4-cs-state { + pins = "gpio47"; + function = "qup1_se4"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi4_data_clk: qup-spi4-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio44", "gpio45", "gpio46"; + function = "qup1_se4"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi5_cs: qup-spi5-cs-state { + pins = "gpio55"; + function = "qup1_se5"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi5_data_clk: qup-spi5-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio52", "gpio53", "gpio54"; + function = "qup1_se5"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi6_cs: qup-spi6-cs-state { + pins = "gpio51"; + function = "qup1_se6"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi6_data_clk: qup-spi6-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio48", "gpio49", "gpio50"; + function = "qup1_se6"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi8_cs: qup-spi8-cs-state { + pins = "gpio59"; + function = "qup2_se0_l3_mira"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi8_data_clk: qup-spi8-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio56", "gpio57", "gpio58"; + function = "qup2_se0_l2_mira"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi9_cs: qup-spi9-cs-state { + pins = "gpio63"; + function = "qup2_se1"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi9_data_clk: qup-spi9-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio60", "gpio61", "gpio62"; + function = "qup2_se1"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi10_cs: qup-spi10-cs-state { + pins = "gpio67"; + function = "qup2_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi10_data_clk: qup-spi10-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio64", "gpio65", "gpio66"; + function = "qup2_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi11_cs: qup-spi11-cs-state { + pins = "gpio71"; + function = "qup2_se3"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi11_data_clk: qup-spi11-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio68", "gpio69", "gpio70"; + function = "qup2_se3"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi12_cs: qup-spi12-cs-state { + pins = "gpio119"; + function = "qup2_se4"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi12_data_clk: qup-spi12-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio2", "gpio3", "gpio118"; + function = "qup2_se4"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi13_cs: qup-spi13-cs-state { + pins = "gpio83"; + function = "qup2_se5"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi13_data_clk: qup-spi13-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio80", "gpio81", "gpio82"; + function = "qup2_se5"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi15_cs: qup-spi15-cs-state { + pins = "gpio75"; + function = "qup2_se7"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi15_data_clk: qup-spi15-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio72", "gpio106", "gpio74"; + function = "qup2_se7"; + drive-strength = <6>; + bias-disable; + }; + + qup_uart7_default: qup-uart7-default-state { + /* TX, RX */ + pins = "gpio26", "gpio27"; + function = "qup1_se7"; + drive-strength = <2>; + bias-disable; + }; + + sdc2_sleep: sdc2-sleep-state { + clk-pins { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd-pins { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data-pins { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + sdc2_default: sdc2-default-state { + clk-pins { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd-pins { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data-pins { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + }; + }; + + apps_smmu: iommu@15000000 { + compatible = "qcom,smmu-500", "arm,mmu-500"; + reg = <0 0x15000000 0 0x100000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>; + }; + + intc: interrupt-controller@17100000 { + compatible = "arm,gic-v3"; + reg = <0 0x17100000 0 0x10000>, /* GICD */ + <0 0x17180000 0 0x200000>; /* GICR * 8 */ + ranges; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0 0x40000>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; + #address-cells = <2>; + #size-cells = <2>; + + gic_its: msi-controller@17140000 { + compatible = "arm,gic-v3-its"; + reg = <0 0x17140000 0 0x20000>; + msi-controller; + #msi-cells = <1>; + }; + }; + + timer@17420000 { + compatible = "arm,armv7-timer-mem"; + reg = <0 0x17420000 0 0x1000>; + ranges = <0 0 0 0x20000000>; + #address-cells = <1>; + #size-cells = <1>; + + frame@17421000 { + reg = <0x17421000 0x1000>, + <0x17422000 0x1000>; + frame-number = <0>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + }; + + frame@17423000 { + reg = <0x17423000 0x1000>; + frame-number = <1>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + frame@17425000 { + reg = <0x17425000 0x1000>; + frame-number = <2>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + frame@17427000 { + reg = <0x17427000 0x1000>; + frame-number = <3>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + frame@17429000 { + reg = <0x17429000 0x1000>; + frame-number = <4>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + frame@1742b000 { + reg = <0x1742b000 0x1000>; + frame-number = <5>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + frame@1742d000 { + reg = <0x1742d000 0x1000>; + frame-number = <6>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + }; + + apps_rsc: rsc@17a00000 { + label = "apps_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0 0x17a00000 0 0x10000>, + <0 0x17a10000 0 0x10000>, + <0 0x17a20000 0 0x10000>, + <0 0x17a30000 0 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, + <WAKE_TCS 2>, <CONTROL_TCS 0>; + + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible = "qcom,sm8550-rpmh-clk"; + #clock-cells = <1>; + clock-names = "xo"; + clocks = <&xo_board>; + }; + + rpmhpd: power-controller { + compatible = "qcom,sm8550-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp1 { + opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; + }; + + rpmhpd_opp_min_svs: opp2 { + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; + }; + + rpmhpd_opp_low_svs: opp3 { + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + }; + + rpmhpd_opp_svs: opp4 { + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + }; + + rpmhpd_opp_svs_l1: opp5 { + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + }; + + rpmhpd_opp_nom: opp6 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM>; + }; + + rpmhpd_opp_nom_l1: opp7 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; + }; + + rpmhpd_opp_nom_l2: opp8 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; + }; + + rpmhpd_opp_turbo: opp9 { + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; + }; + + rpmhpd_opp_turbo_l1: opp10 { + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; + }; + }; + }; + }; + + cpufreq_hw: cpufreq@17d91000 { + compatible = "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss"; + reg = <0 0x17d91000 0 0x1000>, + <0 0x17d92000 0 0x1000>, + <0 0x17d93000 0 0x1000>; + reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; + clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; + #freq-domain-cells = <1>; + }; + + pmu@24091000 { + compatible = "qcom,sm8550-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; + reg = <0 0x24091000 0 0x1000>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; + + operating-points-v2 = <&llcc_bwmon_opp_table>; + + llcc_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-0 { + opp-peak-kBps = <2086000>; + }; + + opp-1 { + opp-peak-kBps = <2929000>; + }; + + opp-2 { + opp-peak-kBps = <5931000>; + }; + + opp-3 { + opp-peak-kBps = <6515000>; + }; + + opp-4 { + opp-peak-kBps = <7980000>; + }; + + opp-5 { + opp-peak-kBps = <10437000>; + }; + + opp-6 { + opp-peak-kBps = <12157000>; + }; + + opp-7 { + opp-peak-kBps = <14060000>; + }; + + opp-8 { + opp-peak-kBps = <16113000>; + }; + }; + }; + + pmu@240b6400 { + compatible = "qcom,sm8550-cpu-bwmon", "qcom,msm8998-bwmon"; + reg = <0 0x240b6400 0 0x600>; + interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; + + operating-points-v2 = <&cpu_bwmon_opp_table>; + + cpu_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-0 { + opp-peak-kBps = <4577000>; + }; + + opp-1 { + opp-peak-kBps = <7110000>; + }; + + opp-2 { + opp-peak-kBps = <9155000>; + }; + + opp-3 { + opp-peak-kBps = <12298000>; + }; + + opp-4 { + opp-peak-kBps = <14236000>; + }; + + opp-5 { + opp-peak-kBps = <16265000>; + }; + }; + }; + + gem_noc: interconnect@24100000 { + compatible = "qcom,sm8550-gem-noc"; + reg = <0 0x24100000 0 0xbb800>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system-cache-controller@25000000 { + compatible = "qcom,sm8550-llcc"; + reg = <0 0x25000000 0 0x800000>, + <0 0x25800000 0 0x200000>; + reg-names = "llcc_base", "llcc_broadcast_base"; + interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; + }; + + remoteproc_adsp: remoteproc@30000000 { + compatible = "qcom,sm8550-adsp-pas"; + reg = <0x0 0x30000000 0x0 0x100>; + + interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd SM8550_LCX>, + <&rpmhpd SM8550_LMX>; + power-domain-names = "lcx", "lmx"; + + interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>; + + memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_adsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + remoteproc_adsp_glink: glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "lpass"; + qcom,remote-pid = <2>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "adsp"; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x1003 0x80>, + <&apps_smmu 0x1063 0x0>; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x1004 0x80>, + <&apps_smmu 0x1064 0x0>; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x1005 0x80>, + <&apps_smmu 0x1065 0x0>; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x1006 0x80>, + <&apps_smmu 0x1066 0x0>; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&apps_smmu 0x1007 0x80>, + <&apps_smmu 0x1067 0x0>; + }; + }; + }; + }; + + nsp_noc: interconnect@320c0000 { + compatible = "qcom,sm8550-nsp-noc"; + reg = <0 0x320c0000 0 0xe080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + remoteproc_cdsp: remoteproc@32300000 { + compatible = "qcom,sm8550-cdsp-pas"; + reg = <0x0 0x32300000 0x0 0x1400000>; + + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd SM8550_CX>, + <&rpmhpd SM8550_MXC>, + <&rpmhpd SM8550_NSP>; + power-domain-names = "cx", "mxc", "nsp"; + + interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; + + memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_cdsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "cdsp"; + qcom,remote-pid = <5>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "cdsp"; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&apps_smmu 0x1961 0x0>, + <&apps_smmu 0x0c01 0x20>, + <&apps_smmu 0x19c1 0x10>; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&apps_smmu 0x1962 0x0>, + <&apps_smmu 0x0c02 0x20>, + <&apps_smmu 0x19c2 0x10>; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x1963 0x0>, + <&apps_smmu 0x0c03 0x20>, + <&apps_smmu 0x19c3 0x10>; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x1964 0x0>, + <&apps_smmu 0x0c04 0x20>, + <&apps_smmu 0x19c4 0x10>; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x1965 0x0>, + <&apps_smmu 0x0c05 0x20>, + <&apps_smmu 0x19c5 0x10>; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x1966 0x0>, + <&apps_smmu 0x0c06 0x20>, + <&apps_smmu 0x19c6 0x10>; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&apps_smmu 0x1967 0x0>, + <&apps_smmu 0x0c07 0x20>, + <&apps_smmu 0x19c7 0x10>; + }; + + compute-cb@8 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <8>; + iommus = <&apps_smmu 0x1968 0x0>, + <&apps_smmu 0x0c08 0x20>, + <&apps_smmu 0x19c8 0x10>; + }; + + /* note: secure cb9 in downstream */ + }; + }; + }; + }; + + thermal-zones { + aoss0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 0>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 1>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 2>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 3>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss3-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 4>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu3-top-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 5>; + + trips { + cpu3_top_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu3_top_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu3_top_crit: cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu3-bottom-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 6>; + + trips { + cpu3_bottom_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu3_bottom_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu3_bottom_crit: cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu4-top-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 7>; + + trips { + cpu4_top_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4_top_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4_top_crit: cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu4-bottom-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 8>; + + trips { + cpu4_bottom_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4_bottom_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4_bottom_crit: cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu5-top-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 9>; + + trips { + cpu5_top_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5_top_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5_top_crit: cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu5-bottom-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 10>; + + trips { + cpu5_bottom_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5_bottom_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5_bottom_crit: cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu6-top-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 11>; + + trips { + cpu6_top_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6_top_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6_top_crit: cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu6-bottom-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 12>; + + trips { + cpu6_bottom_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6_bottom_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6_bottom_crit: cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu7-top-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 13>; + + trips { + cpu7_top_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_top_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_top_crit: cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu7-middle-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 14>; + + trips { + cpu7_middle_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_middle_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_middle_crit: cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu7-bottom-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 15>; + + trips { + cpu7_bottom_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_bottom_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_bottom_crit: cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + aoss1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 0>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 1>; + + trips { + cpu0_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu0_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu0_crit: cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 2>; + + trips { + cpu1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu1_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu1_crit: cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 3>; + + trips { + cpu2_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu2_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu2_crit: cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cdsp0-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 4>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + cdsp0_junction_config: junction-config { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cdsp1-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 5>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + cdsp1_junction_config: junction-config { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cdsp2-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 6>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + cdsp2_junction_config: junction-config { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cdsp3-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 7>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + cdsp3_junction_config: junction-config { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + video-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 8>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mem-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens1 9>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + ddr_config0: ddr0-config { + temperature = <90000>; + hysteresis = <5000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + modem0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 10>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + mdmss0_config0: mdmss0-config0 { + temperature = <102000>; + hysteresis = <3000>; + type = "passive"; + }; + + mdmss0_config1: mdmss0-config1 { + temperature = <105000>; + hysteresis = <3000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + modem1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 11>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + mdmss1_config0: mdmss1-config0 { + temperature = <102000>; + hysteresis = <3000>; + type = "passive"; + }; + + mdmss1_config1: mdmss1-config1 { + temperature = <105000>; + hysteresis = <3000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + modem2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 12>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + mdmss2_config0: mdmss2-config0 { + temperature = <102000>; + hysteresis = <3000>; + type = "passive"; + }; + + mdmss2_config1: mdmss2-config1 { + temperature = <105000>; + hysteresis = <3000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + modem3-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 13>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + mdmss3_config0: mdmss3-config0 { + temperature = <102000>; + hysteresis = <3000>; + type = "passive"; + }; + + mdmss3_config1: mdmss3-config1 { + temperature = <105000>; + hysteresis = <3000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + camera0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 14>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + camera1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 15>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + aoss2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens2 0>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpuss-0-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 1>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + gpu0_junction_config: junction-config { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpuss-1-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 2>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + gpu1_junction_config: junction-config { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpuss-2-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 3>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + gpu2_junction_config: junction-config { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpuss-3-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 4>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + gpu3_junction_config: junction-config { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpuss-4-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 5>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + gpu4_junction_config: junction-config { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpuss-5-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 6>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + gpu5_junction_config: junction-config { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpuss-6-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 7>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + gpu6_junction_config: junction-config { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpuss-7-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 8>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + gpu7_junction_config: junction-config { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi index 8166e3c1ff4e..2e9927b97732 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi @@ -367,7 +367,7 @@ assigned-clocks = <&versaclock6_bb 1>, <&versaclock6_bb 2>, <&versaclock6_bb 3>, <&versaclock6_bb 4>; - assigned-clock-rates = <24000000>, <24000000>, <24000000>, + assigned-clock-rates = <24000000>, <24000000>, <24576000>, <24576000>; OUT1 { @@ -437,20 +437,6 @@ }; }; - /* 0 - lcd_reset */ - /* 1 - lcd_pwr */ - /* 2 - lcd_select */ - /* 3 - backlight-enable */ - /* 4 - Touch_shdwn */ - /* 5 - LCD_H_pol */ - /* 6 - lcd_V_pol */ - gpio_exp1: gpio@20 { - compatible = "onnn,pca9654"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; - touchscreen@26 { compatible = "ilitek,ili2117"; reg = <0x26>; @@ -482,6 +468,16 @@ }; }; }; + + gpio_exp1: gpio@70 { + compatible = "nxp,pca9538"; + reg = <0x70>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "lcd_reset", "lcd_pwr", "lcd_select", + "backlight-enable", "Touch_shdwn", + "LCD_H_pol", "lcd_V_pol"; + }; }; &lvds0 { @@ -638,6 +634,25 @@ #clock-cells = <1>; clock-frequency = <11289600>; + /* Reference versaclock instead of audio_clk_a */ + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&versaclock6_bb 4>, <&audio_clk_b>, + <&audio_clk_c>, + <&cpg CPG_CORE CPG_AUDIO_CLK_I>; + status = "okay"; ports { diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi index d3fc8ffd5b4c..68b04e56ae56 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi @@ -59,7 +59,7 @@ status = "okay"; phy0: ethernet-phy@0 { - compatible = "ethernet-phy-id004d.d074", + compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22"; reg = <0>; interrupt-parent = <&gpio2>; diff --git a/arch/arm64/boot/dts/renesas/r8a774a1-beacon-rzg2m-kit.dts b/arch/arm64/boot/dts/renesas/r8a774a1-beacon-rzg2m-kit.dts index 9ae67263c0df..24da6ee6eccd 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1-beacon-rzg2m-kit.dts +++ b/arch/arm64/boot/dts/renesas/r8a774a1-beacon-rzg2m-kit.dts @@ -58,24 +58,3 @@ clock-names = "du.0", "du.1", "du.2", "dclkin.0", "dclkin.1", "dclkin.2"; }; - -/* Reference versaclock instead of audio_clk_a */ -&rcar_sound { - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&versaclock6_bb 4>, <&audio_clk_b>, - <&audio_clk_c>, - <&cpg CPG_CORE R8A774A1_CLK_S0D4>; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index 7e643243c3be..c21b78685123 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -1678,7 +1678,7 @@ rcar_sound: sound@ec500000 { /* - * #sound-dai-cells is required + * #sound-dai-cells is required if simple-card * * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; diff --git a/arch/arm64/boot/dts/renesas/r8a774b1-beacon-rzg2n-kit.dts b/arch/arm64/boot/dts/renesas/r8a774b1-beacon-rzg2n-kit.dts index 89d708346ba8..8b9df6afffde 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1-beacon-rzg2n-kit.dts +++ b/arch/arm64/boot/dts/renesas/r8a774b1-beacon-rzg2n-kit.dts @@ -14,6 +14,14 @@ compatible = "beacon,beacon-rzg2n", "renesas,r8a774b1"; aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &iic_pmic; serial0 = &scif2; serial1 = &hscif0; serial2 = &hscif1; @@ -46,24 +54,3 @@ clock-names = "du.0", "du.1", "du.3", "dclkin.0", "dclkin.1", "dclkin.3"; }; - -/* Reference versaclock instead of audio_clk_a */ -&rcar_sound { - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&versaclock6_bb 4>, <&audio_clk_b>, - <&audio_clk_c>, - <&cpg CPG_CORE R8A774B1_CLK_S0D4>; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index d541b48c7e38..82216ce7a92a 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -1562,7 +1562,7 @@ rcar_sound: sound@ec500000 { /* - * #sound-dai-cells is required + * #sound-dai-cells is required if simple-card * * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index 151e32ac0368..e21653d86228 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -1317,7 +1317,7 @@ rcar_sound: sound@ec500000 { /* - * #sound-dai-cells is required + * #sound-dai-cells is required if simple-card * * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; diff --git a/arch/arm64/boot/dts/renesas/r8a774e1-beacon-rzg2h-kit.dts b/arch/arm64/boot/dts/renesas/r8a774e1-beacon-rzg2h-kit.dts index 3e9ced3b2d33..146f78cb6f19 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1-beacon-rzg2h-kit.dts +++ b/arch/arm64/boot/dts/renesas/r8a774e1-beacon-rzg2h-kit.dts @@ -14,6 +14,14 @@ compatible = "beacon,beacon-rzg2h", "renesas,r8a774e1"; aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &iic_pmic; serial0 = &scif2; serial1 = &hscif0; serial2 = &hscif1; @@ -51,24 +59,3 @@ clock-names = "du.0", "du.1", "du.3", "dclkin.0", "dclkin.1", "dclkin.3"; }; - -/* Reference versaclock instead of audio_clk_a */ -&rcar_sound { - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&versaclock6_bb 4>, <&audio_clk_b>, - <&audio_clk_c>, - <&cpg CPG_CORE R8A774E1_CLK_S0D4>; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index c5a0e7866b2f..2828e05b40b3 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -1774,7 +1774,7 @@ rcar_sound: sound@ec500000 { /* - * #sound-dai-cells is required + * #sound-dai-cells is required if simple-card * * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi index 07c8763c1e77..f770d160e948 100644 --- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi @@ -1998,7 +1998,7 @@ rcar_sound: sound@ec500000 { /* - * #sound-dai-cells is required + * #sound-dai-cells is required if simple-card * * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi index 1424d4ad941f..09c61696f7fb 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi @@ -1870,7 +1870,7 @@ rcar_sound: sound@ec500000 { /* - * #sound-dai-cells is required + * #sound-dai-cells is required if simple-card * * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index 3c744b7d0dc4..59a18dfcb8cc 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -1750,7 +1750,7 @@ rcar_sound: sound@ec500000 { /* - * #sound-dai-cells is required + * #sound-dai-cells is required if simple-card * * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 997f29521f66..9b4f7ad95ca8 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -1733,7 +1733,7 @@ rcar_sound: sound@ec500000 { /* - * #sound-dai-cells is required + * #sound-dai-cells is required if simple-card * * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts index 004a5eacd460..405404c0843d 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts +++ b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts @@ -287,6 +287,9 @@ }; &pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + avb_pins: avb0 { groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk"; function = "avb0"; @@ -316,6 +319,11 @@ groups = "scif0_data"; function = "scif0"; }; + + scif_clk_pins: scif_clk { + groups = "scif_clk_b"; + function = "scif_clk"; + }; }; &rpc { @@ -391,3 +399,7 @@ status = "okay"; }; + +&scif_clk { + clock-frequency = <14745600>; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a77980a-condor-i.dts b/arch/arm64/boot/dts/renesas/r8a77980a-condor-i.dts index 9f488dea0f34..53fc21709345 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980a-condor-i.dts +++ b/arch/arm64/boot/dts/renesas/r8a77980a-condor-i.dts @@ -13,3 +13,7 @@ model = "Renesas Condor-I board based on r8a77980A (ES2.0)"; compatible = "renesas,condor-i", "renesas,r8a77980a", "renesas,r8a77980"; }; + +&mmc0 { + mmc-hs400-1_8v; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 3053b4b21497..d4718f144e33 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -1469,7 +1469,7 @@ rcar_sound: sound@ec500000 { /* - * #sound-dai-cells is required + * #sound-dai-cells is required if simple-card * * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index f040d03e0a87..e25024a7b66c 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -1037,7 +1037,7 @@ rcar_sound: sound@ec500000 { /* - * #sound-dai-cells is required + * #sound-dai-cells is required if simple-card * * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi index 045d70535519..dd8e0e159526 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi @@ -5,6 +5,7 @@ * Copyright (C) 2021 Renesas Electronics Corp. */ +#include <dt-bindings/gpio/gpio.h> #include "r8a779f0.dtsi" / { @@ -32,6 +33,12 @@ reg = <0x4 0x80000000 0x0 0x80000000>; }; + rc21012_ufs: clk-rc21012-ufs { + compatible = "fixed-clock"; + clock-frequency = <38400000>; + #clock-cells = <0>; + }; + reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; regulator-name = "fixed-1.8V"; @@ -67,6 +74,21 @@ status = "okay"; }; +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + gpio_exp_20: gpio@20 { + compatible = "ti,tca9554"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + &i2c4 { pinctrl-0 = <&i2c4_pins>; pinctrl-names = "default"; @@ -112,6 +134,11 @@ function = "hscif0"; }; + i2c0_pins: i2c0 { + groups = "i2c0"; + function = "i2c0"; + }; + i2c4_pins: i2c4 { groups = "i2c4"; function = "i2c4"; @@ -150,3 +177,14 @@ &scif_clk { clock-frequency = <24000000>; }; + +&ufs { + status = "okay"; +}; + +&ufs30_clk { + compatible = "gpio-gate-clock"; + clocks = <&rc21012_ufs>; + enable-gpios = <&gpio_exp_20 4 GPIO_ACTIVE_LOW>; + /delete-property/ clock-frequency; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index 67a4f2d4480d..f20b612b2b9a 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -14,6 +14,60 @@ #address-cells = <2>; #size-cells = <2>; + cluster01_opp: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <880000>; + clock-latency-ns = <500000>; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <880000>; + clock-latency-ns = <500000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <880000>; + clock-latency-ns = <500000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <880000>; + clock-latency-ns = <500000>; + opp-suspend; + }; + }; + + cluster23_opp: opp-table-1 { + compatible = "operating-points-v2"; + opp-shared; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <880000>; + clock-latency-ns = <500000>; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <880000>; + clock-latency-ns = <500000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <880000>; + clock-latency-ns = <500000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <880000>; + clock-latency-ns = <500000>; + opp-suspend; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -65,6 +119,7 @@ enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; + operating-points-v2 = <&cluster01_opp>; }; a55_1: cpu@100 { @@ -76,6 +131,7 @@ enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; + operating-points-v2 = <&cluster01_opp>; }; a55_2: cpu@10000 { @@ -87,6 +143,7 @@ enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; + operating-points-v2 = <&cluster01_opp>; }; a55_3: cpu@10100 { @@ -98,6 +155,7 @@ enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; + operating-points-v2 = <&cluster01_opp>; }; a55_4: cpu@20000 { @@ -109,6 +167,7 @@ enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; + operating-points-v2 = <&cluster23_opp>; }; a55_5: cpu@20100 { @@ -120,6 +179,7 @@ enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; + operating-points-v2 = <&cluster23_opp>; }; a55_6: cpu@30000 { @@ -131,6 +191,7 @@ enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; + operating-points-v2 = <&cluster23_opp>; }; a55_7: cpu@30100 { @@ -142,6 +203,7 @@ enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; + operating-points-v2 = <&cluster23_opp>; }; L3_CA55_0: cache-controller-0 { @@ -989,6 +1051,7 @@ power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; resets = <&cpg 706>; max-frequency = <200000000>; + iommus = <&ipmmu_ds0 32>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi index c10740aee9f6..bb4a5270f71b 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi @@ -97,6 +97,27 @@ reg = <0x6 0x00000000 0x1 0x00000000>; }; + mini-dp-con { + compatible = "dp-connector"; + label = "CN5"; + type = "mini"; + + port { + mini_dp_con_in: endpoint { + remote-endpoint = <&sn65dsi86_out>; + }; + }; + }; + + reg_1p2v: regulator-1p2v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; regulator-name = "fixed-1.8V"; @@ -114,6 +135,12 @@ regulator-boot-on; regulator-always-on; }; + + sn65dsi86_refclk: clk-x6 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <38400000>; + }; }; &avb0 { @@ -134,6 +161,23 @@ }; }; +&dsi0 { + status = "okay"; + + ports { + port@1 { + dsi0_out: endpoint { + remote-endpoint = <&sn65dsi86_in>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&du { + status = "okay"; +}; + &extal_clk { clock-frequency = <16666666>; }; @@ -172,6 +216,51 @@ }; }; +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + bridge@2c { + compatible = "ti,sn65dsi86"; + reg = <0x2c>; + + clocks = <&sn65dsi86_refclk>; + clock-names = "refclk"; + + interrupt-parent = <&intc_ex>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + + enable-gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; + + vccio-supply = <®_1p8v>; + vpll-supply = <®_1p8v>; + vcca-supply = <®_1p2v>; + vcc-supply = <®_1p2v>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + sn65dsi86_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + sn65dsi86_out: endpoint { + remote-endpoint = <&mini_dp_con_in>; + }; + }; + }; + }; +}; + &mmc0 { pinctrl-0 = <&mmc_pins>; pinctrl-1 = <&mmc_pins>; @@ -221,6 +310,11 @@ function = "i2c0"; }; + i2c1_pins: i2c1 { + groups = "i2c1"; + function = "i2c1"; + }; + keys_pins: keys { pins = "GP_5_0", "GP_5_1", "GP_5_2"; bias-pull-up; diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index 45d8d927ad26..7a87a5dc1b6a 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -39,6 +39,12 @@ clock-latency-ns = <500000>; opp-suspend; }; + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <880000>; + clock-latency-ns = <500000>; + turbo-mode; + }; }; cpus { @@ -1203,6 +1209,136 @@ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; + fcpvd0: fcp@fea10000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea10000 0 0x200>; + clocks = <&cpg CPG_MOD 508>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 508>; + }; + + fcpvd1: fcp@fea11000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea11000 0 0x200>; + clocks = <&cpg CPG_MOD 509>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 509>; + }; + + vspd0: vsp@fea20000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea20000 0 0x7000>; + interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 830>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 830>; + + renesas,fcp = <&fcpvd0>; + }; + + vspd1: vsp@fea28000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea28000 0 0x7000>; + interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 831>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 831>; + + renesas,fcp = <&fcpvd1>; + }; + + du: display@feb00000 { + compatible = "renesas,du-r8a779g0"; + reg = <0 0xfeb00000 0 0x40000>; + interrupts = <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 411>; + clock-names = "du.0"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 411>; + reset-names = "du.0"; + renesas,vsps = <&vspd0 0>, <&vspd1 0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_dsi0: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + du_out_dsi1: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + }; + + dsi0: dsi-encoder@fed80000 { + compatible = "renesas,r8a779g0-dsi-csi2-tx"; + reg = <0 0xfed80000 0 0x10000>; + clocks = <&cpg CPG_MOD 415>, + <&cpg CPG_CORE R8A779G0_CLK_DSIEXT>, + <&cpg CPG_CORE R8A779G0_CLK_DSIREF>; + clock-names = "fck", "dsi", "pll"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 415>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&du_out_dsi0>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + }; + + dsi1: dsi-encoder@fed90000 { + compatible = "renesas,r8a779g0-dsi-csi2-tx"; + reg = <0 0xfed90000 0 0x10000>; + clocks = <&cpg CPG_MOD 416>, + <&cpg CPG_CORE R8A779G0_CLK_DSIEXT>, + <&cpg CPG_CORE R8A779G0_CLK_DSIREF>; + clock-names = "fck", "dsi", "pll"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 416>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + remote-endpoint = <&du_out_dsi1>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + }; + prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index 3f7d451b1199..c8a83e42c4f3 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -531,6 +531,8 @@ gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pinctrl 0 0 152>; + #interrupt-cells = <2>; + interrupt-controller; clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>; power-domains = <&cpg>; resets = <&cpg R9A07G043_GPIO_RSTN>, diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi index 6af5f3bca2d1..9d854706ada5 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi @@ -49,9 +49,81 @@ }; }; +&pinctrl { + interrupt-parent = <&irqc>; +}; + &soc { interrupt-parent = <&gic>; + irqc: interrupt-controller@110a0000 { + compatible = "renesas,r9a07g043u-irqc", + "renesas,rzg2l-irqc"; + reg = <0 0x110a0000 0 0x10000>; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + interrupts = <SOC_PERIPHERAL_IRQ(0) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(1) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(2) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(3) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(4) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(5) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(6) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(7) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(8) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(444) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(445) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(446) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(447) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(448) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(449) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(450) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(451) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(452) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(453) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(454) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(455) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(456) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(457) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(458) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(459) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(460) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(461) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(462) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(463) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(464) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(465) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(466) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(467) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(468) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(469) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(470) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(471) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(472) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(473) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(474) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(475) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(25) IRQ_TYPE_EDGE_RISING>; + interrupt-names = "nmi", + "irq0", "irq1", "irq2", "irq3", + "irq4", "irq5", "irq6", "irq7", + "tint0", "tint1", "tint2", "tint3", + "tint4", "tint5", "tint6", "tint7", + "tint8", "tint9", "tint10", "tint11", + "tint12", "tint13", "tint14", "tint15", + "tint16", "tint17", "tint18", "tint19", + "tint20", "tint21", "tint22", "tint23", + "tint24", "tint25", "tint26", "tint27", + "tint28", "tint29", "tint30", "tint31", + "bus-err"; + clocks = <&cpg CPG_MOD R9A07G043_IA55_CLK>, + <&cpg CPG_MOD R9A07G043_IA55_PCLK>; + clock-names = "clk", "pclk"; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_IA55_RESETN>; + }; + gic: interrupt-controller@11900000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; diff --git a/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts b/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts index 11e1d51c7c0e..d6737395df67 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts @@ -80,6 +80,11 @@ }; }; +&pwc { + renesas,rzv2m-pwc-power; + status = "okay"; +}; + &uart0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi index 0373ec409d54..b5d6f7701ef1 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi @@ -69,6 +69,54 @@ clock-names = "clk"; }; + sdhi0: mmc@85000000 { + compatible = "renesas,sdhi-r9a09g011", + "renesas,rcar-gen3-sdhi"; + reg = <0x0 0x85000000 0 0x2000>; + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A09G011_SDI0_IMCLK>, + <&cpg CPG_MOD R9A09G011_SDI0_CLK_HS>, + <&cpg CPG_MOD R9A09G011_SDI0_IMCLK2>, + <&cpg CPG_MOD R9A09G011_SDI0_ACLK>; + clock-names = "core", "clkh", "cd", "aclk"; + resets = <&cpg R9A09G011_SDI0_IXRST>; + power-domains = <&cpg>; + status = "disabled"; + }; + + sdhi1: mmc@85010000 { + compatible = "renesas,sdhi-r9a09g011", + "renesas,rcar-gen3-sdhi"; + reg = <0x0 0x85010000 0 0x2000>; + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A09G011_SDI1_IMCLK>, + <&cpg CPG_MOD R9A09G011_SDI1_CLK_HS>, + <&cpg CPG_MOD R9A09G011_SDI1_IMCLK2>, + <&cpg CPG_MOD R9A09G011_SDI1_ACLK>; + clock-names = "core", "clkh", "cd", "aclk"; + resets = <&cpg R9A09G011_SDI1_IXRST>; + power-domains = <&cpg>; + status = "disabled"; + }; + + emmc: mmc@85020000 { + compatible = "renesas,sdhi-r9a09g011", + "renesas,rcar-gen3-sdhi"; + reg = <0x0 0x85020000 0 0x2000>; + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A09G011_EMM_IMCLK>, + <&cpg CPG_MOD R9A09G011_EMM_CLK_HS>, + <&cpg CPG_MOD R9A09G011_EMM_IMCLK2>, + <&cpg CPG_MOD R9A09G011_EMM_ACLK>; + clock-names = "core", "clkh", "cd", "aclk"; + resets = <&cpg R9A09G011_EMM_IXRST>; + power-domains = <&cpg>; + status = "disabled"; + }; + avb: ethernet@a3300000 { compatible = "renesas,etheravb-r9a09g011","renesas,etheravb-rzv2m"; reg = <0 0xa3300000 0 0x800>; @@ -117,7 +165,7 @@ power-domains = <&cpg>; #address-cells = <1>; #size-cells = <0>; - status = "disable"; + status = "disabled"; }; cpg: clock-controller@a3500000 { @@ -130,6 +178,14 @@ #power-domain-cells = <0>; }; + pwc: pwc@a3700000 { + compatible = "renesas,r9a09g011-pwc", "renesas,rzv2m-pwc"; + reg = <0 0xa3700000 0 0x800>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + sys: system-controller@a3f03000 { compatible = "renesas,r9a09g011-sys"; reg = <0 0xa3f03000 0 0x400>; diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi index 931efc07d6fb..49ecd33aeeb8 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi @@ -6,6 +6,7 @@ */ #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irqc-rzg2l.h> #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> / { @@ -77,6 +78,8 @@ compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22"; reg = <7>; + interrupt-parent = <&irqc>; + interrupts = <RZG2L_IRQ2 IRQ_TYPE_LEVEL_LOW>; rxc-skew-psec = <2400>; txc-skew-psec = <2400>; rxdv-skew-psec = <0>; @@ -104,6 +107,8 @@ compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22"; reg = <7>; + interrupt-parent = <&irqc>; + interrupts = <RZG2L_IRQ7 IRQ_TYPE_LEVEL_LOW>; rxc-skew-psec = <2400>; txc-skew-psec = <2400>; rxdv-skew-psec = <0>; @@ -151,7 +156,8 @@ <RZG2L_PORT_PINMUX(3, 2, 1)>, /* ET0_RXD0 */ <RZG2L_PORT_PINMUX(3, 3, 1)>, /* ET0_RXD1 */ <RZG2L_PORT_PINMUX(4, 0, 1)>, /* ET0_RXD2 */ - <RZG2L_PORT_PINMUX(4, 1, 1)>; /* ET0_RXD3 */ + <RZG2L_PORT_PINMUX(4, 1, 1)>, /* ET0_RXD3 */ + <RZG2L_PORT_PINMUX(5, 1, 7)>; /* IRQ2 */ }; eth1_pins: eth1 { @@ -169,7 +175,8 @@ <RZG2L_PORT_PINMUX(9, 1, 1)>, /* ET1_RXD0 */ <RZG2L_PORT_PINMUX(9, 2, 1)>, /* ET1_RXD1 */ <RZG2L_PORT_PINMUX(9, 3, 1)>, /* ET1_RXD2 */ - <RZG2L_PORT_PINMUX(10, 0, 1)>; /* ET1_RXD3 */ + <RZG2L_PORT_PINMUX(10, 0, 1)>, /* ET1_RXD3 */ + <RZG2L_PORT_PINMUX(18, 5, 1)>; /* IRQ7 */ }; sdhi0_emmc_pins: sd0emmc { diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi index d97473401819..4a3d5037821f 100644 --- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi +++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi @@ -799,9 +799,6 @@ pinctrl-0 = <&sound_pins>, <&sound_clk_pins>; pinctrl-names = "default"; - /* Single DAI */ - #sound-dai-cells = <0>; - /* audio_clkout0/1/2/3 */ #clock-cells = <1>; clock-frequency = <12288000 11289600>; diff --git a/arch/arm64/boot/dts/renesas/ulcb-audio-graph-card-mix+split.dtsi b/arch/arm64/boot/dts/renesas/ulcb-audio-graph-card-mix+split.dtsi new file mode 100644 index 000000000000..672b0a224ef9 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/ulcb-audio-graph-card-mix+split.dtsi @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree for ULCB + Audio Graph Card (MIX) + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +/* + * Note: + * The HDMI output is ignored due to the limited number of subdevices + * + * (A) CPU0 (2ch) <-----> (2ch) (X) ak4613 (MIX-0) + * (B) CPU1 (2ch) --/ (MIX-1) + * + * (A) aplay -D plughw:0,0 xxx.wav + * (B) aplay -D plughw:0,1 xxx.wav + * + * (A) arecord -D plughw:0,0 xxx.wav + */ + +/ { + sound_card: sound { + compatible = "audio-graph-scu-card"; + label = "rcar-sound"; + + routing = "ak4613 Playback", "DAI0 Playback", + "ak4613 Playback", "DAI1 Playback", + "DAI0 Capture", "ak4613 Capture"; + + dais = <&rsnd_port0 /* (A) CPU0 */ + &rsnd_port1 /* (B) CPU1 */ + >; + }; +}; + +&ak4613 { + port { + #address-cells = <1>; + #size-cells = <0>; + + /* + * (X) ak4613 + */ + prefix = "ak4613"; + convert-rate = <48000>; + + /* (A) CPU0 <-> (X) ak4613 */ + ak4613_ep1: endpoint@0 { + reg = <0>; + remote-endpoint = <&rsnd_for_ak4613_1>; + }; + /* (B) CPU1 -> (X) ak4613 */ + ak4613_ep2: endpoint@1 { + reg = <1>; + remote-endpoint = <&rsnd_for_ak4613_2>; + }; + }; +}; + +&rcar_sound { + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* + * (A) CPU0 + */ + rsnd_port0: port@0 { + reg = <0>; + rsnd_for_ak4613_1: endpoint { + remote-endpoint = <&ak4613_ep1>; + bitclock-master; + frame-master; + playback = <&src1 &ctu02 &mix0 &dvc0 &ssi0>; + capture = <&ssi1 &src0 &dvc1>; + }; + }; + /* + * (B) CPU1 + */ + rsnd_port1: port@1 { + reg = <1>; + rsnd_for_ak4613_2: endpoint { + remote-endpoint = <&ak4613_ep2>; + bitclock-master; + frame-master; + playback = <&src2 &ctu03 &mix0 &dvc0 &ssi0>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/ulcb-audio-graph-card.dtsi b/arch/arm64/boot/dts/renesas/ulcb-audio-graph-card.dtsi new file mode 100644 index 000000000000..3be54df645e6 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/ulcb-audio-graph-card.dtsi @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree for ULCB + Audio Graph Card + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +/* + * (A) CPU0 <-----> ak4613 + * (B) CPU1 -----> HDMI + * + * (A) aplay -D plughw:0,0 xxx.wav + * (B) aplay -D plughw:0,1 xxx.wav + * + * (A) arecord -D plughw:0,0 xxx.wav + */ + +/ { + sound_card: sound { + compatible = "audio-graph-card"; + label = "rcar-sound"; + + dais = <&rsnd_port0 /* (A) CPU0 <-> ak4613 */ + &rsnd_port1 /* (B) CPU1 -> HDMI */ + >; + }; +}; + +&ak4613 { + #sound-dai-cells = <0>; + + port { + /* + * (A) CPU0 <-> ak4613 + */ + ak4613_endpoint: endpoint { + remote-endpoint = <&rsnd_for_ak4613>; + }; + }; +}; + +&hdmi0 { + ports { + port@2 { + /* + * (B) CPU1 -> HDMI + */ + dw_hdmi0_snd_in: endpoint { + remote-endpoint = <&rsnd_for_hdmi>; + }; + }; + }; +}; + +&rcar_sound { + ports { + #address-cells = <1>; + #size-cells = <0>; + rsnd_port0: port@0 { + /* + * (A) CPU0 <-> ak4613 + */ + reg = <0>; + rsnd_for_ak4613: endpoint { + remote-endpoint = <&ak4613_endpoint>; + bitclock-master; + frame-master; + playback = <&ssi0>, <&src0>, <&dvc0>; + capture = <&ssi1>, <&src1>, <&dvc1>; + }; + }; + rsnd_port1: port@1 { + /* + * (B) CPU1 -> HDMI + */ + reg = <1>; + rsnd_for_hdmi: endpoint { + remote-endpoint = <&dw_hdmi0_snd_in>; + bitclock-master; + frame-master; + playback = <&ssi2>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/ulcb-audio-graph-card2-mix+split.dtsi b/arch/arm64/boot/dts/renesas/ulcb-audio-graph-card2-mix+split.dtsi new file mode 100644 index 000000000000..75b024e3fef1 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/ulcb-audio-graph-card2-mix+split.dtsi @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree for ULCB + Audio Graph Card2 (MIX + TDM Split) + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +/* + * Note: + * The HDMI output is ignored due to the limited number of subdevices + * + * (A) CPU0 (2ch) <----> (2ch) (X) ak4613 (MIX-0) + * (B) CPU1 (2ch) --/ (MIX-1) + * + * (A) aplay -D plughw:0,0 xxx.wav + * (B) aplay -D plughw:0,1 xxx.wav + * + * (A) arecord -D plughw:0,0 xxx.wav + */ +/ { + sound_card: sound { + compatible = "audio-graph-card2"; + label = "rcar-sound"; + + routing = "ak4613 Playback", "DAI0 Playback", + "ak4613 Playback", "DAI1 Playback", + "DAI0 Capture", "ak4613 Capture"; + + /delete-property/ dais; + links = <&fe_a /* (A) CPU0 */ + &fe_b /* (B) CPU1 */ + &be_x /* (X) ak4613 */ + >; + + dpcm { + #address-cells = <1>; + #size-cells = <0>; + + ports@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* + * FE + * (A) CPU0 (MIX-0) + * (B) CPU1 (MIX-1) + */ + fe_a: port@0 { reg = <0>; fe_a_ep: endpoint { remote-endpoint = <&rsnd_a_ep>; }; }; + fe_b: port@1 { reg = <1>; fe_b_ep: endpoint { remote-endpoint = <&rsnd_b_ep>; }; }; + }; + + ports@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* + * BE + * (X) ak4613 + */ + be_x: port@0 { reg = <0>; be_x_ep: endpoint { remote-endpoint = <&ak4613_x_ep>; }; }; + }; + }; + }; +}; + +&ak4613 { + port { + /* + * (X) ak4613 + */ + prefix = "ak4613"; + convert-rate = <48000>; + + ak4613_x_ep: endpoint { + remote-endpoint = <&be_x_ep>; + }; + }; +}; + +&rcar_sound { + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* + * (A) CPU0 + */ + port@0 { + reg = <0>; + rsnd_a_ep: endpoint { + remote-endpoint = <&fe_a_ep>; + bitclock-master; + frame-master; + playback = <&src1 &ctu02 &mix0 &dvc0 &ssi0>; + capture = <&ssi1 &src0 &dvc1>; + }; + }; + /* + * (B) CPU1 + */ + port@1 { + reg = <1>; + rsnd_b_ep: endpoint { + remote-endpoint = <&fe_b_ep>; + bitclock-master; + frame-master; + playback = <&src2 &ctu03 &mix0 &dvc0 &ssi0>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/ulcb-audio-graph-card2.dtsi b/arch/arm64/boot/dts/renesas/ulcb-audio-graph-card2.dtsi new file mode 100644 index 000000000000..5ebec1235843 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/ulcb-audio-graph-card2.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree for ULCB + Audio Graph Card2 + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +/* + * (A) CPU0 <----> ak4613 + * (B) CPU1 ----> HDMI + * + * (A) aplay -D plughw:0,0 xxx.wav + * (B) aplay -D plughw:0,1 xxx.wav + * + * (A) arecord -D plughw:0,0 xxx.wav + */ +#include "ulcb-audio-graph-card.dtsi" + +&sound_card { + compatible = "audio-graph-card2"; + + /delete-property/ dais; + links = <&rsnd_port0 /* (A) CPU0 <-> ak4613 */ + &rsnd_port1 /* (B) CPU1 -> HDMI */ + >; +}; diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf-audio-graph-card-mix+split.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf-audio-graph-card-mix+split.dtsi new file mode 100644 index 000000000000..9b01354940fd --- /dev/null +++ b/arch/arm64/boot/dts/renesas/ulcb-kf-audio-graph-card-mix+split.dtsi @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree for ULCB + Kingfisher + Audio Graph Card (MIX + TDM Split) + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +/* + * Note: + * The HDMI output is ignored due to the limited number of subdevices + * + * (A) CPU0 (2ch) <----> (2ch) (X) ak4613 (MIX-0) + * (B) CPU1 (2ch) --/ (MIX-1) + * (C) CPU2 (2ch) ----> (8ch) (Y) PCM3168A-p (TDM-0 : 0,1ch) + * (D) CPU3 (2ch) --/ (TDM-1 : 2,3ch) + * (E) CPU4 (2ch) --/ (TDM-2 : 4,5ch) + * (F) CPU5 (2ch) --/ (TDM-3 : 6,7ch) + * (G) CPU6 (6ch) <---- (6ch) (Z) PCM3168A-c + * + * (A) aplay -D plughw:0,0 xxx.wav (MIX-0) + * (B) aplay -D plughw:0,1 xxx.wav (MIX-1) + * (C) aplay -D plughw:0,2 xxx.wav (TDM-0) + * (D) aplay -D plughw:0,3 xxx.wav (TDM-1) + * (E) aplay -D plughw:0,4 xxx.wav (TDM-2) + * (F) aplay -D plughw:0,5 xxx.wav (TDM-3) + * + * (A) arecord -D plughw:0,0 xxx.wav + * (G) arecord -D plughw:0,6 xxx.wav + */ + +&sound_card { + routing = "ak4613 Playback", "DAI0 Playback", + "ak4613 Playback", "DAI1 Playback", + "DAI0 Capture", "ak4613 Capture", + "pcm3168a Playback", "DAI2 Playback", + "pcm3168a Playback", "DAI3 Playback", + "pcm3168a Playback", "DAI4 Playback", + "pcm3168a Playback", "DAI5 Playback"; + + dais = <&rsnd_port0 /* (A) CPU0 */ + &rsnd_port1 /* (B) CPU1 */ + &rsnd_port2 /* (C) CPU2 */ + &rsnd_port3 /* (D) CPU3 */ + &rsnd_port4 /* (E) CPU4 */ + &rsnd_port5 /* (F) CPU5 */ + &rsnd_port6 /* (G) GPU6 */ + >; +}; + +&pcm3168a { + ports { + #address-cells = <1>; + #size-cells = <0>; + mclk-fs = <512>; + + /* + * (Y) PCM3168A-p + */ + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + prefix = "pcm3168a"; + convert-channels = <8>; /* to 8ch TDM */ + + /* (C) CPU2 -> (Y) PCM3168A-p */ + pcm3168a_endpoint_p1: endpoint@0 { + reg = <0>; + remote-endpoint = <&rsnd_for_pcm3168a_play1>; + clocks = <&clksndsel>; + }; + /* (D) CPU3 -> (Y) PCM3168A-p */ + pcm3168a_endpoint_p2: endpoint@1 { + reg = <1>; + remote-endpoint = <&rsnd_for_pcm3168a_play2>; + clocks = <&clksndsel>; + }; + /* (E) CPU4 -> (Y) PCM3168A-p */ + pcm3168a_endpoint_p3: endpoint@2 { + reg = <2>; + remote-endpoint = <&rsnd_for_pcm3168a_play3>; + clocks = <&clksndsel>; + }; + /* (F) CPU5 -> (Y) PCM3168A-p */ + pcm3168a_endpoint_p4: endpoint@3 { + reg = <3>; + remote-endpoint = <&rsnd_for_pcm3168a_play4>; + clocks = <&clksndsel>; + }; + }; + /* + * (Z) PCM3168A-c + */ + port@1 { + reg = <1>; + /* (G) CPU6 <- PCM3168A-c */ + pcm3168a_endpoint_c: endpoint { + remote-endpoint = <&rsnd_for_pcm3168a_capture>; + clocks = <&clksndsel>; + }; + }; + }; +}; + +&rcar_sound { + ports { + /* rsnd_port0-1 are defined in ulcb.dtsi */ + + /* + * (C) CPU2 + */ + rsnd_port2: port@2 { + reg = <2>; + rsnd_for_pcm3168a_play1: endpoint { + remote-endpoint = <&pcm3168a_endpoint_p1>; + bitclock-master; + frame-master; + playback = <&ssiu30 &ssi3>; + }; + }; + /* + * (D) CPU3 + */ + rsnd_port3: port@3 { + reg = <3>; + rsnd_for_pcm3168a_play2: endpoint { + remote-endpoint = <&pcm3168a_endpoint_p2>; + bitclock-master; + frame-master; + playback = <&ssiu31 &ssi3>; + }; + }; + /* + * (E) CPU4 + */ + rsnd_port4: port@4 { + reg = <4>; + rsnd_for_pcm3168a_play3: endpoint { + remote-endpoint = <&pcm3168a_endpoint_p3>; + bitclock-master; + frame-master; + playback = <&ssiu32 &ssi3>; + }; + }; + /* + * (F) CPU5 + */ + rsnd_port5: port@5 { + reg = <5>; + rsnd_for_pcm3168a_play4: endpoint { + remote-endpoint = <&pcm3168a_endpoint_p4>; + bitclock-master; + frame-master; + playback = <&ssiu33 &ssi3>; + }; + }; + /* + * (G) CPU6 + */ + rsnd_port6: port@6 { + reg = <6>; + rsnd_for_pcm3168a_capture: endpoint { + remote-endpoint = <&pcm3168a_endpoint_c>; + bitclock-master; + frame-master; + dai-tdm-slot-num = <6>; + capture = <&ssi4>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf-audio-graph-card.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf-audio-graph-card.dtsi new file mode 100644 index 000000000000..1db99b7608f0 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/ulcb-kf-audio-graph-card.dtsi @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree for ULCB + Kingfisher + Audio Graph Card + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +/* + * (A) CPU0 <----> ak4613 + * (B) CPU1 ----> HDMI + * (C) CPU2 ----> PCM3168A-p (8ch) + * (D) CPU3 <---- PCM3168A-c (6ch) + * + * (A) aplay -D plughw:0,0 xxx.wav + * (B) aplay -D plughw:0,1 xxx.wav + * (C) aplay -D plughw:0,2 xxx.wav + * + * (A) arecord -D plughw:0,0 xxx.wav + * (D) arecord -D plughw:0,3 xxx.wav + */ + +&sound_card { + dais = <&rsnd_port0 /* (A) CPU0 <-> ak4613 */ + &rsnd_port1 /* (B) CPU1 -> HDMI */ + &rsnd_port2 /* (C) CPU2 -> PCM3168A-p */ + &rsnd_port3 /* (D) CPU3 <- PCM3168A-c */ + >; +}; + +&pcm3168a { + ports { + #address-cells = <1>; + #size-cells = <0>; + mclk-fs = <512>; + /* + * (C) CPU2 -> PCM3168A-p + */ + port@0 { + reg = <0>; + pcm3168a_endpoint_p: endpoint { + remote-endpoint = <&rsnd_for_pcm3168a_play>; + clocks = <&clksndsel>; + }; + }; + /* + * (D) CPU3 <- PCM3168A-c + */ + port@1 { + reg = <1>; + pcm3168a_endpoint_c: endpoint { + remote-endpoint = <&rsnd_for_pcm3168a_capture>; + clocks = <&clksndsel>; + }; + }; + }; +}; + +&rcar_sound { + ports { + /* rsnd_port0/1 are defined in ulcb.dtsi */ + /* + * (C) CPU2 -> PCM3168A-p + */ + rsnd_port2: port@2 { + reg = <2>; + rsnd_for_pcm3168a_play: endpoint { + remote-endpoint = <&pcm3168a_endpoint_p>; + bitclock-master; + frame-master; + dai-tdm-slot-num = <8>; + playback = <&ssi3>; + }; + }; + /* + * (D) CPU3 <- PCM3168A-c + */ + rsnd_port3: port@3 { + reg = <3>; + rsnd_for_pcm3168a_capture: endpoint { + remote-endpoint = <&pcm3168a_endpoint_c>; + bitclock-master; + frame-master; + dai-tdm-slot-num = <6>; + capture = <&ssi4>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf-audio-graph-card2-mix+split.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf-audio-graph-card2-mix+split.dtsi new file mode 100644 index 000000000000..da644128a9ae --- /dev/null +++ b/arch/arm64/boot/dts/renesas/ulcb-kf-audio-graph-card2-mix+split.dtsi @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree for ULCB + Kingfisher + Audio Graph Card2 (MIX + TDM Split) + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +/* + * Note: + * The HDMI output is ignored due to the limited number of subdevices + * + * (A) CPU0 (2ch) <----> (2ch) (X) ak4613 (MIX-0) + * (B) CPU1 (2ch) --/ (MIX-1) + * (C) CPU3 (2ch) ----> (8ch) (Y) PCM3168A-p (TDM-0 : 0,1ch) + * (D) CPU2 (2ch) --/ (TDM-1 : 2,3ch) + * (E) CPU4 (2ch) --/ (TDM-2 : 4,5ch) + * (F) CPU5 (2ch) --/ (TDM-3 : 6,7ch) + * (G) CPU6 (6ch) <---- (6ch) (Z) PCM3168A-c + * + * (A) aplay -D plughw:0,0 xxx.wav (MIX-0) + * (B) aplay -D plughw:0,1 xxx.wav (MIX-1) + * (C) aplay -D plughw:0,2 xxx.wav (TDM-0) + * (D) aplay -D plughw:0,3 xxx.wav (TDM-1) + * (E) aplay -D plughw:0,4 xxx.wav (TDM-2) + * (F) aplay -D plughw:0,5 xxx.wav (TDM-3) + * + * (A) arecord -D plughw:0,0 xxx.wav + * (G) arecord -D plughw:0,6 xxx.wav + */ +&sound_card { + routing = "ak4613 Playback", "DAI0 Playback", + "ak4613 Playback", "DAI1 Playback", + "DAI0 Capture", "ak4613 Capture", + "pcm3168a Playback", "DAI2 Playback", + "pcm3168a Playback", "DAI3 Playback", + "pcm3168a Playback", "DAI4 Playback", + "pcm3168a Playback", "DAI5 Playback", + "DAI6 Capture", "pcm3168a Capture"; + + /delete-property/ dais; + links = <&fe_a /* (A) CPU0 */ + &fe_b /* (B) CPU1 */ + &fe_c /* (C) CPU2 */ + &fe_d /* (D) CPU3 */ + &fe_e /* (E) CPU4 */ + &fe_f /* (F) CPU5 */ + &rsnd_g /* (G) CPU6 */ + &be_x /* (X) ak4613 */ + &be_y /* (Y) PCM3168A-p */ + >; + + dpcm { + ports@0 { + /* + * FE + * + * (A)/(B) are defined on ulcb + * (C) CPU2 + * (D) CPU3 + * (E) CPU4 + * (F) CPU5 + */ + fe_c: port@2 { reg = <2>; fe_c_ep: endpoint { remote-endpoint = <&rsnd_c_ep>; }; }; + fe_d: port@3 { reg = <3>; fe_d_ep: endpoint { remote-endpoint = <&rsnd_d_ep>; }; }; + fe_e: port@4 { reg = <4>; fe_e_ep: endpoint { remote-endpoint = <&rsnd_e_ep>; }; }; + fe_f: port@5 { reg = <5>; fe_f_ep: endpoint { remote-endpoint = <&rsnd_f_ep>; }; }; + }; + + ports@1 { + /* + * BE + * + * (X) is defined on ulcb + * (Y) PCM3168A-p + */ + be_y: port@1 { reg = <1>; be_y_ep: endpoint { remote-endpoint = <&pcm3168a_y_ep>; }; }; + }; + }; +}; + +&pcm3168a { + ports { + #address-cells = <1>; + #size-cells = <0>; + + mclk-fs = <512>; + prefix = "pcm3168a"; + + /* + * (Y) PCM3168A-p + */ + port@0 { + reg = <0>; + convert-channels = <8>; /* to 8ch TDM */ + pcm3168a_y_ep: endpoint { + remote-endpoint = <&be_y_ep>; + clocks = <&clksndsel>; + }; + }; + /* + * (Z) PCM3168A-c + */ + port@1 { + reg = <1>; + pcm3168a_z_ep: endpoint { + remote-endpoint = <&rsnd_g_ep>; + clocks = <&clksndsel>; + }; + }; + }; +}; + +&rcar_sound { + ports { + /* (A)/(B) are defined in ulcb.dtsi */ + + /* + * (C) CPU2 + */ + port@2 { + reg = <2>; + rsnd_c_ep: endpoint { + remote-endpoint = <&fe_c_ep>; + bitclock-master; + frame-master; + playback = <&ssiu30 &ssi3>; + }; + }; + /* + * (D) CPU3 + */ + port@3 { + reg = <3>; + rsnd_d_ep: endpoint { + remote-endpoint = <&fe_d_ep>; + bitclock-master; + frame-master; + playback = <&ssiu31 &ssi3>; + }; + }; + /* + * (E) CPU4 + */ + port@4 { + reg = <4>; + rsnd_e_ep: endpoint { + remote-endpoint = <&fe_e_ep>; + bitclock-master; + frame-master; + playback = <&ssiu32 &ssi3>; + }; + }; + /* + * (F) CPU5 + */ + port@5 { + reg = <5>; + rsnd_f_ep: endpoint { + remote-endpoint = <&fe_f_ep>; + bitclock-master; + frame-master; + playback = <&ssiu33 &ssi3>; + }; + }; + /* + * (G) CPU6 + */ + rsnd_g: port@6 { + reg = <6>; + rsnd_g_ep: endpoint { + remote-endpoint = <&pcm3168a_z_ep>; + bitclock-master; + frame-master; + capture = <&ssi4>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf-audio-graph-card2.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf-audio-graph-card2.dtsi new file mode 100644 index 000000000000..c30e056538e4 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/ulcb-kf-audio-graph-card2.dtsi @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree for ULCB + Kingfisher + Audio Graph Card2 + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +/* + * (A) CPU0 <----> ak4613 + * (B) CPU1 ----> HDMI + * (C) CPU2 ----> PCM3168A-p (8ch) + * (D) CPU3 <---- PCM3168A-c (6ch) + * + * (A) aplay -D plughw:0,0 xxx.wav + * (B) aplay -D plughw:0,1 xxx.wav + * (C) aplay -D plughw:0,2 xxx.wav + * + * (A) arecord -D plughw:0,0 xxx.wav + * (D) arecord -D plughw:0,3 xxx.wav + */ +#include "ulcb-kf-audio-graph-card.dtsi" + +&sound_card { + /delete-property/ dais; + links = <&rsnd_port0 /* (A) CPU0 <-> ak4613 */ + &rsnd_port1 /* (B) CPU1 -> HDMI */ + &rsnd_port2 /* (C) CPU2 -> PCM3168A-p */ + &rsnd_port3 /* (D) CPU3 <- PCM3168A-c */ + >; +}; diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf-simple-audio-card-mix+split.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf-simple-audio-card-mix+split.dtsi new file mode 100644 index 000000000000..bc221f994473 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/ulcb-kf-simple-audio-card-mix+split.dtsi @@ -0,0 +1,153 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree for ULCB + Kingfisher + Simple Audio Card (MIX + TDM Split) + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +/* + * Note: + * The HDMI output is ignored due to the limited number of subdevices + * + * (A) CPU0 (2ch) <----> (2ch) (X) ak4613 (MIX-0) + * (B) CPU1 (2ch) --/ (MIX-1) + * (C) CPU3 (2ch) ----> (8ch) (Y) PCM3168A-p (TDM-0 : 0,1ch) + * (D) CPU2 (2ch) --/ (TDM-1 : 2,3ch) + * (E) CPU4 (2ch) --/ (TDM-2 : 4,5ch) + * (F) CPU5 (2ch) --/ (TDM-3 : 6,7ch) + * (G) CPU6 (6ch) <---- (6ch) (Z) PCM3168A-c + * + * (A) aplay -D plughw:0,0 xxx.wav (MIX-0) + * (B) aplay -D plughw:0,1 xxx.wav (MIX-1) + * (C) aplay -D plughw:0,2 xxx.wav (TDM-0) + * (D) aplay -D plughw:0,3 xxx.wav (TDM-1) + * (E) aplay -D plughw:0,4 xxx.wav (TDM-2) + * (F) aplay -D plughw:0,5 xxx.wav (TDM-3) + * + * (A) arecord -D plughw:0,0 xxx.wav + * (G) arecord -D plughw:0,6 xxx.wav + */ + +&sound_card { + + simple-audio-card,routing = "ak4613 Playback", "DAI0 Playback", + "ak4613 Playback", "DAI1 Playback", + "DAI0 Capture", "ak4613 Capture", + "pcm3168a Playback", "DAI2 Playback", + "pcm3168a Playback", "DAI3 Playback", + "pcm3168a Playback", "DAI4 Playback", + "pcm3168a Playback", "DAI5 Playback"; + + /* dai-link@0 is defined in ulcb.dtsi */ + + simple-audio-card,dai-link@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + convert-channels = <8>; /* to 8ch TDM */ + + /* + * (C) CPU2 + */ + cpu@0 { + reg = <0>; + bitclock-master; + frame-master; + sound-dai = <&rcar_sound 2>; + }; + /* + * (D) CPU3 + */ + cpu@1 { + reg = <1>; + sound-dai = <&rcar_sound 3>; + }; + /* + * (E) CPU4 + */ + cpu@2 { + reg = <2>; + sound-dai = <&rcar_sound 4>; + }; + /* + * (F) CPU5 + */ + cpu@3 { + reg = <3>; + sound-dai = <&rcar_sound 5>; + }; + /* + * (Y) PCM3168A-p + */ + codec { + prefix = "pcm3168a"; + mclk-fs = <512>; + sound-dai = <&pcm3168a 0>; + }; + }; + simple-audio-card,dai-link@2 { + reg = <2>; + /* + * (G) CPU6 + */ + cpu { + bitclock-master; + frame-master; + sound-dai = <&rcar_sound 6>; + }; + /* + * (Z) PCM3168A-c + */ + codec { + prefix = "pcm3168a"; + mclk-fs = <512>; + sound-dai = <&pcm3168a 1>; + }; + }; +}; + +&pcm3168a { + /* + * (Y) PCM3168A-p + * (Z) PCM3168A-c + */ + #sound-dai-cells = <1>; +}; + +&rcar_sound { + rcar_sound,dai { + + /* dai0-1 are defined in ulcb.dtsi */ + + /* + * (C) CPU2 + */ + dai2 { + playback = <&ssiu30 &ssi3>; + }; + /* + * (D) CPU3 + */ + dai3 { + playback = <&ssiu31 &ssi3>; + }; + /* + * (E) CPU4 + */ + dai4 { + playback = <&ssiu32 &ssi3>; + }; + /* + * (F) CPU5 + */ + dai5 { + playback = <&ssiu33 &ssi3>; + }; + /* + * (G) CPU6 + */ + dai6 { + capture = <&ssi4>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf-simple-audio-card.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf-simple-audio-card.dtsi new file mode 100644 index 000000000000..2010e8ac7fdc --- /dev/null +++ b/arch/arm64/boot/dts/renesas/ulcb-kf-simple-audio-card.dtsi @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree for ULCB + Kingfisher + Simple Audio Card + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +/* + * (A) CPU0 <----> ak4613 + * (B) CPU1 ----> HDMI + * (C) CPU2 ----> PCM3168A-p + * (D) CPU3 <---- PCM3168A-c + * + * (A) aplay -D plughw:0,0 xxx.wav + * (B) aplay -D plughw:0,1 xxx.wav + * (C) aplay -D plughw:0,2 xxx.wav + * + * (A) arecord -D plughw:0,0 xxx.wav + * (D) arecord -D plughw:0,3 xxx.wav + */ + +&sound_card { + /* dai-link@0/1 are defined in ulcb.dtsi */ + + /* + * (C) CPU2 -> PCM3168A-p + */ + simple-audio-card,dai-link@2 { + reg = <2>; + cpu { + bitclock-master; + frame-master; + dai-tdm-slot-num = <8>; + sound-dai = <&rcar_sound 2>; + }; + codec { + mclk-fs = <512>; + sound-dai = <&pcm3168a 0>; + }; + }; + /* + * (D) CPU3 <- PCM3168A-c + */ + simple-audio-card,dai-link@3 { + reg = <3>; + cpu { + bitclock-master; + frame-master; + dai-tdm-slot-num = <6>; + sound-dai = <&rcar_sound 3>; + }; + codec { + mclk-fs = <512>; + sound-dai = <&pcm3168a 1>; + }; + }; +}; + +&pcm3168a { + /* + * (C) CPU2 -> PCM3168A-p + * (D) CPU3 <- PCM3168A-c + */ + #sound-dai-cells = <1>; +}; + +&rcar_sound { + + rcar_sound,dai { + /* dai0-1 are defined in ulcb.dtsi */ + + /* + * (C) CPU2 -> PCM3168A-p + */ + dai2 { + playback = <&ssi3>; + }; + /* + * (D) CPU3 <- PCM3168A-c + */ + dai3 { + capture = <&ssi4>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi index 408871c2859d..efc80960380f 100644 --- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi @@ -6,12 +6,6 @@ * Copyright (C) 2017 Cogent Embedded, Inc. */ -/* - * SSI-PCM3168A - * aplay -D plughw:0,2 xxx.wav - * arecord -D plughw:0,3 xxx.wav - */ - / { aliases { serial1 = &hscif0; @@ -126,7 +120,7 @@ }; &i2c2 { - i2cswitch2: i2c-switch@71 { + i2cmux2: i2c-mux@71 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -212,26 +206,6 @@ VCCAD2-supply = <&snd_vcc5v>; VCCDA1-supply = <&snd_vcc5v>; VCCDA2-supply = <&snd_vcc5v>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - mclk-fs = <512>; - port@0 { - reg = <0>; - pcm3168a_endpoint_p: endpoint { - remote-endpoint = <&rsnd_for_pcm3168a_play>; - clocks = <&clksndsel>; - }; - }; - port@1 { - reg = <1>; - pcm3168a_endpoint_c: endpoint { - remote-endpoint = <&rsnd_for_pcm3168a_capture>; - clocks = <&clksndsel>; - }; - }; - }; }; gyroscope@6b { @@ -317,7 +291,7 @@ }; &i2c4 { - i2cswitch4: i2c-switch@71 { + i2cmux4: i2c-mux@71 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -418,30 +392,6 @@ pinctrl-0 = <&sound_pins &sound_clk_pins &sound_pcm_pins>; - - ports { - /* rsnd_port0/1 are defined in ulcb.dtsi */ - rsnd_port2: port@2 { - reg = <2>; - rsnd_for_pcm3168a_play: endpoint { - remote-endpoint = <&pcm3168a_endpoint_p>; - bitclock-master; - frame-master; - dai-tdm-slot-num = <8>; - playback = <&ssi3>; - }; - }; - rsnd_port3: port@3 { - reg = <3>; - rsnd_for_pcm3168a_capture: endpoint { - remote-endpoint = <&pcm3168a_endpoint_c>; - bitclock-master; - frame-master; - dai-tdm-slot-num = <6>; - capture = <&ssi4>; - }; - }; - }; }; &scif1 { @@ -476,14 +426,6 @@ }; }; -&sound_card { - links = <&rsnd_port0 /* ak4613 */ - &rsnd_port1 /* HDMI0 */ - &rsnd_port2 /* pcm3168a playback */ - &rsnd_port3 /* pcm3168a capture */ - >; -}; - &ssi4 { shared-pin; }; @@ -498,3 +440,17 @@ &xhci0 { status = "okay"; }; + +/* + * For sound-test. + * + * We can switch Audio Card for testing + * see also ulcb.dtsi + * + * #include "ulcb-kf-simple-audio-card.dtsi" + * #include "ulcb-kf-simple-audio-card-mix+split.dtsi" + * #include "ulcb-kf-audio-graph-card.dtsi" + * #include "ulcb-kf-audio-graph-card-mix+split.dtsi" + * #include "ulcb-kf-audio-graph-card2-mix+split.dtsi" + */ +#include "ulcb-kf-audio-graph-card2.dtsi" diff --git a/arch/arm64/boot/dts/renesas/ulcb-simple-audio-card-mix+split.dtsi b/arch/arm64/boot/dts/renesas/ulcb-simple-audio-card-mix+split.dtsi new file mode 100644 index 000000000000..217d89019845 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/ulcb-simple-audio-card-mix+split.dtsi @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree for ULCB + Simple Audio Card (MIXer) + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +/* + * Note: + * The HDMI output is ignored due to the limited number of subdevices + * + * (A) CPU0 (2ch) <----> (2ch) (X) ak4613 (MIX-0) + * (B) CPU1 (2ch) --/ (MIX-1) + * + * (A) aplay -D plughw:0,0 xxx.wav + * (B) aplay -D plughw:0,1 xxx.wav + * + * (A) arecord -D plughw:0,0 xxx.wav + */ + +/ { + sound_card: sound { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "simple-scu-audio-card"; + label = "rcar-sound"; + + simple-audio-card,prefix = "ak4613"; + simple-audio-card,routing = "ak4613 Playback", "DAI0 Playback", + "ak4613 Playback", "DAI1 Playback", + "DAI0 Capture", "ak4613 Capture"; + + simple-audio-card,dai-link@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + convert-rate = <48000>; + + /* + * (A) CPU0 + */ + cpu@0 { + reg = <0>; + bitclock-master; + frame-master; + sound-dai = <&rcar_sound 0>; + }; + /* + * (B) CPU1 + */ + cpu@1 { + reg = <1>; + sound-dai = <&rcar_sound 1>; + }; + /* + * (X) ak4613 + */ + codec { + prefix = "ak4613"; + sound-dai = <&ak4613>; + }; + }; + }; +}; + +&ak4613 { + /* + * (X) ak4613 + */ + #sound-dai-cells = <0>; +}; + +&rcar_sound { + #sound-dai-cells = <1>; + + rcar_sound,dai { + /* + * (A) CPU0 + */ + dai0 { + playback = <&src1 &ctu02 &mix0 &dvc0 &ssi0>; + capture = <&ssi1 &src0 &dvc1>; + }; + /* + * (B) CPU1 + */ + dai1 { + playback = <&src2 &ctu03 &mix0 &dvc0 &ssi0>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/ulcb-simple-audio-card.dtsi b/arch/arm64/boot/dts/renesas/ulcb-simple-audio-card.dtsi new file mode 100644 index 000000000000..751cfd8c5257 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/ulcb-simple-audio-card.dtsi @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree for ULCB + Simple Audio Card + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +/* + * (A) CPU0 <----> ak4613 + * (B) CPU1 ----> HDMI + * + * (A) aplay -D plughw:0,0 xxx.wav + * (B) aplay -D plughw:0,1 xxx.wav + * + * (A) arecord -D plughw:0,0 xxx.wav + */ + +/ { + sound_card: sound { + compatible = "simple-audio-card"; + label = "rcar-sound"; + + #address-cells = <1>; + #size-cells = <0>; + + /* + * (A) CPU0 <-> ak4613 + */ + simple-audio-card,dai-link@0 { + reg = <0>; + cpu { + bitclock-master; + frame-master; + sound-dai = <&rcar_sound 0>; + }; + codec { + sound-dai = <&ak4613>; + }; + }; + /* + * (B) CPU1 -> HDMI + */ + simple-audio-card,dai-link@1 { + reg = <1>; + cpu { + bitclock-master; + frame-master; + sound-dai = <&rcar_sound 1>; + }; + codec { + sound-dai = <&hdmi0>; + }; + }; + }; +}; + +&ak4613 { + /* + * (A) CPU0 <-> ak4613 + */ + #sound-dai-cells = <0>; +}; + +&hdmi0 { + /* + * (B) CPU1 -> HDMI + */ + #sound-dai-cells = <0>; +}; + +&rcar_sound { + #sound-dai-cells = <1>; + + rcar_sound,dai { + /* + * (A) CPU0 <-> ak4613 + */ + dai0 { + playback = <&ssi0 &src0 &dvc0>; + capture = <&ssi1 &src1 &dvc1>; + }; + /* + * (B) CPU1 -> HDMI + */ + dai1 { + playback = <&ssi2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi index 29cedf4dc1a9..d693e879b330 100644 --- a/arch/arm64/boot/dts/renesas/ulcb.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi @@ -6,14 +6,6 @@ * Copyright (C) 2016 Cogent Embedded, Inc. */ -/* - * SSI-AK4613 - * aplay -D plughw:0,0 xxx.wav - * arecord -D plughw:0,0 xxx.wav - * SSI-HDMI - * aplay -D plughw:0,1 xxx.wav - */ - #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> @@ -102,15 +94,6 @@ regulator-always-on; }; - sound_card: sound { - compatible = "audio-graph-card2"; - label = "rcar-sound"; - - links = <&rsnd_port0 /* ak4613 */ - &rsnd_port1 /* HDMI0 */ - >; - }; - vcc_sdhi0: regulator-vcc-sdhi0 { compatible = "regulator-fixed"; @@ -201,9 +184,6 @@ }; port@2 { reg = <2>; - dw_hdmi0_snd_in: endpoint { - remote-endpoint = <&rsnd_for_hdmi>; - }; }; }; }; @@ -218,7 +198,6 @@ ak4613: codec@10 { compatible = "asahi-kasei,ak4613"; - #sound-dai-cells = <0>; reg = <0x10>; clocks = <&rcar_sound 3>; @@ -230,12 +209,6 @@ asahi-kasei,out4-single-end; asahi-kasei,out5-single-end; asahi-kasei,out6-single-end; - - port { - ak4613_endpoint: endpoint { - remote-endpoint = <&rsnd_for_ak4613>; - }; - }; }; cs2000: clk-multiplier@4f { @@ -381,9 +354,6 @@ pinctrl-0 = <&sound_pins>, <&sound_clk_pins>; pinctrl-names = "default"; - /* Single DAI */ - #sound-dai-cells = <0>; - /* audio_clkout0/1/2/3 */ #clock-cells = <1>; clock-frequency = <12288000 11289600>; @@ -408,30 +378,6 @@ <&audio_clk_a>, <&cs2000>, <&audio_clk_c>, <&cpg CPG_CORE CPG_AUDIO_CLK_I>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - rsnd_port0: port@0 { - reg = <0>; - rsnd_for_ak4613: endpoint { - remote-endpoint = <&ak4613_endpoint>; - bitclock-master; - frame-master; - playback = <&ssi0>, <&src0>, <&dvc0>; - capture = <&ssi1>, <&src1>, <&dvc1>; - }; - }; - rsnd_port1: port@1 { - reg = <1>; - rsnd_for_hdmi: endpoint { - remote-endpoint = <&dw_hdmi0_snd_in>; - bitclock-master; - frame-master; - playback = <&ssi2>; - }; - }; - }; }; &rpc { @@ -541,3 +487,17 @@ status = "okay"; }; + + +/* + * For sound-test. + * + * We can switch Audio Card for testing + * + * #include "ulcb-simple-audio-card.dtsi" + * #include "ulcb-simple-audio-card-mix+split.dtsi" + * #include "ulcb-audio-graph-card.dtsi" + * #include "ulcb-audio-graph-card-mix+split.dtsi" + * #include "ulcb-audio-graph-card2-mix+split.dtsi" + */ +#include "ulcb-audio-graph-card2.dtsi" diff --git a/arch/arm64/boot/dts/tesla/fsd-evb.dts b/arch/arm64/boot/dts/tesla/fsd-evb.dts index 1db6ddf03f01..8d7794642900 100644 --- a/arch/arm64/boot/dts/tesla/fsd-evb.dts +++ b/arch/arm64/boot/dts/tesla/fsd-evb.dts @@ -10,6 +10,7 @@ /dts-v1/; #include "fsd.dtsi" +#include <dt-bindings/gpio/gpio.h> / { model = "Tesla Full Self-Driving (FSD) Evaluation board"; @@ -28,12 +29,80 @@ device_type = "memory"; reg = <0x0 0x80000000 0x2 0x00000000>; }; + + sound { + compatible = "simple-audio-card"; + + #address-cells = <1>; + #size-cells = <0>; + + simple-audio-card,name = "FSD Audio Card"; + simple-audio-card,widgets = "Line", "Line Out", + "Line", "Line In"; + simple-audio-card,routing = "Line Out", "LLOUT", + "Line Out", "RLOUT", + "MIC2L", "Line In", + "MIC2R", "Line In"; + + simple-audio-card,dai-link@0 { + reg = <0>; + format = "i2s"; + bitclock-master = <&tlv320aic3x>; + frame-master = <&tlv320aic3x>; + + cpu-0 { + sound-dai = <&i2s_0 0>; + }; + cpu-1 { + sound-dai = <&i2s_0 1>; + }; + codec { + sound-dai = <&tlv320aic3x>; + system-clock-frequency = <33000000>; + }; + }; + }; }; &fin_pll { clock-frequency = <24000000>; }; +&hsi2c_5 { + status = "okay"; + + tlv320aic3x: codec@18 { + compatible = "ti,tlv320aic3104"; + reg = <0x18>; + #sound-dai-cells = <0>; + reset-gpios = <&gpg1 6 GPIO_ACTIVE_LOW>; + }; +}; + +&i2s_0 { + status = "okay"; +}; + +&i2s_1 { + status = "okay"; +}; + +&m_can0 { + status = "okay"; +}; + +&m_can1 { + status = "okay"; +}; + +&m_can2 { + status = "okay"; +}; + +&m_can3 { + status = "okay"; +}; + &serial_0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi index e3852c946352..3f898cf4874c 100644 --- a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi +++ b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi @@ -54,14 +54,14 @@ ufs_rst_n: ufs-rst-n-pins { samsung,pins = "gpf5-0"; samsung,pin-function = <FSD_PIN_FUNC_2>; - samsung,pin-pud = <FSD_PIN_PULL_NONE>; + samsung,pin-pud = <FSD_PIN_PULL_DOWN>; samsung,pin-drv = <FSD_PIN_DRV_LV4>; }; ufs_refclk_out: ufs-refclk-out-pins { samsung,pins = "gpf5-1"; samsung,pin-function = <FSD_PIN_FUNC_2>; - samsung,pin-pud = <FSD_PIN_PULL_NONE>; + samsung,pin-pud = <FSD_PIN_PULL_UP>; samsung,pin-drv = <FSD_PIN_DRV_LV4>; }; }; @@ -308,37 +308,79 @@ uart0_data: uart0-data-pins { samsung,pins = "gpb7-0", "gpb7-1"; samsung,pin-function = <FSD_PIN_FUNC_2>; - samsung,pin-pud = <FSD_PIN_PULL_NONE>; + samsung,pin-pud = <FSD_PIN_PULL_UP>; samsung,pin-drv = <FSD_PIN_DRV_LV4>; }; uart1_data: uart1-data-pins { samsung,pins = "gpb7-4", "gpb7-5"; samsung,pin-function = <FSD_PIN_FUNC_2>; - samsung,pin-pud = <FSD_PIN_PULL_NONE>; + samsung,pin-pud = <FSD_PIN_PULL_UP>; samsung,pin-drv = <FSD_PIN_DRV_LV4>; }; spi0_bus: spi0-bus-pins { samsung,pins = "gpb4-0", "gpb4-2", "gpb4-3"; samsung,pin-function = <FSD_PIN_FUNC_2>; - samsung,pin-pud = <FSD_PIN_PULL_UP>; + samsung,pin-pud = <FSD_PIN_PULL_DOWN>; samsung,pin-drv = <FSD_PIN_DRV_LV4>; }; spi1_bus: spi1-bus-pins { samsung,pins = "gpb4-4", "gpb4-6", "gpb4-7"; samsung,pin-function = <FSD_PIN_FUNC_2>; - samsung,pin-pud = <FSD_PIN_PULL_UP>; + samsung,pin-pud = <FSD_PIN_PULL_DOWN>; samsung,pin-drv = <FSD_PIN_DRV_LV4>; }; spi2_bus: spi2-bus-pins { samsung,pins = "gpb5-0", "gpb5-2", "gpb5-3"; samsung,pin-function = <FSD_PIN_FUNC_2>; + samsung,pin-pud = <FSD_PIN_PULL_DOWN>; + samsung,pin-drv = <FSD_PIN_DRV_LV4>; + }; + + m_can0_bus: m-can0-bus-pins { + samsung,pins = "gpd0-0", "gpd0-1"; + samsung,pin-function = <FSD_PIN_FUNC_2>; + samsung,pin-pud = <FSD_PIN_PULL_UP>; + samsung,pin-drv = <FSD_PIN_DRV_LV4>; + }; + + m_can1_bus: m-can1-bus-pins { + samsung,pins = "gpd0-2", "gpd0-3"; + samsung,pin-function = <FSD_PIN_FUNC_2>; + samsung,pin-pud = <FSD_PIN_PULL_UP>; + samsung,pin-drv = <FSD_PIN_DRV_LV4>; + }; + + m_can2_bus: m-can2-bus-pins { + samsung,pins = "gpd0-4", "gpd0-5"; + samsung,pin-function = <FSD_PIN_FUNC_2>; + samsung,pin-pud = <FSD_PIN_PULL_UP>; + samsung,pin-drv = <FSD_PIN_DRV_LV4>; + }; + + m_can3_bus: m-can3-bus-pins { + samsung,pins = "gpd0-6", "gpd0-7"; + samsung,pin-function = <FSD_PIN_FUNC_2>; samsung,pin-pud = <FSD_PIN_PULL_UP>; samsung,pin-drv = <FSD_PIN_DRV_LV4>; }; + + i2s0_bus: i2s0-bus-pins { + samsung,pins = "gpd1-0", "gpd1-1", "gpd1-2", "gpd1-3", "gpd1-4"; + samsung,pin-function = <FSD_PIN_FUNC_2>; + samsung,pin-pud = <FSD_PIN_PULL_DOWN>; + samsung,pin-drv = <FSD_PIN_DRV_LV4>; + }; + + i2s1_bus: i2s1-bus-pins { + samsung,pins = "gpd2-0", "gpd2-1", "gpd2-2", "gpd2-3", "gpd2-4"; + samsung,pin-function = <FSD_PIN_FUNC_2>; + samsung,pin-pud = <FSD_PIN_PULL_DOWN>; + samsung,pin-drv = <FSD_PIN_DRV_LV4>; + }; }; &pinctrl_pmu { diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi index f35bc5a288c2..1c53c68efd53 100644 --- a/arch/arm64/boot/dts/tesla/fsd.dtsi +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi @@ -281,6 +281,8 @@ cpucl_l2: l2-cache0 { compatible = "cache"; + cache-level = <2>; + cache-unified; cache-size = <0x400000>; cache-line-size = <64>; cache-sets = <4096>; @@ -466,6 +468,11 @@ clock-names = "fin_pll"; }; + sysreg_cam: system-controller@12630000 { + compatible = "tesla,fsd-cam-sysreg", "syscon"; + reg = <0x0 0x12630000 0x0 0x500>; + }; + clock_mfc: clock-controller@12810000 { compatible = "tesla,fsd-clock-mfc"; reg = <0x0 0x12810000 0x0 0x3000>; @@ -492,6 +499,11 @@ "dout_cmu_peric_shared1div4_dmaclk"; }; + sysreg_peric: system-controller@14030000 { + compatible = "tesla,fsd-peric-sysreg", "syscon"; + reg = <0x0 0x14030000 0x0 0x1000>; + }; + clock_fsys0: clock-controller@15010000 { compatible = "tesla,fsd-clock-fsys0"; reg = <0x0 0x15010000 0x0 0x3000>; @@ -506,6 +518,11 @@ "dout_cmu_fsys0_shared0div4"; }; + sysreg_fsys0: system-controller@15030000 { + compatible = "tesla,fsd-fsys0-sysreg", "syscon"; + reg = <0x0 0x15030000 0x0 0x1000>; + }; + clock_fsys1: clock-controller@16810000 { compatible = "tesla,fsd-clock-fsys1"; reg = <0x0 0x16810000 0x0 0x3000>; @@ -518,6 +535,11 @@ "dout_cmu_fsys1_shared0div4"; }; + sysreg_fsys1: system-controller@16830000 { + compatible = "tesla,fsd-fsys1-sysreg", "syscon"; + reg = <0x0 0x16830000 0x0 0x1000>; + }; + mdma0: dma-controller@10100000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0x10100000 0x0 0x1000>; @@ -738,6 +760,40 @@ status = "disabled"; }; + i2s_0: i2s@140e0000 { + compatible = "tesla,fsd-i2s"; + reg = <0x0 0x140e0000 0x0 0x100>; + interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&pdma1 14>, <&pdma1 13>, <&pdma1 12>; + dma-names = "tx", "rx", "tx-sec"; + #clock-cells = <1>; + clocks = <&clock_peric PERIC_PCLK_TDM0>, + <&clock_peric PERIC_HCLK_TDM0>, + <&clock_peric PERIC_HCLK_TDM0>; + clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_bus>; + #sound-dai-cells = <1>; + status = "disabled"; + }; + + i2s_1: i2s@140f0000 { + compatible = "tesla,fsd-i2s"; + reg = <0x0 0x140f0000 0x0 0x100>; + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&pdma1 17>, <&pdma1 16>, <&pdma1 15>; + dma-names = "tx", "rx", "tx-sec"; + #clock-cells = <1>; + clocks = <&clock_peric PERIC_PCLK_TDM1>, + <&clock_peric PERIC_HCLK_TDM1>, + <&clock_peric PERIC_HCLK_TDM1>; + clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_bus>; + #sound-dai-cells = <1>; + status = "disabled"; + }; + pinctrl_pmu: pinctrl@114f0000 { compatible = "tesla,fsd-pinctrl"; reg = <0x0 0x114f0000 0x0 0x1000>; @@ -755,6 +811,74 @@ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; }; + m_can0: can@14088000 { + compatible = "bosch,m_can"; + reg = <0x0 0x14088000 0x0 0x0200>, + <0x0 0x14080000 0x0 0x8000>; + reg-names = "m_can", "message_ram"; + interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + pinctrl-names = "default"; + pinctrl-0 = <&m_can0_bus>; + clocks = <&clock_peric PERIC_MCAN0_IPCLKPORT_PCLK>, + <&clock_peric PERIC_MCAN0_IPCLKPORT_CCLK>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + m_can1: can@14098000 { + compatible = "bosch,m_can"; + reg = <0x0 0x14098000 0x0 0x0200>, + <0x0 0x14090000 0x0 0x8000>; + reg-names = "m_can", "message_ram"; + interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + pinctrl-names = "default"; + pinctrl-0 = <&m_can1_bus>; + clocks = <&clock_peric PERIC_MCAN1_IPCLKPORT_PCLK>, + <&clock_peric PERIC_MCAN1_IPCLKPORT_CCLK>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + m_can2: can@140a8000 { + compatible = "bosch,m_can"; + reg = <0x0 0x140a8000 0x0 0x0200>, + <0x0 0x140a0000 0x0 0x8000>; + reg-names = "m_can", "message_ram"; + interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + pinctrl-names = "default"; + pinctrl-0 = <&m_can2_bus>; + clocks = <&clock_peric PERIC_MCAN2_IPCLKPORT_PCLK>, + <&clock_peric PERIC_MCAN2_IPCLKPORT_CCLK>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + m_can3: can@140b8000 { + compatible = "bosch,m_can"; + reg = <0x0 0x140b8000 0x0 0x0200>, + <0x0 0x140b0000 0x0 0x8000>; + reg-names = "m_can", "message_ram"; + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + pinctrl-names = "default"; + pinctrl-0 = <&m_can3_bus>; + clocks = <&clock_peric PERIC_MCAN3_IPCLKPORT_PCLK>, + <&clock_peric PERIC_MCAN3_IPCLKPORT_CCLK>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + spi_0: spi@14140000 { compatible = "tesla,fsd-spi"; reg = <0x0 0x14140000 0x0 0x100>; diff --git a/arch/arm64/crypto/sm4-ce-ccm-core.S b/arch/arm64/crypto/sm4-ce-ccm-core.S index 028207c4afd0..fa85856f33ce 100644 --- a/arch/arm64/crypto/sm4-ce-ccm-core.S +++ b/arch/arm64/crypto/sm4-ce-ccm-core.S @@ -8,6 +8,7 @@ */ #include <linux/linkage.h> +#include <linux/cfi_types.h> #include <asm/assembler.h> #include "sm4-ce-asm.h" @@ -104,7 +105,7 @@ SYM_FUNC_START(sm4_ce_ccm_final) SYM_FUNC_END(sm4_ce_ccm_final) .align 3 -SYM_FUNC_START(sm4_ce_ccm_enc) +SYM_TYPED_FUNC_START(sm4_ce_ccm_enc) /* input: * x0: round key array, CTX * x1: dst @@ -216,7 +217,7 @@ SYM_FUNC_START(sm4_ce_ccm_enc) SYM_FUNC_END(sm4_ce_ccm_enc) .align 3 -SYM_FUNC_START(sm4_ce_ccm_dec) +SYM_TYPED_FUNC_START(sm4_ce_ccm_dec) /* input: * x0: round key array, CTX * x1: dst diff --git a/arch/arm64/crypto/sm4-ce-gcm-core.S b/arch/arm64/crypto/sm4-ce-gcm-core.S index 7aa3ec18a289..347f25d75727 100644 --- a/arch/arm64/crypto/sm4-ce-gcm-core.S +++ b/arch/arm64/crypto/sm4-ce-gcm-core.S @@ -9,6 +9,7 @@ */ #include <linux/linkage.h> +#include <linux/cfi_types.h> #include <asm/assembler.h> #include "sm4-ce-asm.h" @@ -370,7 +371,7 @@ SYM_FUNC_START(pmull_ghash_update) SYM_FUNC_END(pmull_ghash_update) .align 3 -SYM_FUNC_START(sm4_ce_pmull_gcm_enc) +SYM_TYPED_FUNC_START(sm4_ce_pmull_gcm_enc) /* input: * x0: round key array, CTX * x1: dst @@ -581,7 +582,7 @@ SYM_FUNC_END(sm4_ce_pmull_gcm_enc) #define RH3 v20 .align 3 -SYM_FUNC_START(sm4_ce_pmull_gcm_dec) +SYM_TYPED_FUNC_START(sm4_ce_pmull_gcm_dec) /* input: * x0: round key array, CTX * x1: dst diff --git a/arch/mips/ralink/of.c b/arch/mips/ralink/of.c index 01c132bc33d5..4d06de77d92a 100644 --- a/arch/mips/ralink/of.c +++ b/arch/mips/ralink/of.c @@ -64,7 +64,7 @@ void __init plat_mem_setup(void) dtb = get_fdt(); __dt_setup_arch(dtb); - if (!early_init_dt_scan_memory()) + if (early_init_dt_scan_memory()) return; if (soc_info.mem_detect) diff --git a/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi b/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi index 74e17e134387..27714dc2f04a 100644 --- a/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi @@ -659,3 +659,19 @@ interrupts = <16 2 1 9>; }; }; + +&fman0_rx_0x08 { + /delete-property/ fsl,fman-10g-port; +}; + +&fman0_tx_0x28 { + /delete-property/ fsl,fman-10g-port; +}; + +&fman0_rx_0x09 { + /delete-property/ fsl,fman-10g-port; +}; + +&fman0_tx_0x29 { + /delete-property/ fsl,fman-10g-port; +}; diff --git a/arch/powerpc/kernel/vmlinux.lds.S b/arch/powerpc/kernel/vmlinux.lds.S index 8c3862b4c259..958e77a24f85 100644 --- a/arch/powerpc/kernel/vmlinux.lds.S +++ b/arch/powerpc/kernel/vmlinux.lds.S @@ -8,6 +8,7 @@ #define BSS_FIRST_SECTIONS *(.bss.prominit) #define EMITS_PT_NOTE #define RO_EXCEPTION_TABLE_ALIGN 0 +#define RUNTIME_DISCARD_EXIT #define SOFT_MASK_TABLE(align) \ . = ALIGN(align); \ @@ -410,9 +411,12 @@ SECTIONS DISCARDS /DISCARD/ : { *(*.EMB.apuinfo) - *(.glink .iplt .plt .rela* .comment) + *(.glink .iplt .plt) *(.gnu.version*) *(.gnu.attributes) *(.eh_frame) +#ifndef CONFIG_RELOCATABLE + *(.rela*) +#endif } } diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile index 259c3c802cab..45adc4926e79 100644 --- a/arch/riscv/boot/dts/microchip/Makefile +++ b/arch/riscv/boot/dts/microchip/Makefile @@ -3,4 +3,5 @@ dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-m100pfsevp.dtb dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-sev-kit.dtb +dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-tysom-m.dtb obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) diff --git a/arch/riscv/boot/dts/microchip/mpfs-tysom-m-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-tysom-m-fabric.dtsi new file mode 100644 index 000000000000..98f642e83ad4 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-tysom-m-fabric.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2022 Microchip Technology Inc */ + +// #include "dt-bindings/mailbox/miv-ihc.h" + +/ { + fabric_clk3: fabric-clk3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <62500000>; + }; + + fabric_clk1: fabric-clk1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; +}; diff --git a/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts b/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts new file mode 100644 index 000000000000..e0797c7e1b35 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Original all-in-one devicetree: + * Copyright (C) 2020-2022 - Aldec + * Rewritten to use includes: + * Copyright (C) 2022 - Conor Dooley <conor.dooley@microchip.com> + */ + +/dts-v1/; + +#include "mpfs.dtsi" +#include "mpfs-tysom-m-fabric.dtsi" + +/* Clock frequency (in Hz) of the rtcclk */ +#define MTIMER_FREQ 1000000 + +/ { + model = "Aldec TySOM-M-MPFS250T-REV2"; + compatible = "aldec,tysom-m-mpfs250t-rev2", "microchip,mpfs"; + + aliases { + ethernet0 = &mac0; + ethernet1 = &mac1; + serial0 = &mmuart0; + serial1 = &mmuart1; + serial2 = &mmuart2; + serial3 = &mmuart3; + serial4 = &mmuart4; + gpio0 = &gpio0; + gpio1 = &gpio2; + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; + + cpus { + timebase-frequency = <MTIMER_FREQ>; + }; + + ddrc_cache_lo: memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x30000000>; + status = "okay"; + }; + + ddrc_cache_hi: memory@1000000000 { + device_type = "memory"; + reg = <0x10 0x00000000 0x0 0x40000000>; + status = "okay"; + }; + + leds { + compatible = "gpio-leds"; + status = "okay"; + + led0 { + gpios = <&gpio1 23 1>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + hwmon: hwmon@45 { + status = "okay"; + compatible = "ti,ina219"; + reg = <0x45>; + shunt-resistor = <2000>; + }; +}; + +&gpio1 { + interrupts = <27>, <28>, <29>, <30>, + <31>, <32>, <33>, <47>, + <35>, <36>, <37>, <38>, + <39>, <40>, <41>, <42>, + <43>, <44>, <45>, <46>, + <47>, <48>, <49>, <50>; + status = "okay"; +}; + +&mac0 { + status = "okay"; + phy-mode = "gmii"; + phy-handle = <&phy0>; + +}; + +&mac1 { + status = "okay"; + phy-mode = "gmii"; + phy-handle = <&phy1>; + phy1: ethernet-phy@1 { + reg = <1>; + }; + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&mbox { + status = "okay"; +}; + +&mmc { + max-frequency = <200000000>; + cap-mmc-highspeed; + cap-sd-highspeed; + no-1-8-v; + disable-wp; + status = "okay"; +}; + +&mmuart1 { + status = "okay"; +}; + +&mmuart2 { + status = "okay"; +}; + +&mmuart3 { + status = "okay"; +}; + +&mmuart4 { + status = "okay"; +}; + +&refclk { + clock-frequency = <125000000>; +}; + +&rtc { + status = "okay"; +}; + +&spi0 { + status = "okay"; +}; + +&spi1 { + status = "okay"; + flash@0 { + compatible = "micron,n25q128a11", "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <10000000>; + }; +}; + +&syscontroller { + status = "okay"; +}; + +&usb { + status = "okay"; + dr_mode = "host"; +}; diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi index 2b7672bc4b52..d6f18754eb5d 100644 --- a/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi +++ b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi @@ -24,24 +24,22 @@ ð0 { status = "disabled"; -}; -ð1 { - status = "disabled"; + phy0: ethernet-phy@7 { + /delete-property/ interrupt-parent; + /delete-property/ interrupts; + }; }; -&ostm1 { +ð1 { status = "disabled"; -}; -&ostm2 { - status = "disabled"; + phy1: ethernet-phy@7 { + /delete-property/ interrupt-parent; + /delete-property/ interrupts; + }; }; &sdhi0 { status = "disabled"; }; - -&wdt0 { - status = "disabled"; -}; diff --git a/arch/riscv/include/asm/uaccess.h b/arch/riscv/include/asm/uaccess.h index 855450bed9f5..ec0cab9fbddd 100644 --- a/arch/riscv/include/asm/uaccess.h +++ b/arch/riscv/include/asm/uaccess.h @@ -165,7 +165,7 @@ do { \ might_fault(); \ access_ok(__p, sizeof(*__p)) ? \ __get_user((x), __p) : \ - ((x) = 0, -EFAULT); \ + ((x) = (__force __typeof__(x))0, -EFAULT); \ }) #define __put_user_asm(insn, x, ptr, err) \ diff --git a/arch/riscv/kernel/probes/simulate-insn.h b/arch/riscv/kernel/probes/simulate-insn.h index cb6ff7dccb92..de8474146a9b 100644 --- a/arch/riscv/kernel/probes/simulate-insn.h +++ b/arch/riscv/kernel/probes/simulate-insn.h @@ -31,9 +31,9 @@ __RISCV_INSN_FUNCS(fence, 0x7f, 0x0f); } while (0) __RISCV_INSN_FUNCS(c_j, 0xe003, 0xa001); -__RISCV_INSN_FUNCS(c_jr, 0xf007, 0x8002); +__RISCV_INSN_FUNCS(c_jr, 0xf07f, 0x8002); __RISCV_INSN_FUNCS(c_jal, 0xe003, 0x2001); -__RISCV_INSN_FUNCS(c_jalr, 0xf007, 0x9002); +__RISCV_INSN_FUNCS(c_jalr, 0xf07f, 0x9002); __RISCV_INSN_FUNCS(c_beqz, 0xe003, 0xc001); __RISCV_INSN_FUNCS(c_bnez, 0xe003, 0xe001); __RISCV_INSN_FUNCS(c_ebreak, 0xffff, 0x9002); diff --git a/arch/x86/coco/tdx/tdx.c b/arch/x86/coco/tdx/tdx.c index cfd4c95b9f04..669d9e4f2901 100644 --- a/arch/x86/coco/tdx/tdx.c +++ b/arch/x86/coco/tdx/tdx.c @@ -386,8 +386,8 @@ static int handle_mmio(struct pt_regs *regs, struct ve_info *ve) { unsigned long *reg, val, vaddr; char buffer[MAX_INSN_SIZE]; + enum insn_mmio_type mmio; struct insn insn = {}; - enum mmio_type mmio; int size, extend_size; u8 extend_val = 0; @@ -402,10 +402,10 @@ static int handle_mmio(struct pt_regs *regs, struct ve_info *ve) return -EINVAL; mmio = insn_decode_mmio(&insn, &size); - if (WARN_ON_ONCE(mmio == MMIO_DECODE_FAILED)) + if (WARN_ON_ONCE(mmio == INSN_MMIO_DECODE_FAILED)) return -EINVAL; - if (mmio != MMIO_WRITE_IMM && mmio != MMIO_MOVS) { + if (mmio != INSN_MMIO_WRITE_IMM && mmio != INSN_MMIO_MOVS) { reg = insn_get_modrm_reg_ptr(&insn, regs); if (!reg) return -EINVAL; @@ -426,23 +426,23 @@ static int handle_mmio(struct pt_regs *regs, struct ve_info *ve) /* Handle writes first */ switch (mmio) { - case MMIO_WRITE: + case INSN_MMIO_WRITE: memcpy(&val, reg, size); if (!mmio_write(size, ve->gpa, val)) return -EIO; return insn.length; - case MMIO_WRITE_IMM: + case INSN_MMIO_WRITE_IMM: val = insn.immediate.value; if (!mmio_write(size, ve->gpa, val)) return -EIO; return insn.length; - case MMIO_READ: - case MMIO_READ_ZERO_EXTEND: - case MMIO_READ_SIGN_EXTEND: + case INSN_MMIO_READ: + case INSN_MMIO_READ_ZERO_EXTEND: + case INSN_MMIO_READ_SIGN_EXTEND: /* Reads are handled below */ break; - case MMIO_MOVS: - case MMIO_DECODE_FAILED: + case INSN_MMIO_MOVS: + case INSN_MMIO_DECODE_FAILED: /* * MMIO was accessed with an instruction that could not be * decoded or handled properly. It was likely not using io.h @@ -459,15 +459,15 @@ static int handle_mmio(struct pt_regs *regs, struct ve_info *ve) return -EIO; switch (mmio) { - case MMIO_READ: + case INSN_MMIO_READ: /* Zero-extend for 32-bit operation */ extend_size = size == 4 ? sizeof(*reg) : 0; break; - case MMIO_READ_ZERO_EXTEND: + case INSN_MMIO_READ_ZERO_EXTEND: /* Zero extend based on operand size */ extend_size = insn.opnd_bytes; break; - case MMIO_READ_SIGN_EXTEND: + case INSN_MMIO_READ_SIGN_EXTEND: /* Sign extend based on operand size */ extend_size = insn.opnd_bytes; if (size == 1 && val & BIT(7)) diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c index d6f3703e4119..4386b10682ce 100644 --- a/arch/x86/events/amd/core.c +++ b/arch/x86/events/amd/core.c @@ -1387,7 +1387,7 @@ static int __init amd_core_pmu_init(void) * numbered counter following it. */ for (i = 0; i < x86_pmu.num_counters - 1; i += 2) - even_ctr_mask |= 1 << i; + even_ctr_mask |= BIT_ULL(i); pair_constraint = (struct event_constraint) __EVENT_CONSTRAINT(0, even_ctr_mask, 0, diff --git a/arch/x86/events/rapl.c b/arch/x86/events/rapl.c index a829492bca4c..52e6e7ed4f78 100644 --- a/arch/x86/events/rapl.c +++ b/arch/x86/events/rapl.c @@ -800,13 +800,18 @@ static const struct x86_cpu_id rapl_model_match[] __initconst = { X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, &model_hsx), X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE_L, &model_skl), X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE, &model_skl), + X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L, &model_skl), + X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE, &model_skl), X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE, &model_skl), X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, &model_skl), X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_N, &model_skl), X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, &model_spr), + X86_MATCH_INTEL_FAM6_MODEL(EMERALDRAPIDS_X, &model_spr), X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE, &model_skl), X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P, &model_skl), X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_S, &model_skl), + X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE, &model_skl), + X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE_L, &model_skl), {}, }; MODULE_DEVICE_TABLE(x86cpu, rapl_model_match); diff --git a/arch/x86/include/asm/insn-eval.h b/arch/x86/include/asm/insn-eval.h index f07faa61c7f3..54368a43abf6 100644 --- a/arch/x86/include/asm/insn-eval.h +++ b/arch/x86/include/asm/insn-eval.h @@ -32,16 +32,16 @@ int insn_fetch_from_user_inatomic(struct pt_regs *regs, bool insn_decode_from_regs(struct insn *insn, struct pt_regs *regs, unsigned char buf[MAX_INSN_SIZE], int buf_size); -enum mmio_type { - MMIO_DECODE_FAILED, - MMIO_WRITE, - MMIO_WRITE_IMM, - MMIO_READ, - MMIO_READ_ZERO_EXTEND, - MMIO_READ_SIGN_EXTEND, - MMIO_MOVS, +enum insn_mmio_type { + INSN_MMIO_DECODE_FAILED, + INSN_MMIO_WRITE, + INSN_MMIO_WRITE_IMM, + INSN_MMIO_READ, + INSN_MMIO_READ_ZERO_EXTEND, + INSN_MMIO_READ_SIGN_EXTEND, + INSN_MMIO_MOVS, }; -enum mmio_type insn_decode_mmio(struct insn *insn, int *bytes); +enum insn_mmio_type insn_decode_mmio(struct insn *insn, int *bytes); #endif /* _ASM_X86_INSN_EVAL_H */ diff --git a/arch/x86/kernel/callthunks.c b/arch/x86/kernel/callthunks.c index 7d2c75ec9a8c..ffea98f9064b 100644 --- a/arch/x86/kernel/callthunks.c +++ b/arch/x86/kernel/callthunks.c @@ -119,7 +119,7 @@ static bool is_coretext(const struct core_text *ct, void *addr) return within_module_coretext(addr); } -static __init_or_module bool skip_addr(void *dest) +static bool skip_addr(void *dest) { if (dest == error_entry) return true; @@ -181,7 +181,7 @@ static const u8 nops[] = { 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, }; -static __init_or_module void *patch_dest(void *dest, bool direct) +static void *patch_dest(void *dest, bool direct) { unsigned int tsize = SKL_TMPL_SIZE; u8 *pad = dest - tsize; diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index d970ddb0cc65..bca0bd8f4846 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -1981,6 +1981,8 @@ static int ib_prctl_set(struct task_struct *task, unsigned long ctrl) if (ctrl == PR_SPEC_FORCE_DISABLE) task_set_spec_ib_force_disable(task); task_update_spec_tif(task); + if (task == current) + indirect_branch_prediction_barrier(); break; default: return -ERANGE; diff --git a/arch/x86/kernel/crash.c b/arch/x86/kernel/crash.c index 9730c88530fc..305514431f26 100644 --- a/arch/x86/kernel/crash.c +++ b/arch/x86/kernel/crash.c @@ -401,10 +401,8 @@ int crash_load_segments(struct kimage *image) kbuf.buf_align = ELF_CORE_HEADER_ALIGN; kbuf.mem = KEXEC_BUF_MEM_UNKNOWN; ret = kexec_add_buffer(&kbuf); - if (ret) { - vfree((void *)image->elf_headers); + if (ret) return ret; - } image->elf_load_addr = kbuf.mem; pr_debug("Loaded ELF headers at 0x%lx bufsz=0x%lx memsz=0x%lx\n", image->elf_load_addr, kbuf.bufsz, kbuf.memsz); diff --git a/arch/x86/kernel/kprobes/core.c b/arch/x86/kernel/kprobes/core.c index 66299682b6b7..b36f3c367cb2 100644 --- a/arch/x86/kernel/kprobes/core.c +++ b/arch/x86/kernel/kprobes/core.c @@ -37,6 +37,7 @@ #include <linux/extable.h> #include <linux/kdebug.h> #include <linux/kallsyms.h> +#include <linux/kgdb.h> #include <linux/ftrace.h> #include <linux/kasan.h> #include <linux/moduleloader.h> @@ -281,12 +282,15 @@ static int can_probe(unsigned long paddr) if (ret < 0) return 0; +#ifdef CONFIG_KGDB /* - * Another debugging subsystem might insert this breakpoint. - * In that case, we can't recover it. + * If there is a dynamically installed kgdb sw breakpoint, + * this function should not be probed. */ - if (insn.opcode.bytes[0] == INT3_INSN_OPCODE) + if (insn.opcode.bytes[0] == INT3_INSN_OPCODE && + kgdb_has_hit_break(addr)) return 0; +#endif addr += insn.length; } diff --git a/arch/x86/kernel/kprobes/opt.c b/arch/x86/kernel/kprobes/opt.c index e6b8c5362b94..e57e07b0edb6 100644 --- a/arch/x86/kernel/kprobes/opt.c +++ b/arch/x86/kernel/kprobes/opt.c @@ -15,6 +15,7 @@ #include <linux/extable.h> #include <linux/kdebug.h> #include <linux/kallsyms.h> +#include <linux/kgdb.h> #include <linux/ftrace.h> #include <linux/objtool.h> #include <linux/pgtable.h> @@ -279,19 +280,6 @@ static int insn_is_indirect_jump(struct insn *insn) return ret; } -static bool is_padding_int3(unsigned long addr, unsigned long eaddr) -{ - unsigned char ops; - - for (; addr < eaddr; addr++) { - if (get_kernel_nofault(ops, (void *)addr) < 0 || - ops != INT3_INSN_OPCODE) - return false; - } - - return true; -} - /* Decode whole function to ensure any instructions don't jump into target */ static int can_optimize(unsigned long paddr) { @@ -334,15 +322,15 @@ static int can_optimize(unsigned long paddr) ret = insn_decode_kernel(&insn, (void *)recovered_insn); if (ret < 0) return 0; - +#ifdef CONFIG_KGDB /* - * In the case of detecting unknown breakpoint, this could be - * a padding INT3 between functions. Let's check that all the - * rest of the bytes are also INT3. + * If there is a dynamically installed kgdb sw breakpoint, + * this function should not be probed. */ - if (insn.opcode.bytes[0] == INT3_INSN_OPCODE) - return is_padding_int3(addr, paddr - offset + size) ? 1 : 0; - + if (insn.opcode.bytes[0] == INT3_INSN_OPCODE && + kgdb_has_hit_break(addr)) + return 0; +#endif /* Recover address */ insn.kaddr = (void *)addr; insn.next_byte = (void *)(addr + insn.length); diff --git a/arch/x86/kernel/sev.c b/arch/x86/kernel/sev.c index a428c62330d3..679026a640ef 100644 --- a/arch/x86/kernel/sev.c +++ b/arch/x86/kernel/sev.c @@ -1536,32 +1536,32 @@ static enum es_result vc_handle_mmio_movs(struct es_em_ctxt *ctxt, static enum es_result vc_handle_mmio(struct ghcb *ghcb, struct es_em_ctxt *ctxt) { struct insn *insn = &ctxt->insn; + enum insn_mmio_type mmio; unsigned int bytes = 0; - enum mmio_type mmio; enum es_result ret; u8 sign_byte; long *reg_data; mmio = insn_decode_mmio(insn, &bytes); - if (mmio == MMIO_DECODE_FAILED) + if (mmio == INSN_MMIO_DECODE_FAILED) return ES_DECODE_FAILED; - if (mmio != MMIO_WRITE_IMM && mmio != MMIO_MOVS) { + if (mmio != INSN_MMIO_WRITE_IMM && mmio != INSN_MMIO_MOVS) { reg_data = insn_get_modrm_reg_ptr(insn, ctxt->regs); if (!reg_data) return ES_DECODE_FAILED; } switch (mmio) { - case MMIO_WRITE: + case INSN_MMIO_WRITE: memcpy(ghcb->shared_buffer, reg_data, bytes); ret = vc_do_mmio(ghcb, ctxt, bytes, false); break; - case MMIO_WRITE_IMM: + case INSN_MMIO_WRITE_IMM: memcpy(ghcb->shared_buffer, insn->immediate1.bytes, bytes); ret = vc_do_mmio(ghcb, ctxt, bytes, false); break; - case MMIO_READ: + case INSN_MMIO_READ: ret = vc_do_mmio(ghcb, ctxt, bytes, true); if (ret) break; @@ -1572,7 +1572,7 @@ static enum es_result vc_handle_mmio(struct ghcb *ghcb, struct es_em_ctxt *ctxt) memcpy(reg_data, ghcb->shared_buffer, bytes); break; - case MMIO_READ_ZERO_EXTEND: + case INSN_MMIO_READ_ZERO_EXTEND: ret = vc_do_mmio(ghcb, ctxt, bytes, true); if (ret) break; @@ -1581,7 +1581,7 @@ static enum es_result vc_handle_mmio(struct ghcb *ghcb, struct es_em_ctxt *ctxt) memset(reg_data, 0, insn->opnd_bytes); memcpy(reg_data, ghcb->shared_buffer, bytes); break; - case MMIO_READ_SIGN_EXTEND: + case INSN_MMIO_READ_SIGN_EXTEND: ret = vc_do_mmio(ghcb, ctxt, bytes, true); if (ret) break; @@ -1600,7 +1600,7 @@ static enum es_result vc_handle_mmio(struct ghcb *ghcb, struct es_em_ctxt *ctxt) memset(reg_data, sign_byte, insn->opnd_bytes); memcpy(reg_data, ghcb->shared_buffer, bytes); break; - case MMIO_MOVS: + case INSN_MMIO_MOVS: ret = vc_handle_mmio_movs(ctxt, bytes); break; default: diff --git a/arch/x86/kvm/hyperv.c b/arch/x86/kvm/hyperv.c index 2c7f2a26421e..e8296942a868 100644 --- a/arch/x86/kvm/hyperv.c +++ b/arch/x86/kvm/hyperv.c @@ -1769,6 +1769,7 @@ static bool hv_is_vp_in_sparse_set(u32 vp_id, u64 valid_bank_mask, u64 sparse_ba } struct kvm_hv_hcall { + /* Hypercall input data */ u64 param; u64 ingpa; u64 outgpa; @@ -1779,12 +1780,21 @@ struct kvm_hv_hcall { bool fast; bool rep; sse128_t xmm[HV_HYPERCALL_MAX_XMM_REGISTERS]; + + /* + * Current read offset when KVM reads hypercall input data gradually, + * either offset in bytes from 'ingpa' for regular hypercalls or the + * number of already consumed 'XMM halves' for 'fast' hypercalls. + */ + union { + gpa_t data_offset; + int consumed_xmm_halves; + }; }; static int kvm_hv_get_hc_data(struct kvm *kvm, struct kvm_hv_hcall *hc, - u16 orig_cnt, u16 cnt_cap, u64 *data, - int consumed_xmm_halves, gpa_t offset) + u16 orig_cnt, u16 cnt_cap, u64 *data) { /* * Preserve the original count when ignoring entries via a "cap", KVM @@ -1799,11 +1809,11 @@ static int kvm_hv_get_hc_data(struct kvm *kvm, struct kvm_hv_hcall *hc, * Each XMM holds two sparse banks, but do not count halves that * have already been consumed for hypercall parameters. */ - if (orig_cnt > 2 * HV_HYPERCALL_MAX_XMM_REGISTERS - consumed_xmm_halves) + if (orig_cnt > 2 * HV_HYPERCALL_MAX_XMM_REGISTERS - hc->consumed_xmm_halves) return HV_STATUS_INVALID_HYPERCALL_INPUT; for (i = 0; i < cnt; i++) { - j = i + consumed_xmm_halves; + j = i + hc->consumed_xmm_halves; if (j % 2) data[i] = sse128_hi(hc->xmm[j / 2]); else @@ -1812,27 +1822,24 @@ static int kvm_hv_get_hc_data(struct kvm *kvm, struct kvm_hv_hcall *hc, return 0; } - return kvm_read_guest(kvm, hc->ingpa + offset, data, + return kvm_read_guest(kvm, hc->ingpa + hc->data_offset, data, cnt * sizeof(*data)); } static u64 kvm_get_sparse_vp_set(struct kvm *kvm, struct kvm_hv_hcall *hc, - u64 *sparse_banks, int consumed_xmm_halves, - gpa_t offset) + u64 *sparse_banks) { if (hc->var_cnt > HV_MAX_SPARSE_VCPU_BANKS) return -EINVAL; /* Cap var_cnt to ignore banks that cannot contain a legal VP index. */ return kvm_hv_get_hc_data(kvm, hc, hc->var_cnt, KVM_HV_MAX_SPARSE_VCPU_SET_BITS, - sparse_banks, consumed_xmm_halves, offset); + sparse_banks); } -static int kvm_hv_get_tlb_flush_entries(struct kvm *kvm, struct kvm_hv_hcall *hc, u64 entries[], - int consumed_xmm_halves, gpa_t offset) +static int kvm_hv_get_tlb_flush_entries(struct kvm *kvm, struct kvm_hv_hcall *hc, u64 entries[]) { - return kvm_hv_get_hc_data(kvm, hc, hc->rep_cnt, hc->rep_cnt, - entries, consumed_xmm_halves, offset); + return kvm_hv_get_hc_data(kvm, hc, hc->rep_cnt, hc->rep_cnt, entries); } static void hv_tlb_flush_enqueue(struct kvm_vcpu *vcpu, @@ -1926,8 +1933,6 @@ static u64 kvm_hv_flush_tlb(struct kvm_vcpu *vcpu, struct kvm_hv_hcall *hc) struct kvm_vcpu *v; unsigned long i; bool all_cpus; - int consumed_xmm_halves = 0; - gpa_t data_offset; /* * The Hyper-V TLFS doesn't allow more than HV_MAX_SPARSE_VCPU_BANKS @@ -1955,12 +1960,12 @@ static u64 kvm_hv_flush_tlb(struct kvm_vcpu *vcpu, struct kvm_hv_hcall *hc) flush.address_space = hc->ingpa; flush.flags = hc->outgpa; flush.processor_mask = sse128_lo(hc->xmm[0]); - consumed_xmm_halves = 1; + hc->consumed_xmm_halves = 1; } else { if (unlikely(kvm_read_guest(kvm, hc->ingpa, &flush, sizeof(flush)))) return HV_STATUS_INVALID_HYPERCALL_INPUT; - data_offset = sizeof(flush); + hc->data_offset = sizeof(flush); } trace_kvm_hv_flush_tlb(flush.processor_mask, @@ -1985,12 +1990,12 @@ static u64 kvm_hv_flush_tlb(struct kvm_vcpu *vcpu, struct kvm_hv_hcall *hc) flush_ex.flags = hc->outgpa; memcpy(&flush_ex.hv_vp_set, &hc->xmm[0], sizeof(hc->xmm[0])); - consumed_xmm_halves = 2; + hc->consumed_xmm_halves = 2; } else { if (unlikely(kvm_read_guest(kvm, hc->ingpa, &flush_ex, sizeof(flush_ex)))) return HV_STATUS_INVALID_HYPERCALL_INPUT; - data_offset = sizeof(flush_ex); + hc->data_offset = sizeof(flush_ex); } trace_kvm_hv_flush_tlb_ex(flush_ex.hv_vp_set.valid_bank_mask, @@ -2009,8 +2014,7 @@ static u64 kvm_hv_flush_tlb(struct kvm_vcpu *vcpu, struct kvm_hv_hcall *hc) if (!hc->var_cnt) goto ret_success; - if (kvm_get_sparse_vp_set(kvm, hc, sparse_banks, - consumed_xmm_halves, data_offset)) + if (kvm_get_sparse_vp_set(kvm, hc, sparse_banks)) return HV_STATUS_INVALID_HYPERCALL_INPUT; } @@ -2021,8 +2025,10 @@ static u64 kvm_hv_flush_tlb(struct kvm_vcpu *vcpu, struct kvm_hv_hcall *hc) * consumed_xmm_halves to make sure TLB flush entries are read * from the correct offset. */ - data_offset += hc->var_cnt * sizeof(sparse_banks[0]); - consumed_xmm_halves += hc->var_cnt; + if (hc->fast) + hc->consumed_xmm_halves += hc->var_cnt; + else + hc->data_offset += hc->var_cnt * sizeof(sparse_banks[0]); } if (hc->code == HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE || @@ -2030,8 +2036,7 @@ static u64 kvm_hv_flush_tlb(struct kvm_vcpu *vcpu, struct kvm_hv_hcall *hc) hc->rep_cnt > ARRAY_SIZE(__tlb_flush_entries)) { tlb_flush_entries = NULL; } else { - if (kvm_hv_get_tlb_flush_entries(kvm, hc, __tlb_flush_entries, - consumed_xmm_halves, data_offset)) + if (kvm_hv_get_tlb_flush_entries(kvm, hc, __tlb_flush_entries)) return HV_STATUS_INVALID_HYPERCALL_INPUT; tlb_flush_entries = __tlb_flush_entries; } @@ -2180,9 +2185,13 @@ static u64 kvm_hv_send_ipi(struct kvm_vcpu *vcpu, struct kvm_hv_hcall *hc) if (!hc->var_cnt) goto ret_success; - if (kvm_get_sparse_vp_set(kvm, hc, sparse_banks, 1, - offsetof(struct hv_send_ipi_ex, - vp_set.bank_contents))) + if (!hc->fast) + hc->data_offset = offsetof(struct hv_send_ipi_ex, + vp_set.bank_contents); + else + hc->consumed_xmm_halves = 1; + + if (kvm_get_sparse_vp_set(kvm, hc, sparse_banks)) return HV_STATUS_INVALID_HYPERCALL_INPUT; } diff --git a/arch/x86/kvm/irq_comm.c b/arch/x86/kvm/irq_comm.c index 0687162c4f22..3742d9adacfc 100644 --- a/arch/x86/kvm/irq_comm.c +++ b/arch/x86/kvm/irq_comm.c @@ -426,8 +426,9 @@ void kvm_scan_ioapic_routes(struct kvm_vcpu *vcpu, kvm_set_msi_irq(vcpu->kvm, entry, &irq); if (irq.trig_mode && - kvm_apic_match_dest(vcpu, NULL, APIC_DEST_NOSHORT, - irq.dest_id, irq.dest_mode)) + (kvm_apic_match_dest(vcpu, NULL, APIC_DEST_NOSHORT, + irq.dest_id, irq.dest_mode) || + kvm_apic_pending_eoi(vcpu, irq.vector))) __set_bit(irq.vector, ioapic_handled_vectors); } } diff --git a/arch/x86/kvm/lapic.h b/arch/x86/kvm/lapic.h index 28e3769066e2..58c3242fcc7a 100644 --- a/arch/x86/kvm/lapic.h +++ b/arch/x86/kvm/lapic.h @@ -188,11 +188,11 @@ static inline bool lapic_in_kernel(struct kvm_vcpu *vcpu) extern struct static_key_false_deferred apic_hw_disabled; -static inline int kvm_apic_hw_enabled(struct kvm_lapic *apic) +static inline bool kvm_apic_hw_enabled(struct kvm_lapic *apic) { if (static_branch_unlikely(&apic_hw_disabled.key)) return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE; - return MSR_IA32_APICBASE_ENABLE; + return true; } extern struct static_key_false_deferred apic_sw_disabled; diff --git a/arch/x86/kvm/mmu/spte.h b/arch/x86/kvm/mmu/spte.h index 1f03701b943a..6f54dc9409c9 100644 --- a/arch/x86/kvm/mmu/spte.h +++ b/arch/x86/kvm/mmu/spte.h @@ -363,7 +363,7 @@ static __always_inline bool is_rsvd_spte(struct rsvd_bits_validate *rsvd_check, * A shadow-present leaf SPTE may be non-writable for 4 possible reasons: * * 1. To intercept writes for dirty logging. KVM write-protects huge pages - * so that they can be split be split down into the dirty logging + * so that they can be split down into the dirty logging * granularity (4KiB) whenever the guest writes to them. KVM also * write-protects 4KiB pages so that writes can be recorded in the dirty log * (e.g. if not using PML). SPTEs are write-protected for dirty logging diff --git a/arch/x86/kvm/mmu/tdp_mmu.c b/arch/x86/kvm/mmu/tdp_mmu.c index 771210ce5181..d6df38d371a0 100644 --- a/arch/x86/kvm/mmu/tdp_mmu.c +++ b/arch/x86/kvm/mmu/tdp_mmu.c @@ -1074,7 +1074,9 @@ static int tdp_mmu_map_handle_target_level(struct kvm_vcpu *vcpu, int ret = RET_PF_FIXED; bool wrprot = false; - WARN_ON(sp->role.level != fault->goal_level); + if (WARN_ON_ONCE(sp->role.level != fault->goal_level)) + return RET_PF_RETRY; + if (unlikely(!fault->slot)) new_spte = make_mmio_spte(vcpu, iter->gfn, ACC_ALL); else @@ -1173,9 +1175,6 @@ int kvm_tdp_mmu_map(struct kvm_vcpu *vcpu, struct kvm_page_fault *fault) if (fault->nx_huge_page_workaround_enabled) disallowed_hugepage_adjust(fault, iter.old_spte, iter.level); - if (iter.level == fault->goal_level) - break; - /* * If SPTE has been frozen by another thread, just give up and * retry, avoiding unnecessary page table allocation and free. @@ -1183,6 +1182,9 @@ int kvm_tdp_mmu_map(struct kvm_vcpu *vcpu, struct kvm_page_fault *fault) if (is_removed_spte(iter.old_spte)) goto retry; + if (iter.level == fault->goal_level) + goto map_target_level; + /* Step down into the lower level page table if it exists. */ if (is_shadow_present_pte(iter.old_spte) && !is_large_pte(iter.old_spte)) @@ -1203,8 +1205,8 @@ int kvm_tdp_mmu_map(struct kvm_vcpu *vcpu, struct kvm_page_fault *fault) r = tdp_mmu_link_sp(kvm, &iter, sp, true); /* - * Also force the guest to retry the access if the upper level SPTEs - * aren't in place. + * Force the guest to retry if installing an upper level SPTE + * failed, e.g. because a different task modified the SPTE. */ if (r) { tdp_mmu_free_sp(sp); @@ -1214,11 +1216,20 @@ int kvm_tdp_mmu_map(struct kvm_vcpu *vcpu, struct kvm_page_fault *fault) if (fault->huge_page_disallowed && fault->req_level >= iter.level) { spin_lock(&kvm->arch.tdp_mmu_pages_lock); - track_possible_nx_huge_page(kvm, sp); + if (sp->nx_huge_page_disallowed) + track_possible_nx_huge_page(kvm, sp); spin_unlock(&kvm->arch.tdp_mmu_pages_lock); } } + /* + * The walk aborted before reaching the target level, e.g. because the + * iterator detected an upper level SPTE was frozen during traversal. + */ + WARN_ON_ONCE(iter.level == fault->goal_level); + goto retry; + +map_target_level: ret = tdp_mmu_map_handle_target_level(vcpu, fault, &iter); retry: diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index 684393c22105..eb594620dd75 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -238,7 +238,8 @@ static bool pmc_resume_counter(struct kvm_pmc *pmc) return false; /* recalibrate sample period and check if it's accepted by perf core */ - if (perf_event_period(pmc->perf_event, + if (is_sampling_event(pmc->perf_event) && + perf_event_period(pmc->perf_event, get_sample_period(pmc, pmc->counter))) return false; diff --git a/arch/x86/kvm/pmu.h b/arch/x86/kvm/pmu.h index 85ff3c0588ba..cdb91009701d 100644 --- a/arch/x86/kvm/pmu.h +++ b/arch/x86/kvm/pmu.h @@ -140,7 +140,8 @@ static inline u64 get_sample_period(struct kvm_pmc *pmc, u64 counter_value) static inline void pmc_update_sample_period(struct kvm_pmc *pmc) { - if (!pmc->perf_event || pmc->is_paused) + if (!pmc->perf_event || pmc->is_paused || + !is_sampling_event(pmc->perf_event)) return; perf_event_period(pmc->perf_event, diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c index b6f4411b613e..d93c715cda6a 100644 --- a/arch/x86/kvm/vmx/nested.c +++ b/arch/x86/kvm/vmx/nested.c @@ -5296,10 +5296,19 @@ static int handle_vmclear(struct kvm_vcpu *vcpu) if (vmptr == vmx->nested.current_vmptr) nested_release_vmcs12(vcpu); - kvm_vcpu_write_guest(vcpu, - vmptr + offsetof(struct vmcs12, - launch_state), - &zero, sizeof(zero)); + /* + * Silently ignore memory errors on VMCLEAR, Intel's pseudocode + * for VMCLEAR includes a "ensure that data for VMCS referenced + * by the operand is in memory" clause that guards writes to + * memory, i.e. doing nothing for I/O is architecturally valid. + * + * FIXME: Suppress failures if and only if no memslot is found, + * i.e. exit to userspace if __copy_to_user() fails. + */ + (void)kvm_vcpu_write_guest(vcpu, + vmptr + offsetof(struct vmcs12, + launch_state), + &zero, sizeof(zero)); } else if (vmx->nested.hv_evmcs && vmptr == vmx->nested.hv_evmcs_vmptr) { nested_release_evmcs(vcpu); } @@ -6873,7 +6882,8 @@ void nested_vmx_setup_ctls_msrs(struct vmcs_config *vmcs_conf, u32 ept_caps) SECONDARY_EXEC_ENABLE_INVPCID | SECONDARY_EXEC_RDSEED_EXITING | SECONDARY_EXEC_XSAVES | - SECONDARY_EXEC_TSC_SCALING; + SECONDARY_EXEC_TSC_SCALING | + SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE; /* * We can emulate "VMCS shadowing," even if the hardware diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index fe5615fd8295..fc9008dbed33 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -4459,6 +4459,13 @@ vmx_adjust_secondary_exec_control(struct vcpu_vmx *vmx, u32 *exec_control, * controls for features that are/aren't exposed to the guest. */ if (nested) { + /* + * All features that can be added or removed to VMX MSRs must + * be supported in the first place for nested virtualization. + */ + if (WARN_ON_ONCE(!(vmcs_config.nested.secondary_ctls_high & control))) + enabled = false; + if (enabled) vmx->nested.msrs.secondary_ctls_high |= control; else diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 312aea1854ae..da4bbd043a7b 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -13132,6 +13132,9 @@ int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r, struct x86_exception *e) { if (r == X86EMUL_PROPAGATE_FAULT) { + if (KVM_BUG_ON(!e, vcpu->kvm)) + return -EIO; + kvm_inject_emulated_page_fault(vcpu, e); return 1; } diff --git a/arch/x86/kvm/xen.c b/arch/x86/kvm/xen.c index d7af40240248..2e29bdc2949c 100644 --- a/arch/x86/kvm/xen.c +++ b/arch/x86/kvm/xen.c @@ -41,7 +41,7 @@ static int kvm_xen_shared_info_init(struct kvm *kvm, gfn_t gfn) int ret = 0; int idx = srcu_read_lock(&kvm->srcu); - if (gfn == GPA_INVALID) { + if (gfn == KVM_XEN_INVALID_GFN) { kvm_gpc_deactivate(gpc); goto out; } @@ -659,7 +659,7 @@ int kvm_xen_hvm_get_attr(struct kvm *kvm, struct kvm_xen_hvm_attr *data) if (kvm->arch.xen.shinfo_cache.active) data->u.shared_info.gfn = gpa_to_gfn(kvm->arch.xen.shinfo_cache.gpa); else - data->u.shared_info.gfn = GPA_INVALID; + data->u.shared_info.gfn = KVM_XEN_INVALID_GFN; r = 0; break; @@ -705,7 +705,7 @@ int kvm_xen_vcpu_set_attr(struct kvm_vcpu *vcpu, struct kvm_xen_vcpu_attr *data) BUILD_BUG_ON(offsetof(struct vcpu_info, time) != offsetof(struct compat_vcpu_info, time)); - if (data->u.gpa == GPA_INVALID) { + if (data->u.gpa == KVM_XEN_INVALID_GPA) { kvm_gpc_deactivate(&vcpu->arch.xen.vcpu_info_cache); r = 0; break; @@ -719,7 +719,7 @@ int kvm_xen_vcpu_set_attr(struct kvm_vcpu *vcpu, struct kvm_xen_vcpu_attr *data) break; case KVM_XEN_VCPU_ATTR_TYPE_VCPU_TIME_INFO: - if (data->u.gpa == GPA_INVALID) { + if (data->u.gpa == KVM_XEN_INVALID_GPA) { kvm_gpc_deactivate(&vcpu->arch.xen.vcpu_time_info_cache); r = 0; break; @@ -739,7 +739,7 @@ int kvm_xen_vcpu_set_attr(struct kvm_vcpu *vcpu, struct kvm_xen_vcpu_attr *data) r = -EOPNOTSUPP; break; } - if (data->u.gpa == GPA_INVALID) { + if (data->u.gpa == KVM_XEN_INVALID_GPA) { r = 0; deactivate_out: kvm_gpc_deactivate(&vcpu->arch.xen.runstate_cache); @@ -937,7 +937,7 @@ int kvm_xen_vcpu_get_attr(struct kvm_vcpu *vcpu, struct kvm_xen_vcpu_attr *data) if (vcpu->arch.xen.vcpu_info_cache.active) data->u.gpa = vcpu->arch.xen.vcpu_info_cache.gpa; else - data->u.gpa = GPA_INVALID; + data->u.gpa = KVM_XEN_INVALID_GPA; r = 0; break; @@ -945,7 +945,7 @@ int kvm_xen_vcpu_get_attr(struct kvm_vcpu *vcpu, struct kvm_xen_vcpu_attr *data) if (vcpu->arch.xen.vcpu_time_info_cache.active) data->u.gpa = vcpu->arch.xen.vcpu_time_info_cache.gpa; else - data->u.gpa = GPA_INVALID; + data->u.gpa = KVM_XEN_INVALID_GPA; r = 0; break; @@ -1069,6 +1069,7 @@ int kvm_xen_write_hypercall_page(struct kvm_vcpu *vcpu, u64 data) u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 : kvm->arch.xen_hvm_config.blob_size_32; u8 *page; + int ret; if (page_num >= blob_size) return 1; @@ -1079,10 +1080,10 @@ int kvm_xen_write_hypercall_page(struct kvm_vcpu *vcpu, u64 data) if (IS_ERR(page)) return PTR_ERR(page); - if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE)) { - kfree(page); + ret = kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE); + kfree(page); + if (ret) return 1; - } } return 0; } @@ -1183,30 +1184,22 @@ static bool wait_pending_event(struct kvm_vcpu *vcpu, int nr_ports, static bool kvm_xen_schedop_poll(struct kvm_vcpu *vcpu, bool longmode, u64 param, u64 *r) { - int idx, i; struct sched_poll sched_poll; evtchn_port_t port, *ports; - gpa_t gpa; + struct x86_exception e; + int i; if (!lapic_in_kernel(vcpu) || !(vcpu->kvm->arch.xen_hvm_config.flags & KVM_XEN_HVM_CONFIG_EVTCHN_SEND)) return false; - idx = srcu_read_lock(&vcpu->kvm->srcu); - gpa = kvm_mmu_gva_to_gpa_system(vcpu, param, NULL); - srcu_read_unlock(&vcpu->kvm->srcu, idx); - if (!gpa) { - *r = -EFAULT; - return true; - } - if (IS_ENABLED(CONFIG_64BIT) && !longmode) { struct compat_sched_poll sp32; /* Sanity check that the compat struct definition is correct */ BUILD_BUG_ON(sizeof(sp32) != 16); - if (kvm_vcpu_read_guest(vcpu, gpa, &sp32, sizeof(sp32))) { + if (kvm_read_guest_virt(vcpu, param, &sp32, sizeof(sp32), &e)) { *r = -EFAULT; return true; } @@ -1220,8 +1213,8 @@ static bool kvm_xen_schedop_poll(struct kvm_vcpu *vcpu, bool longmode, sched_poll.nr_ports = sp32.nr_ports; sched_poll.timeout = sp32.timeout; } else { - if (kvm_vcpu_read_guest(vcpu, gpa, &sched_poll, - sizeof(sched_poll))) { + if (kvm_read_guest_virt(vcpu, param, &sched_poll, + sizeof(sched_poll), &e)) { *r = -EFAULT; return true; } @@ -1243,18 +1236,13 @@ static bool kvm_xen_schedop_poll(struct kvm_vcpu *vcpu, bool longmode, } else ports = &port; + if (kvm_read_guest_virt(vcpu, (gva_t)sched_poll.ports, ports, + sched_poll.nr_ports * sizeof(*ports), &e)) { + *r = -EFAULT; + return true; + } + for (i = 0; i < sched_poll.nr_ports; i++) { - idx = srcu_read_lock(&vcpu->kvm->srcu); - gpa = kvm_mmu_gva_to_gpa_system(vcpu, - (gva_t)(sched_poll.ports + i), - NULL); - srcu_read_unlock(&vcpu->kvm->srcu, idx); - - if (!gpa || kvm_vcpu_read_guest(vcpu, gpa, - &ports[i], sizeof(port))) { - *r = -EFAULT; - goto out; - } if (ports[i] >= max_evtchn_port(vcpu->kvm)) { *r = -EINVAL; goto out; @@ -1330,9 +1318,8 @@ static bool kvm_xen_hcall_vcpu_op(struct kvm_vcpu *vcpu, bool longmode, int cmd, int vcpu_id, u64 param, u64 *r) { struct vcpu_set_singleshot_timer oneshot; + struct x86_exception e; s64 delta; - gpa_t gpa; - int idx; if (!kvm_xen_timer_enabled(vcpu)) return false; @@ -1343,9 +1330,6 @@ static bool kvm_xen_hcall_vcpu_op(struct kvm_vcpu *vcpu, bool longmode, int cmd, *r = -EINVAL; return true; } - idx = srcu_read_lock(&vcpu->kvm->srcu); - gpa = kvm_mmu_gva_to_gpa_system(vcpu, param, NULL); - srcu_read_unlock(&vcpu->kvm->srcu, idx); /* * The only difference for 32-bit compat is the 4 bytes of @@ -1363,9 +1347,8 @@ static bool kvm_xen_hcall_vcpu_op(struct kvm_vcpu *vcpu, bool longmode, int cmd, BUILD_BUG_ON(sizeof_field(struct compat_vcpu_set_singleshot_timer, flags) != sizeof_field(struct vcpu_set_singleshot_timer, flags)); - if (!gpa || - kvm_vcpu_read_guest(vcpu, gpa, &oneshot, longmode ? sizeof(oneshot) : - sizeof(struct compat_vcpu_set_singleshot_timer))) { + if (kvm_read_guest_virt(vcpu, param, &oneshot, longmode ? sizeof(oneshot) : + sizeof(struct compat_vcpu_set_singleshot_timer), &e)) { *r = -EFAULT; return true; } @@ -1825,20 +1808,20 @@ static int kvm_xen_eventfd_update(struct kvm *kvm, { u32 port = data->u.evtchn.send_port; struct evtchnfd *evtchnfd; + int ret; - if (!port || port >= max_evtchn_port(kvm)) - return -EINVAL; - + /* Protect writes to evtchnfd as well as the idr lookup. */ mutex_lock(&kvm->lock); evtchnfd = idr_find(&kvm->arch.xen.evtchn_ports, port); - mutex_unlock(&kvm->lock); + ret = -ENOENT; if (!evtchnfd) - return -ENOENT; + goto out_unlock; /* For an UPDATE, nothing may change except the priority/vcpu */ + ret = -EINVAL; if (evtchnfd->type != data->u.evtchn.type) - return -EINVAL; + goto out_unlock; /* * Port cannot change, and if it's zero that was an eventfd @@ -1846,20 +1829,21 @@ static int kvm_xen_eventfd_update(struct kvm *kvm, */ if (!evtchnfd->deliver.port.port || evtchnfd->deliver.port.port != data->u.evtchn.deliver.port.port) - return -EINVAL; + goto out_unlock; /* We only support 2 level event channels for now */ if (data->u.evtchn.deliver.port.priority != KVM_IRQ_ROUTING_XEN_EVTCHN_PRIO_2LEVEL) - return -EINVAL; + goto out_unlock; - mutex_lock(&kvm->lock); evtchnfd->deliver.port.priority = data->u.evtchn.deliver.port.priority; if (evtchnfd->deliver.port.vcpu_id != data->u.evtchn.deliver.port.vcpu) { evtchnfd->deliver.port.vcpu_id = data->u.evtchn.deliver.port.vcpu; evtchnfd->deliver.port.vcpu_idx = -1; } + ret = 0; +out_unlock: mutex_unlock(&kvm->lock); - return 0; + return ret; } /* @@ -1871,12 +1855,9 @@ static int kvm_xen_eventfd_assign(struct kvm *kvm, { u32 port = data->u.evtchn.send_port; struct eventfd_ctx *eventfd = NULL; - struct evtchnfd *evtchnfd = NULL; + struct evtchnfd *evtchnfd; int ret = -EINVAL; - if (!port || port >= max_evtchn_port(kvm)) - return -EINVAL; - evtchnfd = kzalloc(sizeof(struct evtchnfd), GFP_KERNEL); if (!evtchnfd) return -ENOMEM; @@ -1952,8 +1933,7 @@ static int kvm_xen_eventfd_deassign(struct kvm *kvm, u32 port) if (!evtchnfd) return -ENOENT; - if (kvm) - synchronize_srcu(&kvm->srcu); + synchronize_srcu(&kvm->srcu); if (!evtchnfd->deliver.port.port) eventfd_ctx_put(evtchnfd->deliver.eventfd.ctx); kfree(evtchnfd); @@ -1962,18 +1942,42 @@ static int kvm_xen_eventfd_deassign(struct kvm *kvm, u32 port) static int kvm_xen_eventfd_reset(struct kvm *kvm) { - struct evtchnfd *evtchnfd; + struct evtchnfd *evtchnfd, **all_evtchnfds; int i; + int n = 0; mutex_lock(&kvm->lock); + + /* + * Because synchronize_srcu() cannot be called inside the + * critical section, first collect all the evtchnfd objects + * in an array as they are removed from evtchn_ports. + */ + idr_for_each_entry(&kvm->arch.xen.evtchn_ports, evtchnfd, i) + n++; + + all_evtchnfds = kmalloc_array(n, sizeof(struct evtchnfd *), GFP_KERNEL); + if (!all_evtchnfds) { + mutex_unlock(&kvm->lock); + return -ENOMEM; + } + + n = 0; idr_for_each_entry(&kvm->arch.xen.evtchn_ports, evtchnfd, i) { + all_evtchnfds[n++] = evtchnfd; idr_remove(&kvm->arch.xen.evtchn_ports, evtchnfd->send_port); - synchronize_srcu(&kvm->srcu); + } + mutex_unlock(&kvm->lock); + + synchronize_srcu(&kvm->srcu); + + while (n--) { + evtchnfd = all_evtchnfds[n]; if (!evtchnfd->deliver.port.port) eventfd_ctx_put(evtchnfd->deliver.eventfd.ctx); kfree(evtchnfd); } - mutex_unlock(&kvm->lock); + kfree(all_evtchnfds); return 0; } @@ -2002,20 +2006,22 @@ static bool kvm_xen_hcall_evtchn_send(struct kvm_vcpu *vcpu, u64 param, u64 *r) { struct evtchnfd *evtchnfd; struct evtchn_send send; - gpa_t gpa; - int idx; - - idx = srcu_read_lock(&vcpu->kvm->srcu); - gpa = kvm_mmu_gva_to_gpa_system(vcpu, param, NULL); - srcu_read_unlock(&vcpu->kvm->srcu, idx); + struct x86_exception e; - if (!gpa || kvm_vcpu_read_guest(vcpu, gpa, &send, sizeof(send))) { + /* Sanity check: this structure is the same for 32-bit and 64-bit */ + BUILD_BUG_ON(sizeof(send) != 4); + if (kvm_read_guest_virt(vcpu, param, &send, sizeof(send), &e)) { *r = -EFAULT; return true; } - /* The evtchn_ports idr is protected by vcpu->kvm->srcu */ + /* + * evtchnfd is protected by kvm->srcu; the idr lookup instead + * is protected by RCU. + */ + rcu_read_lock(); evtchnfd = idr_find(&vcpu->kvm->arch.xen.evtchn_ports, send.port); + rcu_read_unlock(); if (!evtchnfd) return false; diff --git a/arch/x86/lib/insn-eval.c b/arch/x86/lib/insn-eval.c index 21104c41cba0..558a605929db 100644 --- a/arch/x86/lib/insn-eval.c +++ b/arch/x86/lib/insn-eval.c @@ -1595,16 +1595,16 @@ bool insn_decode_from_regs(struct insn *insn, struct pt_regs *regs, * Returns: * * Type of the instruction. Size of the memory operand is stored in - * @bytes. If decode failed, MMIO_DECODE_FAILED returned. + * @bytes. If decode failed, INSN_MMIO_DECODE_FAILED returned. */ -enum mmio_type insn_decode_mmio(struct insn *insn, int *bytes) +enum insn_mmio_type insn_decode_mmio(struct insn *insn, int *bytes) { - enum mmio_type type = MMIO_DECODE_FAILED; + enum insn_mmio_type type = INSN_MMIO_DECODE_FAILED; *bytes = 0; if (insn_get_opcode(insn)) - return MMIO_DECODE_FAILED; + return INSN_MMIO_DECODE_FAILED; switch (insn->opcode.bytes[0]) { case 0x88: /* MOV m8,r8 */ @@ -1613,7 +1613,7 @@ enum mmio_type insn_decode_mmio(struct insn *insn, int *bytes) case 0x89: /* MOV m16/m32/m64, r16/m32/m64 */ if (!*bytes) *bytes = insn->opnd_bytes; - type = MMIO_WRITE; + type = INSN_MMIO_WRITE; break; case 0xc6: /* MOV m8, imm8 */ @@ -1622,7 +1622,7 @@ enum mmio_type insn_decode_mmio(struct insn *insn, int *bytes) case 0xc7: /* MOV m16/m32/m64, imm16/imm32/imm64 */ if (!*bytes) *bytes = insn->opnd_bytes; - type = MMIO_WRITE_IMM; + type = INSN_MMIO_WRITE_IMM; break; case 0x8a: /* MOV r8, m8 */ @@ -1631,7 +1631,7 @@ enum mmio_type insn_decode_mmio(struct insn *insn, int *bytes) case 0x8b: /* MOV r16/r32/r64, m16/m32/m64 */ if (!*bytes) *bytes = insn->opnd_bytes; - type = MMIO_READ; + type = INSN_MMIO_READ; break; case 0xa4: /* MOVS m8, m8 */ @@ -1640,7 +1640,7 @@ enum mmio_type insn_decode_mmio(struct insn *insn, int *bytes) case 0xa5: /* MOVS m16/m32/m64, m16/m32/m64 */ if (!*bytes) *bytes = insn->opnd_bytes; - type = MMIO_MOVS; + type = INSN_MMIO_MOVS; break; case 0x0f: /* Two-byte instruction */ @@ -1651,7 +1651,7 @@ enum mmio_type insn_decode_mmio(struct insn *insn, int *bytes) case 0xb7: /* MOVZX r32/r64, m16 */ if (!*bytes) *bytes = 2; - type = MMIO_READ_ZERO_EXTEND; + type = INSN_MMIO_READ_ZERO_EXTEND; break; case 0xbe: /* MOVSX r16/r32/r64, m8 */ @@ -1660,7 +1660,7 @@ enum mmio_type insn_decode_mmio(struct insn *insn, int *bytes) case 0xbf: /* MOVSX r32/r64, m16 */ if (!*bytes) *bytes = 2; - type = MMIO_READ_SIGN_EXTEND; + type = INSN_MMIO_READ_SIGN_EXTEND; break; } break; diff --git a/arch/x86/lib/iomap_copy_64.S b/arch/x86/lib/iomap_copy_64.S index a1f9416bf67a..6ff2f56cb0f7 100644 --- a/arch/x86/lib/iomap_copy_64.S +++ b/arch/x86/lib/iomap_copy_64.S @@ -10,6 +10,6 @@ */ SYM_FUNC_START(__iowrite32_copy) movl %edx,%ecx - rep movsd + rep movsl RET SYM_FUNC_END(__iowrite32_copy) |