select ARCH_SHMOBILE

select ARM_PATCH_PHYS_VIRT if MMU

select CLKDEV_LOOKUP

select GENERIC_CLOCKEVENTS

select HAVE_ARM_SCU if SMP

select HAVE_ARM_TWD if SMP

select NO_IOPORT_MAP

select PINCTRL

select PM_GENERIC_DOMAINS if PM

select SPARSE_IRQ

help

Support for Renesas ARM SoC platforms using a non-multiplatform

i2c@13860000 {

pinctrl-0 = <&i2c0_bus>;

pinctrl-names = "default";

status = "okay";

usb3503: usb3503@08 {

max77686: pmic@09 {

compatible = "maxim,max77686";

reg = <0x09>;

#clock-cells = <1>;

samsung,pins = "gpx1-3";

samsung,pin-pud = <0>;

};

};

compatible = "fsl,imx53-vpu";

reg = <0x63ff4000 0x1000>;

interrupts = <9>;

<&clks IMX5_CLK_VPU_GATE>;

clock-names = "per", "ahb";

resets = <&src 1>;

pinctrl-names = "default";

pinctrl-0 = <&pinctrl_enet>;

phy-mode = "rgmii";

phy-supply = <&vgen2_1v2_eth>;

status = "okay";

};

MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0

MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0

MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0

MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8

>;

};

#define MX6SX_PAD_GPIO1_IO07__USDHC2_WP 0x0030 0x0378 0x0870 0x1 0x1

#define MX6SX_PAD_GPIO1_IO07__ENET2_MDIO 0x0030 0x0378 0x0770 0x2 0x0

#define MX6SX_PAD_GPIO1_IO07__AUDMUX_MCLK 0x0030 0x0378 0x0000 0x3 0x0

#define MX6SX_PAD_GPIO1_IO07__GPIO1_IO_7 0x0030 0x0378 0x0000 0x5 0x0

#define MX6SX_PAD_GPIO1_IO07__SRC_EARLY_RESET 0x0030 0x0378 0x0000 0x6 0x0

#define MX6SX_PAD_GPIO1_IO07__DCIC2_OUT 0x0030 0x0378 0x0000 0x7 0x0

#define MX6SX_PAD_GPIO1_IO09__WDOG2_WDOG_B 0x0038 0x0380 0x0000 0x1 0x0

#define MX6SX_PAD_GPIO1_IO09__SDMA_EXT_EVENT_1 0x0038 0x0380 0x0820 0x2 0x0

#define MX6SX_PAD_GPIO1_IO09__CCM_OUT0 0x0038 0x0380 0x0000 0x3 0x0

#define MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x0038 0x0380 0x0000 0x5 0x0

#define MX6SX_PAD_GPIO1_IO09__SRC_INT_BOOT 0x0038 0x0380 0x0000 0x6 0x0

#define MX6SX_PAD_GPIO1_IO09__OBSERVE_MUX_OUT_4 0x0038 0x0380 0x0000 0x7 0x0

#define MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x0068 0x03B0 0x079C 0x1 0x1

#define MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x0068 0x03B0 0x07C4 0x2 0x2

#define MX6SX_PAD_CSI_DATA07__KPP_ROW_7 0x0068 0x03B0 0x07DC 0x3 0x0

#define MX6SX_PAD_CSI_DATA07__GPIO1_IO_21 0x0068 0x03B0 0x0000 0x5 0x0

#define MX6SX_PAD_CSI_DATA07__WEIM_DATA_16 0x0068 0x03B0 0x0000 0x6 0x0

#define MX6SX_PAD_CSI_DATA07__DCIC1_OUT 0x0068 0x03B0 0x0000 0x7 0x0

#define MX6SX_PAD_CSI_VSYNC__CSI1_VSYNC 0x0078 0x03C0 0x0708 0x0 0x0

#define MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x0078 0x03C0 0x07A4 0x1 0x1

#define MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x0078 0x03C0 0x0674 0x2 0x1

#define MX6SX_PAD_CSI_VSYNC__MQS_RIGHT 0x0078 0x03C0 0x0000 0x4 0x0

#define MX6SX_PAD_CSI_VSYNC__GPIO1_IO_25 0x0078 0x03C0 0x0000 0x5 0x0

#define MX6SX_PAD_CSI_VSYNC__WEIM_DATA_24 0x0078 0x03C0 0x0000 0x6 0x0

#define MX6SX_PAD_ENET2_TX_CLK__ENET2_TX_CLK 0x00A0 0x03E8 0x0000 0x0 0x0

#define MX6SX_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x00A0 0x03E8 0x076C 0x1 0x1

#define MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA 0x00A0 0x03E8 0x07BC 0x2 0x1

#define MX6SX_PAD_ENET2_TX_CLK__MLB_CLK 0x00A0 0x03E8 0x07E8 0x4 0x1

#define MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0x00A0 0x03E8 0x0000 0x5 0x0

#define MX6SX_PAD_ENET2_TX_CLK__USB_OTG2_PWR 0x00A0 0x03E8 0x0000 0x6 0x0

#define MX6SX_PAD_KEY_COL4__SAI2_RX_BCLK 0x00B4 0x03FC 0x0808 0x7 0x0

#define MX6SX_PAD_KEY_ROW0__KPP_ROW_0 0x00B8 0x0400 0x0000 0x0 0x0

#define MX6SX_PAD_KEY_ROW0__USDHC3_WP 0x00B8 0x0400 0x0000 0x1 0x0

#define MX6SX_PAD_KEY_ROW0__ECSPI1_MOSI 0x00B8 0x0400 0x0718 0x3 0x0

#define MX6SX_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x00B8 0x0400 0x0660 0x4 0x0

#define MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x00B8 0x0400 0x0000 0x5 0x0

#define MX6SX_PAD_KEY_ROW1__M4_NMI 0x00BC 0x0404 0x0000 0x8 0x0

#define MX6SX_PAD_KEY_ROW2__KPP_ROW_2 0x00C0 0x0408 0x0000 0x0 0x0

#define MX6SX_PAD_KEY_ROW2__USDHC4_WP 0x00C0 0x0408 0x0878 0x1 0x1

#define MX6SX_PAD_KEY_ROW2__CAN1_RX 0x00C0 0x0408 0x068C 0x3 0x1

#define MX6SX_PAD_KEY_ROW2__CANFD_RX1 0x00C0 0x0408 0x0694 0x4 0x1

#define MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x00C0 0x0408 0x0000 0x5 0x0

#define MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05 0x0164 0x04AC 0x0000 0x0 0x0

#define MX6SX_PAD_NAND_DATA05__USDHC2_DATA5 0x0164 0x04AC 0x0000 0x1 0x0

#define MX6SX_PAD_NAND_DATA05__QSPI2_B_DQS 0x0164 0x04AC 0x0000 0x2 0x0

#define MX6SX_PAD_NAND_DATA05__AUDMUX_AUD4_RXC 0x0164 0x04AC 0x064C 0x4 0x0

#define MX6SX_PAD_NAND_DATA05__GPIO4_IO_9 0x0164 0x04AC 0x0000 0x5 0x0

#define MX6SX_PAD_NAND_DATA05__WEIM_AD_5 0x0164 0x04AC 0x0000 0x6 0x0

#define MX6SX_PAD_QSPI1A_SS1_B__SIM_M_HADDR_12 0x019C 0x04E4 0x0000 0x7 0x0

#define MX6SX_PAD_QSPI1A_SS1_B__SDMA_DEBUG_PC_3 0x019C 0x04E4 0x0000 0x9 0x0

#define MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 0x01A0 0x04E8 0x0000 0x0 0x0

#define MX6SX_PAD_QSPI1B_DATA0__ECSPI3_MOSI 0x01A0 0x04E8 0x0738 0x2 0x1

#define MX6SX_PAD_QSPI1B_DATA0__ESAI_RX_FS 0x01A0 0x04E8 0x0778 0x3 0x2

#define MX6SX_PAD_QSPI1B_DATA0__CSI1_DATA_22 0x01A0 0x04E8 0x06F4 0x4 0x1

#define MX6SX_PAD_SD1_DATA2__AUDMUX_AUD5_TXFS 0x0230 0x0578 0x0670 0x1 0x1

#define MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x0230 0x0578 0x0000 0x2 0x0

#define MX6SX_PAD_SD1_DATA2__GPT_COMPARE2 0x0230 0x0578 0x0000 0x3 0x0

#define MX6SX_PAD_SD1_DATA2__GPIO6_IO_4 0x0230 0x0578 0x0000 0x5 0x0

#define MX6SX_PAD_SD1_DATA2__ECSPI4_RDY 0x0230 0x0578 0x0000 0x6 0x0

#define MX6SX_PAD_SD1_DATA2__CCM_OUT0 0x0230 0x0578 0x0000 0x7 0x0

#define MX6SX_PAD_SD2_DATA3__VADC_CLAMP_CURRENT_3 0x024C 0x0594 0x0000 0x8 0x0

#define MX6SX_PAD_SD2_DATA3__MMDC_DEBUG_31 0x024C 0x0594 0x0000 0x9 0x0

#define MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x0250 0x0598 0x0000 0x0 0x0

#define MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x0250 0x0598 0x0740 0x2 0x0

#define MX6SX_PAD_SD3_CLK__AUDMUX_AUD6_RXFS 0x0250 0x0598 0x0680 0x3 0x0

#define MX6SX_PAD_SD3_CLK__LCDIF2_VSYNC 0x0250 0x0598 0x0000 0x4 0x0

#define MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x0274 0x05BC 0x0000 0x0 0x0

#define MX6SX_PAD_SD3_DATA7__CAN1_RX 0x0274 0x05BC 0x068C 0x1 0x0

#define MX6SX_PAD_SD3_DATA7__CANFD_RX1 0x0274 0x05BC 0x0694 0x2 0x0

#define MX6SX_PAD_SD3_DATA7__LCDIF2_DATA_5 0x0274 0x05BC 0x0000 0x4 0x0

#define MX6SX_PAD_SD3_DATA7__GPIO7_IO_9 0x0274 0x05BC 0x0000 0x5 0x0

#define MX6SX_PAD_SD3_DATA7__ENET1_1588_EVENT0_IN 0x0274 0x05BC 0x0000 0x6 0x0

#define MX6SX_PAD_SD4_DATA6__SDMA_DEBUG_EVENT_CHANNEL_1 0x0298 0x05E0 0x0000 0x9 0x0

#define MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x029C 0x05E4 0x0000 0x0 0x0

#define MX6SX_PAD_SD4_DATA7__RAWNAND_DATA08 0x029C 0x05E4 0x0000 0x1 0x0

#define MX6SX_PAD_SD4_DATA7__ECSPI3_SS0 0x029C 0x05E4 0x073C 0x3 0x0

#define MX6SX_PAD_SD4_DATA7__LCDIF2_DATA_15 0x029C 0x05E4 0x0000 0x4 0x0

#define MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x029C 0x05E4 0x0000 0x5 0x0

renesas,function = "msiof0";

};

usb0_pins: usb0 {

renesas,groups = "usb0";

renesas,function = "usb0";

};

&i2c6 {

status = "okay";

clock-frequency = <100000>;

&mmc0 { /* sdmmc */

num-slots = <1>;

status = "okay";

vmmc-supply = <&vcc_sd0>;

slot@0 {

&mmc0 {

num-slots = <1>;

status = "okay";

vmmc-supply = <&vcc_sd0>;

slot@0 {

clock-frequency = <100000>;

resets = <&apb2_rst 0>;

status = "disabled";

};

i2c1: i2c@01c2b000 {

clock-frequency = <100000>;

resets = <&apb2_rst 1>;

status = "disabled";

};

i2c2: i2c@01c2b400 {

clock-frequency = <100000>;

resets = <&apb2_rst 2>;

status = "disabled";

};

i2c3: i2c@01c2b800 {

clock-frequency = <100000>;

resets = <&apb2_rst 3>;

status = "disabled";

};

gmac: ethernet@01c30000 {

vcc4-supply = <&sys_3v3_reg>;

vcc5-supply = <&sys_3v3_reg>;

vcc6-supply = <&vio_reg>;

vccio-supply = <&sys_3v3_reg>;

regulators {

regulator-max-microvolt = <3300000>;

regulator-always-on;

};

};

};

vcc4-supply = <&sys_3v3_reg>;

vcc5-supply = <&sys_3v3_reg>;

vcc6-supply = <&vio_reg>;

vccio-supply = <&sys_3v3_reg>;

regulators {

regulator-max-microvolt = <3300000>;

regulator-always-on;

};

};

};

};

pinctrl_esdhc1: esdhc1grp {

VF610_PAD_PTA24__ESDHC1_CLK 0x31ef

VF610_PAD_PTA25__ESDHC1_CMD 0x31ef

VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef

bool

default AT91_PMC_UNIT && AT91_USE_OLD_CLK

config AT91_SAM9_ALT_RESET

bool

default !ARCH_AT91X40

config SOC_AT91SAM9

bool

select AT91_SAM9_TIME

select CPU_ARM926T

select GENERIC_CLOCKEVENTS

config SOC_SAMA5

bool

select AT91_SAM9_TIME

select CPU_V7

select GENERIC_CLOCKEVENTS

select USE_OF

menu "Atmel AT91 System-on-Chip"

depends on !MMU

select CPU_ARM7TDMI

select ARCH_USES_GETTIMEOFFSET

help

Select this if you are using one of Atmel's AT91X40 SoC.

if SOC_SAM_V4_V5

config SOC_AT91RM9200

bool "AT91RM9200"

select CPU_ARM920T

select GENERIC_CLOCKEVENTS

select HAVE_AT91_DBGU0

select HAVE_AT91_USB_CLK

config SOC_AT91SAM9260

bool "AT91RM9200"

select SOC_AT91RM9200

select AT91_USE_OLD_CLK

config ARCH_AT91SAM9260

bool "AT91SAM9260 or AT91SAM9XE or AT91SAM9G20"

select SOC_AT91SAM9260

select AT91_USE_OLD_CLK

config ARCH_AT91SAM9261

bool "AT91SAM9261 or AT91SAM9G10"

select SOC_AT91SAM9261

select AT91_USE_OLD_CLK

config ARCH_AT91SAM9263

bool "AT91SAM9263"

select SOC_AT91SAM9263

select AT91_USE_OLD_CLK

config ARCH_AT91SAM9RL

bool "AT91SAM9RL"

select SOC_AT91SAM9RL

select AT91_USE_OLD_CLK

config ARCH_AT91SAM9G45

bool "AT91SAM9G45"

select SOC_AT91SAM9G45

select AT91_USE_OLD_CLK

endchoice

# Makefile for the linux kernel.

#

obj-m :=

obj-n :=

obj- :=

obj-$(CONFIG_OLD_CLK_AT91) += clock.o

obj-$(CONFIG_AT91_SAM9_ALT_RESET) += at91sam9_alt_reset.o

obj-$(CONFIG_AT91_SAM9G45_RESET) += at91sam9g45_reset.o

#include "at91_aic.h"

#include "generic.h"

static const char *at91rm9200_dt_board_compat[] __initdata = {

"atmel,at91rm9200",

NULL

DT_MACHINE_START(at91rm9200_dt, "Atmel AT91RM9200 (Device Tree)")

.init_time = at91rm9200_timer_init,

.map_io = at91_map_io,

.init_early = at91rm9200_dt_initialize,

.dt_compat = at91rm9200_dt_board_compat,

MACHINE_END

at91sam926x_pit_init();

}

static const char *at91_dt_board_compat[] __initdata = {

"atmel,at91sam9",

NULL

/* Maintainer: Atmel */

.init_time = sam9_dt_timer_init,

.map_io = at91_map_io,

.init_early = at91_dt_initialize,

.dt_compat = at91_dt_board_compat,

MACHINE_END

at91sam926x_pit_init();

}

static int ksz9021rn_phy_fixup(struct phy_device *phy)

{

int value;

/* Maintainer: Atmel */

.init_time = sama5_dt_timer_init,

.map_io = at91_map_io,

.init_early = at91_dt_initialize,

.init_machine = sama5_dt_device_init,

.dt_compat = sama5_dt_board_compat,

MACHINE_END

static struct irq_domain *at91_aic_domain;

static struct device_node *at91_aic_np;

static unsigned int n_irqs = NR_AIC_IRQS;

#ifdef CONFIG_PM

void at91_irq_suspend(void)

{

}

void at91_irq_resume(void)

{

}

#else

handle_IRQ(irqnr, regs);

}

static void at91_aic_mask_irq(struct irq_data *d)

{

/* Disable interrupt on AIC */

clear_backup(d->hwirq);

}

static void at91_aic_unmask_irq(struct irq_data *d)

{

/* Enable interrupt on AIC */

set_backup(d->hwirq);

}

static void at91_aic_eoi(struct irq_data *d)

{

/*

at91_aic_write(AT91_AIC_EOICR, 0);

}

static unsigned long *at91_extern_irq;

u32 at91_get_extern_irq(void)

if (srctype < 0)

return srctype;

return 0;

}

at91_aic_write(AT91_AIC_ICCR, 0xFFFFFFFF);

}

/*

* Initialize the AIC interrupt controller.

*/

at91_pinctrl_gpio_suspend();

else

at91_gpio_suspend();

switch (state) {

/*

goto error;

}

error:

target_state = PM_SUSPEND_ON;

if (of_have_populated_dt())

at91_pinctrl_gpio_resume();

else

void __init at91_init_interrupts(unsigned int *priority)

{

/* Initialize the AIC interrupt controller */

/* Enable GPIO interrupts */

at91_gpio_irq_setup();

* along with this program; if not, write to the Free Software

* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA

*/

#include <linux/init.h>

#include <linux/sizes.h>

#include <asm/mach/map.h>

#include <asm/system_misc.h>

#include <mach/hardware.h>

#include "common.h"

/*

* This maps the generic CLPS711x registers

*/

clps711x_intc_init(CLPS711X_PHYS_BASE, SZ_16K);

}

void __init clps711x_timer_init(void)

{

}

void clps711x_restart(enum reboot_mode mode, const char *cmd)

/* drivers/irqchip/irq-clps711x.c */

void clps711x_intc_init(phys_addr_t, resource_size_t);

config SOC_IMX27

bool

select CPU_ARM926T

select IMX_HAVE_IOMUX_V1

select MXC_AVIC

config SOC_IMX5

bool

select HAVE_IMX_SRC

select MXC_TZIC

obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o

obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o

obj-$(CONFIG_HAVE_IMX_SRC) += src.o

AFLAGS_headsmp.o :=-Wa,-march=armv7-a

obj-$(CONFIG_SMP) += headsmp.o platsmp.o

obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o

obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o

obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o mach-imx6sl.o

obj-$(CONFIG_SOC_IMX6SX) += clk-imx6sx.o mach-imx6sx.o

clk[IMX6QDL_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6);

clk[IMX6QDL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8);

clk[IMX6QDL_CLK_TWD] = imx_clk_fixed_factor("twd", "arm", 1, 2);

clk[IMX6QDL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);

clk[IMX6QDL_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);

clk[IMX6QDL_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels));

clk[IMX6QDL_CLK_ASRC_SEL] = imx_clk_mux("asrc_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels));

clk[IMX6QDL_CLK_SPDIF_SEL] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels));

clk[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels));

clk[IMX6QDL_CLK_GPU3D_CORE_SEL] = imx_clk_mux("gpu3d_core_sel", base + 0x18, 4, 2, gpu3d_core_sels, ARRAY_SIZE(gpu3d_core_sels));

clk[IMX6QDL_CLK_GPU3D_SHADER_SEL] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels));

ldr r6, [r11, #0x0]

ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]

ldr r6, [r11, #0x0]

/* use r11 to store the IO address */

ldr r11, [r0, #PM_INFO_MX6Q_SRC_V_OFFSET]

static struct platform_device *devices[] __initdata = {

&msm_clock_7x30,

&msm_device_gpio_7x30,

&msm_device_uart2,

#endif

&msm_device_smd,

}

static struct msm_gpio_chip msm_gpio_banks[] = {

/* H2W pins <-> UART1 */

TROUT_GPIO_BANK("MISC2", 0x00, TROUT_GPIO_MISC2_BASE, 0x40),

#else

msm_map_common_io();

iotable_init(trout_io_desc, ARRAY_SIZE(trout_io_desc));

/* route UART3 to the "H2W" extended usb connector */

writeb(0x80, TROUT_CPLD_BASE + 0x00);

#endif

.length = MSM_SHARED_RAM_SIZE,

.type = MT_DEVICE,

},

{

/* Must be last: virtual and pfn filled in by debug_ll_addr() */

.length = SZ_4K,

* pages are peripheral interface or not.

*/

asm("mcr p15, 0, %0, c15, c2, 4" : : "r" (0));

#ifdef CONFIG_MMU

debug_ll_addr(&msm_io_desc[size - 1].pfn,

&msm_io_desc[size - 1].virtual);

config ARCH_SHMOBILE

bool

menuconfig ARCH_SHMOBILE_MULTI

bool "Renesas ARM SoCs" if ARCH_MULTI_V7

depends on MMU

config ARCH_R8A7779

bool "R-Car H1 (R8A77790)"

config ARCH_R8A7790

bool "R-Car H2 (R8A77900)"

config ARCH_R8A7791

comment "Renesas ARM SoCs Board Type"

config ARCH_SH7372

bool "SH-Mobile AP4 (SH7372)"

select ARCH_WANT_OPTIONAL_GPIOLIB

select ARM_CPU_SUSPEND if PM || CPU_IDLE

config ARCH_SH73A0

bool "SH-Mobile AG5 (R8A73A00)"

select ARCH_WANT_OPTIONAL_GPIOLIB

select ARM_GIC

select I2C

select RENESAS_INTC_IRQPIN

config ARCH_R8A73A4

bool "R-Mobile APE6 (R8A73A40)"

select ARCH_WANT_OPTIONAL_GPIOLIB

select ARM_GIC

select RENESAS_IRQC

config ARCH_R8A7740

bool "R-Mobile A1 (R8A77400)"

select ARCH_WANT_OPTIONAL_GPIOLIB

select ARM_GIC

select RENESAS_INTC_IRQPIN

config ARCH_R8A7778

bool "R-Car M1A (R8A77781)"

select ARCH_WANT_OPTIONAL_GPIOLIB

select ARM_GIC

config ARCH_R8A7779

bool "R-Car H1 (R8A77790)"

select ARCH_WANT_OPTIONAL_GPIOLIB

select ARM_GIC

config ARCH_R8A7790

bool "R-Car H2 (R8A77900)"

select ARCH_WANT_OPTIONAL_GPIOLIB

select ARM_GIC

select MIGHT_HAVE_PCI

select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE

config ARCH_R8A7791

select ARCH_WANT_OPTIONAL_GPIOLIB

select ARM_GIC

select MIGHT_HAVE_PCI

select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE

config ARCH_R7S72100

obj-y := timer.o console.o

# CPU objects

obj-$(CONFIG_ARCH_R8A73A4) += setup-r8a73a4.o

obj-$(CONFIG_ARCH_R8A7778) += setup-r8a7778.o

obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o

obj-$(CONFIG_ARCH_R7S72100) += setup-r7s72100.o

# CPU reset vector handling objects

cpu-y := platsmp.o headsmp.o

# SMP objects

smp-y := $(cpu-y)

obj-$(CONFIG_SUSPEND) += suspend.o

obj-$(CONFIG_CPU_IDLE) += cpuidle.o

obj-$(CONFIG_CPU_FREQ) += cpufreq.o

# Board objects

ifdef CONFIG_ARCH_SHMOBILE_MULTI

#define GPIO_PORT8CR IOMEM(0xe6050008)

static void __init eva_init(void)

{

struct platform_device *usb = NULL;

regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,

platform_add_devices(eva_devices,

ARRAY_SIZE(eva_devices));

if (usb)

rmobile_add_device_to_domain("A3SP", usb);

#define USCCR1 IOMEM(0xE6058144)

static void __init mackerel_init(void)

{

{ "A4LC", &lcdc_device, },

{ "A4LC", &hdmi_lcdc_device, },

{ "A4LC", &meram_device, },

static struct rmobile_pm_domain r8a7740_pm_domains[] = {

{

.genpd.name = "A4S",

.bit_shift = 10,

.gov = &pm_domain_always_on_gov,

.no_debug = true,

.suspend = r8a7740_pd_a4s_suspend,

.genpd.name = "A3SP",

.bit_shift = 11,

.gov = &pm_domain_always_on_gov,

.no_debug = true,

.suspend = r8a7740_pd_a3sp_suspend,

},

};

void __init r8a7740_init_pm_domains(void)

#define SYSCISR_RETRIES 1000

#define SYSCISR_DELAY_US 1

static void __iomem *rcar_sysc_base;

static DEFINE_SPINLOCK(rcar_sysc_lock); /* SMP CPUs + I/O devices */

return rcar_sysc_base;

}

#define PSTR_RETRIES 100

#define PSTR_DELAY_US 10

static int rmobile_pd_power_down(struct generic_pm_domain *genpd)

{

struct rmobile_pm_domain *rmobile_pd = to_rmobile_pd(genpd);

rmobile_add_device_to_domain_td(data[j].domain_name,

data[j].pdev, &latencies);

}

struct platform_device *pdev;

};

extern void rmobile_init_domains(struct rmobile_pm_domain domains[], int num);

extern void rmobile_add_device_to_domain_td(const char *domain_name,

struct platform_device *pdev,

static inline void rmobile_add_devices_to_domains(struct pm_domain_device d[],

int size) {}

#endif /* PM_RMOBILE_H */

void __init r8a7740_add_standard_devices(void)

{

/* I2C work-around */

r8a7740_i2c_workaround(&i2c0_device);

r8a7740_i2c_workaround(&i2c1_device);

ARRAY_SIZE(r8a7740_late_devices));

/* add devices to PM domain */

}

void __init r8a7740_add_early_devices(void)

void __init sh7372_add_standard_devices(void)

{

{ "A3RV", &vpu_device, },

{ "A4MP", &spu0_device, },

{ "A4MP", &spu1_device, },

#include <linux/clk-provider.h>

#include <linux/clocksource.h>

#include <linux/init.h>

#include <asm/mach/arch.h>

static const char * const sunxi_board_dt_compat[] = {

"allwinner,sun4i-a10",

};

DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)")

.dt_compat = sunxi_board_dt_compat,

MACHINE_END

static const char * const sun6i_board_dt_compat[] = {

};

DT_MACHINE_START(SUN7I_DT, "Allwinner sun7i (A20) Family")

.dt_compat = sun7i_board_dt_compat,

MACHINE_END

static const char * const sun8i_board_dt_compat[] = {

# The byte offset of the kernel image in RAM from the start of RAM.

ifeq ($(CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET), y)

else

TEXT_OFFSET := 0x00080000

endif

CONFIG_BLK_DEV_SD=y

# CONFIG_SCSI_LOWLEVEL is not set

CONFIG_ATA=y

CONFIG_PATA_PLATFORM=y

CONFIG_PATA_OF_PLATFORM=y

CONFIG_NETDEVICES=y

CONFIG_VIRTIO_NET=y

CONFIG_SMC91X=y

CONFIG_SMSC911X=y

# CONFIG_WLAN is not set

CONFIG_INPUT_EVDEV=y

# CONFIG_SERIO_SERPORT is not set

#define __ASM_SPARSEMEM_H

#ifdef CONFIG_SPARSEMEM

#define SECTION_SIZE_BITS 30

#endif

#define __ARM_NR_compat_cacheflush (__ARM_NR_COMPAT_BASE+2)

#define __ARM_NR_compat_set_tls (__ARM_NR_COMPAT_BASE+5)

#endif

#define __ARCH_WANT_SYS_CLONE

__SYSCALL(__NR_sched_getattr, sys_sched_getattr)

#define __NR_renameat2 382

__SYSCALL(__NR_renameat2, sys_renameat2)

if (l1ip != ICACHE_POLICY_PIPT)

set_bit(ICACHEF_ALIASING, &__icache_flags);

set_bit(ICACHEF_AIVIVT, &__icache_flags);

pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str[l1ip], cpu);

if (uefi_debug)

pr_cont("\n");

}

}

efi_native_runtime_setup();

set_bit(EFI_RUNTIME_SERVICES, &efi.flags);

return 0;

err_unmap:

#define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET)

#error PAGE_OFFSET must be at least 2MB aligned

#error TEXT_OFFSET must be less than 2MB

#endif

if (test_thread_flag(TIF_SYSCALL_TRACEPOINT))

trace_sys_enter(regs, regs->syscallno);

audit_syscall_entry(syscall_get_arch(), regs->syscallno,

regs->orig_x0, regs->regs[1], regs->regs[2], regs->regs[3]);

return regs->syscallno;

}

asmlinkage void syscall_trace_exit(struct pt_regs *regs)

{

audit_syscall_exit(regs);

if (test_thread_flag(TIF_SYSCALL_TRACEPOINT))

trace_sys_exit(regs, regs_return_value(regs));

#include <linux/of_fdt.h>

#include <linux/dma-mapping.h>

#include <linux/dma-contiguous.h>

#include <asm/fixmap.h>

#include <asm/sections.h>

memblock_reserve(__virt_to_phys(initrd_start), initrd_end - initrd_start);

#endif

/* 4GB maximum for 32-bit only capable devices */

if (IS_ENABLED(CONFIG_ZONE_DMA))

#define KSTK_EIP(tsk) ((tsk)->thread.frame0->pc)

#define KSTK_ESP(tsk) ((tsk)->thread.frame0->sp)

/* data cache prefetch */

#define ARCH_HAS_PREFETCH

/*

* The following defines stop scripts/checksyscalls.sh from complaining about

#define __NR_sched_getattr 1337

#define __NR_renameat2 1338

#define __NR_getrandom 1339

#endif /* _UAPI_ASM_IA64_UNISTD_H */

data8 sys_sched_getattr

data8 sys_renameat2

data8 sys_getrandom

.org sys_call_table + 8*NR_syscalls // guard against failures to increase NR_syscalls

#endif /* __IA64_ASM_PARAVIRTUALIZED_NATIVE */

#define __NR_sched_setattr 381

#define __NR_sched_getattr 382

#define __NR_renameat2 383

#endif /* _UAPI_ASM_MICROBLAZE_UNISTD_H */

.long sys_sched_setattr

.long sys_sched_getattr

.long sys_renameat2

pr_warn("DB1200: cant get I2C close to 50MHz\n");

else

clk_set_rate(c, pfc);

clk_put(c);

}

}

/* Audio PSC clock is supplied externally. (FIXME: platdata!!) */

__raw_writel(PSC_SEL_CLK_SERCLK,

(void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);

wmb();

switch (bcm47xx_bus_type) {

#ifdef CONFIG_BCM47XX_SSB

case BCM47XX_BUS_TYPE_SSB:

break;

#endif

#ifdef CONFIG_BCM47XX_BCMA

case BCM47XX_BUS_TYPE_BCMA:

break;

#endif

}

static int octeon_uart;

extern asmlinkage void handle_int(void);

/**

* Return non zero if we are currently running in the Octeon simulator

octeon_kill_core(NULL);

}

/**

* Return a string representing the system type

*

*/

const char *octeon_board_type_string(void)

{

}

const char *get_system_type(void)

#endif

#define GICBIS(reg, mask, bits) \

do { u32 data; \

data &= ~(mask); \

data |= ((bits) & (mask)); \

GICWRITE((reg), data); \

#define irq_canonicalize(irq) (irq) /* Sane hardware, sane code ... */

#endif

extern void do_IRQ(unsigned int irq);

extern void arch_init_irq(void);

#ifndef __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H

#define __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H

/*

* Prepare segments for EVA boot:

*

* This is in case the processor boots in legacy configuration

* (SI_EVAReset is de-asserted and CONFIG5.K == 0)

*

* ========================= Mappings =============================

* Virtual memory Physical memory Mapping

* 0x00000000 - 0x7fffffff 0x80000000 - 0xfffffffff MUSUK (kuseg)

*

*

* Lowmem is expanded to 2GB

*/

/*

* Get Config.K0 value and use it to program

* the segmentation registers

*/

andi t1, 0x7 /* CCA */

move t2, t1

ins t2, t1, 16, 3

mtc0 t0, $16, 5

sync

jal mips_ihb

.endm

.macro kernel_entry_setup

sll t0, t0, 6 /* SC bit */

bgez t0, 9f

b 0f

9:

/* Assume we came from YAMON... */

#ifdef CONFIG_EVA

sync

ehb

#endif

.endm

#include <asm/mach-netlogic/multi-node.h>

#include <asm-generic/topology.h>

#endif /* _ASM_MACH_NETLOGIC_TOPOLOGY_H */

} \

} while(0)

#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)

#define pte_none(pte) (!(((pte).pte_low | (pte).pte_high) & ~_PAGE_GLOBAL))

}

}

}

static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)

{

}

#endif

}

static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)

{

extern void __update_tlb(struct vm_area_struct *vma, unsigned long address,

pte_t pte);

static inline void update_mmu_cache(struct vm_area_struct *vma,

unsigned long address, pte_t *ptep)

{

pte_t pte = *ptep;

__update_tlb(vma, address, pte);

}

static inline void update_mmu_cache_pmd(struct vm_area_struct *vma,

{

int arch = EM_MIPS;

#ifdef CONFIG_64BIT

arch |= __AUDIT_ARCH_64BIT;

#endif

#if defined(__LITTLE_ENDIAN)

arch |= __AUDIT_ARCH_LE;

#include <asm/asm-offsets.h>

#include <asm/asmmacro.h>

#include <asm/cacheops.h>

#include <asm/mipsregs.h>

#include <asm/mipsmtregs.h>

#include <asm/pm.h>

1: jal mips_cps_core_init

nop

/*

* Boot any other VPEs within this core that should be online, and

* deactivate this VPE if it should be offline.

if (mipspmu.irq >= 0) {

/* Request my own irq handler. */

err = request_irq(mipspmu.irq, mipsxx_pmu_handle_irq,

"mips_perf_pmu", NULL);

if (err) {

pr_warning("Unable to request IRQ%d for MIPS "

move s0, t2 # Save syscall pointer

move a0, sp

/*

* where the real syscall number is in a0

* note: NR_syscall is the first O32 syscall but the macro is

* only defined when compiling with -mabi=32 (CONFIG_32BIT)

* therefore __NR_O32_Linux is used (4000)

*/

1: jal syscall_trace_enter

static int loongson_cu2_call(struct notifier_block *nfb, unsigned long action,

void *data)

{

int fr = !test_thread_flag(TIF_32BIT_FPREGS);

switch (action) {

case CU2_EXCEPTION:

preempt_disable();

if (!fr)

set_c0_status(ST0_CU1 | ST0_CU2);

else

KSTK_STATUS(current) |= ST0_FR;

else

KSTK_STATUS(current) &= ~ST0_FR;

set_thread_flag(TIF_USEDFPU);

if (!used_math()) {

_init_fpu();

#include <asm/page.h>

#include <asm/pgalloc.h>

#include <asm/sections.h>

#include <linux/irq.h>

#include <asm/bootinfo.h>

#include <asm/mc146818-time.h>

EXPORT_SYMBOL(__flush_anon_page);

{

struct page *page;

if (unlikely(!pfn_valid(pfn)))

return;

page = pfn_to_page(pfn);

if (page_mapping(page) && Page_dcache_dirty(page)) {

ClearPageDcacheDirty(page);

}

}

unsigned long _page_cachable_default;

EXPORT_SYMBOL(_page_cachable_default);

/* otherwise look in the environment */

memsize_str = fw_getenv("memsize");

if (eva) {

/* Look for ememsize for EVA */

ememsize_str = fw_getenv("ememsize");

}

if (!memsize && !ememsize) {

pr_warn("memsize not set in YAMON, set to default (32Mb)\n");

* the range 40-71.

*/

{

u32 pending;

ri = kmalloc(sizeof(struct kvm_rma_info), GFP_KERNEL);

if (!ri)

return NULL;

if (!page)

goto err_out;

atomic_set(&ri->use_count, 1);

{

unsigned long align_pages = HPT_ALIGN_PAGES;

/* Old CPUs require HPT aligned on a multiple of its size */

if (!cpu_has_feature(CPU_FTR_ARCH_206))

align_pages = nr_pages;

}

EXPORT_SYMBOL_GPL(kvm_alloc_hpt);

#

config CPU_SH2

bool

config CPU_SH2A

bool

bool

select CPU_HAS_INTEVT

select CPU_HAS_SR_RB

select SYS_SUPPORTS_SH_TMU

config CPU_SH4

select CPU_HAS_INTEVT

select CPU_HAS_SR_RB

select CPU_HAS_FPU if !CPU_SH4AL_DSP

select SYS_SUPPORTS_SH_TMU

select SYS_SUPPORTS_HUGETLBFS if MMU

#define KVM_REFILL_PAGES 25

#define KVM_MAX_CPUID_ENTRIES 80

#define KVM_NR_FIXED_MTRR_REGION 88

#define ASYNC_PF_PER_VCPU 64

sysenter_badsys:

movl $-ENOSYS,%eax

jmp sysenter_after_call

CFI_ENDPROC

.macro FIXUP_ESPFIX_STACK

goto exception;

break;

case VCPU_SREG_CS:

if (!(seg_desc.type & 8))

goto exception;

ctxt->execute = opcode.u.execute;

if (unlikely(ctxt->d &

/*

* These are copied unconditionally here, and checked unconditionally

* in x86_emulate_insn.

if (ctxt->d & NotImpl)

return EMULATION_FAILED;

if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))

ctxt->op_bytes = 8;

if (cpumask_test_cpu(cpu, mm_cpumask(active_mm))) {

cpumask_clear_cpu(cpu, mm_cpumask(active_mm));

load_cr3(swapper_pg_dir);

}

}

EXPORT_SYMBOL_GPL(leave_mm);

*

* This is in units of pages.

*/

void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start,

unsigned long end, unsigned long vmflag)