diff options
Diffstat (limited to 'arch')
815 files changed, 23979 insertions, 21676 deletions
diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig index 56a4df952fb0..22e58a99f38b 100644 --- a/arch/alpha/Kconfig +++ b/arch/alpha/Kconfig @@ -477,7 +477,7 @@ config ALPHA_BROKEN_IRQ_MASK config VGA_HOSE bool - depends on ALPHA_GENERIC || ALPHA_TITAN || ALPHA_MARVEL || ALPHA_TSUNAMI + depends on VGA_CONSOLE && (ALPHA_GENERIC || ALPHA_TITAN || ALPHA_MARVEL || ALPHA_TSUNAMI) default y help Support VGA on an arbitrary hose; needed for several platforms diff --git a/arch/alpha/include/asm/atomic.h b/arch/alpha/include/asm/atomic.h index f62251e82ffa..3bb7ffeae3bc 100644 --- a/arch/alpha/include/asm/atomic.h +++ b/arch/alpha/include/asm/atomic.h @@ -3,6 +3,7 @@ #include <linux/types.h> #include <asm/barrier.h> +#include <asm/cmpxchg.h> /* * Atomic operations that C can't guarantee us. Useful for @@ -168,73 +169,6 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v) return result; } -/* - * Atomic exchange routines. - */ - -#define __ASM__MB -#define ____xchg(type, args...) __xchg ## type ## _local(args) -#define ____cmpxchg(type, args...) __cmpxchg ## type ## _local(args) -#include <asm/xchg.h> - -#define xchg_local(ptr,x) \ - ({ \ - __typeof__(*(ptr)) _x_ = (x); \ - (__typeof__(*(ptr))) __xchg_local((ptr), (unsigned long)_x_, \ - sizeof(*(ptr))); \ - }) - -#define cmpxchg_local(ptr, o, n) \ - ({ \ - __typeof__(*(ptr)) _o_ = (o); \ - __typeof__(*(ptr)) _n_ = (n); \ - (__typeof__(*(ptr))) __cmpxchg_local((ptr), (unsigned long)_o_, \ - (unsigned long)_n_, \ - sizeof(*(ptr))); \ - }) - -#define cmpxchg64_local(ptr, o, n) \ - ({ \ - BUILD_BUG_ON(sizeof(*(ptr)) != 8); \ - cmpxchg_local((ptr), (o), (n)); \ - }) - -#ifdef CONFIG_SMP -#undef __ASM__MB -#define __ASM__MB "\tmb\n" -#endif -#undef ____xchg -#undef ____cmpxchg -#define ____xchg(type, args...) __xchg ##type(args) -#define ____cmpxchg(type, args...) __cmpxchg ##type(args) -#include <asm/xchg.h> - -#define xchg(ptr,x) \ - ({ \ - __typeof__(*(ptr)) _x_ = (x); \ - (__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_, \ - sizeof(*(ptr))); \ - }) - -#define cmpxchg(ptr, o, n) \ - ({ \ - __typeof__(*(ptr)) _o_ = (o); \ - __typeof__(*(ptr)) _n_ = (n); \ - (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \ - (unsigned long)_n_, sizeof(*(ptr)));\ - }) - -#define cmpxchg64(ptr, o, n) \ - ({ \ - BUILD_BUG_ON(sizeof(*(ptr)) != 8); \ - cmpxchg((ptr), (o), (n)); \ - }) - -#undef __ASM__MB -#undef ____cmpxchg - -#define __HAVE_ARCH_CMPXCHG 1 - #define atomic64_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), old, new)) #define atomic64_xchg(v, new) (xchg(&((v)->counter), new)) diff --git a/arch/alpha/include/asm/cmpxchg.h b/arch/alpha/include/asm/cmpxchg.h new file mode 100644 index 000000000000..429e8cd0d78e --- /dev/null +++ b/arch/alpha/include/asm/cmpxchg.h @@ -0,0 +1,71 @@ +#ifndef _ALPHA_CMPXCHG_H +#define _ALPHA_CMPXCHG_H + +/* + * Atomic exchange routines. + */ + +#define __ASM__MB +#define ____xchg(type, args...) __xchg ## type ## _local(args) +#define ____cmpxchg(type, args...) __cmpxchg ## type ## _local(args) +#include <asm/xchg.h> + +#define xchg_local(ptr, x) \ +({ \ + __typeof__(*(ptr)) _x_ = (x); \ + (__typeof__(*(ptr))) __xchg_local((ptr), (unsigned long)_x_, \ + sizeof(*(ptr))); \ +}) + +#define cmpxchg_local(ptr, o, n) \ +({ \ + __typeof__(*(ptr)) _o_ = (o); \ + __typeof__(*(ptr)) _n_ = (n); \ + (__typeof__(*(ptr))) __cmpxchg_local((ptr), (unsigned long)_o_, \ + (unsigned long)_n_, \ + sizeof(*(ptr))); \ +}) + +#define cmpxchg64_local(ptr, o, n) \ +({ \ + BUILD_BUG_ON(sizeof(*(ptr)) != 8); \ + cmpxchg_local((ptr), (o), (n)); \ +}) + +#ifdef CONFIG_SMP +#undef __ASM__MB +#define __ASM__MB "\tmb\n" +#endif +#undef ____xchg +#undef ____cmpxchg +#define ____xchg(type, args...) __xchg ##type(args) +#define ____cmpxchg(type, args...) __cmpxchg ##type(args) +#include <asm/xchg.h> + +#define xchg(ptr, x) \ +({ \ + __typeof__(*(ptr)) _x_ = (x); \ + (__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_, \ + sizeof(*(ptr))); \ +}) + +#define cmpxchg(ptr, o, n) \ +({ \ + __typeof__(*(ptr)) _o_ = (o); \ + __typeof__(*(ptr)) _n_ = (n); \ + (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \ + (unsigned long)_n_, sizeof(*(ptr)));\ +}) + +#define cmpxchg64(ptr, o, n) \ +({ \ + BUILD_BUG_ON(sizeof(*(ptr)) != 8); \ + cmpxchg((ptr), (o), (n)); \ +}) + +#undef __ASM__MB +#undef ____cmpxchg + +#define __HAVE_ARCH_CMPXCHG 1 + +#endif /* _ALPHA_CMPXCHG_H */ diff --git a/arch/alpha/include/asm/rtc.h b/arch/alpha/include/asm/rtc.h index 1f7fba671ae6..d70408d36677 100644 --- a/arch/alpha/include/asm/rtc.h +++ b/arch/alpha/include/asm/rtc.h @@ -1,14 +1,10 @@ #ifndef _ALPHA_RTC_H #define _ALPHA_RTC_H -#if defined(CONFIG_ALPHA_GENERIC) +#if defined(CONFIG_ALPHA_MARVEL) && defined(CONFIG_SMP) \ + || defined(CONFIG_ALPHA_GENERIC) # define get_rtc_time alpha_mv.rtc_get_time # define set_rtc_time alpha_mv.rtc_set_time -#else -# if defined(CONFIG_ALPHA_MARVEL) && defined(CONFIG_SMP) -# define get_rtc_time marvel_get_rtc_time -# define set_rtc_time marvel_set_rtc_time -# endif #endif #include <asm-generic/rtc.h> diff --git a/arch/alpha/include/asm/xchg.h b/arch/alpha/include/asm/xchg.h index 1d1b436fbff2..0ca9724597c1 100644 --- a/arch/alpha/include/asm/xchg.h +++ b/arch/alpha/include/asm/xchg.h @@ -1,10 +1,10 @@ -#ifndef _ALPHA_ATOMIC_H +#ifndef _ALPHA_CMPXCHG_H #error Do not include xchg.h directly! #else /* * xchg/xchg_local and cmpxchg/cmpxchg_local share the same code * except that local version do not have the expensive memory barrier. - * So this file is included twice from asm/system.h. + * So this file is included twice from asm/cmpxchg.h. */ /* diff --git a/arch/alpha/kernel/core_tsunami.c b/arch/alpha/kernel/core_tsunami.c index 5e7c28f92f19..61893d7bdda5 100644 --- a/arch/alpha/kernel/core_tsunami.c +++ b/arch/alpha/kernel/core_tsunami.c @@ -11,6 +11,7 @@ #include <asm/core_tsunami.h> #undef __EXTERN_INLINE +#include <linux/module.h> #include <linux/types.h> #include <linux/pci.h> #include <linux/sched.h> diff --git a/arch/alpha/kernel/sys_marvel.c b/arch/alpha/kernel/sys_marvel.c index 14a4b6a7cf59..407accc80877 100644 --- a/arch/alpha/kernel/sys_marvel.c +++ b/arch/alpha/kernel/sys_marvel.c @@ -317,7 +317,7 @@ marvel_init_irq(void) } static int -marvel_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +marvel_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { struct pci_controller *hose = dev->sysdata; struct io7_port *io7_port = hose->sysdata; diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index cf006d40342c..554ec1dd89d4 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -11,6 +11,7 @@ config ARM select HAVE_OPROFILE if (HAVE_PERF_EVENTS) select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL select HAVE_ARCH_KGDB + select HAVE_ARCH_TRACEHOOK select HAVE_KPROBES if !XIP_KERNEL select HAVE_KRETPROBES if (HAVE_KPROBES) select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) @@ -30,10 +31,12 @@ config ARM select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)) select HAVE_C_RECORDMCOUNT select HAVE_GENERIC_HARDIRQS + select HARDIRQS_SW_RESEND + select GENERIC_IRQ_PROBE select GENERIC_IRQ_SHOW select CPU_PM if (SUSPEND || CPU_IDLE) select GENERIC_PCI_IOMAP - select HAVE_BPF_JIT if NET + select HAVE_BPF_JIT help The ARM series is a line of low-power-consumption RISC chip designs licensed by ARM Ltd and targeted at embedded applications and @@ -126,14 +129,6 @@ config TRACE_IRQFLAGS_SUPPORT bool default y -config HARDIRQS_SW_RESEND - bool - default y - -config GENERIC_IRQ_PROBE - bool - default y - config GENERIC_LOCKBREAK bool default y @@ -280,6 +275,7 @@ config ARCH_INTEGRATOR select NEED_MACH_IO_H select NEED_MACH_MEMORY_H select SPARSE_IRQ + select MULTI_IRQ_HANDLER help Support for ARM's Integrator platform. @@ -632,7 +628,6 @@ config ARCH_MMP select CLKDEV_LOOKUP select GENERIC_CLOCKEVENTS select GPIO_PXA - select TICK_ONESHOT select PLAT_PXA select SPARSE_IRQ select GENERIC_ALLOCATOR @@ -716,7 +711,6 @@ config ARCH_PXA select ARCH_REQUIRE_GPIOLIB select GENERIC_CLOCKEVENTS select GPIO_PXA - select TICK_ONESHOT select PLAT_PXA select SPARSE_IRQ select AUTO_ZRELADDR @@ -783,7 +777,6 @@ config ARCH_SA1100 select CPU_FREQ select GENERIC_CLOCKEVENTS select CLKDEV_LOOKUP - select TICK_ONESHOT select ARCH_REQUIRE_GPIOLIB select HAVE_IDE select NEED_MACH_MEMORY_H @@ -1186,6 +1179,15 @@ if !MMU source "arch/arm/Kconfig-nommu" endif +config ARM_ERRATA_326103 + bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" + depends on CPU_V6 + help + Executing a SWP instruction to read-only memory does not set bit 11 + of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to + treat the access as a read, preventing a COW from occurring and + causing the faulting task to livelock. + config ARM_ERRATA_411920 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" depends on CPU_V6 || CPU_V6K @@ -1543,10 +1545,15 @@ config HAVE_ARM_SCU help This option enables support for the ARM system coherency unit +config ARM_ARCH_TIMER + bool "Architected timer support" + depends on CPU_V7 + help + This option enables support for the ARM architected timer + config HAVE_ARM_TWD bool depends on SMP - select TICK_ONESHOT help This options enables support for the ARM timer and watchdog unit diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 047a20780fc1..aaf96bccd4a0 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -70,8 +70,6 @@ arch-$(CONFIG_CPU_32v4) :=-D__LINUX_ARM_ARCH__=4 -march=armv4 arch-$(CONFIG_CPU_32v3) :=-D__LINUX_ARM_ARCH__=3 -march=armv3 # This selects how we optimise for the processor. -tune-$(CONFIG_CPU_ARM610) :=-mtune=arm610 -tune-$(CONFIG_CPU_ARM710) :=-mtune=arm710 tune-$(CONFIG_CPU_ARM7TDMI) :=-mtune=arm7tdmi tune-$(CONFIG_CPU_ARM720T) :=-mtune=arm7tdmi tune-$(CONFIG_CPU_ARM740T) :=-mtune=arm7tdmi diff --git a/arch/arm/boot/compressed/atags_to_fdt.c b/arch/arm/boot/compressed/atags_to_fdt.c index 6ce11c481178..797f04bedb47 100644 --- a/arch/arm/boot/compressed/atags_to_fdt.c +++ b/arch/arm/boot/compressed/atags_to_fdt.c @@ -77,6 +77,8 @@ int atags_to_fdt(void *atag_list, void *fdt, int total_space) } else if (atag->hdr.tag == ATAG_MEM) { if (memcount >= sizeof(mem_reg_property)/4) continue; + if (!atag->u.mem.size) + continue; mem_reg_property[memcount++] = cpu_to_fdt32(atag->u.mem.start); mem_reg_property[memcount++] = cpu_to_fdt32(atag->u.mem.size); } else if (atag->hdr.tag == ATAG_INITRD2) { diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index 5f6045f1766c..b8c64b80bafc 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -273,7 +273,7 @@ restart: adr r0, LC0 add r0, r0, #0x100 mov r1, r6 sub r2, sp, r6 - blne atags_to_fdt + bleq atags_to_fdt ldmfd sp!, {r0-r3, ip, lr} sub sp, sp, #0x10000 @@ -567,6 +567,12 @@ __armv3_mpu_cache_on: mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 mov pc, lr +#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH +#define CB_BITS 0x08 +#else +#define CB_BITS 0x0c +#endif + __setup_mmu: sub r3, r4, #16384 @ Page directory size bic r3, r3, #0xff @ Align the pointer bic r3, r3, #0x3f00 @@ -578,17 +584,14 @@ __setup_mmu: sub r3, r4, #16384 @ Page directory size mov r9, r0, lsr #18 mov r9, r9, lsl #18 @ start of RAM add r10, r9, #0x10000000 @ a reasonable RAM size - mov r1, #0x12 - orr r1, r1, #3 << 10 + mov r1, #0x12 @ XN|U + section mapping + orr r1, r1, #3 << 10 @ AP=11 add r2, r3, #16384 1: cmp r1, r9 @ if virt > start of RAM -#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH - orrhs r1, r1, #0x08 @ set cacheable -#else - orrhs r1, r1, #0x0c @ set cacheable, bufferable -#endif - cmp r1, r10 @ if virt > end of RAM - bichs r1, r1, #0x0c @ clear cacheable, bufferable + cmphs r10, r1 @ && end of RAM > virt + bic r1, r1, #0x1c @ clear XN|U + C + B + orrlo r1, r1, #0x10 @ Set XN|U for non-RAM + orrhs r1, r1, r6 @ set RAM section settings str r1, [r0], #4 @ 1:1 mapping add r1, r1, #1048576 teq r0, r2 @@ -599,7 +602,7 @@ __setup_mmu: sub r3, r4, #16384 @ Page directory size * so there is no map overlap problem for up to 1 MB compressed kernel. * If the execution is in RAM then we would only be duplicating the above. */ - mov r1, #0x1e + orr r1, r6, #0x04 @ ensure B is set for this orr r1, r1, #3 << 10 mov r2, pc mov r2, r2, lsr #20 @@ -620,6 +623,7 @@ __arm926ejs_mmu_cache_on: __armv4_mmu_cache_on: mov r12, lr #ifdef CONFIG_MMU + mov r6, #CB_BITS | 0x12 @ U bl __setup_mmu mov r0, #0 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer @@ -641,6 +645,7 @@ __armv7_mmu_cache_on: #ifdef CONFIG_MMU mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0 tst r11, #0xf @ VMSA + movne r6, #CB_BITS | 0x02 @ !XN blne __setup_mmu mov r0, #0 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer @@ -655,7 +660,7 @@ __armv7_mmu_cache_on: orr r0, r0, #1 << 25 @ big-endian page tables #endif orrne r0, r0, #1 @ MMU enabled - movne r1, #-1 + movne r1, #0xfffffffd @ domain 0 = client mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer mcrne p15, 0, r1, c3, c0, 0 @ load domain access control #endif @@ -668,6 +673,7 @@ __armv7_mmu_cache_on: __fa526_cache_on: mov r12, lr + mov r6, #CB_BITS | 0x12 @ U bl __setup_mmu mov r0, #0 mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache @@ -680,18 +686,6 @@ __fa526_cache_on: mcr p15, 0, r0, c8, c7, 0 @ flush UTLB mov pc, r12 -__arm6_mmu_cache_on: - mov r12, lr - bl __setup_mmu - mov r0, #0 - mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 - mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 - mov r0, #0x30 - bl __common_mmu_cache_on - mov r0, #0 - mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 - mov pc, r12 - __common_mmu_cache_on: #ifndef CONFIG_THUMB2_KERNEL #ifndef DEBUG @@ -756,16 +750,6 @@ call_cache_fn: adr r12, proc_types .align 2 .type proc_types,#object proc_types: - .word 0x41560600 @ ARM6/610 - .word 0xffffffe0 - W(b) __arm6_mmu_cache_off @ works, but slow - W(b) __arm6_mmu_cache_off - mov pc, lr - THUMB( nop ) -@ b __arm6_mmu_cache_on @ untested -@ b __arm6_mmu_cache_off -@ b __armv3_mmu_cache_flush - .word 0x00000000 @ old ARM ID .word 0x0000f000 mov pc, lr @@ -777,8 +761,10 @@ proc_types: .word 0x41007000 @ ARM7/710 .word 0xfff8fe00 - W(b) __arm7_mmu_cache_off - W(b) __arm7_mmu_cache_off + mov pc, lr + THUMB( nop ) + mov pc, lr + THUMB( nop ) mov pc, lr THUMB( nop ) @@ -977,21 +963,6 @@ __armv7_mmu_cache_off: mcr p15, 0, r0, c7, c5, 4 @ ISB mov pc, r12 -__arm6_mmu_cache_off: - mov r0, #0x00000030 @ ARM6 control reg. - b __armv3_mmu_cache_off - -__arm7_mmu_cache_off: - mov r0, #0x00000070 @ ARM7 control reg. - b __armv3_mmu_cache_off - -__armv3_mmu_cache_off: - mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off - mov r0, #0 - mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 - mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 - mov pc, lr - /* * Clean and flush the cache to maintain consistency. * diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi index 799ad1889b51..773ef484037a 100644 --- a/arch/arm/boot/dts/at91sam9g20.dtsi +++ b/arch/arm/boot/dts/at91sam9g20.dtsi @@ -55,7 +55,6 @@ #interrupt-cells = <2>; compatible = "atmel,at91rm9200-aic"; interrupt-controller; - interrupt-parent; reg = <0xfffff000 0x200>; }; diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index 9e6eb6ecea0e..c8042147eaa2 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -56,7 +56,6 @@ #interrupt-cells = <2>; compatible = "atmel,at91rm9200-aic"; interrupt-controller; - interrupt-parent; reg = <0xfffff000 0x200>; }; diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index 70ab3a4e026f..dd4ed748469a 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -54,7 +54,6 @@ #interrupt-cells = <2>; compatible = "atmel,at91rm9200-aic"; interrupt-controller; - interrupt-parent; reg = <0xfffff000 0x200>; }; diff --git a/arch/arm/boot/dts/db8500.dtsi b/arch/arm/boot/dts/db8500.dtsi index d73dce645667..14bc30705099 100644 --- a/arch/arm/boot/dts/db8500.dtsi +++ b/arch/arm/boot/dts/db8500.dtsi @@ -24,7 +24,6 @@ #interrupt-cells = <3>; #address-cells = <1>; interrupt-controller; - interrupt-parent; reg = <0xa0411000 0x1000>, <0xa0410100 0x100>; }; diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts index 37c0ff9c8b90..83e72294aefb 100644 --- a/arch/arm/boot/dts/highbank.dts +++ b/arch/arm/boot/dts/highbank.dts @@ -89,7 +89,6 @@ #size-cells = <0>; #address-cells = <1>; interrupt-controller; - interrupt-parent; reg = <0xfff11000 0x1000>, <0xfff10100 0x100>; }; diff --git a/arch/arm/boot/dts/msm8660-surf.dts b/arch/arm/boot/dts/msm8660-surf.dts index 15ded0deaa79..45bc4bb04e57 100644 --- a/arch/arm/boot/dts/msm8660-surf.dts +++ b/arch/arm/boot/dts/msm8660-surf.dts @@ -10,7 +10,7 @@ intc: interrupt-controller@02080000 { compatible = "qcom,msm-8660-qgic"; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <3>; reg = < 0x02080000 0x1000 >, < 0x02081000 0x1000 >; }; @@ -19,6 +19,6 @@ compatible = "qcom,msm-hsuart", "qcom,msm-uart"; reg = <0x19c40000 0x1000>, <0x19c00000 0x1000>; - interrupts = <195>; + interrupts = <0 195 0x0>; }; }; diff --git a/arch/arm/boot/dts/versatile-ab.dts b/arch/arm/boot/dts/versatile-ab.dts index 0b32925f2147..e2fe3195c0d1 100644 --- a/arch/arm/boot/dts/versatile-ab.dts +++ b/arch/arm/boot/dts/versatile-ab.dts @@ -173,7 +173,7 @@ mmc@5000 { compatible = "arm,primecell"; reg = < 0x5000 0x1000>; - interrupts = <22>; + interrupts = <22 34>; }; kmi@6000 { compatible = "arm,pl050", "arm,primecell"; diff --git a/arch/arm/boot/dts/versatile-pb.dts b/arch/arm/boot/dts/versatile-pb.dts index 166461073b78..7e8175269064 100644 --- a/arch/arm/boot/dts/versatile-pb.dts +++ b/arch/arm/boot/dts/versatile-pb.dts @@ -41,7 +41,7 @@ mmc@b000 { compatible = "arm,primecell"; reg = <0xb000 0x1000>; - interrupts = <23>; + interrupts = <23 34>; }; }; }; diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c index dcb13494ca0d..c4110d1b1f2d 100644 --- a/arch/arm/common/it8152.c +++ b/arch/arm/common/it8152.c @@ -222,7 +222,7 @@ static int it8152_pci_write_config(struct pci_bus *bus, return PCIBIOS_SUCCESSFUL; } -static struct pci_ops it8152_ops = { +struct pci_ops it8152_ops = { .read = it8152_pci_read_config, .write = it8152_pci_write_config, }; @@ -346,9 +346,4 @@ void pcibios_set_master(struct pci_dev *dev) } -struct pci_bus * __init it8152_pci_scan_bus(int nr, struct pci_sys_data *sys) -{ - return pci_scan_root_bus(NULL, nr, &it8152_ops, sys, &sys->resources); -} - EXPORT_SYMBOL(dma_set_coherent_mask); diff --git a/arch/arm/common/via82c505.c b/arch/arm/common/via82c505.c index 1171a5010aea..6cb362e56d29 100644 --- a/arch/arm/common/via82c505.c +++ b/arch/arm/common/via82c505.c @@ -51,7 +51,7 @@ via82c505_write_config(struct pci_bus *bus, unsigned int devfn, int where, return PCIBIOS_SUCCESSFUL; } -static struct pci_ops via82c505_ops = { +struct pci_ops via82c505_ops = { .read = via82c505_read_config, .write = via82c505_write_config, }; @@ -81,12 +81,3 @@ int __init via82c505_setup(int nr, struct pci_sys_data *sys) { return (nr == 0); } - -struct pci_bus * __init via82c505_scan_bus(int nr, struct pci_sys_data *sysdata) -{ - if (nr == 0) - return pci_scan_root_bus(NULL, 0, &via82c505_ops, sysdata, - &sysdata->resources); - - return NULL; -} diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c index 7a66311f3066..e0d538803cc3 100644 --- a/arch/arm/common/vic.c +++ b/arch/arm/common/vic.c @@ -39,6 +39,7 @@ * struct vic_device - VIC PM device * @irq: The IRQ number for the base of the VIC. * @base: The register base for the VIC. + * @valid_sources: A bitmask of valid interrupts * @resume_sources: A bitmask of interrupts for resume. * @resume_irqs: The IRQs enabled for resume. * @int_select: Save for VIC_INT_SELECT. @@ -50,6 +51,7 @@ struct vic_device { void __iomem *base; int irq; + u32 valid_sources; u32 resume_sources; u32 resume_irqs; u32 int_select; @@ -164,10 +166,32 @@ static int __init vic_pm_init(void) late_initcall(vic_pm_init); #endif /* CONFIG_PM */ +static struct irq_chip vic_chip; + +static int vic_irqdomain_map(struct irq_domain *d, unsigned int irq, + irq_hw_number_t hwirq) +{ + struct vic_device *v = d->host_data; + + /* Skip invalid IRQs, only register handlers for the real ones */ + if (!(v->valid_sources & (1 << hwirq))) + return -ENOTSUPP; + irq_set_chip_and_handler(irq, &vic_chip, handle_level_irq); + irq_set_chip_data(irq, v->base); + set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); + return 0; +} + +static struct irq_domain_ops vic_irqdomain_ops = { + .map = vic_irqdomain_map, + .xlate = irq_domain_xlate_onetwocell, +}; + /** * vic_register() - Register a VIC. * @base: The base address of the VIC. * @irq: The base IRQ for the VIC. + * @valid_sources: bitmask of valid interrupts * @resume_sources: bitmask of interrupts allowed for resume sources. * @node: The device tree node associated with the VIC. * @@ -178,7 +202,8 @@ late_initcall(vic_pm_init); * This also configures the IRQ domain for the VIC. */ static void __init vic_register(void __iomem *base, unsigned int irq, - u32 resume_sources, struct device_node *node) + u32 valid_sources, u32 resume_sources, + struct device_node *node) { struct vic_device *v; @@ -189,11 +214,12 @@ static void __init vic_register(void __iomem *base, unsigned int irq, v = &vic_devices[vic_id]; v->base = base; + v->valid_sources = valid_sources; v->resume_sources = resume_sources; v->irq = irq; vic_id++; - v->domain = irq_domain_add_legacy(node, 32, irq, 0, - &irq_domain_simple_ops, v); + v->domain = irq_domain_add_legacy(node, fls(valid_sources), irq, 0, + &vic_irqdomain_ops, v); } static void vic_ack_irq(struct irq_data *d) @@ -287,23 +313,6 @@ static void __init vic_clear_interrupts(void __iomem *base) } } -static void __init vic_set_irq_sources(void __iomem *base, - unsigned int irq_start, u32 vic_sources) -{ - unsigned int i; - - for (i = 0; i < 32; i++) { - if (vic_sources & (1 << i)) { - unsigned int irq = irq_start + i; - - irq_set_chip_and_handler(irq, &vic_chip, - handle_level_irq); - irq_set_chip_data(irq, base); - set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); - } - } -} - /* * The PL190 cell from ARM has been modified by ST to handle 64 interrupts. * The original cell has 32 interrupts, while the modified one has 64, @@ -338,8 +347,7 @@ static void __init vic_init_st(void __iomem *base, unsigned int irq_start, writel(32, base + VIC_PL190_DEF_VECT_ADDR); } - vic_set_irq_sources(base, irq_start, vic_sources); - vic_register(base, irq_start, 0, node); + vic_register(base, irq_start, vic_sources, 0, node); } void __init __vic_init(void __iomem *base, unsigned int irq_start, @@ -379,9 +387,7 @@ void __init __vic_init(void __iomem *base, unsigned int irq_start, vic_init2(base); - vic_set_irq_sources(base, irq_start, vic_sources); - - vic_register(base, irq_start, resume_sources, node); + vic_register(base, irq_start, vic_sources, resume_sources, node); } /** @@ -427,19 +433,18 @@ int __init vic_of_init(struct device_node *node, struct device_node *parent) /* * Handle each interrupt in a single VIC. Returns non-zero if we've - * handled at least one interrupt. This does a single read of the - * status register and handles all interrupts in order from LSB first. + * handled at least one interrupt. This reads the status register + * before handling each interrupt, which is necessary given that + * handle_IRQ may briefly re-enable interrupts for soft IRQ handling. */ static int handle_one_vic(struct vic_device *vic, struct pt_regs *regs) { u32 stat, irq; int handled = 0; - stat = readl_relaxed(vic->base + VIC_IRQ_STATUS); - while (stat) { + while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) { irq = ffs(stat) - 1; handle_IRQ(irq_find_mapping(vic->domain, irq), regs); - stat &= ~(1 << irq); handled = 1; } diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig index b5ac644e12af..6b31cb60daab 100644 --- a/arch/arm/configs/imx_v4_v5_defconfig +++ b/arch/arm/configs/imx_v4_v5_defconfig @@ -112,6 +112,7 @@ CONFIG_WATCHDOG=y CONFIG_IMX2_WDT=y CONFIG_MFD_MC13XXX=y CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_MC13783=y CONFIG_REGULATOR_MC13892=y CONFIG_FB=y diff --git a/arch/arm/configs/mini2440_defconfig b/arch/arm/configs/mini2440_defconfig index 42da9183acc8..082175c54e7c 100644 --- a/arch/arm/configs/mini2440_defconfig +++ b/arch/arm/configs/mini2440_defconfig @@ -14,6 +14,8 @@ CONFIG_MODULE_FORCE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set CONFIG_BLK_DEV_INTEGRITY=y CONFIG_ARCH_S3C24XX=y +# CONFIG_CPU_S3C2410 is not set +CONFIG_CPU_S3C2440=y CONFIG_S3C_ADC=y CONFIG_S3C24XX_PWM=y CONFIG_MACH_MINI2440=y diff --git a/arch/arm/configs/rpc_defconfig b/arch/arm/configs/rpc_defconfig index af278f7a2246..00515ef9782d 100644 --- a/arch/arm/configs/rpc_defconfig +++ b/arch/arm/configs/rpc_defconfig @@ -8,8 +8,6 @@ CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set CONFIG_ARCH_RPC=y -CONFIG_CPU_ARM610=y -CONFIG_CPU_ARM710=y CONFIG_CPU_SA110=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig index 889d73ac1ae1..7e84f453e8a6 100644 --- a/arch/arm/configs/u8500_defconfig +++ b/arch/arm/configs/u8500_defconfig @@ -8,8 +8,6 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_LBDAF is not set # CONFIG_BLK_DEV_BSG is not set CONFIG_ARCH_U8500=y -CONFIG_UX500_SOC_DB5500=y -CONFIG_UX500_SOC_DB8500=y CONFIG_MACH_HREFV60=y CONFIG_MACH_SNOWBALL=y CONFIG_MACH_U5500=y @@ -39,7 +37,6 @@ CONFIG_CAIF=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=65536 -CONFIG_MISC_DEVICES=y CONFIG_AB8500_PWM=y CONFIG_SENSORS_BH1780=y CONFIG_NETDEVICES=y @@ -65,16 +62,18 @@ CONFIG_SERIAL_AMBA_PL011=y CONFIG_SERIAL_AMBA_PL011_CONSOLE=y CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_NOMADIK=y -CONFIG_I2C=y -CONFIG_I2C_NOMADIK=y CONFIG_SPI=y CONFIG_SPI_PL022=y CONFIG_GPIO_STMPE=y CONFIG_GPIO_TC3589X=y +CONFIG_POWER_SUPPLY=y +CONFIG_AB8500_BM=y +CONFIG_AB8500_BATTERY_THERM_ON_BATCTRL=y CONFIG_MFD_STMPE=y CONFIG_MFD_TC3589X=y CONFIG_AB5500_CORE=y CONFIG_AB8500_CORE=y +CONFIG_REGULATOR=y CONFIG_REGULATOR_AB8500=y # CONFIG_HID_SUPPORT is not set CONFIG_USB_GADGET=y diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h new file mode 100644 index 000000000000..ed2e95d46e29 --- /dev/null +++ b/arch/arm/include/asm/arch_timer.h @@ -0,0 +1,19 @@ +#ifndef __ASMARM_ARCH_TIMER_H +#define __ASMARM_ARCH_TIMER_H + +#ifdef CONFIG_ARM_ARCH_TIMER +int arch_timer_of_register(void); +int arch_timer_sched_clock_init(void); +#else +static inline int arch_timer_of_register(void) +{ + return -ENXIO; +} + +static inline int arch_timer_sched_clock_init(void) +{ + return -ENXIO; +} +#endif + +#endif diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h index d5d8d5c72682..004c1bc95d2b 100644 --- a/arch/arm/include/asm/cacheflush.h +++ b/arch/arm/include/asm/cacheflush.h @@ -101,7 +101,7 @@ struct cpu_cache_fns { void (*flush_user_range)(unsigned long, unsigned long, unsigned int); void (*coherent_kern_range)(unsigned long, unsigned long); - void (*coherent_user_range)(unsigned long, unsigned long); + int (*coherent_user_range)(unsigned long, unsigned long); void (*flush_kern_dcache_area)(void *, size_t); void (*dma_map_area)(const void *, size_t, int); @@ -142,7 +142,7 @@ extern void __cpuc_flush_kern_all(void); extern void __cpuc_flush_user_all(void); extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int); extern void __cpuc_coherent_kern_range(unsigned long, unsigned long); -extern void __cpuc_coherent_user_range(unsigned long, unsigned long); +extern int __cpuc_coherent_user_range(unsigned long, unsigned long); extern void __cpuc_flush_dcache_area(void *, size_t); /* @@ -249,7 +249,7 @@ extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr * Harvard caches are synchronised for the user space address range. * This is used for the ARM private sys_cacheflush system call. */ -#define flush_cache_user_range(vma,start,end) \ +#define flush_cache_user_range(start,end) \ __cpuc_coherent_user_range((start) & PAGE_MASK, PAGE_ALIGN(end)) /* diff --git a/arch/arm/include/asm/cmpxchg.h b/arch/arm/include/asm/cmpxchg.h index d41d7cbf0ada..7eb18c1d8d6c 100644 --- a/arch/arm/include/asm/cmpxchg.h +++ b/arch/arm/include/asm/cmpxchg.h @@ -229,66 +229,19 @@ static inline unsigned long __cmpxchg_local(volatile void *ptr, (unsigned long)(n), \ sizeof(*(ptr)))) -#ifndef CONFIG_CPU_V6 /* min ARCH >= ARMv6K */ - -/* - * Note : ARMv7-M (currently unsupported by Linux) does not support - * ldrexd/strexd. If ARMv7-M is ever supported by the Linux kernel, it should - * not be allowed to use __cmpxchg64. - */ -static inline unsigned long long __cmpxchg64(volatile void *ptr, - unsigned long long old, - unsigned long long new) -{ - register unsigned long long oldval asm("r0"); - register unsigned long long __old asm("r2") = old; - register unsigned long long __new asm("r4") = new; - unsigned long res; - - do { - asm volatile( - " @ __cmpxchg8\n" - " ldrexd %1, %H1, [%2]\n" - " mov %0, #0\n" - " teq %1, %3\n" - " teqeq %H1, %H3\n" - " strexdeq %0, %4, %H4, [%2]\n" - : "=&r" (res), "=&r" (oldval) - : "r" (ptr), "Ir" (__old), "r" (__new) - : "memory", "cc"); - } while (res); - - return oldval; -} - -static inline unsigned long long __cmpxchg64_mb(volatile void *ptr, - unsigned long long old, - unsigned long long new) -{ - unsigned long long ret; - - smp_mb(); - ret = __cmpxchg64(ptr, old, new); - smp_mb(); - - return ret; -} - -#define cmpxchg64(ptr,o,n) \ - ((__typeof__(*(ptr)))__cmpxchg64_mb((ptr), \ - (unsigned long long)(o), \ - (unsigned long long)(n))) - -#define cmpxchg64_local(ptr,o,n) \ - ((__typeof__(*(ptr)))__cmpxchg64((ptr), \ - (unsigned long long)(o), \ - (unsigned long long)(n))) - -#else /* min ARCH = ARMv6 */ - -#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n)) - -#endif +#define cmpxchg64(ptr, o, n) \ + ((__typeof__(*(ptr)))atomic64_cmpxchg(container_of((ptr), \ + atomic64_t, \ + counter), \ + (unsigned long)(o), \ + (unsigned long)(n))) + +#define cmpxchg64_local(ptr, o, n) \ + ((__typeof__(*(ptr)))local64_cmpxchg(container_of((ptr), \ + local64_t, \ + a), \ + (unsigned long)(o), \ + (unsigned long)(n))) #endif /* __LINUX_ARM_ARCH__ >= 6 */ diff --git a/arch/arm/include/asm/glue-df.h b/arch/arm/include/asm/glue-df.h index 354d571e8bcc..8cacbcda76da 100644 --- a/arch/arm/include/asm/glue-df.h +++ b/arch/arm/include/asm/glue-df.h @@ -31,14 +31,6 @@ #undef CPU_DABORT_HANDLER #undef MULTI_DABORT -#if defined(CONFIG_CPU_ARM610) -# ifdef CPU_DABORT_HANDLER -# define MULTI_DABORT 1 -# else -# define CPU_DABORT_HANDLER cpu_arm6_data_abort -# endif -#endif - #if defined(CONFIG_CPU_ARM710) # ifdef CPU_DABORT_HANDLER # define MULTI_DABORT 1 diff --git a/arch/arm/include/asm/glue-proc.h b/arch/arm/include/asm/glue-proc.h index e2be7f142668..ac1dd54724b6 100644 --- a/arch/arm/include/asm/glue-proc.h +++ b/arch/arm/include/asm/glue-proc.h @@ -23,15 +23,6 @@ * CPU_NAME - the prefix for CPU related functions */ -#ifdef CONFIG_CPU_ARM610 -# ifdef CPU_NAME -# undef MULTI_CPU -# define MULTI_CPU -# else -# define CPU_NAME cpu_arm6 -# endif -#endif - #ifdef CONFIG_CPU_ARM7TDMI # ifdef CPU_NAME # undef MULTI_CPU @@ -41,15 +32,6 @@ # endif #endif -#ifdef CONFIG_CPU_ARM710 -# ifdef CPU_NAME -# undef MULTI_CPU -# define MULTI_CPU -# else -# define CPU_NAME cpu_arm7 -# endif -#endif - #ifdef CONFIG_CPU_ARM720T # ifdef CPU_NAME # undef MULTI_CPU diff --git a/arch/arm/include/asm/hardware/it8152.h b/arch/arm/include/asm/hardware/it8152.h index 73f84fa4f366..d36a73d7c0e8 100644 --- a/arch/arm/include/asm/hardware/it8152.h +++ b/arch/arm/include/asm/hardware/it8152.h @@ -110,6 +110,6 @@ extern void it8152_irq_demux(unsigned int irq, struct irq_desc *desc); extern void it8152_init_irq(void); extern int it8152_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); extern int it8152_pci_setup(int nr, struct pci_sys_data *sys); -extern struct pci_bus *it8152_pci_scan_bus(int nr, struct pci_sys_data *sys); +extern struct pci_ops it8152_ops; #endif /* __ASM_HARDWARE_IT8152_H */ diff --git a/arch/arm/include/asm/jump_label.h b/arch/arm/include/asm/jump_label.h index 5c5ca2ea62b0..bfc198c75913 100644 --- a/arch/arm/include/asm/jump_label.h +++ b/arch/arm/include/asm/jump_label.h @@ -14,7 +14,7 @@ #define JUMP_LABEL_NOP "nop" #endif -static __always_inline bool arch_static_branch(struct jump_label_key *key) +static __always_inline bool arch_static_branch(struct static_key *key) { asm goto("1:\n\t" JUMP_LABEL_NOP "\n\t" diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h index d943b7d20f11..26c511fddf8f 100644 --- a/arch/arm/include/asm/mach/pci.h +++ b/arch/arm/include/asm/mach/pci.h @@ -12,13 +12,14 @@ #define __ASM_MACH_PCI_H struct pci_sys_data; +struct pci_ops; struct pci_bus; struct hw_pci { #ifdef CONFIG_PCI_DOMAINS int domain; #endif - struct list_head buses; + struct pci_ops *ops; int nr_controllers; int (*setup)(int nr, struct pci_sys_data *); struct pci_bus *(*scan)(int nr, struct pci_sys_data *); @@ -45,16 +46,10 @@ struct pci_sys_data { u8 (*swizzle)(struct pci_dev *, u8 *); /* IRQ mapping */ int (*map_irq)(const struct pci_dev *, u8, u8); - struct hw_pci *hw; void *private_data; /* platform controller private data */ }; /* - * This is the standard PCI-PCI bridge swizzling algorithm. - */ -#define pci_std_swizzle pci_common_swizzle - -/* * Call this with your hw_pci struct to initialise the PCI system. */ void pci_common_init(struct hw_pci *); @@ -62,22 +57,22 @@ void pci_common_init(struct hw_pci *); /* * PCI controllers */ +extern struct pci_ops iop3xx_ops; extern int iop3xx_pci_setup(int nr, struct pci_sys_data *); -extern struct pci_bus *iop3xx_pci_scan_bus(int nr, struct pci_sys_data *); extern void iop3xx_pci_preinit(void); extern void iop3xx_pci_preinit_cond(void); +extern struct pci_ops dc21285_ops; extern int dc21285_setup(int nr, struct pci_sys_data *); -extern struct pci_bus *dc21285_scan_bus(int nr, struct pci_sys_data *); extern void dc21285_preinit(void); extern void dc21285_postinit(void); +extern struct pci_ops via82c505_ops; extern int via82c505_setup(int nr, struct pci_sys_data *); -extern struct pci_bus *via82c505_scan_bus(int nr, struct pci_sys_data *); extern void via82c505_init(void *sysdata); +extern struct pci_ops pci_v3_ops; extern int pci_v3_setup(int nr, struct pci_sys_data *); -extern struct pci_bus *pci_v3_scan_bus(int nr, struct pci_sys_data *); extern void pci_v3_preinit(void); extern void pci_v3_postinit(void); diff --git a/arch/arm/include/asm/mach/time.h b/arch/arm/include/asm/mach/time.h index f73c908b7fa0..6ca945f534ab 100644 --- a/arch/arm/include/asm/mach/time.h +++ b/arch/arm/include/asm/mach/time.h @@ -42,4 +42,9 @@ struct sys_timer { extern void timer_tick(void); +struct timespec; +typedef void (*clock_access_fn)(struct timespec *); +extern int register_persistent_clock(clock_access_fn read_boot, + clock_access_fn read_persistent); + #endif diff --git a/arch/arm/include/asm/mmu.h b/arch/arm/include/asm/mmu.h index b8e580a297e4..14965658a923 100644 --- a/arch/arm/include/asm/mmu.h +++ b/arch/arm/include/asm/mmu.h @@ -34,11 +34,4 @@ typedef struct { #endif -/* - * switch_mm() may do a full cache flush over the context switch, - * so enable interrupts over the context switch to avoid high - * latency. - */ -#define __ARCH_WANT_INTERRUPTS_ON_CTXSW - #endif diff --git a/arch/arm/include/asm/mmu_context.h b/arch/arm/include/asm/mmu_context.h index a0b3cac0547c..0306bc642c0d 100644 --- a/arch/arm/include/asm/mmu_context.h +++ b/arch/arm/include/asm/mmu_context.h @@ -43,45 +43,104 @@ void __check_kvm_seq(struct mm_struct *mm); #define ASID_FIRST_VERSION (1 << ASID_BITS) extern unsigned int cpu_last_asid; -#ifdef CONFIG_SMP -DECLARE_PER_CPU(struct mm_struct *, current_mm); -#endif void __init_new_context(struct task_struct *tsk, struct mm_struct *mm); void __new_context(struct mm_struct *mm); +void cpu_set_reserved_ttbr0(void); -static inline void check_context(struct mm_struct *mm) +static inline void switch_new_context(struct mm_struct *mm) { - /* - * This code is executed with interrupts enabled. Therefore, - * mm->context.id cannot be updated to the latest ASID version - * on a different CPU (and condition below not triggered) - * without first getting an IPI to reset the context. The - * alternative is to take a read_lock on mm->context.id_lock - * (after changing its type to rwlock_t). - */ - if (unlikely((mm->context.id ^ cpu_last_asid) >> ASID_BITS)) - __new_context(mm); + unsigned long flags; + + __new_context(mm); + + local_irq_save(flags); + cpu_switch_mm(mm->pgd, mm); + local_irq_restore(flags); +} +static inline void check_and_switch_context(struct mm_struct *mm, + struct task_struct *tsk) +{ if (unlikely(mm->context.kvm_seq != init_mm.context.kvm_seq)) __check_kvm_seq(mm); + + /* + * Required during context switch to avoid speculative page table + * walking with the wrong TTBR. + */ + cpu_set_reserved_ttbr0(); + + if (!((mm->context.id ^ cpu_last_asid) >> ASID_BITS)) + /* + * The ASID is from the current generation, just switch to the + * new pgd. This condition is only true for calls from + * context_switch() and interrupts are already disabled. + */ + cpu_switch_mm(mm->pgd, mm); + else if (irqs_disabled()) + /* + * Defer the new ASID allocation until after the context + * switch critical region since __new_context() cannot be + * called with interrupts disabled (it sends IPIs). + */ + set_ti_thread_flag(task_thread_info(tsk), TIF_SWITCH_MM); + else + /* + * That is a direct call to switch_mm() or activate_mm() with + * interrupts enabled and a new context. + */ + switch_new_context(mm); } #define init_new_context(tsk,mm) (__init_new_context(tsk,mm),0) -#else - -static inline void check_context(struct mm_struct *mm) +#define finish_arch_post_lock_switch \ + finish_arch_post_lock_switch +static inline void finish_arch_post_lock_switch(void) { + if (test_and_clear_thread_flag(TIF_SWITCH_MM)) + switch_new_context(current->mm); +} + +#else /* !CONFIG_CPU_HAS_ASID */ + #ifdef CONFIG_MMU + +static inline void check_and_switch_context(struct mm_struct *mm, + struct task_struct *tsk) +{ if (unlikely(mm->context.kvm_seq != init_mm.context.kvm_seq)) __check_kvm_seq(mm); -#endif + + if (irqs_disabled()) + /* + * cpu_switch_mm() needs to flush the VIVT caches. To avoid + * high interrupt latencies, defer the call and continue + * running with the old mm. Since we only support UP systems + * on non-ASID CPUs, the old mm will remain valid until the + * finish_arch_post_lock_switch() call. + */ + set_ti_thread_flag(task_thread_info(tsk), TIF_SWITCH_MM); + else + cpu_switch_mm(mm->pgd, mm); } +#define finish_arch_post_lock_switch \ + finish_arch_post_lock_switch +static inline void finish_arch_post_lock_switch(void) +{ + if (test_and_clear_thread_flag(TIF_SWITCH_MM)) { + struct mm_struct *mm = current->mm; + cpu_switch_mm(mm->pgd, mm); + } +} + +#endif /* CONFIG_MMU */ + #define init_new_context(tsk,mm) 0 -#endif +#endif /* CONFIG_CPU_HAS_ASID */ #define destroy_context(mm) do { } while(0) @@ -119,12 +178,7 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next, __flush_icache_all(); #endif if (!cpumask_test_and_set_cpu(cpu, mm_cpumask(next)) || prev != next) { -#ifdef CONFIG_SMP - struct mm_struct **crt_mm = &per_cpu(current_mm, cpu); - *crt_mm = next; -#endif - check_context(next); - cpu_switch_mm(next->pgd, next); + check_and_switch_context(next, tsk); if (cache_is_vivt()) cpumask_clear_cpu(cpu, mm_cpumask(prev)); } diff --git a/arch/arm/include/asm/page.h b/arch/arm/include/asm/page.h index 5838361c48b3..ecf901902e44 100644 --- a/arch/arm/include/asm/page.h +++ b/arch/arm/include/asm/page.h @@ -34,7 +34,6 @@ * processor(s) we're building for. * * We have the following to choose from: - * v3 - ARMv3 * v4wt - ARMv4 with writethrough cache, without minicache * v4wb - ARMv4 with writeback cache, without minicache * v4_mc - ARMv4 with minicache @@ -44,14 +43,6 @@ #undef _USER #undef MULTI_USER -#ifdef CONFIG_CPU_COPY_V3 -# ifdef _USER -# define MULTI_USER 1 -# else -# define _USER v3 -# endif -#endif - #ifdef CONFIG_CPU_COPY_V4WT # ifdef _USER # define MULTI_USER 1 diff --git a/arch/arm/include/asm/pgtable-3level.h b/arch/arm/include/asm/pgtable-3level.h index 759af70f9a0a..b24903549d1c 100644 --- a/arch/arm/include/asm/pgtable-3level.h +++ b/arch/arm/include/asm/pgtable-3level.h @@ -69,8 +69,6 @@ */ #define L_PTE_PRESENT (_AT(pteval_t, 3) << 0) /* Valid */ #define L_PTE_FILE (_AT(pteval_t, 1) << 2) /* only when !PRESENT */ -#define L_PTE_BUFFERABLE (_AT(pteval_t, 1) << 2) /* AttrIndx[0] */ -#define L_PTE_CACHEABLE (_AT(pteval_t, 1) << 3) /* AttrIndx[1] */ #define L_PTE_USER (_AT(pteval_t, 1) << 6) /* AP[1] */ #define L_PTE_RDONLY (_AT(pteval_t, 1) << 7) /* AP[2] */ #define L_PTE_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */ diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h index 451808ba1211..355ece523f41 100644 --- a/arch/arm/include/asm/ptrace.h +++ b/arch/arm/include/asm/ptrace.h @@ -249,6 +249,11 @@ static inline unsigned long kernel_stack_pointer(struct pt_regs *regs) return regs->ARM_sp; } +static inline unsigned long user_stack_pointer(struct pt_regs *regs) +{ + return regs->ARM_sp; +} + #endif /* __KERNEL__ */ #endif /* __ASSEMBLY__ */ diff --git a/arch/arm/include/asm/syscall.h b/arch/arm/include/asm/syscall.h new file mode 100644 index 000000000000..c334a23ddf75 --- /dev/null +++ b/arch/arm/include/asm/syscall.h @@ -0,0 +1,93 @@ +/* + * Access to user system call parameters and results + * + * See asm-generic/syscall.h for descriptions of what we must do here. + */ + +#ifndef _ASM_ARM_SYSCALL_H +#define _ASM_ARM_SYSCALL_H + +#include <linux/err.h> + +extern const unsigned long sys_call_table[]; + +static inline int syscall_get_nr(struct task_struct *task, + struct pt_regs *regs) +{ + return task_thread_info(task)->syscall; +} + +static inline void syscall_rollback(struct task_struct *task, + struct pt_regs *regs) +{ + regs->ARM_r0 = regs->ARM_ORIG_r0; +} + +static inline long syscall_get_error(struct task_struct *task, + struct pt_regs *regs) +{ + unsigned long error = regs->ARM_r0; + return IS_ERR_VALUE(error) ? error : 0; +} + +static inline long syscall_get_return_value(struct task_struct *task, + struct pt_regs *regs) +{ + return regs->ARM_r0; +} + +static inline void syscall_set_return_value(struct task_struct *task, + struct pt_regs *regs, + int error, long val) +{ + regs->ARM_r0 = (long) error ? error : val; +} + +#define SYSCALL_MAX_ARGS 7 + +static inline void syscall_get_arguments(struct task_struct *task, + struct pt_regs *regs, + unsigned int i, unsigned int n, + unsigned long *args) +{ + if (i + n > SYSCALL_MAX_ARGS) { + unsigned long *args_bad = args + SYSCALL_MAX_ARGS - i; + unsigned int n_bad = n + i - SYSCALL_MAX_ARGS; + pr_warning("%s called with max args %d, handling only %d\n", + __func__, i + n, SYSCALL_MAX_ARGS); + memset(args_bad, 0, n_bad * sizeof(args[0])); + n = SYSCALL_MAX_ARGS - i; + } + + if (i == 0) { + args[0] = regs->ARM_ORIG_r0; + args++; + i++; + n--; + } + + memcpy(args, ®s->ARM_r0 + i, n * sizeof(args[0])); +} + +static inline void syscall_set_arguments(struct task_struct *task, + struct pt_regs *regs, + unsigned int i, unsigned int n, + const unsigned long *args) +{ + if (i + n > SYSCALL_MAX_ARGS) { + pr_warning("%s called with max args %d, handling only %d\n", + __func__, i + n, SYSCALL_MAX_ARGS); + n = SYSCALL_MAX_ARGS - i; + } + + if (i == 0) { + regs->ARM_ORIG_r0 = args[0]; + args++; + i++; + n--; + } + + memcpy(®s->ARM_r0 + i, args, n * sizeof(args[0])); +} + +#endif /* _ASM_ARM_SYSCALL_H */ diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h index d4c24d412a8d..68388eb4946b 100644 --- a/arch/arm/include/asm/thread_info.h +++ b/arch/arm/include/asm/thread_info.h @@ -118,6 +118,13 @@ extern void iwmmxt_task_switch(struct thread_info *); extern void vfp_sync_hwstate(struct thread_info *); extern void vfp_flush_hwstate(struct thread_info *); +struct user_vfp; +struct user_vfp_exc; + +extern int vfp_preserve_user_clear_hwstate(struct user_vfp __user *, + struct user_vfp_exc __user *); +extern int vfp_restore_user_hwstate(struct user_vfp __user *, + struct user_vfp_exc __user *); #endif /* @@ -146,6 +153,7 @@ extern void vfp_flush_hwstate(struct thread_info *); #define TIF_MEMDIE 18 /* is terminating due to OOM killer */ #define TIF_RESTORE_SIGMASK 20 #define TIF_SECCOMP 21 +#define TIF_SWITCH_MM 22 /* deferred switch_mm */ #define _TIF_SIGPENDING (1 << TIF_SIGPENDING) #define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED) diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h index 85fe61e73202..6e924d3a77eb 100644 --- a/arch/arm/include/asm/tlbflush.h +++ b/arch/arm/include/asm/tlbflush.h @@ -65,21 +65,6 @@ #define MULTI_TLB 1 #endif -#define v3_tlb_flags (TLB_V3_FULL | TLB_V3_PAGE) - -#ifdef CONFIG_CPU_TLB_V3 -# define v3_possible_flags v3_tlb_flags -# define v3_always_flags v3_tlb_flags -# ifdef _TLB -# define MULTI_TLB 1 -# else -# define _TLB v3 -# endif -#else -# define v3_possible_flags 0 -# define v3_always_flags (-1UL) -#endif - #define v4_tlb_flags (TLB_V4_U_FULL | TLB_V4_U_PAGE) #ifdef CONFIG_CPU_TLB_V4WT @@ -298,8 +283,7 @@ extern struct cpu_tlb_fns cpu_tlb; * implemented the "%?" method, but this has been discontinued due to too * many people getting it wrong. */ -#define possible_tlb_flags (v3_possible_flags | \ - v4_possible_flags | \ +#define possible_tlb_flags (v4_possible_flags | \ v4wbi_possible_flags | \ fr_possible_flags | \ v4wb_possible_flags | \ @@ -307,8 +291,7 @@ extern struct cpu_tlb_fns cpu_tlb; v6wbi_possible_flags | \ v7wbi_possible_flags) -#define always_tlb_flags (v3_always_flags & \ - v4_always_flags & \ +#define always_tlb_flags (v4_always_flags & \ v4wbi_always_flags & \ fr_always_flags & \ v4wb_always_flags & \ diff --git a/arch/arm/include/asm/tls.h b/arch/arm/include/asm/tls.h index 60843eb0f61c..73409e6c0251 100644 --- a/arch/arm/include/asm/tls.h +++ b/arch/arm/include/asm/tls.h @@ -7,6 +7,8 @@ .macro set_tls_v6k, tp, tmp1, tmp2 mcr p15, 0, \tp, c13, c0, 3 @ set TLS register + mov \tmp1, #0 + mcr p15, 0, \tmp1, c13, c0, 2 @ clear user r/w TLS register .endm .macro set_tls_v6, tp, tmp1, tmp2 @@ -15,6 +17,8 @@ mov \tmp2, #0xffff0fff tst \tmp1, #HWCAP_TLS @ hardware TLS available? mcrne p15, 0, \tp, c13, c0, 3 @ yes, set TLS register + movne \tmp1, #0 + mcrne p15, 0, \tmp1, c13, c0, 2 @ clear user r/w TLS register streq \tp, [\tmp2, #-15] @ set TLS value at 0xffff0ff0 .endm diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile index 7b787d642af4..22b0f1e255f0 100644 --- a/arch/arm/kernel/Makefile +++ b/arch/arm/kernel/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_ARM_CPU_SUSPEND) += sleep.o suspend.o obj-$(CONFIG_SMP) += smp.o smp_tlb.o obj-$(CONFIG_HAVE_ARM_SCU) += smp_scu.o obj-$(CONFIG_HAVE_ARM_TWD) += smp_twd.o +obj-$(CONFIG_ARM_ARCH_TIMER) += arch_timer.o obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o insn.o obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o insn.o obj-$(CONFIG_JUMP_LABEL) += jump_label.o insn.o patch.o diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c new file mode 100644 index 000000000000..dd58035621f7 --- /dev/null +++ b/arch/arm/kernel/arch_timer.c @@ -0,0 +1,350 @@ +/* + * linux/arch/arm/kernel/arch_timer.c + * + * Copyright (C) 2011 ARM Ltd. + * All Rights Reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/delay.h> +#include <linux/device.h> +#include <linux/smp.h> +#include <linux/cpu.h> +#include <linux/jiffies.h> +#include <linux/clockchips.h> +#include <linux/interrupt.h> +#include <linux/of_irq.h> +#include <linux/io.h> + +#include <asm/cputype.h> +#include <asm/localtimer.h> +#include <asm/arch_timer.h> +#include <asm/system_info.h> +#include <asm/sched_clock.h> + +static unsigned long arch_timer_rate; +static int arch_timer_ppi; +static int arch_timer_ppi2; + +static struct clock_event_device __percpu **arch_timer_evt; + +/* + * Architected system timer support. + */ + +#define ARCH_TIMER_CTRL_ENABLE (1 << 0) +#define ARCH_TIMER_CTRL_IT_MASK (1 << 1) +#define ARCH_TIMER_CTRL_IT_STAT (1 << 2) + +#define ARCH_TIMER_REG_CTRL 0 +#define ARCH_TIMER_REG_FREQ 1 +#define ARCH_TIMER_REG_TVAL 2 + +static void arch_timer_reg_write(int reg, u32 val) +{ + switch (reg) { + case ARCH_TIMER_REG_CTRL: + asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" (val)); + break; + case ARCH_TIMER_REG_TVAL: + asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val)); + break; + } + + isb(); +} + +static u32 arch_timer_reg_read(int reg) +{ + u32 val; + + switch (reg) { + case ARCH_TIMER_REG_CTRL: + asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val)); + break; + case ARCH_TIMER_REG_FREQ: + asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val)); + break; + case ARCH_TIMER_REG_TVAL: + asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val)); + break; + default: + BUG(); + } + + return val; +} + +static irqreturn_t arch_timer_handler(int irq, void *dev_id) +{ + struct clock_event_device *evt = *(struct clock_event_device **)dev_id; + unsigned long ctrl; + + ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL); + if (ctrl & ARCH_TIMER_CTRL_IT_STAT) { + ctrl |= ARCH_TIMER_CTRL_IT_MASK; + arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl); + evt->event_handler(evt); + return IRQ_HANDLED; + } + + return IRQ_NONE; +} + +static void arch_timer_disable(void) +{ + unsigned long ctrl; + + ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL); + ctrl &= ~ARCH_TIMER_CTRL_ENABLE; + arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl); +} + +static void arch_timer_set_mode(enum clock_event_mode mode, + struct clock_event_device *clk) +{ + switch (mode) { + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_SHUTDOWN: + arch_timer_disable(); + break; + default: + break; + } +} + +static int arch_timer_set_next_event(unsigned long evt, + struct clock_event_device *unused) +{ + unsigned long ctrl; + + ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL); + ctrl |= ARCH_TIMER_CTRL_ENABLE; + ctrl &= ~ARCH_TIMER_CTRL_IT_MASK; + + arch_timer_reg_write(ARCH_TIMER_REG_TVAL, evt); + arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl); + + return 0; +} + +static int __cpuinit arch_timer_setup(struct clock_event_device *clk) +{ + /* Be safe... */ + arch_timer_disable(); + + clk->features = CLOCK_EVT_FEAT_ONESHOT; + clk->name = "arch_sys_timer"; + clk->rating = 450; + clk->set_mode = arch_timer_set_mode; + clk->set_next_event = arch_timer_set_next_event; + clk->irq = arch_timer_ppi; + + clockevents_config_and_register(clk, arch_timer_rate, + 0xf, 0x7fffffff); + + *__this_cpu_ptr(arch_timer_evt) = clk; + + enable_percpu_irq(clk->irq, 0); + if (arch_timer_ppi2) + enable_percpu_irq(arch_timer_ppi2, 0); + + return 0; +} + +/* Is the optional system timer available? */ +static int local_timer_is_architected(void) +{ + return (cpu_architecture() >= CPU_ARCH_ARMv7) && + ((read_cpuid_ext(CPUID_EXT_PFR1) >> 16) & 0xf) == 1; +} + +static int arch_timer_available(void) +{ + unsigned long freq; + + if (!local_timer_is_architected()) + return -ENXIO; + + if (arch_timer_rate == 0) { + arch_timer_reg_write(ARCH_TIMER_REG_CTRL, 0); + freq = arch_timer_reg_read(ARCH_TIMER_REG_FREQ); + + /* Check the timer frequency. */ + if (freq == 0) { + pr_warn("Architected timer frequency not available\n"); + return -EINVAL; + } + + arch_timer_rate = freq; + } + + pr_info_once("Architected local timer running at %lu.%02luMHz.\n", + arch_timer_rate / 1000000, (arch_timer_rate / 10000) % 100); + return 0; +} + +static inline cycle_t arch_counter_get_cntpct(void) +{ + u32 cvall, cvalh; + + asm volatile("mrrc p15, 0, %0, %1, c14" : "=r" (cvall), "=r" (cvalh)); + + return ((cycle_t) cvalh << 32) | cvall; +} + +static inline cycle_t arch_counter_get_cntvct(void) +{ + u32 cvall, cvalh; + + asm volatile("mrrc p15, 1, %0, %1, c14" : "=r" (cvall), "=r" (cvalh)); + + return ((cycle_t) cvalh << 32) | cvall; +} + +static u32 notrace arch_counter_get_cntvct32(void) +{ + cycle_t cntvct = arch_counter_get_cntvct(); + + /* + * The sched_clock infrastructure only knows about counters + * with at most 32bits. Forget about the upper 24 bits for the + * time being... + */ + return (u32)(cntvct & (u32)~0); +} + +static cycle_t arch_counter_read(struct clocksource *cs) +{ + return arch_counter_get_cntpct(); +} + +static struct clocksource clocksource_counter = { + .name = "arch_sys_counter", + .rating = 400, + .read = arch_counter_read, + .mask = CLOCKSOURCE_MASK(56), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +static void __cpuinit arch_timer_stop(struct clock_event_device *clk) +{ + pr_debug("arch_timer_teardown disable IRQ%d cpu #%d\n", + clk->irq, smp_processor_id()); + disable_percpu_irq(clk->irq); + if (arch_timer_ppi2) + disable_percpu_irq(arch_timer_ppi2); + arch_timer_set_mode(CLOCK_EVT_MODE_UNUSED, clk); +} + +static struct local_timer_ops arch_timer_ops __cpuinitdata = { + .setup = arch_timer_setup, + .stop = arch_timer_stop, +}; + +static struct clock_event_device arch_timer_global_evt; + +static int __init arch_timer_register(void) +{ + int err; + + err = arch_timer_available(); + if (err) + return err; + + arch_timer_evt = alloc_percpu(struct clock_event_device *); + if (!arch_timer_evt) + return -ENOMEM; + + clocksource_register_hz(&clocksource_counter, arch_timer_rate); + + err = request_percpu_irq(arch_timer_ppi, arch_timer_handler, + "arch_timer", arch_timer_evt); + if (err) { + pr_err("arch_timer: can't register interrupt %d (%d)\n", + arch_timer_ppi, err); + goto out_free; + } + + if (arch_timer_ppi2) { + err = request_percpu_irq(arch_timer_ppi2, arch_timer_handler, + "arch_timer", arch_timer_evt); + if (err) { + pr_err("arch_timer: can't register interrupt %d (%d)\n", + arch_timer_ppi2, err); + arch_timer_ppi2 = 0; + goto out_free_irq; + } + } + + err = local_timer_register(&arch_timer_ops); + if (err) { + /* + * We couldn't register as a local timer (could be + * because we're on a UP platform, or because some + * other local timer is already present...). Try as a + * global timer instead. + */ + arch_timer_global_evt.cpumask = cpumask_of(0); + err = arch_timer_setup(&arch_timer_global_evt); + } + + if (err) + goto out_free_irq; + + return 0; + +out_free_irq: + free_percpu_irq(arch_timer_ppi, arch_timer_evt); + if (arch_timer_ppi2) + free_percpu_irq(arch_timer_ppi2, arch_timer_evt); + +out_free: + free_percpu(arch_timer_evt); + + return err; +} + +static const struct of_device_id arch_timer_of_match[] __initconst = { + { .compatible = "arm,armv7-timer", }, + {}, +}; + +int __init arch_timer_of_register(void) +{ + struct device_node *np; + u32 freq; + + np = of_find_matching_node(NULL, arch_timer_of_match); + if (!np) { + pr_err("arch_timer: can't find DT node\n"); + return -ENODEV; + } + + /* Try to determine the frequency from the device tree or CNTFRQ */ + if (!of_property_read_u32(np, "clock-frequency", &freq)) + arch_timer_rate = freq; + + arch_timer_ppi = irq_of_parse_and_map(np, 0); + arch_timer_ppi2 = irq_of_parse_and_map(np, 1); + pr_info("arch_timer: found %s irqs %d %d\n", + np->name, arch_timer_ppi, arch_timer_ppi2); + + return arch_timer_register(); +} + +int __init arch_timer_sched_clock_init(void) +{ + int err; + + err = arch_timer_available(); + if (err) + return err; + + setup_sched_clock(arch_counter_get_cntvct32, 32, arch_timer_rate); + return 0; +} diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c index ede5f7741c42..25552508c3fd 100644 --- a/arch/arm/kernel/bios32.c +++ b/arch/arm/kernel/bios32.c @@ -374,16 +374,29 @@ EXPORT_SYMBOL(pcibios_fixup_bus); #endif /* - * Swizzle the device pin each time we cross a bridge. - * This might update pin and returns the slot number. + * Swizzle the device pin each time we cross a bridge. If a platform does + * not provide a swizzle function, we perform the standard PCI swizzling. + * + * The default swizzling walks up the bus tree one level at a time, applying + * the standard swizzle function at each step, stopping when it finds the PCI + * root bus. This will return the slot number of the bridge device on the + * root bus and the interrupt pin on that device which should correspond + * with the downstream device interrupt. + * + * Platforms may override this, in which case the slot and pin returned + * depend entirely on the platform code. However, please note that the + * PCI standard swizzle is implemented on plug-in cards and Cardbus based + * PCI extenders, so it can not be ignored. */ static u8 __devinit pcibios_swizzle(struct pci_dev *dev, u8 *pin) { struct pci_sys_data *sys = dev->sysdata; - int slot = 0, oldpin = *pin; + int slot, oldpin = *pin; if (sys->swizzle) slot = sys->swizzle(dev, pin); + else + slot = pci_common_swizzle(dev, pin); if (debug_pci) printk("PCI: %s swizzling pin %d => pin %d slot %d\n", @@ -410,7 +423,7 @@ static int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) return irq; } -static void __init pcibios_init_hw(struct hw_pci *hw) +static void __init pcibios_init_hw(struct hw_pci *hw, struct list_head *head) { struct pci_sys_data *sys = NULL; int ret; @@ -424,7 +437,6 @@ static void __init pcibios_init_hw(struct hw_pci *hw) #ifdef CONFIG_PCI_DOMAINS sys->domain = hw->domain; #endif - sys->hw = hw; sys->busnr = busnr; sys->swizzle = hw->swizzle; sys->map_irq = hw->map_irq; @@ -440,14 +452,18 @@ static void __init pcibios_init_hw(struct hw_pci *hw) &iomem_resource, sys->mem_offset); } - sys->bus = hw->scan(nr, sys); + if (hw->scan) + sys->bus = hw->scan(nr, sys); + else + sys->bus = pci_scan_root_bus(NULL, sys->busnr, + hw->ops, sys, &sys->resources); if (!sys->bus) panic("PCI: unable to scan bus!"); busnr = sys->bus->subordinate + 1; - list_add(&sys->node, &hw->buses); + list_add(&sys->node, head); } else { kfree(sys); if (ret < 0) @@ -459,19 +475,18 @@ static void __init pcibios_init_hw(struct hw_pci *hw) void __init pci_common_init(struct hw_pci *hw) { struct pci_sys_data *sys; - - INIT_LIST_HEAD(&hw->buses); + LIST_HEAD(head); pci_add_flags(PCI_REASSIGN_ALL_RSRC); if (hw->preinit) hw->preinit(); - pcibios_init_hw(hw); + pcibios_init_hw(hw, &head); if (hw->postinit) hw->postinit(); pci_fixup_irqs(pcibios_swizzle, pcibios_map_irq); - list_for_each_entry(sys, &hw->buses, node) { + list_for_each_entry(sys, &head, node) { struct pci_bus *bus = sys->bus; if (!pci_has_flag(PCI_PROBE_ONLY)) { diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index 7fd3ad048da9..437f0c426517 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S @@ -556,10 +556,6 @@ call_fpe: #endif tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2 -#if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710) - and r8, r0, #0x0f000000 @ mask out op-code bits - teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)? -#endif moveq pc, lr get_thread_info r10 @ get current thread and r8, r0, #0x00000f00 @ mask out CP number diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S index 54ee265dd819..7bd2d3cb8957 100644 --- a/arch/arm/kernel/entry-common.S +++ b/arch/arm/kernel/entry-common.S @@ -335,20 +335,6 @@ ENDPROC(ftrace_stub) *----------------------------------------------------------------------------- */ - /* If we're optimising for StrongARM the resulting code won't - run on an ARM7 and we can save a couple of instructions. - --pb */ -#ifdef CONFIG_CPU_ARM710 -#define A710(code...) code -.Larm710bug: - ldmia sp, {r0 - lr}^ @ Get calling r0 - lr - mov r0, r0 - add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 -#else -#define A710(code...) -#endif - .align 5 ENTRY(vector_swi) sub sp, sp, #S_FRAME_SIZE @@ -379,9 +365,6 @@ ENTRY(vector_swi) ldreq r10, [lr, #-4] @ get SWI instruction #else ldr r10, [lr, #-4] @ get SWI instruction - A710( and ip, r10, #0x0f000000 @ check for SWI ) - A710( teq ip, #0x0f000000 ) - A710( bne .Larm710bug ) #endif #ifdef CONFIG_CPU_ENDIAN_BE8 rev r10, r10 @ little endian instruction @@ -392,26 +375,15 @@ ENTRY(vector_swi) /* * Pure EABI user space always put syscall number into scno (r7). */ - A710( ldr ip, [lr, #-4] @ get SWI instruction ) - A710( and ip, ip, #0x0f000000 @ check for SWI ) - A710( teq ip, #0x0f000000 ) - A710( bne .Larm710bug ) - #elif defined(CONFIG_ARM_THUMB) - /* Legacy ABI only, possibly thumb mode. */ tst r8, #PSR_T_BIT @ this is SPSR from save_user_regs addne scno, r7, #__NR_SYSCALL_BASE @ put OS number in ldreq scno, [lr, #-4] #else - /* Legacy ABI only. */ ldr scno, [lr, #-4] @ get SWI instruction - A710( and ip, scno, #0x0f000000 @ check for SWI ) - A710( teq ip, #0x0f000000 ) - A710( bne .Larm710bug ) - #endif #ifdef CONFIG_ALIGNMENT_TRAP diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index 3bf0c7f8b043..835898e7d704 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -277,10 +277,6 @@ __create_page_tables: mov r3, r3, lsl #PMD_ORDER add r0, r4, r3 - rsb r3, r3, #0x4000 @ PTRS_PER_PGD*sizeof(long) - cmp r3, #0x0800 @ limit to 512MB - movhi r3, #0x0800 - add r6, r0, r3 mov r3, r7, lsr #SECTION_SHIFT ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags orr r3, r7, r3, lsl #SECTION_SHIFT @@ -289,13 +285,10 @@ __create_page_tables: #else orr r3, r3, #PMD_SECT_XN #endif -1: str r3, [r0], #4 + str r3, [r0], #4 #ifdef CONFIG_ARM_LPAE str r7, [r0], #4 #endif - add r3, r3, #1 << SECTION_SHIFT - cmp r0, r6 - blo 1b #else /* CONFIG_DEBUG_ICEDCC || CONFIG_DEBUG_SEMIHOSTING */ /* we don't need any serial debugging mappings */ diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c index 71ccdbfed662..8349d4e97e2b 100644 --- a/arch/arm/kernel/irq.c +++ b/arch/arm/kernel/irq.c @@ -155,10 +155,10 @@ static bool migrate_one_irq(struct irq_desc *desc) } c = irq_data_get_irq_chip(d); - if (c->irq_set_affinity) - c->irq_set_affinity(d, affinity, true); - else + if (!c->irq_set_affinity) pr_debug("IRQ%u: unable to set affinity\n", d->irq); + else if (c->irq_set_affinity(d, affinity, true) == IRQ_SET_MASK_OK && ret) + cpumask_copy(d->affinity, affinity); return ret; } diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c index 80abafb9bf33..14e38261cd31 100644 --- a/arch/arm/kernel/ptrace.c +++ b/arch/arm/kernel/ptrace.c @@ -24,6 +24,7 @@ #include <linux/hw_breakpoint.h> #include <linux/regset.h> #include <linux/audit.h> +#include <linux/tracehook.h> #include <asm/pgtable.h> #include <asm/traps.h> @@ -906,49 +907,33 @@ long arch_ptrace(struct task_struct *child, long request, return ret; } -#ifdef __ARMEB__ -#define AUDIT_ARCH_NR AUDIT_ARCH_ARMEB -#else -#define AUDIT_ARCH_NR AUDIT_ARCH_ARM -#endif - asmlinkage int syscall_trace(int why, struct pt_regs *regs, int scno) { unsigned long ip; - /* - * Save IP. IP is used to denote syscall entry/exit: - * IP = 0 -> entry, = 1 -> exit - */ - ip = regs->ARM_ip; - regs->ARM_ip = why; - - if (!ip) + if (why) audit_syscall_exit(regs); else - audit_syscall_entry(AUDIT_ARCH_NR, scno, regs->ARM_r0, + audit_syscall_entry(AUDIT_ARCH_ARM, scno, regs->ARM_r0, regs->ARM_r1, regs->ARM_r2, regs->ARM_r3); if (!test_thread_flag(TIF_SYSCALL_TRACE)) return scno; - if (!(current->ptrace & PT_PTRACED)) - return scno; current_thread_info()->syscall = scno; - /* the 0x80 provides a way for the tracing parent to distinguish - between a syscall stop and SIGTRAP delivery */ - ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD) - ? 0x80 : 0)); /* - * this isn't the same as continuing with a signal, but it will do - * for normal use. strace only continues with a signal if the - * stopping signal is not SIGTRAP. -brl + * IP is used to denote syscall entry/exit: + * IP = 0 -> entry, =1 -> exit */ - if (current->exit_code) { - send_sig(current->exit_code, current, 1); - current->exit_code = 0; - } + ip = regs->ARM_ip; + regs->ARM_ip = why; + + if (why) + tracehook_report_syscall_exit(regs, 0); + else if (tracehook_report_syscall_entry(regs)) + current_thread_info()->syscall = -1; + regs->ARM_ip = ip; return current_thread_info()->syscall; diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index b91411371ae1..ebfac782593f 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -523,7 +523,21 @@ int __init arm_add_memory(phys_addr_t start, unsigned long size) */ size -= start & ~PAGE_MASK; bank->start = PAGE_ALIGN(start); - bank->size = size & PAGE_MASK; + +#ifndef CONFIG_LPAE + if (bank->start + size < bank->start) { + printk(KERN_CRIT "Truncating memory at 0x%08llx to fit in " + "32-bit physical address space\n", (long long)start); + /* + * To ensure bank->start + bank->size is representable in + * 32 bits, we use ULONG_MAX as the upper limit rather than 4GB. + * This means we lose a page after masking. + */ + size = ULONG_MAX - bank->start; + } +#endif + + bank->size = size & PAGE_MASK; /* * Check whether this memory region has non-zero size or diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c index 7cb532fc8aa4..73d9a420850d 100644 --- a/arch/arm/kernel/signal.c +++ b/arch/arm/kernel/signal.c @@ -180,44 +180,23 @@ static int restore_iwmmxt_context(struct iwmmxt_sigframe *frame) static int preserve_vfp_context(struct vfp_sigframe __user *frame) { - struct thread_info *thread = current_thread_info(); - struct vfp_hard_struct *h = &thread->vfpstate.hard; const unsigned long magic = VFP_MAGIC; const unsigned long size = VFP_STORAGE_SIZE; int err = 0; - vfp_sync_hwstate(thread); __put_user_error(magic, &frame->magic, err); __put_user_error(size, &frame->size, err); - /* - * Copy the floating point registers. There can be unused - * registers see asm/hwcap.h for details. - */ - err |= __copy_to_user(&frame->ufp.fpregs, &h->fpregs, - sizeof(h->fpregs)); - /* - * Copy the status and control register. - */ - __put_user_error(h->fpscr, &frame->ufp.fpscr, err); - - /* - * Copy the exception registers. - */ - __put_user_error(h->fpexc, &frame->ufp_exc.fpexc, err); - __put_user_error(h->fpinst, &frame->ufp_exc.fpinst, err); - __put_user_error(h->fpinst2, &frame->ufp_exc.fpinst2, err); + if (err) + return -EFAULT; - return err ? -EFAULT : 0; + return vfp_preserve_user_clear_hwstate(&frame->ufp, &frame->ufp_exc); } static int restore_vfp_context(struct vfp_sigframe __user *frame) { - struct thread_info *thread = current_thread_info(); - struct vfp_hard_struct *h = &thread->vfpstate.hard; unsigned long magic; unsigned long size; - unsigned long fpexc; int err = 0; __get_user_error(magic, &frame->magic, err); @@ -228,33 +207,7 @@ static int restore_vfp_context(struct vfp_sigframe __user *frame) if (magic != VFP_MAGIC || size != VFP_STORAGE_SIZE) return -EINVAL; - vfp_flush_hwstate(thread); - - /* - * Copy the floating point registers. There can be unused - * registers see asm/hwcap.h for details. - */ - err |= __copy_from_user(&h->fpregs, &frame->ufp.fpregs, - sizeof(h->fpregs)); - /* - * Copy the status and control register. - */ - __get_user_error(h->fpscr, &frame->ufp.fpscr, err); - - /* - * Sanitise and restore the exception registers. - */ - __get_user_error(fpexc, &frame->ufp_exc.fpexc, err); - /* Ensure the VFP is enabled. */ - fpexc |= FPEXC_EN; - /* Ensure FPINST2 is invalid and the exception flag is cleared. */ - fpexc &= ~(FPEXC_EX | FPEXC_FP2V); - h->fpexc = fpexc; - - __get_user_error(h->fpinst, &frame->ufp_exc.fpinst, err); - __get_user_error(h->fpinst2, &frame->ufp_exc.fpinst2, err); - - return err ? -EFAULT : 0; + return vfp_restore_user_hwstate(&frame->ufp, &frame->ufp_exc); } #endif @@ -636,6 +589,8 @@ handle_signal(unsigned long sig, struct k_sigaction *ka, */ block_sigmask(ka, sig); + tracehook_signal_handler(sig, info, ka, regs, 0); + return 0; } diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index addbbe8028c2..cf58558ef4b9 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -251,8 +251,6 @@ asmlinkage void __cpuinit secondary_start_kernel(void) struct mm_struct *mm = &init_mm; unsigned int cpu = smp_processor_id(); - printk("CPU%u: Booted secondary processor\n", cpu); - /* * All kernel threads share the same mm context; grab a * reference and switch to it. @@ -264,6 +262,8 @@ asmlinkage void __cpuinit secondary_start_kernel(void) enter_lazy_tlb(mm, current); local_flush_tlb_all(); + printk("CPU%u: Booted secondary processor\n", cpu); + cpu_init(); preempt_disable(); trace_hardirqs_off(); @@ -454,6 +454,9 @@ static struct local_timer_ops *lt_ops; #ifdef CONFIG_LOCAL_TIMERS int local_timer_register(struct local_timer_ops *ops) { + if (!is_smp() || !setup_max_cpus) + return -ENXIO; + if (lt_ops) return -EBUSY; @@ -510,10 +513,6 @@ static void ipi_cpu_stop(unsigned int cpu) local_fiq_disable(); local_irq_disable(); -#ifdef CONFIG_HOTPLUG_CPU - platform_cpu_kill(cpu); -#endif - while (1) cpu_relax(); } @@ -576,17 +575,25 @@ void smp_send_reschedule(int cpu) smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE); } +#ifdef CONFIG_HOTPLUG_CPU +static void smp_kill_cpus(cpumask_t *mask) +{ + unsigned int cpu; + for_each_cpu(cpu, mask) + platform_cpu_kill(cpu); +} +#else +static void smp_kill_cpus(cpumask_t *mask) { } +#endif + void smp_send_stop(void) { unsigned long timeout; + struct cpumask mask; - if (num_online_cpus() > 1) { - struct cpumask mask; - cpumask_copy(&mask, cpu_online_mask); - cpumask_clear_cpu(smp_processor_id(), &mask); - - smp_cross_call(&mask, IPI_CPU_STOP); - } + cpumask_copy(&mask, cpu_online_mask); + cpumask_clear_cpu(smp_processor_id(), &mask); + smp_cross_call(&mask, IPI_CPU_STOP); /* Wait up to one second for other CPUs to stop */ timeout = USEC_PER_SEC; @@ -595,6 +602,8 @@ void smp_send_stop(void) if (num_online_cpus() > 1) pr_warning("SMP: failed to stop secondary CPUs\n"); + + smp_kill_cpus(&mask); } /* diff --git a/arch/arm/kernel/smp_scu.c b/arch/arm/kernel/smp_scu.c index 8f5dd7963356..b9f015e843d8 100644 --- a/arch/arm/kernel/smp_scu.c +++ b/arch/arm/kernel/smp_scu.c @@ -11,6 +11,7 @@ #include <linux/init.h> #include <linux/io.h> +#include <asm/smp_plat.h> #include <asm/smp_scu.h> #include <asm/cacheflush.h> #include <asm/cputype.h> @@ -74,7 +75,7 @@ void scu_enable(void __iomem *scu_base) int scu_power_mode(void __iomem *scu_base, unsigned int mode) { unsigned int val; - int cpu = smp_processor_id(); + int cpu = cpu_logical_map(smp_processor_id()); if (mode > 3 || mode == 1 || cpu > 3) return -EINVAL; diff --git a/arch/arm/kernel/sys_arm.c b/arch/arm/kernel/sys_arm.c index d2b177905cdb..76cbb055dd05 100644 --- a/arch/arm/kernel/sys_arm.c +++ b/arch/arm/kernel/sys_arm.c @@ -115,7 +115,7 @@ int kernel_execve(const char *filename, "Ir" (THREAD_START_SP - sizeof(regs)), "r" (®s), "Ir" (sizeof(regs)) - : "r0", "r1", "r2", "r3", "ip", "lr", "memory"); + : "r0", "r1", "r2", "r3", "r8", "r9", "ip", "lr", "memory"); out: return ret; diff --git a/arch/arm/kernel/thumbee.c b/arch/arm/kernel/thumbee.c index aab899764053..7b8403b76666 100644 --- a/arch/arm/kernel/thumbee.c +++ b/arch/arm/kernel/thumbee.c @@ -20,6 +20,7 @@ #include <linux/kernel.h> #include <linux/init.h> +#include <asm/cputype.h> #include <asm/system_info.h> #include <asm/thread_notify.h> @@ -67,8 +68,7 @@ static int __init thumbee_init(void) if (cpu_arch < CPU_ARCH_ARMv7) return 0; - /* processor feature register 0 */ - asm("mrc p15, 0, %0, c0, c1, 0\n" : "=r" (pfr0)); + pfr0 = read_cpuid_ext(CPUID_EXT_PFR0); if ((pfr0 & 0x0000f000) != 0x00001000) return 0; diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c index fe31b22f18fd..af2afb019672 100644 --- a/arch/arm/kernel/time.c +++ b/arch/arm/kernel/time.c @@ -110,6 +110,42 @@ void timer_tick(void) } #endif +static void dummy_clock_access(struct timespec *ts) +{ + ts->tv_sec = 0; + ts->tv_nsec = 0; +} + +static clock_access_fn __read_persistent_clock = dummy_clock_access; +static clock_access_fn __read_boot_clock = dummy_clock_access;; + +void read_persistent_clock(struct timespec *ts) +{ + __read_persistent_clock(ts); +} + +void read_boot_clock(struct timespec *ts) +{ + __read_boot_clock(ts); +} + +int __init register_persistent_clock(clock_access_fn read_boot, + clock_access_fn read_persistent) +{ + /* Only allow the clockaccess functions to be registered once */ + if (__read_persistent_clock == dummy_clock_access && + __read_boot_clock == dummy_clock_access) { + if (read_boot) + __read_boot_clock = read_boot; + if (read_persistent) + __read_persistent_clock = read_persistent; + + return 0; + } + + return -EINVAL; +} + #if defined(CONFIG_PM) && !defined(CONFIG_GENERIC_CLOCKEVENTS) static int timer_suspend(void) { diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c index 778454750a6c..3647170e9a16 100644 --- a/arch/arm/kernel/traps.c +++ b/arch/arm/kernel/traps.c @@ -479,14 +479,14 @@ static int bad_syscall(int n, struct pt_regs *regs) return regs->ARM_r0; } -static inline void +static inline int do_cache_op(unsigned long start, unsigned long end, int flags) { struct mm_struct *mm = current->active_mm; struct vm_area_struct *vma; if (end < start || flags) - return; + return -EINVAL; down_read(&mm->mmap_sem); vma = find_vma(mm, start); @@ -496,9 +496,11 @@ do_cache_op(unsigned long start, unsigned long end, int flags) if (end > vma->vm_end) end = vma->vm_end; - flush_cache_user_range(vma, start, end); + up_read(&mm->mmap_sem); + return flush_cache_user_range(start, end); } up_read(&mm->mmap_sem); + return -EINVAL; } /* @@ -544,8 +546,7 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs) * the specified region). */ case NR(cacheflush): - do_cache_op(regs->ARM_r0, regs->ARM_r1, regs->ARM_r2); - return 0; + return do_cache_op(regs->ARM_r0, regs->ARM_r1, regs->ARM_r2); case NR(usr26): if (!(elf_hwcap & HWCAP_26BIT)) diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 0ade0acc1ed9..992769ae2599 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -17,30 +17,13 @@ lib-y := backtrace.o changebit.o csumipv6.o csumpartial.o \ call_with_stack.o mmu-y := clear_user.o copy_page.o getuser.o putuser.o - -# the code in uaccess.S is not preemption safe and -# probably faster on ARMv3 only -ifeq ($(CONFIG_PREEMPT),y) - mmu-y += copy_from_user.o copy_to_user.o -else -ifneq ($(CONFIG_CPU_32v3),y) - mmu-y += copy_from_user.o copy_to_user.o -else - mmu-y += uaccess.o -endif -endif +mmu-y += copy_from_user.o copy_to_user.o # using lib_ here won't override already available weak symbols obj-$(CONFIG_UACCESS_WITH_MEMCPY) += uaccess_with_memcpy.o -lib-$(CONFIG_MMU) += $(mmu-y) - -ifeq ($(CONFIG_CPU_32v3),y) - lib-y += io-readsw-armv3.o io-writesw-armv3.o -else - lib-y += io-readsw-armv4.o io-writesw-armv4.o -endif - +lib-$(CONFIG_MMU) += $(mmu-y) +lib-y += io-readsw-armv4.o io-writesw-armv4.o lib-$(CONFIG_ARCH_RPC) += ecard.o io-acorn.o floppydma.o lib-$(CONFIG_ARCH_SHARK) += io-shark.o diff --git a/arch/arm/lib/io-readsw-armv3.S b/arch/arm/lib/io-readsw-armv3.S deleted file mode 100644 index 88487c8c4f23..000000000000 --- a/arch/arm/lib/io-readsw-armv3.S +++ /dev/null @@ -1,106 +0,0 @@ -/* - * linux/arch/arm/lib/io-readsw-armv3.S - * - * Copyright (C) 1995-2000 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <linux/linkage.h> -#include <asm/assembler.h> - -.Linsw_bad_alignment: - adr r0, .Linsw_bad_align_msg - mov r2, lr - b panic -.Linsw_bad_align_msg: - .asciz "insw: bad buffer alignment (0x%p, lr=0x%08lX)\n" - .align - -.Linsw_align: tst r1, #1 - bne .Linsw_bad_alignment - - ldr r3, [r0] - strb r3, [r1], #1 - mov r3, r3, lsr #8 - strb r3, [r1], #1 - - subs r2, r2, #1 - moveq pc, lr - -ENTRY(__raw_readsw) - teq r2, #0 @ do we have to check for the zero len? - moveq pc, lr - tst r1, #3 - bne .Linsw_align - -.Linsw_aligned: mov ip, #0xff - orr ip, ip, ip, lsl #8 - stmfd sp!, {r4, r5, r6, lr} - - subs r2, r2, #8 - bmi .Lno_insw_8 - -.Linsw_8_lp: ldr r3, [r0] - and r3, r3, ip - ldr r4, [r0] - orr r3, r3, r4, lsl #16 - - ldr r4, [r0] - and r4, r4, ip - ldr r5, [r0] - orr r4, r4, r5, lsl #16 - - ldr r5, [r0] - and r5, r5, ip - ldr r6, [r0] - orr r5, r5, r6, lsl #16 - - ldr r6, [r0] - and r6, r6, ip - ldr lr, [r0] - orr r6, r6, lr, lsl #16 - - stmia r1!, {r3 - r6} - - subs r2, r2, #8 - bpl .Linsw_8_lp - - tst r2, #7 - ldmeqfd sp!, {r4, r5, r6, pc} - -.Lno_insw_8: tst r2, #4 - beq .Lno_insw_4 - - ldr r3, [r0] - and r3, r3, ip - ldr r4, [r0] - orr r3, r3, r4, lsl #16 - - ldr r4, [r0] - and r4, r4, ip - ldr r5, [r0] - orr r4, r4, r5, lsl #16 - - stmia r1!, {r3, r4} - -.Lno_insw_4: tst r2, #2 - beq .Lno_insw_2 - - ldr r3, [r0] - and r3, r3, ip - ldr r4, [r0] - orr r3, r3, r4, lsl #16 - - str r3, [r1], #4 - -.Lno_insw_2: tst r2, #1 - ldrne r3, [r0] - strneb r3, [r1], #1 - movne r3, r3, lsr #8 - strneb r3, [r1] - - ldmfd sp!, {r4, r5, r6, pc} - - diff --git a/arch/arm/lib/io-writesw-armv3.S b/arch/arm/lib/io-writesw-armv3.S deleted file mode 100644 index 49b800419e32..000000000000 --- a/arch/arm/lib/io-writesw-armv3.S +++ /dev/null @@ -1,126 +0,0 @@ -/* - * linux/arch/arm/lib/io-writesw-armv3.S - * - * Copyright (C) 1995-2000 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <linux/linkage.h> -#include <asm/assembler.h> - -.Loutsw_bad_alignment: - adr r0, .Loutsw_bad_align_msg - mov r2, lr - b panic -.Loutsw_bad_align_msg: - .asciz "outsw: bad buffer alignment (0x%p, lr=0x%08lX)\n" - .align - -.Loutsw_align: tst r1, #1 - bne .Loutsw_bad_alignment - - add r1, r1, #2 - - ldr r3, [r1, #-4] - mov r3, r3, lsr #16 - orr r3, r3, r3, lsl #16 - str r3, [r0] - subs r2, r2, #1 - moveq pc, lr - -ENTRY(__raw_writesw) - teq r2, #0 @ do we have to check for the zero len? - moveq pc, lr - tst r1, #3 - bne .Loutsw_align - - stmfd sp!, {r4, r5, r6, lr} - - subs r2, r2, #8 - bmi .Lno_outsw_8 - -.Loutsw_8_lp: ldmia r1!, {r3, r4, r5, r6} - - mov ip, r3, lsl #16 - orr ip, ip, ip, lsr #16 - str ip, [r0] - - mov ip, r3, lsr #16 - orr ip, ip, ip, lsl #16 - str ip, [r0] - - mov ip, r4, lsl #16 - orr ip, ip, ip, lsr #16 - str ip, [r0] - - mov ip, r4, lsr #16 - orr ip, ip, ip, lsl #16 - str ip, [r0] - - mov ip, r5, lsl #16 - orr ip, ip, ip, lsr #16 - str ip, [r0] - - mov ip, r5, lsr #16 - orr ip, ip, ip, lsl #16 - str ip, [r0] - - mov ip, r6, lsl #16 - orr ip, ip, ip, lsr #16 - str ip, [r0] - - mov ip, r6, lsr #16 - orr ip, ip, ip, lsl #16 - str ip, [r0] - - subs r2, r2, #8 - bpl .Loutsw_8_lp - - tst r2, #7 - ldmeqfd sp!, {r4, r5, r6, pc} - -.Lno_outsw_8: tst r2, #4 - beq .Lno_outsw_4 - - ldmia r1!, {r3, r4} - - mov ip, r3, lsl #16 - orr ip, ip, ip, lsr #16 - str ip, [r0] - - mov ip, r3, lsr #16 - orr ip, ip, ip, lsl #16 - str ip, [r0] - - mov ip, r4, lsl #16 - orr ip, ip, ip, lsr #16 - str ip, [r0] - - mov ip, r4, lsr #16 - orr ip, ip, ip, lsl #16 - str ip, [r0] - -.Lno_outsw_4: tst r2, #2 - beq .Lno_outsw_2 - - ldr r3, [r1], #4 - - mov ip, r3, lsl #16 - orr ip, ip, ip, lsr #16 - str ip, [r0] - - mov ip, r3, lsr #16 - orr ip, ip, ip, lsl #16 - str ip, [r0] - -.Lno_outsw_2: tst r2, #1 - - ldrne r3, [r1] - - movne ip, r3, lsl #16 - orrne ip, ip, ip, lsr #16 - strne ip, [r0] - - ldmfd sp!, {r4, r5, r6, pc} diff --git a/arch/arm/lib/uaccess.S b/arch/arm/lib/uaccess.S deleted file mode 100644 index 5c908b1cb8ed..000000000000 --- a/arch/arm/lib/uaccess.S +++ /dev/null @@ -1,564 +0,0 @@ -/* - * linux/arch/arm/lib/uaccess.S - * - * Copyright (C) 1995, 1996,1997,1998 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Routines to block copy data to/from user memory - * These are highly optimised both for the 4k page size - * and for various alignments. - */ -#include <linux/linkage.h> -#include <asm/assembler.h> -#include <asm/errno.h> -#include <asm/domain.h> - - .text - -#define PAGE_SHIFT 12 - -/* Prototype: int __copy_to_user(void *to, const char *from, size_t n) - * Purpose : copy a block to user memory from kernel memory - * Params : to - user memory - * : from - kernel memory - * : n - number of bytes to copy - * Returns : Number of bytes NOT copied. - */ - -.Lc2u_dest_not_aligned: - rsb ip, ip, #4 - cmp ip, #2 - ldrb r3, [r1], #1 -USER( TUSER( strb) r3, [r0], #1) @ May fault - ldrgeb r3, [r1], #1 -USER( TUSER( strgeb) r3, [r0], #1) @ May fault - ldrgtb r3, [r1], #1 -USER( TUSER( strgtb) r3, [r0], #1) @ May fault - sub r2, r2, ip - b .Lc2u_dest_aligned - -ENTRY(__copy_to_user) - stmfd sp!, {r2, r4 - r7, lr} - cmp r2, #4 - blt .Lc2u_not_enough - ands ip, r0, #3 - bne .Lc2u_dest_not_aligned -.Lc2u_dest_aligned: - - ands ip, r1, #3 - bne .Lc2u_src_not_aligned -/* - * Seeing as there has to be at least 8 bytes to copy, we can - * copy one word, and force a user-mode page fault... - */ - -.Lc2u_0fupi: subs r2, r2, #4 - addmi ip, r2, #4 - bmi .Lc2u_0nowords - ldr r3, [r1], #4 -USER( TUSER( str) r3, [r0], #4) @ May fault - mov ip, r0, lsl #32 - PAGE_SHIFT @ On each page, use a ld/st??t instruction - rsb ip, ip, #0 - movs ip, ip, lsr #32 - PAGE_SHIFT - beq .Lc2u_0fupi -/* - * ip = max no. of bytes to copy before needing another "strt" insn - */ - cmp r2, ip - movlt ip, r2 - sub r2, r2, ip - subs ip, ip, #32 - blt .Lc2u_0rem8lp - -.Lc2u_0cpy8lp: ldmia r1!, {r3 - r6} - stmia r0!, {r3 - r6} @ Shouldnt fault - ldmia r1!, {r3 - r6} - subs ip, ip, #32 - stmia r0!, {r3 - r6} @ Shouldnt fault - bpl .Lc2u_0cpy8lp - -.Lc2u_0rem8lp: cmn ip, #16 - ldmgeia r1!, {r3 - r6} - stmgeia r0!, {r3 - r6} @ Shouldnt fault - tst ip, #8 - ldmneia r1!, {r3 - r4} - stmneia r0!, {r3 - r4} @ Shouldnt fault - tst ip, #4 - ldrne r3, [r1], #4 - TUSER( strne) r3, [r0], #4 @ Shouldnt fault - ands ip, ip, #3 - beq .Lc2u_0fupi -.Lc2u_0nowords: teq ip, #0 - beq .Lc2u_finished -.Lc2u_nowords: cmp ip, #2 - ldrb r3, [r1], #1 -USER( TUSER( strb) r3, [r0], #1) @ May fault - ldrgeb r3, [r1], #1 -USER( TUSER( strgeb) r3, [r0], #1) @ May fault - ldrgtb r3, [r1], #1 -USER( TUSER( strgtb) r3, [r0], #1) @ May fault - b .Lc2u_finished - -.Lc2u_not_enough: - movs ip, r2 - bne .Lc2u_nowords -.Lc2u_finished: mov r0, #0 - ldmfd sp!, {r2, r4 - r7, pc} - -.Lc2u_src_not_aligned: - bic r1, r1, #3 - ldr r7, [r1], #4 - cmp ip, #2 - bgt .Lc2u_3fupi - beq .Lc2u_2fupi -.Lc2u_1fupi: subs r2, r2, #4 - addmi ip, r2, #4 - bmi .Lc2u_1nowords - mov r3, r7, pull #8 - ldr r7, [r1], #4 - orr r3, r3, r7, push #24 -USER( TUSER( str) r3, [r0], #4) @ May fault - mov ip, r0, lsl #32 - PAGE_SHIFT - rsb ip, ip, #0 - movs ip, ip, lsr #32 - PAGE_SHIFT - beq .Lc2u_1fupi - cmp r2, ip - movlt ip, r2 - sub r2, r2, ip - subs ip, ip, #16 - blt .Lc2u_1rem8lp - -.Lc2u_1cpy8lp: mov r3, r7, pull #8 - ldmia r1!, {r4 - r7} - subs ip, ip, #16 - orr r3, r3, r4, push #24 - mov r4, r4, pull #8 - orr r4, r4, r5, push #24 - mov r5, r5, pull #8 - orr r5, r5, r6, push #24 - mov r6, r6, pull #8 - orr r6, r6, r7, push #24 - stmia r0!, {r3 - r6} @ Shouldnt fault - bpl .Lc2u_1cpy8lp - -.Lc2u_1rem8lp: tst ip, #8 - movne r3, r7, pull #8 - ldmneia r1!, {r4, r7} - orrne r3, r3, r4, push #24 - movne r4, r4, pull #8 - orrne r4, r4, r7, push #24 - stmneia r0!, {r3 - r4} @ Shouldnt fault - tst ip, #4 - movne r3, r7, pull #8 - ldrne r7, [r1], #4 - orrne r3, r3, r7, push #24 - TUSER( strne) r3, [r0], #4 @ Shouldnt fault - ands ip, ip, #3 - beq .Lc2u_1fupi -.Lc2u_1nowords: mov r3, r7, get_byte_1 - teq ip, #0 - beq .Lc2u_finished - cmp ip, #2 -USER( TUSER( strb) r3, [r0], #1) @ May fault - movge r3, r7, get_byte_2 -USER( TUSER( strgeb) r3, [r0], #1) @ May fault - movgt r3, r7, get_byte_3 -USER( TUSER( strgtb) r3, [r0], #1) @ May fault - b .Lc2u_finished - -.Lc2u_2fupi: subs r2, r2, #4 - addmi ip, r2, #4 - bmi .Lc2u_2nowords - mov r3, r7, pull #16 - ldr r7, [r1], #4 - orr r3, r3, r7, push #16 -USER( TUSER( str) r3, [r0], #4) @ May fault - mov ip, r0, lsl #32 - PAGE_SHIFT - rsb ip, ip, #0 - movs ip, ip, lsr #32 - PAGE_SHIFT - beq .Lc2u_2fupi - cmp r2, ip - movlt ip, r2 - sub r2, r2, ip - subs ip, ip, #16 - blt .Lc2u_2rem8lp - -.Lc2u_2cpy8lp: mov r3, r7, pull #16 - ldmia r1!, {r4 - r7} - subs ip, ip, #16 - orr r3, r3, r4, push #16 - mov r4, r4, pull #16 - orr r4, r4, r5, push #16 - mov r5, r5, pull #16 - orr r5, r5, r6, push #16 - mov r6, r6, pull #16 - orr r6, r6, r7, push #16 - stmia r0!, {r3 - r6} @ Shouldnt fault - bpl .Lc2u_2cpy8lp - -.Lc2u_2rem8lp: tst ip, #8 - movne r3, r7, pull #16 - ldmneia r1!, {r4, r7} - orrne r3, r3, r4, push #16 - movne r4, r4, pull #16 - orrne r4, r4, r7, push #16 - stmneia r0!, {r3 - r4} @ Shouldnt fault - tst ip, #4 - movne r3, r7, pull #16 - ldrne r7, [r1], #4 - orrne r3, r3, r7, push #16 - TUSER( strne) r3, [r0], #4 @ Shouldnt fault - ands ip, ip, #3 - beq .Lc2u_2fupi -.Lc2u_2nowords: mov r3, r7, get_byte_2 - teq ip, #0 - beq .Lc2u_finished - cmp ip, #2 -USER( TUSER( strb) r3, [r0], #1) @ May fault - movge r3, r7, get_byte_3 -USER( TUSER( strgeb) r3, [r0], #1) @ May fault - ldrgtb r3, [r1], #0 -USER( TUSER( strgtb) r3, [r0], #1) @ May fault - b .Lc2u_finished - -.Lc2u_3fupi: subs r2, r2, #4 - addmi ip, r2, #4 - bmi .Lc2u_3nowords - mov r3, r7, pull #24 - ldr r7, [r1], #4 - orr r3, r3, r7, push #8 -USER( TUSER( str) r3, [r0], #4) @ May fault - mov ip, r0, lsl #32 - PAGE_SHIFT - rsb ip, ip, #0 - movs ip, ip, lsr #32 - PAGE_SHIFT - beq .Lc2u_3fupi - cmp r2, ip - movlt ip, r2 - sub r2, r2, ip - subs ip, ip, #16 - blt .Lc2u_3rem8lp - -.Lc2u_3cpy8lp: mov r3, r7, pull #24 - ldmia r1!, {r4 - r7} - subs ip, ip, #16 - orr r3, r3, r4, push #8 - mov r4, r4, pull #24 - orr r4, r4, r5, push #8 - mov r5, r5, pull #24 - orr r5, r5, r6, push #8 - mov r6, r6, pull #24 - orr r6, r6, r7, push #8 - stmia r0!, {r3 - r6} @ Shouldnt fault - bpl .Lc2u_3cpy8lp - -.Lc2u_3rem8lp: tst ip, #8 - movne r3, r7, pull #24 - ldmneia r1!, {r4, r7} - orrne r3, r3, r4, push #8 - movne r4, r4, pull #24 - orrne r4, r4, r7, push #8 - stmneia r0!, {r3 - r4} @ Shouldnt fault - tst ip, #4 - movne r3, r7, pull #24 - ldrne r7, [r1], #4 - orrne r3, r3, r7, push #8 - TUSER( strne) r3, [r0], #4 @ Shouldnt fault - ands ip, ip, #3 - beq .Lc2u_3fupi -.Lc2u_3nowords: mov r3, r7, get_byte_3 - teq ip, #0 - beq .Lc2u_finished - cmp ip, #2 -USER( TUSER( strb) r3, [r0], #1) @ May fault - ldrgeb r3, [r1], #1 -USER( TUSER( strgeb) r3, [r0], #1) @ May fault - ldrgtb r3, [r1], #0 -USER( TUSER( strgtb) r3, [r0], #1) @ May fault - b .Lc2u_finished -ENDPROC(__copy_to_user) - - .pushsection .fixup,"ax" - .align 0 -9001: ldmfd sp!, {r0, r4 - r7, pc} - .popsection - -/* Prototype: unsigned long __copy_from_user(void *to,const void *from,unsigned long n); - * Purpose : copy a block from user memory to kernel memory - * Params : to - kernel memory - * : from - user memory - * : n - number of bytes to copy - * Returns : Number of bytes NOT copied. - */ -.Lcfu_dest_not_aligned: - rsb ip, ip, #4 - cmp ip, #2 -USER( TUSER( ldrb) r3, [r1], #1) @ May fault - strb r3, [r0], #1 -USER( TUSER( ldrgeb) r3, [r1], #1) @ May fault - strgeb r3, [r0], #1 -USER( TUSER( ldrgtb) r3, [r1], #1) @ May fault - strgtb r3, [r0], #1 - sub r2, r2, ip - b .Lcfu_dest_aligned - -ENTRY(__copy_from_user) - stmfd sp!, {r0, r2, r4 - r7, lr} - cmp r2, #4 - blt .Lcfu_not_enough - ands ip, r0, #3 - bne .Lcfu_dest_not_aligned -.Lcfu_dest_aligned: - ands ip, r1, #3 - bne .Lcfu_src_not_aligned - -/* - * Seeing as there has to be at least 8 bytes to copy, we can - * copy one word, and force a user-mode page fault... - */ - -.Lcfu_0fupi: subs r2, r2, #4 - addmi ip, r2, #4 - bmi .Lcfu_0nowords -USER( TUSER( ldr) r3, [r1], #4) - str r3, [r0], #4 - mov ip, r1, lsl #32 - PAGE_SHIFT @ On each page, use a ld/st??t instruction - rsb ip, ip, #0 - movs ip, ip, lsr #32 - PAGE_SHIFT - beq .Lcfu_0fupi -/* - * ip = max no. of bytes to copy before needing another "strt" insn - */ - cmp r2, ip - movlt ip, r2 - sub r2, r2, ip - subs ip, ip, #32 - blt .Lcfu_0rem8lp - -.Lcfu_0cpy8lp: ldmia r1!, {r3 - r6} @ Shouldnt fault - stmia r0!, {r3 - r6} - ldmia r1!, {r3 - r6} @ Shouldnt fault - subs ip, ip, #32 - stmia r0!, {r3 - r6} - bpl .Lcfu_0cpy8lp - -.Lcfu_0rem8lp: cmn ip, #16 - ldmgeia r1!, {r3 - r6} @ Shouldnt fault - stmgeia r0!, {r3 - r6} - tst ip, #8 - ldmneia r1!, {r3 - r4} @ Shouldnt fault - stmneia r0!, {r3 - r4} - tst ip, #4 - TUSER( ldrne) r3, [r1], #4 @ Shouldnt fault - strne r3, [r0], #4 - ands ip, ip, #3 - beq .Lcfu_0fupi -.Lcfu_0nowords: teq ip, #0 - beq .Lcfu_finished -.Lcfu_nowords: cmp ip, #2 -USER( TUSER( ldrb) r3, [r1], #1) @ May fault - strb r3, [r0], #1 -USER( TUSER( ldrgeb) r3, [r1], #1) @ May fault - strgeb r3, [r0], #1 -USER( TUSER( ldrgtb) r3, [r1], #1) @ May fault - strgtb r3, [r0], #1 - b .Lcfu_finished - -.Lcfu_not_enough: - movs ip, r2 - bne .Lcfu_nowords -.Lcfu_finished: mov r0, #0 - add sp, sp, #8 - ldmfd sp!, {r4 - r7, pc} - -.Lcfu_src_not_aligned: - bic r1, r1, #3 -USER( TUSER( ldr) r7, [r1], #4) @ May fault - cmp ip, #2 - bgt .Lcfu_3fupi - beq .Lcfu_2fupi -.Lcfu_1fupi: subs r2, r2, #4 - addmi ip, r2, #4 - bmi .Lcfu_1nowords - mov r3, r7, pull #8 -USER( TUSER( ldr) r7, [r1], #4) @ May fault - orr r3, r3, r7, push #24 - str r3, [r0], #4 - mov ip, r1, lsl #32 - PAGE_SHIFT - rsb ip, ip, #0 - movs ip, ip, lsr #32 - PAGE_SHIFT - beq .Lcfu_1fupi - cmp r2, ip - movlt ip, r2 - sub r2, r2, ip - subs ip, ip, #16 - blt .Lcfu_1rem8lp - -.Lcfu_1cpy8lp: mov r3, r7, pull #8 - ldmia r1!, {r4 - r7} @ Shouldnt fault - subs ip, ip, #16 - orr r3, r3, r4, push #24 - mov r4, r4, pull #8 - orr r4, r4, r5, push #24 - mov r5, r5, pull #8 - orr r5, r5, r6, push #24 - mov r6, r6, pull #8 - orr r6, r6, r7, push #24 - stmia r0!, {r3 - r6} - bpl .Lcfu_1cpy8lp - -.Lcfu_1rem8lp: tst ip, #8 - movne r3, r7, pull #8 - ldmneia r1!, {r4, r7} @ Shouldnt fault - orrne r3, r3, r4, push #24 - movne r4, r4, pull #8 - orrne r4, r4, r7, push #24 - stmneia r0!, {r3 - r4} - tst ip, #4 - movne r3, r7, pull #8 -USER( TUSER( ldrne) r7, [r1], #4) @ May fault - orrne r3, r3, r7, push #24 - strne r3, [r0], #4 - ands ip, ip, #3 - beq .Lcfu_1fupi -.Lcfu_1nowords: mov r3, r7, get_byte_1 - teq ip, #0 - beq .Lcfu_finished - cmp ip, #2 - strb r3, [r0], #1 - movge r3, r7, get_byte_2 - strgeb r3, [r0], #1 - movgt r3, r7, get_byte_3 - strgtb r3, [r0], #1 - b .Lcfu_finished - -.Lcfu_2fupi: subs r2, r2, #4 - addmi ip, r2, #4 - bmi .Lcfu_2nowords - mov r3, r7, pull #16 -USER( TUSER( ldr) r7, [r1], #4) @ May fault - orr r3, r3, r7, push #16 - str r3, [r0], #4 - mov ip, r1, lsl #32 - PAGE_SHIFT - rsb ip, ip, #0 - movs ip, ip, lsr #32 - PAGE_SHIFT - beq .Lcfu_2fupi - cmp r2, ip - movlt ip, r2 - sub r2, r2, ip - subs ip, ip, #16 - blt .Lcfu_2rem8lp - - -.Lcfu_2cpy8lp: mov r3, r7, pull #16 - ldmia r1!, {r4 - r7} @ Shouldnt fault - subs ip, ip, #16 - orr r3, r3, r4, push #16 - mov r4, r4, pull #16 - orr r4, r4, r5, push #16 - mov r5, r5, pull #16 - orr r5, r5, r6, push #16 - mov r6, r6, pull #16 - orr r6, r6, r7, push #16 - stmia r0!, {r3 - r6} - bpl .Lcfu_2cpy8lp - -.Lcfu_2rem8lp: tst ip, #8 - movne r3, r7, pull #16 - ldmneia r1!, {r4, r7} @ Shouldnt fault - orrne r3, r3, r4, push #16 - movne r4, r4, pull #16 - orrne r4, r4, r7, push #16 - stmneia r0!, {r3 - r4} - tst ip, #4 - movne r3, r7, pull #16 -USER( TUSER( ldrne) r7, [r1], #4) @ May fault - orrne r3, r3, r7, push #16 - strne r3, [r0], #4 - ands ip, ip, #3 - beq .Lcfu_2fupi -.Lcfu_2nowords: mov r3, r7, get_byte_2 - teq ip, #0 - beq .Lcfu_finished - cmp ip, #2 - strb r3, [r0], #1 - movge r3, r7, get_byte_3 - strgeb r3, [r0], #1 -USER( TUSER( ldrgtb) r3, [r1], #0) @ May fault - strgtb r3, [r0], #1 - b .Lcfu_finished - -.Lcfu_3fupi: subs r2, r2, #4 - addmi ip, r2, #4 - bmi .Lcfu_3nowords - mov r3, r7, pull #24 -USER( TUSER( ldr) r7, [r1], #4) @ May fault - orr r3, r3, r7, push #8 - str r3, [r0], #4 - mov ip, r1, lsl #32 - PAGE_SHIFT - rsb ip, ip, #0 - movs ip, ip, lsr #32 - PAGE_SHIFT - beq .Lcfu_3fupi - cmp r2, ip - movlt ip, r2 - sub r2, r2, ip - subs ip, ip, #16 - blt .Lcfu_3rem8lp - -.Lcfu_3cpy8lp: mov r3, r7, pull #24 - ldmia r1!, {r4 - r7} @ Shouldnt fault - orr r3, r3, r4, push #8 - mov r4, r4, pull #24 - orr r4, r4, r5, push #8 - mov r5, r5, pull #24 - orr r5, r5, r6, push #8 - mov r6, r6, pull #24 - orr r6, r6, r7, push #8 - stmia r0!, {r3 - r6} - subs ip, ip, #16 - bpl .Lcfu_3cpy8lp - -.Lcfu_3rem8lp: tst ip, #8 - movne r3, r7, pull #24 - ldmneia r1!, {r4, r7} @ Shouldnt fault - orrne r3, r3, r4, push #8 - movne r4, r4, pull #24 - orrne r4, r4, r7, push #8 - stmneia r0!, {r3 - r4} - tst ip, #4 - movne r3, r7, pull #24 -USER( TUSER( ldrne) r7, [r1], #4) @ May fault - orrne r3, r3, r7, push #8 - strne r3, [r0], #4 - ands ip, ip, #3 - beq .Lcfu_3fupi -.Lcfu_3nowords: mov r3, r7, get_byte_3 - teq ip, #0 - beq .Lcfu_finished - cmp ip, #2 - strb r3, [r0], #1 -USER( TUSER( ldrgeb) r3, [r1], #1) @ May fault - strgeb r3, [r0], #1 -USER( TUSER( ldrgtb) r3, [r1], #1) @ May fault - strgtb r3, [r0], #1 - b .Lcfu_finished -ENDPROC(__copy_from_user) - - .pushsection .fixup,"ax" - .align 0 - /* - * We took an exception. r0 contains a pointer to - * the byte not copied. - */ -9001: ldr r2, [sp], #4 @ void *to - sub r2, r0, r2 @ bytes copied - ldr r1, [sp], #4 @ unsigned long count - subs r4, r1, r2 @ bytes left to copy - movne r1, r4 - blne __memzero - mov r0, r4 - ldmfd sp!, {r4 - r7, pc} - .popsection - diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c index 364c19357e60..89106792d067 100644 --- a/arch/arm/mach-at91/at91rm9200.c +++ b/arch/arm/mach-at91/at91rm9200.c @@ -26,15 +26,6 @@ #include "clock.h" #include "sam9_smc.h" -static struct map_desc at91rm9200_io_desc[] __initdata = { - { - .virtual = AT91_VA_BASE_EMAC, - .pfn = __phys_to_pfn(AT91RM9200_BASE_EMAC), - .length = SZ_16K, - .type = MT_DEVICE, - }, -}; - /* -------------------------------------------------------------------- * Clocks * -------------------------------------------------------------------- */ @@ -315,7 +306,6 @@ static void __init at91rm9200_map_io(void) { /* Map peripherals */ at91_init_sram(0, AT91RM9200_SRAM_BASE, AT91RM9200_SRAM_SIZE); - iotable_init(at91rm9200_io_desc, ARRAY_SIZE(at91rm9200_io_desc)); } static void __init at91rm9200_ioremap_registers(void) diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c index 99ce5c955e39..60c472861e5e 100644 --- a/arch/arm/mach-at91/at91rm9200_devices.c +++ b/arch/arm/mach-at91/at91rm9200_devices.c @@ -140,8 +140,8 @@ static struct macb_platform_data eth_data; static struct resource eth_resources[] = { [0] = { - .start = AT91_VA_BASE_EMAC, - .end = AT91_VA_BASE_EMAC + SZ_16K - 1, + .start = AT91RM9200_BASE_EMAC, + .end = AT91RM9200_BASE_EMAC + SZ_16K - 1, .flags = IORESOURCE_MEM, }, [1] = { @@ -1173,7 +1173,6 @@ void __init at91_add_device_serial(void) printk(KERN_INFO "AT91: No default serial console defined.\n"); } #else -void __init __deprecated at91_init_serial(struct at91_uart_config *config) {} void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {} void __init at91_set_serial_console(unsigned portnr) {} void __init at91_add_device_serial(void) {} diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c index dd7f782b0b91..104ca40d8d18 100644 --- a/arch/arm/mach-at91/at91rm9200_time.c +++ b/arch/arm/mach-at91/at91rm9200_time.c @@ -23,6 +23,7 @@ #include <linux/interrupt.h> #include <linux/irq.h> #include <linux/clockchips.h> +#include <linux/export.h> #include <asm/mach/time.h> @@ -176,6 +177,7 @@ static struct clock_event_device clkevt = { }; void __iomem *at91_st_base; +EXPORT_SYMBOL_GPL(at91_st_base); void __init at91rm9200_ioremap_st(u32 addr) { diff --git a/arch/arm/mach-at91/board-rm9200ek.c b/arch/arm/mach-at91/board-rm9200ek.c index 11cbaa8946fe..b2e4fe21f346 100644 --- a/arch/arm/mach-at91/board-rm9200ek.c +++ b/arch/arm/mach-at91/board-rm9200ek.c @@ -117,7 +117,7 @@ static struct i2c_board_info __initdata ek_i2c_devices[] = { }; #define EK_FLASH_BASE AT91_CHIPSELECT_0 -#define EK_FLASH_SIZE SZ_2M +#define EK_FLASH_SIZE SZ_8M static struct physmap_flash_data ek_flash_data = { .width = 2, diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c index c3f994462864..065fed342424 100644 --- a/arch/arm/mach-at91/board-sam9261ek.c +++ b/arch/arm/mach-at91/board-sam9261ek.c @@ -85,8 +85,6 @@ static struct resource dm9000_resource[] = { .flags = IORESOURCE_MEM }, [2] = { - .start = AT91_PIN_PC11, - .end = AT91_PIN_PC11, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE | IORESOURCE_IRQ_HIGHEDGE, } @@ -130,6 +128,8 @@ static struct sam9_smc_config __initdata dm9000_smc_config = { static void __init ek_add_device_dm9000(void) { + struct resource *r = &dm9000_resource[2]; + /* Configure chip-select 2 (DM9000) */ sam9_smc_configure(0, 2, &dm9000_smc_config); @@ -139,6 +139,7 @@ static void __init ek_add_device_dm9000(void) /* Configure Interrupt pin as input, no pull-up */ at91_set_gpio_input(AT91_PIN_PC11, 0); + r->start = r->end = gpio_to_irq(AT91_PIN_PC11); platform_device_register(&dm9000_device); } #else diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c index a0f4d7424cdc..6b692824c988 100644 --- a/arch/arm/mach-at91/clock.c +++ b/arch/arm/mach-at91/clock.c @@ -35,6 +35,7 @@ #include "generic.h" void __iomem *at91_pmc_base; +EXPORT_SYMBOL_GPL(at91_pmc_base); /* * There's a lot more which can be done with clocks, including cpufreq diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h index 36604782a78f..ea2c57a86ca6 100644 --- a/arch/arm/mach-at91/include/mach/at91_pmc.h +++ b/arch/arm/mach-at91/include/mach/at91_pmc.h @@ -25,7 +25,7 @@ extern void __iomem *at91_pmc_base; #define at91_pmc_write(field, value) \ __raw_writel(value, at91_pmc_base + field) #else -.extern at91_aic_base +.extern at91_pmc_base #endif #define AT91_PMC_SCER 0x00 /* System Clock Enable Register */ diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h index e9e29a6c3868..01db372be8e5 100644 --- a/arch/arm/mach-at91/include/mach/hardware.h +++ b/arch/arm/mach-at91/include/mach/hardware.h @@ -94,7 +94,6 @@ * Virtual to Physical Address mapping for IO devices. */ #define AT91_VA_BASE_SYS AT91_IO_P2V(AT91_BASE_SYS) -#define AT91_VA_BASE_EMAC AT91_IO_P2V(AT91RM9200_BASE_EMAC) /* Internal SRAM is mapped below the IO devices */ #define AT91_SRAM_MAX SZ_1M diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c index 97cc04dc8073..f44a2e7272e3 100644 --- a/arch/arm/mach-at91/setup.c +++ b/arch/arm/mach-at91/setup.c @@ -54,6 +54,7 @@ void __init at91_init_interrupts(unsigned int *priority) } void __iomem *at91_ramc_base[2]; +EXPORT_SYMBOL_GPL(at91_ramc_base); void __init at91_ioremap_ramc(int id, u32 addr, u32 size) { @@ -292,6 +293,7 @@ void __init at91_ioremap_rstc(u32 base_addr) } void __iomem *at91_matrix_base; +EXPORT_SYMBOL_GPL(at91_matrix_base); void __init at91_ioremap_matrix(u32 base_addr) { diff --git a/arch/arm/mach-bcmring/core.c b/arch/arm/mach-bcmring/core.c index 22e4e0a28ad1..adbfb1994582 100644 --- a/arch/arm/mach-bcmring/core.c +++ b/arch/arm/mach-bcmring/core.c @@ -52,8 +52,8 @@ #include <mach/csp/chipcHw_inline.h> #include <mach/csp/tmrHw_reg.h> -static AMBA_APB_DEVICE(uartA, "uarta", MM_ADDR_IO_UARTA, { IRQ_UARTA }, NULL); -static AMBA_APB_DEVICE(uartB, "uartb", MM_ADDR_IO_UARTB, { IRQ_UARTB }, NULL); +static AMBA_APB_DEVICE(uartA, "uartA", 0, MM_ADDR_IO_UARTA, {IRQ_UARTA}, NULL); +static AMBA_APB_DEVICE(uartB, "uartB", 0, MM_ADDR_IO_UARTB, {IRQ_UARTB}, NULL); static struct clk pll1_clk = { .name = "PLL1", diff --git a/arch/arm/mach-cns3xxx/pcie.c b/arch/arm/mach-cns3xxx/pcie.c index 79d001f831e0..311328314163 100644 --- a/arch/arm/mach-cns3xxx/pcie.c +++ b/arch/arm/mach-cns3xxx/pcie.c @@ -166,12 +166,6 @@ static struct pci_ops cns3xxx_pcie_ops = { .write = cns3xxx_pci_write_config, }; -static struct pci_bus *cns3xxx_pci_scan_bus(int nr, struct pci_sys_data *sys) -{ - return pci_scan_root_bus(NULL, sys->busnr, &cns3xxx_pcie_ops, sys, - &sys->resources); -} - static int cns3xxx_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev); @@ -221,10 +215,9 @@ static struct cns3xxx_pcie cns3xxx_pcie[] = { .irqs = { IRQ_CNS3XXX_PCIE0_RC, IRQ_CNS3XXX_PCIE0_DEVICE, }, .hw_pci = { .domain = 0, - .swizzle = pci_std_swizzle, .nr_controllers = 1, + .ops = &cns3xxx_pcie_ops, .setup = cns3xxx_pci_setup, - .scan = cns3xxx_pci_scan_bus, .map_irq = cns3xxx_pcie_map_irq, }, }, @@ -264,10 +257,9 @@ static struct cns3xxx_pcie cns3xxx_pcie[] = { .irqs = { IRQ_CNS3XXX_PCIE1_RC, IRQ_CNS3XXX_PCIE1_DEVICE, }, .hw_pci = { .domain = 1, - .swizzle = pci_std_swizzle, .nr_controllers = 1, + .ops = &cns3xxx_pcie_ops, .setup = cns3xxx_pci_setup, - .scan = cns3xxx_pci_scan_bus, .map_irq = cns3xxx_pcie_map_irq, }, }, diff --git a/arch/arm/mach-dove/pcie.c b/arch/arm/mach-dove/pcie.c index 48a032005ea3..47921b0cdc65 100644 --- a/arch/arm/mach-dove/pcie.c +++ b/arch/arm/mach-dove/pcie.c @@ -43,6 +43,7 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys) return 0; pp = &pcie_port[nr]; + sys->private_data = pp; pp->root_bus_nr = sys->busnr; /* @@ -93,19 +94,6 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys) return 1; } -static struct pcie_port *bus_to_port(int bus) -{ - int i; - - for (i = num_pcie_ports - 1; i >= 0; i--) { - int rbus = pcie_port[i].root_bus_nr; - if (rbus != -1 && rbus <= bus) - break; - } - - return i >= 0 ? pcie_port + i : NULL; -} - static int pcie_valid_config(struct pcie_port *pp, int bus, int dev) { /* @@ -121,7 +109,8 @@ static int pcie_valid_config(struct pcie_port *pp, int bus, int dev) static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 *val) { - struct pcie_port *pp = bus_to_port(bus->number); + struct pci_sys_data *sys = bus->sysdata; + struct pcie_port *pp = sys->private_data; unsigned long flags; int ret; @@ -140,7 +129,8 @@ static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, static int pcie_wr_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 val) { - struct pcie_port *pp = bus_to_port(bus->number); + struct pci_sys_data *sys = bus->sysdata; + struct pcie_port *pp = sys->private_data; unsigned long flags; int ret; @@ -194,14 +184,14 @@ dove_pcie_scan_bus(int nr, struct pci_sys_data *sys) static int __init dove_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { - struct pcie_port *pp = bus_to_port(dev->bus->number); + struct pci_sys_data *sys = dev->sysdata; + struct pcie_port *pp = sys->private_data; return pp->index ? IRQ_DOVE_PCIE1 : IRQ_DOVE_PCIE0; } static struct hw_pci dove_pci __initdata = { .nr_controllers = 2, - .swizzle = pci_std_swizzle, .setup = dove_pcie_setup, .scan = dove_pcie_scan_bus, .map_irq = dove_pcie_map_irq, diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 0491ceef1cda..b8df521fb68e 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -232,6 +232,9 @@ config MACH_ARMLEX4210 config MACH_UNIVERSAL_C210 bool "Mobile UNIVERSAL_C210 Board" select CPU_EXYNOS4210 + select S5P_HRT + select CLKSRC_MMIO + select HAVE_SCHED_CLOCK select S5P_GPIO_INT select S5P_DEV_FIMC0 select S5P_DEV_FIMC1 @@ -368,6 +371,7 @@ comment "Flattened Device Tree based board for EXYNOS SoCs" config MACH_EXYNOS4_DT bool "Samsung Exynos4 Machine using device tree" + depends on ARCH_EXYNOS4 select CPU_EXYNOS4210 select USE_OF select ARM_AMBA @@ -380,6 +384,7 @@ config MACH_EXYNOS4_DT config MACH_EXYNOS5_DT bool "SAMSUNG EXYNOS5 Machine using device tree" + depends on ARCH_EXYNOS5 select SOC_EXYNOS5250 select USE_OF select ARM_AMBA diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c index df54c2a92225..6efd1e5919fd 100644 --- a/arch/arm/mach-exynos/clock-exynos4.c +++ b/arch/arm/mach-exynos/clock-exynos4.c @@ -497,25 +497,25 @@ static struct clk exynos4_init_clocks_off[] = { .ctrlbit = (1 << 3), }, { .name = "hsmmc", - .devname = "s3c-sdhci.0", + .devname = "exynos4-sdhci.0", .parent = &exynos4_clk_aclk_133.clk, .enable = exynos4_clk_ip_fsys_ctrl, .ctrlbit = (1 << 5), }, { .name = "hsmmc", - .devname = "s3c-sdhci.1", + .devname = "exynos4-sdhci.1", .parent = &exynos4_clk_aclk_133.clk, .enable = exynos4_clk_ip_fsys_ctrl, .ctrlbit = (1 << 6), }, { .name = "hsmmc", - .devname = "s3c-sdhci.2", + .devname = "exynos4-sdhci.2", .parent = &exynos4_clk_aclk_133.clk, .enable = exynos4_clk_ip_fsys_ctrl, .ctrlbit = (1 << 7), }, { .name = "hsmmc", - .devname = "s3c-sdhci.3", + .devname = "exynos4-sdhci.3", .parent = &exynos4_clk_aclk_133.clk, .enable = exynos4_clk_ip_fsys_ctrl, .ctrlbit = (1 << 8), @@ -1202,7 +1202,7 @@ static struct clksrc_clk exynos4_clk_sclk_uart3 = { static struct clksrc_clk exynos4_clk_sclk_mmc0 = { .clk = { .name = "sclk_mmc", - .devname = "s3c-sdhci.0", + .devname = "exynos4-sdhci.0", .parent = &exynos4_clk_dout_mmc0.clk, .enable = exynos4_clksrc_mask_fsys_ctrl, .ctrlbit = (1 << 0), @@ -1213,7 +1213,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc0 = { static struct clksrc_clk exynos4_clk_sclk_mmc1 = { .clk = { .name = "sclk_mmc", - .devname = "s3c-sdhci.1", + .devname = "exynos4-sdhci.1", .parent = &exynos4_clk_dout_mmc1.clk, .enable = exynos4_clksrc_mask_fsys_ctrl, .ctrlbit = (1 << 4), @@ -1224,7 +1224,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc1 = { static struct clksrc_clk exynos4_clk_sclk_mmc2 = { .clk = { .name = "sclk_mmc", - .devname = "s3c-sdhci.2", + .devname = "exynos4-sdhci.2", .parent = &exynos4_clk_dout_mmc2.clk, .enable = exynos4_clksrc_mask_fsys_ctrl, .ctrlbit = (1 << 8), @@ -1235,7 +1235,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc2 = { static struct clksrc_clk exynos4_clk_sclk_mmc3 = { .clk = { .name = "sclk_mmc", - .devname = "s3c-sdhci.3", + .devname = "exynos4-sdhci.3", .parent = &exynos4_clk_dout_mmc3.clk, .enable = exynos4_clksrc_mask_fsys_ctrl, .ctrlbit = (1 << 12), @@ -1340,10 +1340,10 @@ static struct clk_lookup exynos4_clk_lookup[] = { CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk), CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk), CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk), - CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk), - CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk), - CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk), - CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk), + CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk), + CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk), + CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk), + CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk), CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0), CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0), CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1), diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c index d013982d0f8e..7ac6ff4c46bd 100644 --- a/arch/arm/mach-exynos/clock-exynos5.c +++ b/arch/arm/mach-exynos/clock-exynos5.c @@ -455,25 +455,25 @@ static struct clk exynos5_init_clocks_off[] = { .ctrlbit = (1 << 20), }, { .name = "hsmmc", - .devname = "s3c-sdhci.0", + .devname = "exynos4-sdhci.0", .parent = &exynos5_clk_aclk_200.clk, .enable = exynos5_clk_ip_fsys_ctrl, .ctrlbit = (1 << 12), }, { .name = "hsmmc", - .devname = "s3c-sdhci.1", + .devname = "exynos4-sdhci.1", .parent = &exynos5_clk_aclk_200.clk, .enable = exynos5_clk_ip_fsys_ctrl, .ctrlbit = (1 << 13), }, { .name = "hsmmc", - .devname = "s3c-sdhci.2", + .devname = "exynos4-sdhci.2", .parent = &exynos5_clk_aclk_200.clk, .enable = exynos5_clk_ip_fsys_ctrl, .ctrlbit = (1 << 14), }, { .name = "hsmmc", - .devname = "s3c-sdhci.3", + .devname = "exynos4-sdhci.3", .parent = &exynos5_clk_aclk_200.clk, .enable = exynos5_clk_ip_fsys_ctrl, .ctrlbit = (1 << 15), @@ -678,7 +678,7 @@ static struct clk exynos5_clk_pdma1 = { .name = "dma", .devname = "dma-pl330.1", .enable = exynos5_clk_ip_fsys_ctrl, - .ctrlbit = (1 << 1), + .ctrlbit = (1 << 2), }; static struct clk exynos5_clk_mdma1 = { @@ -813,7 +813,7 @@ static struct clksrc_clk exynos5_clk_sclk_uart3 = { static struct clksrc_clk exynos5_clk_sclk_mmc0 = { .clk = { .name = "sclk_mmc", - .devname = "s3c-sdhci.0", + .devname = "exynos4-sdhci.0", .parent = &exynos5_clk_dout_mmc0.clk, .enable = exynos5_clksrc_mask_fsys_ctrl, .ctrlbit = (1 << 0), @@ -824,7 +824,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc0 = { static struct clksrc_clk exynos5_clk_sclk_mmc1 = { .clk = { .name = "sclk_mmc", - .devname = "s3c-sdhci.1", + .devname = "exynos4-sdhci.1", .parent = &exynos5_clk_dout_mmc1.clk, .enable = exynos5_clksrc_mask_fsys_ctrl, .ctrlbit = (1 << 4), @@ -835,7 +835,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc1 = { static struct clksrc_clk exynos5_clk_sclk_mmc2 = { .clk = { .name = "sclk_mmc", - .devname = "s3c-sdhci.2", + .devname = "exynos4-sdhci.2", .parent = &exynos5_clk_dout_mmc2.clk, .enable = exynos5_clksrc_mask_fsys_ctrl, .ctrlbit = (1 << 8), @@ -846,7 +846,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc2 = { static struct clksrc_clk exynos5_clk_sclk_mmc3 = { .clk = { .name = "sclk_mmc", - .devname = "s3c-sdhci.3", + .devname = "exynos4-sdhci.3", .parent = &exynos5_clk_dout_mmc3.clk, .enable = exynos5_clksrc_mask_fsys_ctrl, .ctrlbit = (1 << 12), @@ -990,10 +990,10 @@ static struct clk_lookup exynos5_clk_lookup[] = { CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1.clk), CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2.clk), CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3.clk), - CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk), - CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk), - CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk), - CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk), + CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk), + CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk), + CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk), + CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk), CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0), CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1), CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1), diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index 8614aab47cc0..5ccd6e80a607 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -326,6 +326,11 @@ static void __init exynos4_map_io(void) s3c_fimc_setname(2, "exynos4-fimc"); s3c_fimc_setname(3, "exynos4-fimc"); + s3c_sdhci_setname(0, "exynos4-sdhci"); + s3c_sdhci_setname(1, "exynos4-sdhci"); + s3c_sdhci_setname(2, "exynos4-sdhci"); + s3c_sdhci_setname(3, "exynos4-sdhci"); + /* The I2C bus controllers are directly compatible with s3c2440 */ s3c_i2c0_setname("s3c2440-i2c"); s3c_i2c1_setname("s3c2440-i2c"); @@ -344,6 +349,11 @@ static void __init exynos5_map_io(void) s3c_device_i2c0.resource[1].start = EXYNOS5_IRQ_IIC; s3c_device_i2c0.resource[1].end = EXYNOS5_IRQ_IIC; + s3c_sdhci_setname(0, "exynos4-sdhci"); + s3c_sdhci_setname(1, "exynos4-sdhci"); + s3c_sdhci_setname(2, "exynos4-sdhci"); + s3c_sdhci_setname(3, "exynos4-sdhci"); + /* The I2C bus controllers are directly compatible with s3c2440 */ s3c_i2c0_setname("s3c2440-i2c"); s3c_i2c1_setname("s3c2440-i2c"); @@ -537,7 +547,9 @@ void __init exynos5_init_irq(void) { int irq; - gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU); +#ifdef CONFIG_OF + of_irq_init(exynos4_dt_irq_match); +#endif for (irq = 0; irq < EXYNOS5_MAX_COMBINER_NR; irq++) { combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq), diff --git a/arch/arm/mach-exynos/dev-dwmci.c b/arch/arm/mach-exynos/dev-dwmci.c index b025db4bf602..79035018fb74 100644 --- a/arch/arm/mach-exynos/dev-dwmci.c +++ b/arch/arm/mach-exynos/dev-dwmci.c @@ -16,6 +16,7 @@ #include <linux/dma-mapping.h> #include <linux/platform_device.h> #include <linux/interrupt.h> +#include <linux/ioport.h> #include <linux/mmc/dw_mmc.h> #include <plat/devs.h> @@ -33,16 +34,8 @@ static int exynos4_dwmci_init(u32 slot_id, irq_handler_t handler, void *data) } static struct resource exynos4_dwmci_resource[] = { - [0] = { - .start = EXYNOS4_PA_DWMCI, - .end = EXYNOS4_PA_DWMCI + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_DWMCI, - .end = IRQ_DWMCI, - .flags = IORESOURCE_IRQ, - } + [0] = DEFINE_RES_MEM(EXYNOS4_PA_DWMCI, SZ_4K), + [1] = DEFINE_RES_IRQ(EXYNOS4_IRQ_DWMCI), }; static struct dw_mci_board exynos4_dwci_pdata = { diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h index 9bee8535d9e0..591e78521a9f 100644 --- a/arch/arm/mach-exynos/include/mach/irqs.h +++ b/arch/arm/mach-exynos/include/mach/irqs.h @@ -212,6 +212,8 @@ #define IRQ_MFC EXYNOS4_IRQ_MFC #define IRQ_SDO EXYNOS4_IRQ_SDO +#define IRQ_I2S0 EXYNOS4_IRQ_I2S0 + #define IRQ_ADC EXYNOS4_IRQ_ADC0 #define IRQ_TC EXYNOS4_IRQ_PEN0 diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h index 024d38ff1718..6e6d11ff352a 100644 --- a/arch/arm/mach-exynos/include/mach/map.h +++ b/arch/arm/mach-exynos/include/mach/map.h @@ -89,6 +89,10 @@ #define EXYNOS4_PA_MDMA1 0x12840000 #define EXYNOS4_PA_PDMA0 0x12680000 #define EXYNOS4_PA_PDMA1 0x12690000 +#define EXYNOS5_PA_MDMA0 0x10800000 +#define EXYNOS5_PA_MDMA1 0x11C10000 +#define EXYNOS5_PA_PDMA0 0x121A0000 +#define EXYNOS5_PA_PDMA1 0x121B0000 #define EXYNOS4_PA_SYSMMU_MDMA 0x10A40000 #define EXYNOS4_PA_SYSMMU_SSS 0x10A50000 diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h index e141c1fd68d8..d9578a58ae7f 100644 --- a/arch/arm/mach-exynos/include/mach/regs-clock.h +++ b/arch/arm/mach-exynos/include/mach/regs-clock.h @@ -255,9 +255,15 @@ /* For EXYNOS5250 */ +#define EXYNOS5_APLL_LOCK EXYNOS_CLKREG(0x00000) #define EXYNOS5_APLL_CON0 EXYNOS_CLKREG(0x00100) #define EXYNOS5_CLKSRC_CPU EXYNOS_CLKREG(0x00200) +#define EXYNOS5_CLKMUX_STATCPU EXYNOS_CLKREG(0x00400) #define EXYNOS5_CLKDIV_CPU0 EXYNOS_CLKREG(0x00500) +#define EXYNOS5_CLKDIV_CPU1 EXYNOS_CLKREG(0x00504) +#define EXYNOS5_CLKDIV_STATCPU0 EXYNOS_CLKREG(0x00600) +#define EXYNOS5_CLKDIV_STATCPU1 EXYNOS_CLKREG(0x00604) + #define EXYNOS5_MPLL_CON0 EXYNOS_CLKREG(0x04100) #define EXYNOS5_CLKSRC_CORE1 EXYNOS_CLKREG(0x04204) diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c index 0d26f50081ad..4711c8920e37 100644 --- a/arch/arm/mach-exynos/mach-exynos5-dt.c +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c @@ -45,7 +45,7 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = { "exynos4210-uart.3", NULL), OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL), OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL), - OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.2", NULL), + OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL), {}, }; diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c index b3982c867c9c..ed90aef404c3 100644 --- a/arch/arm/mach-exynos/mach-nuri.c +++ b/arch/arm/mach-exynos/mach-nuri.c @@ -112,6 +112,7 @@ static struct s3c_sdhci_platdata nuri_hsmmc0_data __initdata = { .host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | MMC_CAP_ERASE), + .host_caps2 = MMC_CAP2_BROKEN_VOLTAGE, .cd_type = S3C_SDHCI_CD_PERMANENT, .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, }; @@ -307,49 +308,7 @@ static struct i2c_board_info i2c1_devs[] __initdata = { }; /* TSP */ -static u8 mxt_init_vals[] = { - /* MXT_GEN_COMMAND(6) */ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - /* MXT_GEN_POWER(7) */ - 0x20, 0xff, 0x32, - /* MXT_GEN_ACQUIRE(8) */ - 0x0a, 0x00, 0x05, 0x00, 0x00, 0x00, 0x09, 0x23, - /* MXT_TOUCH_MULTI(9) */ - 0x00, 0x00, 0x00, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x02, 0x00, - 0x00, 0x01, 0x01, 0x0e, 0x0a, 0x0a, 0x0a, 0x0a, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, - /* MXT_TOUCH_KEYARRAY(15) */ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, - 0x00, - /* MXT_SPT_GPIOPWM(19) */ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - /* MXT_PROCI_GRIPFACE(20) */ - 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x28, 0x04, - 0x0f, 0x0a, - /* MXT_PROCG_NOISE(22) */ - 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x23, 0x00, - 0x00, 0x05, 0x0f, 0x19, 0x23, 0x2d, 0x03, - /* MXT_TOUCH_PROXIMITY(23) */ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, - /* MXT_PROCI_ONETOUCH(24) */ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - /* MXT_SPT_SELFTEST(25) */ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, - /* MXT_PROCI_TWOTOUCH(27) */ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - /* MXT_SPT_CTECONFIG(28) */ - 0x00, 0x00, 0x02, 0x08, 0x10, 0x00, -}; - static struct mxt_platform_data mxt_platform_data = { - .config = mxt_init_vals, - .config_length = ARRAY_SIZE(mxt_init_vals), - .x_line = 18, .y_line = 11, .x_size = 1024, @@ -571,7 +530,7 @@ static struct regulator_init_data __initdata max8997_ldo7_data = { static struct regulator_init_data __initdata max8997_ldo8_data = { .constraints = { - .name = "VUSB/VDAC_3.3V_C210", + .name = "VUSB+VDAC_3.3V_C210", .min_uV = 3300000, .max_uV = 3300000, .valid_ops_mask = REGULATOR_CHANGE_STATUS, @@ -1347,6 +1306,7 @@ static struct platform_device *nuri_devices[] __initdata = { static void __init nuri_map_io(void) { + clk_xusbxti.rate = 24000000; exynos_init_io(NULL, 0); s3c24xx_init_clocks(24000000); s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs)); @@ -1379,7 +1339,6 @@ static void __init nuri_machine_init(void) nuri_camera_init(); nuri_ehci_init(); - clk_xusbxti.rate = 24000000; /* Last */ platform_add_devices(nuri_devices, ARRAY_SIZE(nuri_devices)); diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c index 6bb9dbdd73fd..a34036eb8ba2 100644 --- a/arch/arm/mach-exynos/mach-universal_c210.c +++ b/arch/arm/mach-exynos/mach-universal_c210.c @@ -29,6 +29,7 @@ #include <asm/mach-types.h> #include <plat/regs-serial.h> +#include <plat/clock.h> #include <plat/cpu.h> #include <plat/devs.h> #include <plat/iic.h> @@ -39,6 +40,7 @@ #include <plat/pd.h> #include <plat/regs-fb-v4.h> #include <plat/fimc-core.h> +#include <plat/s5p-time.h> #include <plat/camport.h> #include <plat/mipi_csis.h> @@ -746,6 +748,7 @@ static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = { .max_width = 8, .host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED), + .host_caps2 = MMC_CAP2_BROKEN_VOLTAGE, .cd_type = S3C_SDHCI_CD_PERMANENT, .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, }; @@ -1057,9 +1060,11 @@ static struct platform_device *universal_devices[] __initdata = { static void __init universal_map_io(void) { + clk_xusbxti.rate = 24000000; exynos_init_io(NULL, 0); s3c24xx_init_clocks(24000000); s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs)); + s5p_set_timer_source(S5P_PWM2, S5P_PWM4); } static void s5p_tv_setup(void) @@ -1110,7 +1115,7 @@ MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210") .map_io = universal_map_io, .handle_irq = gic_handle_irq, .init_machine = universal_machine_init, - .timer = &exynos4_timer, + .timer = &s5p_timer, .reserve = &universal_reserve, .restart = exynos4_restart, MACHINE_END diff --git a/arch/arm/mach-footbridge/cats-pci.c b/arch/arm/mach-footbridge/cats-pci.c index 32321f66dec4..5cec2567c9c5 100644 --- a/arch/arm/mach-footbridge/cats-pci.c +++ b/arch/arm/mach-footbridge/cats-pci.c @@ -16,6 +16,11 @@ /* cats host-specific stuff */ static int irqmap_cats[] __initdata = { IRQ_PCI, IRQ_IN0, IRQ_IN1, IRQ_IN3 }; +static u8 cats_no_swizzle(struct pci_dev *dev, u8 *pin) +{ + return 0; +} + static int __init cats_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { if (dev->irq >= 255) @@ -39,11 +44,11 @@ static int __init cats_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) * cards being used (ie, pci-pci bridge based cards)? */ static struct hw_pci cats_pci __initdata = { - .swizzle = NULL, + .swizzle = cats_no_swizzle, .map_irq = cats_map_irq, .nr_controllers = 1, + .ops = &dc21285_ops, .setup = dc21285_setup, - .scan = dc21285_scan_bus, .preinit = dc21285_preinit, .postinit = dc21285_postinit, }; diff --git a/arch/arm/mach-footbridge/dc21285.c b/arch/arm/mach-footbridge/dc21285.c index e17e11de4f5e..9d62e3381024 100644 --- a/arch/arm/mach-footbridge/dc21285.c +++ b/arch/arm/mach-footbridge/dc21285.c @@ -129,7 +129,7 @@ dc21285_write_config(struct pci_bus *bus, unsigned int devfn, int where, return PCIBIOS_SUCCESSFUL; } -static struct pci_ops dc21285_ops = { +struct pci_ops dc21285_ops = { .read = dc21285_read_config, .write = dc21285_write_config, }; @@ -284,11 +284,6 @@ int __init dc21285_setup(int nr, struct pci_sys_data *sys) return 1; } -struct pci_bus * __init dc21285_scan_bus(int nr, struct pci_sys_data *sys) -{ - return pci_scan_root_bus(NULL, 0, &dc21285_ops, sys, &sys->resources); -} - #define dc21285_request_irq(_a, _b, _c, _d, _e) \ WARN_ON(request_irq(_a, _b, _c, _d, _e) < 0) diff --git a/arch/arm/mach-footbridge/ebsa285-pci.c b/arch/arm/mach-footbridge/ebsa285-pci.c index 511c673ffa9d..fd12d8a36dc5 100644 --- a/arch/arm/mach-footbridge/ebsa285-pci.c +++ b/arch/arm/mach-footbridge/ebsa285-pci.c @@ -29,11 +29,10 @@ static int __init ebsa285_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) } static struct hw_pci ebsa285_pci __initdata = { - .swizzle = pci_std_swizzle, .map_irq = ebsa285_map_irq, .nr_controllers = 1, + .ops = &dc21285_ops, .setup = dc21285_setup, - .scan = dc21285_scan_bus, .preinit = dc21285_preinit, .postinit = dc21285_postinit, }; diff --git a/arch/arm/mach-footbridge/netwinder-pci.c b/arch/arm/mach-footbridge/netwinder-pci.c index 62187610e17e..0fba5134e4fe 100644 --- a/arch/arm/mach-footbridge/netwinder-pci.c +++ b/arch/arm/mach-footbridge/netwinder-pci.c @@ -43,11 +43,10 @@ static int __init netwinder_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) } static struct hw_pci netwinder_pci __initdata = { - .swizzle = pci_std_swizzle, .map_irq = netwinder_map_irq, .nr_controllers = 1, + .ops = &dc21285_ops, .setup = dc21285_setup, - .scan = dc21285_scan_bus, .preinit = dc21285_preinit, .postinit = dc21285_postinit, }; diff --git a/arch/arm/mach-footbridge/personal-pci.c b/arch/arm/mach-footbridge/personal-pci.c index aeb651d914a6..5c9ee54613b2 100644 --- a/arch/arm/mach-footbridge/personal-pci.c +++ b/arch/arm/mach-footbridge/personal-pci.c @@ -41,8 +41,8 @@ static int __init personal_server_map_irq(const struct pci_dev *dev, u8 slot, static struct hw_pci personal_server_pci __initdata = { .map_irq = personal_server_map_irq, .nr_controllers = 1, + .ops = &dc21285_ops, .setup = dc21285_setup, - .scan = dc21285_scan_bus, .preinit = dc21285_preinit, .postinit = dc21285_postinit, }; diff --git a/arch/arm/mach-imx/imx27-dt.c b/arch/arm/mach-imx/imx27-dt.c index 861ceb8232d6..ed38d03c61f2 100644 --- a/arch/arm/mach-imx/imx27-dt.c +++ b/arch/arm/mach-imx/imx27-dt.c @@ -35,7 +35,7 @@ static const struct of_dev_auxdata imx27_auxdata_lookup[] __initconst = { static int __init imx27_avic_add_irq_domain(struct device_node *np, struct device_node *interrupt_parent) { - irq_domain_add_simple(np, 0); + irq_domain_add_legacy(np, 64, 0, 0, &irq_domain_simple_ops, NULL); return 0; } @@ -44,7 +44,9 @@ static int __init imx27_gpio_add_irq_domain(struct device_node *np, { static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS; - irq_domain_add_simple(np, gpio_irq_base); + gpio_irq_base -= 32; + irq_domain_add_legacy(np, 32, gpio_irq_base, 0, &irq_domain_simple_ops, + NULL); return 0; } diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c index 05250aed61fb..e10f3914fcfe 100644 --- a/arch/arm/mach-imx/mm-imx5.c +++ b/arch/arm/mach-imx/mm-imx5.c @@ -35,7 +35,7 @@ static void imx5_idle(void) } clk_enable(gpc_dvfs_clk); mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF); - if (tzic_enable_wake() != 0) + if (!tzic_enable_wake()) cpu_do_idle(); clk_disable(gpc_dvfs_clk); } diff --git a/arch/arm/mach-integrator/impd1.c b/arch/arm/mach-integrator/impd1.c index 3e538da6cb1f..e428f3ab15c7 100644 --- a/arch/arm/mach-integrator/impd1.c +++ b/arch/arm/mach-integrator/impd1.c @@ -398,24 +398,16 @@ static int impd1_probe(struct lm_device *dev) struct impd1_device *idev = impd1_devs + i; struct amba_device *d; unsigned long pc_base; + char devname[32]; pc_base = dev->resource.start + idev->offset; - - d = amba_device_alloc(NULL, pc_base, SZ_4K); - if (!d) + snprintf(devname, 32, "lm%x:%5.5lx", dev->id, idev->offset >> 12); + d = amba_ahb_device_add(&dev->dev, devname, pc_base, SZ_4K, + dev->irq, dev->irq, + idev->platform_data, idev->id); + if (IS_ERR(d)) { + dev_err(&dev->dev, "unable to register device: %ld\n", PTR_ERR(d)); continue; - - dev_set_name(&d->dev, "lm%x:%5.5lx", dev->id, idev->offset >> 12); - d->dev.parent = &dev->dev; - d->irq[0] = dev->irq; - d->irq[1] = dev->irq; - d->periphid = idev->id; - d->dev.platform_data = idev->platform_data; - - ret = amba_device_add(d, &dev->resource); - if (ret) { - dev_err(&d->dev, "unable to register device: %d\n", ret); - amba_device_put(d); } } diff --git a/arch/arm/mach-integrator/include/mach/entry-macro.S b/arch/arm/mach-integrator/include/mach/entry-macro.S deleted file mode 100644 index 5cc7b85ad9df..000000000000 --- a/arch/arm/mach-integrator/include/mach/entry-macro.S +++ /dev/null @@ -1,39 +0,0 @@ -/* - * arch/arm/mach-integrator/include/mach/entry-macro.S - * - * Low-level IRQ helper macros for Integrator platforms - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ -#include <mach/hardware.h> -#include <mach/platform.h> -#include <mach/irqs.h> - - .macro get_irqnr_preamble, base, tmp - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp -/* FIXME: should not be using soo many LDRs here */ - ldr \base, =IO_ADDRESS(INTEGRATOR_IC_BASE) - mov \irqnr, #IRQ_PIC_START - ldr \irqstat, [\base, #IRQ_STATUS] @ get masked status - ldr \base, =IO_ADDRESS(INTEGRATOR_HDR_BASE) - teq \irqstat, #0 - ldreq \irqstat, [\base, #(INTEGRATOR_HDR_IC_OFFSET+IRQ_STATUS)] - moveq \irqnr, #IRQ_CIC_START - -1001: tst \irqstat, #15 - bne 1002f - add \irqnr, \irqnr, #4 - movs \irqstat, \irqstat, lsr #4 - bne 1001b -1002: tst \irqstat, #1 - bne 1003f - add \irqnr, \irqnr, #1 - movs \irqstat, \irqstat, lsr #1 - bne 1002b -1003: /* EQ will be set if no irqs pending */ - .endm - diff --git a/arch/arm/mach-integrator/include/mach/irqs.h b/arch/arm/mach-integrator/include/mach/irqs.h index a19a1a2fcf6b..7371018455d2 100644 --- a/arch/arm/mach-integrator/include/mach/irqs.h +++ b/arch/arm/mach-integrator/include/mach/irqs.h @@ -22,37 +22,37 @@ /* * Interrupt numbers */ -#define IRQ_PIC_START 0 -#define IRQ_SOFTINT 0 -#define IRQ_UARTINT0 1 -#define IRQ_UARTINT1 2 -#define IRQ_KMIINT0 3 -#define IRQ_KMIINT1 4 -#define IRQ_TIMERINT0 5 -#define IRQ_TIMERINT1 6 -#define IRQ_TIMERINT2 7 -#define IRQ_RTCINT 8 -#define IRQ_AP_EXPINT0 9 -#define IRQ_AP_EXPINT1 10 -#define IRQ_AP_EXPINT2 11 -#define IRQ_AP_EXPINT3 12 -#define IRQ_AP_PCIINT0 13 -#define IRQ_AP_PCIINT1 14 -#define IRQ_AP_PCIINT2 15 -#define IRQ_AP_PCIINT3 16 -#define IRQ_AP_V3INT 17 -#define IRQ_AP_CPINT0 18 -#define IRQ_AP_CPINT1 19 -#define IRQ_AP_LBUSTIMEOUT 20 -#define IRQ_AP_APCINT 21 -#define IRQ_CP_CLCDCINT 22 -#define IRQ_CP_MMCIINT0 23 -#define IRQ_CP_MMCIINT1 24 -#define IRQ_CP_AACIINT 25 -#define IRQ_CP_CPPLDINT 26 -#define IRQ_CP_ETHINT 27 -#define IRQ_CP_TSPENINT 28 -#define IRQ_PIC_END 31 +#define IRQ_PIC_START 1 +#define IRQ_SOFTINT 1 +#define IRQ_UARTINT0 2 +#define IRQ_UARTINT1 3 +#define IRQ_KMIINT0 4 +#define IRQ_KMIINT1 5 +#define IRQ_TIMERINT0 6 +#define IRQ_TIMERINT1 7 +#define IRQ_TIMERINT2 8 +#define IRQ_RTCINT 9 +#define IRQ_AP_EXPINT0 10 +#define IRQ_AP_EXPINT1 11 +#define IRQ_AP_EXPINT2 12 +#define IRQ_AP_EXPINT3 13 +#define IRQ_AP_PCIINT0 14 +#define IRQ_AP_PCIINT1 15 +#define IRQ_AP_PCIINT2 16 +#define IRQ_AP_PCIINT3 17 +#define IRQ_AP_V3INT 18 +#define IRQ_AP_CPINT0 19 +#define IRQ_AP_CPINT1 20 +#define IRQ_AP_LBUSTIMEOUT 21 +#define IRQ_AP_APCINT 22 +#define IRQ_CP_CLCDCINT 23 +#define IRQ_CP_MMCIINT0 24 +#define IRQ_CP_MMCIINT1 25 +#define IRQ_CP_AACIINT 26 +#define IRQ_CP_CPPLDINT 27 +#define IRQ_CP_ETHINT 28 +#define IRQ_CP_TSPENINT 29 +#define IRQ_PIC_END 29 #define IRQ_CIC_START 32 #define IRQ_CM_SOFTINT 32 @@ -80,4 +80,3 @@ #define NR_IRQS_INTEGRATOR_AP 34 #define NR_IRQS_INTEGRATOR_CP 47 - diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c index 871f148ffd72..c857501c5783 100644 --- a/arch/arm/mach-integrator/integrator_ap.c +++ b/arch/arm/mach-integrator/integrator_ap.c @@ -162,12 +162,6 @@ static void __init ap_map_io(void) #define INTEGRATOR_SC_VALID_INT 0x003fffff -static struct fpga_irq_data sc_irq_data = { - .base = VA_IC_BASE, - .irq_start = 0, - .chip.name = "SC", -}; - static void __init ap_init_irq(void) { /* Disable all interrupts initially. */ @@ -178,7 +172,8 @@ static void __init ap_init_irq(void) writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR); writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR); - fpga_irq_init(-1, INTEGRATOR_SC_VALID_INT, &sc_irq_data); + fpga_irq_init(VA_IC_BASE, "SC", IRQ_PIC_START, + -1, INTEGRATOR_SC_VALID_INT, NULL); } #ifdef CONFIG_PM @@ -478,6 +473,7 @@ MACHINE_START(INTEGRATOR, "ARM-Integrator") .nr_irqs = NR_IRQS_INTEGRATOR_AP, .init_early = integrator_init_early, .init_irq = ap_init_irq, + .handle_irq = fpga_handle_irq, .timer = &ap_timer, .init_machine = ap_init, .restart = integrator_restart, diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c index 48a115a91d9d..a56c53608939 100644 --- a/arch/arm/mach-integrator/integrator_cp.c +++ b/arch/arm/mach-integrator/integrator_cp.c @@ -143,30 +143,14 @@ static void __init intcp_map_io(void) iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc)); } -static struct fpga_irq_data cic_irq_data = { - .base = INTCP_VA_CIC_BASE, - .irq_start = IRQ_CIC_START, - .chip.name = "CIC", -}; - -static struct fpga_irq_data pic_irq_data = { - .base = INTCP_VA_PIC_BASE, - .irq_start = IRQ_PIC_START, - .chip.name = "PIC", -}; - -static struct fpga_irq_data sic_irq_data = { - .base = INTCP_VA_SIC_BASE, - .irq_start = IRQ_SIC_START, - .chip.name = "SIC", -}; - static void __init intcp_init_irq(void) { - u32 pic_mask, sic_mask; + u32 pic_mask, cic_mask, sic_mask; + /* These masks are for the HW IRQ registers */ pic_mask = ~((~0u) << (11 - IRQ_PIC_START)); pic_mask |= (~((~0u) << (29 - 22))) << 22; + cic_mask = ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START)); sic_mask = ~((~0u) << (1 + IRQ_SIC_END - IRQ_SIC_START)); /* @@ -179,12 +163,14 @@ static void __init intcp_init_irq(void) writel(sic_mask, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR); writel(sic_mask, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR); - fpga_irq_init(-1, pic_mask, &pic_irq_data); + fpga_irq_init(INTCP_VA_PIC_BASE, "PIC", IRQ_PIC_START, + -1, pic_mask, NULL); - fpga_irq_init(-1, ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START)), - &cic_irq_data); + fpga_irq_init(INTCP_VA_CIC_BASE, "CIC", IRQ_CIC_START, + -1, cic_mask, NULL); - fpga_irq_init(IRQ_CP_CPPLDINT, sic_mask, &sic_irq_data); + fpga_irq_init(INTCP_VA_SIC_BASE, "SIC", IRQ_SIC_START, + IRQ_CP_CPPLDINT, sic_mask, NULL); } /* @@ -467,6 +453,7 @@ MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP") .nr_irqs = NR_IRQS_INTEGRATOR_CP, .init_early = intcp_init_early, .init_irq = intcp_init_irq, + .handle_irq = fpga_handle_irq, .timer = &cp_timer, .init_machine = intcp_init, .restart = integrator_restart, diff --git a/arch/arm/mach-integrator/pci.c b/arch/arm/mach-integrator/pci.c index f1ca9c122861..6c1667e728f5 100644 --- a/arch/arm/mach-integrator/pci.c +++ b/arch/arm/mach-integrator/pci.c @@ -70,21 +70,10 @@ */ static u8 __init integrator_swizzle(struct pci_dev *dev, u8 *pinp) { - int pin = *pinp; + if (*pinp == 0) + *pinp = 1; - if (pin == 0) - pin = 1; - - while (dev->bus->self) { - pin = pci_swizzle_interrupt_pin(dev, pin); - /* - * move up the chain of bridges, swizzling as we go. - */ - dev = dev->bus->self; - } - *pinp = pin; - - return PCI_SLOT(dev->devfn); + return pci_common_swizzle(dev, pinp); } static int irq_tab[4] __initdata = { @@ -109,7 +98,7 @@ static struct hw_pci integrator_pci __initdata = { .map_irq = integrator_map_irq, .setup = pci_v3_setup, .nr_controllers = 1, - .scan = pci_v3_scan_bus, + .ops = &pci_v3_ops, .preinit = pci_v3_preinit, .postinit = pci_v3_postinit, }; diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c index 67e6f9a9d1a0..b866880e82ac 100644 --- a/arch/arm/mach-integrator/pci_v3.c +++ b/arch/arm/mach-integrator/pci_v3.c @@ -340,7 +340,7 @@ static int v3_write_config(struct pci_bus *bus, unsigned int devfn, int where, return PCIBIOS_SUCCESSFUL; } -static struct pci_ops pci_v3_ops = { +struct pci_ops pci_v3_ops = { .read = v3_read_config, .write = v3_write_config, }; @@ -488,12 +488,6 @@ int __init pci_v3_setup(int nr, struct pci_sys_data *sys) return ret; } -struct pci_bus * __init pci_v3_scan_bus(int nr, struct pci_sys_data *sys) -{ - return pci_scan_root_bus(NULL, sys->busnr, &pci_v3_ops, sys, - &sys->resources); -} - /* * V3_LB_BASE? - local bus address * V3_LB_MAP? - pci bus address diff --git a/arch/arm/mach-iop13xx/iq81340mc.c b/arch/arm/mach-iop13xx/iq81340mc.c index 5c96b73e6964..e3f3e7daa79e 100644 --- a/arch/arm/mach-iop13xx/iq81340mc.c +++ b/arch/arm/mach-iop13xx/iq81340mc.c @@ -54,7 +54,6 @@ iq81340mc_pcix_map_irq(const struct pci_dev *dev, u8 idsel, u8 pin) } static struct hw_pci iq81340mc_pci __initdata = { - .swizzle = pci_std_swizzle, .nr_controllers = 0, .setup = iop13xx_pci_setup, .map_irq = iq81340mc_pcix_map_irq, diff --git a/arch/arm/mach-iop13xx/iq81340sc.c b/arch/arm/mach-iop13xx/iq81340sc.c index aa4dd750135a..060cddde2fd4 100644 --- a/arch/arm/mach-iop13xx/iq81340sc.c +++ b/arch/arm/mach-iop13xx/iq81340sc.c @@ -56,7 +56,6 @@ iq81340sc_atux_map_irq(struct pci_dev *dev, u8 idsel, u8 pin) } static struct hw_pci iq81340sc_pci __initdata = { - .swizzle = pci_std_swizzle, .nr_controllers = 0, .setup = iop13xx_pci_setup, .scan = iop13xx_scan_bus, diff --git a/arch/arm/mach-iop32x/em7210.c b/arch/arm/mach-iop32x/em7210.c index 24069e03fdc1..9f369f09c29d 100644 --- a/arch/arm/mach-iop32x/em7210.c +++ b/arch/arm/mach-iop32x/em7210.c @@ -103,11 +103,10 @@ em7210_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) } static struct hw_pci em7210_pci __initdata = { - .swizzle = pci_std_swizzle, .nr_controllers = 1, + .ops = &iop3xx_ops, .setup = iop3xx_pci_setup, .preinit = iop3xx_pci_preinit, - .scan = iop3xx_pci_scan_bus, .map_irq = em7210_pci_map_irq, }; diff --git a/arch/arm/mach-iop32x/glantank.c b/arch/arm/mach-iop32x/glantank.c index 204e1d1cd766..c15a100ba779 100644 --- a/arch/arm/mach-iop32x/glantank.c +++ b/arch/arm/mach-iop32x/glantank.c @@ -96,11 +96,10 @@ glantank_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) } static struct hw_pci glantank_pci __initdata = { - .swizzle = pci_std_swizzle, .nr_controllers = 1, + .ops = &iop3xx_ops, .setup = iop3xx_pci_setup, .preinit = iop3xx_pci_preinit, - .scan = iop3xx_pci_scan_bus, .map_irq = glantank_pci_map_irq, }; diff --git a/arch/arm/mach-iop32x/iq31244.c b/arch/arm/mach-iop32x/iq31244.c index 3eb642af1cdc..ddd1c7ecfe57 100644 --- a/arch/arm/mach-iop32x/iq31244.c +++ b/arch/arm/mach-iop32x/iq31244.c @@ -130,11 +130,10 @@ ep80219_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) } static struct hw_pci ep80219_pci __initdata = { - .swizzle = pci_std_swizzle, .nr_controllers = 1, + .ops = &iop3xx_ops, .setup = iop3xx_pci_setup, .preinit = iop3xx_pci_preinit, - .scan = iop3xx_pci_scan_bus, .map_irq = ep80219_pci_map_irq, }; @@ -166,11 +165,10 @@ iq31244_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) } static struct hw_pci iq31244_pci __initdata = { - .swizzle = pci_std_swizzle, .nr_controllers = 1, + .ops = &iop3xx_ops, .setup = iop3xx_pci_setup, .preinit = iop3xx_pci_preinit, - .scan = iop3xx_pci_scan_bus, .map_irq = iq31244_pci_map_irq, }; diff --git a/arch/arm/mach-iop32x/iq80321.c b/arch/arm/mach-iop32x/iq80321.c index 2ec724b58a2c..bf155e6a3b45 100644 --- a/arch/arm/mach-iop32x/iq80321.c +++ b/arch/arm/mach-iop32x/iq80321.c @@ -101,11 +101,10 @@ iq80321_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) } static struct hw_pci iq80321_pci __initdata = { - .swizzle = pci_std_swizzle, .nr_controllers = 1, + .ops = &iop3xx_ops, .setup = iop3xx_pci_setup, .preinit = iop3xx_pci_preinit_cond, - .scan = iop3xx_pci_scan_bus, .map_irq = iq80321_pci_map_irq, }; diff --git a/arch/arm/mach-iop32x/n2100.c b/arch/arm/mach-iop32x/n2100.c index 6b6d55912444..5a7ae91e8849 100644 --- a/arch/arm/mach-iop32x/n2100.c +++ b/arch/arm/mach-iop32x/n2100.c @@ -114,11 +114,10 @@ n2100_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) } static struct hw_pci n2100_pci __initdata = { - .swizzle = pci_std_swizzle, .nr_controllers = 1, + .ops = &iop3xx_ops, .setup = iop3xx_pci_setup, .preinit = iop3xx_pci_preinit, - .scan = iop3xx_pci_scan_bus, .map_irq = n2100_pci_map_irq, }; diff --git a/arch/arm/mach-iop33x/iq80331.c b/arch/arm/mach-iop33x/iq80331.c index abce934f3816..e74a7debe793 100644 --- a/arch/arm/mach-iop33x/iq80331.c +++ b/arch/arm/mach-iop33x/iq80331.c @@ -84,11 +84,10 @@ iq80331_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) } static struct hw_pci iq80331_pci __initdata = { - .swizzle = pci_std_swizzle, .nr_controllers = 1, + .ops = &iop3xx_ops, .setup = iop3xx_pci_setup, .preinit = iop3xx_pci_preinit_cond, - .scan = iop3xx_pci_scan_bus, .map_irq = iq80331_pci_map_irq, }; diff --git a/arch/arm/mach-iop33x/iq80332.c b/arch/arm/mach-iop33x/iq80332.c index 7513559e25bb..e2f5beece6e8 100644 --- a/arch/arm/mach-iop33x/iq80332.c +++ b/arch/arm/mach-iop33x/iq80332.c @@ -84,11 +84,10 @@ iq80332_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) } static struct hw_pci iq80332_pci __initdata = { - .swizzle = pci_std_swizzle, .nr_controllers = 1, + .ops = &iop3xx_ops, .setup = iop3xx_pci_setup, .preinit = iop3xx_pci_preinit_cond, - .scan = iop3xx_pci_scan_bus, .map_irq = iq80332_pci_map_irq, }; diff --git a/arch/arm/mach-ixp2000/enp2611.c b/arch/arm/mach-ixp2000/enp2611.c index 4867f408617c..73df2f688813 100644 --- a/arch/arm/mach-ixp2000/enp2611.c +++ b/arch/arm/mach-ixp2000/enp2611.c @@ -141,13 +141,6 @@ static struct pci_ops enp2611_pci_ops = { .write = enp2611_pci_write_config }; -static struct pci_bus * __init enp2611_pci_scan_bus(int nr, - struct pci_sys_data *sys) -{ - return pci_scan_root_bus(NULL, sys->busnr, &enp2611_pci_ops, sys, - &sys->resources); -} - static int __init enp2611_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { @@ -180,9 +173,9 @@ static int __init enp2611_pci_map_irq(const struct pci_dev *dev, u8 slot, struct hw_pci enp2611_pci __initdata = { .nr_controllers = 1, + .ops = &enp2611_pci_ops, .setup = enp2611_pci_setup, .preinit = enp2611_pci_preinit, - .scan = enp2611_pci_scan_bus, .map_irq = enp2611_pci_map_irq, }; diff --git a/arch/arm/mach-ixp2000/include/mach/platform.h b/arch/arm/mach-ixp2000/include/mach/platform.h index bb0f8dcf9ee1..6b500c0858be 100644 --- a/arch/arm/mach-ixp2000/include/mach/platform.h +++ b/arch/arm/mach-ixp2000/include/mach/platform.h @@ -127,10 +127,10 @@ unsigned long ixp2000_gettimeoffset(void); struct pci_sys_data; +extern struct pci_ops ixp2000_pci_ops; u32 *ixp2000_pci_config_addr(unsigned int bus, unsigned int devfn, int where); void ixp2000_pci_preinit(void); int ixp2000_pci_setup(int, struct pci_sys_data*); -struct pci_bus* ixp2000_pci_scan_bus(int, struct pci_sys_data*); int ixp2000_pci_read_config(struct pci_bus*, unsigned int, int, int, u32 *); int ixp2000_pci_write_config(struct pci_bus*, unsigned int, int, int, u32); diff --git a/arch/arm/mach-ixp2000/ixdp2400.c b/arch/arm/mach-ixp2000/ixdp2400.c index 915ad49e3b8f..4ec44801d303 100644 --- a/arch/arm/mach-ixp2000/ixdp2400.c +++ b/arch/arm/mach-ixp2000/ixdp2400.c @@ -146,10 +146,10 @@ static void ixdp2400_pci_postinit(void) static struct hw_pci ixdp2400_pci __initdata = { .nr_controllers = 1, + .ops = &ixp2000_pci_ops, .setup = ixdp2400_pci_setup, .preinit = ixdp2400_pci_preinit, .postinit = ixdp2400_pci_postinit, - .scan = ixp2000_pci_scan_bus, .map_irq = ixdp2400_pci_map_irq, }; diff --git a/arch/arm/mach-ixp2000/ixdp2800.c b/arch/arm/mach-ixp2000/ixdp2800.c index a9f1819ea049..44378c31d177 100644 --- a/arch/arm/mach-ixp2000/ixdp2800.c +++ b/arch/arm/mach-ixp2000/ixdp2800.c @@ -246,10 +246,10 @@ static void __init ixdp2800_pci_postinit(void) struct __initdata hw_pci ixdp2800_pci __initdata = { .nr_controllers = 1, + .ops = &ixp2000_pci_ops, .setup = ixdp2800_pci_setup, .preinit = ixdp2800_pci_preinit, .postinit = ixdp2800_pci_postinit, - .scan = ixp2000_pci_scan_bus, .map_irq = ixdp2800_pci_map_irq, }; diff --git a/arch/arm/mach-ixp2000/ixdp2x01.c b/arch/arm/mach-ixp2000/ixdp2x01.c index 5196c39cdba4..af8b801d7d59 100644 --- a/arch/arm/mach-ixp2000/ixdp2x01.c +++ b/arch/arm/mach-ixp2000/ixdp2x01.c @@ -327,9 +327,9 @@ static int ixdp2x01_pci_setup(int nr, struct pci_sys_data *sys) struct hw_pci ixdp2x01_pci __initdata = { .nr_controllers = 1, + .ops = &ixp2000_pci_ops, .setup = ixdp2x01_pci_setup, .preinit = ixdp2x01_pci_preinit, - .scan = ixp2000_pci_scan_bus, .map_irq = ixdp2x01_pci_map_irq, }; diff --git a/arch/arm/mach-ixp2000/pci.c b/arch/arm/mach-ixp2000/pci.c index 9c02de932fac..d706838db023 100644 --- a/arch/arm/mach-ixp2000/pci.c +++ b/arch/arm/mach-ixp2000/pci.c @@ -124,17 +124,11 @@ int ixp2000_pci_write_config(struct pci_bus *bus, unsigned int devfn, int where, } -static struct pci_ops ixp2000_pci_ops = { +struct pci_ops ixp2000_pci_ops = { .read = ixp2000_pci_read_config, .write = ixp2000_pci_write_config }; -struct pci_bus *ixp2000_pci_scan_bus(int nr, struct pci_sys_data *sysdata) -{ - return pci_scan_root_bus(NULL, sysdata->busnr, &ixp2000_pci_ops, - sysdata, &sysdata->resources); -} - int ixp2000_pci_abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs) { diff --git a/arch/arm/mach-ixp23xx/include/mach/platform.h b/arch/arm/mach-ixp23xx/include/mach/platform.h index 50de558e722e..798d8b42ab4a 100644 --- a/arch/arm/mach-ixp23xx/include/mach/platform.h +++ b/arch/arm/mach-ixp23xx/include/mach/platform.h @@ -37,7 +37,7 @@ void ixp23xx_sys_init(void); void ixp23xx_restart(char, const char *); int ixp23xx_pci_setup(int, struct pci_sys_data *); void ixp23xx_pci_preinit(void); -struct pci_bus *ixp23xx_pci_scan_bus(int, struct pci_sys_data*); +extern struct pci_ops ixp23xx_pci_ops; void ixp23xx_pci_slave_init(void); extern struct sys_timer ixp23xx_timer; diff --git a/arch/arm/mach-ixp23xx/ixdp2351.c b/arch/arm/mach-ixp23xx/ixdp2351.c index b0e07db5ceaf..8b48e32a8a62 100644 --- a/arch/arm/mach-ixp23xx/ixdp2351.c +++ b/arch/arm/mach-ixp23xx/ixdp2351.c @@ -251,9 +251,9 @@ static int __init ixdp2351_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) struct hw_pci ixdp2351_pci __initdata = { .nr_controllers = 1, + .ops = &ixp23xx_pci_ops, .preinit = ixp23xx_pci_preinit, .setup = ixp23xx_pci_setup, - .scan = ixp23xx_pci_scan_bus, .map_irq = ixdp2351_map_irq, }; diff --git a/arch/arm/mach-ixp23xx/pci.c b/arch/arm/mach-ixp23xx/pci.c index 911f5a58e006..9211506ef556 100644 --- a/arch/arm/mach-ixp23xx/pci.c +++ b/arch/arm/mach-ixp23xx/pci.c @@ -140,12 +140,6 @@ struct pci_ops ixp23xx_pci_ops = { .write = ixp23xx_pci_write_config, }; -struct pci_bus *ixp23xx_pci_scan_bus(int nr, struct pci_sys_data *sysdata) -{ - return pci_scan_root_bus(NULL, sysdata->busnr, &ixp23xx_pci_ops, - sysdata, &sysdata->resources); -} - int ixp23xx_pci_abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs) { volatile unsigned long temp; diff --git a/arch/arm/mach-ixp23xx/roadrunner.c b/arch/arm/mach-ixp23xx/roadrunner.c index eaaa3fa9fd05..8c0e5de3c609 100644 --- a/arch/arm/mach-ixp23xx/roadrunner.c +++ b/arch/arm/mach-ixp23xx/roadrunner.c @@ -118,9 +118,9 @@ static void __init roadrunner_pci_preinit(void) static struct hw_pci roadrunner_pci __initdata = { .nr_controllers = 1, + .ops = &ixp23xx_pci_ops, .preinit = roadrunner_pci_preinit, .setup = ixp23xx_pci_setup, - .scan = ixp23xx_pci_scan_bus, .map_irq = roadrunner_map_irq, }; diff --git a/arch/arm/mach-ixp4xx/avila-pci.c b/arch/arm/mach-ixp4xx/avila-pci.c index 8fea0a3c5246..548c7d43ade6 100644 --- a/arch/arm/mach-ixp4xx/avila-pci.c +++ b/arch/arm/mach-ixp4xx/avila-pci.c @@ -65,10 +65,9 @@ static int __init avila_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) struct hw_pci avila_pci __initdata = { .nr_controllers = 1, + .ops = &ixp4xx_ops, .preinit = avila_pci_preinit, - .swizzle = pci_std_swizzle, .setup = ixp4xx_setup, - .scan = ixp4xx_scan_bus, .map_irq = avila_map_irq, }; diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c index d5719eb42591..1694f01ce2b6 100644 --- a/arch/arm/mach-ixp4xx/common-pci.c +++ b/arch/arm/mach-ixp4xx/common-pci.c @@ -480,12 +480,6 @@ int ixp4xx_setup(int nr, struct pci_sys_data *sys) return 1; } -struct pci_bus * __devinit ixp4xx_scan_bus(int nr, struct pci_sys_data *sys) -{ - return pci_scan_root_bus(NULL, sys->busnr, &ixp4xx_ops, sys, - &sys->resources); -} - int dma_set_coherent_mask(struct device *dev, u64 mask) { if (mask >= SZ_64M - 1) diff --git a/arch/arm/mach-ixp4xx/coyote-pci.c b/arch/arm/mach-ixp4xx/coyote-pci.c index 71f5c9c60fc3..5d14ce2aee6d 100644 --- a/arch/arm/mach-ixp4xx/coyote-pci.c +++ b/arch/arm/mach-ixp4xx/coyote-pci.c @@ -48,10 +48,9 @@ static int __init coyote_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) struct hw_pci coyote_pci __initdata = { .nr_controllers = 1, + .ops = &ixp4xx_ops, .preinit = coyote_pci_preinit, - .swizzle = pci_std_swizzle, .setup = ixp4xx_setup, - .scan = ixp4xx_scan_bus, .map_irq = coyote_map_irq, }; diff --git a/arch/arm/mach-ixp4xx/dsmg600-pci.c b/arch/arm/mach-ixp4xx/dsmg600-pci.c index 0532510b5e8c..8dca76937723 100644 --- a/arch/arm/mach-ixp4xx/dsmg600-pci.c +++ b/arch/arm/mach-ixp4xx/dsmg600-pci.c @@ -62,10 +62,9 @@ static int __init dsmg600_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) struct hw_pci __initdata dsmg600_pci = { .nr_controllers = 1, + .ops = &ixp4xx_ops, .preinit = dsmg600_pci_preinit, - .swizzle = pci_std_swizzle, .setup = ixp4xx_setup, - .scan = ixp4xx_scan_bus, .map_irq = dsmg600_map_irq, }; diff --git a/arch/arm/mach-ixp4xx/fsg-pci.c b/arch/arm/mach-ixp4xx/fsg-pci.c index d2ac803328f7..fd4a8625b4ae 100644 --- a/arch/arm/mach-ixp4xx/fsg-pci.c +++ b/arch/arm/mach-ixp4xx/fsg-pci.c @@ -59,10 +59,9 @@ static int __init fsg_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) struct hw_pci fsg_pci __initdata = { .nr_controllers = 1, + .ops = &ixp4xx_ops, .preinit = fsg_pci_preinit, - .swizzle = pci_std_swizzle, .setup = ixp4xx_setup, - .scan = ixp4xx_scan_bus, .map_irq = fsg_map_irq, }; diff --git a/arch/arm/mach-ixp4xx/gateway7001-pci.c b/arch/arm/mach-ixp4xx/gateway7001-pci.c index 76581fb467c4..d9d6cc089707 100644 --- a/arch/arm/mach-ixp4xx/gateway7001-pci.c +++ b/arch/arm/mach-ixp4xx/gateway7001-pci.c @@ -47,10 +47,9 @@ static int __init gateway7001_map_irq(const struct pci_dev *dev, u8 slot, struct hw_pci gateway7001_pci __initdata = { .nr_controllers = 1, + .ops = &ixp4xx_ops, .preinit = gateway7001_pci_preinit, - .swizzle = pci_std_swizzle, .setup = ixp4xx_setup, - .scan = ixp4xx_scan_bus, .map_irq = gateway7001_map_irq, }; diff --git a/arch/arm/mach-ixp4xx/goramo_mlr.c b/arch/arm/mach-ixp4xx/goramo_mlr.c index 46bb924962ee..b800a031207c 100644 --- a/arch/arm/mach-ixp4xx/goramo_mlr.c +++ b/arch/arm/mach-ixp4xx/goramo_mlr.c @@ -473,11 +473,10 @@ static int __init gmlr_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) static struct hw_pci gmlr_hw_pci __initdata = { .nr_controllers = 1, + .ops = &ixp4xx_ops, .preinit = gmlr_pci_preinit, .postinit = gmlr_pci_postinit, - .swizzle = pci_std_swizzle, .setup = ixp4xx_setup, - .scan = ixp4xx_scan_bus, .map_irq = gmlr_map_irq, }; diff --git a/arch/arm/mach-ixp4xx/gtwx5715-pci.c b/arch/arm/mach-ixp4xx/gtwx5715-pci.c index d68fc068c38d..551d114c9e14 100644 --- a/arch/arm/mach-ixp4xx/gtwx5715-pci.c +++ b/arch/arm/mach-ixp4xx/gtwx5715-pci.c @@ -67,10 +67,9 @@ static int __init gtwx5715_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) struct hw_pci gtwx5715_pci __initdata = { .nr_controllers = 1, + .ops = &ixp4xx_ops, .preinit = gtwx5715_pci_preinit, - .swizzle = pci_std_swizzle, .setup = ixp4xx_setup, - .scan = ixp4xx_scan_bus, .map_irq = gtwx5715_map_irq, }; diff --git a/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h b/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h index 292d55ed2113..cf03614d250d 100644 --- a/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h +++ b/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h @@ -75,4 +75,7 @@ struct ixp46x_ts_regs { #define TX_SNAPSHOT_LOCKED (1<<0) #define RX_SNAPSHOT_LOCKED (1<<1) +/* The ptp_ixp46x module will set this variable */ +extern int ixp46x_phc_index; + #endif diff --git a/arch/arm/mach-ixp4xx/include/mach/platform.h b/arch/arm/mach-ixp4xx/include/mach/platform.h index b66bedc64de1..5bce94aacca9 100644 --- a/arch/arm/mach-ixp4xx/include/mach/platform.h +++ b/arch/arm/mach-ixp4xx/include/mach/platform.h @@ -130,7 +130,7 @@ extern void ixp4xx_restart(char, const char *); extern void ixp4xx_pci_preinit(void); struct pci_sys_data; extern int ixp4xx_setup(int nr, struct pci_sys_data *sys); -extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys); +extern struct pci_ops ixp4xx_ops; /* * GPIO-functions diff --git a/arch/arm/mach-ixp4xx/ixdp425-pci.c b/arch/arm/mach-ixp4xx/ixdp425-pci.c index fffd8c5e40bf..318424dd3c50 100644 --- a/arch/arm/mach-ixp4xx/ixdp425-pci.c +++ b/arch/arm/mach-ixp4xx/ixdp425-pci.c @@ -60,10 +60,9 @@ static int __init ixdp425_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) struct hw_pci ixdp425_pci __initdata = { .nr_controllers = 1, + .ops = &ixp4xx_ops, .preinit = ixdp425_pci_preinit, - .swizzle = pci_std_swizzle, .setup = ixp4xx_setup, - .scan = ixp4xx_scan_bus, .map_irq = ixdp425_map_irq, }; diff --git a/arch/arm/mach-ixp4xx/ixdpg425-pci.c b/arch/arm/mach-ixp4xx/ixdpg425-pci.c index 34efe75015ec..1f8717ba13dc 100644 --- a/arch/arm/mach-ixp4xx/ixdpg425-pci.c +++ b/arch/arm/mach-ixp4xx/ixdpg425-pci.c @@ -42,10 +42,9 @@ static int __init ixdpg425_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) struct hw_pci ixdpg425_pci __initdata = { .nr_controllers = 1, + .ops = &ixp4xx_ops, .preinit = ixdpg425_pci_preinit, - .swizzle = pci_std_swizzle, .setup = ixp4xx_setup, - .scan = ixp4xx_scan_bus, .map_irq = ixdpg425_map_irq, }; diff --git a/arch/arm/mach-ixp4xx/miccpt-pci.c b/arch/arm/mach-ixp4xx/miccpt-pci.c index ca0bae7fca90..d114ccd2017c 100644 --- a/arch/arm/mach-ixp4xx/miccpt-pci.c +++ b/arch/arm/mach-ixp4xx/miccpt-pci.c @@ -61,10 +61,9 @@ static int __init miccpt_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) struct hw_pci miccpt_pci __initdata = { .nr_controllers = 1, + .ops = &ixp4xx_ops, .preinit = miccpt_pci_preinit, - .swizzle = pci_std_swizzle, .setup = ixp4xx_setup, - .scan = ixp4xx_scan_bus, .map_irq = miccpt_map_irq, }; diff --git a/arch/arm/mach-ixp4xx/nas100d-pci.c b/arch/arm/mach-ixp4xx/nas100d-pci.c index 5434ccf553eb..8f0eba0a6800 100644 --- a/arch/arm/mach-ixp4xx/nas100d-pci.c +++ b/arch/arm/mach-ixp4xx/nas100d-pci.c @@ -58,10 +58,9 @@ static int __init nas100d_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) struct hw_pci __initdata nas100d_pci = { .nr_controllers = 1, + .ops = &ixp4xx_ops, .preinit = nas100d_pci_preinit, - .swizzle = pci_std_swizzle, .setup = ixp4xx_setup, - .scan = ixp4xx_scan_bus, .map_irq = nas100d_map_irq, }; diff --git a/arch/arm/mach-ixp4xx/nslu2-pci.c b/arch/arm/mach-ixp4xx/nslu2-pci.c index b57160535e47..032defe111aa 100644 --- a/arch/arm/mach-ixp4xx/nslu2-pci.c +++ b/arch/arm/mach-ixp4xx/nslu2-pci.c @@ -54,10 +54,9 @@ static int __init nslu2_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) struct hw_pci __initdata nslu2_pci = { .nr_controllers = 1, + .ops = &ixp4xx_ops, .preinit = nslu2_pci_preinit, - .swizzle = pci_std_swizzle, .setup = ixp4xx_setup, - .scan = ixp4xx_scan_bus, .map_irq = nslu2_map_irq, }; diff --git a/arch/arm/mach-ixp4xx/vulcan-pci.c b/arch/arm/mach-ixp4xx/vulcan-pci.c index 0bc3f34c282f..a4220fa5e0c3 100644 --- a/arch/arm/mach-ixp4xx/vulcan-pci.c +++ b/arch/arm/mach-ixp4xx/vulcan-pci.c @@ -56,10 +56,9 @@ static int __init vulcan_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) struct hw_pci vulcan_pci __initdata = { .nr_controllers = 1, + .ops = &ixp4xx_ops, .preinit = vulcan_pci_preinit, - .swizzle = pci_std_swizzle, .setup = ixp4xx_setup, - .scan = ixp4xx_scan_bus, .map_irq = vulcan_map_irq, }; diff --git a/arch/arm/mach-ixp4xx/wg302v2-pci.c b/arch/arm/mach-ixp4xx/wg302v2-pci.c index f27dfcfe811b..c92e5b82af36 100644 --- a/arch/arm/mach-ixp4xx/wg302v2-pci.c +++ b/arch/arm/mach-ixp4xx/wg302v2-pci.c @@ -46,10 +46,9 @@ static int __init wg302v2_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) struct hw_pci wg302v2_pci __initdata = { .nr_controllers = 1, + .ops = &ixp4xx_ops, .preinit = wg302v2_pci_preinit, - .swizzle = pci_std_swizzle, .setup = ixp4xx_setup, - .scan = ixp4xx_scan_bus, .map_irq = wg302v2_map_irq, }; diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c index 1c672d9e6656..f7fe1b9f3170 100644 --- a/arch/arm/mach-kirkwood/board-dt.c +++ b/arch/arm/mach-kirkwood/board-dt.c @@ -14,6 +14,7 @@ #include <linux/init.h> #include <linux/of.h> #include <linux/of_platform.h> +#include <linux/kexec.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <mach/bridge-regs.h> diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c index f56a0118c1bb..de373176ee67 100644 --- a/arch/arm/mach-kirkwood/pcie.c +++ b/arch/arm/mach-kirkwood/pcie.c @@ -44,12 +44,6 @@ struct pcie_port { static int pcie_port_map[2]; static int num_pcie_ports; -static inline struct pcie_port *bus_to_port(struct pci_bus *bus) -{ - struct pci_sys_data *sys = bus->sysdata; - return sys->private_data; -} - static int pcie_valid_config(struct pcie_port *pp, int bus, int dev) { /* @@ -79,7 +73,8 @@ static int pcie_valid_config(struct pcie_port *pp, int bus, int dev) static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 *val) { - struct pcie_port *pp = bus_to_port(bus); + struct pci_sys_data *sys = bus->sysdata; + struct pcie_port *pp = sys->private_data; unsigned long flags; int ret; @@ -98,7 +93,8 @@ static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, static int pcie_wr_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 val) { - struct pcie_port *pp = bus_to_port(bus); + struct pci_sys_data *sys = bus->sysdata; + struct pcie_port *pp = sys->private_data; unsigned long flags; int ret; @@ -248,13 +244,13 @@ kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys) static int __init kirkwood_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { - struct pcie_port *pp = bus_to_port(dev->bus); + struct pci_sys_data *sys = dev->sysdata; + struct pcie_port *pp = sys->private_data; return pp->irq; } static struct hw_pci kirkwood_pci __initdata = { - .swizzle = pci_std_swizzle, .setup = kirkwood_pcie_setup, .scan = kirkwood_pcie_scan_bus, .map_irq = kirkwood_pcie_map_irq, diff --git a/arch/arm/mach-ks8695/pci.c b/arch/arm/mach-ks8695/pci.c index acc701435817..bb18193b4bac 100644 --- a/arch/arm/mach-ks8695/pci.c +++ b/arch/arm/mach-ks8695/pci.c @@ -141,12 +141,6 @@ static struct pci_ops ks8695_pci_ops = { .write = ks8695_pci_writeconfig, }; -static struct pci_bus* __init ks8695_pci_scan_bus(int nr, struct pci_sys_data *sys) -{ - return pci_scan_root_bus(NULL, sys->busnr, &ks8695_pci_ops, sys, - &sys->resources); -} - static struct resource pci_mem = { .name = "PCI Memory space", .start = KS8695_PCIMEM_PA, @@ -302,11 +296,10 @@ static void ks8695_show_pciregs(void) static struct hw_pci ks8695_pci __initdata = { .nr_controllers = 1, + .ops = &ks8695_pci_ops, .preinit = ks8695_pci_preinit, .setup = ks8695_pci_setup, - .scan = ks8695_pci_scan_bus, .postinit = NULL, - .swizzle = pci_std_swizzle, .map_irq = NULL, }; diff --git a/arch/arm/mach-msm/board-halibut.c b/arch/arm/mach-msm/board-halibut.c index 3698a370d636..26aac363a064 100644 --- a/arch/arm/mach-msm/board-halibut.c +++ b/arch/arm/mach-msm/board-halibut.c @@ -86,9 +86,6 @@ static void __init halibut_init(void) static void __init halibut_fixup(struct tag *tags, char **cmdline, struct meminfo *mi) { - mi->nr_banks=1; - mi->bank[0].start = PHYS_OFFSET; - mi->bank[0].size = (101*1024*1024); } static void __init halibut_map_io(void) diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c index 962e71169750..fb3496a52ef4 100644 --- a/arch/arm/mach-msm/board-msm8x60.c +++ b/arch/arm/mach-msm/board-msm8x60.c @@ -17,6 +17,7 @@ #include <linux/irqdomain.h> #include <linux/of.h> #include <linux/of_address.h> +#include <linux/of_irq.h> #include <linux/of_platform.h> #include <linux/memblock.h> @@ -49,10 +50,22 @@ static void __init msm8x60_map_io(void) msm_map_msm8x60_io(); } +#ifdef CONFIG_OF +static struct of_device_id msm_dt_gic_match[] __initdata = { + { .compatible = "qcom,msm-8660-qgic", .data = gic_of_init }, + {} +}; +#endif + static void __init msm8x60_init_irq(void) { - gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE, - (void *)MSM_QGIC_CPU_BASE); + if (!of_have_populated_dt()) + gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE, + (void *)MSM_QGIC_CPU_BASE); +#ifdef CONFIG_OF + else + of_irq_init(msm_dt_gic_match); +#endif /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */ writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4); @@ -73,16 +86,8 @@ static struct of_dev_auxdata msm_auxdata_lookup[] __initdata = { {} }; -static struct of_device_id msm_dt_gic_match[] __initdata = { - { .compatible = "qcom,msm-8660-qgic", }, - {} -}; - static void __init msm8x60_dt_init(void) { - irq_domain_generate_simple(msm_dt_gic_match, MSM8X60_QGIC_DIST_PHYS, - GIC_SPI_START); - if (of_machine_is_compatible("qcom,msm8660-surf")) { printk(KERN_INFO "Init surf UART registers\n"); msm8x60_init_uart12dm(); diff --git a/arch/arm/mach-msm/board-trout-panel.c b/arch/arm/mach-msm/board-trout-panel.c index 25105c1027fe..89bf6b426699 100644 --- a/arch/arm/mach-msm/board-trout-panel.c +++ b/arch/arm/mach-msm/board-trout-panel.c @@ -12,6 +12,7 @@ #include <asm/io.h> #include <asm/mach-types.h> +#include <asm/system_info.h> #include <mach/msm_fb.h> #include <mach/vreg.h> diff --git a/arch/arm/mach-msm/board-trout.c b/arch/arm/mach-msm/board-trout.c index 5414f76ec0a9..d4060a37e23d 100644 --- a/arch/arm/mach-msm/board-trout.c +++ b/arch/arm/mach-msm/board-trout.c @@ -19,6 +19,7 @@ #include <linux/platform_device.h> #include <linux/clkdev.h> +#include <asm/system_info.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> diff --git a/arch/arm/mach-msm/proc_comm.c b/arch/arm/mach-msm/proc_comm.c index 67e701c7f183..9980dc736e7b 100644 --- a/arch/arm/mach-msm/proc_comm.c +++ b/arch/arm/mach-msm/proc_comm.c @@ -121,7 +121,7 @@ int msm_proc_comm(unsigned cmd, unsigned *data1, unsigned *data2) * and unknown state. This function should be called early to * wait on the ARM9. */ -void __init proc_comm_boot_wait(void) +void __devinit proc_comm_boot_wait(void) { void __iomem *base = MSM_SHARED_RAM_BASE; diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c index df3e38055a24..2e56e86b6d68 100644 --- a/arch/arm/mach-mv78xx0/pcie.c +++ b/arch/arm/mach-mv78xx0/pcie.c @@ -147,6 +147,7 @@ static int __init mv78xx0_pcie_setup(int nr, struct pci_sys_data *sys) return 0; pp = &pcie_port[nr]; + sys->private_data = pp; pp->root_bus_nr = sys->busnr; /* @@ -161,19 +162,6 @@ static int __init mv78xx0_pcie_setup(int nr, struct pci_sys_data *sys) return 1; } -static struct pcie_port *bus_to_port(int bus) -{ - int i; - - for (i = num_pcie_ports - 1; i >= 0; i--) { - int rbus = pcie_port[i].root_bus_nr; - if (rbus != -1 && rbus <= bus) - break; - } - - return i >= 0 ? pcie_port + i : NULL; -} - static int pcie_valid_config(struct pcie_port *pp, int bus, int dev) { /* @@ -189,7 +177,8 @@ static int pcie_valid_config(struct pcie_port *pp, int bus, int dev) static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 *val) { - struct pcie_port *pp = bus_to_port(bus->number); + struct pci_sys_data *sys = bus->sysdata; + struct pcie_port *pp = sys->private_data; unsigned long flags; int ret; @@ -208,7 +197,8 @@ static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, static int pcie_wr_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 val) { - struct pcie_port *pp = bus_to_port(bus->number); + struct pci_sys_data *sys = bus->sysdata; + struct pcie_port *pp = sys->private_data; unsigned long flags; int ret; @@ -263,7 +253,8 @@ mv78xx0_pcie_scan_bus(int nr, struct pci_sys_data *sys) static int __init mv78xx0_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { - struct pcie_port *pp = bus_to_port(dev->bus->number); + struct pci_sys_data *sys = dev->bus->sysdata; + struct pcie_port *pp = sys->private_data; return IRQ_MV78XX0_PCIE_00 + (pp->maj << 2) + pp->min; } @@ -271,7 +262,6 @@ static int __init mv78xx0_pcie_map_irq(const struct pci_dev *dev, u8 slot, static struct hw_pci mv78xx0_pci __initdata = { .nr_controllers = 8, .preinit = mv78xx0_pcie_preinit, - .swizzle = pci_std_swizzle, .setup = mv78xx0_pcie_setup, .scan = mv78xx0_pcie_scan_bus, .map_irq = mv78xx0_pcie_map_irq, diff --git a/arch/arm/mach-mxs/devices-mx23.h b/arch/arm/mach-mxs/devices-mx23.h index 4d1329d59287..9acdd6387047 100644 --- a/arch/arm/mach-mxs/devices-mx23.h +++ b/arch/arm/mach-mxs/devices-mx23.h @@ -11,10 +11,16 @@ #include <mach/mx23.h> #include <mach/devices-common.h> #include <mach/mxsfb.h> +#include <linux/amba/bus.h> -extern const struct amba_device mx23_duart_device __initconst; -#define mx23_add_duart() \ - mxs_add_duart(&mx23_duart_device) +static inline int mx23_add_duart(void) +{ + struct amba_device *d; + + d = amba_ahb_device_add(NULL, "duart", MX23_DUART_BASE_ADDR, SZ_8K, + MX23_INT_DUART, 0, 0, 0); + return IS_ERR(d) ? PTR_ERR(d) : 0; +} extern const struct mxs_auart_data mx23_auart_data[] __initconst; #define mx23_add_auart(id) mxs_add_auart(&mx23_auart_data[id]) diff --git a/arch/arm/mach-mxs/devices-mx28.h b/arch/arm/mach-mxs/devices-mx28.h index 9dbeae130842..84b2960df117 100644 --- a/arch/arm/mach-mxs/devices-mx28.h +++ b/arch/arm/mach-mxs/devices-mx28.h @@ -11,10 +11,16 @@ #include <mach/mx28.h> #include <mach/devices-common.h> #include <mach/mxsfb.h> +#include <linux/amba/bus.h> -extern const struct amba_device mx28_duart_device __initconst; -#define mx28_add_duart() \ - mxs_add_duart(&mx28_duart_device) +static inline int mx28_add_duart(void) +{ + struct amba_device *d; + + d = amba_ahb_device_add(NULL, "duart", MX28_DUART_BASE_ADDR, SZ_8K, + MX28_INT_DUART, 0, 0, 0); + return IS_ERR(d) ? PTR_ERR(d) : 0; +} extern const struct mxs_auart_data mx28_auart_data[] __initconst; #define mx28_add_auart(id) mxs_add_auart(&mx28_auart_data[id]) diff --git a/arch/arm/mach-mxs/devices.c b/arch/arm/mach-mxs/devices.c index 01faffec3064..cf50b5a66dda 100644 --- a/arch/arm/mach-mxs/devices.c +++ b/arch/arm/mach-mxs/devices.c @@ -75,22 +75,6 @@ err: return pdev; } -int __init mxs_add_amba_device(const struct amba_device *dev) -{ - struct amba_device *adev = amba_device_alloc(dev->dev.init_name, - dev->res.start, resource_size(&dev->res)); - - if (!adev) { - pr_err("%s: failed to allocate memory", __func__); - return -ENOMEM; - } - - adev->irq[0] = dev->irq[0]; - adev->irq[1] = dev->irq[1]; - - return amba_device_add(adev, &iomem_resource); -} - struct device mxs_apbh_bus = { .init_name = "mxs_apbh", .parent = &platform_bus, diff --git a/arch/arm/mach-mxs/devices/Makefile b/arch/arm/mach-mxs/devices/Makefile index c8f5c9541a30..5f72d9787444 100644 --- a/arch/arm/mach-mxs/devices/Makefile +++ b/arch/arm/mach-mxs/devices/Makefile @@ -1,4 +1,3 @@ -obj-$(CONFIG_MXS_HAVE_AMBA_DUART) += amba-duart.o obj-$(CONFIG_MXS_HAVE_PLATFORM_AUART) += platform-auart.o obj-y += platform-dma.o obj-$(CONFIG_MXS_HAVE_PLATFORM_FEC) += platform-fec.o diff --git a/arch/arm/mach-mxs/devices/amba-duart.c b/arch/arm/mach-mxs/devices/amba-duart.c deleted file mode 100644 index a5479f766046..000000000000 --- a/arch/arm/mach-mxs/devices/amba-duart.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (C) 2009-2010 Pengutronix - * Uwe Kleine-Koenig <[email protected]> - * - * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include <asm/irq.h> -#include <mach/mx23.h> -#include <mach/mx28.h> -#include <mach/devices-common.h> - -#define MXS_AMBA_DUART_DEVICE(name, soc) \ -const struct amba_device name##_device __initconst = { \ - .dev = { \ - .init_name = "duart", \ - }, \ - .res = { \ - .start = soc ## _DUART_BASE_ADDR, \ - .end = (soc ## _DUART_BASE_ADDR) + SZ_8K - 1, \ - .flags = IORESOURCE_MEM, \ - }, \ - .irq = {soc ## _INT_DUART}, \ -} - -#ifdef CONFIG_SOC_IMX23 -MXS_AMBA_DUART_DEVICE(mx23_duart, MX23); -#endif - -#ifdef CONFIG_SOC_IMX28 -MXS_AMBA_DUART_DEVICE(mx28_duart, MX28); -#endif - -int __init mxs_add_duart(const struct amba_device *dev) -{ - return mxs_add_amba_device(dev); -} diff --git a/arch/arm/mach-mxs/include/mach/devices-common.h b/arch/arm/mach-mxs/include/mach/devices-common.h index f2e383955d88..21e45a70d344 100644 --- a/arch/arm/mach-mxs/include/mach/devices-common.h +++ b/arch/arm/mach-mxs/include/mach/devices-common.h @@ -27,11 +27,6 @@ static inline struct platform_device *mxs_add_platform_device( name, id, res, num_resources, data, size_data, 0); } -int __init mxs_add_amba_device(const struct amba_device *dev); - -/* duart */ -int __init mxs_add_duart(const struct amba_device *dev); - /* auart */ struct mxs_auart_data { int id; diff --git a/arch/arm/mach-omap1/ams-delta-fiq.c b/arch/arm/mach-omap1/ams-delta-fiq.c index fcce7ff37630..cfd98b186fcc 100644 --- a/arch/arm/mach-omap1/ams-delta-fiq.c +++ b/arch/arm/mach-omap1/ams-delta-fiq.c @@ -48,7 +48,7 @@ static irqreturn_t deferred_fiq(int irq, void *dev_id) struct irq_chip *irq_chip = NULL; int gpio, irq_num, fiq_count; - irq_desc = irq_to_desc(IH_GPIO_BASE); + irq_desc = irq_to_desc(gpio_to_irq(AMS_DELTA_GPIO_PIN_KEYBRD_CLK)); if (irq_desc) irq_chip = irq_desc->irq_data.chip; diff --git a/arch/arm/mach-omap1/mux.c b/arch/arm/mach-omap1/mux.c index 087dba0df47e..e9cc52d4cb28 100644 --- a/arch/arm/mach-omap1/mux.c +++ b/arch/arm/mach-omap1/mux.c @@ -27,6 +27,7 @@ #include <linux/io.h> #include <linux/spinlock.h> +#include <mach/hardware.h> #include <plat/mux.h> diff --git a/arch/arm/mach-omap1/timer.c b/arch/arm/mach-omap1/timer.c index 6e90665a7c47..fb202af01d0d 100644 --- a/arch/arm/mach-omap1/timer.c +++ b/arch/arm/mach-omap1/timer.c @@ -47,9 +47,9 @@ static int omap1_dm_timer_set_src(struct platform_device *pdev, int n = (pdev->id - 1) << 1; u32 l; - l = __raw_readl(MOD_CONF_CTRL_1) & ~(0x03 << n); + l = omap_readl(MOD_CONF_CTRL_1) & ~(0x03 << n); l |= source << n; - __raw_writel(l, MOD_CONF_CTRL_1); + omap_writel(l, MOD_CONF_CTRL_1); return 0; } diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index a39fc4bbd2b8..130ab00c09a2 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -20,6 +20,7 @@ #include <linux/usb/otg.h> #include <linux/spi/spi.h> #include <linux/i2c/twl.h> +#include <linux/mfd/twl6040.h> #include <linux/gpio_keys.h> #include <linux/regulator/machine.h> #include <linux/regulator/fixed.h> @@ -560,7 +561,7 @@ static struct regulator_init_data sdp4430_vusim = { }, }; -static struct twl4030_codec_data twl6040_codec = { +static struct twl6040_codec_data twl6040_codec = { /* single-step ramp for headset and handsfree */ .hs_left_step = 0x0f, .hs_right_step = 0x0f, @@ -568,7 +569,7 @@ static struct twl4030_codec_data twl6040_codec = { .hf_right_step = 0x1d, }; -static struct twl4030_vibra_data twl6040_vibra = { +static struct twl6040_vibra_data twl6040_vibra = { .vibldrv_res = 8, .vibrdrv_res = 3, .viblmotor_res = 10, @@ -577,16 +578,14 @@ static struct twl4030_vibra_data twl6040_vibra = { .vddvibr_uV = 0, /* fixed volt supply - VBAT */ }; -static struct twl4030_audio_data twl6040_audio = { +static struct twl6040_platform_data twl6040_data = { .codec = &twl6040_codec, .vibra = &twl6040_vibra, .audpwron_gpio = 127, - .naudint_irq = OMAP44XX_IRQ_SYS_2N, .irq_base = TWL6040_CODEC_IRQ_BASE, }; static struct twl4030_platform_data sdp4430_twldata = { - .audio = &twl6040_audio, /* Regulators */ .vusim = &sdp4430_vusim, .vaux1 = &sdp4430_vaux1, @@ -617,7 +616,8 @@ static int __init omap4_i2c_init(void) TWL_COMMON_REGULATOR_VCXIO | TWL_COMMON_REGULATOR_VUSB | TWL_COMMON_REGULATOR_CLK32KG); - omap4_pmic_init("twl6030", &sdp4430_twldata); + omap4_pmic_init("twl6030", &sdp4430_twldata, + &twl6040_data, OMAP44XX_IRQ_SYS_2N); omap_register_i2c_bus(2, 400, NULL, 0); omap_register_i2c_bus(3, 400, sdp4430_i2c_3_boardinfo, ARRAY_SIZE(sdp4430_i2c_3_boardinfo)); diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index 74e1687b5170..098d183a0086 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -137,7 +137,7 @@ static struct twl4030_platform_data sdp4430_twldata = { static void __init omap4_i2c_init(void) { - omap4_pmic_init("twl6030", &sdp4430_twldata); + omap4_pmic_init("twl6030", &sdp4430_twldata, NULL, 0); } static void __init omap4_init(void) diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index 930c0d380435..740cee9369ba 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c @@ -641,7 +641,7 @@ static struct regulator_consumer_supply dummy_supplies[] = { static void __init igep_init(void) { - regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); + regulator_register_fixed(1, dummy_supplies, ARRAY_SIZE(dummy_supplies)); omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); /* Get IGEP2 hardware revision */ diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c index d8c0e89f0126..1b782ba53433 100644 --- a/arch/arm/mach-omap2/board-omap4panda.c +++ b/arch/arm/mach-omap2/board-omap4panda.c @@ -25,6 +25,7 @@ #include <linux/gpio.h> #include <linux/usb/otg.h> #include <linux/i2c/twl.h> +#include <linux/mfd/twl6040.h> #include <linux/regulator/machine.h> #include <linux/regulator/fixed.h> #include <linux/wl12xx.h> @@ -284,7 +285,7 @@ static int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers) return 0; } -static struct twl4030_codec_data twl6040_codec = { +static struct twl6040_codec_data twl6040_codec = { /* single-step ramp for headset and handsfree */ .hs_left_step = 0x0f, .hs_right_step = 0x0f, @@ -292,17 +293,14 @@ static struct twl4030_codec_data twl6040_codec = { .hf_right_step = 0x1d, }; -static struct twl4030_audio_data twl6040_audio = { +static struct twl6040_platform_data twl6040_data = { .codec = &twl6040_codec, .audpwron_gpio = 127, - .naudint_irq = OMAP44XX_IRQ_SYS_2N, .irq_base = TWL6040_CODEC_IRQ_BASE, }; /* Panda board uses the common PMIC configuration */ -static struct twl4030_platform_data omap4_panda_twldata = { - .audio = &twl6040_audio, -}; +static struct twl4030_platform_data omap4_panda_twldata; /* * Display monitor features are burnt in their EEPROM as EDID data. The EEPROM @@ -326,7 +324,8 @@ static int __init omap4_panda_i2c_init(void) TWL_COMMON_REGULATOR_VCXIO | TWL_COMMON_REGULATOR_VUSB | TWL_COMMON_REGULATOR_CLK32KG); - omap4_pmic_init("twl6030", &omap4_panda_twldata); + omap4_pmic_init("twl6030", &omap4_panda_twldata, + &twl6040_data, OMAP44XX_IRQ_SYS_2N); omap_register_i2c_bus(2, 400, NULL, 0); /* * Bus 3 is attached to the DVI port where devices like the pico DLP diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c index 7072e0d651b1..3d9d746b221a 100644 --- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c +++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c @@ -165,83 +165,3 @@ int omap2_select_table_rate(struct clk *clk, unsigned long rate) return 0; } - -#ifdef CONFIG_CPU_FREQ -/* - * Walk PRCM rate table and fillout cpufreq freq_table - * XXX This should be replaced by an OPP layer in the near future - */ -static struct cpufreq_frequency_table *freq_table; - -void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table) -{ - const struct prcm_config *prcm; - int i = 0; - int tbl_sz = 0; - - if (!cpu_is_omap24xx()) - return; - - for (prcm = rate_table; prcm->mpu_speed; prcm++) { - if (!(prcm->flags & cpu_mask)) - continue; - if (prcm->xtal_speed != sclk->rate) - continue; - - /* don't put bypass rates in table */ - if (prcm->dpll_speed == prcm->xtal_speed) - continue; - - tbl_sz++; - } - - /* - * XXX Ensure that we're doing what CPUFreq expects for this error - * case and the following one - */ - if (tbl_sz == 0) { - pr_warning("%s: no matching entries in rate_table\n", - __func__); - return; - } - - /* Include the CPUFREQ_TABLE_END terminator entry */ - tbl_sz++; - - freq_table = kzalloc(sizeof(struct cpufreq_frequency_table) * tbl_sz, - GFP_ATOMIC); - if (!freq_table) { - pr_err("%s: could not kzalloc frequency table\n", __func__); - return; - } - - for (prcm = rate_table; prcm->mpu_speed; prcm++) { - if (!(prcm->flags & cpu_mask)) - continue; - if (prcm->xtal_speed != sclk->rate) - continue; - - /* don't put bypass rates in table */ - if (prcm->dpll_speed == prcm->xtal_speed) - continue; - - freq_table[i].index = i; - freq_table[i].frequency = prcm->mpu_speed / 1000; - i++; - } - - freq_table[i].index = i; - freq_table[i].frequency = CPUFREQ_TABLE_END; - - *table = &freq_table[0]; -} - -void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table) -{ - if (!cpu_is_omap24xx()) - return; - - kfree(freq_table); -} - -#endif diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index f57ed5baeccf..d9f4931513f9 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -536,10 +536,5 @@ struct clk_functions omap2_clk_functions = { .clk_set_rate = omap2_clk_set_rate, .clk_set_parent = omap2_clk_set_parent, .clk_disable_unused = omap2_clk_disable_unused, -#ifdef CONFIG_CPU_FREQ - /* These will be removed when the OPP code is integrated */ - .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table, - .clk_exit_cpufreq_table = omap2_clk_exit_cpufreq_table, -#endif }; diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index b8c2a686481c..a1bb23a23351 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -146,14 +146,6 @@ extern const struct clksel_rate gpt_sys_rates[]; extern const struct clksel_rate gfx_l3_rates[]; extern const struct clksel_rate dsp_ick_rates[]; -#if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_CPU_FREQ) -extern void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table); -extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table); -#else -#define omap2_clk_init_cpufreq_table 0 -#define omap2_clk_exit_cpufreq_table 0 -#endif - extern const struct clkops clkops_omap2_iclk_dflt_wait; extern const struct clkops clkops_omap2_iclk_dflt; extern const struct clkops clkops_omap2_iclk_idle_only; diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h index 1e2d3322f33e..c88420de1151 100644 --- a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h +++ b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h @@ -941,10 +941,10 @@ #define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29) #define OMAP4_DSI1_LANEENABLE_SHIFT 24 #define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24) -#define OMAP4_DSI2_PIPD_SHIFT 19 -#define OMAP4_DSI2_PIPD_MASK (0x1f << 19) -#define OMAP4_DSI1_PIPD_SHIFT 14 -#define OMAP4_DSI1_PIPD_MASK (0x1f << 14) +#define OMAP4_DSI1_PIPD_SHIFT 19 +#define OMAP4_DSI1_PIPD_MASK (0x1f << 19) +#define OMAP4_DSI2_PIPD_SHIFT 14 +#define OMAP4_DSI2_PIPD_MASK (0x1f << 14) /* CONTROL_MCBSPLP */ #define OMAP4_ALBCTRLRX_FSX_SHIFT 31 diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 2c27fdb61e66..7144ae651d3d 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -1422,6 +1422,9 @@ static int _ocp_softreset(struct omap_hwmod *oh) goto dis_opt_clks; _write_sysconfig(v, oh); + if (oh->class->sysc->srst_udelay) + udelay(oh->class->sysc->srst_udelay); + if (oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS) omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs) @@ -1903,10 +1906,20 @@ void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs) */ int omap_hwmod_softreset(struct omap_hwmod *oh) { - if (!oh) + u32 v; + int ret; + + if (!oh || !(oh->_sysc_cache)) return -EINVAL; - return _ocp_softreset(oh); + v = oh->_sysc_cache; + ret = _set_softreset(oh, &v); + if (ret) + goto error; + _write_sysconfig(v, oh); + +error: + return ret; } /** diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index a5409ce3f323..a6bde34e443a 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -1000,7 +1000,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = { .flags = OMAP_FIREWALL_L4, } }, - .flags = OCPIF_SWSUP_IDLE, .user = OCP_USER_MPU | OCP_USER_SDMA, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index c4f56cb60d7d..04a3885f4475 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -1049,7 +1049,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = { .slave = &omap2430_dss_venc_hwmod, .clk = "dss_ick", .addr = omap2_dss_venc_addrs, - .flags = OCPIF_SWSUP_IDLE, .user = OCP_USER_MPU | OCP_USER_SDMA, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 34b9766d1d23..db86ce90c69f 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -1676,7 +1676,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = { .flags = OMAP_FIREWALL_L4, } }, - .flags = OCPIF_SWSUP_IDLE, .user = OCP_USER_MPU | OCP_USER_SDMA, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index cc9bd106a854..6abc75753e42 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -2594,6 +2594,15 @@ static struct omap_hwmod omap44xx_ipu_hwmod = { static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = { .rev_offs = 0x0000, .sysc_offs = 0x0010, + /* + * ISS needs 100 OCP clk cycles delay after a softreset before + * accessing sysconfig again. + * The lowest frequency at the moment for L3 bus is 100 MHz, so + * 1usec delay is needed. Add an x2 margin to be safe (2 usecs). + * + * TODO: Indicate errata when available. + */ + .srst_udelay = 2, .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index 0cdd359a128e..9fc2f44188cb 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c @@ -108,8 +108,14 @@ static void omap_uart_set_noidle(struct platform_device *pdev) static void omap_uart_set_smartidle(struct platform_device *pdev) { struct omap_device *od = to_omap_device(pdev); + u8 idlemode; - omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_SMART); + if (od->hwmods[0]->class->sysc->idlemodes & SIDLE_SMART_WKUP) + idlemode = HWMOD_IDLEMODE_SMART_WKUP; + else + idlemode = HWMOD_IDLEMODE_SMART; + + omap_hwmod_set_slave_idlemode(od->hwmods[0], idlemode); } #else @@ -120,124 +126,8 @@ static void omap_uart_set_smartidle(struct platform_device *pdev) {} #endif /* CONFIG_PM */ #ifdef CONFIG_OMAP_MUX -static struct omap_device_pad default_uart1_pads[] __initdata = { - { - .name = "uart1_cts.uart1_cts", - .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0, - }, - { - .name = "uart1_rts.uart1_rts", - .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0, - }, - { - .name = "uart1_tx.uart1_tx", - .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0, - }, - { - .name = "uart1_rx.uart1_rx", - .flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP, - .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0, - .idle = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0, - }, -}; - -static struct omap_device_pad default_uart2_pads[] __initdata = { - { - .name = "uart2_cts.uart2_cts", - .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0, - }, - { - .name = "uart2_rts.uart2_rts", - .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0, - }, - { - .name = "uart2_tx.uart2_tx", - .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0, - }, - { - .name = "uart2_rx.uart2_rx", - .flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP, - .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0, - .idle = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0, - }, -}; - -static struct omap_device_pad default_uart3_pads[] __initdata = { - { - .name = "uart3_cts_rctx.uart3_cts_rctx", - .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0, - }, - { - .name = "uart3_rts_sd.uart3_rts_sd", - .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0, - }, - { - .name = "uart3_tx_irtx.uart3_tx_irtx", - .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0, - }, - { - .name = "uart3_rx_irrx.uart3_rx_irrx", - .flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP, - .enable = OMAP_PIN_INPUT | OMAP_MUX_MODE0, - .idle = OMAP_PIN_INPUT | OMAP_MUX_MODE0, - }, -}; - -static struct omap_device_pad default_omap36xx_uart4_pads[] __initdata = { - { - .name = "gpmc_wait2.uart4_tx", - .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0, - }, - { - .name = "gpmc_wait3.uart4_rx", - .flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP, - .enable = OMAP_PIN_INPUT | OMAP_MUX_MODE2, - .idle = OMAP_PIN_INPUT | OMAP_MUX_MODE2, - }, -}; - -static struct omap_device_pad default_omap4_uart4_pads[] __initdata = { - { - .name = "uart4_tx.uart4_tx", - .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0, - }, - { - .name = "uart4_rx.uart4_rx", - .flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP, - .enable = OMAP_PIN_INPUT | OMAP_MUX_MODE0, - .idle = OMAP_PIN_INPUT | OMAP_MUX_MODE0, - }, -}; - static void omap_serial_fill_default_pads(struct omap_board_data *bdata) { - switch (bdata->id) { - case 0: - bdata->pads = default_uart1_pads; - bdata->pads_cnt = ARRAY_SIZE(default_uart1_pads); - break; - case 1: - bdata->pads = default_uart2_pads; - bdata->pads_cnt = ARRAY_SIZE(default_uart2_pads); - break; - case 2: - bdata->pads = default_uart3_pads; - bdata->pads_cnt = ARRAY_SIZE(default_uart3_pads); - break; - case 3: - if (cpu_is_omap44xx()) { - bdata->pads = default_omap4_uart4_pads; - bdata->pads_cnt = - ARRAY_SIZE(default_omap4_uart4_pads); - } else if (cpu_is_omap3630()) { - bdata->pads = default_omap36xx_uart4_pads; - bdata->pads_cnt = - ARRAY_SIZE(default_omap36xx_uart4_pads); - } - break; - default: - break; - } } #else static void omap_serial_fill_default_pads(struct omap_board_data *bdata) {} diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c index 4b57757bf9d1..7a7b89304c48 100644 --- a/arch/arm/mach-omap2/twl-common.c +++ b/arch/arm/mach-omap2/twl-common.c @@ -37,6 +37,16 @@ static struct i2c_board_info __initdata pmic_i2c_board_info = { .flags = I2C_CLIENT_WAKE, }; +static struct i2c_board_info __initdata omap4_i2c1_board_info[] = { + { + .addr = 0x48, + .flags = I2C_CLIENT_WAKE, + }, + { + I2C_BOARD_INFO("twl6040", 0x4b), + }, +}; + void __init omap_pmic_init(int bus, u32 clkrate, const char *pmic_type, int pmic_irq, struct twl4030_platform_data *pmic_data) @@ -49,14 +59,31 @@ void __init omap_pmic_init(int bus, u32 clkrate, omap_register_i2c_bus(bus, clkrate, &pmic_i2c_board_info, 1); } +void __init omap4_pmic_init(const char *pmic_type, + struct twl4030_platform_data *pmic_data, + struct twl6040_platform_data *twl6040_data, int twl6040_irq) +{ + /* PMIC part*/ + strncpy(omap4_i2c1_board_info[0].type, pmic_type, + sizeof(omap4_i2c1_board_info[0].type)); + omap4_i2c1_board_info[0].irq = OMAP44XX_IRQ_SYS_1N; + omap4_i2c1_board_info[0].platform_data = pmic_data; + + /* TWL6040 audio IC part */ + omap4_i2c1_board_info[1].irq = twl6040_irq; + omap4_i2c1_board_info[1].platform_data = twl6040_data; + + omap_register_i2c_bus(1, 400, omap4_i2c1_board_info, 2); + +} + void __init omap_pmic_late_init(void) { /* Init the OMAP TWL parameters (if PMIC has been registerd) */ - if (!pmic_i2c_board_info.irq) - return; - - omap3_twl_init(); - omap4_twl_init(); + if (pmic_i2c_board_info.irq) + omap3_twl_init(); + if (omap4_i2c1_board_info[0].irq) + omap4_twl_init(); } #if defined(CONFIG_ARCH_OMAP3) diff --git a/arch/arm/mach-omap2/twl-common.h b/arch/arm/mach-omap2/twl-common.h index 275dde8cb27a..09627483a57f 100644 --- a/arch/arm/mach-omap2/twl-common.h +++ b/arch/arm/mach-omap2/twl-common.h @@ -29,6 +29,7 @@ struct twl4030_platform_data; +struct twl6040_platform_data; void omap_pmic_init(int bus, u32 clkrate, const char *pmic_type, int pmic_irq, struct twl4030_platform_data *pmic_data); @@ -46,12 +47,9 @@ static inline void omap3_pmic_init(const char *pmic_type, omap_pmic_init(1, 2600, pmic_type, INT_34XX_SYS_NIRQ, pmic_data); } -static inline void omap4_pmic_init(const char *pmic_type, - struct twl4030_platform_data *pmic_data) -{ - /* Phoenix Audio IC needs I2C1 to start with 400 KHz or less */ - omap_pmic_init(1, 400, pmic_type, OMAP44XX_IRQ_SYS_1N, pmic_data); -} +void omap4_pmic_init(const char *pmic_type, + struct twl4030_platform_data *pmic_data, + struct twl6040_platform_data *audio_data, int twl6040_irq); void omap3_pmic_get_config(struct twl4030_platform_data *pmic_data, u32 pdata_flags, u32 regulators_flags); diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c index e52108c9aaea..49a3fd630313 100644 --- a/arch/arm/mach-orion5x/db88f5281-setup.c +++ b/arch/arm/mach-orion5x/db88f5281-setup.c @@ -265,7 +265,6 @@ static int __init db88f5281_pci_map_irq(const struct pci_dev *dev, u8 slot, static struct hw_pci db88f5281_pci __initdata = { .nr_controllers = 2, .preinit = db88f5281_pci_preinit, - .swizzle = pci_std_swizzle, .setup = orion5x_pci_sys_setup, .scan = orion5x_pci_sys_scan_bus, .map_irq = db88f5281_pci_map_irq, diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c index c3ed15b8ea25..8c06ccac44c2 100644 --- a/arch/arm/mach-orion5x/dns323-setup.c +++ b/arch/arm/mach-orion5x/dns323-setup.c @@ -86,7 +86,6 @@ static int __init dns323_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) static struct hw_pci dns323_pci __initdata = { .nr_controllers = 2, - .swizzle = pci_std_swizzle, .setup = orion5x_pci_sys_setup, .scan = orion5x_pci_sys_scan_bus, .map_irq = dns323_pci_map_irq, diff --git a/arch/arm/mach-orion5x/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c index 47587b832842..1e458efafb9a 100644 --- a/arch/arm/mach-orion5x/kurobox_pro-setup.c +++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c @@ -138,7 +138,6 @@ static int __init kurobox_pro_pci_map_irq(const struct pci_dev *dev, u8 slot, static struct hw_pci kurobox_pro_pci __initdata = { .nr_controllers = 2, - .swizzle = pci_std_swizzle, .setup = orion5x_pci_sys_setup, .scan = orion5x_pci_sys_scan_bus, .map_irq = kurobox_pro_pci_map_irq, diff --git a/arch/arm/mach-orion5x/mpp.h b/arch/arm/mach-orion5x/mpp.h index eac68978a2c2..db70e79a1198 100644 --- a/arch/arm/mach-orion5x/mpp.h +++ b/arch/arm/mach-orion5x/mpp.h @@ -65,8 +65,8 @@ #define MPP8_GIGE MPP(8, 0x1, 0, 0, 1, 1, 1) #define MPP9_UNUSED MPP(9, 0x0, 0, 0, 1, 1, 1) -#define MPP9_GPIO MPP(9, 0x0, 0, 0, 1, 1, 1) -#define MPP9_GIGE MPP(9, 0x1, 1, 1, 1, 1, 1) +#define MPP9_GPIO MPP(9, 0x0, 1, 1, 1, 1, 1) +#define MPP9_GIGE MPP(9, 0x1, 0, 0, 1, 1, 1) #define MPP10_UNUSED MPP(10, 0x0, 0, 0, 1, 1, 1) #define MPP10_GPIO MPP(10, 0x0, 1, 1, 1, 1, 1) diff --git a/arch/arm/mach-orion5x/mss2-setup.c b/arch/arm/mach-orion5x/mss2-setup.c index 65faaa34de61..1c16d045333e 100644 --- a/arch/arm/mach-orion5x/mss2-setup.c +++ b/arch/arm/mach-orion5x/mss2-setup.c @@ -89,7 +89,6 @@ static int __init mss2_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) static struct hw_pci mss2_pci __initdata = { .nr_controllers = 2, - .swizzle = pci_std_swizzle, .setup = orion5x_pci_sys_setup, .scan = orion5x_pci_sys_scan_bus, .map_irq = mss2_pci_map_irq, diff --git a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c index 292038fc59fd..78a6a11d8216 100644 --- a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c +++ b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c @@ -149,7 +149,6 @@ rd88f5181l_fxo_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) static struct hw_pci rd88f5181l_fxo_pci __initdata = { .nr_controllers = 2, - .swizzle = pci_std_swizzle, .setup = orion5x_pci_sys_setup, .scan = orion5x_pci_sys_scan_bus, .map_irq = rd88f5181l_fxo_pci_map_irq, diff --git a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c index c44eabaabc16..2f5dc54cd4cd 100644 --- a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c +++ b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c @@ -161,7 +161,6 @@ rd88f5181l_ge_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) static struct hw_pci rd88f5181l_ge_pci __initdata = { .nr_controllers = 2, - .swizzle = pci_std_swizzle, .setup = orion5x_pci_sys_setup, .scan = orion5x_pci_sys_scan_bus, .map_irq = rd88f5181l_ge_pci_map_irq, diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c index e3ce61711478..399130fac0b6 100644 --- a/arch/arm/mach-orion5x/rd88f5182-setup.c +++ b/arch/arm/mach-orion5x/rd88f5182-setup.c @@ -200,7 +200,6 @@ static int __init rd88f5182_pci_map_irq(const struct pci_dev *dev, u8 slot, static struct hw_pci rd88f5182_pci __initdata = { .nr_controllers = 2, .preinit = rd88f5182_pci_preinit, - .swizzle = pci_std_swizzle, .setup = orion5x_pci_sys_setup, .scan = orion5x_pci_sys_scan_bus, .map_irq = rd88f5182_pci_map_irq, diff --git a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c index 2c5fab00d205..e91bf0ba4e8e 100644 --- a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c +++ b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c @@ -102,7 +102,6 @@ static void __init rd88f6183ap_ge_init(void) static struct hw_pci rd88f6183ap_ge_pci __initdata = { .nr_controllers = 2, - .swizzle = pci_std_swizzle, .setup = orion5x_pci_sys_setup, .scan = orion5x_pci_sys_scan_bus, .map_irq = orion5x_pci_map_irq, diff --git a/arch/arm/mach-orion5x/terastation_pro2-setup.c b/arch/arm/mach-orion5x/terastation_pro2-setup.c index 632a861ef82b..90e571dc4deb 100644 --- a/arch/arm/mach-orion5x/terastation_pro2-setup.c +++ b/arch/arm/mach-orion5x/terastation_pro2-setup.c @@ -122,7 +122,6 @@ static int __init tsp2_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) static struct hw_pci tsp2_pci __initdata = { .nr_controllers = 2, .preinit = tsp2_pci_preinit, - .swizzle = pci_std_swizzle, .setup = orion5x_pci_sys_setup, .scan = orion5x_pci_sys_scan_bus, .map_irq = tsp2_pci_map_irq, diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c index 5d6408745582..b184f680e0db 100644 --- a/arch/arm/mach-orion5x/ts209-setup.c +++ b/arch/arm/mach-orion5x/ts209-setup.c @@ -170,7 +170,6 @@ static int __init qnap_ts209_pci_map_irq(const struct pci_dev *dev, u8 slot, static struct hw_pci qnap_ts209_pci __initdata = { .nr_controllers = 2, .preinit = qnap_ts209_pci_preinit, - .swizzle = pci_std_swizzle, .setup = orion5x_pci_sys_setup, .scan = orion5x_pci_sys_scan_bus, .map_irq = qnap_ts209_pci_map_irq, diff --git a/arch/arm/mach-orion5x/ts409-setup.c b/arch/arm/mach-orion5x/ts409-setup.c index 4e6ff759cd32..a5c2e64c4ece 100644 --- a/arch/arm/mach-orion5x/ts409-setup.c +++ b/arch/arm/mach-orion5x/ts409-setup.c @@ -140,7 +140,6 @@ static int __init qnap_ts409_pci_map_irq(const struct pci_dev *dev, u8 slot, static struct hw_pci qnap_ts409_pci __initdata = { .nr_controllers = 2, - .swizzle = pci_std_swizzle, .setup = orion5x_pci_sys_setup, .scan = orion5x_pci_sys_scan_bus, .map_irq = qnap_ts409_pci_map_irq, diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c index 078c03f7cd52..754c12b6abf0 100644 --- a/arch/arm/mach-orion5x/wnr854t-setup.c +++ b/arch/arm/mach-orion5x/wnr854t-setup.c @@ -155,7 +155,6 @@ static int __init wnr854t_pci_map_irq(const struct pci_dev *dev, u8 slot, static struct hw_pci wnr854t_pci __initdata = { .nr_controllers = 2, - .swizzle = pci_std_swizzle, .setup = orion5x_pci_sys_setup, .scan = orion5x_pci_sys_scan_bus, .map_irq = wnr854t_pci_map_irq, diff --git a/arch/arm/mach-orion5x/wrt350n-v2-setup.c b/arch/arm/mach-orion5x/wrt350n-v2-setup.c index 46a9778171ce..45c21251eb1e 100644 --- a/arch/arm/mach-orion5x/wrt350n-v2-setup.c +++ b/arch/arm/mach-orion5x/wrt350n-v2-setup.c @@ -243,7 +243,6 @@ static int __init wrt350n_v2_pci_map_irq(const struct pci_dev *dev, u8 slot, static struct hw_pci wrt350n_v2_pci __initdata = { .nr_controllers = 2, - .swizzle = pci_std_swizzle, .setup = orion5x_pci_sys_setup, .scan = orion5x_pci_sys_scan_bus, .map_irq = wrt350n_v2_pci_map_irq, diff --git a/arch/arm/mach-prima2/irq.c b/arch/arm/mach-prima2/irq.c index 37c2de9b6f26..a7b9415d30f8 100644 --- a/arch/arm/mach-prima2/irq.c +++ b/arch/arm/mach-prima2/irq.c @@ -42,7 +42,8 @@ sirfsoc_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num) static __init void sirfsoc_irq_init(void) { sirfsoc_alloc_gc(sirfsoc_intc_base, 0, 32); - sirfsoc_alloc_gc(sirfsoc_intc_base + 4, 32, SIRFSOC_INTENAL_IRQ_END - 32); + sirfsoc_alloc_gc(sirfsoc_intc_base + 4, 32, + SIRFSOC_INTENAL_IRQ_END + 1 - 32); writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0); writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1); @@ -68,7 +69,8 @@ void __init sirfsoc_of_irq_init(void) if (!sirfsoc_intc_base) panic("unable to map intc cpu registers\n"); - irq_domain_add_legacy(np, 32, 0, 0, &irq_domain_simple_ops, NULL); + irq_domain_add_legacy(np, SIRFSOC_INTENAL_IRQ_END + 1, 0, 0, + &irq_domain_simple_ops, NULL); of_node_put(np); diff --git a/arch/arm/mach-pxa/cm-x2xx-pci.c b/arch/arm/mach-pxa/cm-x2xx-pci.c index ebd9259f5ac9..d8f816c24a2f 100644 --- a/arch/arm/mach-pxa/cm-x2xx-pci.c +++ b/arch/arm/mach-pxa/cm-x2xx-pci.c @@ -181,11 +181,10 @@ static void cmx2xx_pci_preinit(void) } static struct hw_pci cmx2xx_pci __initdata = { - .swizzle = pci_std_swizzle, .map_irq = cmx2xx_pci_map_irq, .nr_controllers = 1, + .ops = &it8152_ops, .setup = it8152_pci_setup, - .scan = it8152_pci_scan_bus, .preinit = cmx2xx_pci_preinit, }; diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h b/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h index c54cef25895c..cbf51ae81855 100644 --- a/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h +++ b/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h @@ -17,6 +17,7 @@ * * bit 23 - Input/Output (PXA2xx specific) * bit 24 - Wakeup Enable(PXA2xx specific) + * bit 25 - Keep Output (PXA2xx specific) */ #define MFP_DIR_IN (0x0 << 23) @@ -25,6 +26,12 @@ #define MFP_DIR(x) (((x) >> 23) & 0x1) #define MFP_LPM_CAN_WAKEUP (0x1 << 24) + +/* + * MFP_LPM_KEEP_OUTPUT must be specified for pins that need to + * retain their last output level (low or high). + * Note: MFP_LPM_KEEP_OUTPUT has no effect on pins configured for input. + */ #define MFP_LPM_KEEP_OUTPUT (0x1 << 25) #define WAKEUP_ON_EDGE_RISE (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_RISE) diff --git a/arch/arm/mach-pxa/mfp-pxa2xx.c b/arch/arm/mach-pxa/mfp-pxa2xx.c index b0a842887780..ef0426a159d4 100644 --- a/arch/arm/mach-pxa/mfp-pxa2xx.c +++ b/arch/arm/mach-pxa/mfp-pxa2xx.c @@ -33,6 +33,8 @@ #define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2)) #define GPLR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5)) #define GPDR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x0c) +#define GPSR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x18) +#define GPCR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x24) #define PWER_WE35 (1 << 24) @@ -348,6 +350,7 @@ static inline void pxa27x_mfp_init(void) {} #ifdef CONFIG_PM static unsigned long saved_gafr[2][4]; static unsigned long saved_gpdr[4]; +static unsigned long saved_gplr[4]; static unsigned long saved_pgsr[4]; static int pxa2xx_mfp_suspend(void) @@ -366,14 +369,26 @@ static int pxa2xx_mfp_suspend(void) } for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) { - saved_gafr[0][i] = GAFR_L(i); saved_gafr[1][i] = GAFR_U(i); saved_gpdr[i] = GPDR(i * 32); + saved_gplr[i] = GPLR(i * 32); saved_pgsr[i] = PGSR(i); - GPDR(i * 32) = gpdr_lpm[i]; + GPSR(i * 32) = PGSR(i); + GPCR(i * 32) = ~PGSR(i); + } + + /* set GPDR bits taking into account MFP_LPM_KEEP_OUTPUT */ + for (i = 0; i < pxa_last_gpio; i++) { + if ((gpdr_lpm[gpio_to_bank(i)] & GPIO_bit(i)) || + ((gpio_desc[i].config & MFP_LPM_KEEP_OUTPUT) && + (saved_gpdr[gpio_to_bank(i)] & GPIO_bit(i)))) + GPDR(i) |= GPIO_bit(i); + else + GPDR(i) &= ~GPIO_bit(i); } + return 0; } @@ -384,6 +399,8 @@ static void pxa2xx_mfp_resume(void) for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) { GAFR_L(i) = saved_gafr[0][i]; GAFR_U(i) = saved_gafr[1][i]; + GPSR(i * 32) = saved_gplr[i]; + GPCR(i * 32) = ~saved_gplr[i]; GPDR(i * 32) = saved_gpdr[i]; PGSR(i) = saved_pgsr[i]; } diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index 6bce78edce7a..4726c246dcdc 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c @@ -421,8 +421,11 @@ void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info) pxa_register_device(&pxa27x_device_i2c_power, info); } +static struct pxa_gpio_platform_data pxa27x_gpio_info __initdata = { + .gpio_set_wake = gpio_set_wake, +}; + static struct platform_device *devices[] __initdata = { - &pxa_device_gpio, &pxa27x_device_udc, &pxa_device_pmu, &pxa_device_i2s, @@ -458,6 +461,7 @@ static int __init pxa27x_init(void) register_syscore_ops(&pxa2xx_mfp_syscore_ops); register_syscore_ops(&pxa2xx_clock_syscore_ops); + pxa_register_device(&pxa_device_gpio, &pxa27x_gpio_info); ret = platform_add_devices(devices, ARRAY_SIZE(devices)); } diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig index 0f3a327ebcaa..b34287ab5afd 100644 --- a/arch/arm/mach-s3c24xx/Kconfig +++ b/arch/arm/mach-s3c24xx/Kconfig @@ -111,10 +111,6 @@ config S3C24XX_SETUP_TS help Compile in platform device definition for Samsung TouchScreen. -# cpu-specific sections - -if CPU_S3C2410 - config S3C2410_DMA bool depends on S3C24XX_DMA && (CPU_S3C2410 || CPU_S3C2442) @@ -127,6 +123,10 @@ config S3C2410_PM help Power Management code common to S3C2410 and better +# cpu-specific sections + +if CPU_S3C2410 + config S3C24XX_SIMTEC_NOR bool help diff --git a/arch/arm/mach-s5pv210/dma.c b/arch/arm/mach-s5pv210/dma.c index 86ce62f66190..b8337e248b09 100644 --- a/arch/arm/mach-s5pv210/dma.c +++ b/arch/arm/mach-s5pv210/dma.c @@ -33,8 +33,6 @@ #include <mach/irqs.h> #include <mach/dma.h> -static u64 dma_dmamask = DMA_BIT_MASK(32); - static u8 pdma0_peri[] = { DMACH_UART0_RX, DMACH_UART0_TX, diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c index a9ea64e0da0d..48d018f2332b 100644 --- a/arch/arm/mach-s5pv210/mach-aquila.c +++ b/arch/arm/mach-s5pv210/mach-aquila.c @@ -484,8 +484,8 @@ static struct wm8994_pdata wm8994_platform_data = { .gpio_defaults[8] = 0x0100, .gpio_defaults[9] = 0x0100, .gpio_defaults[10] = 0x0100, - .ldo[0] = { S5PV210_MP03(6), NULL, &wm8994_ldo1_data }, /* XM0FRNB_2 */ - .ldo[1] = { 0, NULL, &wm8994_ldo2_data }, + .ldo[0] = { S5PV210_MP03(6), &wm8994_ldo1_data }, /* XM0FRNB_2 */ + .ldo[1] = { 0, &wm8994_ldo2_data }, }; /* GPIO I2C PMIC */ diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c index 2cf5ed75f390..32395664e879 100644 --- a/arch/arm/mach-s5pv210/mach-goni.c +++ b/arch/arm/mach-s5pv210/mach-goni.c @@ -25,6 +25,7 @@ #include <linux/gpio_keys.h> #include <linux/input.h> #include <linux/gpio.h> +#include <linux/mmc/host.h> #include <linux/interrupt.h> #include <asm/hardware/vic.h> @@ -674,8 +675,8 @@ static struct wm8994_pdata wm8994_platform_data = { .gpio_defaults[8] = 0x0100, .gpio_defaults[9] = 0x0100, .gpio_defaults[10] = 0x0100, - .ldo[0] = { S5PV210_MP03(6), NULL, &wm8994_ldo1_data }, /* XM0FRNB_2 */ - .ldo[1] = { 0, NULL, &wm8994_ldo2_data }, + .ldo[0] = { S5PV210_MP03(6), &wm8994_ldo1_data }, /* XM0FRNB_2 */ + .ldo[1] = { 0, &wm8994_ldo2_data }, }; /* GPIO I2C PMIC */ @@ -765,6 +766,7 @@ static void __init goni_pmic_init(void) /* MoviNAND */ static struct s3c_sdhci_platdata goni_hsmmc0_data __initdata = { .max_width = 4, + .host_caps2 = MMC_CAP2_BROKEN_VOLTAGE, .cd_type = S3C_SDHCI_CD_PERMANENT, }; diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c index 7c524b4e415d..16be4c56abe3 100644 --- a/arch/arm/mach-sa1100/generic.c +++ b/arch/arm/mach-sa1100/generic.c @@ -306,7 +306,7 @@ void sa11x0_register_irda(struct irda_platform_data *irda) } static struct resource sa1100_rtc_resources[] = { - DEFINE_RES_MEM(0x90010000, 0x9001003f), + DEFINE_RES_MEM(0x90010000, 0x40), DEFINE_RES_IRQ_NAMED(IRQ_RTC1Hz, "rtc 1Hz"), DEFINE_RES_IRQ_NAMED(IRQ_RTCAlrm, "rtc alarm"), }; diff --git a/arch/arm/mach-sa1100/pci-nanoengine.c b/arch/arm/mach-sa1100/pci-nanoengine.c index b49108b890a8..ff02e2da99f2 100644 --- a/arch/arm/mach-sa1100/pci-nanoengine.c +++ b/arch/arm/mach-sa1100/pci-nanoengine.c @@ -129,12 +129,6 @@ static int __init pci_nanoengine_map_irq(const struct pci_dev *dev, u8 slot, return NANOENGINE_IRQ_GPIO_PCI; } -struct pci_bus * __init pci_nanoengine_scan_bus(int nr, struct pci_sys_data *sys) -{ - return pci_scan_root_bus(NULL, sys->busnr, &pci_nano_ops, sys, - &sys->resources); -} - static struct resource pci_io_ports = DEFINE_RES_IO_NAMED(0x400, 0x400, "PCI IO"); @@ -274,7 +268,7 @@ int __init pci_nanoengine_setup(int nr, struct pci_sys_data *sys) static struct hw_pci nanoengine_pci __initdata = { .map_irq = pci_nanoengine_map_irq, .nr_controllers = 1, - .scan = pci_nanoengine_scan_bus, + .ops = &pci_nano_ops, .setup = pci_nanoengine_setup, }; diff --git a/arch/arm/mach-shark/pci.c b/arch/arm/mach-shark/pci.c index 7cb79a092f31..9089407d5326 100644 --- a/arch/arm/mach-shark/pci.c +++ b/arch/arm/mach-shark/pci.c @@ -29,10 +29,9 @@ extern void __init via82c505_preinit(void); static struct hw_pci shark_pci __initdata = { .setup = via82c505_setup, - .swizzle = pci_std_swizzle, .map_irq = shark_map_irq, .nr_controllers = 1, - .scan = via82c505_scan_bus, + .ops = &via82c505_ops, .preinit = via82c505_preinit, }; diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c index cb224a344af0..0891ec6e27f5 100644 --- a/arch/arm/mach-shmobile/board-ag5evm.c +++ b/arch/arm/mach-shmobile/board-ag5evm.c @@ -365,23 +365,13 @@ static struct platform_device mipidsi0_device = { }; /* SDHI0 */ -static irqreturn_t ag5evm_sdhi0_gpio_cd(int irq, void *arg) -{ - struct device *dev = arg; - struct sh_mobile_sdhi_info *info = dev->platform_data; - struct tmio_mmc_data *pdata = info->pdata; - - tmio_mmc_cd_wakeup(pdata); - - return IRQ_HANDLED; -} - static struct sh_mobile_sdhi_info sdhi0_info = { .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, - .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT, + .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD, .tmio_caps = MMC_CAP_SD_HIGHSPEED, .tmio_ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29, + .cd_gpio = GPIO_PORT251, }; static struct resource sdhi0_resources[] = { @@ -557,7 +547,6 @@ static void __init ag5evm_init(void) lcd_backlight_reset(); /* enable SDHI0 on CN15 [SD I/F] */ - gpio_request(GPIO_FN_SDHICD0, NULL); gpio_request(GPIO_FN_SDHIWP0, NULL); gpio_request(GPIO_FN_SDHICMD0, NULL); gpio_request(GPIO_FN_SDHICLK0, NULL); @@ -566,13 +555,6 @@ static void __init ag5evm_init(void) gpio_request(GPIO_FN_SDHID0_1, NULL); gpio_request(GPIO_FN_SDHID0_0, NULL); - if (!request_irq(intcs_evt2irq(0x3c0), ag5evm_sdhi0_gpio_cd, - IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, - "sdhi0 cd", &sdhi0_device.dev)) - sdhi0_info.tmio_flags |= TMIO_MMC_HAS_COLD_CD; - else - pr_warn("Unable to setup SDHI0 GPIO IRQ\n"); - /* enable SDHI1 on CN4 [WLAN I/F] */ gpio_request(GPIO_FN_SDHICLK1, NULL); gpio_request(GPIO_FN_SDHICMD1_PU, NULL); diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c index f49e28abe0ab..8c6202bb6aeb 100644 --- a/arch/arm/mach-shmobile/board-mackerel.c +++ b/arch/arm/mach-shmobile/board-mackerel.c @@ -1011,21 +1011,12 @@ static int slot_cn7_get_cd(struct platform_device *pdev) } /* SDHI0 */ -static irqreturn_t mackerel_sdhi0_gpio_cd(int irq, void *arg) -{ - struct device *dev = arg; - struct sh_mobile_sdhi_info *info = dev->platform_data; - struct tmio_mmc_data *pdata = info->pdata; - - tmio_mmc_cd_wakeup(pdata); - - return IRQ_HANDLED; -} - static struct sh_mobile_sdhi_info sdhi0_info = { .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, + .tmio_flags = TMIO_MMC_USE_GPIO_CD, .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ, + .cd_gpio = GPIO_PORT172, }; static struct resource sdhi0_resources[] = { @@ -1384,7 +1375,6 @@ static void __init mackerel_init(void) { u32 srcr4; struct clk *clk; - int ret; /* External clock source */ clk_set_rate(&sh7372_dv_clki_clk, 27000000); @@ -1481,7 +1471,6 @@ static void __init mackerel_init(void) irq_set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH); /* enable SDHI0 */ - gpio_request(GPIO_FN_SDHICD0, NULL); gpio_request(GPIO_FN_SDHIWP0, NULL); gpio_request(GPIO_FN_SDHICMD0, NULL); gpio_request(GPIO_FN_SDHICLK0, NULL); @@ -1490,13 +1479,6 @@ static void __init mackerel_init(void) gpio_request(GPIO_FN_SDHID0_1, NULL); gpio_request(GPIO_FN_SDHID0_0, NULL); - ret = request_irq(evt2irq(0x3340), mackerel_sdhi0_gpio_cd, - IRQF_TRIGGER_FALLING, "sdhi0 cd", &sdhi0_device.dev); - if (!ret) - sdhi0_info.tmio_flags |= TMIO_MMC_HAS_COLD_CD; - else - pr_err("Cannot get IRQ #%d: %d\n", evt2irq(0x3340), ret); - #if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE) /* enable SDHI1 */ gpio_request(GPIO_FN_SDHICMD1, NULL); diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S index 6ac015c89206..b202c1272526 100644 --- a/arch/arm/mach-shmobile/headsmp.S +++ b/arch/arm/mach-shmobile/headsmp.S @@ -16,6 +16,59 @@ __CPUINIT +/* Cache invalidation nicked from arch/arm/mach-imx/head-v7.S, thanks! + * + * The secondary kernel init calls v7_flush_dcache_all before it enables + * the L1; however, the L1 comes out of reset in an undefined state, so + * the clean + invalidate performed by v7_flush_dcache_all causes a bunch + * of cache lines with uninitialized data and uninitialized tags to get + * written out to memory, which does really unpleasant things to the main + * processor. We fix this by performing an invalidate, rather than a + * clean + invalidate, before jumping into the kernel. + * + * This funciton is cloned from arch/arm/mach-tegra/headsmp.S, and needs + * to be called for both secondary cores startup and primary core resume + * procedures. Ideally, it should be moved into arch/arm/mm/cache-v7.S. + */ +ENTRY(v7_invalidate_l1) + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache + mcr p15, 2, r0, c0, c0, 0 + mrc p15, 1, r0, c0, c0, 0 + + ldr r1, =0x7fff + and r2, r1, r0, lsr #13 + + ldr r1, =0x3ff + + and r3, r1, r0, lsr #3 @ NumWays - 1 + add r2, r2, #1 @ NumSets + + and r0, r0, #0x7 + add r0, r0, #4 @ SetShift + + clz r1, r3 @ WayShift + add r4, r3, #1 @ NumWays +1: sub r2, r2, #1 @ NumSets-- + mov r3, r4 @ Temp = NumWays +2: subs r3, r3, #1 @ Temp-- + mov r5, r3, lsl r1 + mov r6, r2, lsl r0 + orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift) + mcr p15, 0, r5, c7, c6, 2 + bgt 2b + cmp r2, #0 + bgt 1b + dsb + isb + mov pc, lr +ENDPROC(v7_invalidate_l1) + +ENTRY(shmobile_invalidate_start) + bl v7_invalidate_l1 + b secondary_startup +ENDPROC(shmobile_invalidate_start) + /* * Reset vector for secondary CPUs. * This will be mapped at address 0 by SBAR register. @@ -24,4 +77,5 @@ .align 12 ENTRY(shmobile_secondary_vector) ldr pc, 1f -1: .long secondary_startup - PAGE_OFFSET + PLAT_PHYS_OFFSET +1: .long shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET +ENDPROC(shmobile_secondary_vector) diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index 83ad3fe0a75f..c85e6ecda606 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -4,7 +4,6 @@ extern void shmobile_earlytimer_init(void); extern struct sys_timer shmobile_timer; struct twd_local_timer; -void shmobile_twd_init(struct twd_local_timer *twd_local_timer); extern void shmobile_setup_console(void); extern void shmobile_secondary_vector(void); extern int shmobile_platform_cpu_kill(unsigned int cpu); @@ -82,5 +81,6 @@ extern int r8a7779_platform_cpu_kill(unsigned int cpu); extern void r8a7779_secondary_init(unsigned int cpu); extern int r8a7779_boot_secondary(unsigned int cpu); extern void r8a7779_smp_prepare_cpus(void); +extern void r8a7779_register_twd(void); #endif /* __ARCH_MACH_COMMON_H */ diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c index 12c6f529ab89..e98e46f6cf55 100644 --- a/arch/arm/mach-shmobile/setup-r8a7779.c +++ b/arch/arm/mach-shmobile/setup-r8a7779.c @@ -262,10 +262,14 @@ void __init r8a7779_add_standard_devices(void) ARRAY_SIZE(r8a7779_late_devices)); } +/* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */ +void __init __weak r8a7779_register_twd(void) { } + static void __init r8a7779_earlytimer_init(void) { r8a7779_clock_init(); shmobile_earlytimer_init(); + r8a7779_register_twd(); } void __init r8a7779_add_early_devices(void) diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c index 5bebffc10455..04a0dfe75493 100644 --- a/arch/arm/mach-shmobile/setup-sh73a0.c +++ b/arch/arm/mach-shmobile/setup-sh73a0.c @@ -688,10 +688,14 @@ void __init sh73a0_add_standard_devices(void) ARRAY_SIZE(sh73a0_late_devices)); } +/* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */ +void __init __weak sh73a0_register_twd(void) { } + static void __init sh73a0_earlytimer_init(void) { sh73a0_clock_init(); shmobile_earlytimer_init(); + sh73a0_register_twd(); } void __init sh73a0_add_early_devices(void) diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c index b62e19d4c9af..6d1d0238cbf7 100644 --- a/arch/arm/mach-shmobile/smp-r8a7779.c +++ b/arch/arm/mach-shmobile/smp-r8a7779.c @@ -64,8 +64,15 @@ static void __iomem *scu_base_addr(void) static DEFINE_SPINLOCK(scu_lock); static unsigned long tmp; +#ifdef CONFIG_HAVE_ARM_TWD static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29); +void __init r8a7779_register_twd(void) +{ + twd_local_timer_register(&twd_local_timer); +} +#endif + static void modify_scu_cpu_psr(unsigned long set, unsigned long clr) { void __iomem *scu_base = scu_base_addr(); @@ -84,7 +91,6 @@ unsigned int __init r8a7779_get_core_count(void) { void __iomem *scu_base = scu_base_addr(); - shmobile_twd_init(&twd_local_timer); return scu_get_core_count(scu_base); } diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c index 14ad8b052f1a..e36c41c4ab40 100644 --- a/arch/arm/mach-shmobile/smp-sh73a0.c +++ b/arch/arm/mach-shmobile/smp-sh73a0.c @@ -42,7 +42,13 @@ static void __iomem *scu_base_addr(void) static DEFINE_SPINLOCK(scu_lock); static unsigned long tmp; +#ifdef CONFIG_HAVE_ARM_TWD static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29); +void __init sh73a0_register_twd(void) +{ + twd_local_timer_register(&twd_local_timer); +} +#endif static void modify_scu_cpu_psr(unsigned long set, unsigned long clr) { @@ -62,7 +68,6 @@ unsigned int __init sh73a0_get_core_count(void) { void __iomem *scu_base = scu_base_addr(); - shmobile_twd_init(&twd_local_timer); return scu_get_core_count(scu_base); } diff --git a/arch/arm/mach-shmobile/timer.c b/arch/arm/mach-shmobile/timer.c index 2fba5f3d1c8a..8b79e7917a23 100644 --- a/arch/arm/mach-shmobile/timer.c +++ b/arch/arm/mach-shmobile/timer.c @@ -46,15 +46,6 @@ static void __init shmobile_timer_init(void) { } -void __init shmobile_twd_init(struct twd_local_timer *twd_local_timer) -{ -#ifdef CONFIG_HAVE_ARM_TWD - int err = twd_local_timer_register(twd_local_timer); - if (err) - pr_err("twd_local_timer_register failed %d\n", err); -#endif -} - struct sys_timer shmobile_timer = { .init = shmobile_timer_init, }; diff --git a/arch/arm/mach-tegra/flowctrl.c b/arch/arm/mach-tegra/flowctrl.c index fef66a7486ed..f07488e0bd32 100644 --- a/arch/arm/mach-tegra/flowctrl.c +++ b/arch/arm/mach-tegra/flowctrl.c @@ -53,10 +53,10 @@ static void flowctrl_update(u8 offset, u32 value) void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value) { - return flowctrl_update(flowctrl_offset_halt_cpu[cpuid], value); + return flowctrl_update(flowctrl_offset_cpu_csr[cpuid], value); } void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value) { - return flowctrl_update(flowctrl_offset_cpu_csr[cpuid], value); + return flowctrl_update(flowctrl_offset_halt_cpu[cpuid], value); } diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c index 54a816ff3847..0e09137506ec 100644 --- a/arch/arm/mach-tegra/pcie.c +++ b/arch/arm/mach-tegra/pcie.c @@ -475,7 +475,6 @@ static struct hw_pci tegra_pcie_hw __initdata = { .nr_controllers = 2, .setup = tegra_pcie_setup, .scan = tegra_pcie_scan_bus, - .swizzle = pci_std_swizzle, .map_irq = tegra_pcie_map_irq, }; diff --git a/arch/arm/mach-tegra/timer.c b/arch/arm/mach-tegra/timer.c index 1eed8d4a80ef..315672c7bd48 100644 --- a/arch/arm/mach-tegra/timer.c +++ b/arch/arm/mach-tegra/timer.c @@ -124,7 +124,7 @@ static u64 tegra_rtc_read_ms(void) } /* - * read_persistent_clock - Return time from a persistent clock. + * tegra_read_persistent_clock - Return time from a persistent clock. * * Reads the time from a source which isn't disabled during PM, the * 32k sync timer. Convert the cycles elapsed since last read into @@ -133,7 +133,7 @@ static u64 tegra_rtc_read_ms(void) * tegra_rtc driver could be executing to avoid race conditions * on the RTC shadow register */ -void read_persistent_clock(struct timespec *ts) +static void tegra_read_persistent_clock(struct timespec *ts) { u64 delta; struct timespec *tsp = &persistent_ts; @@ -243,6 +243,7 @@ static void __init tegra_init_timer(void) tegra_clockevent.irq = tegra_timer_irq.irq; clockevents_register_device(&tegra_clockevent); tegra_twd_init(); + register_persistent_clock(NULL, tegra_read_persistent_clock); } struct sys_timer tegra_timer = { diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c index 1621ad07d284..33339745d432 100644 --- a/arch/arm/mach-u300/core.c +++ b/arch/arm/mach-u300/core.c @@ -1667,8 +1667,10 @@ void __init u300_init_irq(void) for (i = 0; i < U300_VIC_IRQS_END; i++) set_bit(i, (unsigned long *) &mask[0]); - vic_init((void __iomem *) U300_INTCON0_VBASE, 0, mask[0], mask[0]); - vic_init((void __iomem *) U300_INTCON1_VBASE, 32, mask[1], mask[1]); + vic_init((void __iomem *) U300_INTCON0_VBASE, IRQ_U300_INTCON0_START, + mask[0], mask[0]); + vic_init((void __iomem *) U300_INTCON1_VBASE, IRQ_U300_INTCON1_START, + mask[1], mask[1]); } diff --git a/arch/arm/mach-u300/i2c.c b/arch/arm/mach-u300/i2c.c index a38f80238ea9..cb04bd6ab3e7 100644 --- a/arch/arm/mach-u300/i2c.c +++ b/arch/arm/mach-u300/i2c.c @@ -146,9 +146,6 @@ static struct ab3100_platform_data ab3100_plf_data = { .min_uV = 1800000, .max_uV = 1800000, .valid_modes_mask = REGULATOR_MODE_NORMAL, - .valid_ops_mask = - REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, .always_on = 1, .boot_on = 1, }, @@ -160,9 +157,6 @@ static struct ab3100_platform_data ab3100_plf_data = { .min_uV = 2500000, .max_uV = 2500000, .valid_modes_mask = REGULATOR_MODE_NORMAL, - .valid_ops_mask = - REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, .always_on = 1, .boot_on = 1, }, @@ -230,8 +224,7 @@ static struct ab3100_platform_data ab3100_plf_data = { .max_uV = 1800000, .valid_modes_mask = REGULATOR_MODE_NORMAL, .valid_ops_mask = - REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, + REGULATOR_CHANGE_VOLTAGE, .always_on = 1, .boot_on = 1, }, diff --git a/arch/arm/mach-u300/include/mach/irqs.h b/arch/arm/mach-u300/include/mach/irqs.h index ee78a26707eb..ec09c1e07b1a 100644 --- a/arch/arm/mach-u300/include/mach/irqs.h +++ b/arch/arm/mach-u300/include/mach/irqs.h @@ -12,101 +12,101 @@ #ifndef __MACH_IRQS_H #define __MACH_IRQS_H -#define IRQ_U300_INTCON0_START 0 -#define IRQ_U300_INTCON1_START 32 +#define IRQ_U300_INTCON0_START 1 +#define IRQ_U300_INTCON1_START 33 /* These are on INTCON0 - 30 lines */ -#define IRQ_U300_IRQ0_EXT 0 -#define IRQ_U300_IRQ1_EXT 1 -#define IRQ_U300_DMA 2 -#define IRQ_U300_VIDEO_ENC_0 3 -#define IRQ_U300_VIDEO_ENC_1 4 -#define IRQ_U300_AAIF_RX 5 -#define IRQ_U300_AAIF_TX 6 -#define IRQ_U300_AAIF_VGPIO 7 -#define IRQ_U300_AAIF_WAKEUP 8 -#define IRQ_U300_PCM_I2S0_FRAME 9 -#define IRQ_U300_PCM_I2S0_FIFO 10 -#define IRQ_U300_PCM_I2S1_FRAME 11 -#define IRQ_U300_PCM_I2S1_FIFO 12 -#define IRQ_U300_XGAM_GAMCON 13 -#define IRQ_U300_XGAM_CDI 14 -#define IRQ_U300_XGAM_CDICON 15 +#define IRQ_U300_IRQ0_EXT 1 +#define IRQ_U300_IRQ1_EXT 2 +#define IRQ_U300_DMA 3 +#define IRQ_U300_VIDEO_ENC_0 4 +#define IRQ_U300_VIDEO_ENC_1 5 +#define IRQ_U300_AAIF_RX 6 +#define IRQ_U300_AAIF_TX 7 +#define IRQ_U300_AAIF_VGPIO 8 +#define IRQ_U300_AAIF_WAKEUP 9 +#define IRQ_U300_PCM_I2S0_FRAME 10 +#define IRQ_U300_PCM_I2S0_FIFO 11 +#define IRQ_U300_PCM_I2S1_FRAME 12 +#define IRQ_U300_PCM_I2S1_FIFO 13 +#define IRQ_U300_XGAM_GAMCON 14 +#define IRQ_U300_XGAM_CDI 15 +#define IRQ_U300_XGAM_CDICON 16 #if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) /* MMIACC not used on the DB3210 or DB3350 chips */ -#define IRQ_U300_XGAM_MMIACC 16 +#define IRQ_U300_XGAM_MMIACC 17 #endif -#define IRQ_U300_XGAM_PDI 17 -#define IRQ_U300_XGAM_PDICON 18 -#define IRQ_U300_XGAM_GAMEACC 19 -#define IRQ_U300_XGAM_MCIDCT 20 -#define IRQ_U300_APEX 21 -#define IRQ_U300_UART0 22 -#define IRQ_U300_SPI 23 -#define IRQ_U300_TIMER_APP_OS 24 -#define IRQ_U300_TIMER_APP_DD 25 -#define IRQ_U300_TIMER_APP_GP1 26 -#define IRQ_U300_TIMER_APP_GP2 27 -#define IRQ_U300_TIMER_OS 28 -#define IRQ_U300_TIMER_MS 29 -#define IRQ_U300_KEYPAD_KEYBF 30 -#define IRQ_U300_KEYPAD_KEYBR 31 +#define IRQ_U300_XGAM_PDI 18 +#define IRQ_U300_XGAM_PDICON 19 +#define IRQ_U300_XGAM_GAMEACC 20 +#define IRQ_U300_XGAM_MCIDCT 21 +#define IRQ_U300_APEX 22 +#define IRQ_U300_UART0 23 +#define IRQ_U300_SPI 24 +#define IRQ_U300_TIMER_APP_OS 25 +#define IRQ_U300_TIMER_APP_DD 26 +#define IRQ_U300_TIMER_APP_GP1 27 +#define IRQ_U300_TIMER_APP_GP2 28 +#define IRQ_U300_TIMER_OS 29 +#define IRQ_U300_TIMER_MS 30 +#define IRQ_U300_KEYPAD_KEYBF 31 +#define IRQ_U300_KEYPAD_KEYBR 32 /* These are on INTCON1 - 32 lines */ -#define IRQ_U300_GPIO_PORT0 32 -#define IRQ_U300_GPIO_PORT1 33 -#define IRQ_U300_GPIO_PORT2 34 +#define IRQ_U300_GPIO_PORT0 33 +#define IRQ_U300_GPIO_PORT1 34 +#define IRQ_U300_GPIO_PORT2 35 #if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) || \ defined(CONFIG_MACH_U300_BS335) /* These are for DB3150, DB3200 and DB3350 */ -#define IRQ_U300_WDOG 35 -#define IRQ_U300_EVHIST 36 -#define IRQ_U300_MSPRO 37 -#define IRQ_U300_MMCSD_MCIINTR0 38 -#define IRQ_U300_MMCSD_MCIINTR1 39 -#define IRQ_U300_I2C0 40 -#define IRQ_U300_I2C1 41 -#define IRQ_U300_RTC 42 -#define IRQ_U300_NFIF 43 -#define IRQ_U300_NFIF2 44 +#define IRQ_U300_WDOG 36 +#define IRQ_U300_EVHIST 37 +#define IRQ_U300_MSPRO 38 +#define IRQ_U300_MMCSD_MCIINTR0 39 +#define IRQ_U300_MMCSD_MCIINTR1 40 +#define IRQ_U300_I2C0 41 +#define IRQ_U300_I2C1 42 +#define IRQ_U300_RTC 43 +#define IRQ_U300_NFIF 44 +#define IRQ_U300_NFIF2 45 #endif /* DB3150 and DB3200 have only 45 IRQs */ #if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) -#define U300_VIC_IRQS_END 45 +#define U300_VIC_IRQS_END 46 #endif /* The DB3350-specific interrupt lines */ #ifdef CONFIG_MACH_U300_BS335 -#define IRQ_U300_ISP_F0 45 -#define IRQ_U300_ISP_F1 46 -#define IRQ_U300_ISP_F2 47 -#define IRQ_U300_ISP_F3 48 -#define IRQ_U300_ISP_F4 49 -#define IRQ_U300_GPIO_PORT3 50 -#define IRQ_U300_SYSCON_PLL_LOCK 51 -#define IRQ_U300_UART1 52 -#define IRQ_U300_GPIO_PORT4 53 -#define IRQ_U300_GPIO_PORT5 54 -#define IRQ_U300_GPIO_PORT6 55 -#define U300_VIC_IRQS_END 56 +#define IRQ_U300_ISP_F0 46 +#define IRQ_U300_ISP_F1 47 +#define IRQ_U300_ISP_F2 48 +#define IRQ_U300_ISP_F3 49 +#define IRQ_U300_ISP_F4 50 +#define IRQ_U300_GPIO_PORT3 51 +#define IRQ_U300_SYSCON_PLL_LOCK 52 +#define IRQ_U300_UART1 53 +#define IRQ_U300_GPIO_PORT4 54 +#define IRQ_U300_GPIO_PORT5 55 +#define IRQ_U300_GPIO_PORT6 56 +#define U300_VIC_IRQS_END 57 #endif /* The DB3210-specific interrupt lines */ #ifdef CONFIG_MACH_U300_BS365 -#define IRQ_U300_GPIO_PORT3 35 -#define IRQ_U300_GPIO_PORT4 36 -#define IRQ_U300_WDOG 37 -#define IRQ_U300_EVHIST 38 -#define IRQ_U300_MSPRO 39 -#define IRQ_U300_MMCSD_MCIINTR0 40 -#define IRQ_U300_MMCSD_MCIINTR1 41 -#define IRQ_U300_I2C0 42 -#define IRQ_U300_I2C1 43 -#define IRQ_U300_RTC 44 -#define IRQ_U300_NFIF 45 -#define IRQ_U300_NFIF2 46 -#define IRQ_U300_SYSCON_PLL_LOCK 47 -#define U300_VIC_IRQS_END 48 +#define IRQ_U300_GPIO_PORT3 36 +#define IRQ_U300_GPIO_PORT4 37 +#define IRQ_U300_WDOG 38 +#define IRQ_U300_EVHIST 39 +#define IRQ_U300_MSPRO 40 +#define IRQ_U300_MMCSD_MCIINTR0 41 +#define IRQ_U300_MMCSD_MCIINTR1 42 +#define IRQ_U300_I2C0 43 +#define IRQ_U300_I2C1 44 +#define IRQ_U300_RTC 45 +#define IRQ_U300_NFIF 46 +#define IRQ_U300_NFIF2 47 +#define IRQ_U300_SYSCON_PLL_LOCK 48 +#define U300_VIC_IRQS_END 49 #endif /* Maximum 8*7 GPIO lines */ @@ -117,6 +117,6 @@ #define IRQ_U300_GPIO_END (U300_VIC_IRQS_END) #endif -#define NR_IRQS (IRQ_U300_GPIO_END) +#define NR_IRQS (IRQ_U300_GPIO_END - IRQ_U300_INTCON0_START) #endif diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig index 880d02ec89d4..ef7099eea0f2 100644 --- a/arch/arm/mach-ux500/Kconfig +++ b/arch/arm/mach-ux500/Kconfig @@ -17,6 +17,7 @@ config UX500_SOC_DB5500 config UX500_SOC_DB8500 bool select MFD_DB8500_PRCMU + select REGULATOR select REGULATOR_DB8500_PRCMU select CPU_FREQ_TABLE if CPU_FREQ diff --git a/arch/arm/mach-ux500/devices-common.c b/arch/arm/mach-ux500/devices-common.c index c5312a4b49f5..dfdd4a54668d 100644 --- a/arch/arm/mach-ux500/devices-common.c +++ b/arch/arm/mach-ux500/devices-common.c @@ -11,7 +11,6 @@ #include <linux/irq.h> #include <linux/slab.h> #include <linux/platform_device.h> -#include <linux/amba/bus.h> #include <plat/gpio-nomadik.h> @@ -19,38 +18,6 @@ #include "devices-common.h" -struct amba_device * -dbx500_add_amba_device(struct device *parent, const char *name, - resource_size_t base, int irq, void *pdata, - unsigned int periphid) -{ - struct amba_device *dev; - int ret; - - dev = amba_device_alloc(name, base, SZ_4K); - if (!dev) - return ERR_PTR(-ENOMEM); - - dev->dma_mask = DMA_BIT_MASK(32); - dev->dev.coherent_dma_mask = DMA_BIT_MASK(32); - - dev->irq[0] = irq; - - dev->periphid = periphid; - - dev->dev.platform_data = pdata; - - dev->dev.parent = parent; - - ret = amba_device_add(dev, &iomem_resource); - if (ret) { - amba_device_put(dev); - return ERR_PTR(ret); - } - - return dev; -} - static struct platform_device * dbx500_add_gpio(struct device *parent, int id, resource_size_t addr, int irq, struct nmk_gpio_platform_data *pdata) diff --git a/arch/arm/mach-ux500/devices-common.h b/arch/arm/mach-ux500/devices-common.h index 39c74ec82add..f75bcb2ab13b 100644 --- a/arch/arm/mach-ux500/devices-common.h +++ b/arch/arm/mach-ux500/devices-common.h @@ -11,13 +11,9 @@ #include <linux/platform_device.h> #include <linux/dma-mapping.h> #include <linux/sys_soc.h> +#include <linux/amba/bus.h> #include <plat/i2c.h> -extern struct amba_device * -dbx500_add_amba_device(struct device *parent, const char *name, - resource_size_t base, int irq, void *pdata, - unsigned int periphid); - struct spi_master_cntlr; static inline struct amba_device * @@ -25,8 +21,8 @@ dbx500_add_msp_spi(struct device *parent, const char *name, resource_size_t base, int irq, struct spi_master_cntlr *pdata) { - return dbx500_add_amba_device(parent, name, base, irq, - pdata, 0); + return amba_ahb_device_add(parent, name, base, SZ_4K, irq, 0, + pdata, 0); } static inline struct amba_device * @@ -34,8 +30,8 @@ dbx500_add_spi(struct device *parent, const char *name, resource_size_t base, int irq, struct spi_master_cntlr *pdata, u32 periphid) { - return dbx500_add_amba_device(parent, name, base, irq, - pdata, periphid); + return amba_ahb_device_add(parent, name, base, SZ_4K, irq, 0, + pdata, periphid); } struct mmci_platform_data; @@ -44,8 +40,8 @@ static inline struct amba_device * dbx500_add_sdi(struct device *parent, const char *name, resource_size_t base, int irq, struct mmci_platform_data *pdata, u32 periphid) { - return dbx500_add_amba_device(parent, name, base, irq, - pdata, periphid); + return amba_ahb_device_add(parent, name, base, SZ_4K, irq, 0, + pdata, periphid); } struct amba_pl011_data; @@ -54,7 +50,7 @@ static inline struct amba_device * dbx500_add_uart(struct device *parent, const char *name, resource_size_t base, int irq, struct amba_pl011_data *pdata) { - return dbx500_add_amba_device(parent, name, base, irq, pdata, 0); + return amba_ahb_device_add(parent, name, base, SZ_4K, irq, 0, pdata, 0); } struct nmk_i2c_controller; @@ -85,7 +81,8 @@ dbx500_add_i2c(struct device *parent, int id, resource_size_t base, int irq, static inline struct amba_device * dbx500_add_rtc(struct device *parent, resource_size_t base, int irq) { - return dbx500_add_amba_device(parent, "rtc-pl031", base, irq, NULL, 0); + return amba_apb_device_add(parent, "rtc-pl031", base, SZ_4K, irq, + 0, NULL, 0); } struct nmk_gpio_platform_data; diff --git a/arch/arm/mach-ux500/devices-db8500.h b/arch/arm/mach-ux500/devices-db8500.h index 9fd93e9da529..6fc7eb24d9a0 100644 --- a/arch/arm/mach-ux500/devices-db8500.h +++ b/arch/arm/mach-ux500/devices-db8500.h @@ -31,7 +31,7 @@ static inline struct amba_device * db8500_add_ssp(struct device *parent, const char *name, resource_size_t base, int irq, struct pl022_ssp_controller *pdata) { - return dbx500_add_amba_device(parent, name, base, irq, pdata, 0); + return amba_ahb_device_add(parent, name, base, SZ_4K, irq, 0, pdata, 0); } diff --git a/arch/arm/mach-ux500/mbox-db5500.c b/arch/arm/mach-ux500/mbox-db5500.c index 2b2d51caf9d8..0127490218cd 100644 --- a/arch/arm/mach-ux500/mbox-db5500.c +++ b/arch/arm/mach-ux500/mbox-db5500.c @@ -168,7 +168,7 @@ static ssize_t mbox_read_fifo(struct device *dev, return sprintf(buf, "0x%X\n", mbox_value); } -static DEVICE_ATTR(fifo, S_IWUGO | S_IRUGO, mbox_read_fifo, mbox_write_fifo); +static DEVICE_ATTR(fifo, S_IWUSR | S_IRUGO, mbox_read_fifo, mbox_write_fifo); static int mbox_show(struct seq_file *s, void *data) { diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c index d2058ef8345f..eff5842f6232 100644 --- a/arch/arm/mach-ux500/platsmp.c +++ b/arch/arm/mach-ux500/platsmp.c @@ -99,7 +99,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) */ write_pen_release(cpu_logical_map(cpu)); - gic_raise_softirq(cpumask_of(cpu), 1); + smp_send_reschedule(cpu); timeout = jiffies + (1 * HZ); while (time_before(jiffies, timeout)) { diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c index 6bbd74e950ab..cf4687ee2a7b 100644 --- a/arch/arm/mach-versatile/core.c +++ b/arch/arm/mach-versatile/core.c @@ -66,12 +66,6 @@ #define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE) #define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE) -static struct fpga_irq_data sic_irq = { - .base = VA_SIC_BASE, - .irq_start = IRQ_SIC_START, - .chip.name = "SIC", -}; - #if 1 #define IRQ_MMCI0A IRQ_VICSOURCE22 #define IRQ_AACI IRQ_VICSOURCE24 @@ -105,8 +99,11 @@ void __init versatile_init_irq(void) writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR); - fpga_irq_init(IRQ_VICSOURCE31, ~PIC_MASK, &sic_irq); - irq_domain_generate_simple(sic_of_match, VERSATILE_SIC_BASE, IRQ_SIC_START); + np = of_find_matching_node_by_address(NULL, sic_of_match, + VERSATILE_SIC_BASE); + + fpga_irq_init(VA_SIC_BASE, "SIC", IRQ_SIC_START, + IRQ_VICSOURCE31, ~PIC_MASK, np); /* * Interrupts on secondary controller from 0 to 8 are routed to @@ -666,17 +663,18 @@ static struct amba_device *amba_devs[] __initdata = { * having a specific name. */ struct of_dev_auxdata versatile_auxdata_lookup[] __initdata = { - OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI0_BASE, "fpga:05", NULL), + OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI0_BASE, "fpga:05", &mmc0_plat_data), OF_DEV_AUXDATA("arm,primecell", VERSATILE_KMI0_BASE, "fpga:06", NULL), OF_DEV_AUXDATA("arm,primecell", VERSATILE_KMI1_BASE, "fpga:07", NULL), OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART3_BASE, "fpga:09", NULL), + /* FIXME: this is buggy, the platform data is needed for this MMC instance too */ OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI1_BASE, "fpga:0b", NULL), OF_DEV_AUXDATA("arm,primecell", VERSATILE_CLCD_BASE, "dev:20", &clcd_plat_data), OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART0_BASE, "dev:f1", NULL), OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART1_BASE, "dev:f2", NULL), OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART2_BASE, "dev:f3", NULL), - OF_DEV_AUXDATA("arm,primecell", VERSATILE_SSP_BASE, "dev:f4", NULL), + OF_DEV_AUXDATA("arm,primecell", VERSATILE_SSP_BASE, "dev:f4", &ssp0_plat_data), #if 0 /* diff --git a/arch/arm/mach-versatile/pci.c b/arch/arm/mach-versatile/pci.c index d2268be8c34c..15c6a00000ec 100644 --- a/arch/arm/mach-versatile/pci.c +++ b/arch/arm/mach-versatile/pci.c @@ -303,12 +303,6 @@ int __init pci_versatile_setup(int nr, struct pci_sys_data *sys) } -struct pci_bus * __init pci_versatile_scan_bus(int nr, struct pci_sys_data *sys) -{ - return pci_scan_root_bus(NULL, sys->busnr, &pci_versatile_ops, sys, - &sys->resources); -} - void __init pci_versatile_preinit(void) { pcibios_min_io = 0x44000000; @@ -339,19 +333,16 @@ static int __init versatile_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) * 26 1 29 * 27 1 30 */ - irq = 27 + ((slot + pin - 1) & 3); - - printk("PCI map irq: slot %d, pin %d, devslot %d, irq: %d\n",slot,pin,devslot,irq); + irq = 27 + ((slot - 24 + pin - 1) & 3); return irq; } static struct hw_pci versatile_pci __initdata = { - .swizzle = NULL, .map_irq = versatile_map_irq, .nr_controllers = 1, + .ops = &pci_versatile_ops, .setup = pci_versatile_setup, - .scan = pci_versatile_scan_bus, .preinit = pci_versatile_preinit, }; diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c index 47cdcca5a7e7..04dd092211b8 100644 --- a/arch/arm/mach-vexpress/v2m.c +++ b/arch/arm/mach-vexpress/v2m.c @@ -19,8 +19,10 @@ #include <linux/clkdev.h> #include <linux/mtd/physmap.h> +#include <asm/arch_timer.h> #include <asm/mach-types.h> #include <asm/sizes.h> +#include <asm/smp_twd.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/mach/time.h> @@ -616,7 +618,6 @@ void __init v2m_dt_init_early(void) } clkdev_add_table(v2m_dt_lookups, ARRAY_SIZE(v2m_dt_lookups)); - versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000); } static struct of_device_id vexpress_irq_match[] __initdata = { @@ -643,6 +644,11 @@ static void __init v2m_dt_timer_init(void) return; node = of_find_node_by_path(path); v2m_sp804_init(of_iomap(node, 0), irq_of_parse_and_map(node, 0)); + if (arch_timer_of_register() != 0) + twd_local_timer_of_register(); + + if (arch_timer_sched_clock_init() != 0) + versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000); } static struct sys_timer v2m_dt_timer = { diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 7edef9121632..101b9681c08c 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -4,23 +4,6 @@ comment "Processor Type" # which CPUs we support in the kernel image, and the compiler instruction # optimiser behaviour. -# ARM610 -config CPU_ARM610 - bool "Support ARM610 processor" if ARCH_RPC - select CPU_32v3 - select CPU_CACHE_V3 - select CPU_CACHE_VIVT - select CPU_CP15_MMU - select CPU_COPY_V3 if MMU - select CPU_TLB_V3 if MMU - select CPU_PABRT_LEGACY - help - The ARM610 is the successor to the ARM3 processor - and was produced by VLSI Technology Inc. - - Say Y if you want support for the ARM610 processor. - Otherwise, say N. - # ARM7TDMI config CPU_ARM7TDMI bool "Support ARM7TDMI processor" @@ -36,25 +19,6 @@ config CPU_ARM7TDMI Say Y if you want support for the ARM7TDMI processor. Otherwise, say N. -# ARM710 -config CPU_ARM710 - bool "Support ARM710 processor" if ARCH_RPC - select CPU_32v3 - select CPU_CACHE_V3 - select CPU_CACHE_VIVT - select CPU_CP15_MMU - select CPU_COPY_V3 if MMU - select CPU_TLB_V3 if MMU - select CPU_PABRT_LEGACY - help - A 32-bit RISC microprocessor based on the ARM7 processor core - designed by Advanced RISC Machines Ltd. The ARM710 is the - successor to the ARM610 processor. It was released in - July 1994 by VLSI Technology Inc. - - Say Y if you want support for the ARM710 processor. - Otherwise, say N. - # ARM720T config CPU_ARM720T bool "Support ARM720T processor" if ARCH_INTEGRATOR @@ -530,9 +494,6 @@ config CPU_CACHE_FA if MMU # The copy-page model -config CPU_COPY_V3 - bool - config CPU_COPY_V4WT bool @@ -549,11 +510,6 @@ config CPU_COPY_V6 bool # This selects the TLB model -config CPU_TLB_V3 - bool - help - ARM Architecture Version 3 TLB. - config CPU_TLB_V4WT bool help @@ -723,7 +679,7 @@ config CPU_HIGH_VECTOR bool "Select the High exception vector" help Say Y here to select high exception vector(0xFFFF0000~). - The exception vector can be vary depending on the platform + The exception vector can vary depending on the platform design in nommu mode. If your platform needs to select high exception vector, say Y. Otherwise or if you are unsure, say N, and the low exception @@ -731,7 +687,7 @@ config CPU_HIGH_VECTOR config CPU_ICACHE_DISABLE bool "Disable I-Cache (I-bit)" - depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3) + depends on CPU_CP15 && !(CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3) help Say Y here to disable the processor instruction cache. Unless you have a reason not to or are unsure, say N. diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile index bca7e61928c7..8a9c4cb50a93 100644 --- a/arch/arm/mm/Makefile +++ b/arch/arm/mm/Makefile @@ -44,7 +44,6 @@ obj-$(CONFIG_CPU_CACHE_FA) += cache-fa.o AFLAGS_cache-v6.o :=-Wa,-march=armv6 AFLAGS_cache-v7.o :=-Wa,-march=armv7-a -obj-$(CONFIG_CPU_COPY_V3) += copypage-v3.o obj-$(CONFIG_CPU_COPY_V4WT) += copypage-v4wt.o obj-$(CONFIG_CPU_COPY_V4WB) += copypage-v4wb.o obj-$(CONFIG_CPU_COPY_FEROCEON) += copypage-feroceon.o @@ -54,7 +53,6 @@ obj-$(CONFIG_CPU_XSCALE) += copypage-xscale.o obj-$(CONFIG_CPU_XSC3) += copypage-xsc3.o obj-$(CONFIG_CPU_COPY_FA) += copypage-fa.o -obj-$(CONFIG_CPU_TLB_V3) += tlb-v3.o obj-$(CONFIG_CPU_TLB_V4WT) += tlb-v4.o obj-$(CONFIG_CPU_TLB_V4WB) += tlb-v4wb.o obj-$(CONFIG_CPU_TLB_V4WBI) += tlb-v4wbi.o @@ -66,8 +64,6 @@ obj-$(CONFIG_CPU_TLB_FA) += tlb-fa.o AFLAGS_tlb-v6.o :=-Wa,-march=armv6 AFLAGS_tlb-v7.o :=-Wa,-march=armv7-a -obj-$(CONFIG_CPU_ARM610) += proc-arm6_7.o -obj-$(CONFIG_CPU_ARM710) += proc-arm6_7.o obj-$(CONFIG_CPU_ARM7TDMI) += proc-arm7tdmi.o obj-$(CONFIG_CPU_ARM720T) += proc-arm720.o obj-$(CONFIG_CPU_ARM740T) += proc-arm740.o diff --git a/arch/arm/mm/abort-ev6.S b/arch/arm/mm/abort-ev6.S index ff1f7cc11f87..80741992a9fc 100644 --- a/arch/arm/mm/abort-ev6.S +++ b/arch/arm/mm/abort-ev6.S @@ -26,18 +26,23 @@ ENTRY(v6_early_abort) mrc p15, 0, r1, c5, c0, 0 @ get FSR mrc p15, 0, r0, c6, c0, 0 @ get FAR /* - * Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR (erratum 326103). - * The test below covers all the write situations, including Java bytecodes + * Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR. */ - bic r1, r1, #1 << 11 @ clear bit 11 of FSR +#ifdef CONFIG_ARM_ERRATA_326103 + ldr ip, =0x4107b36 + mrc p15, 0, r3, c0, c0, 0 @ get processor id + teq ip, r3, lsr #4 @ r0 ARM1136? + bne do_DataAbort tst r5, #PSR_J_BIT @ Java? + tsteq r5, #PSR_T_BIT @ Thumb? bne do_DataAbort - do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3 - ldreq r3, [r4] @ read aborted ARM instruction + bic r1, r1, #1 << 11 @ clear bit 11 of FSR + ldr r3, [r4] @ read aborted ARM instruction #ifdef CONFIG_CPU_ENDIAN_BE8 - reveq r3, r3 + rev r3, r3 #endif do_ldrd_abort tmp=ip, insn=r3 tst r3, #1 << 20 @ L = 0 -> write orreq r1, r1, #1 << 11 @ yes. +#endif b do_DataAbort diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index a53fd2aaa2f4..2a8e380501e8 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -32,6 +32,7 @@ static void __iomem *l2x0_base; static DEFINE_RAW_SPINLOCK(l2x0_lock); static u32 l2x0_way_mask; /* Bitmask of active ways */ static u32 l2x0_size; +static unsigned long sync_reg_offset = L2X0_CACHE_SYNC; struct l2x0_regs l2x0_saved_regs; @@ -61,12 +62,7 @@ static inline void cache_sync(void) { void __iomem *base = l2x0_base; -#ifdef CONFIG_PL310_ERRATA_753970 - /* write to an unmmapped register */ - writel_relaxed(0, base + L2X0_DUMMY_REG); -#else - writel_relaxed(0, base + L2X0_CACHE_SYNC); -#endif + writel_relaxed(0, base + sync_reg_offset); cache_wait(base + L2X0_CACHE_SYNC, 1); } @@ -85,10 +81,13 @@ static inline void l2x0_inv_line(unsigned long addr) } #if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915) +static inline void debug_writel(unsigned long val) +{ + if (outer_cache.set_debug) + outer_cache.set_debug(val); +} -#define debug_writel(val) outer_cache.set_debug(val) - -static void l2x0_set_debug(unsigned long val) +static void pl310_set_debug(unsigned long val) { writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL); } @@ -98,7 +97,7 @@ static inline void debug_writel(unsigned long val) { } -#define l2x0_set_debug NULL +#define pl310_set_debug NULL #endif #ifdef CONFIG_PL310_ERRATA_588369 @@ -331,6 +330,11 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask) else ways = 8; type = "L310"; +#ifdef CONFIG_PL310_ERRATA_753970 + /* Unmapped register. */ + sync_reg_offset = L2X0_DUMMY_REG; +#endif + outer_cache.set_debug = pl310_set_debug; break; case L2X0_CACHE_ID_PART_L210: ways = (aux >> 13) & 0xf; @@ -379,7 +383,6 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask) outer_cache.flush_all = l2x0_flush_all; outer_cache.inv_all = l2x0_inv_all; outer_cache.disable = l2x0_disable; - outer_cache.set_debug = l2x0_set_debug; printk(KERN_INFO "%s cache controller enabled\n", type); printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n", diff --git a/arch/arm/mm/cache-v3.S b/arch/arm/mm/cache-v3.S index c2301f226100..52e35f32eefb 100644 --- a/arch/arm/mm/cache-v3.S +++ b/arch/arm/mm/cache-v3.S @@ -78,6 +78,7 @@ ENTRY(v3_coherent_kern_range) * - end - virtual end address */ ENTRY(v3_coherent_user_range) + mov r0, #0 mov pc, lr /* diff --git a/arch/arm/mm/cache-v4.S b/arch/arm/mm/cache-v4.S index fd9bb7addc8d..022135d2b7e4 100644 --- a/arch/arm/mm/cache-v4.S +++ b/arch/arm/mm/cache-v4.S @@ -88,6 +88,7 @@ ENTRY(v4_coherent_kern_range) * - end - virtual end address */ ENTRY(v4_coherent_user_range) + mov r0, #0 mov pc, lr /* diff --git a/arch/arm/mm/cache-v4wb.S b/arch/arm/mm/cache-v4wb.S index 4f2c14151ccb..8f1eeae340c8 100644 --- a/arch/arm/mm/cache-v4wb.S +++ b/arch/arm/mm/cache-v4wb.S @@ -167,9 +167,9 @@ ENTRY(v4wb_coherent_user_range) add r0, r0, #CACHE_DLINESIZE cmp r0, r1 blo 1b - mov ip, #0 - mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache - mcr p15, 0, ip, c7, c10, 4 @ drain WB + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache + mcr p15, 0, r0, c7, c10, 4 @ drain WB mov pc, lr diff --git a/arch/arm/mm/cache-v4wt.S b/arch/arm/mm/cache-v4wt.S index 4d7b467631ce..b34a5f908a82 100644 --- a/arch/arm/mm/cache-v4wt.S +++ b/arch/arm/mm/cache-v4wt.S @@ -125,6 +125,7 @@ ENTRY(v4wt_coherent_user_range) add r0, r0, #CACHE_DLINESIZE cmp r0, r1 blo 1b + mov r0, #0 mov pc, lr /* diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S index 74c2e5a33a4d..4b10760c56d6 100644 --- a/arch/arm/mm/cache-v6.S +++ b/arch/arm/mm/cache-v6.S @@ -12,6 +12,7 @@ #include <linux/linkage.h> #include <linux/init.h> #include <asm/assembler.h> +#include <asm/errno.h> #include <asm/unwind.h> #include "proc-macros.S" @@ -135,7 +136,6 @@ ENTRY(v6_coherent_user_range) 1: USER( mcr p15, 0, r0, c7, c10, 1 ) @ clean D line add r0, r0, #CACHE_LINE_SIZE -2: cmp r0, r1 blo 1b #endif @@ -154,13 +154,11 @@ ENTRY(v6_coherent_user_range) /* * Fault handling for the cache operation above. If the virtual address in r0 - * isn't mapped, just try the next page. + * isn't mapped, fail with -EFAULT. */ 9001: - mov r0, r0, lsr #12 - mov r0, r0, lsl #12 - add r0, r0, #4096 - b 2b + mov r0, #-EFAULT + mov pc, lr UNWIND(.fnend ) ENDPROC(v6_coherent_user_range) ENDPROC(v6_coherent_kern_range) diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index a655d3da386d..39e3fb3db801 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -13,6 +13,7 @@ #include <linux/linkage.h> #include <linux/init.h> #include <asm/assembler.h> +#include <asm/errno.h> #include <asm/unwind.h> #include "proc-macros.S" @@ -198,7 +199,6 @@ ENTRY(v7_coherent_user_range) add r12, r12, r2 cmp r12, r1 blo 2b -3: mov r0, #0 ALT_SMP(mcr p15, 0, r0, c7, c1, 6) @ invalidate BTB Inner Shareable ALT_UP(mcr p15, 0, r0, c7, c5, 6) @ invalidate BTB @@ -208,13 +208,11 @@ ENTRY(v7_coherent_user_range) /* * Fault handling for the cache operation above. If the virtual address in r0 - * isn't mapped, just try the next page. + * isn't mapped, fail with -EFAULT. */ 9001: - mov r12, r12, lsr #12 - mov r12, r12, lsl #12 - add r12, r12, #4096 - b 3b + mov r0, #-EFAULT + mov pc, lr UNWIND(.fnend ) ENDPROC(v7_coherent_kern_range) ENDPROC(v7_coherent_user_range) diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c index ee9bb363d606..806cc4f63516 100644 --- a/arch/arm/mm/context.c +++ b/arch/arm/mm/context.c @@ -18,30 +18,39 @@ static DEFINE_RAW_SPINLOCK(cpu_asid_lock); unsigned int cpu_last_asid = ASID_FIRST_VERSION; -#ifdef CONFIG_SMP -DEFINE_PER_CPU(struct mm_struct *, current_mm); -#endif #ifdef CONFIG_ARM_LPAE -#define cpu_set_asid(asid) { \ - unsigned long ttbl, ttbh; \ - asm volatile( \ - " mrrc p15, 0, %0, %1, c2 @ read TTBR0\n" \ - " mov %1, %2, lsl #(48 - 32) @ set ASID\n" \ - " mcrr p15, 0, %0, %1, c2 @ set TTBR0\n" \ - : "=&r" (ttbl), "=&r" (ttbh) \ - : "r" (asid & ~ASID_MASK)); \ +void cpu_set_reserved_ttbr0(void) +{ + unsigned long ttbl = __pa(swapper_pg_dir); + unsigned long ttbh = 0; + + /* + * Set TTBR0 to swapper_pg_dir which contains only global entries. The + * ASID is set to 0. + */ + asm volatile( + " mcrr p15, 0, %0, %1, c2 @ set TTBR0\n" + : + : "r" (ttbl), "r" (ttbh)); + isb(); } #else -#define cpu_set_asid(asid) \ - asm(" mcr p15, 0, %0, c13, c0, 1\n" : : "r" (asid)) +void cpu_set_reserved_ttbr0(void) +{ + u32 ttb; + /* Copy TTBR1 into TTBR0 */ + asm volatile( + " mrc p15, 0, %0, c2, c0, 1 @ read TTBR1\n" + " mcr p15, 0, %0, c2, c0, 0 @ set TTBR0\n" + : "=r" (ttb)); + isb(); +} #endif /* * We fork()ed a process, and we need a new context for the child - * to run in. We reserve version 0 for initial tasks so we will - * always allocate an ASID. The ASID 0 is reserved for the TTBR - * register changing sequence. + * to run in. */ void __init_new_context(struct task_struct *tsk, struct mm_struct *mm) { @@ -51,9 +60,7 @@ void __init_new_context(struct task_struct *tsk, struct mm_struct *mm) static void flush_context(void) { - /* set the reserved ASID before flushing the TLB */ - cpu_set_asid(0); - isb(); + cpu_set_reserved_ttbr0(); local_flush_tlb_all(); if (icache_is_vivt_asid_tagged()) { __flush_icache_all(); @@ -98,14 +105,7 @@ static void reset_context(void *info) { unsigned int asid; unsigned int cpu = smp_processor_id(); - struct mm_struct *mm = per_cpu(current_mm, cpu); - - /* - * Check if a current_mm was set on this CPU as it might still - * be in the early booting stages and using the reserved ASID. - */ - if (!mm) - return; + struct mm_struct *mm = current->active_mm; smp_rmb(); asid = cpu_last_asid + cpu + 1; @@ -114,8 +114,7 @@ static void reset_context(void *info) set_mm_context(mm, asid); /* set the new ASID */ - cpu_set_asid(mm->context.id); - isb(); + cpu_switch_mm(mm->pgd, mm); } #else diff --git a/arch/arm/mm/copypage-v3.c b/arch/arm/mm/copypage-v3.c deleted file mode 100644 index 3935bddd4769..000000000000 --- a/arch/arm/mm/copypage-v3.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * linux/arch/arm/mm/copypage-v3.c - * - * Copyright (C) 1995-1999 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <linux/init.h> -#include <linux/highmem.h> - -/* - * ARMv3 optimised copy_user_highpage - * - * FIXME: do we need to handle cache stuff... - */ -static void __naked -v3_copy_user_page(void *kto, const void *kfrom) -{ - asm("\n\ - stmfd sp!, {r4, lr} @ 2\n\ - mov r2, %2 @ 1\n\ - ldmia %0!, {r3, r4, ip, lr} @ 4+1\n\ -1: stmia %1!, {r3, r4, ip, lr} @ 4\n\ - ldmia %0!, {r3, r4, ip, lr} @ 4+1\n\ - stmia %1!, {r3, r4, ip, lr} @ 4\n\ - ldmia %0!, {r3, r4, ip, lr} @ 4+1\n\ - stmia %1!, {r3, r4, ip, lr} @ 4\n\ - ldmia %0!, {r3, r4, ip, lr} @ 4\n\ - subs r2, r2, #1 @ 1\n\ - stmia %1!, {r3, r4, ip, lr} @ 4\n\ - ldmneia %0!, {r3, r4, ip, lr} @ 4\n\ - bne 1b @ 1\n\ - ldmfd sp!, {r4, pc} @ 3" - : - : "r" (kfrom), "r" (kto), "I" (PAGE_SIZE / 64)); -} - -void v3_copy_user_highpage(struct page *to, struct page *from, - unsigned long vaddr, struct vm_area_struct *vma) -{ - void *kto, *kfrom; - - kto = kmap_atomic(to); - kfrom = kmap_atomic(from); - v3_copy_user_page(kto, kfrom); - kunmap_atomic(kfrom); - kunmap_atomic(kto); -} - -/* - * ARMv3 optimised clear_user_page - * - * FIXME: do we need to handle cache stuff... - */ -void v3_clear_user_highpage(struct page *page, unsigned long vaddr) -{ - void *ptr, *kaddr = kmap_atomic(page); - asm volatile("\n\ - mov r1, %2 @ 1\n\ - mov r2, #0 @ 1\n\ - mov r3, #0 @ 1\n\ - mov ip, #0 @ 1\n\ - mov lr, #0 @ 1\n\ -1: stmia %0!, {r2, r3, ip, lr} @ 4\n\ - stmia %0!, {r2, r3, ip, lr} @ 4\n\ - stmia %0!, {r2, r3, ip, lr} @ 4\n\ - stmia %0!, {r2, r3, ip, lr} @ 4\n\ - subs r1, r1, #1 @ 1\n\ - bne 1b @ 1" - : "=r" (ptr) - : "0" (kaddr), "I" (PAGE_SIZE / 64) - : "r1", "r2", "r3", "ip", "lr"); - kunmap_atomic(kaddr); -} - -struct cpu_user_fns v3_user_fns __initdata = { - .cpu_clear_user_highpage = v3_clear_user_highpage, - .cpu_copy_user_highpage = v3_copy_user_highpage, -}; diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c index 9055b5a84ec5..c3bd83450227 100644 --- a/arch/arm/mm/fault.c +++ b/arch/arm/mm/fault.c @@ -247,7 +247,9 @@ good_area: return handle_mm_fault(mm, vma, addr & PAGE_MASK, flags); check_stack: - if (vma->vm_flags & VM_GROWSDOWN && !expand_stack(vma, addr)) + /* Don't allow expansion below FIRST_USER_ADDRESS */ + if (vma->vm_flags & VM_GROWSDOWN && + addr >= FIRST_USER_ADDRESS && !expand_stack(vma, addr)) goto good_area; out: return fault; @@ -320,7 +322,7 @@ retry: */ perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, addr); - if (flags & FAULT_FLAG_ALLOW_RETRY) { + if (!(fault & VM_FAULT_ERROR) && flags & FAULT_FLAG_ALLOW_RETRY) { if (fault & VM_FAULT_MAJOR) { tsk->maj_flt++; perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, @@ -430,9 +432,6 @@ do_translation_fault(unsigned long addr, unsigned int fsr, index = pgd_index(addr); - /* - * FIXME: CP15 C1 is write only on ARMv3 architectures. - */ pgd = cpu_get_pgd() + index; pgd_k = init_mm.pgd + index; diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c index 595079fa9d1d..8f5813bbffb5 100644 --- a/arch/arm/mm/init.c +++ b/arch/arm/mm/init.c @@ -293,11 +293,11 @@ EXPORT_SYMBOL(pfn_valid); #endif #ifndef CONFIG_SPARSEMEM -static void arm_memory_present(void) +static void __init arm_memory_present(void) { } #else -static void arm_memory_present(void) +static void __init arm_memory_present(void) { struct memblock_region *reg; diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index b86f8933ff91..aa78de8bfdd3 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -489,7 +489,8 @@ static void __init build_mem_type_table(void) */ for (i = 0; i < ARRAY_SIZE(mem_types); i++) { mem_types[i].prot_pte |= PTE_EXT_AF; - mem_types[i].prot_sect |= PMD_SECT_AF; + if (mem_types[i].prot_sect) + mem_types[i].prot_sect |= PMD_SECT_AF; } kern_pgprot |= PTE_EXT_AF; vecs_pgprot |= PTE_EXT_AF; @@ -618,8 +619,8 @@ static void __init alloc_init_section(pud_t *pud, unsigned long addr, } } -static void alloc_init_pud(pgd_t *pgd, unsigned long addr, unsigned long end, - unsigned long phys, const struct mem_type *type) +static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr, + unsigned long end, unsigned long phys, const struct mem_type *type) { pud_t *pud = pud_offset(pgd, addr); unsigned long next; diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c index 6486d2f253cd..d51225f90ae2 100644 --- a/arch/arm/mm/nommu.c +++ b/arch/arm/mm/nommu.c @@ -13,6 +13,7 @@ #include <asm/sections.h> #include <asm/page.h> #include <asm/setup.h> +#include <asm/traps.h> #include <asm/mach/arch.h> #include "mm.h" @@ -39,6 +40,7 @@ void __init sanity_check_meminfo(void) */ void __init paging_init(struct machine_desc *mdesc) { + early_trap_init((void *)CONFIG_VECTORS_BASE); bootmem_init(); } diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S index 234951345eb3..0650bb87c1e3 100644 --- a/arch/arm/mm/proc-arm1020.S +++ b/arch/arm/mm/proc-arm1020.S @@ -241,6 +241,7 @@ ENTRY(arm1020_coherent_user_range) cmp r0, r1 blo 1b mcr p15, 0, ip, c7, c10, 4 @ drain WB + mov r0, #0 mov pc, lr /* diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S index c244b06caac9..4188478325a6 100644 --- a/arch/arm/mm/proc-arm1020e.S +++ b/arch/arm/mm/proc-arm1020e.S @@ -235,6 +235,7 @@ ENTRY(arm1020e_coherent_user_range) cmp r0, r1 blo 1b mcr p15, 0, ip, c7, c10, 4 @ drain WB + mov r0, #0 mov pc, lr /* diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S index 38fe22efd18f..33c68824bff0 100644 --- a/arch/arm/mm/proc-arm1022.S +++ b/arch/arm/mm/proc-arm1022.S @@ -224,6 +224,7 @@ ENTRY(arm1022_coherent_user_range) cmp r0, r1 blo 1b mcr p15, 0, ip, c7, c10, 4 @ drain WB + mov r0, #0 mov pc, lr /* diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S index 3eb9c3c26c75..fbc1d5fc24dc 100644 --- a/arch/arm/mm/proc-arm1026.S +++ b/arch/arm/mm/proc-arm1026.S @@ -218,6 +218,7 @@ ENTRY(arm1026_coherent_user_range) cmp r0, r1 blo 1b mcr p15, 0, ip, c7, c10, 4 @ drain WB + mov r0, #0 mov pc, lr /* diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S deleted file mode 100644 index 4fbeb5b8e6c2..000000000000 --- a/arch/arm/mm/proc-arm6_7.S +++ /dev/null @@ -1,327 +0,0 @@ -/* - * linux/arch/arm/mm/proc-arm6,7.S - * - * Copyright (C) 1997-2000 Russell King - * hacked for non-paged-MM by Hyok S. Choi, 2003. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * These are the low level assembler for performing cache and TLB - * functions on the ARM610 & ARM710. - */ -#include <linux/linkage.h> -#include <linux/init.h> -#include <asm/assembler.h> -#include <asm/asm-offsets.h> -#include <asm/hwcap.h> -#include <asm/pgtable-hwdef.h> -#include <asm/pgtable.h> -#include <asm/ptrace.h> - -#include "proc-macros.S" - -ENTRY(cpu_arm6_dcache_clean_area) -ENTRY(cpu_arm7_dcache_clean_area) - mov pc, lr - -/* - * Function: arm6_7_data_abort () - * - * Params : r2 = pt_regs - * : r4 = aborted context pc - * : r5 = aborted context psr - * - * Purpose : obtain information about current aborted instruction - * - * Returns : r4-r5, r10-r11, r13 preserved - */ - -ENTRY(cpu_arm7_data_abort) - mrc p15, 0, r1, c5, c0, 0 @ get FSR - mrc p15, 0, r0, c6, c0, 0 @ get FAR - ldr r8, [r4] @ read arm instruction - tst r8, #1 << 20 @ L = 0 -> write? - orreq r1, r1, #1 << 11 @ yes. - and r7, r8, #15 << 24 - add pc, pc, r7, lsr #22 @ Now branch to the relevant processing routine - nop - -/* 0 */ b .data_unknown -/* 1 */ b do_DataAbort @ swp -/* 2 */ b .data_unknown -/* 3 */ b .data_unknown -/* 4 */ b .data_arm_lateldrpostconst @ ldr rd, [rn], #m -/* 5 */ b .data_arm_lateldrpreconst @ ldr rd, [rn, #m] -/* 6 */ b .data_arm_lateldrpostreg @ ldr rd, [rn], rm -/* 7 */ b .data_arm_lateldrprereg @ ldr rd, [rn, rm] -/* 8 */ b .data_arm_ldmstm @ ldm*a rn, <rlist> -/* 9 */ b .data_arm_ldmstm @ ldm*b rn, <rlist> -/* a */ b .data_unknown -/* b */ b .data_unknown -/* c */ b do_DataAbort @ ldc rd, [rn], #m @ Same as ldr rd, [rn], #m -/* d */ b do_DataAbort @ ldc rd, [rn, #m] -/* e */ b .data_unknown -/* f */ -.data_unknown: @ Part of jumptable - mov r0, r4 - mov r1, r8 - b baddataabort - -ENTRY(cpu_arm6_data_abort) - mrc p15, 0, r1, c5, c0, 0 @ get FSR - mrc p15, 0, r0, c6, c0, 0 @ get FAR - ldr r8, [r4] @ read arm instruction - tst r8, #1 << 20 @ L = 0 -> write? - orreq r1, r1, #1 << 11 @ yes. - and r7, r8, #14 << 24 - teq r7, #8 << 24 @ was it ldm/stm - bne do_DataAbort - -.data_arm_ldmstm: - tst r8, #1 << 21 @ check writeback bit - beq do_DataAbort @ no writeback -> no fixup - mov r7, #0x11 - orr r7, r7, #0x1100 - and r6, r8, r7 - and r9, r8, r7, lsl #1 - add r6, r6, r9, lsr #1 - and r9, r8, r7, lsl #2 - add r6, r6, r9, lsr #2 - and r9, r8, r7, lsl #3 - add r6, r6, r9, lsr #3 - add r6, r6, r6, lsr #8 - add r6, r6, r6, lsr #4 - and r6, r6, #15 @ r6 = no. of registers to transfer. - and r9, r8, #15 << 16 @ Extract 'n' from instruction - ldr r7, [r2, r9, lsr #14] @ Get register 'Rn' - tst r8, #1 << 23 @ Check U bit - subne r7, r7, r6, lsl #2 @ Undo increment - addeq r7, r7, r6, lsl #2 @ Undo decrement - str r7, [r2, r9, lsr #14] @ Put register 'Rn' - b do_DataAbort - -.data_arm_apply_r6_and_rn: - and r9, r8, #15 << 16 @ Extract 'n' from instruction - ldr r7, [r2, r9, lsr #14] @ Get register 'Rn' - tst r8, #1 << 23 @ Check U bit - subne r7, r7, r6 @ Undo incrmenet - addeq r7, r7, r6 @ Undo decrement - str r7, [r2, r9, lsr #14] @ Put register 'Rn' - b do_DataAbort - -.data_arm_lateldrpreconst: - tst r8, #1 << 21 @ check writeback bit - beq do_DataAbort @ no writeback -> no fixup -.data_arm_lateldrpostconst: - movs r6, r8, lsl #20 @ Get offset - beq do_DataAbort @ zero -> no fixup - and r9, r8, #15 << 16 @ Extract 'n' from instruction - ldr r7, [r2, r9, lsr #14] @ Get register 'Rn' - tst r8, #1 << 23 @ Check U bit - subne r7, r7, r6, lsr #20 @ Undo increment - addeq r7, r7, r6, lsr #20 @ Undo decrement - str r7, [r2, r9, lsr #14] @ Put register 'Rn' - b do_DataAbort - -.data_arm_lateldrprereg: - tst r8, #1 << 21 @ check writeback bit - beq do_DataAbort @ no writeback -> no fixup -.data_arm_lateldrpostreg: - and r7, r8, #15 @ Extract 'm' from instruction - ldr r6, [r2, r7, lsl #2] @ Get register 'Rm' - mov r9, r8, lsr #7 @ get shift count - ands r9, r9, #31 - and r7, r8, #0x70 @ get shift type - orreq r7, r7, #8 @ shift count = 0 - add pc, pc, r7 - nop - - mov r6, r6, lsl r9 @ 0: LSL #!0 - b .data_arm_apply_r6_and_rn - b .data_arm_apply_r6_and_rn @ 1: LSL #0 - nop - b .data_unknown @ 2: MUL? - nop - b .data_unknown @ 3: MUL? - nop - mov r6, r6, lsr r9 @ 4: LSR #!0 - b .data_arm_apply_r6_and_rn - mov r6, r6, lsr #32 @ 5: LSR #32 - b .data_arm_apply_r6_and_rn - b .data_unknown @ 6: MUL? - nop - b .data_unknown @ 7: MUL? - nop - mov r6, r6, asr r9 @ 8: ASR #!0 - b .data_arm_apply_r6_and_rn - mov r6, r6, asr #32 @ 9: ASR #32 - b .data_arm_apply_r6_and_rn - b .data_unknown @ A: MUL? - nop - b .data_unknown @ B: MUL? - nop - mov r6, r6, ror r9 @ C: ROR #!0 - b .data_arm_apply_r6_and_rn - mov r6, r6, rrx @ D: RRX - b .data_arm_apply_r6_and_rn - b .data_unknown @ E: MUL? - nop - b .data_unknown @ F: MUL? - -/* - * Function: arm6_7_proc_init (void) - * : arm6_7_proc_fin (void) - * - * Notes : This processor does not require these - */ -ENTRY(cpu_arm6_proc_init) -ENTRY(cpu_arm7_proc_init) - mov pc, lr - -ENTRY(cpu_arm6_proc_fin) -ENTRY(cpu_arm7_proc_fin) - mov r0, #0x31 @ ....S..DP...M - mcr p15, 0, r0, c1, c0, 0 @ disable caches - mov pc, lr - -ENTRY(cpu_arm6_do_idle) -ENTRY(cpu_arm7_do_idle) - mov pc, lr - -/* - * Function: arm6_7_switch_mm(unsigned long pgd_phys) - * Params : pgd_phys Physical address of page table - * Purpose : Perform a task switch, saving the old processes state, and restoring - * the new. - */ -ENTRY(cpu_arm6_switch_mm) -ENTRY(cpu_arm7_switch_mm) -#ifdef CONFIG_MMU - mov r1, #0 - mcr p15, 0, r1, c7, c0, 0 @ flush cache - mcr p15, 0, r0, c2, c0, 0 @ update page table ptr - mcr p15, 0, r1, c5, c0, 0 @ flush TLBs -#endif - mov pc, lr - -/* - * Function: arm6_7_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext) - * Params : r0 = Address to set - * : r1 = value to set - * Purpose : Set a PTE and flush it out of any WB cache - */ - .align 5 -ENTRY(cpu_arm6_set_pte_ext) -ENTRY(cpu_arm7_set_pte_ext) -#ifdef CONFIG_MMU - armv3_set_pte_ext wc_disable=0 -#endif /* CONFIG_MMU */ - mov pc, lr - -/* - * Function: _arm6_7_reset - * Params : r0 = address to jump to - * Notes : This sets up everything for a reset - */ - .pushsection .idmap.text, "ax" -ENTRY(cpu_arm6_reset) -ENTRY(cpu_arm7_reset) - mov r1, #0 - mcr p15, 0, r1, c7, c0, 0 @ flush cache -#ifdef CONFIG_MMU - mcr p15, 0, r1, c5, c0, 0 @ flush TLB -#endif - mov r1, #0x30 - mcr p15, 0, r1, c1, c0, 0 @ turn off MMU etc - mov pc, r0 -ENDPROC(cpu_arm6_reset) -ENDPROC(cpu_arm7_reset) - .popsection - - __CPUINIT - - .type __arm6_setup, #function -__arm6_setup: mov r0, #0 - mcr p15, 0, r0, c7, c0 @ flush caches on v3 -#ifdef CONFIG_MMU - mcr p15, 0, r0, c5, c0 @ flush TLBs on v3 - mov r0, #0x3d @ . ..RS BLDP WCAM - orr r0, r0, #0x100 @ . ..01 0011 1101 -#else - mov r0, #0x3c @ . ..RS BLDP WCA. -#endif - mov pc, lr - .size __arm6_setup, . - __arm6_setup - - .type __arm7_setup, #function -__arm7_setup: mov r0, #0 - mcr p15, 0, r0, c7, c0 @ flush caches on v3 -#ifdef CONFIG_MMU - mcr p15, 0, r0, c5, c0 @ flush TLBs on v3 - mcr p15, 0, r0, c3, c0 @ load domain access register - mov r0, #0x7d @ . ..RS BLDP WCAM - orr r0, r0, #0x100 @ . ..01 0111 1101 -#else - mov r0, #0x7c @ . ..RS BLDP WCA. -#endif - mov pc, lr - .size __arm7_setup, . - __arm7_setup - - __INITDATA - - @ define struct processor (see <asm/proc-fns.h> and proc-macros.S) - define_processor_functions arm6, dabort=cpu_arm6_data_abort, pabort=legacy_pabort - define_processor_functions arm7, dabort=cpu_arm7_data_abort, pabort=legacy_pabort - - .section ".rodata" - - string cpu_arch_name, "armv3" - string cpu_elf_name, "v3" - string cpu_arm6_name, "ARM6" - string cpu_arm610_name, "ARM610" - string cpu_arm7_name, "ARM7" - string cpu_arm710_name, "ARM710" - - .align - - .section ".proc.info.init", #alloc, #execinstr - -.macro arm67_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, \ - cpu_mm_mmu_flags:req, cpu_flush:req, cpu_proc_funcs:req - .type __\name\()_proc_info, #object -__\name\()_proc_info: - .long \cpu_val - .long \cpu_mask - .long \cpu_mm_mmu_flags - .long PMD_TYPE_SECT | \ - PMD_BIT4 | \ - PMD_SECT_AP_WRITE | \ - PMD_SECT_AP_READ - b \cpu_flush - .long cpu_arch_name - .long cpu_elf_name - .long HWCAP_SWP | HWCAP_26BIT - .long \cpu_name - .long \cpu_proc_funcs - .long v3_tlb_fns - .long v3_user_fns - .long v3_cache_fns - .size __\name\()_proc_info, . - __\name\()_proc_info -.endm - - arm67_proc_info arm6, 0x41560600, 0xfffffff0, cpu_arm6_name, \ - 0x00000c1e, __arm6_setup, arm6_processor_functions - arm67_proc_info arm610, 0x41560610, 0xfffffff0, cpu_arm610_name, \ - 0x00000c1e, __arm6_setup, arm6_processor_functions - arm67_proc_info arm7, 0x41007000, 0xffffff00, cpu_arm7_name, \ - 0x00000c1e, __arm7_setup, arm7_processor_functions - arm67_proc_info arm710, 0x41007100, 0xfff8ff00, cpu_arm710_name, \ - PMD_TYPE_SECT | \ - PMD_SECT_BUFFERABLE | \ - PMD_SECT_CACHEABLE | \ - PMD_BIT4 | \ - PMD_SECT_AP_WRITE | \ - PMD_SECT_AP_READ, \ - __arm7_setup, arm7_processor_functions diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S index cb941ae95f66..1a8c138eb897 100644 --- a/arch/arm/mm/proc-arm920.S +++ b/arch/arm/mm/proc-arm920.S @@ -210,6 +210,7 @@ ENTRY(arm920_coherent_user_range) cmp r0, r1 blo 1b mcr p15, 0, r0, c7, c10, 4 @ drain WB + mov r0, #0 mov pc, lr /* diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S index 4ec0e074dd55..4c44d7e1c3ca 100644 --- a/arch/arm/mm/proc-arm922.S +++ b/arch/arm/mm/proc-arm922.S @@ -212,6 +212,7 @@ ENTRY(arm922_coherent_user_range) cmp r0, r1 blo 1b mcr p15, 0, r0, c7, c10, 4 @ drain WB + mov r0, #0 mov pc, lr /* diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S index 9dccd9a365b3..ec5b1180994f 100644 --- a/arch/arm/mm/proc-arm925.S +++ b/arch/arm/mm/proc-arm925.S @@ -258,6 +258,7 @@ ENTRY(arm925_coherent_user_range) cmp r0, r1 blo 1b mcr p15, 0, r0, c7, c10, 4 @ drain WB + mov r0, #0 mov pc, lr /* diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S index 820259b81a1f..c31e62c606c0 100644 --- a/arch/arm/mm/proc-arm926.S +++ b/arch/arm/mm/proc-arm926.S @@ -221,6 +221,7 @@ ENTRY(arm926_coherent_user_range) cmp r0, r1 blo 1b mcr p15, 0, r0, c7, c10, 4 @ drain WB + mov r0, #0 mov pc, lr /* diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S index 9fdc0a170974..a613a7dd7146 100644 --- a/arch/arm/mm/proc-arm940.S +++ b/arch/arm/mm/proc-arm940.S @@ -160,7 +160,7 @@ ENTRY(arm940_coherent_user_range) * - size - region size */ ENTRY(arm940_flush_kern_dcache_area) - mov ip, #0 + mov r0, #0 mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index @@ -168,8 +168,8 @@ ENTRY(arm940_flush_kern_dcache_area) bcs 2b @ entries 63 to 0 subs r1, r1, #1 << 4 bcs 1b @ segments 7 to 0 - mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache - mcr p15, 0, ip, c7, c10, 4 @ drain WB + mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache + mcr p15, 0, r0, c7, c10, 4 @ drain WB mov pc, lr /* diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S index f684cfedcca9..9f4f2999fdd0 100644 --- a/arch/arm/mm/proc-arm946.S +++ b/arch/arm/mm/proc-arm946.S @@ -190,6 +190,7 @@ ENTRY(arm946_coherent_user_range) cmp r0, r1 blo 1b mcr p15, 0, r0, c7, c10, 4 @ drain WB + mov r0, #0 mov pc, lr /* diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S index ba3c500584ac..23a8e4c7f2bd 100644 --- a/arch/arm/mm/proc-feroceon.S +++ b/arch/arm/mm/proc-feroceon.S @@ -232,6 +232,7 @@ ENTRY(feroceon_coherent_user_range) cmp r0, r1 blo 1b mcr p15, 0, r0, c7, c10, 4 @ drain WB + mov r0, #0 mov pc, lr /* diff --git a/arch/arm/mm/proc-mohawk.S b/arch/arm/mm/proc-mohawk.S index cdfedc5b8ad8..b0475468c711 100644 --- a/arch/arm/mm/proc-mohawk.S +++ b/arch/arm/mm/proc-mohawk.S @@ -193,6 +193,7 @@ ENTRY(mohawk_coherent_user_range) cmp r0, r1 blo 1b mcr p15, 0, r0, c7, c10, 4 @ drain WB + mov r0, #0 mov pc, lr /* diff --git a/arch/arm/mm/proc-v7-2level.S b/arch/arm/mm/proc-v7-2level.S index 3a4b3e7b888c..42ac069c8012 100644 --- a/arch/arm/mm/proc-v7-2level.S +++ b/arch/arm/mm/proc-v7-2level.S @@ -49,15 +49,10 @@ ENTRY(cpu_v7_switch_mm) #ifdef CONFIG_ARM_ERRATA_754322 dsb #endif - mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID - isb -1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 - isb -#ifdef CONFIG_ARM_ERRATA_754322 - dsb -#endif mcr p15, 0, r1, c13, c0, 1 @ set context ID isb + mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 + isb #endif mov pc, lr ENDPROC(cpu_v7_switch_mm) diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index f1c8486f7501..c2e2b66f72b5 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -255,6 +255,18 @@ __v7_setup: mcr p15, 0, r5, c10, c2, 0 @ write PRRR mcr p15, 0, r6, c10, c2, 1 @ write NMRR #endif +#ifndef CONFIG_ARM_THUMBEE + mrc p15, 0, r0, c0, c1, 0 @ read ID_PFR0 for ThumbEE + and r0, r0, #(0xf << 12) @ ThumbEE enabled field + teq r0, #(1 << 12) @ check if ThumbEE is present + bne 1f + mov r5, #0 + mcr p14, 6, r5, c1, c0, 0 @ Initialize TEEHBR to 0 + mrc p14, 6, r0, c0, c0, 0 @ load TEECR + orr r0, r0, #1 @ set the 1st bit in order to + mcr p14, 6, r0, c0, c0, 0 @ stop userspace TEEHBR access +1: +#endif adr r5, v7_crval ldmia r5, {r5, r6} #ifdef CONFIG_CPU_ENDIAN_BE8 diff --git a/arch/arm/mm/tlb-v3.S b/arch/arm/mm/tlb-v3.S deleted file mode 100644 index d253995ec4ca..000000000000 --- a/arch/arm/mm/tlb-v3.S +++ /dev/null @@ -1,48 +0,0 @@ -/* - * linux/arch/arm/mm/tlbv3.S - * - * Copyright (C) 1997-2002 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * ARM architecture version 3 TLB handling functions. - * - * Processors: ARM610, ARM710. - */ -#include <linux/linkage.h> -#include <linux/init.h> -#include <asm/asm-offsets.h> -#include <asm/tlbflush.h> -#include "proc-macros.S" - - .align 5 -/* - * v3_flush_user_tlb_range(start, end, mm) - * - * Invalidate a range of TLB entries in the specified address space. - * - * - start - range start address - * - end - range end address - * - mm - mm_struct describing address space - */ - .align 5 -ENTRY(v3_flush_user_tlb_range) - vma_vm_mm r2, r2 - act_mm r3 @ get current->active_mm - teq r2, r3 @ == mm ? - movne pc, lr @ no, we dont do anything -ENTRY(v3_flush_kern_tlb_range) - bic r0, r0, #0x0ff - bic r0, r0, #0xf00 -1: mcr p15, 0, r0, c6, c0, 0 @ invalidate TLB entry - add r0, r0, #PAGE_SZ - cmp r0, r1 - blo 1b - mov pc, lr - - __INITDATA - - /* define struct cpu_tlb_fns (see <asm/tlbflush.h> and proc-macros.S) */ - define_tlb_functions v3, v3_tlb_flags diff --git a/arch/arm/plat-iop/pci.c b/arch/arm/plat-iop/pci.c index 0da42058a20f..8daae9b230ea 100644 --- a/arch/arm/plat-iop/pci.c +++ b/arch/arm/plat-iop/pci.c @@ -160,7 +160,7 @@ iop3xx_write_config(struct pci_bus *bus, unsigned int devfn, int where, return PCIBIOS_SUCCESSFUL; } -static struct pci_ops iop3xx_ops = { +struct pci_ops iop3xx_ops = { .read = iop3xx_read_config, .write = iop3xx_write_config, }; @@ -220,12 +220,6 @@ int iop3xx_pci_setup(int nr, struct pci_sys_data *sys) return 1; } -struct pci_bus *iop3xx_pci_scan_bus(int nr, struct pci_sys_data *sys) -{ - return pci_scan_root_bus(NULL, sys->busnr, &iop3xx_ops, sys, - &sys->resources); -} - void __init iop3xx_atu_setup(void) { /* BAR 0 ( Disabled ) */ diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c index 8506cbb7fea4..62ec5c452792 100644 --- a/arch/arm/plat-omap/clock.c +++ b/arch/arm/plat-omap/clock.c @@ -398,32 +398,6 @@ struct clk dummy_ck = { .ops = &clkops_null, }; -#ifdef CONFIG_CPU_FREQ -void clk_init_cpufreq_table(struct cpufreq_frequency_table **table) -{ - unsigned long flags; - - if (!arch_clock || !arch_clock->clk_init_cpufreq_table) - return; - - spin_lock_irqsave(&clockfw_lock, flags); - arch_clock->clk_init_cpufreq_table(table); - spin_unlock_irqrestore(&clockfw_lock, flags); -} - -void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table) -{ - unsigned long flags; - - if (!arch_clock || !arch_clock->clk_exit_cpufreq_table) - return; - - spin_lock_irqsave(&clockfw_lock, flags); - arch_clock->clk_exit_cpufreq_table(table); - spin_unlock_irqrestore(&clockfw_lock, flags); -} -#endif - /* * */ diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c index 5068fe5a6910..44ae077dbc28 100644 --- a/arch/arm/plat-omap/counter_32k.c +++ b/arch/arm/plat-omap/counter_32k.c @@ -19,6 +19,7 @@ #include <linux/io.h> #include <linux/clocksource.h> +#include <asm/mach/time.h> #include <asm/sched_clock.h> #include <plat/hardware.h> @@ -43,7 +44,7 @@ static u32 notrace omap_32k_read_sched_clock(void) } /** - * read_persistent_clock - Return time from a persistent clock. + * omap_read_persistent_clock - Return time from a persistent clock. * * Reads the time from a source which isn't disabled during PM, the * 32k sync timer. Convert the cycles elapsed since last read into @@ -52,7 +53,7 @@ static u32 notrace omap_32k_read_sched_clock(void) static struct timespec persistent_ts; static cycles_t cycles, last_cycles; static unsigned int persistent_mult, persistent_shift; -void read_persistent_clock(struct timespec *ts) +static void omap_read_persistent_clock(struct timespec *ts) { unsigned long long nsecs; cycles_t delta; @@ -116,6 +117,7 @@ int __init omap_init_clocksource_32k(void) printk(err, "32k_counter"); setup_sched_clock(omap_32k_read_sched_clock, 32, 32768); + register_persistent_clock(NULL, omap_read_persistent_clock); } return 0; } diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index ecdb3da0dea9..c58d896cd5c3 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -916,6 +916,13 @@ void omap_start_dma(int lch) l |= OMAP_DMA_CCR_BUFFERING_DISABLE; l |= OMAP_DMA_CCR_EN; + /* + * As dma_write() uses IO accessors which are weakly ordered, there + * is no guarantee that data in coherent DMA memory will be visible + * to the DMA device. Add a memory barrier here to ensure that any + * such data is visible prior to enabling DMA. + */ + mb(); p->dma_write(l, CCR, lch); dma_chan[lch].flags |= OMAP_DMA_ACTIVE; @@ -965,6 +972,13 @@ void omap_stop_dma(int lch) p->dma_write(l, CCR, lch); } + /* + * Ensure that data transferred by DMA is visible to any access + * after DMA has been disabled. This is important for coherent + * DMA regions. + */ + mb(); + if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) { int next_lch, cur_lch = lch; char dma_chan_link_map[dma_lch_count]; diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h index 240a7b9fd946..d0ef57c1d71b 100644 --- a/arch/arm/plat-omap/include/plat/clock.h +++ b/arch/arm/plat-omap/include/plat/clock.h @@ -272,8 +272,6 @@ struct clk { #endif }; -struct cpufreq_frequency_table; - struct clk_functions { int (*clk_enable)(struct clk *clk); void (*clk_disable)(struct clk *clk); @@ -283,10 +281,6 @@ struct clk_functions { void (*clk_allow_idle)(struct clk *clk); void (*clk_deny_idle)(struct clk *clk); void (*clk_disable_unused)(struct clk *clk); -#ifdef CONFIG_CPU_FREQ - void (*clk_init_cpufreq_table)(struct cpufreq_frequency_table **); - void (*clk_exit_cpufreq_table)(struct cpufreq_frequency_table **); -#endif }; extern int mpurate; @@ -301,10 +295,6 @@ extern void recalculate_root_clocks(void); extern unsigned long followparent_recalc(struct clk *clk); extern void clk_enable_init_clocks(void); unsigned long omap_fixed_divisor_recalc(struct clk *clk); -#ifdef CONFIG_CPU_FREQ -extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table); -extern void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table); -#endif extern struct clk *omap_clk_get_by_name(const char *name); extern int omap_clk_enable_autoidle_all(void); extern int omap_clk_disable_autoidle_all(void); diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index 8070145ccb98..3f26db4ee8e6 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -305,6 +305,7 @@ struct omap_hwmod_sysc_fields { * @rev_offs: IP block revision register offset (from module base addr) * @sysc_offs: OCP_SYSCONFIG register offset (from module base addr) * @syss_offs: OCP_SYSSTATUS register offset (from module base addr) + * @srst_udelay: Delay needed after doing a softreset in usecs * @idlemodes: One or more of {SIDLE,MSTANDBY}_{OFF,FORCE,SMART} * @sysc_flags: SYS{C,S}_HAS* flags indicating SYSCONFIG bits supported * @clockact: the default value of the module CLOCKACTIVITY bits @@ -330,9 +331,10 @@ struct omap_hwmod_class_sysconfig { u16 sysc_offs; u16 syss_offs; u16 sysc_flags; + struct omap_hwmod_sysc_fields *sysc_fields; + u8 srst_udelay; u8 idlemodes; u8 clockact; - struct omap_hwmod_sysc_fields *sysc_fields; }; /** diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index eec98afa0f83..f9a8c5341ee9 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c @@ -348,7 +348,6 @@ u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc, sdrc_actim_ctrl_b_1, sdrc_mr_1); } -#ifdef CONFIG_PM void omap3_sram_restore_context(void) { omap_sram_ceil = omap_sram_base + omap_sram_size; @@ -358,17 +357,18 @@ void omap3_sram_restore_context(void) omap3_sram_configure_core_dpll_sz); omap_push_sram_idle(); } -#endif /* CONFIG_PM */ - -#endif /* CONFIG_ARCH_OMAP3 */ static inline int omap34xx_sram_init(void) { -#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) omap3_sram_restore_context(); -#endif return 0; } +#else +static inline int omap34xx_sram_init(void) +{ + return 0; +} +#endif /* CONFIG_ARCH_OMAP3 */ static inline int am33xx_sram_init(void) { diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig index 71553f410016..a0ffc77da809 100644 --- a/arch/arm/plat-samsung/Kconfig +++ b/arch/arm/plat-samsung/Kconfig @@ -302,6 +302,7 @@ comment "Power management" config SAMSUNG_PM_DEBUG bool "S3C2410 PM Suspend debug" depends on PM + select DEBUG_LL help Say Y here if you want verbose debugging from the PM Suspend and Resume code. See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt> diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h index 317e246ffc56..e834c5ef437c 100644 --- a/arch/arm/plat-samsung/include/plat/sdhci.h +++ b/arch/arm/plat-samsung/include/plat/sdhci.h @@ -18,6 +18,8 @@ #ifndef __PLAT_S3C_SDHCI_H #define __PLAT_S3C_SDHCI_H __FILE__ +#include <plat/devs.h> + struct platform_device; struct mmc_host; struct mmc_card; @@ -356,4 +358,30 @@ static inline void exynos4_default_sdhci3(void) { } #endif /* CONFIG_EXYNOS4_SETUP_SDHCI */ +static inline void s3c_sdhci_setname(int id, char *name) +{ + switch (id) { +#ifdef CONFIG_S3C_DEV_HSMMC + case 0: + s3c_device_hsmmc0.name = name; + break; +#endif +#ifdef CONFIG_S3C_DEV_HSMMC1 + case 1: + s3c_device_hsmmc1.name = name; + break; +#endif +#ifdef CONFIG_S3C_DEV_HSMMC2 + case 2: + s3c_device_hsmmc2.name = name; + break; +#endif +#ifdef CONFIG_S3C_DEV_HSMMC3 + case 3: + s3c_device_hsmmc3.name = name; + break; +#endif + } +} + #endif /* __PLAT_S3C_SDHCI_H */ diff --git a/arch/arm/plat-versatile/Kconfig b/arch/arm/plat-versatile/Kconfig index 043f7b02a9e7..81ee7cc34457 100644 --- a/arch/arm/plat-versatile/Kconfig +++ b/arch/arm/plat-versatile/Kconfig @@ -5,6 +5,12 @@ config PLAT_VERSATILE_CLCD config PLAT_VERSATILE_FPGA_IRQ bool + select IRQ_DOMAIN + +config PLAT_VERSATILE_FPGA_IRQ_NR + int + default 4 + depends on PLAT_VERSATILE_FPGA_IRQ config PLAT_VERSATILE_LEDS def_bool y if LEDS_CLASS diff --git a/arch/arm/plat-versatile/fpga-irq.c b/arch/arm/plat-versatile/fpga-irq.c index f0cc8e19b094..6e70d03824a1 100644 --- a/arch/arm/plat-versatile/fpga-irq.c +++ b/arch/arm/plat-versatile/fpga-irq.c @@ -3,7 +3,10 @@ */ #include <linux/irq.h> #include <linux/io.h> +#include <linux/irqdomain.h> +#include <linux/module.h> +#include <asm/exception.h> #include <asm/mach/irq.h> #include <plat/fpga-irq.h> @@ -12,10 +15,32 @@ #define IRQ_ENABLE_SET 0x08 #define IRQ_ENABLE_CLEAR 0x0c +/** + * struct fpga_irq_data - irq data container for the FPGA IRQ controller + * @base: memory offset in virtual memory + * @irq_start: first IRQ number handled by this instance + * @chip: chip container for this instance + * @domain: IRQ domain for this instance + * @valid: mask for valid IRQs on this controller + * @used_irqs: number of active IRQs on this controller + */ +struct fpga_irq_data { + void __iomem *base; + unsigned int irq_start; + struct irq_chip chip; + u32 valid; + struct irq_domain *domain; + u8 used_irqs; +}; + +/* we cannot allocate memory when the controllers are initially registered */ +static struct fpga_irq_data fpga_irq_devices[CONFIG_PLAT_VERSATILE_FPGA_IRQ_NR]; +static int fpga_irq_id; + static void fpga_irq_mask(struct irq_data *d) { struct fpga_irq_data *f = irq_data_get_irq_chip_data(d); - u32 mask = 1 << (d->irq - f->irq_start); + u32 mask = 1 << d->hwirq; writel(mask, f->base + IRQ_ENABLE_CLEAR); } @@ -23,7 +48,7 @@ static void fpga_irq_mask(struct irq_data *d) static void fpga_irq_unmask(struct irq_data *d) { struct fpga_irq_data *f = irq_data_get_irq_chip_data(d); - u32 mask = 1 << (d->irq - f->irq_start); + u32 mask = 1 << d->hwirq; writel(mask, f->base + IRQ_ENABLE_SET); } @@ -41,32 +66,93 @@ static void fpga_irq_handle(unsigned int irq, struct irq_desc *desc) do { irq = ffs(status) - 1; status &= ~(1 << irq); - - generic_handle_irq(irq + f->irq_start); + generic_handle_irq(irq_find_mapping(f->domain, irq)); } while (status); } -void __init fpga_irq_init(int parent_irq, u32 valid, struct fpga_irq_data *f) +/* + * Handle each interrupt in a single FPGA IRQ controller. Returns non-zero + * if we've handled at least one interrupt. This does a single read of the + * status register and handles all interrupts in order from LSB first. + */ +static int handle_one_fpga(struct fpga_irq_data *f, struct pt_regs *regs) +{ + int handled = 0; + int irq; + u32 status; + + while ((status = readl(f->base + IRQ_STATUS))) { + irq = ffs(status) - 1; + handle_IRQ(irq_find_mapping(f->domain, irq), regs); + handled = 1; + } + + return handled; +} + +/* + * Keep iterating over all registered FPGA IRQ controllers until there are + * no pending interrupts. + */ +asmlinkage void __exception_irq_entry fpga_handle_irq(struct pt_regs *regs) { - unsigned int i; + int i, handled; + do { + for (i = 0, handled = 0; i < fpga_irq_id; ++i) + handled |= handle_one_fpga(&fpga_irq_devices[i], regs); + } while (handled); +} + +static int fpga_irqdomain_map(struct irq_domain *d, unsigned int irq, + irq_hw_number_t hwirq) +{ + struct fpga_irq_data *f = d->host_data; + + /* Skip invalid IRQs, only register handlers for the real ones */ + if (!(f->valid & (1 << hwirq))) + return -ENOTSUPP; + irq_set_chip_data(irq, f); + irq_set_chip_and_handler(irq, &f->chip, + handle_level_irq); + set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); + f->used_irqs++; + return 0; +} + +static struct irq_domain_ops fpga_irqdomain_ops = { + .map = fpga_irqdomain_map, + .xlate = irq_domain_xlate_onetwocell, +}; + +void __init fpga_irq_init(void __iomem *base, const char *name, int irq_start, + int parent_irq, u32 valid, struct device_node *node) +{ + struct fpga_irq_data *f; + + if (fpga_irq_id >= ARRAY_SIZE(fpga_irq_devices)) { + printk(KERN_ERR "%s: too few FPGA IRQ controllers, increase CONFIG_PLAT_VERSATILE_FPGA_IRQ_NR\n", __func__); + return; + } + + f = &fpga_irq_devices[fpga_irq_id]; + f->base = base; + f->irq_start = irq_start; + f->chip.name = name; f->chip.irq_ack = fpga_irq_mask; f->chip.irq_mask = fpga_irq_mask; f->chip.irq_unmask = fpga_irq_unmask; + f->valid = valid; if (parent_irq != -1) { irq_set_handler_data(parent_irq, f); irq_set_chained_handler(parent_irq, fpga_irq_handle); } - for (i = 0; i < 32; i++) { - if (valid & (1 << i)) { - unsigned int irq = f->irq_start + i; + f->domain = irq_domain_add_legacy(node, fls(valid), f->irq_start, 0, + &fpga_irqdomain_ops, f); + pr_info("FPGA IRQ chip %d \"%s\" @ %p, %u irqs\n", + fpga_irq_id, name, base, f->used_irqs); - irq_set_chip_data(irq, f); - irq_set_chip_and_handler(irq, &f->chip, - handle_level_irq); - set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); - } - } + fpga_irq_id++; } diff --git a/arch/arm/plat-versatile/include/plat/fpga-irq.h b/arch/arm/plat-versatile/include/plat/fpga-irq.h index 627fafd1e595..91bcfb67551d 100644 --- a/arch/arm/plat-versatile/include/plat/fpga-irq.h +++ b/arch/arm/plat-versatile/include/plat/fpga-irq.h @@ -1,12 +1,11 @@ #ifndef PLAT_FPGA_IRQ_H #define PLAT_FPGA_IRQ_H -struct fpga_irq_data { - void __iomem *base; - unsigned int irq_start; - struct irq_chip chip; -}; +struct device_node; +struct pt_regs; -void fpga_irq_init(int, u32, struct fpga_irq_data *); +void fpga_handle_irq(struct pt_regs *regs); +void fpga_irq_init(void __iomem *, const char *, int, int, u32, + struct device_node *node); #endif diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types index f9c9f33f8cbe..2997e56ce0dd 100644 --- a/arch/arm/tools/mach-types +++ b/arch/arm/tools/mach-types @@ -16,7 +16,7 @@ # are merged into mainline or have been edited in the machine database # within the last 12 months. References to machine_is_NAME() do not count! # -# Last update: Tue Dec 6 11:07:38 2011 +# Last update: Thu Apr 26 08:44:23 2012 # # machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number # @@ -205,6 +205,7 @@ omap_fsample MACH_OMAP_FSAMPLE OMAP_FSAMPLE 970 snapper_cl15 MACH_SNAPPER_CL15 SNAPPER_CL15 986 omap_palmz71 MACH_OMAP_PALMZ71 OMAP_PALMZ71 993 smdk2412 MACH_SMDK2412 SMDK2412 1009 +bkde303 MACH_BKDE303 BKDE303 1021 smdk2413 MACH_SMDK2413 SMDK2413 1022 aml_m5900 MACH_AML_M5900 AML_M5900 1024 balloon3 MACH_BALLOON3 BALLOON3 1029 @@ -381,8 +382,6 @@ davinci_da850_evm MACH_DAVINCI_DA850_EVM DAVINCI_DA850_EVM 2157 at91sam9g10ek MACH_AT91SAM9G10EK AT91SAM9G10EK 2159 omap_4430sdp MACH_OMAP_4430SDP OMAP_4430SDP 2160 magx_zn5 MACH_MAGX_ZN5 MAGX_ZN5 2162 -btmavb101 MACH_BTMAVB101 BTMAVB101 2172 -btmawb101 MACH_BTMAWB101 BTMAWB101 2173 tx25 MACH_TX25 TX25 2177 omap3_torpedo MACH_OMAP3_TORPEDO OMAP3_TORPEDO 2178 anw6410 MACH_ANW6410 ANW6410 2183 @@ -397,7 +396,6 @@ net2big_v2 MACH_NET2BIG_V2 NET2BIG_V2 2204 net5big_v2 MACH_NET5BIG_V2 NET5BIG_V2 2206 inetspace_v2 MACH_INETSPACE_V2 INETSPACE_V2 2208 at91sam9g45ekes MACH_AT91SAM9G45EKES AT91SAM9G45EKES 2212 -pc7302 MACH_PC7302 PC7302 2220 spear600 MACH_SPEAR600 SPEAR600 2236 spear300 MACH_SPEAR300 SPEAR300 2237 lilly1131 MACH_LILLY1131 LILLY1131 2239 @@ -407,7 +405,6 @@ d2net MACH_D2NET D2NET 2282 bigdisk MACH_BIGDISK BIGDISK 2283 at91sam9g20ek_2mmc MACH_AT91SAM9G20EK_2MMC AT91SAM9G20EK_2MMC 2288 bcmring MACH_BCMRING BCMRING 2289 -dp6xx MACH_DP6XX DP6XX 2302 mahimahi MACH_MAHIMAHI MAHIMAHI 2304 smdk6442 MACH_SMDK6442 SMDK6442 2324 openrd_base MACH_OPENRD_BASE OPENRD_BASE 2325 @@ -444,8 +441,6 @@ mx28evk MACH_MX28EVK MX28EVK 2531 smartq5 MACH_SMARTQ5 SMARTQ5 2534 davinci_dm6467tevm MACH_DAVINCI_DM6467TEVM DAVINCI_DM6467TEVM 2548 mxt_td60 MACH_MXT_TD60 MXT_TD60 2550 -riot_bei2 MACH_RIOT_BEI2 RIOT_BEI2 2576 -riot_x37 MACH_RIOT_X37 RIOT_X37 2578 pca101 MACH_PCA101 PCA101 2595 capc7117 MACH_CAPC7117 CAPC7117 2612 icontrol MACH_ICONTROL ICONTROL 2624 @@ -460,7 +455,6 @@ spear320 MACH_SPEAR320 SPEAR320 2661 aquila MACH_AQUILA AQUILA 2676 esata_sheevaplug MACH_ESATA_SHEEVAPLUG ESATA_SHEEVAPLUG 2678 msm7x30_surf MACH_MSM7X30_SURF MSM7X30_SURF 2679 -ea2478devkit MACH_EA2478DEVKIT EA2478DEVKIT 2683 terastation_wxl MACH_TERASTATION_WXL TERASTATION_WXL 2697 msm7x25_surf MACH_MSM7X25_SURF MSM7X25_SURF 2703 msm7x25_ffa MACH_MSM7X25_FFA MSM7X25_FFA 2704 @@ -479,8 +473,6 @@ wbd222 MACH_WBD222 WBD222 2753 msm8x60_surf MACH_MSM8X60_SURF MSM8X60_SURF 2755 msm8x60_sim MACH_MSM8X60_SIM MSM8X60_SIM 2756 tcc8000_sdk MACH_TCC8000_SDK TCC8000_SDK 2758 -nanos MACH_NANOS NANOS 2759 -stamp9g45 MACH_STAMP9G45 STAMP9G45 2761 cns3420vb MACH_CNS3420VB CNS3420VB 2776 omap4_panda MACH_OMAP4_PANDA OMAP4_PANDA 2791 ti8168evm MACH_TI8168EVM TI8168EVM 2800 @@ -490,12 +482,9 @@ eukrea_cpuimx35sd MACH_EUKREA_CPUIMX35SD EUKREA_CPUIMX35SD 2821 eukrea_cpuimx51sd MACH_EUKREA_CPUIMX51SD EUKREA_CPUIMX51SD 2822 eukrea_cpuimx51 MACH_EUKREA_CPUIMX51 EUKREA_CPUIMX51 2823 smdkc210 MACH_SMDKC210 SMDKC210 2838 -pca102 MACH_PCA102 PCA102 2843 +pcaal1 MACH_PCAAL1 PCAAL1 2843 t5325 MACH_T5325 T5325 2846 income MACH_INCOME INCOME 2849 -vvbox_sdorig2 MACH_VVBOX_SDORIG2 VVBOX_SDORIG2 2857 -vvbox_sdlite2 MACH_VVBOX_SDLITE2 VVBOX_SDLITE2 2858 -vvbox_sdpro4 MACH_VVBOX_SDPRO4 VVBOX_SDPRO4 2859 mx257sx MACH_MX257SX MX257SX 2861 goni MACH_GONI GONI 2862 bv07 MACH_BV07 BV07 2882 @@ -504,6 +493,7 @@ devixp MACH_DEVIXP DEVIXP 2885 miccpt MACH_MICCPT MICCPT 2886 mic256 MACH_MIC256 MIC256 2887 u5500 MACH_U5500 U5500 2890 +pov15hd MACH_POV15HD POV15HD 2910 linkstation_lschl MACH_LINKSTATION_LSCHL LINKSTATION_LSCHL 2913 smdkv310 MACH_SMDKV310 SMDKV310 2925 wm8505_7in_netbook MACH_WM8505_7IN_NETBOOK WM8505_7IN_NETBOOK 2928 @@ -537,243 +527,24 @@ trimslice MACH_TRIMSLICE TRIMSLICE 3209 mackerel MACH_MACKEREL MACKEREL 3211 kaen MACH_KAEN KAEN 3217 nokia_rm680 MACH_NOKIA_RM680 NOKIA_RM680 3220 -dm6446_adbox MACH_DM6446_ADBOX DM6446_ADBOX 3226 -quad_salsa MACH_QUAD_SALSA QUAD_SALSA 3227 -abb_gma_1_1 MACH_ABB_GMA_1_1 ABB_GMA_1_1 3228 -svcid MACH_SVCID SVCID 3229 msm8960_sim MACH_MSM8960_SIM MSM8960_SIM 3230 msm8960_rumi3 MACH_MSM8960_RUMI3 MSM8960_RUMI3 3231 -icon_g MACH_ICON_G ICON_G 3232 -mb3 MACH_MB3 MB3 3233 gsia18s MACH_GSIA18S GSIA18S 3234 -pivicc MACH_PIVICC PIVICC 3235 -pcm048 MACH_PCM048 PCM048 3236 -dds MACH_DDS DDS 3237 -chalten_xa1 MACH_CHALTEN_XA1 CHALTEN_XA1 3238 -ts48xx MACH_TS48XX TS48XX 3239 -tonga2_tfttimer MACH_TONGA2_TFTTIMER TONGA2_TFTTIMER 3240 -whistler MACH_WHISTLER WHISTLER 3241 -asl_phoenix MACH_ASL_PHOENIX ASL_PHOENIX 3242 -at91sam9263otlite MACH_AT91SAM9263OTLITE AT91SAM9263OTLITE 3243 -ddplug MACH_DDPLUG DDPLUG 3244 -d2plug MACH_D2PLUG D2PLUG 3245 -kzm9d MACH_KZM9D KZM9D 3246 -verdi_lte MACH_VERDI_LTE VERDI_LTE 3247 -nanozoom MACH_NANOZOOM NANOZOOM 3248 -dm3730_som_lv MACH_DM3730_SOM_LV DM3730_SOM_LV 3249 -dm3730_torpedo MACH_DM3730_TORPEDO DM3730_TORPEDO 3250 -anchovy MACH_ANCHOVY ANCHOVY 3251 -re2rev20 MACH_RE2REV20 RE2REV20 3253 -re2rev21 MACH_RE2REV21 RE2REV21 3254 -cns21xx MACH_CNS21XX CNS21XX 3255 -rider MACH_RIDER RIDER 3257 -nsk330 MACH_NSK330 NSK330 3258 -cns2133evb MACH_CNS2133EVB CNS2133EVB 3259 -z3_816x_mod MACH_Z3_816X_MOD Z3_816X_MOD 3260 -z3_814x_mod MACH_Z3_814X_MOD Z3_814X_MOD 3261 -beect MACH_BEECT BEECT 3262 -dma_thunderbug MACH_DMA_THUNDERBUG DMA_THUNDERBUG 3263 -omn_at91sam9g20 MACH_OMN_AT91SAM9G20 OMN_AT91SAM9G20 3264 -mx25_e2s_uc MACH_MX25_E2S_UC MX25_E2S_UC 3265 -mione MACH_MIONE MIONE 3266 -top9000_tcu MACH_TOP9000_TCU TOP9000_TCU 3267 -top9000_bsl MACH_TOP9000_BSL TOP9000_BSL 3268 -kingdom MACH_KINGDOM KINGDOM 3269 -armadillo460 MACH_ARMADILLO460 ARMADILLO460 3270 -lq2 MACH_LQ2 LQ2 3271 -sweda_tms2 MACH_SWEDA_TMS2 SWEDA_TMS2 3272 mx53_loco MACH_MX53_LOCO MX53_LOCO 3273 -acer_a8 MACH_ACER_A8 ACER_A8 3275 -acer_gauguin MACH_ACER_GAUGUIN ACER_GAUGUIN 3276 -guppy MACH_GUPPY GUPPY 3277 -mx61_ard MACH_MX61_ARD MX61_ARD 3278 tx53 MACH_TX53 TX53 3279 -omapl138_case_a3 MACH_OMAPL138_CASE_A3 OMAPL138_CASE_A3 3280 -uemd MACH_UEMD UEMD 3281 -ccwmx51mut MACH_CCWMX51MUT CCWMX51MUT 3282 -rockhopper MACH_ROCKHOPPER ROCKHOPPER 3283 encore MACH_ENCORE ENCORE 3284 -hkdkc100 MACH_HKDKC100 HKDKC100 3285 -ts42xx MACH_TS42XX TS42XX 3286 -aebl MACH_AEBL AEBL 3287 wario MACH_WARIO WARIO 3288 -gfs_spm MACH_GFS_SPM GFS_SPM 3289 cm_t3730 MACH_CM_T3730 CM_T3730 3290 -isc3 MACH_ISC3 ISC3 3291 -rascal MACH_RASCAL RASCAL 3292 hrefv60 MACH_HREFV60 HREFV60 3293 -tpt_2_0 MACH_TPT_2_0 TPT_2_0 3294 -splendor MACH_SPLENDOR SPLENDOR 3296 -msm8x60_qt MACH_MSM8X60_QT MSM8X60_QT 3298 -htc_hd_mini MACH_HTC_HD_MINI HTC_HD_MINI 3299 -athene MACH_ATHENE ATHENE 3300 -deep_r_ek_1 MACH_DEEP_R_EK_1 DEEP_R_EK_1 3301 -vivow_ct MACH_VIVOW_CT VIVOW_CT 3302 -nery_1000 MACH_NERY_1000 NERY_1000 3303 -rfl109145_ssrv MACH_RFL109145_SSRV RFL109145_SSRV 3304 -nmh MACH_NMH NMH 3305 -wn802t MACH_WN802T WN802T 3306 -dragonet MACH_DRAGONET DRAGONET 3307 -at91sam9263desk16l MACH_AT91SAM9263DESK16L AT91SAM9263DESK16L 3309 -bcmhana_sv MACH_BCMHANA_SV BCMHANA_SV 3310 -bcmhana_tablet MACH_BCMHANA_TABLET BCMHANA_TABLET 3311 -koi MACH_KOI KOI 3312 -ts4800 MACH_TS4800 TS4800 3313 -tqma9263 MACH_TQMA9263 TQMA9263 3314 -holiday MACH_HOLIDAY HOLIDAY 3315 -pcats_overlay MACH_PCATS_OVERLAY PCATS_OVERLAY 3317 -hwgw6410 MACH_HWGW6410 HWGW6410 3318 -shenzhou MACH_SHENZHOU SHENZHOU 3319 -cwme9210 MACH_CWME9210 CWME9210 3320 -cwme9210js MACH_CWME9210JS CWME9210JS 3321 -colibri_tegra2 MACH_COLIBRI_TEGRA2 COLIBRI_TEGRA2 3323 -w21 MACH_W21 W21 3324 -polysat1 MACH_POLYSAT1 POLYSAT1 3325 -dataway MACH_DATAWAY DATAWAY 3326 -cobral138 MACH_COBRAL138 COBRAL138 3327 -roverpcs8 MACH_ROVERPCS8 ROVERPCS8 3328 -marvelc MACH_MARVELC MARVELC 3329 -navefihid MACH_NAVEFIHID NAVEFIHID 3330 -dm365_cv100 MACH_DM365_CV100 DM365_CV100 3331 -able MACH_ABLE ABLE 3332 -legacy MACH_LEGACY LEGACY 3333 -icong MACH_ICONG ICONG 3334 -rover_g8 MACH_ROVER_G8 ROVER_G8 3335 -t5388p MACH_T5388P T5388P 3336 -dingo MACH_DINGO DINGO 3337 -goflexhome MACH_GOFLEXHOME GOFLEXHOME 3338 -lanreadyfn511 MACH_LANREADYFN511 LANREADYFN511 3340 -omap3_baia MACH_OMAP3_BAIA OMAP3_BAIA 3341 -omap3smartdisplay MACH_OMAP3SMARTDISPLAY OMAP3SMARTDISPLAY 3342 -xilinx MACH_XILINX XILINX 3343 -a2f MACH_A2F A2F 3344 -sky25 MACH_SKY25 SKY25 3345 -ccmx53 MACH_CCMX53 CCMX53 3346 -ccmx53js MACH_CCMX53JS CCMX53JS 3347 -ccwmx53 MACH_CCWMX53 CCWMX53 3348 -ccwmx53js MACH_CCWMX53JS CCWMX53JS 3349 -frisms MACH_FRISMS FRISMS 3350 -msm7x27a_ffa MACH_MSM7X27A_FFA MSM7X27A_FFA 3351 -msm7x27a_surf MACH_MSM7X27A_SURF MSM7X27A_SURF 3352 -msm7x27a_rumi3 MACH_MSM7X27A_RUMI3 MSM7X27A_RUMI3 3353 -dimmsam9g20 MACH_DIMMSAM9G20 DIMMSAM9G20 3354 -dimm_imx28 MACH_DIMM_IMX28 DIMM_IMX28 3355 -amk_a4 MACH_AMK_A4 AMK_A4 3356 -gnet_sgme MACH_GNET_SGME GNET_SGME 3357 -shooter_u MACH_SHOOTER_U SHOOTER_U 3358 -vmx53 MACH_VMX53 VMX53 3359 -rhino MACH_RHINO RHINO 3360 armlex4210 MACH_ARMLEX4210 ARMLEX4210 3361 -swarcoextmodem MACH_SWARCOEXTMODEM SWARCOEXTMODEM 3362 snowball MACH_SNOWBALL SNOWBALL 3363 -pcm049 MACH_PCM049 PCM049 3364 -vigor MACH_VIGOR VIGOR 3365 -oslo_amundsen MACH_OSLO_AMUNDSEN OSLO_AMUNDSEN 3366 -gsl_diamond MACH_GSL_DIAMOND GSL_DIAMOND 3367 -cv2201 MACH_CV2201 CV2201 3368 -cv2202 MACH_CV2202 CV2202 3369 -cv2203 MACH_CV2203 CV2203 3370 -vit_ibox MACH_VIT_IBOX VIT_IBOX 3371 -dm6441_esp MACH_DM6441_ESP DM6441_ESP 3372 -at91sam9x5ek MACH_AT91SAM9X5EK AT91SAM9X5EK 3373 -libra MACH_LIBRA LIBRA 3374 -easycrrh MACH_EASYCRRH EASYCRRH 3375 -tripel MACH_TRIPEL TRIPEL 3376 -endian_mini MACH_ENDIAN_MINI ENDIAN_MINI 3377 xilinx_ep107 MACH_XILINX_EP107 XILINX_EP107 3378 nuri MACH_NURI NURI 3379 -janus MACH_JANUS JANUS 3380 -ddnas MACH_DDNAS DDNAS 3381 -tag MACH_TAG TAG 3382 -tagw MACH_TAGW TAGW 3383 -nitrogen_vm_imx51 MACH_NITROGEN_VM_IMX51 NITROGEN_VM_IMX51 3384 -viprinet MACH_VIPRINET VIPRINET 3385 -bockw MACH_BOCKW BOCKW 3386 -eva2000 MACH_EVA2000 EVA2000 3387 -steelyard MACH_STEELYARD STEELYARD 3388 -nsslsboard MACH_NSSLSBOARD NSSLSBOARD 3392 -geneva_b5 MACH_GENEVA_B5 GENEVA_B5 3393 -spear1340 MACH_SPEAR1340 SPEAR1340 3394 -rexmas MACH_REXMAS REXMAS 3395 -msm8960_cdp MACH_MSM8960_CDP MSM8960_CDP 3396 -msm8960_fluid MACH_MSM8960_FLUID MSM8960_FLUID 3398 -msm8960_apq MACH_MSM8960_APQ MSM8960_APQ 3399 -helios_v2 MACH_HELIOS_V2 HELIOS_V2 3400 -mif10p MACH_MIF10P MIF10P 3401 -iam28 MACH_IAM28 IAM28 3402 -picasso MACH_PICASSO PICASSO 3403 -mr301a MACH_MR301A MR301A 3404 -notle MACH_NOTLE NOTLE 3405 -eelx2 MACH_EELX2 EELX2 3406 -moon MACH_MOON MOON 3407 -ruby MACH_RUBY RUBY 3408 -goldengate MACH_GOLDENGATE GOLDENGATE 3409 -ctbu_gen2 MACH_CTBU_GEN2 CTBU_GEN2 3410 -kmp_am17_01 MACH_KMP_AM17_01 KMP_AM17_01 3411 wtplug MACH_WTPLUG WTPLUG 3412 -mx27su2 MACH_MX27SU2 MX27SU2 3413 -nb31 MACH_NB31 NB31 3414 -hjsdu MACH_HJSDU HJSDU 3415 -td3_rev1 MACH_TD3_REV1 TD3_REV1 3416 -eag_ci4000 MACH_EAG_CI4000 EAG_CI4000 3417 -net5big_nand_v2 MACH_NET5BIG_NAND_V2 NET5BIG_NAND_V2 3418 -cpx2 MACH_CPX2 CPX2 3419 -net2big_nand_v2 MACH_NET2BIG_NAND_V2 NET2BIG_NAND_V2 3420 -ecuv5 MACH_ECUV5 ECUV5 3421 -hsgx6d MACH_HSGX6D HSGX6D 3422 -dawad7 MACH_DAWAD7 DAWAD7 3423 -sam9repeater MACH_SAM9REPEATER SAM9REPEATER 3424 -gt_i5700 MACH_GT_I5700 GT_I5700 3425 -ctera_plug_c2 MACH_CTERA_PLUG_C2 CTERA_PLUG_C2 3426 -marvelct MACH_MARVELCT MARVELCT 3427 -ag11005 MACH_AG11005 AG11005 3428 -vangogh MACH_VANGOGH VANGOGH 3430 -matrix505 MACH_MATRIX505 MATRIX505 3431 -oce_nigma MACH_OCE_NIGMA OCE_NIGMA 3432 -t55 MACH_T55 T55 3433 -bio3k MACH_BIO3K BIO3K 3434 -expressct MACH_EXPRESSCT EXPRESSCT 3435 -cardhu MACH_CARDHU CARDHU 3436 -aruba MACH_ARUBA ARUBA 3437 -bonaire MACH_BONAIRE BONAIRE 3438 -nuc700evb MACH_NUC700EVB NUC700EVB 3439 -nuc710evb MACH_NUC710EVB NUC710EVB 3440 -nuc740evb MACH_NUC740EVB NUC740EVB 3441 -nuc745evb MACH_NUC745EVB NUC745EVB 3442 -transcede MACH_TRANSCEDE TRANSCEDE 3443 -mora MACH_MORA MORA 3444 -nda_evm MACH_NDA_EVM NDA_EVM 3445 -timu MACH_TIMU TIMU 3446 -expressh MACH_EXPRESSH EXPRESSH 3447 veridis_a300 MACH_VERIDIS_A300 VERIDIS_A300 3448 -dm368_leopard MACH_DM368_LEOPARD DM368_LEOPARD 3449 -omap_mcop MACH_OMAP_MCOP OMAP_MCOP 3450 -tritip MACH_TRITIP TRITIP 3451 -sm1k MACH_SM1K SM1K 3452 -monch MACH_MONCH MONCH 3453 -curacao MACH_CURACAO CURACAO 3454 origen MACH_ORIGEN ORIGEN 3455 -epc10 MACH_EPC10 EPC10 3456 -sgh_i740 MACH_SGH_I740 SGH_I740 3457 -tuna MACH_TUNA TUNA 3458 -mx51_tulip MACH_MX51_TULIP MX51_TULIP 3459 -mx51_aster7 MACH_MX51_ASTER7 MX51_ASTER7 3460 -acro37xbrd MACH_ACRO37XBRD ACRO37XBRD 3461 -elke MACH_ELKE ELKE 3462 -sbc6000x MACH_SBC6000X SBC6000X 3463 -r1801e MACH_R1801E R1801E 3464 -h1600 MACH_H1600 H1600 3465 -mini210 MACH_MINI210 MINI210 3466 -mini8168 MACH_MINI8168 MINI8168 3467 -pc7308 MACH_PC7308 PC7308 3468 -kmm2m01 MACH_KMM2M01 KMM2M01 3470 -mx51erebus MACH_MX51EREBUS MX51EREBUS 3471 wm8650refboard MACH_WM8650REFBOARD WM8650REFBOARD 3472 -tuxrail MACH_TUXRAIL TUXRAIL 3473 -arthur MACH_ARTHUR ARTHUR 3474 -doorboy MACH_DOORBOY DOORBOY 3475 xarina MACH_XARINA XARINA 3476 -roverx7 MACH_ROVERX7 ROVERX7 3477 sdvr MACH_SDVR SDVR 3478 acer_maya MACH_ACER_MAYA ACER_MAYA 3479 pico MACH_PICO PICO 3480 @@ -999,6 +770,7 @@ promwad_jade MACH_PROMWAD_JADE PROMWAD_JADE 3708 amp MACH_AMP AMP 3709 gnet_amp MACH_GNET_AMP GNET_AMP 3710 toques MACH_TOQUES TOQUES 3711 +apx4devkit MACH_APX4DEVKIT APX4DEVKIT 3712 dct_storm MACH_DCT_STORM DCT_STORM 3713 owl MACH_OWL OWL 3715 cogent_csb1741 MACH_COGENT_CSB1741 COGENT_CSB1741 3716 @@ -1063,7 +835,6 @@ shelter MACH_SHELTER SHELTER 3778 omap3_devkit8500 MACH_OMAP3_DEVKIT8500 OMAP3_DEVKIT8500 3779 edgetd MACH_EDGETD EDGETD 3780 copperyard MACH_COPPERYARD COPPERYARD 3781 -edge MACH_EDGE EDGE 3782 edge_u MACH_EDGE_U EDGE_U 3783 edge_td MACH_EDGE_TD EDGE_TD 3784 wdss MACH_WDSS WDSS 3785 @@ -1169,3 +940,269 @@ elite_ulk MACH_ELITE_ULK ELITE_ULK 3888 pov2 MACH_POV2 POV2 3889 ipod_touch_2g MACH_IPOD_TOUCH_2G IPOD_TOUCH_2G 3890 da850_pqab MACH_DA850_PQAB DA850_PQAB 3891 +fermi MACH_FERMI FERMI 3892 +ccardwmx28 MACH_CCARDWMX28 CCARDWMX28 3893 +ccardmx28 MACH_CCARDMX28 CCARDMX28 3894 +fs20_fcm2050 MACH_FS20_FCM2050 FS20_FCM2050 3895 +kinetis MACH_KINETIS KINETIS 3896 +kai MACH_KAI KAI 3897 +bcthb2 MACH_BCTHB2 BCTHB2 3898 +inels3_cu MACH_INELS3_CU INELS3_CU 3899 +da850_apollo MACH_DA850_APOLLO DA850_APOLLO 3901 +tracnas MACH_TRACNAS TRACNAS 3902 +mityarm335x MACH_MITYARM335X MITYARM335X 3903 +xcgz7x MACH_XCGZ7X XCGZ7X 3904 +cubox MACH_CUBOX CUBOX 3905 +terminator MACH_TERMINATOR TERMINATOR 3906 +eye03 MACH_EYE03 EYE03 3907 +kota3 MACH_KOTA3 KOTA3 3908 +pscpe MACH_PSCPE PSCPE 3910 +akt1100 MACH_AKT1100 AKT1100 3911 +pcaaxl2 MACH_PCAAXL2 PCAAXL2 3912 +primodd_ct MACH_PRIMODD_CT PRIMODD_CT 3913 +nsbc MACH_NSBC NSBC 3914 +meson2_skt MACH_MESON2_SKT MESON2_SKT 3915 +meson2_ref MACH_MESON2_REF MESON2_REF 3916 +ccardwmx28js MACH_CCARDWMX28JS CCARDWMX28JS 3917 +ccardmx28js MACH_CCARDMX28JS CCARDMX28JS 3918 +indico MACH_INDICO INDICO 3919 +msm8960dt MACH_MSM8960DT MSM8960DT 3920 +primods MACH_PRIMODS PRIMODS 3921 +beluga_m1388 MACH_BELUGA_M1388 BELUGA_M1388 3922 +primotd MACH_PRIMOTD PRIMOTD 3923 +varan_master MACH_VARAN_MASTER VARAN_MASTER 3924 +primodd MACH_PRIMODD PRIMODD 3925 +jetduo MACH_JETDUO JETDUO 3926 +mx53_umobo MACH_MX53_UMOBO MX53_UMOBO 3927 +trats MACH_TRATS TRATS 3928 +starcraft MACH_STARCRAFT STARCRAFT 3929 +qseven_tegra2 MACH_QSEVEN_TEGRA2 QSEVEN_TEGRA2 3930 +lichee_sun4i_devbd MACH_LICHEE_SUN4I_DEVBD LICHEE_SUN4I_DEVBD 3931 +movenow MACH_MOVENOW MOVENOW 3932 +golf_u MACH_GOLF_U GOLF_U 3933 +msm7627a_evb MACH_MSM7627A_EVB MSM7627A_EVB 3934 +rambo MACH_RAMBO RAMBO 3935 +golfu MACH_GOLFU GOLFU 3936 +mango310 MACH_MANGO310 MANGO310 3937 +dns343 MACH_DNS343 DNS343 3938 +var_som_om44 MACH_VAR_SOM_OM44 VAR_SOM_OM44 3939 +naon MACH_NAON NAON 3940 +vp4000 MACH_VP4000 VP4000 3941 +impcard MACH_IMPCARD IMPCARD 3942 +smoovcam MACH_SMOOVCAM SMOOVCAM 3943 +cobham3725 MACH_COBHAM3725 COBHAM3725 3944 +cobham3730 MACH_COBHAM3730 COBHAM3730 3945 +cobham3703 MACH_COBHAM3703 COBHAM3703 3946 +quetzal MACH_QUETZAL QUETZAL 3947 +apq8064_cdp MACH_APQ8064_CDP APQ8064_CDP 3948 +apq8064_mtp MACH_APQ8064_MTP APQ8064_MTP 3949 +apq8064_fluid MACH_APQ8064_FLUID APQ8064_FLUID 3950 +apq8064_liquid MACH_APQ8064_LIQUID APQ8064_LIQUID 3951 +mango210 MACH_MANGO210 MANGO210 3952 +mango100 MACH_MANGO100 MANGO100 3953 +mango24 MACH_MANGO24 MANGO24 3954 +mango64 MACH_MANGO64 MANGO64 3955 +nsa320 MACH_NSA320 NSA320 3956 +elv_ccu2 MACH_ELV_CCU2 ELV_CCU2 3957 +triton_x00 MACH_TRITON_X00 TRITON_X00 3958 +triton_1500_2000 MACH_TRITON_1500_2000 TRITON_1500_2000 3959 +pogoplugv4 MACH_POGOPLUGV4 POGOPLUGV4 3960 +venus_cl MACH_VENUS_CL VENUS_CL 3961 +vulcano_g20 MACH_VULCANO_G20 VULCANO_G20 3962 +sgs_i9100 MACH_SGS_I9100 SGS_I9100 3963 +stsv2 MACH_STSV2 STSV2 3964 +csb1724 MACH_CSB1724 CSB1724 3965 +omapl138_lcdk MACH_OMAPL138_LCDK OMAPL138_LCDK 3966 +pvd_mx25 MACH_PVD_MX25 PVD_MX25 3968 +meson6_skt MACH_MESON6_SKT MESON6_SKT 3969 +meson6_ref MACH_MESON6_REF MESON6_REF 3970 +pxm MACH_PXM PXM 3971 +pogoplugv3 MACH_POGOPLUGV3 POGOPLUGV3 3973 +mlp89626 MACH_MLP89626 MLP89626 3974 +iomegahmndce MACH_IOMEGAHMNDCE IOMEGAHMNDCE 3975 +pogoplugv3pci MACH_POGOPLUGV3PCI POGOPLUGV3PCI 3976 +bntv250 MACH_BNTV250 BNTV250 3977 +mx53_qseven MACH_MX53_QSEVEN MX53_QSEVEN 3978 +gtl_it1100 MACH_GTL_IT1100 GTL_IT1100 3979 +mx6q_sabresd MACH_MX6Q_SABRESD MX6Q_SABRESD 3980 +mt4 MACH_MT4 MT4 3981 +jumbo_d MACH_JUMBO_D JUMBO_D 3982 +jumbo_i MACH_JUMBO_I JUMBO_I 3983 +fs20_dmp MACH_FS20_DMP FS20_DMP 3984 +dns320 MACH_DNS320 DNS320 3985 +mx28bacos MACH_MX28BACOS MX28BACOS 3986 +tl80 MACH_TL80 TL80 3987 +polatis_nic_1001 MACH_POLATIS_NIC_1001 POLATIS_NIC_1001 3988 +tely MACH_TELY TELY 3989 +u8520 MACH_U8520 U8520 3990 +manta MACH_MANTA MANTA 3991 +mpq8064_cdp MACH_MPQ8064_CDP MPQ8064_CDP 3993 +mpq8064_dtv MACH_MPQ8064_DTV MPQ8064_DTV 3995 +dm368som MACH_DM368SOM DM368SOM 3996 +gprisb2 MACH_GPRISB2 GPRISB2 3997 +chammid MACH_CHAMMID CHAMMID 3998 +seoul2 MACH_SEOUL2 SEOUL2 3999 +omap4_nooktablet MACH_OMAP4_NOOKTABLET OMAP4_NOOKTABLET 4000 +aalto MACH_AALTO AALTO 4001 +metro MACH_METRO METRO 4002 +cydm3730 MACH_CYDM3730 CYDM3730 4003 +tqma53 MACH_TQMA53 TQMA53 4004 +msm7627a_qrd3 MACH_MSM7627A_QRD3 MSM7627A_QRD3 4005 +mx28_canby MACH_MX28_CANBY MX28_CANBY 4006 +tiger MACH_TIGER TIGER 4007 +pcats_9307_type_a MACH_PCATS_9307_TYPE_A PCATS_9307_TYPE_A 4008 +pcats_9307_type_o MACH_PCATS_9307_TYPE_O PCATS_9307_TYPE_O 4009 +pcats_9307_type_r MACH_PCATS_9307_TYPE_R PCATS_9307_TYPE_R 4010 +streamplug MACH_STREAMPLUG STREAMPLUG 4011 +icechicken_dev MACH_ICECHICKEN_DEV ICECHICKEN_DEV 4012 +hedgehog MACH_HEDGEHOG HEDGEHOG 4013 +yusend_obc MACH_YUSEND_OBC YUSEND_OBC 4014 +imxninja MACH_IMXNINJA IMXNINJA 4015 +omap4_jarod MACH_OMAP4_JAROD OMAP4_JAROD 4016 +eco5_pk MACH_ECO5_PK ECO5_PK 4017 +qj2440 MACH_QJ2440 QJ2440 4018 +mx6q_mercury MACH_MX6Q_MERCURY MX6Q_MERCURY 4019 +cm6810 MACH_CM6810 CM6810 4020 +omap4_torpedo MACH_OMAP4_TORPEDO OMAP4_TORPEDO 4021 +nsa310 MACH_NSA310 NSA310 4022 +tmx536 MACH_TMX536 TMX536 4023 +ktt20 MACH_KTT20 KTT20 4024 +dragonix MACH_DRAGONIX DRAGONIX 4025 +lungching MACH_LUNGCHING LUNGCHING 4026 +bulogics MACH_BULOGICS BULOGICS 4027 +mx535_sx MACH_MX535_SX MX535_SX 4028 +ngui3250 MACH_NGUI3250 NGUI3250 4029 +salutec_dac MACH_SALUTEC_DAC SALUTEC_DAC 4030 +loco MACH_LOCO LOCO 4031 +ctera_plug_usi MACH_CTERA_PLUG_USI CTERA_PLUG_USI 4032 +scepter MACH_SCEPTER SCEPTER 4033 +sga MACH_SGA SGA 4034 +p_81_j5 MACH_P_81_J5 P_81_J5 4035 +p_81_o4 MACH_P_81_O4 P_81_O4 4036 +msm8625_surf MACH_MSM8625_SURF MSM8625_SURF 4037 +carallon_shark MACH_CARALLON_SHARK CARALLON_SHARK 4038 +ordog MACH_ORDOG ORDOG 4040 +puente_io MACH_PUENTE_IO PUENTE_IO 4041 +msm8625_evb MACH_MSM8625_EVB MSM8625_EVB 4042 +ev_am1707 MACH_EV_AM1707 EV_AM1707 4043 +ev_am1707e2 MACH_EV_AM1707E2 EV_AM1707E2 4044 +ev_am3517e2 MACH_EV_AM3517E2 EV_AM3517E2 4045 +calabria MACH_CALABRIA CALABRIA 4046 +ev_imx287 MACH_EV_IMX287 EV_IMX287 4047 +erau MACH_ERAU ERAU 4048 +sichuan MACH_SICHUAN SICHUAN 4049 +davinci_da850 MACH_DAVINCI_DA850 DAVINCI_DA850 4051 +omap138_trunarc MACH_OMAP138_TRUNARC OMAP138_TRUNARC 4052 +bcm4761 MACH_BCM4761 BCM4761 4053 +picasso_e2 MACH_PICASSO_E2 PICASSO_E2 4054 +picasso_mf MACH_PICASSO_MF PICASSO_MF 4055 +miro MACH_MIRO MIRO 4056 +at91sam9g20ewon3 MACH_AT91SAM9G20EWON3 AT91SAM9G20EWON3 4057 +yoyo MACH_YOYO YOYO 4058 +windjkl MACH_WINDJKL WINDJKL 4059 +monarudo MACH_MONARUDO MONARUDO 4060 +batan MACH_BATAN BATAN 4061 +tadao MACH_TADAO TADAO 4062 +baso MACH_BASO BASO 4063 +mahon MACH_MAHON MAHON 4064 +villec2 MACH_VILLEC2 VILLEC2 4065 +asi1230 MACH_ASI1230 ASI1230 4066 +alaska MACH_ALASKA ALASKA 4067 +swarco_shdsl2 MACH_SWARCO_SHDSL2 SWARCO_SHDSL2 4068 +oxrtu MACH_OXRTU OXRTU 4069 +omap5_panda MACH_OMAP5_PANDA OMAP5_PANDA 4070 +c8000 MACH_C8000 C8000 4072 +bje_display3_5 MACH_BJE_DISPLAY3_5 BJE_DISPLAY3_5 4073 +picomod7 MACH_PICOMOD7 PICOMOD7 4074 +picocom5 MACH_PICOCOM5 PICOCOM5 4075 +qblissa8 MACH_QBLISSA8 QBLISSA8 4076 +armstonea8 MACH_ARMSTONEA8 ARMSTONEA8 4077 +netdcu14 MACH_NETDCU14 NETDCU14 4078 +at91sam9x5_epiphan MACH_AT91SAM9X5_EPIPHAN AT91SAM9X5_EPIPHAN 4079 +p2u MACH_P2U P2U 4080 +doris MACH_DORIS DORIS 4081 +j49 MACH_J49 J49 4082 +vdss2e MACH_VDSS2E VDSS2E 4083 +vc300 MACH_VC300 VC300 4084 +ns115_pad_test MACH_NS115_PAD_TEST NS115_PAD_TEST 4085 +ns115_pad_ref MACH_NS115_PAD_REF NS115_PAD_REF 4086 +ns115_phone_test MACH_NS115_PHONE_TEST NS115_PHONE_TEST 4087 +ns115_phone_ref MACH_NS115_PHONE_REF NS115_PHONE_REF 4088 +golfc MACH_GOLFC GOLFC 4089 +xerox_olympus MACH_XEROX_OLYMPUS XEROX_OLYMPUS 4090 +mx6sl_arm2 MACH_MX6SL_ARM2 MX6SL_ARM2 4091 +csb1701_csb1726 MACH_CSB1701_CSB1726 CSB1701_CSB1726 4092 +at91sam9xeek MACH_AT91SAM9XEEK AT91SAM9XEEK 4093 +ebv210 MACH_EBV210 EBV210 4094 +msm7627a_qrd7 MACH_MSM7627A_QRD7 MSM7627A_QRD7 4095 +svthin MACH_SVTHIN SVTHIN 4096 +duovero MACH_DUOVERO DUOVERO 4097 +chupacabra MACH_CHUPACABRA CHUPACABRA 4098 +scorpion MACH_SCORPION SCORPION 4099 +davinci_he_hmi10 MACH_DAVINCI_HE_HMI10 DAVINCI_HE_HMI10 4100 +topkick MACH_TOPKICK TOPKICK 4101 +m3_auguestrush MACH_M3_AUGUESTRUSH M3_AUGUESTRUSH 4102 +ipc335x MACH_IPC335X IPC335X 4103 +sun4i MACH_SUN4I SUN4I 4104 +imx233_olinuxino MACH_IMX233_OLINUXINO IMX233_OLINUXINO 4105 +k2_wl MACH_K2_WL K2_WL 4106 +k2_ul MACH_K2_UL K2_UL 4107 +k2_cl MACH_K2_CL K2_CL 4108 +minbari_w MACH_MINBARI_W MINBARI_W 4109 +minbari_m MACH_MINBARI_M MINBARI_M 4110 +k035 MACH_K035 K035 4111 +ariel MACH_ARIEL ARIEL 4112 +arielsaarc MACH_ARIELSAARC ARIELSAARC 4113 +arieldkb MACH_ARIELDKB ARIELDKB 4114 +armadillo810 MACH_ARMADILLO810 ARMADILLO810 4115 +tam335x MACH_TAM335X TAM335X 4116 +grouper MACH_GROUPER GROUPER 4117 +mpcsa21_9g20 MACH_MPCSA21_9G20 MPCSA21_9G20 4118 +m6u_cpu MACH_M6U_CPU M6U_CPU 4119 +davinci_dp10 MACH_DAVINCI_DP10 DAVINCI_DP10 4120 +ginkgo MACH_GINKGO GINKGO 4121 +cgt_qmx6 MACH_CGT_QMX6 CGT_QMX6 4122 +profpga MACH_PROFPGA PROFPGA 4123 +acfx100oc MACH_ACFX100OC ACFX100OC 4124 +acfx100nb MACH_ACFX100NB ACFX100NB 4125 +capricorn MACH_CAPRICORN CAPRICORN 4126 +pisces MACH_PISCES PISCES 4127 +aries MACH_ARIES ARIES 4128 +cancer MACH_CANCER CANCER 4129 +leo MACH_LEO LEO 4130 +virgo MACH_VIRGO VIRGO 4131 +sagittarius MACH_SAGITTARIUS SAGITTARIUS 4132 +devil MACH_DEVIL DEVIL 4133 +ballantines MACH_BALLANTINES BALLANTINES 4134 +omap3_procerusvpu MACH_OMAP3_PROCERUSVPU OMAP3_PROCERUSVPU 4135 +my27 MACH_MY27 MY27 4136 +sun6i MACH_SUN6I SUN6I 4137 +sun5i MACH_SUN5I SUN5I 4138 +mx512_mx MACH_MX512_MX MX512_MX 4139 +kzm9g MACH_KZM9G KZM9G 4140 +vdstbn MACH_VDSTBN VDSTBN 4141 +cfa10036 MACH_CFA10036 CFA10036 4142 +cfa10049 MACH_CFA10049 CFA10049 4143 +pcm051 MACH_PCM051 PCM051 4144 +vybrid_vf7xx MACH_VYBRID_VF7XX VYBRID_VF7XX 4145 +vybrid_vf6xx MACH_VYBRID_VF6XX VYBRID_VF6XX 4146 +vybrid_vf5xx MACH_VYBRID_VF5XX VYBRID_VF5XX 4147 +vybrid_vf4xx MACH_VYBRID_VF4XX VYBRID_VF4XX 4148 +aria_g25 MACH_ARIA_G25 ARIA_G25 4149 +bcm21553 MACH_BCM21553 BCM21553 4150 +smdk5410 MACH_SMDK5410 SMDK5410 4151 +lpc18xx MACH_LPC18XX LPC18XX 4152 +oratisparty MACH_ORATISPARTY ORATISPARTY 4153 +qseven MACH_QSEVEN QSEVEN 4154 +gmv_generic MACH_GMV_GENERIC GMV_GENERIC 4155 +th_link_eth MACH_TH_LINK_ETH TH_LINK_ETH 4156 +tn_muninn MACH_TN_MUNINN TN_MUNINN 4157 +rampage MACH_RAMPAGE RAMPAGE 4158 +visstrim_mv10 MACH_VISSTRIM_MV10 VISSTRIM_MV10 4159 +mx28_wilma MACH_MX28_WILMA MX28_WILMA 4164 +msm8625_ffa MACH_MSM8625_FFA MSM8625_FFA 4166 +vpu101 MACH_VPU101 VPU101 4167 +baileys MACH_BAILEYS BAILEYS 4169 +familybox MACH_FAMILYBOX FAMILYBOX 4170 +ensemble_mx35 MACH_ENSEMBLE_MX35 ENSEMBLE_MX35 4171 +sc_sps_1 MACH_SC_SPS_1 SC_SPS_1 4172 diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c index 858748eaa144..586961929e96 100644 --- a/arch/arm/vfp/vfpmodule.c +++ b/arch/arm/vfp/vfpmodule.c @@ -11,12 +11,15 @@ #include <linux/types.h> #include <linux/cpu.h> #include <linux/cpu_pm.h> +#include <linux/hardirq.h> #include <linux/kernel.h> #include <linux/notifier.h> #include <linux/signal.h> #include <linux/sched.h> #include <linux/smp.h> #include <linux/init.h> +#include <linux/uaccess.h> +#include <linux/user.h> #include <asm/cp15.h> #include <asm/cputype.h> @@ -238,11 +241,11 @@ static void vfp_panic(char *reason, u32 inst) { int i; - printk(KERN_ERR "VFP: Error: %s\n", reason); - printk(KERN_ERR "VFP: EXC 0x%08x SCR 0x%08x INST 0x%08x\n", + pr_err("VFP: Error: %s\n", reason); + pr_err("VFP: EXC 0x%08x SCR 0x%08x INST 0x%08x\n", fmrx(FPEXC), fmrx(FPSCR), inst); for (i = 0; i < 32; i += 2) - printk(KERN_ERR "VFP: s%2u: 0x%08x s%2u: 0x%08x\n", + pr_err("VFP: s%2u: 0x%08x s%2u: 0x%08x\n", i, vfp_get_float(i), i+1, vfp_get_float(i+1)); } @@ -430,7 +433,10 @@ void VFP_bounce(u32 trigger, u32 fpexc, struct pt_regs *regs) static void vfp_enable(void *unused) { - u32 access = get_copro_access(); + u32 access; + + BUG_ON(preemptible()); + access = get_copro_access(); /* * Enable full access to VFP (cp10 and cp11) @@ -446,7 +452,7 @@ static int vfp_pm_suspend(void) /* if vfp is on, then save state for resumption */ if (fpexc & FPEXC_EN) { - printk(KERN_DEBUG "%s: saving vfp state\n", __func__); + pr_debug("%s: saving vfp state\n", __func__); vfp_save_state(&ti->vfpstate, fpexc); /* disable, just in case */ @@ -529,6 +535,93 @@ void vfp_flush_hwstate(struct thread_info *thread) } /* + * Save the current VFP state into the provided structures and prepare + * for entry into a new function (signal handler). + */ +int vfp_preserve_user_clear_hwstate(struct user_vfp __user *ufp, + struct user_vfp_exc __user *ufp_exc) +{ + struct thread_info *thread = current_thread_info(); + struct vfp_hard_struct *hwstate = &thread->vfpstate.hard; + int err = 0; + + /* Ensure that the saved hwstate is up-to-date. */ + vfp_sync_hwstate(thread); + + /* + * Copy the floating point registers. There can be unused + * registers see asm/hwcap.h for details. + */ + err |= __copy_to_user(&ufp->fpregs, &hwstate->fpregs, + sizeof(hwstate->fpregs)); + /* + * Copy the status and control register. + */ + __put_user_error(hwstate->fpscr, &ufp->fpscr, err); + + /* + * Copy the exception registers. + */ + __put_user_error(hwstate->fpexc, &ufp_exc->fpexc, err); + __put_user_error(hwstate->fpinst, &ufp_exc->fpinst, err); + __put_user_error(hwstate->fpinst2, &ufp_exc->fpinst2, err); + + if (err) + return -EFAULT; + + /* Ensure that VFP is disabled. */ + vfp_flush_hwstate(thread); + + /* + * As per the PCS, clear the length and stride bits for function + * entry. + */ + hwstate->fpscr &= ~(FPSCR_LENGTH_MASK | FPSCR_STRIDE_MASK); + return 0; +} + +/* Sanitise and restore the current VFP state from the provided structures. */ +int vfp_restore_user_hwstate(struct user_vfp __user *ufp, + struct user_vfp_exc __user *ufp_exc) +{ + struct thread_info *thread = current_thread_info(); + struct vfp_hard_struct *hwstate = &thread->vfpstate.hard; + unsigned long fpexc; + int err = 0; + + /* Disable VFP to avoid corrupting the new thread state. */ + vfp_flush_hwstate(thread); + + /* + * Copy the floating point registers. There can be unused + * registers see asm/hwcap.h for details. + */ + err |= __copy_from_user(&hwstate->fpregs, &ufp->fpregs, + sizeof(hwstate->fpregs)); + /* + * Copy the status and control register. + */ + __get_user_error(hwstate->fpscr, &ufp->fpscr, err); + + /* + * Sanitise and restore the exception registers. + */ + __get_user_error(fpexc, &ufp_exc->fpexc, err); + + /* Ensure the VFP is enabled. */ + fpexc |= FPEXC_EN; + + /* Ensure FPINST2 is invalid and the exception flag is cleared. */ + fpexc &= ~(FPEXC_EX | FPEXC_FP2V); + hwstate->fpexc = fpexc; + + __get_user_error(hwstate->fpinst, &ufp_exc->fpinst, err); + __get_user_error(hwstate->fpinst2, &ufp_exc->fpinst2, err); + + return err ? -EFAULT : 0; +} + +/* * VFP hardware can lose all context when a CPU goes offline. * As we will be running in SMP mode with CPU hotplug, we will save the * hardware state at every thread switch. We clear our held state when @@ -558,7 +651,7 @@ static int __init vfp_init(void) unsigned int cpu_arch = cpu_architecture(); if (cpu_arch >= CPU_ARCH_ARMv6) - vfp_enable(NULL); + on_each_cpu(vfp_enable, NULL, 1); /* * First check that there is a VFP that we can use. @@ -571,18 +664,16 @@ static int __init vfp_init(void) barrier(); vfp_vector = vfp_null_entry; - printk(KERN_INFO "VFP support v0.3: "); + pr_info("VFP support v0.3: "); if (VFP_arch) - printk("not present\n"); + pr_cont("not present\n"); else if (vfpsid & FPSID_NODOUBLE) { - printk("no double precision support\n"); + pr_cont("no double precision support\n"); } else { hotcpu_notifier(vfp_hotplug, 0); - smp_call_function(vfp_enable, NULL, 1); - VFP_arch = (vfpsid & FPSID_ARCH_MASK) >> FPSID_ARCH_BIT; /* Extract the architecture version */ - printk("implementor %02x architecture %d part %02x variant %x rev %x\n", + pr_cont("implementor %02x architecture %d part %02x variant %x rev %x\n", (vfpsid & FPSID_IMPLEMENTER_MASK) >> FPSID_IMPLEMENTER_BIT, (vfpsid & FPSID_ARCH_MASK) >> FPSID_ARCH_BIT, (vfpsid & FPSID_PART_MASK) >> FPSID_PART_BIT, diff --git a/arch/blackfin/ADI_BSD.txt b/arch/blackfin/ADI_BSD.txt deleted file mode 100644 index 501d0b645943..000000000000 --- a/arch/blackfin/ADI_BSD.txt +++ /dev/null @@ -1,41 +0,0 @@ -This BSD-Style License applies to a few files in ./arch/blackfin directory, -and is included here, so people understand which code they can use outside -the Linux kernel, in non-GPL based projects. - -Using the files released under the "ADI BSD" license, must comply with -these license terms. - --------------------------------------------------------------------------- - -Copyright Analog Devices, Inc. - -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions -are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - Neither the name of Analog Devices, Inc. nor the names of its - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - The use of this software may or may not infringe the patent rights - of one or more patent holders. This license does not release you - from the requirement that you obtain separate licenses from these - patent holders to use this software. - -THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR -IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, -MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, -INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -BUT NOT LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF -SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR -OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -ADVISED OF THE POSSIBILITY OF SUCH DAMAGE diff --git a/arch/blackfin/Clear_BSD.txt b/arch/blackfin/Clear_BSD.txt new file mode 100644 index 000000000000..bfa4b378a368 --- /dev/null +++ b/arch/blackfin/Clear_BSD.txt @@ -0,0 +1,33 @@ +The Clear BSD license: + +Copyright (c) 2012, Analog Devices, Inc. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted (subject to the limitations in the +disclaimer below) provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the + distribution. + +* Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + +NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index 373a6902d8fa..383e7ecda923 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -226,6 +226,12 @@ config BF561 help BF561 Processor Support. +config BF609 + bool "BF609" + select CLKDEV_LOOKUP + help + BF609 Processor Support. + endchoice config SMP @@ -251,27 +257,27 @@ config HOTPLUG_CPU config BF_REV_MIN int - default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) + default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x default 2 if (BF537 || BF536 || BF534) default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM) default 4 if (BF538 || BF539) config BF_REV_MAX int - default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) + default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x default 3 if (BF537 || BF536 || BF534 || BF54xM) default 5 if (BF561 || BF538 || BF539) default 6 if (BF533 || BF532 || BF531) choice prompt "Silicon Rev" - default BF_REV_0_0 if (BF51x || BF52x) + default BF_REV_0_0 if (BF51x || BF52x || BF60x) default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM)) default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561) config BF_REV_0_0 bool "0.0" - depends on (BF51x || BF52x || (BF54x && !BF54xM)) + depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x) config BF_REV_0_1 bool "0.1" @@ -350,6 +356,7 @@ source "arch/blackfin/mach-bf561/Kconfig" source "arch/blackfin/mach-bf537/Kconfig" source "arch/blackfin/mach-bf538/Kconfig" source "arch/blackfin/mach-bf548/Kconfig" +source "arch/blackfin/mach-bf609/Kconfig" menu "Board customizations" @@ -379,6 +386,12 @@ config BOOT_LOAD memory region is used to capture NULL pointer references as well as some core kernel functions. +config PHY_RAM_BASE_ADDRESS + hex "Physical RAM Base" + default 0x0 + help + set BF609 FPGA physical SRAM base address + config ROM_BASE hex "Kernel ROM Base" depends on ROMKERNEL @@ -422,7 +435,7 @@ config BFIN_KERNEL_CLOCK config PLL_BYPASS bool "Bypass PLL" - depends on BFIN_KERNEL_CLOCK + depends on BFIN_KERNEL_CLOCK && (!BF60x) default n config CLKIN_HALF @@ -441,7 +454,7 @@ config VCO_MULT default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT) default "22" if BFIN533_BLUETECHNIX_CM default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM) - default "20" if BFIN561_EZKIT + default "20" if (BFIN561_EZKIT || BF609) default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD) default "25" if BFIN527_AD7160EVAL help @@ -473,12 +486,45 @@ config SCLK_DIV int "System Clock Divider" depends on BFIN_KERNEL_CLOCK range 1 15 - default 5 + default 4 help - This sets the frequency of the system clock (including SDRAM or DDR). + This sets the frequency of the system clock (including SDRAM or DDR) on + !BF60x else it set the clock for system buses and provides the + source from which SCLK0 and SCLK1 are derived. This can be between 1 and 15 System Clock = (PLL frequency) / (this setting) +config SCLK0_DIV + int "System Clock0 Divider" + depends on BFIN_KERNEL_CLOCK && BF60x + range 1 15 + default 1 + help + This sets the frequency of the system clock0 for PVP and all other + peripherals not clocked by SCLK1. + This can be between 1 and 15 + System Clock0 = (System Clock) / (this setting) + +config SCLK1_DIV + int "System Clock1 Divider" + depends on BFIN_KERNEL_CLOCK && BF60x + range 1 15 + default 1 + help + This sets the frequency of the system clock1 (including SPORT, SPI and ACM). + This can be between 1 and 15 + System Clock1 = (System Clock) / (this setting) + +config DCLK_DIV + int "DDR Clock Divider" + depends on BFIN_KERNEL_CLOCK && BF60x + range 1 15 + default 2 + help + This sets the frequency of the DDR memory. + This can be between 1 and 15 + DDR Clock = (PLL frequency) / (this setting) + choice prompt "DDR SDRAM Chip Type" depends on BFIN_KERNEL_CLOCK @@ -494,7 +540,7 @@ endchoice choice prompt "DDR/SDRAM Timing" - depends on BFIN_KERNEL_CLOCK + depends on BFIN_KERNEL_CLOCK && !BF60x default BFIN_KERNEL_CLOCK_MEMINIT_CALC help This option allows you to specify Blackfin SDRAM/DDR Timing parameters @@ -576,6 +622,7 @@ config MAX_VCO_HZ default 600000000 if BF548 default 533333333 if BF549 default 600000000 if BF561 + default 800000000 if BF609 config MIN_VCO_HZ int @@ -583,6 +630,7 @@ config MIN_VCO_HZ config MAX_SCLK_HZ int + default 200000000 if BF609 default 133333333 config MIN_SCLK_HZ @@ -1051,7 +1099,7 @@ endchoice config BFIN_L2_DCACHEABLE bool "Enable DCACHE for L2 SRAM" depends on BFIN_DCACHE - depends on (BF54x || BF561) && !SMP + depends on (BF54x || BF561 || BF60x) && !SMP default n choice prompt "L2 SRAM DCACHE policy" @@ -1077,6 +1125,7 @@ config MPU comment "Asynchronous Memory Configuration" menu "EBIU_AMGCTL Global Control" + depends on !BF60x config C_AMCKEN bool "Enable CLKOUT" default y @@ -1127,6 +1176,7 @@ endchoice endmenu menu "EBIU_AMBCTL Control" + depends on !BF60x config BANK_0 hex "Bank 0 (AMBCTL0.L)" default 0x7BB0 @@ -1206,7 +1256,7 @@ config ARCH_SUSPEND_POSSIBLE choice prompt "Standby Power Saving Mode" - depends on PM + depends on PM && !BF60x default PM_BFIN_SLEEP_DEEPER config PM_BFIN_SLEEP_DEEPER bool "Sleep Deeper" @@ -1261,6 +1311,118 @@ config PM_BFIN_WAKE_GP On ADSP-BF549 this option enables the the same functionality on the /MRXON pin also PH7. +config PM_BFIN_WAKE_PA15 + bool "Allow Wake-Up from PA15" + depends on PM && BF60x + default n + help + Enable PA15 Wake-Up + +config PM_BFIN_WAKE_PA15_POL + int "Wake-up priority" + depends on PM_BFIN_WAKE_PA15 + default 0 + help + Wake-Up priority 0(low) 1(high) + +config PM_BFIN_WAKE_PB15 + bool "Allow Wake-Up from PB15" + depends on PM && BF60x + default n + help + Enable PB15 Wake-Up + +config PM_BFIN_WAKE_PB15_POL + int "Wake-up priority" + depends on PM_BFIN_WAKE_PB15 + default 0 + help + Wake-Up priority 0(low) 1(high) + +config PM_BFIN_WAKE_PC15 + bool "Allow Wake-Up from PC15" + depends on PM && BF60x + default n + help + Enable PC15 Wake-Up + +config PM_BFIN_WAKE_PC15_POL + int "Wake-up priority" + depends on PM_BFIN_WAKE_PC15 + default 0 + help + Wake-Up priority 0(low) 1(high) + +config PM_BFIN_WAKE_PD06 + bool "Allow Wake-Up from PD06(ETH0_PHYINT)" + depends on PM && BF60x + default n + help + Enable PD06(ETH0_PHYINT) Wake-up + +config PM_BFIN_WAKE_PD06_POL + int "Wake-up priority" + depends on PM_BFIN_WAKE_PD06 + default 0 + help + Wake-Up priority 0(low) 1(high) + +config PM_BFIN_WAKE_PE12 + bool "Allow Wake-Up from PE12(ETH1_PHYINT, PUSH BUTTON)" + depends on PM && BF60x + default n + help + Enable PE12(ETH1_PHYINT, PUSH BUTTON) Wake-up + +config PM_BFIN_WAKE_PE12_POL + int "Wake-up priority" + depends on PM_BFIN_WAKE_PE12 + default 0 + help + Wake-Up priority 0(low) 1(high) + +config PM_BFIN_WAKE_PG04 + bool "Allow Wake-Up from PG04(CAN0_RX)" + depends on PM && BF60x + default n + help + Enable PG04(CAN0_RX) Wake-up + +config PM_BFIN_WAKE_PG04_POL + int "Wake-up priority" + depends on PM_BFIN_WAKE_PG04 + default 0 + help + Wake-Up priority 0(low) 1(high) + +config PM_BFIN_WAKE_PG13 + bool "Allow Wake-Up from PG13" + depends on PM && BF60x + default n + help + Enable PG13 Wake-Up + +config PM_BFIN_WAKE_PG13_POL + int "Wake-up priority" + depends on PM_BFIN_WAKE_PG13 + default 0 + help + Wake-Up priority 0(low) 1(high) + +config PM_BFIN_WAKE_USB + bool "Allow Wake-Up from (USB)" + depends on PM && BF60x + default n + help + Enable (USB) Wake-up + +config PM_BFIN_WAKE_USB_POL + int "Wake-up priority" + depends on PM_BFIN_WAKE_USB + default 0 + help + Wake-Up priority 0(low) 1(high) + endmenu menu "CPU Frequency scaling" diff --git a/arch/blackfin/Kconfig.debug b/arch/blackfin/Kconfig.debug index e2a3d4c8ab9a..79594694ee90 100644 --- a/arch/blackfin/Kconfig.debug +++ b/arch/blackfin/Kconfig.debug @@ -253,4 +253,11 @@ config BFIN_PSEUDODBG_INSNS Most people should say N here. +config BFIN_PM_WAKEUP_TIME_BENCH + bool "Display the total time for kernel to resume from power saving mode" + default n + help + Display the total time when kernel resumes normal from standby or + suspend to mem mode. + endmenu diff --git a/arch/blackfin/Makefile b/arch/blackfin/Makefile index 46f42b2066e5..74fdf679da01 100644 --- a/arch/blackfin/Makefile +++ b/arch/blackfin/Makefile @@ -54,6 +54,7 @@ machine-$(CONFIG_BF548M) := bf548 machine-$(CONFIG_BF549) := bf548 machine-$(CONFIG_BF549M) := bf548 machine-$(CONFIG_BF561) := bf561 +machine-$(CONFIG_BF609) := bf609 MACHINE := $(machine-y) export MACHINE @@ -86,6 +87,7 @@ cpu-$(CONFIG_BF548M) := bf548m cpu-$(CONFIG_BF549) := bf549 cpu-$(CONFIG_BF549M) := bf549m cpu-$(CONFIG_BF561) := bf561 +cpu-$(CONFIG_BF609) := bf609 rev-$(CONFIG_BF_REV_0_0) := 0.0 rev-$(CONFIG_BF_REV_0_1) := 0.1 diff --git a/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig b/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig index 680730eeaf23..e2a2fa5935ce 100644 --- a/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig +++ b/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig @@ -21,14 +21,12 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_IOSCHED_CFQ is not set CONFIG_PREEMPT_VOLUNTARY=y CONFIG_BF561=y +CONFIG_SMP=y CONFIG_IRQ_TIMER0=10 CONFIG_CLKIN_HZ=30000000 CONFIG_HIGH_RES_TIMERS=y CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 CONFIG_BFIN_GPTIMERS=m -CONFIG_BFIN_EXTMEM_WRITETHROUGH=y -CONFIG_BFIN_L2_DCACHEABLE=y -CONFIG_BFIN_L2_WRITETHROUGH=y CONFIG_C_CDPRIO=y CONFIG_BANK_3=0xAAC2 CONFIG_BINFMT_FLAT=y diff --git a/arch/blackfin/configs/BF609-EZKIT_defconfig b/arch/blackfin/configs/BF609-EZKIT_defconfig new file mode 100644 index 000000000000..be9526bee4fb --- /dev/null +++ b/arch/blackfin/configs/BF609-EZKIT_defconfig @@ -0,0 +1,155 @@ +CONFIG_EXPERIMENTAL=y +CONFIG_SYSVIPC=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_BLK_DEV_INITRD=y +CONFIG_EXPERT=y +# CONFIG_ELF_CORE is not set +# CONFIG_FUTEX is not set +# CONFIG_SIGNALFD is not set +# CONFIG_TIMERFD is not set +# CONFIG_EVENTFD is not set +# CONFIG_AIO is not set +CONFIG_SLAB=y +CONFIG_MMAP_ALLOW_UNINITIALIZED=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_PREEMPT_VOLUNTARY=y +CONFIG_BF609=y +CONFIG_PINT1_ASSIGN=0x01010000 +CONFIG_PINT2_ASSIGN=0x07000101 +CONFIG_PINT3_ASSIGN=0x02020303 +CONFIG_HIGH_RES_TIMERS=y +CONFIG_IP_CHECKSUM_L1=y +CONFIG_SYSCALL_TAB_L1=y +CONFIG_CPLB_SWITCH_TAB_L1=y +# CONFIG_APP_STACK_L1 is not set +# CONFIG_BFIN_INS_LOWOVERHEAD is not set +CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 +CONFIG_BINFMT_FLAT=y +CONFIG_BINFMT_ZFLAT=y +CONFIG_PM_BFIN_WAKE_PE12=y +CONFIG_PM_BFIN_WAKE_PE12_POL=1 +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +# CONFIG_IPV6 is not set +CONFIG_NETFILTER=y +CONFIG_CAN=y +CONFIG_CAN_BFIN=y +CONFIG_IRDA=y +CONFIG_IRTTY_SIR=y +# CONFIG_WIRELESS is not set +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_FW_LOADER=m +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_COMPLEX_MAPPINGS=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_UBI=m +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_NETDEVICES=y +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +CONFIG_STMMAC_ETH=y +CONFIG_STMMAC_IEEE1588=y +# CONFIG_WLAN is not set +# CONFIG_INPUT_MOUSEDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_MISC=y +CONFIG_INPUT_BFIN_ROTARY=y +# CONFIG_SERIO is not set +# CONFIG_LEGACY_PTYS is not set +CONFIG_BFIN_SIMPLE_TIMER=m +CONFIG_BFIN_LINKPORT=y +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_BFIN=y +CONFIG_SERIAL_BFIN_CONSOLE=y +CONFIG_SERIAL_BFIN_UART0=y +# CONFIG_HW_RANDOM is not set +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_BLACKFIN_TWI=y +CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100 +CONFIG_SPI=y +CONFIG_SPI_BFIN6XX=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y +# CONFIG_HWMON is not set +CONFIG_WATCHDOG=y +CONFIG_BFIN_WDT=y +CONFIG_SOUND=m +CONFIG_SND=m +CONFIG_SND_MIXER_OSS=m +CONFIG_SND_PCM_OSS=m +# CONFIG_SND_DRIVERS is not set +# CONFIG_SND_SPI is not set +# CONFIG_SND_USB is not set +CONFIG_SND_SOC=m +CONFIG_SND_BF6XX_I2S=m +CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61=m +CONFIG_SND_SOC_ALL_CODECS=m +CONFIG_USB=y +CONFIG_USB_MUSB_HDRC=y +CONFIG_USB_MUSB_BLACKFIN=m +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MUSB_HDRC=y +CONFIG_USB_ZERO=y +CONFIG_MMC=y +CONFIG_SDH_BFIN=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_EXT2_FS=y +# CONFIG_DNOTIFY is not set +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_JFFS2_FS=m +CONFIG_UBIFS_FS=m +CONFIG_NFS_FS=m +CONFIG_NFS_V3=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +CONFIG_DEBUG_FS=y +CONFIG_DEBUG_SHIRQ=y +CONFIG_DETECT_HUNG_TASK=y +CONFIG_DEBUG_INFO=y +CONFIG_FRAME_POINTER=y +# CONFIG_FTRACE is not set +CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y +CONFIG_EARLY_PRINTK=y +CONFIG_CPLB_INFO=y +CONFIG_BFIN_PSEUDODBG_INSNS=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_ANSI_CPRNG is not set diff --git a/arch/blackfin/include/asm/bfin-global.h b/arch/blackfin/include/asm/bfin-global.h index 17bcbf60bcae..608be5e6d25c 100644 --- a/arch/blackfin/include/asm/bfin-global.h +++ b/arch/blackfin/include/asm/bfin-global.h @@ -35,6 +35,11 @@ extern void bfin_setup_cpudata(unsigned int cpu); extern unsigned long get_cclk(void); extern unsigned long get_sclk(void); +#ifdef CONFIG_BF60x +extern unsigned long get_sclk0(void); +extern unsigned long get_sclk1(void); +extern unsigned long get_dclk(void); +#endif extern unsigned long sclk_to_usecs(unsigned long sclk); extern unsigned long usecs_to_sclk(unsigned long usecs); diff --git a/arch/blackfin/include/asm/bfin6xx_spi.h b/arch/blackfin/include/asm/bfin6xx_spi.h new file mode 100644 index 000000000000..89370b653dcd --- /dev/null +++ b/arch/blackfin/include/asm/bfin6xx_spi.h @@ -0,0 +1,258 @@ +/* + * Analog Devices SPI3 controller driver + * + * Copyright (c) 2011 Analog Devices Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef _SPI_CHANNEL_H_ +#define _SPI_CHANNEL_H_ + +#include <linux/types.h> + +/* SPI_CONTROL */ +#define SPI_CTL_EN 0x00000001 /* Enable */ +#define SPI_CTL_MSTR 0x00000002 /* Master/Slave */ +#define SPI_CTL_PSSE 0x00000004 /* controls modf error in master mode */ +#define SPI_CTL_ODM 0x00000008 /* Open Drain Mode */ +#define SPI_CTL_CPHA 0x00000010 /* Clock Phase */ +#define SPI_CTL_CPOL 0x00000020 /* Clock Polarity */ +#define SPI_CTL_ASSEL 0x00000040 /* Slave Select Pin Control */ +#define SPI_CTL_SELST 0x00000080 /* Slave Select Polarity in-between transfers */ +#define SPI_CTL_EMISO 0x00000100 /* Enable MISO */ +#define SPI_CTL_SIZE 0x00000600 /* Word Transfer Size */ +#define SPI_CTL_SIZE08 0x00000000 /* SIZE: 8 bits */ +#define SPI_CTL_SIZE16 0x00000200 /* SIZE: 16 bits */ +#define SPI_CTL_SIZE32 0x00000400 /* SIZE: 32 bits */ +#define SPI_CTL_LSBF 0x00001000 /* LSB First */ +#define SPI_CTL_FCEN 0x00002000 /* Flow-Control Enable */ +#define SPI_CTL_FCCH 0x00004000 /* Flow-Control Channel Selection */ +#define SPI_CTL_FCPL 0x00008000 /* Flow-Control Polarity */ +#define SPI_CTL_FCWM 0x00030000 /* Flow-Control Water-Mark */ +#define SPI_CTL_FIFO0 0x00000000 /* FCWM: TFIFO empty or RFIFO Full */ +#define SPI_CTL_FIFO1 0x00010000 /* FCWM: TFIFO 75% or more empty or RFIFO 75% or more full */ +#define SPI_CTL_FIFO2 0x00020000 /* FCWM: TFIFO 50% or more empty or RFIFO 50% or more full */ +#define SPI_CTL_FMODE 0x00040000 /* Fast-mode Enable */ +#define SPI_CTL_MIOM 0x00300000 /* Multiple I/O Mode */ +#define SPI_CTL_MIO_DIS 0x00000000 /* MIOM: Disable */ +#define SPI_CTL_MIO_DUAL 0x00100000 /* MIOM: Enable DIOM (Dual I/O Mode) */ +#define SPI_CTL_MIO_QUAD 0x00200000 /* MIOM: Enable QUAD (Quad SPI Mode) */ +#define SPI_CTL_SOSI 0x00400000 /* Start on MOSI */ +/* SPI_RX_CONTROL */ +#define SPI_RXCTL_REN 0x00000001 /* Receive Channel Enable */ +#define SPI_RXCTL_RTI 0x00000004 /* Receive Transfer Initiate */ +#define SPI_RXCTL_RWCEN 0x00000008 /* Receive Word Counter Enable */ +#define SPI_RXCTL_RDR 0x00000070 /* Receive Data Request */ +#define SPI_RXCTL_RDR_DIS 0x00000000 /* RDR: Disabled */ +#define SPI_RXCTL_RDR_NE 0x00000010 /* RDR: RFIFO not empty */ +#define SPI_RXCTL_RDR_25 0x00000020 /* RDR: RFIFO 25% full */ +#define SPI_RXCTL_RDR_50 0x00000030 /* RDR: RFIFO 50% full */ +#define SPI_RXCTL_RDR_75 0x00000040 /* RDR: RFIFO 75% full */ +#define SPI_RXCTL_RDR_FULL 0x00000050 /* RDR: RFIFO full */ +#define SPI_RXCTL_RDO 0x00000100 /* Receive Data Over-Run */ +#define SPI_RXCTL_RRWM 0x00003000 /* FIFO Regular Water-Mark */ +#define SPI_RXCTL_RWM_0 0x00000000 /* RRWM: RFIFO Empty */ +#define SPI_RXCTL_RWM_25 0x00001000 /* RRWM: RFIFO 25% full */ +#define SPI_RXCTL_RWM_50 0x00002000 /* RRWM: RFIFO 50% full */ +#define SPI_RXCTL_RWM_75 0x00003000 /* RRWM: RFIFO 75% full */ +#define SPI_RXCTL_RUWM 0x00070000 /* FIFO Urgent Water-Mark */ +#define SPI_RXCTL_UWM_DIS 0x00000000 /* RUWM: Disabled */ +#define SPI_RXCTL_UWM_25 0x00010000 /* RUWM: RFIFO 25% full */ +#define SPI_RXCTL_UWM_50 0x00020000 /* RUWM: RFIFO 50% full */ +#define SPI_RXCTL_UWM_75 0x00030000 /* RUWM: RFIFO 75% full */ +#define SPI_RXCTL_UWM_FULL 0x00040000 /* RUWM: RFIFO full */ +/* SPI_TX_CONTROL */ +#define SPI_TXCTL_TEN 0x00000001 /* Transmit Channel Enable */ +#define SPI_TXCTL_TTI 0x00000004 /* Transmit Transfer Initiate */ +#define SPI_TXCTL_TWCEN 0x00000008 /* Transmit Word Counter Enable */ +#define SPI_TXCTL_TDR 0x00000070 /* Transmit Data Request */ +#define SPI_TXCTL_TDR_DIS 0x00000000 /* TDR: Disabled */ +#define SPI_TXCTL_TDR_NF 0x00000010 /* TDR: TFIFO not full */ +#define SPI_TXCTL_TDR_25 0x00000020 /* TDR: TFIFO 25% empty */ +#define SPI_TXCTL_TDR_50 0x00000030 /* TDR: TFIFO 50% empty */ +#define SPI_TXCTL_TDR_75 0x00000040 /* TDR: TFIFO 75% empty */ +#define SPI_TXCTL_TDR_EMPTY 0x00000050 /* TDR: TFIFO empty */ +#define SPI_TXCTL_TDU 0x00000100 /* Transmit Data Under-Run */ +#define SPI_TXCTL_TRWM 0x00003000 /* FIFO Regular Water-Mark */ +#define SPI_TXCTL_RWM_FULL 0x00000000 /* TRWM: TFIFO full */ +#define SPI_TXCTL_RWM_25 0x00001000 /* TRWM: TFIFO 25% empty */ +#define SPI_TXCTL_RWM_50 0x00002000 /* TRWM: TFIFO 50% empty */ +#define SPI_TXCTL_RWM_75 0x00003000 /* TRWM: TFIFO 75% empty */ +#define SPI_TXCTL_TUWM 0x00070000 /* FIFO Urgent Water-Mark */ +#define SPI_TXCTL_UWM_DIS 0x00000000 /* TUWM: Disabled */ +#define SPI_TXCTL_UWM_25 0x00010000 /* TUWM: TFIFO 25% empty */ +#define SPI_TXCTL_UWM_50 0x00020000 /* TUWM: TFIFO 50% empty */ +#define SPI_TXCTL_UWM_75 0x00030000 /* TUWM: TFIFO 75% empty */ +#define SPI_TXCTL_UWM_EMPTY 0x00040000 /* TUWM: TFIFO empty */ +/* SPI_CLOCK */ +#define SPI_CLK_BAUD 0x0000FFFF /* Baud Rate */ +/* SPI_DELAY */ +#define SPI_DLY_STOP 0x000000FF /* Transfer delay time in multiples of SCK period */ +#define SPI_DLY_LEADX 0x00000100 /* Extended (1 SCK) LEAD Control */ +#define SPI_DLY_LAGX 0x00000200 /* Extended (1 SCK) LAG control */ +/* SPI_SSEL */ +#define SPI_SLVSEL_SSE1 0x00000002 /* SPISSEL1 Enable */ +#define SPI_SLVSEL_SSE2 0x00000004 /* SPISSEL2 Enable */ +#define SPI_SLVSEL_SSE3 0x00000008 /* SPISSEL3 Enable */ +#define SPI_SLVSEL_SSE4 0x00000010 /* SPISSEL4 Enable */ +#define SPI_SLVSEL_SSE5 0x00000020 /* SPISSEL5 Enable */ +#define SPI_SLVSEL_SSE6 0x00000040 /* SPISSEL6 Enable */ +#define SPI_SLVSEL_SSE7 0x00000080 /* SPISSEL7 Enable */ +#define SPI_SLVSEL_SSEL1 0x00000200 /* SPISSEL1 Value */ +#define SPI_SLVSEL_SSEL2 0x00000400 /* SPISSEL2 Value */ +#define SPI_SLVSEL_SSEL3 0x00000800 /* SPISSEL3 Value */ +#define SPI_SLVSEL_SSEL4 0x00001000 /* SPISSEL4 Value */ +#define SPI_SLVSEL_SSEL5 0x00002000 /* SPISSEL5 Value */ +#define SPI_SLVSEL_SSEL6 0x00004000 /* SPISSEL6 Value */ +#define SPI_SLVSEL_SSEL7 0x00008000 /* SPISSEL7 Value */ +/* SPI_RWC */ +#define SPI_RWC_VALUE 0x0000FFFF /* Received Word-Count */ +/* SPI_RWCR */ +#define SPI_RWCR_VALUE 0x0000FFFF /* Received Word-Count Reload */ +/* SPI_TWC */ +#define SPI_TWC_VALUE 0x0000FFFF /* Transmitted Word-Count */ +/* SPI_TWCR */ +#define SPI_TWCR_VALUE 0x0000FFFF /* Transmitted Word-Count Reload */ +/* SPI_IMASK */ +#define SPI_IMSK_RUWM 0x00000002 /* Receive Urgent Water-Mark Interrupt Mask */ +#define SPI_IMSK_TUWM 0x00000004 /* Transmit Urgent Water-Mark Interrupt Mask */ +#define SPI_IMSK_ROM 0x00000010 /* Receive Over-Run Error Interrupt Mask */ +#define SPI_IMSK_TUM 0x00000020 /* Transmit Under-Run Error Interrupt Mask */ +#define SPI_IMSK_TCM 0x00000040 /* Transmit Collision Error Interrupt Mask */ +#define SPI_IMSK_MFM 0x00000080 /* Mode Fault Error Interrupt Mask */ +#define SPI_IMSK_RSM 0x00000100 /* Receive Start Interrupt Mask */ +#define SPI_IMSK_TSM 0x00000200 /* Transmit Start Interrupt Mask */ +#define SPI_IMSK_RFM 0x00000400 /* Receive Finish Interrupt Mask */ +#define SPI_IMSK_TFM 0x00000800 /* Transmit Finish Interrupt Mask */ +/* SPI_IMASKCL */ +#define SPI_IMSK_CLR_RUW 0x00000002 /* Receive Urgent Water-Mark Interrupt Mask */ +#define SPI_IMSK_CLR_TUWM 0x00000004 /* Transmit Urgent Water-Mark Interrupt Mask */ +#define SPI_IMSK_CLR_ROM 0x00000010 /* Receive Over-Run Error Interrupt Mask */ +#define SPI_IMSK_CLR_TUM 0x00000020 /* Transmit Under-Run Error Interrupt Mask */ +#define SPI_IMSK_CLR_TCM 0x00000040 /* Transmit Collision Error Interrupt Mask */ +#define SPI_IMSK_CLR_MFM 0x00000080 /* Mode Fault Error Interrupt Mask */ +#define SPI_IMSK_CLR_RSM 0x00000100 /* Receive Start Interrupt Mask */ +#define SPI_IMSK_CLR_TSM 0x00000200 /* Transmit Start Interrupt Mask */ +#define SPI_IMSK_CLR_RFM 0x00000400 /* Receive Finish Interrupt Mask */ +#define SPI_IMSK_CLR_TFM 0x00000800 /* Transmit Finish Interrupt Mask */ +/* SPI_IMASKST */ +#define SPI_IMSK_SET_RUWM 0x00000002 /* Receive Urgent Water-Mark Interrupt Mask */ +#define SPI_IMSK_SET_TUWM 0x00000004 /* Transmit Urgent Water-Mark Interrupt Mask */ +#define SPI_IMSK_SET_ROM 0x00000010 /* Receive Over-Run Error Interrupt Mask */ +#define SPI_IMSK_SET_TUM 0x00000020 /* Transmit Under-Run Error Interrupt Mask */ +#define SPI_IMSK_SET_TCM 0x00000040 /* Transmit Collision Error Interrupt Mask */ +#define SPI_IMSK_SET_MFM 0x00000080 /* Mode Fault Error Interrupt Mask */ +#define SPI_IMSK_SET_RSM 0x00000100 /* Receive Start Interrupt Mask */ +#define SPI_IMSK_SET_TSM 0x00000200 /* Transmit Start Interrupt Mask */ +#define SPI_IMSK_SET_RFM 0x00000400 /* Receive Finish Interrupt Mask */ +#define SPI_IMSK_SET_TFM 0x00000800 /* Transmit Finish Interrupt Mask */ +/* SPI_STATUS */ +#define SPI_STAT_SPIF 0x00000001 /* SPI Finished */ +#define SPI_STAT_RUWM 0x00000002 /* Receive Urgent Water-Mark Breached */ +#define SPI_STAT_TUWM 0x00000004 /* Transmit Urgent Water-Mark Breached */ +#define SPI_STAT_ROE 0x00000010 /* Receive Over-Run Error Indication */ +#define SPI_STAT_TUE 0x00000020 /* Transmit Under-Run Error Indication */ +#define SPI_STAT_TCE 0x00000040 /* Transmit Collision Error Indication */ +#define SPI_STAT_MODF 0x00000080 /* Mode Fault Error Indication */ +#define SPI_STAT_RS 0x00000100 /* Receive Start Indication */ +#define SPI_STAT_TS 0x00000200 /* Transmit Start Indication */ +#define SPI_STAT_RF 0x00000400 /* Receive Finish Indication */ +#define SPI_STAT_TF 0x00000800 /* Transmit Finish Indication */ +#define SPI_STAT_RFS 0x00007000 /* SPI_RFIFO status */ +#define SPI_STAT_RFIFO_EMPTY 0x00000000 /* RFS: RFIFO Empty */ +#define SPI_STAT_RFIFO_25 0x00001000 /* RFS: RFIFO 25% Full */ +#define SPI_STAT_RFIFO_50 0x00002000 /* RFS: RFIFO 50% Full */ +#define SPI_STAT_RFIFO_75 0x00003000 /* RFS: RFIFO 75% Full */ +#define SPI_STAT_RFIFO_FULL 0x00004000 /* RFS: RFIFO Full */ +#define SPI_STAT_TFS 0x00070000 /* SPI_TFIFO status */ +#define SPI_STAT_TFIFO_FULL 0x00000000 /* TFS: TFIFO full */ +#define SPI_STAT_TFIFO_25 0x00010000 /* TFS: TFIFO 25% empty */ +#define SPI_STAT_TFIFO_50 0x00020000 /* TFS: TFIFO 50% empty */ +#define SPI_STAT_TFIFO_75 0x00030000 /* TFS: TFIFO 75% empty */ +#define SPI_STAT_TFIFO_EMPTY 0x00040000 /* TFS: TFIFO empty */ +#define SPI_STAT_FCS 0x00100000 /* Flow-Control Stall Indication */ +#define SPI_STAT_RFE 0x00400000 /* SPI_RFIFO Empty */ +#define SPI_STAT_TFF 0x00800000 /* SPI_TFIFO Full */ +/* SPI_ILAT */ +#define SPI_ILAT_RUWMI 0x00000002 /* Receive Urgent Water Mark Interrupt */ +#define SPI_ILAT_TUWMI 0x00000004 /* Transmit Urgent Water Mark Interrupt */ +#define SPI_ILAT_ROI 0x00000010 /* Receive Over-Run Error Indication */ +#define SPI_ILAT_TUI 0x00000020 /* Transmit Under-Run Error Indication */ +#define SPI_ILAT_TCI 0x00000040 /* Transmit Collision Error Indication */ +#define SPI_ILAT_MFI 0x00000080 /* Mode Fault Error Indication */ +#define SPI_ILAT_RSI 0x00000100 /* Receive Start Indication */ +#define SPI_ILAT_TSI 0x00000200 /* Transmit Start Indication */ +#define SPI_ILAT_RFI 0x00000400 /* Receive Finish Indication */ +#define SPI_ILAT_TFI 0x00000800 /* Transmit Finish Indication */ +/* SPI_ILATCL */ +#define SPI_ILAT_CLR_RUWMI 0x00000002 /* Receive Urgent Water Mark Interrupt */ +#define SPI_ILAT_CLR_TUWMI 0x00000004 /* Transmit Urgent Water Mark Interrupt */ +#define SPI_ILAT_CLR_ROI 0x00000010 /* Receive Over-Run Error Indication */ +#define SPI_ILAT_CLR_TUI 0x00000020 /* Transmit Under-Run Error Indication */ +#define SPI_ILAT_CLR_TCI 0x00000040 /* Transmit Collision Error Indication */ +#define SPI_ILAT_CLR_MFI 0x00000080 /* Mode Fault Error Indication */ +#define SPI_ILAT_CLR_RSI 0x00000100 /* Receive Start Indication */ +#define SPI_ILAT_CLR_TSI 0x00000200 /* Transmit Start Indication */ +#define SPI_ILAT_CLR_RFI 0x00000400 /* Receive Finish Indication */ +#define SPI_ILAT_CLR_TFI 0x00000800 /* Transmit Finish Indication */ + +/* + * bfin spi3 registers layout + */ +struct bfin_spi_regs { + u32 revid; + u32 control; + u32 rx_control; + u32 tx_control; + u32 clock; + u32 delay; + u32 ssel; + u32 rwc; + u32 rwcr; + u32 twc; + u32 twcr; + u32 reserved0; + u32 emask; + u32 emaskcl; + u32 emaskst; + u32 reserved1; + u32 status; + u32 elat; + u32 elatcl; + u32 reserved2; + u32 rfifo; + u32 reserved3; + u32 tfifo; +}; + +#define MAX_CTRL_CS 8 /* cs in spi controller */ + +/* device.platform_data for SSP controller devices */ +struct bfin6xx_spi_master { + u16 num_chipselect; + u16 pin_req[7]; +}; + +/* spi_board_info.controller_data for SPI slave devices, + * copied to spi_device.platform_data ... mostly for dma tuning + */ +struct bfin6xx_spi_chip { + u32 control; + u16 cs_chg_udelay; /* Some devices require 16-bit delays */ + u32 tx_dummy_val; /* tx value for rx only transfer */ + bool enable_dma; +}; + +#endif /* _SPI_CHANNEL_H_ */ diff --git a/arch/blackfin/include/asm/bfin_crc.h b/arch/blackfin/include/asm/bfin_crc.h new file mode 100644 index 000000000000..3deb4452ceed --- /dev/null +++ b/arch/blackfin/include/asm/bfin_crc.h @@ -0,0 +1,139 @@ +/* + * bfin_crc.h - interface to Blackfin CRC controllers + * + * Copyright 2012 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __BFIN_CRC_H__ +#define __BFIN_CRC_H__ + +/* Function driver which use hardware crc must initialize the structure */ +struct crc_info { + /* Input data address */ + unsigned char *in_addr; + /* Output data address */ + unsigned char *out_addr; + /* Input or output bytes */ + unsigned long datasize; + union { + /* CRC to compare with that of input buffer */ + unsigned long crc_compare; + /* Value to compare with input data */ + unsigned long val_verify; + /* Value to fill */ + unsigned long val_fill; + }; + /* Value to program the 32b CRC Polynomial */ + unsigned long crc_poly; + union { + /* CRC calculated from the input data */ + unsigned long crc_result; + /* First failed position to verify input data */ + unsigned long pos_verify; + }; + /* CRC mirror flags */ + unsigned int bitmirr:1; + unsigned int bytmirr:1; + unsigned int w16swp:1; + unsigned int fdsel:1; + unsigned int rsltmirr:1; + unsigned int polymirr:1; + unsigned int cmpmirr:1; +}; + +/* Userspace interface */ +#define CRC_IOC_MAGIC 'C' +#define CRC_IOC_CALC_CRC _IOWR('C', 0x01, unsigned int) +#define CRC_IOC_MEMCPY_CRC _IOWR('C', 0x02, unsigned int) +#define CRC_IOC_VERIFY_VAL _IOWR('C', 0x03, unsigned int) +#define CRC_IOC_FILL_VAL _IOWR('C', 0x04, unsigned int) + + +#ifdef __KERNEL__ + +#include <linux/types.h> +#include <linux/spinlock.h> +#include <linux/miscdevice.h> + +struct crc_register { + u32 control; + u32 datacnt; + u32 datacntrld; + u32 __pad_1[2]; + u32 compare; + u32 fillval; + u32 datafifo; + u32 intren; + u32 intrenset; + u32 intrenclr; + u32 poly; + u32 __pad_2[4]; + u32 status; + u32 datacntcap; + u32 __pad_3; + u32 result; + u32 curresult; + u32 __pad_4[3]; + u32 revid; +}; + +struct bfin_crc { + struct miscdevice mdev; + struct list_head list; + int irq; + int dma_ch_src; + int dma_ch_dest; + volatile struct crc_register *regs; + struct crc_info *info; + struct mutex mutex; + struct completion c; + unsigned short opmode; + char name[20]; +}; + +/* CRC_STATUS Masks */ +#define CMPERR 0x00000002 /* Compare error */ +#define DCNTEXP 0x00000010 /* datacnt register expired */ +#define IBR 0x00010000 /* Input buffer ready */ +#define OBR 0x00020000 /* Output buffer ready */ +#define IRR 0x00040000 /* Immediate result readt */ +#define LUTDONE 0x00080000 /* Look-up table generation done */ +#define FSTAT 0x00700000 /* FIFO status */ +#define MAX_FIFO 4 /* Max fifo size */ + +/* CRC_CONTROL Masks */ +#define BLKEN 0x00000001 /* Block enable */ +#define OPMODE 0x000000F0 /* Operation mode */ +#define OPMODE_OFFSET 4 /* Operation mode mask offset*/ +#define MODE_DMACPY_CRC 1 /* MTM CRC compute and compare */ +#define MODE_DATA_FILL 2 /* MTM data fill */ +#define MODE_CALC_CRC 3 /* MSM CRC compute and compare */ +#define MODE_DATA_VERIFY 4 /* MSM data verify */ +#define AUTOCLRZ 0x00000100 /* Auto clear to zero */ +#define AUTOCLRF 0x00000200 /* Auto clear to one */ +#define OBRSTALL 0x00001000 /* Stall on output buffer ready */ +#define IRRSTALL 0x00002000 /* Stall on immediate result ready */ +#define BITMIRR 0x00010000 /* Mirror bits within each byte of 32-bit input data */ +#define BITMIRR_OFFSET 16 /* Mirror bits offset */ +#define BYTMIRR 0x00020000 /* Mirror bytes of 32-bit input data */ +#define BYTMIRR_OFFSET 17 /* Mirror bytes offset */ +#define W16SWP 0x00040000 /* Mirror uppper and lower 16-bit word of 32-bit input data */ +#define W16SWP_OFFSET 18 /* Mirror 16-bit word offset */ +#define FDSEL 0x00080000 /* FIFO is written after input data is mirrored */ +#define FDSEL_OFFSET 19 /* Mirror FIFO offset */ +#define RSLTMIRR 0x00100000 /* CRC result registers are mirrored. */ +#define RSLTMIRR_OFFSET 20 /* Mirror CRC result offset. */ +#define POLYMIRR 0x00200000 /* CRC poly register is mirrored. */ +#define POLYMIRR_OFFSET 21 /* Mirror CRC poly offset. */ +#define CMPMIRR 0x00400000 /* CRC compare register is mirrored. */ +#define CMPMIRR_OFFSET 22 /* Mirror CRC compare offset. */ + +/* CRC_INTREN Masks */ +#define CMPERRI 0x02 /* CRC_ERROR_INTR */ +#define DCNTEXPI 0x10 /* CRC_STATUS_INTR */ + +#endif + +#endif diff --git a/arch/blackfin/include/asm/bfin_dma.h b/arch/blackfin/include/asm/bfin_dma.h index d51120744148..6319f4e49083 100644 --- a/arch/blackfin/include/asm/bfin_dma.h +++ b/arch/blackfin/include/asm/bfin_dma.h @@ -15,12 +15,55 @@ #define DMAEN 0x0001 /* DMA Channel Enable */ #define WNR 0x0002 /* Channel Direction (W/R*) */ #define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */ +#define PSIZE_8 0x00000000 /* Transfer Word Size = 16 */ + +#ifdef CONFIG_BF60x + +#define PSIZE_16 0x00000010 /* Transfer Word Size = 16 */ +#define PSIZE_32 0x00000020 /* Transfer Word Size = 32 */ +#define PSIZE_64 0x00000030 /* Transfer Word Size = 32 */ +#define WDSIZE_16 0x00000100 /* Transfer Word Size = 16 */ +#define WDSIZE_32 0x00000200 /* Transfer Word Size = 32 */ +#define WDSIZE_64 0x00000300 /* Transfer Word Size = 32 */ +#define WDSIZE_128 0x00000400 /* Transfer Word Size = 32 */ +#define WDSIZE_256 0x00000500 /* Transfer Word Size = 32 */ +#define DMA2D 0x04000000 /* DMA Mode (2D/1D*) */ +#define RESTART 0x00000004 /* DMA Buffer Clear SYNC */ +#define DI_EN_X 0x00100000 /* Data Interrupt Enable in X count */ +#define DI_EN_Y 0x00200000 /* Data Interrupt Enable in Y count */ +#define DI_EN_P 0x00300000 /* Data Interrupt Enable in Peripheral */ +#define DI_EN DI_EN_X /* Data Interrupt Enable */ +#define NDSIZE_0 0x00000000 /* Next Descriptor Size = 1 */ +#define NDSIZE_1 0x00010000 /* Next Descriptor Size = 2 */ +#define NDSIZE_2 0x00020000 /* Next Descriptor Size = 3 */ +#define NDSIZE_3 0x00030000 /* Next Descriptor Size = 4 */ +#define NDSIZE_4 0x00040000 /* Next Descriptor Size = 5 */ +#define NDSIZE_5 0x00050000 /* Next Descriptor Size = 6 */ +#define NDSIZE_6 0x00060000 /* Next Descriptor Size = 7 */ +#define NDSIZE 0x00070000 /* Next Descriptor Size */ +#define NDSIZE_OFFSET 16 /* Next Descriptor Size Offset */ +#define DMAFLOW_LIST 0x00004000 /* Descriptor List Mode */ +#define DMAFLOW_LARGE DMAFLOW_LIST +#define DMAFLOW_ARRAY 0x00005000 /* Descriptor Array Mode */ +#define DMAFLOW_LIST_DEMAND 0x00006000 /* Descriptor Demand List Mode */ +#define DMAFLOW_ARRAY_DEMAND 0x00007000 /* Descriptor Demand Array Mode */ +#define DMA_RUN_DFETCH 0x00000100 /* DMA Channel Running Indicator (DFETCH) */ +#define DMA_RUN 0x00000200 /* DMA Channel Running Indicator */ +#define DMA_RUN_WAIT_TRIG 0x00000300 /* DMA Channel Running Indicator (WAIT TRIG) */ +#define DMA_RUN_WAIT_ACK 0x00000400 /* DMA Channel Running Indicator (WAIT ACK) */ + +#else + +#define PSIZE_16 0x0000 /* Transfer Word Size = 16 */ +#define PSIZE_32 0x0000 /* Transfer Word Size = 32 */ #define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */ #define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */ #define DMA2D 0x0010 /* DMA Mode (2D/1D*) */ #define RESTART 0x0020 /* DMA Buffer Clear */ #define DI_SEL 0x0040 /* Data Interrupt Timing Select */ #define DI_EN 0x0080 /* Data Interrupt Enable */ +#define DI_EN_X 0x00C0 /* Data Interrupt Enable in X count*/ +#define DI_EN_Y 0x0080 /* Data Interrupt Enable in Y count*/ #define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ #define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ #define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ @@ -32,18 +75,26 @@ #define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ #define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ #define NDSIZE 0x0f00 /* Next Descriptor Size */ -#define DMAFLOW 0x7000 /* Flow Control */ -#define DMAFLOW_STOP 0x0000 /* Stop Mode */ -#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */ +#define NDSIZE_OFFSET 8 /* Next Descriptor Size Offset */ #define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */ #define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ #define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ +#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */ +#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */ + +#endif +#define DMAFLOW 0x7000 /* Flow Control */ +#define DMAFLOW_STOP 0x0000 /* Stop Mode */ +#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */ /* DMA_IRQ_STATUS Masks */ #define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */ #define DMA_ERR 0x0002 /* DMA Error Interrupt Status */ -#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */ -#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */ +#ifdef CONFIG_BF60x +#define DMA_PIRQ 0x0004 /* DMA Peripheral Error Interrupt Status */ +#else +#define DMA_PIRQ 0 +#endif /* * All Blackfin system MMRs are padded to 32bits even if the register @@ -57,6 +108,26 @@ struct bfin_dma_regs { u32 next_desc_ptr; u32 start_addr; +#ifdef CONFIG_BF60x + u32 cfg; + u32 x_count; + u32 x_modify; + u32 y_count; + u32 y_modify; + u32 pad1; + u32 pad2; + u32 curr_desc_ptr; + u32 prev_desc_ptr; + u32 curr_addr; + u32 irq_status; + u32 curr_x_count; + u32 curr_y_count; + u32 pad3; + u32 bw_limit_count; + u32 curr_bw_limit_count; + u32 bw_monitor_count; + u32 curr_bw_monitor_count; +#else __BFP(config); u32 __pad0; __BFP(x_count); @@ -71,8 +142,10 @@ struct bfin_dma_regs { u32 __pad1; __BFP(curr_y_count); u32 __pad2; +#endif }; +#ifndef CONFIG_BF60x /* * bfin handshake mdma registers layout */ @@ -85,6 +158,7 @@ struct bfin_hmdma_regs { __BFP(ecount); __BFP(bcount); }; +#endif #undef __BFP diff --git a/arch/blackfin/include/asm/bfin_pfmon.h b/arch/blackfin/include/asm/bfin_pfmon.h index accd47e2db40..bf52e1f32257 100644 --- a/arch/blackfin/include/asm/bfin_pfmon.h +++ b/arch/blackfin/include/asm/bfin_pfmon.h @@ -3,7 +3,7 @@ * * Copyright 2005-2011 Analog Devices Inc. * - * Licensed under the ADI BSD license or GPL-2 (or later). + * Licensed under the Clear BSD license or GPL-2 (or later). */ #ifndef __ASM_BFIN_PFMON_H__ diff --git a/arch/blackfin/include/asm/bfin_ppi.h b/arch/blackfin/include/asm/bfin_ppi.h index 3be05faa2c65..a4e872e16e75 100644 --- a/arch/blackfin/include/asm/bfin_ppi.h +++ b/arch/blackfin/include/asm/bfin_ppi.h @@ -10,6 +10,7 @@ #define __ASM_BFIN_PPI_H__ #include <linux/types.h> +#include <asm/blackfin.h> /* * All Blackfin system MMRs are padded to 32bits even if the register @@ -48,6 +49,133 @@ struct bfin_eppi_regs { u32 clip; }; +/* + * bfin eppi3 registers layout + */ +struct bfin_eppi3_regs { + u32 stat; + u32 hcnt; + u32 hdly; + u32 vcnt; + u32 vdly; + u32 frame; + u32 line; + u32 clkdiv; + u32 ctl; + u32 fs1_wlhb; + u32 fs1_paspl; + u32 fs2_wlvb; + u32 fs2_palpf; + u32 imsk; + u32 oddclip; + u32 evenclip; + u32 fs1_dly; + u32 fs2_dly; + u32 ctl2; +}; + #undef __BFP +#ifdef EPPI0_CTL2 +#define EPPI_STAT_CFIFOERR 0x00000001 /* Chroma FIFO Error */ +#define EPPI_STAT_YFIFOERR 0x00000002 /* Luma FIFO Error */ +#define EPPI_STAT_LTERROVR 0x00000004 /* Line Track Overflow */ +#define EPPI_STAT_LTERRUNDR 0x00000008 /* Line Track Underflow */ +#define EPPI_STAT_FTERROVR 0x00000010 /* Frame Track Overflow */ +#define EPPI_STAT_FTERRUNDR 0x00000020 /* Frame Track Underflow */ +#define EPPI_STAT_ERRNCOR 0x00000040 /* Preamble Error Not Corrected */ +#define EPPI_STAT_PXPERR 0x00000080 /* PxP Ready Error */ +#define EPPI_STAT_ERRDET 0x00004000 /* Preamble Error Detected */ +#define EPPI_STAT_FLD 0x00008000 /* Current Field Received by EPPI */ + +#define EPPI_HCNT_VALUE 0x0000FFFF /* Holds the number of samples to read in or write out per line, after PPIx_HDLY number of cycles have expired since the last assertion of PPIx_FS1 */ + +#define EPPI_HDLY_VALUE 0x0000FFFF /* Number of PPIx_CLK cycles to delay after assertion of PPIx_FS1 before starting to read or write data */ + +#define EPPI_VCNT_VALUE 0x0000FFFF /* Holds the number of lines to read in or write out, after PPIx_VDLY number of lines from the start of frame */ + +#define EPPI_VDLY_VALUE 0x0000FFFF /* Number of lines to wait after the start of a new frame before starting to read/transmit data */ + +#define EPPI_FRAME_VALUE 0x0000FFFF /* Holds the number of lines expected per frame of data */ + +#define EPPI_LINE_VALUE 0x0000FFFF /* Holds the number of samples expected per line */ + +#define EPPI_CLKDIV_VALUE 0x0000FFFF /* Internal clock divider */ + +#define EPPI_CTL_EN 0x00000001 /* PPI Enable */ +#define EPPI_CTL_DIR 0x00000002 /* PPI Direction */ +#define EPPI_CTL_XFRTYPE 0x0000000C /* PPI Operating Mode */ +#define EPPI_CTL_ACTIVE656 0x00000000 /* XFRTYPE: ITU656 Active Video Only Mode */ +#define EPPI_CTL_ENTIRE656 0x00000004 /* XFRTYPE: ITU656 Entire Field Mode */ +#define EPPI_CTL_VERT656 0x00000008 /* XFRTYPE: ITU656 Vertical Blanking Only Mode */ +#define EPPI_CTL_NON656 0x0000000C /* XFRTYPE: Non-ITU656 Mode (GP Mode) */ +#define EPPI_CTL_FSCFG 0x00000030 /* Frame Sync Configuration */ +#define EPPI_CTL_SYNC0 0x00000000 /* FSCFG: Sync Mode 0 */ +#define EPPI_CTL_SYNC1 0x00000010 /* FSCFG: Sync Mode 1 */ +#define EPPI_CTL_SYNC2 0x00000020 /* FSCFG: Sync Mode 2 */ +#define EPPI_CTL_SYNC3 0x00000030 /* FSCFG: Sync Mode 3 */ +#define EPPI_CTL_FLDSEL 0x00000040 /* Field Select/Trigger */ +#define EPPI_CTL_ITUTYPE 0x00000080 /* ITU Interlace or Progressive */ +#define EPPI_CTL_BLANKGEN 0x00000100 /* ITU Output Mode with Internal Blanking Generation */ +#define EPPI_CTL_ICLKGEN 0x00000200 /* Internal Clock Generation */ +#define EPPI_CTL_IFSGEN 0x00000400 /* Internal Frame Sync Generation */ +#define EPPI_CTL_SIGNEXT 0x00000800 /* Sign Extension */ +#define EPPI_CTL_POLC 0x00003000 /* Frame Sync and Data Driving and Sampling Edges */ +#define EPPI_CTL_POLC0 0x00000000 /* POLC: Clock/Sync polarity mode 0 */ +#define EPPI_CTL_POLC1 0x00001000 /* POLC: Clock/Sync polarity mode 1 */ +#define EPPI_CTL_POLC2 0x00002000 /* POLC: Clock/Sync polarity mode 2 */ +#define EPPI_CTL_POLC3 0x00003000 /* POLC: Clock/Sync polarity mode 3 */ +#define EPPI_CTL_POLS 0x0000C000 /* Frame Sync Polarity */ +#define EPPI_CTL_FS1HI_FS2HI 0x00000000 /* POLS: FS1 and FS2 are active high */ +#define EPPI_CTL_FS1LO_FS2HI 0x00004000 /* POLS: FS1 is active low. FS2 is active high */ +#define EPPI_CTL_FS1HI_FS2LO 0x00008000 /* POLS: FS1 is active high. FS2 is active low */ +#define EPPI_CTL_FS1LO_FS2LO 0x0000C000 /* POLS: FS1 and FS2 are active low */ +#define EPPI_CTL_DLEN 0x00070000 /* Data Length */ +#define EPPI_CTL_DLEN08 0x00000000 /* DLEN: 8 bits */ +#define EPPI_CTL_DLEN10 0x00010000 /* DLEN: 10 bits */ +#define EPPI_CTL_DLEN12 0x00020000 /* DLEN: 12 bits */ +#define EPPI_CTL_DLEN14 0x00030000 /* DLEN: 14 bits */ +#define EPPI_CTL_DLEN16 0x00040000 /* DLEN: 16 bits */ +#define EPPI_CTL_DLEN18 0x00050000 /* DLEN: 18 bits */ +#define EPPI_CTL_DLEN20 0x00060000 /* DLEN: 20 bits */ +#define EPPI_CTL_DLEN24 0x00070000 /* DLEN: 24 bits */ +#define EPPI_CTL_DMIRR 0x00080000 /* Data Mirroring */ +#define EPPI_CTL_SKIPEN 0x00100000 /* Skip Enable */ +#define EPPI_CTL_SKIPEO 0x00200000 /* Skip Even or Odd */ +#define EPPI_CTL_PACKEN 0x00400000 /* Pack/Unpack Enable */ +#define EPPI_CTL_SWAPEN 0x00800000 /* Swap Enable */ +#define EPPI_CTL_SPLTEO 0x01000000 /* Split Even and Odd Data Samples */ +#define EPPI_CTL_SUBSPLTODD 0x02000000 /* Sub-Split Odd Samples */ +#define EPPI_CTL_SPLTWRD 0x04000000 /* Split Word */ +#define EPPI_CTL_RGBFMTEN 0x08000000 /* RGB Formatting Enable */ +#define EPPI_CTL_DMACFG 0x10000000 /* One or Two DMA Channels Mode */ +#define EPPI_CTL_DMAFINEN 0x20000000 /* DMA Finish Enable */ +#define EPPI_CTL_MUXSEL 0x40000000 /* MUX Select */ +#define EPPI_CTL_CLKGATEN 0x80000000 /* Clock Gating Enable */ + +#define EPPI_FS2_WLVB_F2VBAD 0xFF000000 /* In GP transmit mode with BLANKGEN = 1, contains number of lines of vertical blanking after field 2 */ +#define EPPI_FS2_WLVB_F2VBBD 0x00FF0000 /* In GP transmit mode with BLANKGEN = 1, contains number of lines of vertical blanking before field 2 */ +#define EPPI_FS2_WLVB_F1VBAD 0x0000FF00 /* In GP transmit mode with, BLANKGEN = 1, contains number of lines of vertical blanking after field 1 */ +#define EPPI_FS2_WLVB_F1VBBD 0x000000FF /* In GP 2, or 3 FS modes used to generate PPIx_FS2 width (32-bit). In GP Transmit mode, with BLANKGEN=1, contains the number of lines of Vertical blanking before field 1. */ + +#define EPPI_FS2_PALPF_F2ACT 0xFFFF0000 /* Number of lines of Active Data in Field 2 */ +#define EPPI_FS2_PALPF_F1ACT 0x0000FFFF /* Number of lines of Active Data in Field 1 */ + +#define EPPI_IMSK_CFIFOERR 0x00000001 /* Mask CFIFO Underflow or Overflow Error Interrupt */ +#define EPPI_IMSK_YFIFOERR 0x00000002 /* Mask YFIFO Underflow or Overflow Error Interrupt */ +#define EPPI_IMSK_LTERROVR 0x00000004 /* Mask Line Track Overflow Error Interrupt */ +#define EPPI_IMSK_LTERRUNDR 0x00000008 /* Mask Line Track Underflow Error Interrupt */ +#define EPPI_IMSK_FTERROVR 0x00000010 /* Mask Frame Track Overflow Error Interrupt */ +#define EPPI_IMSK_FTERRUNDR 0x00000020 /* Mask Frame Track Underflow Error Interrupt */ +#define EPPI_IMSK_ERRNCOR 0x00000040 /* Mask ITU Preamble Error Not Corrected Interrupt */ +#define EPPI_IMSK_PXPERR 0x00000080 /* Mask PxP Ready Error Interrupt */ + +#define EPPI_ODDCLIP_HIGHODD 0xFFFF0000 +#define EPPI_ODDCLIP_LOWODD 0x0000FFFF + +#define EPPI_EVENCLIP_HIGHEVEN 0xFFFF0000 +#define EPPI_EVENCLIP_LOWEVEN 0x0000FFFF + +#define EPPI_CTL2_FS1FINEN 0x00000002 /* HSYNC Finish Enable */ +#endif #endif diff --git a/arch/blackfin/include/asm/bfin_rotary.h b/arch/blackfin/include/asm/bfin_rotary.h index 0b6910bdc57f..8895a750c70c 100644 --- a/arch/blackfin/include/asm/bfin_rotary.h +++ b/arch/blackfin/include/asm/bfin_rotary.h @@ -39,6 +39,7 @@ struct bfin_rotary_platform_data { unsigned int rotary_rel_code; unsigned short debounce; /* 0..17 */ unsigned short mode; + unsigned short pm_wakeup; }; /* CNT_CONFIG bitmasks */ diff --git a/arch/blackfin/include/asm/bfin_serial.h b/arch/blackfin/include/asm/bfin_serial.h index 68bcc3d119b6..8597158010b5 100644 --- a/arch/blackfin/include/asm/bfin_serial.h +++ b/arch/blackfin/include/asm/bfin_serial.h @@ -18,7 +18,7 @@ defined(CONFIG_BFIN_UART1_CTSRTS) || \ defined(CONFIG_BFIN_UART2_CTSRTS) || \ defined(CONFIG_BFIN_UART3_CTSRTS) -# ifdef BFIN_UART_BF54X_STYLE +# if defined(BFIN_UART_BF54X_STYLE) || defined(BFIN_UART_BF60X_STYLE) # define CONFIG_SERIAL_BFIN_HARD_CTSRTS # else # define CONFIG_SERIAL_BFIN_CTSRTS @@ -58,14 +58,69 @@ struct bfin_serial_port { #endif }; +#ifdef BFIN_UART_BF60X_STYLE + +/* UART_CTL Masks */ +#define UCEN 0x1 /* Enable UARTx Clocks */ +#define LOOP_ENA 0x2 /* Loopback Mode Enable */ +#define UMOD_MDB 0x10 /* Enable MDB Mode */ +#define UMOD_IRDA 0x20 /* Enable IrDA Mode */ +#define UMOD_MASK 0x30 /* Uart Mode Mask */ +#define WLS(x) (((x-5) & 0x03) << 8) /* Word Length Select */ +#define WLS_MASK 0x300 /* Word length Select Mask */ +#define WLS_OFFSET 8 /* Word length Select Offset */ +#define STB 0x1000 /* Stop Bits */ +#define STBH 0x2000 /* Half Stop Bits */ +#define PEN 0x4000 /* Parity Enable */ +#define EPS 0x8000 /* Even Parity Select */ +#define STP 0x10000 /* Stick Parity */ +#define FPE 0x20000 /* Force Parity Error On Transmit */ +#define FFE 0x40000 /* Force Framing Error On Transmit */ +#define SB 0x80000 /* Set Break */ +#define LCR_MASK (SB | STP | EPS | PEN | STB | WLS_MASK) +#define FCPOL 0x400000 /* Flow Control Pin Polarity */ +#define RPOLC 0x800000 /* IrDA RX Polarity Change */ +#define TPOLC 0x1000000 /* IrDA TX Polarity Change */ +#define MRTS 0x2000000 /* Manual Request To Send */ +#define XOFF 0x4000000 /* Transmitter Off */ +#define ARTS 0x8000000 /* Automatic Request To Send */ +#define ACTS 0x10000000 /* Automatic Clear To Send */ +#define RFIT 0x20000000 /* Receive FIFO IRQ Threshold */ +#define RFRT 0x40000000 /* Receive FIFO RTS Threshold */ + +/* UART_STAT Masks */ +#define DR 0x01 /* Data Ready */ +#define OE 0x02 /* Overrun Error */ +#define PE 0x04 /* Parity Error */ +#define FE 0x08 /* Framing Error */ +#define BI 0x10 /* Break Interrupt */ +#define THRE 0x20 /* THR Empty */ +#define TEMT 0x80 /* TSR and UART_THR Empty */ +#define TFI 0x100 /* Transmission Finished Indicator */ + +#define ASTKY 0x200 /* Address Sticky */ +#define ADDR 0x400 /* Address bit status */ +#define RO 0x800 /* Reception Ongoing */ +#define SCTS 0x1000 /* Sticky CTS */ +#define CTS 0x10000 /* Clear To Send */ +#define RFCS 0x20000 /* Receive FIFO Count Status */ + +/* UART_CLOCK Masks */ +#define EDBO 0x80000000 /* Enable Devide by One */ + +#else /* BFIN_UART_BF60X_STYLE */ + /* UART_LCR Masks */ #define WLS(x) (((x)-5) & 0x03) /* Word Length Select */ +#define WLS_MASK 0x03 /* Word length Select Mask */ +#define WLS_OFFSET 0 /* Word length Select Offset */ #define STB 0x04 /* Stop Bits */ #define PEN 0x08 /* Parity Enable */ #define EPS 0x10 /* Even Parity Select */ #define STP 0x20 /* Stick Parity */ #define SB 0x40 /* Set Break */ #define DLAB 0x80 /* Divisor Latch Access */ +#define LCR_MASK (SB | STP | EPS | PEN | STB | WLS_MASK) /* UART_LSR Masks */ #define DR 0x01 /* Data Ready */ @@ -77,15 +132,6 @@ struct bfin_serial_port { #define TEMT 0x40 /* TSR and UART_THR Empty */ #define TFI 0x80 /* Transmission Finished Indicator */ -/* UART_IER Masks */ -#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */ -#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */ -#define ELSI 0x04 /* Enable RX Status Interrupt */ -#define EDSSI 0x08 /* Enable Modem Status Interrupt */ -#define EDTPTI 0x10 /* Enable DMA Transmit PIRQ Interrupt */ -#define ETFI 0x20 /* Enable Transmission Finished Interrupt */ -#define ERFCI 0x40 /* Enable Receive FIFO Count Interrupt */ - /* UART_MCR Masks */ #define XOFF 0x01 /* Transmitter Off */ #define MRTS 0x02 /* Manual Request To Send */ @@ -103,13 +149,36 @@ struct bfin_serial_port { /* UART_GCTL Masks */ #define UCEN 0x01 /* Enable UARTx Clocks */ -#define IREN 0x02 /* Enable IrDA Mode */ +#define UMOD_IRDA 0x02 /* Enable IrDA Mode */ +#define UMOD_MASK 0x02 /* Uart Mode Mask */ #define TPOLC 0x04 /* IrDA TX Polarity Change */ #define RPOLC 0x08 /* IrDA RX Polarity Change */ #define FPE 0x10 /* Force Parity Error On Transmit */ #define FFE 0x20 /* Force Framing Error On Transmit */ -#ifdef BFIN_UART_BF54X_STYLE +#endif /* BFIN_UART_BF60X_STYLE */ + +/* UART_IER Masks */ +#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */ +#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */ +#define ELSI 0x04 /* Enable RX Status Interrupt */ +#define EDSSI 0x08 /* Enable Modem Status Interrupt */ +#define EDTPTI 0x10 /* Enable DMA Transmit PIRQ Interrupt */ +#define ETFI 0x20 /* Enable Transmission Finished Interrupt */ +#define ERFCI 0x40 /* Enable Receive FIFO Count Interrupt */ + +#if defined(BFIN_UART_BF60X_STYLE) +# define OFFSET_REDIV 0x00 /* Version ID Register */ +# define OFFSET_CTL 0x04 /* Control Register */ +# define OFFSET_STAT 0x08 /* Status Register */ +# define OFFSET_SCR 0x0C /* SCR Scratch Register */ +# define OFFSET_CLK 0x10 /* Clock Rate Register */ +# define OFFSET_IER 0x14 /* Interrupt Enable Register */ +# define OFFSET_IER_SET 0x18 /* Set Interrupt Enable Register */ +# define OFFSET_IER_CLEAR 0x1C /* Clear Interrupt Enable Register */ +# define OFFSET_RBR 0x20 /* Receive Buffer register */ +# define OFFSET_THR 0x24 /* Transmit Holding register */ +#elif defined(BFIN_UART_BF54X_STYLE) # define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ # define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ # define OFFSET_GCTL 0x08 /* Global Control Register */ @@ -145,7 +214,23 @@ struct bfin_serial_port { */ #define __BFP(m) u16 m; u16 __pad_##m struct bfin_uart_regs { -#ifdef BFIN_UART_BF54X_STYLE +#if defined(BFIN_UART_BF60X_STYLE) + u32 revid; + u32 ctl; + u32 stat; + u32 scr; + u32 clk; + u32 ier; + u32 ier_set; + u32 ier_clear; + u32 rbr; + u32 thr; + u32 taip; + u32 tsr; + u32 rsr; + u32 txdiv; + u32 rxdiv; +#elif defined(BFIN_UART_BF54X_STYLE) __BFP(dll); __BFP(dlh); __BFP(gctl); @@ -182,13 +267,70 @@ struct bfin_uart_regs { }; #undef __BFP +#define port_membase(uart) (((struct bfin_serial_port *)(uart))->port.membase) + +/* #ifndef port_membase # define port_membase(p) 0 #endif +*/ +#ifdef BFIN_UART_BF60X_STYLE + +#define UART_GET_CHAR(p) bfin_read32(port_membase(p) + OFFSET_RBR) +#define UART_GET_CLK(p) bfin_read32(port_membase(p) + OFFSET_CLK) +#define UART_GET_CTL(p) bfin_read32(port_membase(p) + OFFSET_CTL) +#define UART_GET_GCTL(p) UART_GET_CTL(p) +#define UART_GET_LCR(p) UART_GET_CTL(p) +#define UART_GET_MCR(p) UART_GET_CTL(p) +#if ANOMALY_05001001 +#define UART_GET_STAT(p) \ +({ \ + u32 __ret; \ + unsigned long flags; \ + flags = hard_local_irq_save(); \ + __ret = bfin_read32(port_membase(p) + OFFSET_STAT); \ + hard_local_irq_restore(flags); \ + __ret; \ +}) +#else +#define UART_GET_STAT(p) bfin_read32(port_membase(p) + OFFSET_STAT) +#endif +#define UART_GET_MSR(p) UART_GET_STAT(p) + +#define UART_PUT_CHAR(p, v) bfin_write32(port_membase(p) + OFFSET_THR, v) +#define UART_PUT_CLK(p, v) bfin_write32(port_membase(p) + OFFSET_CLK, v) +#define UART_PUT_CTL(p, v) bfin_write32(port_membase(p) + OFFSET_CTL, v) +#define UART_PUT_GCTL(p, v) UART_PUT_CTL(p, v) +#define UART_PUT_LCR(p, v) UART_PUT_CTL(p, v) +#define UART_PUT_MCR(p, v) UART_PUT_CTL(p, v) +#define UART_PUT_STAT(p, v) bfin_write32(port_membase(p) + OFFSET_STAT, v) + +#define UART_CLEAR_IER(p, v) bfin_write32(port_membase(p) + OFFSET_IER_CLEAR, v) +#define UART_GET_IER(p) bfin_read32(port_membase(p) + OFFSET_IER) +#define UART_SET_IER(p, v) bfin_write32(port_membase(p) + OFFSET_IER_SET, v) + +#define UART_CLEAR_DLAB(p) /* MMRs not muxed on BF60x */ +#define UART_SET_DLAB(p) /* MMRs not muxed on BF60x */ + +#define UART_CLEAR_LSR(p) UART_PUT_STAT(p, -1) +#define UART_GET_LSR(p) UART_GET_STAT(p) +#define UART_PUT_LSR(p, v) UART_PUT_STAT(p, v) + +/* This handles hard CTS/RTS */ +#define BFIN_UART_CTSRTS_HARD +#define UART_CLEAR_SCTS(p) UART_PUT_STAT(p, SCTS) +#define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS) +#define UART_DISABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS | MRTS)) +#define UART_ENABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS | ARTS) +#define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v) +#define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF) + +#else /* BFIN_UART_BF60X_STYLE */ #define UART_GET_CHAR(p) bfin_read16(port_membase(p) + OFFSET_RBR) #define UART_GET_DLL(p) bfin_read16(port_membase(p) + OFFSET_DLL) #define UART_GET_DLH(p) bfin_read16(port_membase(p) + OFFSET_DLH) +#define UART_GET_CLK(p) ((UART_GET_DLH(p) << 8) | UART_GET_DLL(p)) #define UART_GET_GCTL(p) bfin_read16(port_membase(p) + OFFSET_GCTL) #define UART_GET_LCR(p) bfin_read16(port_membase(p) + OFFSET_LCR) #define UART_GET_MCR(p) bfin_read16(port_membase(p) + OFFSET_MCR) @@ -197,6 +339,11 @@ struct bfin_uart_regs { #define UART_PUT_CHAR(p, v) bfin_write16(port_membase(p) + OFFSET_THR, v) #define UART_PUT_DLL(p, v) bfin_write16(port_membase(p) + OFFSET_DLL, v) #define UART_PUT_DLH(p, v) bfin_write16(port_membase(p) + OFFSET_DLH, v) +#define UART_PUT_CLK(p, v) do \ +{\ +UART_PUT_DLL(p, v & 0xFF); \ +UART_PUT_DLH(p, (v >> 8) & 0xFF); } while (0); + #define UART_PUT_GCTL(p, v) bfin_write16(port_membase(p) + OFFSET_GCTL, v) #define UART_PUT_LCR(p, v) bfin_write16(port_membase(p) + OFFSET_LCR, v) #define UART_PUT_MCR(p, v) bfin_write16(port_membase(p) + OFFSET_MCR, v) @@ -233,12 +380,17 @@ struct bfin_uart_regs { #define UART_CLEAR_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) & ~DLAB); SSYNC(); } while (0) #define UART_SET_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) | DLAB); SSYNC(); } while (0) +#define get_lsr_cache(uart) (((struct bfin_serial_port *)(uart))->lsr) +#define put_lsr_cache(uart, v) (((struct bfin_serial_port *)(uart))->lsr = (v)) + +/* #ifndef put_lsr_cache # define put_lsr_cache(p, v) #endif #ifndef get_lsr_cache # define get_lsr_cache(p) 0 #endif +*/ /* The hardware clears the LSR bits upon read, so we need to cache * some of the more fun bits in software so they don't get lost @@ -267,7 +419,9 @@ static inline void UART_PUT_LSR(void *p, uint16_t val) #define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v) #define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0) -#endif +#endif /* BFIN_UART_BF54X_STYLE */ + +#endif /* BFIN_UART_BF60X_STYLE */ #ifndef BFIN_UART_TX_FIFO_SIZE # define BFIN_UART_TX_FIFO_SIZE 2 diff --git a/arch/blackfin/include/asm/bfin_sport.h b/arch/blackfin/include/asm/bfin_sport.h index 0afcfbd54a82..f8907ea6b5b6 100644 --- a/arch/blackfin/include/asm/bfin_sport.h +++ b/arch/blackfin/include/asm/bfin_sport.h @@ -24,6 +24,7 @@ struct sport_config { /* TDM (multichannels), I2S or other mode */ unsigned int mode:3; + unsigned int polled; /* use poll instead of irq when set */ /* if TDM mode is selected, channels must be set */ int channels; /* Must be in 8 units */ diff --git a/arch/blackfin/include/asm/bfin_sport3.h b/arch/blackfin/include/asm/bfin_sport3.h new file mode 100644 index 000000000000..03c00220d69b --- /dev/null +++ b/arch/blackfin/include/asm/bfin_sport3.h @@ -0,0 +1,107 @@ +/* + * bfin_sport - Analog Devices BF6XX SPORT registers + * + * Copyright (c) 2012 Analog Devices Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef _BFIN_SPORT3_H_ +#define _BFIN_SPORT3_H_ + +#include <linux/types.h> + +#define SPORT_CTL_SPENPRI 0x00000001 /* Enable Primary Channel */ +#define SPORT_CTL_DTYPE 0x00000006 /* Data type select */ +#define SPORT_CTL_RJUSTIFY_ZFILL 0x00000000 /* DTYPE: MCM mode: Right-justify, zero-fill unused MSBs */ +#define SPORT_CTL_RJUSTIFY_SFILL 0x00000002 /* DTYPE: MCM mode: Right-justify, sign-extend unused MSBs */ +#define SPORT_CTL_USE_U_LAW 0x00000004 /* DTYPE: MCM mode: Compand using u-law */ +#define SPORT_CTL_USE_A_LAW 0x00000006 /* DTYPE: MCM mode: Compand using A-law */ +#define SPORT_CTL_LSBF 0x00000008 /* Serial bit endian select */ +#define SPORT_CTL_SLEN 0x000001F0 /* Serial Word length select */ +#define SPORT_CTL_PACK 0x00000200 /* 16-bit to 32-bit packing enable */ +#define SPORT_CTL_ICLK 0x00000400 /* Internal Clock Select */ +#define SPORT_CTL_OPMODE 0x00000800 /* Operation mode */ +#define SPORT_CTL_CKRE 0x00001000 /* Clock rising edge select */ +#define SPORT_CTL_FSR 0x00002000 /* Frame Sync required */ +#define SPORT_CTL_IFS 0x00004000 /* Internal Frame Sync select */ +#define SPORT_CTL_DIFS 0x00008000 /* Data-independent frame sync select */ +#define SPORT_CTL_LFS 0x00010000 /* Active low frame sync select */ +#define SPORT_CTL_LAFS 0x00020000 /* Late Transmit frame select */ +#define SPORT_CTL_RJUST 0x00040000 /* Right Justified mode select */ +#define SPORT_CTL_FSED 0x00080000 /* External frame sync edge select */ +#define SPORT_CTL_TFIEN 0x00100000 /* Transmit finish interrrupt enable select */ +#define SPORT_CTL_GCLKEN 0x00200000 /* Gated clock mode select */ +#define SPORT_CTL_SPENSEC 0x01000000 /* Enable secondary channel */ +#define SPORT_CTL_SPTRAN 0x02000000 /* Data direction control */ +#define SPORT_CTL_DERRSEC 0x04000000 /* Secondary channel error status */ +#define SPORT_CTL_DXSSEC 0x18000000 /* Secondary channel data buffer status */ +#define SPORT_CTL_SEC_EMPTY 0x00000000 /* DXSSEC: Empty */ +#define SPORT_CTL_SEC_PART_FULL 0x10000000 /* DXSSEC: Partially full */ +#define SPORT_CTL_SEC_FULL 0x18000000 /* DXSSEC: Full */ +#define SPORT_CTL_DERRPRI 0x20000000 /* Primary channel error status */ +#define SPORT_CTL_DXSPRI 0xC0000000 /* Primary channel data buffer status */ +#define SPORT_CTL_PRM_EMPTY 0x00000000 /* DXSPRI: Empty */ +#define SPORT_CTL_PRM_PART_FULL 0x80000000 /* DXSPRI: Partially full */ +#define SPORT_CTL_PRM_FULL 0xC0000000 /* DXSPRI: Full */ + +#define SPORT_DIV_CLKDIV 0x0000FFFF /* Clock divisor */ +#define SPORT_DIV_FSDIV 0xFFFF0000 /* Frame sync divisor */ + +#define SPORT_MCTL_MCE 0x00000001 /* Multichannel enable */ +#define SPORT_MCTL_MCPDE 0x00000004 /* Multichannel data packing select */ +#define SPORT_MCTL_MFD 0x000000F0 /* Multichannel frame delay */ +#define SPORT_MCTL_WSIZE 0x00007F00 /* Number of multichannel slots */ +#define SPORT_MCTL_WOFFSET 0x03FF0000 /* Window offset size */ + +#define SPORT_CNT_CLKCNT 0x0000FFFF /* Current state of clk div counter */ +#define SPORT_CNT_FSDIVCNT 0xFFFF0000 /* Current state of frame div counter */ + +#define SPORT_ERR_DERRPMSK 0x00000001 /* Primary channel data error interrupt enable */ +#define SPORT_ERR_DERRSMSK 0x00000002 /* Secondary channel data error interrupt enable */ +#define SPORT_ERR_FSERRMSK 0x00000004 /* Frame sync error interrupt enable */ +#define SPORT_ERR_DERRPSTAT 0x00000010 /* Primary channel data error status */ +#define SPORT_ERR_DERRSSTAT 0x00000020 /* Secondary channel data error status */ +#define SPORT_ERR_FSERRSTAT 0x00000040 /* Frame sync error status */ + +#define SPORT_MSTAT_CURCHAN 0x000003FF /* Channel which is being serviced in the multichannel operation */ + +#define SPORT_CTL2_FSMUXSEL 0x00000001 /* Frame Sync MUX Select */ +#define SPORT_CTL2_CKMUXSEL 0x00000002 /* Clock MUX Select */ +#define SPORT_CTL2_LBSEL 0x00000004 /* Loopback Select */ + +struct sport_register { + u32 spctl; + u32 div; + u32 spmctl; + u32 spcs0; + u32 spcs1; + u32 spcs2; + u32 spcs3; + u32 spcnt; + u32 sperrctl; + u32 spmstat; + u32 spctl2; + u32 txa; + u32 rxa; + u32 txb; + u32 rxb; + u32 revid; +}; + +struct bfin_snd_platform_data { + const unsigned short *pin_req; +}; + +#endif diff --git a/arch/blackfin/include/asm/bfin_twi.h b/arch/blackfin/include/asm/bfin_twi.h index e767d649dfc4..2f3339a47626 100644 --- a/arch/blackfin/include/asm/bfin_twi.h +++ b/arch/blackfin/include/asm/bfin_twi.h @@ -10,6 +10,7 @@ #define __ASM_BFIN_TWI_H__ #include <linux/types.h> +#include <linux/i2c.h> /* * All Blackfin system MMRs are padded to 32bits even if the register @@ -42,4 +43,145 @@ struct bfin_twi_regs { #undef __BFP +struct bfin_twi_iface { + int irq; + spinlock_t lock; + char read_write; + u8 command; + u8 *transPtr; + int readNum; + int writeNum; + int cur_mode; + int manual_stop; + int result; + struct i2c_adapter adap; + struct completion complete; + struct i2c_msg *pmsg; + int msg_num; + int cur_msg; + u16 saved_clkdiv; + u16 saved_control; + struct bfin_twi_regs *regs_base; +}; + +#define DEFINE_TWI_REG(reg_name, reg) \ +static inline u16 read_##reg_name(struct bfin_twi_iface *iface) \ + { return iface->regs_base->reg; } \ +static inline void write_##reg_name(struct bfin_twi_iface *iface, u16 v) \ + { iface->regs_base->reg = v; } + +DEFINE_TWI_REG(CLKDIV, clkdiv) +DEFINE_TWI_REG(CONTROL, control) +DEFINE_TWI_REG(SLAVE_CTL, slave_ctl) +DEFINE_TWI_REG(SLAVE_STAT, slave_stat) +DEFINE_TWI_REG(SLAVE_ADDR, slave_addr) +DEFINE_TWI_REG(MASTER_CTL, master_ctl) +DEFINE_TWI_REG(MASTER_STAT, master_stat) +DEFINE_TWI_REG(MASTER_ADDR, master_addr) +DEFINE_TWI_REG(INT_STAT, int_stat) +DEFINE_TWI_REG(INT_MASK, int_mask) +DEFINE_TWI_REG(FIFO_CTL, fifo_ctl) +DEFINE_TWI_REG(FIFO_STAT, fifo_stat) +DEFINE_TWI_REG(XMT_DATA8, xmt_data8) +DEFINE_TWI_REG(XMT_DATA16, xmt_data16) +#if !ANOMALY_05001001 +DEFINE_TWI_REG(RCV_DATA8, rcv_data8) +DEFINE_TWI_REG(RCV_DATA16, rcv_data16) +#else +static inline u16 read_RCV_DATA8(struct bfin_twi_iface *iface) +{ + u16 ret; + unsigned long flags; + + flags = hard_local_irq_save(); + ret = iface->regs_base->rcv_data8; + hard_local_irq_restore(flags); + + return ret; +} + +static inline u16 read_RCV_DATA16(struct bfin_twi_iface *iface) +{ + u16 ret; + unsigned long flags; + + flags = hard_local_irq_save(); + ret = iface->regs_base->rcv_data16; + hard_local_irq_restore(flags); + + return ret; +} +#endif + + +/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/ +/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */ +#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */ +#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */ + +/* TWI_PRESCALE Masks */ +#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */ +#define TWI_ENA 0x0080 /* TWI Enable */ +#define SCCB 0x0200 /* SCCB Compatibility Enable */ + +/* TWI_SLAVE_CTL Masks */ +#define SEN 0x0001 /* Slave Enable */ +#define SADD_LEN 0x0002 /* Slave Address Length */ +#define STDVAL 0x0004 /* Slave Transmit Data Valid */ +#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */ +#define GEN 0x0010 /* General Call Address Matching Enabled */ + +/* TWI_SLAVE_STAT Masks */ +#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */ +#define GCALL 0x0002 /* General Call Indicator */ + +/* TWI_MASTER_CTL Masks */ +#define MEN 0x0001 /* Master Mode Enable */ +#define MADD_LEN 0x0002 /* Master Address Length */ +#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */ +#define FAST 0x0008 /* Use Fast Mode Timing Specs */ +#define STOP 0x0010 /* Issue Stop Condition */ +#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */ +#define DCNT 0x3FC0 /* Data Bytes To Transfer */ +#define SDAOVR 0x4000 /* Serial Data Override */ +#define SCLOVR 0x8000 /* Serial Clock Override */ + +/* TWI_MASTER_STAT Masks */ +#define MPROG 0x0001 /* Master Transfer In Progress */ +#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */ +#define ANAK 0x0004 /* Address Not Acknowledged */ +#define DNAK 0x0008 /* Data Not Acknowledged */ +#define BUFRDERR 0x0010 /* Buffer Read Error */ +#define BUFWRERR 0x0020 /* Buffer Write Error */ +#define SDASEN 0x0040 /* Serial Data Sense */ +#define SCLSEN 0x0080 /* Serial Clock Sense */ +#define BUSBUSY 0x0100 /* Bus Busy Indicator */ + +/* TWI_INT_SRC and TWI_INT_ENABLE Masks */ +#define SINIT 0x0001 /* Slave Transfer Initiated */ +#define SCOMP 0x0002 /* Slave Transfer Complete */ +#define SERR 0x0004 /* Slave Transfer Error */ +#define SOVF 0x0008 /* Slave Overflow */ +#define MCOMP 0x0010 /* Master Transfer Complete */ +#define MERR 0x0020 /* Master Transfer Error */ +#define XMTSERV 0x0040 /* Transmit FIFO Service */ +#define RCVSERV 0x0080 /* Receive FIFO Service */ + +/* TWI_FIFO_CTRL Masks */ +#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */ +#define RCVFLUSH 0x0002 /* Receive Buffer Flush */ +#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */ +#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */ + +/* TWI_FIFO_STAT Masks */ +#define XMTSTAT 0x0003 /* Transmit FIFO Status */ +#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */ +#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */ +#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */ + +#define RCVSTAT 0x000C /* Receive FIFO Status */ +#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */ +#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */ +#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */ + #endif diff --git a/arch/blackfin/include/asm/blackfin.h b/arch/blackfin/include/asm/blackfin.h index 7be5368c0512..f111f366d758 100644 --- a/arch/blackfin/include/asm/blackfin.h +++ b/arch/blackfin/include/asm/blackfin.h @@ -63,20 +63,16 @@ static inline void CSYNC(void) #if ANOMALY_05000312 || ANOMALY_05000244 #define SSYNC(scratch) \ -do { \ cli scratch; \ nop; nop; nop; \ SSYNC; \ - sti scratch; \ -} while (0) + sti scratch; #define CSYNC(scratch) \ -do { \ cli scratch; \ nop; nop; nop; \ CSYNC; \ - sti scratch; \ -} while (0) + sti scratch; #else #define SSYNC(scratch) SSYNC; diff --git a/arch/blackfin/include/asm/clkdev.h b/arch/blackfin/include/asm/clkdev.h new file mode 100644 index 000000000000..9053beda8c50 --- /dev/null +++ b/arch/blackfin/include/asm/clkdev.h @@ -0,0 +1,14 @@ +#ifndef __ASM_CLKDEV__H_ +#define __ASM_CLKDEV__H_ + +#include <linux/slab.h> + +static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size) +{ + return kzalloc(size, GFP_KERNEL); +} + +#define __clk_put(clk) +#define __clk_get(clk) ({ 1; }) + +#endif diff --git a/arch/blackfin/include/asm/clocks.h b/arch/blackfin/include/asm/clocks.h index 6f0b61852f58..9b3c85b3c288 100644 --- a/arch/blackfin/include/asm/clocks.h +++ b/arch/blackfin/include/asm/clocks.h @@ -48,4 +48,27 @@ # define CONFIG_VCO_MULT 0 #endif +#include <linux/clk.h> + +struct clk_ops { + unsigned long (*get_rate)(struct clk *clk); + unsigned long (*round_rate)(struct clk *clk, unsigned long rate); + int (*set_rate)(struct clk *clk, unsigned long rate); + int (*enable)(struct clk *clk); + int (*disable)(struct clk *clk); +}; + +struct clk { + struct clk *parent; + const char *name; + unsigned long rate; + spinlock_t lock; + u32 flags; + const struct clk_ops *ops; + void __iomem *reg; + u32 mask; + u32 shift; +}; + +int clk_init(void); #endif diff --git a/arch/blackfin/include/asm/cplb.h b/arch/blackfin/include/asm/cplb.h index fda96261ed62..5c37f620c4b3 100644 --- a/arch/blackfin/include/asm/cplb.h +++ b/arch/blackfin/include/asm/cplb.h @@ -62,6 +62,10 @@ #define SIZE_4K 0x00001000 /* 4K */ #define SIZE_1M 0x00100000 /* 1M */ #define SIZE_4M 0x00400000 /* 4M */ +#define SIZE_16K 0x00004000 /* 16K */ +#define SIZE_64K 0x00010000 /* 64K */ +#define SIZE_16M 0x01000000 /* 16M */ +#define SIZE_64M 0x04000000 /* 64M */ #define MAX_CPLBS 16 diff --git a/arch/blackfin/include/asm/def_LPBlackfin.h b/arch/blackfin/include/asm/def_LPBlackfin.h index 823679011457..fe0ca03a1cb2 100644 --- a/arch/blackfin/include/asm/def_LPBlackfin.h +++ b/arch/blackfin/include/asm/def_LPBlackfin.h @@ -3,7 +3,7 @@ * * Copyright 2005-2008 Analog Devices Inc. * - * Licensed under the ADI BSD license or GPL-2 (or later). + * Licensed under the Clear BSD license or GPL-2 (or later). */ #ifndef _DEF_LPBLACKFIN_H @@ -622,6 +622,10 @@ do { \ #define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */ #define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */ #define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */ +#define PAGE_SIZE_16KB 0x00040000 /* 16 KB page size */ +#define PAGE_SIZE_64KB 0x00050000 /* 64 KB page size */ +#define PAGE_SIZE_16MB 0x00060000 /* 16 MB page size */ +#define PAGE_SIZE_64MB 0x00070000 /* 64 MB page size */ #define CPLB_L1SRAM 0x00000020 /* 0=SRAM mapped in L1, 0=SRAM not * mapped to L1 */ diff --git a/arch/blackfin/include/asm/dma.h b/arch/blackfin/include/asm/dma.h index dac0c97242bb..40e9c2bbc6e3 100644 --- a/arch/blackfin/include/asm/dma.h +++ b/arch/blackfin/include/asm/dma.h @@ -22,12 +22,22 @@ #define DATA_SIZE_8 0 #define DATA_SIZE_16 1 #define DATA_SIZE_32 2 +#ifdef CONFIG_BF60x +#define DATA_SIZE_64 3 +#endif #define DMA_FLOW_STOP 0 #define DMA_FLOW_AUTO 1 +#ifdef CONFIG_BF60x +#define DMA_FLOW_LIST 4 +#define DMA_FLOW_ARRAY 5 +#define DMA_FLOW_LIST_DEMAND 6 +#define DMA_FLOW_ARRAY_DEMAND 7 +#else #define DMA_FLOW_ARRAY 4 #define DMA_FLOW_SMALL 6 #define DMA_FLOW_LARGE 7 +#endif #define DIMENSION_LINEAR 0 #define DIMENSION_2D 1 @@ -36,26 +46,80 @@ #define DIR_WRITE 1 #define INTR_DISABLE 0 +#ifdef CONFIG_BF60x +#define INTR_ON_PERI 1 +#endif #define INTR_ON_BUF 2 #define INTR_ON_ROW 3 #define DMA_NOSYNC_KEEP_DMA_BUF 0 #define DMA_SYNC_RESTART 1 +#ifdef DMA_MMR_SIZE_32 +#define DMA_MMR_SIZE_TYPE long +#define DMA_MMR_READ bfin_read32 +#define DMA_MMR_WRITE bfin_write32 +#else +#define DMA_MMR_SIZE_TYPE short +#define DMA_MMR_READ bfin_read16 +#define DMA_MMR_WRITE bfin_write16 +#endif + +struct dma_desc_array { + unsigned long start_addr; + unsigned DMA_MMR_SIZE_TYPE cfg; + unsigned DMA_MMR_SIZE_TYPE x_count; + DMA_MMR_SIZE_TYPE x_modify; +} __attribute__((packed)); + struct dmasg { void *next_desc_addr; unsigned long start_addr; - unsigned short cfg; - unsigned short x_count; - short x_modify; - unsigned short y_count; - short y_modify; + unsigned DMA_MMR_SIZE_TYPE cfg; + unsigned DMA_MMR_SIZE_TYPE x_count; + DMA_MMR_SIZE_TYPE x_modify; + unsigned DMA_MMR_SIZE_TYPE y_count; + DMA_MMR_SIZE_TYPE y_modify; } __attribute__((packed)); struct dma_register { void *next_desc_ptr; /* DMA Next Descriptor Pointer register */ unsigned long start_addr; /* DMA Start address register */ +#ifdef CONFIG_BF60x + unsigned long cfg; /* DMA Configuration register */ + unsigned long x_count; /* DMA x_count register */ + + long x_modify; /* DMA x_modify register */ + + unsigned long y_count; /* DMA y_count register */ + + long y_modify; /* DMA y_modify register */ + + unsigned long reserved; + unsigned long reserved2; + + void *curr_desc_ptr; /* DMA Current Descriptor Pointer + register */ + void *prev_desc_ptr; /* DMA previous initial Descriptor Pointer + register */ + unsigned long curr_addr_ptr; /* DMA Current Address Pointer + register */ + unsigned long irq_status; /* DMA irq status register */ + + unsigned long curr_x_count; /* DMA Current x-count register */ + + unsigned long curr_y_count; /* DMA Current y-count register */ + + unsigned long reserved3; + + unsigned long bw_limit_count; /* DMA band width limit count register */ + unsigned long curr_bw_limit_count; /* DMA Current band width limit + count register */ + unsigned long bw_monitor_count; /* DMA band width limit count register */ + unsigned long curr_bw_monitor_count; /* DMA Current band width limit + count register */ +#else unsigned short cfg; /* DMA Configuration register */ unsigned short dummy1; /* DMA Configuration register */ @@ -92,6 +156,7 @@ struct dma_register { unsigned short dummy9; unsigned long reserved3; +#endif }; @@ -131,23 +196,23 @@ static inline void set_dma_curr_desc_addr(unsigned int channel, void *addr) { dma_ch[channel].regs->curr_desc_ptr = addr; } -static inline void set_dma_x_count(unsigned int channel, unsigned short x_count) +static inline void set_dma_x_count(unsigned int channel, unsigned DMA_MMR_SIZE_TYPE x_count) { dma_ch[channel].regs->x_count = x_count; } -static inline void set_dma_y_count(unsigned int channel, unsigned short y_count) +static inline void set_dma_y_count(unsigned int channel, unsigned DMA_MMR_SIZE_TYPE y_count) { dma_ch[channel].regs->y_count = y_count; } -static inline void set_dma_x_modify(unsigned int channel, short x_modify) +static inline void set_dma_x_modify(unsigned int channel, DMA_MMR_SIZE_TYPE x_modify) { dma_ch[channel].regs->x_modify = x_modify; } -static inline void set_dma_y_modify(unsigned int channel, short y_modify) +static inline void set_dma_y_modify(unsigned int channel, DMA_MMR_SIZE_TYPE y_modify) { dma_ch[channel].regs->y_modify = y_modify; } -static inline void set_dma_config(unsigned int channel, unsigned short config) +static inline void set_dma_config(unsigned int channel, unsigned DMA_MMR_SIZE_TYPE config) { dma_ch[channel].regs->cfg = config; } @@ -156,23 +221,55 @@ static inline void set_dma_curr_addr(unsigned int channel, unsigned long addr) dma_ch[channel].regs->curr_addr_ptr = addr; } -static inline unsigned short +#ifdef CONFIG_BF60x +static inline unsigned long +set_bfin_dma_config2(char direction, char flow_mode, char intr_mode, + char dma_mode, char mem_width, char syncmode, char peri_width) +{ + unsigned long config = 0; + + switch (intr_mode) { + case INTR_ON_BUF: + if (dma_mode == DIMENSION_2D) + config = DI_EN_Y; + else + config = DI_EN_X; + break; + case INTR_ON_ROW: + config = DI_EN_X; + break; + case INTR_ON_PERI: + config = DI_EN_P; + break; + }; + + return config | (direction << 1) | (mem_width << 8) | (dma_mode << 26) | + (flow_mode << 12) | (syncmode << 2) | (peri_width << 4); +} +#endif + +static inline unsigned DMA_MMR_SIZE_TYPE set_bfin_dma_config(char direction, char flow_mode, - char intr_mode, char dma_mode, char width, char syncmode) + char intr_mode, char dma_mode, char mem_width, char syncmode) { - return (direction << 1) | (width << 2) | (dma_mode << 4) | +#ifdef CONFIG_BF60x + return set_bfin_dma_config2(direction, flow_mode, intr_mode, dma_mode, + mem_width, syncmode, mem_width); +#else + return (direction << 1) | (mem_width << 2) | (dma_mode << 4) | (intr_mode << 6) | (flow_mode << 12) | (syncmode << 5); +#endif } -static inline unsigned short get_dma_curr_irqstat(unsigned int channel) +static inline unsigned DMA_MMR_SIZE_TYPE get_dma_curr_irqstat(unsigned int channel) { return dma_ch[channel].regs->irq_status; } -static inline unsigned short get_dma_curr_xcount(unsigned int channel) +static inline unsigned DMA_MMR_SIZE_TYPE get_dma_curr_xcount(unsigned int channel) { return dma_ch[channel].regs->curr_x_count; } -static inline unsigned short get_dma_curr_ycount(unsigned int channel) +static inline unsigned DMA_MMR_SIZE_TYPE get_dma_curr_ycount(unsigned int channel) { return dma_ch[channel].regs->curr_y_count; } @@ -184,7 +281,7 @@ static inline void *get_dma_curr_desc_ptr(unsigned int channel) { return dma_ch[channel].regs->curr_desc_ptr; } -static inline unsigned short get_dma_config(unsigned int channel) +static inline unsigned DMA_MMR_SIZE_TYPE get_dma_config(unsigned int channel) { return dma_ch[channel].regs->cfg; } @@ -203,8 +300,8 @@ static inline void set_dma_sg(unsigned int channel, struct dmasg *sg, int ndsize dma_ch[channel].regs->next_desc_ptr = sg; dma_ch[channel].regs->cfg = - (dma_ch[channel].regs->cfg & ~(0xf << 8)) | - ((ndsize & 0xf) << 8); + (dma_ch[channel].regs->cfg & ~NDSIZE) | + ((ndsize << NDSIZE_OFFSET) & NDSIZE); } static inline int dma_channel_active(unsigned int channel) @@ -239,7 +336,7 @@ static inline void dma_enable_irq(unsigned int channel) } static inline void clear_dma_irqstat(unsigned int channel) { - dma_ch[channel].regs->irq_status = DMA_DONE | DMA_ERR; + dma_ch[channel].regs->irq_status = DMA_DONE | DMA_ERR | DMA_PIRQ; } void *dma_memcpy(void *dest, const void *src, size_t count); diff --git a/arch/blackfin/include/asm/dpmc.h b/arch/blackfin/include/asm/dpmc.h index c4ec959dad78..e91eae8330a6 100644 --- a/arch/blackfin/include/asm/dpmc.h +++ b/arch/blackfin/include/asm/dpmc.h @@ -9,6 +9,651 @@ #ifndef _BLACKFIN_DPMC_H_ #define _BLACKFIN_DPMC_H_ +#ifdef __ASSEMBLY__ +#define PM_REG0 R7 +#define PM_REG1 R6 +#define PM_REG2 R5 +#define PM_REG3 R4 +#define PM_REG4 R3 +#define PM_REG5 R2 +#define PM_REG6 R1 +#define PM_REG7 R0 +#define PM_REG8 P5 +#define PM_REG9 P4 +#define PM_REG10 P3 +#define PM_REG11 P2 +#define PM_REG12 P1 +#define PM_REG13 P0 + +#define PM_REGSET0 R7:7 +#define PM_REGSET1 R7:6 +#define PM_REGSET2 R7:5 +#define PM_REGSET3 R7:4 +#define PM_REGSET4 R7:3 +#define PM_REGSET5 R7:2 +#define PM_REGSET6 R7:1 +#define PM_REGSET7 R7:0 +#define PM_REGSET8 R7:0, P5:5 +#define PM_REGSET9 R7:0, P5:4 +#define PM_REGSET10 R7:0, P5:3 +#define PM_REGSET11 R7:0, P5:2 +#define PM_REGSET12 R7:0, P5:1 +#define PM_REGSET13 R7:0, P5:0 + +#define _PM_PUSH(n, x, w, base) PM_REG##n = w[FP + ((x) - (base))]; +#define _PM_POP(n, x, w, base) w[FP + ((x) - (base))] = PM_REG##n; +#define PM_PUSH_SYNC(n) [--sp] = (PM_REGSET##n); +#define PM_POP_SYNC(n) (PM_REGSET##n) = [sp++]; +#define PM_PUSH(n, x) PM_REG##n = [FP++]; +#define PM_POP(n, x) [FP--] = PM_REG##n; +#define PM_CORE_PUSH(n, x) _PM_PUSH(n, x, , COREMMR_BASE) +#define PM_CORE_POP(n, x) _PM_POP(n, x, , COREMMR_BASE) +#define PM_SYS_PUSH(n, x) _PM_PUSH(n, x, , SYSMMR_BASE) +#define PM_SYS_POP(n, x) _PM_POP(n, x, , SYSMMR_BASE) +#define PM_SYS_PUSH16(n, x) _PM_PUSH(n, x, w, SYSMMR_BASE) +#define PM_SYS_POP16(n, x) _PM_POP(n, x, w, SYSMMR_BASE) + + .macro bfin_init_pm_bench_cycles +#ifdef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH + R4 = 0; + CYCLES = R4; + CYCLES2 = R4; + R4 = SYSCFG; + BITSET(R4, 1); + SYSCFG = R4; +#endif + .endm + + .macro bfin_cpu_reg_save + /* + * Save the core regs early so we can blow them away when + * saving/restoring MMR states + */ + [--sp] = (R7:0, P5:0); + [--sp] = fp; + [--sp] = usp; + + [--sp] = i0; + [--sp] = i1; + [--sp] = i2; + [--sp] = i3; + + [--sp] = m0; + [--sp] = m1; + [--sp] = m2; + [--sp] = m3; + + [--sp] = l0; + [--sp] = l1; + [--sp] = l2; + [--sp] = l3; + + [--sp] = b0; + [--sp] = b1; + [--sp] = b2; + [--sp] = b3; + [--sp] = a0.x; + [--sp] = a0.w; + [--sp] = a1.x; + [--sp] = a1.w; + + [--sp] = LC0; + [--sp] = LC1; + [--sp] = LT0; + [--sp] = LT1; + [--sp] = LB0; + [--sp] = LB1; + + /* We can't push RETI directly as that'll change IPEND[4] */ + r7 = RETI; + [--sp] = RETS; + [--sp] = ASTAT; +#ifndef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH + [--sp] = CYCLES; + [--sp] = CYCLES2; +#endif + [--sp] = SYSCFG; + [--sp] = RETX; + [--sp] = SEQSTAT; + [--sp] = r7; + + /* Save first func arg in M3 */ + M3 = R0; + .endm + + .macro bfin_cpu_reg_restore + /* Restore Core Registers */ + RETI = [sp++]; + SEQSTAT = [sp++]; + RETX = [sp++]; + SYSCFG = [sp++]; +#ifndef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH + CYCLES2 = [sp++]; + CYCLES = [sp++]; +#endif + ASTAT = [sp++]; + RETS = [sp++]; + + LB1 = [sp++]; + LB0 = [sp++]; + LT1 = [sp++]; + LT0 = [sp++]; + LC1 = [sp++]; + LC0 = [sp++]; + + a1.w = [sp++]; + a1.x = [sp++]; + a0.w = [sp++]; + a0.x = [sp++]; + b3 = [sp++]; + b2 = [sp++]; + b1 = [sp++]; + b0 = [sp++]; + + l3 = [sp++]; + l2 = [sp++]; + l1 = [sp++]; + l0 = [sp++]; + + m3 = [sp++]; + m2 = [sp++]; + m1 = [sp++]; + m0 = [sp++]; + + i3 = [sp++]; + i2 = [sp++]; + i1 = [sp++]; + i0 = [sp++]; + + usp = [sp++]; + fp = [sp++]; + (R7:0, P5:0) = [sp++]; + + .endm + + .macro bfin_sys_mmr_save + /* Save system MMRs */ + FP.H = hi(SYSMMR_BASE); + FP.L = lo(SYSMMR_BASE); +#ifdef SIC_IMASK0 + PM_SYS_PUSH(0, SIC_IMASK0) + PM_SYS_PUSH(1, SIC_IMASK1) +# ifdef SIC_IMASK2 + PM_SYS_PUSH(2, SIC_IMASK2) +# endif +#else +# ifdef SIC_IMASK + PM_SYS_PUSH(0, SIC_IMASK) +# endif +#endif + +#ifdef SIC_IAR0 + PM_SYS_PUSH(3, SIC_IAR0) + PM_SYS_PUSH(4, SIC_IAR1) + PM_SYS_PUSH(5, SIC_IAR2) +#endif +#ifdef SIC_IAR3 + PM_SYS_PUSH(6, SIC_IAR3) +#endif +#ifdef SIC_IAR4 + PM_SYS_PUSH(7, SIC_IAR4) + PM_SYS_PUSH(8, SIC_IAR5) + PM_SYS_PUSH(9, SIC_IAR6) +#endif +#ifdef SIC_IAR7 + PM_SYS_PUSH(10, SIC_IAR7) +#endif +#ifdef SIC_IAR8 + PM_SYS_PUSH(11, SIC_IAR8) + PM_SYS_PUSH(12, SIC_IAR9) + PM_SYS_PUSH(13, SIC_IAR10) +#endif + PM_PUSH_SYNC(13) +#ifdef SIC_IAR11 + PM_SYS_PUSH(0, SIC_IAR11) +#endif + +#ifdef SIC_IWR + PM_SYS_PUSH(1, SIC_IWR) +#endif +#ifdef SIC_IWR0 + PM_SYS_PUSH(1, SIC_IWR0) +#endif +#ifdef SIC_IWR1 + PM_SYS_PUSH(2, SIC_IWR1) +#endif +#ifdef SIC_IWR2 + PM_SYS_PUSH(3, SIC_IWR2) +#endif + +#ifdef PINT0_ASSIGN + PM_SYS_PUSH(4, PINT0_MASK_SET) + PM_SYS_PUSH(5, PINT1_MASK_SET) + PM_SYS_PUSH(6, PINT2_MASK_SET) + PM_SYS_PUSH(7, PINT3_MASK_SET) + PM_SYS_PUSH(8, PINT0_ASSIGN) + PM_SYS_PUSH(9, PINT1_ASSIGN) + PM_SYS_PUSH(10, PINT2_ASSIGN) + PM_SYS_PUSH(11, PINT3_ASSIGN) + PM_SYS_PUSH(12, PINT0_INVERT_SET) + PM_SYS_PUSH(13, PINT1_INVERT_SET) + PM_PUSH_SYNC(13) + PM_SYS_PUSH(0, PINT2_INVERT_SET) + PM_SYS_PUSH(1, PINT3_INVERT_SET) + PM_SYS_PUSH(2, PINT0_EDGE_SET) + PM_SYS_PUSH(3, PINT1_EDGE_SET) + PM_SYS_PUSH(4, PINT2_EDGE_SET) + PM_SYS_PUSH(5, PINT3_EDGE_SET) +#endif + +#ifdef SYSCR + PM_SYS_PUSH16(6, SYSCR) +#endif + +#ifdef EBIU_AMGCTL + PM_SYS_PUSH16(7, EBIU_AMGCTL) + PM_SYS_PUSH(8, EBIU_AMBCTL0) + PM_SYS_PUSH(9, EBIU_AMBCTL1) +#endif +#ifdef EBIU_FCTL + PM_SYS_PUSH(10, EBIU_MBSCTL) + PM_SYS_PUSH(11, EBIU_MODE) + PM_SYS_PUSH(12, EBIU_FCTL) + PM_PUSH_SYNC(12) +#else + PM_PUSH_SYNC(9) +#endif + .endm + + + .macro bfin_sys_mmr_restore +/* Restore System MMRs */ + FP.H = hi(SYSMMR_BASE); + FP.L = lo(SYSMMR_BASE); + +#ifdef EBIU_FCTL + PM_POP_SYNC(12) + PM_SYS_POP(12, EBIU_FCTL) + PM_SYS_POP(11, EBIU_MODE) + PM_SYS_POP(10, EBIU_MBSCTL) +#else + PM_POP_SYNC(9) +#endif + +#ifdef EBIU_AMBCTL + PM_SYS_POP(9, EBIU_AMBCTL1) + PM_SYS_POP(8, EBIU_AMBCTL0) + PM_SYS_POP16(7, EBIU_AMGCTL) +#endif + +#ifdef SYSCR + PM_SYS_POP16(6, SYSCR) +#endif + +#ifdef PINT0_ASSIGN + PM_SYS_POP(5, PINT3_EDGE_SET) + PM_SYS_POP(4, PINT2_EDGE_SET) + PM_SYS_POP(3, PINT1_EDGE_SET) + PM_SYS_POP(2, PINT0_EDGE_SET) + PM_SYS_POP(1, PINT3_INVERT_SET) + PM_SYS_POP(0, PINT2_INVERT_SET) + PM_POP_SYNC(13) + PM_SYS_POP(13, PINT1_INVERT_SET) + PM_SYS_POP(12, PINT0_INVERT_SET) + PM_SYS_POP(11, PINT3_ASSIGN) + PM_SYS_POP(10, PINT2_ASSIGN) + PM_SYS_POP(9, PINT1_ASSIGN) + PM_SYS_POP(8, PINT0_ASSIGN) + PM_SYS_POP(7, PINT3_MASK_SET) + PM_SYS_POP(6, PINT2_MASK_SET) + PM_SYS_POP(5, PINT1_MASK_SET) + PM_SYS_POP(4, PINT0_MASK_SET) +#endif + +#ifdef SIC_IWR2 + PM_SYS_POP(3, SIC_IWR2) +#endif +#ifdef SIC_IWR1 + PM_SYS_POP(2, SIC_IWR1) +#endif +#ifdef SIC_IWR0 + PM_SYS_POP(1, SIC_IWR0) +#endif +#ifdef SIC_IWR + PM_SYS_POP(1, SIC_IWR) +#endif + +#ifdef SIC_IAR11 + PM_SYS_POP(0, SIC_IAR11) +#endif + PM_POP_SYNC(13) +#ifdef SIC_IAR8 + PM_SYS_POP(13, SIC_IAR10) + PM_SYS_POP(12, SIC_IAR9) + PM_SYS_POP(11, SIC_IAR8) +#endif +#ifdef SIC_IAR7 + PM_SYS_POP(10, SIC_IAR7) +#endif +#ifdef SIC_IAR6 + PM_SYS_POP(9, SIC_IAR6) + PM_SYS_POP(8, SIC_IAR5) + PM_SYS_POP(7, SIC_IAR4) +#endif +#ifdef SIC_IAR3 + PM_SYS_POP(6, SIC_IAR3) +#endif +#ifdef SIC_IAR0 + PM_SYS_POP(5, SIC_IAR2) + PM_SYS_POP(4, SIC_IAR1) + PM_SYS_POP(3, SIC_IAR0) +#endif +#ifdef SIC_IMASK0 +# ifdef SIC_IMASK2 + PM_SYS_POP(2, SIC_IMASK2) +# endif + PM_SYS_POP(1, SIC_IMASK1) + PM_SYS_POP(0, SIC_IMASK0) +#else +# ifdef SIC_IMASK + PM_SYS_POP(0, SIC_IMASK) +# endif +#endif + .endm + + .macro bfin_core_mmr_save + /* Save Core MMRs */ + I0.H = hi(COREMMR_BASE); + I0.L = lo(COREMMR_BASE); + I1 = I0; + I2 = I0; + I3 = I0; + B0 = I0; + B1 = I0; + B2 = I0; + B3 = I0; + I1.L = lo(DCPLB_ADDR0); + I2.L = lo(DCPLB_DATA0); + I3.L = lo(ICPLB_ADDR0); + B0.L = lo(ICPLB_DATA0); + B1.L = lo(EVT2); + B2.L = lo(IMASK); + B3.L = lo(TCNTL); + + /* Event Vectors */ + FP = B1; + PM_PUSH(0, EVT2) + PM_PUSH(1, EVT3) + FP += 4; /* EVT4 */ + PM_PUSH(2, EVT5) + PM_PUSH(3, EVT6) + PM_PUSH(4, EVT7) + PM_PUSH(5, EVT8) + PM_PUSH_SYNC(5) + + PM_PUSH(0, EVT9) + PM_PUSH(1, EVT10) + PM_PUSH(2, EVT11) + PM_PUSH(3, EVT12) + PM_PUSH(4, EVT13) + PM_PUSH(5, EVT14) + PM_PUSH(6, EVT15) + + /* CEC */ + FP = B2; + PM_PUSH(7, IMASK) + FP += 4; /* IPEND */ + PM_PUSH(8, ILAT) + PM_PUSH(9, IPRIO) + + /* Core Timer */ + FP = B3; + PM_PUSH(10, TCNTL) + PM_PUSH(11, TPERIOD) + PM_PUSH(12, TSCALE) + PM_PUSH(13, TCOUNT) + PM_PUSH_SYNC(13) + + /* Misc non-contiguous registers */ + FP = I0; + PM_CORE_PUSH(0, DMEM_CONTROL); + PM_CORE_PUSH(1, IMEM_CONTROL); + PM_CORE_PUSH(2, TBUFCTL); + PM_PUSH_SYNC(2) + + /* DCPLB Addr */ + FP = I1; + PM_PUSH(0, DCPLB_ADDR0) + PM_PUSH(1, DCPLB_ADDR1) + PM_PUSH(2, DCPLB_ADDR2) + PM_PUSH(3, DCPLB_ADDR3) + PM_PUSH(4, DCPLB_ADDR4) + PM_PUSH(5, DCPLB_ADDR5) + PM_PUSH(6, DCPLB_ADDR6) + PM_PUSH(7, DCPLB_ADDR7) + PM_PUSH(8, DCPLB_ADDR8) + PM_PUSH(9, DCPLB_ADDR9) + PM_PUSH(10, DCPLB_ADDR10) + PM_PUSH(11, DCPLB_ADDR11) + PM_PUSH(12, DCPLB_ADDR12) + PM_PUSH(13, DCPLB_ADDR13) + PM_PUSH_SYNC(13) + PM_PUSH(0, DCPLB_ADDR14) + PM_PUSH(1, DCPLB_ADDR15) + + /* DCPLB Data */ + FP = I2; + PM_PUSH(2, DCPLB_DATA0) + PM_PUSH(3, DCPLB_DATA1) + PM_PUSH(4, DCPLB_DATA2) + PM_PUSH(5, DCPLB_DATA3) + PM_PUSH(6, DCPLB_DATA4) + PM_PUSH(7, DCPLB_DATA5) + PM_PUSH(8, DCPLB_DATA6) + PM_PUSH(9, DCPLB_DATA7) + PM_PUSH(10, DCPLB_DATA8) + PM_PUSH(11, DCPLB_DATA9) + PM_PUSH(12, DCPLB_DATA10) + PM_PUSH(13, DCPLB_DATA11) + PM_PUSH_SYNC(13) + PM_PUSH(0, DCPLB_DATA12) + PM_PUSH(1, DCPLB_DATA13) + PM_PUSH(2, DCPLB_DATA14) + PM_PUSH(3, DCPLB_DATA15) + + /* ICPLB Addr */ + FP = I3; + PM_PUSH(4, ICPLB_ADDR0) + PM_PUSH(5, ICPLB_ADDR1) + PM_PUSH(6, ICPLB_ADDR2) + PM_PUSH(7, ICPLB_ADDR3) + PM_PUSH(8, ICPLB_ADDR4) + PM_PUSH(9, ICPLB_ADDR5) + PM_PUSH(10, ICPLB_ADDR6) + PM_PUSH(11, ICPLB_ADDR7) + PM_PUSH(12, ICPLB_ADDR8) + PM_PUSH(13, ICPLB_ADDR9) + PM_PUSH_SYNC(13) + PM_PUSH(0, ICPLB_ADDR10) + PM_PUSH(1, ICPLB_ADDR11) + PM_PUSH(2, ICPLB_ADDR12) + PM_PUSH(3, ICPLB_ADDR13) + PM_PUSH(4, ICPLB_ADDR14) + PM_PUSH(5, ICPLB_ADDR15) + + /* ICPLB Data */ + FP = B0; + PM_PUSH(6, ICPLB_DATA0) + PM_PUSH(7, ICPLB_DATA1) + PM_PUSH(8, ICPLB_DATA2) + PM_PUSH(9, ICPLB_DATA3) + PM_PUSH(10, ICPLB_DATA4) + PM_PUSH(11, ICPLB_DATA5) + PM_PUSH(12, ICPLB_DATA6) + PM_PUSH(13, ICPLB_DATA7) + PM_PUSH_SYNC(13) + PM_PUSH(0, ICPLB_DATA8) + PM_PUSH(1, ICPLB_DATA9) + PM_PUSH(2, ICPLB_DATA10) + PM_PUSH(3, ICPLB_DATA11) + PM_PUSH(4, ICPLB_DATA12) + PM_PUSH(5, ICPLB_DATA13) + PM_PUSH(6, ICPLB_DATA14) + PM_PUSH(7, ICPLB_DATA15) + PM_PUSH_SYNC(7) + .endm + + .macro bfin_core_mmr_restore + /* Restore Core MMRs */ + I0.H = hi(COREMMR_BASE); + I0.L = lo(COREMMR_BASE); + I1 = I0; + I2 = I0; + I3 = I0; + B0 = I0; + B1 = I0; + B2 = I0; + B3 = I0; + I1.L = lo(DCPLB_ADDR15); + I2.L = lo(DCPLB_DATA15); + I3.L = lo(ICPLB_ADDR15); + B0.L = lo(ICPLB_DATA15); + B1.L = lo(EVT15); + B2.L = lo(IPRIO); + B3.L = lo(TCOUNT); + + /* ICPLB Data */ + FP = B0; + PM_POP_SYNC(7) + PM_POP(7, ICPLB_DATA15) + PM_POP(6, ICPLB_DATA14) + PM_POP(5, ICPLB_DATA13) + PM_POP(4, ICPLB_DATA12) + PM_POP(3, ICPLB_DATA11) + PM_POP(2, ICPLB_DATA10) + PM_POP(1, ICPLB_DATA9) + PM_POP(0, ICPLB_DATA8) + PM_POP_SYNC(13) + PM_POP(13, ICPLB_DATA7) + PM_POP(12, ICPLB_DATA6) + PM_POP(11, ICPLB_DATA5) + PM_POP(10, ICPLB_DATA4) + PM_POP(9, ICPLB_DATA3) + PM_POP(8, ICPLB_DATA2) + PM_POP(7, ICPLB_DATA1) + PM_POP(6, ICPLB_DATA0) + + /* ICPLB Addr */ + FP = I3; + PM_POP(5, ICPLB_ADDR15) + PM_POP(4, ICPLB_ADDR14) + PM_POP(3, ICPLB_ADDR13) + PM_POP(2, ICPLB_ADDR12) + PM_POP(1, ICPLB_ADDR11) + PM_POP(0, ICPLB_ADDR10) + PM_POP_SYNC(13) + PM_POP(13, ICPLB_ADDR9) + PM_POP(12, ICPLB_ADDR8) + PM_POP(11, ICPLB_ADDR7) + PM_POP(10, ICPLB_ADDR6) + PM_POP(9, ICPLB_ADDR5) + PM_POP(8, ICPLB_ADDR4) + PM_POP(7, ICPLB_ADDR3) + PM_POP(6, ICPLB_ADDR2) + PM_POP(5, ICPLB_ADDR1) + PM_POP(4, ICPLB_ADDR0) + + /* DCPLB Data */ + FP = I2; + PM_POP(3, DCPLB_DATA15) + PM_POP(2, DCPLB_DATA14) + PM_POP(1, DCPLB_DATA13) + PM_POP(0, DCPLB_DATA12) + PM_POP_SYNC(13) + PM_POP(13, DCPLB_DATA11) + PM_POP(12, DCPLB_DATA10) + PM_POP(11, DCPLB_DATA9) + PM_POP(10, DCPLB_DATA8) + PM_POP(9, DCPLB_DATA7) + PM_POP(8, DCPLB_DATA6) + PM_POP(7, DCPLB_DATA5) + PM_POP(6, DCPLB_DATA4) + PM_POP(5, DCPLB_DATA3) + PM_POP(4, DCPLB_DATA2) + PM_POP(3, DCPLB_DATA1) + PM_POP(2, DCPLB_DATA0) + + /* DCPLB Addr */ + FP = I1; + PM_POP(1, DCPLB_ADDR15) + PM_POP(0, DCPLB_ADDR14) + PM_POP_SYNC(13) + PM_POP(13, DCPLB_ADDR13) + PM_POP(12, DCPLB_ADDR12) + PM_POP(11, DCPLB_ADDR11) + PM_POP(10, DCPLB_ADDR10) + PM_POP(9, DCPLB_ADDR9) + PM_POP(8, DCPLB_ADDR8) + PM_POP(7, DCPLB_ADDR7) + PM_POP(6, DCPLB_ADDR6) + PM_POP(5, DCPLB_ADDR5) + PM_POP(4, DCPLB_ADDR4) + PM_POP(3, DCPLB_ADDR3) + PM_POP(2, DCPLB_ADDR2) + PM_POP(1, DCPLB_ADDR1) + PM_POP(0, DCPLB_ADDR0) + + + /* Misc non-contiguous registers */ + + /* icache & dcache will enable later + drop IMEM_CONTROL, DMEM_CONTROL pop + */ + FP = I0; + PM_POP_SYNC(2) + PM_CORE_POP(2, TBUFCTL) + PM_CORE_POP(1, IMEM_CONTROL) + PM_CORE_POP(0, DMEM_CONTROL) + + /* Core Timer */ + FP = B3; + R0 = 0x1; + [FP - 0xC] = R0; + + PM_POP_SYNC(13) + FP = B3; + PM_POP(13, TCOUNT) + PM_POP(12, TSCALE) + PM_POP(11, TPERIOD) + PM_POP(10, TCNTL) + + /* CEC */ + FP = B2; + PM_POP(9, IPRIO) + PM_POP(8, ILAT) + FP += -4; /* IPEND */ + PM_POP(7, IMASK) + + /* Event Vectors */ + FP = B1; + PM_POP(6, EVT15) + PM_POP(5, EVT14) + PM_POP(4, EVT13) + PM_POP(3, EVT12) + PM_POP(2, EVT11) + PM_POP(1, EVT10) + PM_POP(0, EVT9) + PM_POP_SYNC(5) + PM_POP(5, EVT8) + PM_POP(4, EVT7) + PM_POP(3, EVT6) + PM_POP(2, EVT5) + FP += -4; /* EVT4 */ + PM_POP(1, EVT3) + PM_POP(0, EVT2) + .endm +#endif + #include <mach/pll.h> /* PLL_CTL Masks */ @@ -98,6 +743,16 @@ #define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ #endif +#ifdef CONFIG_BF60x +#define PA15WE 0x00000001 /* Allow Wake-Up from PA15 */ +#define PB15WE 0x00000002 /* Allow Wake-Up from PB15 */ +#define PC15WE 0x00000004 /* Allow Wake-Up from PC15 */ +#define PD06WE 0x00000008 /* Allow Wake-Up from PD06(ETH0_PHYINT) */ +#define PE12WE 0x00000010 /* Allow Wake-Up from PE12(ETH1_PHYINT, PUSH BUTTON) */ +#define PG04WE 0x00000020 /* Allow Wake-Up from PG04(CAN0_RX) */ +#define PG13WE 0x00000040 /* Allow Wake-Up from PG13 */ +#define USBWE 0x00000080 /* Allow Wake-Up from (USB) */ +#else #define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */ #define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */ #define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */ @@ -113,6 +768,7 @@ #else #define USBWE 0x0800 /* Enable USB Wakeup From Hibernate */ #endif +#endif #ifndef __ASSEMBLY__ diff --git a/arch/blackfin/include/asm/fixed_code.h b/arch/blackfin/include/asm/fixed_code.h index 73fe53e7fd24..5395088b2d0e 100644 --- a/arch/blackfin/include/asm/fixed_code.h +++ b/arch/blackfin/include/asm/fixed_code.h @@ -29,24 +29,28 @@ extern void sigreturn_stub(void); #endif #endif -#define FIXED_CODE_START 0x400 +#ifndef CONFIG_PHY_RAM_BASE_ADDRESS +#define CONFIG_PHY_RAM_BASE_ADDRESS 0x0 +#endif + +#define FIXED_CODE_START (CONFIG_PHY_RAM_BASE_ADDRESS + 0x400) -#define SIGRETURN_STUB 0x400 +#define SIGRETURN_STUB (CONFIG_PHY_RAM_BASE_ADDRESS + 0x400) -#define ATOMIC_SEQS_START 0x410 +#define ATOMIC_SEQS_START (CONFIG_PHY_RAM_BASE_ADDRESS + 0x410) -#define ATOMIC_XCHG32 0x410 -#define ATOMIC_CAS32 0x420 -#define ATOMIC_ADD32 0x430 -#define ATOMIC_SUB32 0x440 -#define ATOMIC_IOR32 0x450 -#define ATOMIC_AND32 0x460 -#define ATOMIC_XOR32 0x470 +#define ATOMIC_XCHG32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x410) +#define ATOMIC_CAS32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x420) +#define ATOMIC_ADD32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x430) +#define ATOMIC_SUB32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x440) +#define ATOMIC_IOR32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x450) +#define ATOMIC_AND32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x460) +#define ATOMIC_XOR32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x470) -#define ATOMIC_SEQS_END 0x480 +#define ATOMIC_SEQS_END (CONFIG_PHY_RAM_BASE_ADDRESS + 0x480) -#define SAFE_USER_INSTRUCTION 0x480 +#define SAFE_USER_INSTRUCTION (CONFIG_PHY_RAM_BASE_ADDRESS + 0x480) -#define FIXED_CODE_END 0x490 +#define FIXED_CODE_END (CONFIG_PHY_RAM_BASE_ADDRESS + 0x490) #endif diff --git a/arch/blackfin/include/asm/gpio.h b/arch/blackfin/include/asm/gpio.h index 12d3571b5232..3d84d96f7c2c 100644 --- a/arch/blackfin/include/asm/gpio.h +++ b/arch/blackfin/include/asm/gpio.h @@ -26,6 +26,7 @@ #ifndef __ASSEMBLY__ #include <linux/compiler.h> +#include <linux/gpio.h> /*********************************************************** * @@ -244,6 +245,49 @@ static inline int gpio_set_debounce(unsigned gpio, unsigned debounce) return -EINVAL; } +static inline int gpio_request_one(unsigned gpio, unsigned long flags, const char *label) +{ + int err; + + err = bfin_gpio_request(gpio, label); + if (err) + return err; + + if (flags & GPIOF_DIR_IN) + err = bfin_gpio_direction_input(gpio); + else + err = bfin_gpio_direction_output(gpio, + (flags & GPIOF_INIT_HIGH) ? 1 : 0); + + if (err) + bfin_gpio_free(gpio); + + return err; +} + +static inline int gpio_request_array(const struct gpio *array, size_t num) +{ + int i, err; + + for (i = 0; i < num; i++, array++) { + err = gpio_request_one(array->gpio, array->flags, array->label); + if (err) + goto err_free; + } + return 0; + +err_free: + while (i--) + bfin_gpio_free((--array)->gpio); + return err; +} + +static inline void gpio_free_array(const struct gpio *array, size_t num) +{ + while (num--) + bfin_gpio_free((array++)->gpio); +} + static inline int __gpio_get_value(unsigned gpio) { return bfin_gpio_get_value(gpio); diff --git a/arch/blackfin/include/asm/gptimers.h b/arch/blackfin/include/asm/gptimers.h index 38bddcb190c8..381e3d621a4c 100644 --- a/arch/blackfin/include/asm/gptimers.h +++ b/arch/blackfin/include/asm/gptimers.h @@ -44,6 +44,13 @@ # define TIMER_GROUP2 1 #endif /* + * BF609: 8 timers: + */ +#if defined(CONFIG_BF60x) +# define MAX_BLACKFIN_GPTIMERS 8 +# define TIMER0_GROUP_REG TIMER_RUN +#endif +/* * All others: 3 timers: */ #define TIMER_GROUP1 0 @@ -104,6 +111,72 @@ # define FS2_TIMER_BIT TIMER1bit #endif +#ifdef CONFIG_BF60x +/* + * Timer Configuration Register Bits + */ +#define TIMER_EMU_RUN 0x8000 +#define TIMER_BPER_EN 0x4000 +#define TIMER_BWID_EN 0x2000 +#define TIMER_BDLY_EN 0x1000 +#define TIMER_OUT_DIS 0x0800 +#define TIMER_TIN_SEL 0x0400 +#define TIMER_CLK_SEL 0x0300 +#define TIMER_CLK_SCLK 0x0000 +#define TIMER_CLK_ALT_CLK0 0x0100 +#define TIMER_CLK_ALT_CLK1 0x0300 +#define TIMER_PULSE_HI 0x0080 +#define TIMER_SLAVE_TRIG 0x0040 +#define TIMER_IRQ_MODE 0x0030 +#define TIMER_IRQ_ACT_EDGE 0x0000 +#define TIMER_IRQ_DLY 0x0010 +#define TIMER_IRQ_WID_DLY 0x0020 +#define TIMER_IRQ_PER 0x0030 +#define TIMER_MODE 0x000f +#define TIMER_MODE_WDOG_P 0x0008 +#define TIMER_MODE_WDOG_W 0x0009 +#define TIMER_MODE_PWM_CONT 0x000c +#define TIMER_MODE_PWM 0x000d +#define TIMER_MODE_WDTH 0x000a +#define TIMER_MODE_WDTH_D 0x000b +#define TIMER_MODE_EXT_CLK 0x000e +#define TIMER_MODE_PININT 0x000f + +/* + * Timer Status Register Bits + */ +#define TIMER_STATUS_TIMIL0 0x0001 +#define TIMER_STATUS_TIMIL1 0x0002 +#define TIMER_STATUS_TIMIL2 0x0004 +#define TIMER_STATUS_TIMIL3 0x0008 +#define TIMER_STATUS_TIMIL4 0x0010 +#define TIMER_STATUS_TIMIL5 0x0020 +#define TIMER_STATUS_TIMIL6 0x0040 +#define TIMER_STATUS_TIMIL7 0x0080 + +#define TIMER_STATUS_TOVF0 0x0001 /* timer 0 overflow error */ +#define TIMER_STATUS_TOVF1 0x0002 +#define TIMER_STATUS_TOVF2 0x0004 +#define TIMER_STATUS_TOVF3 0x0008 +#define TIMER_STATUS_TOVF4 0x0010 +#define TIMER_STATUS_TOVF5 0x0020 +#define TIMER_STATUS_TOVF6 0x0040 +#define TIMER_STATUS_TOVF7 0x0080 + +/* + * Timer Slave Enable Status : write 1 to clear + */ +#define TIMER_STATUS_TRUN0 0x0001 +#define TIMER_STATUS_TRUN1 0x0002 +#define TIMER_STATUS_TRUN2 0x0004 +#define TIMER_STATUS_TRUN3 0x0008 +#define TIMER_STATUS_TRUN4 0x0010 +#define TIMER_STATUS_TRUN5 0x0020 +#define TIMER_STATUS_TRUN6 0x0040 +#define TIMER_STATUS_TRUN7 0x0080 + +#else + /* * Timer Configuration Register Bits */ @@ -170,12 +243,18 @@ #define TIMER_STATUS_TRUN10 0x4000 #define TIMER_STATUS_TRUN11 0x8000 +#endif + /* The actual gptimer API */ void set_gptimer_pwidth(unsigned int timer_id, uint32_t width); uint32_t get_gptimer_pwidth(unsigned int timer_id); void set_gptimer_period(unsigned int timer_id, uint32_t period); uint32_t get_gptimer_period(unsigned int timer_id); +#ifdef CONFIG_BF60x +void set_gptimer_delay(unsigned int timer_id, uint32_t delay); +uint32_t get_gptimer_delay(unsigned int timer_id); +#endif uint32_t get_gptimer_count(unsigned int timer_id); int get_gptimer_intr(unsigned int timer_id); void clear_gptimer_intr(unsigned int timer_id); @@ -217,16 +296,41 @@ struct bfin_gptimer_regs { u32 counter; u32 period; u32 width; +#ifdef CONFIG_BF60x + u32 delay; +#endif }; /* * bfin group timer registers layout */ +#ifndef CONFIG_BF60x struct bfin_gptimer_group_regs { __BFP(enable); __BFP(disable); u32 status; }; +#else +struct bfin_gptimer_group_regs { + __BFP(run); + __BFP(enable); + __BFP(disable); + __BFP(stop_cfg); + __BFP(stop_cfg_set); + __BFP(stop_cfg_clr); + __BFP(data_imsk); + __BFP(stat_imsk); + __BFP(tr_msk); + __BFP(tr_ie); + __BFP(data_ilat); + __BFP(stat_ilat); + __BFP(err_status); + __BFP(bcast_per); + __BFP(bcast_wid); + __BFP(bcast_dly); + +}; +#endif #undef __BFP diff --git a/arch/blackfin/include/asm/irqflags.h b/arch/blackfin/include/asm/irqflags.h index 43eb4749de3d..07aff230a812 100644 --- a/arch/blackfin/include/asm/irqflags.h +++ b/arch/blackfin/include/asm/irqflags.h @@ -67,7 +67,11 @@ static inline notrace unsigned long __hard_local_irq_save(void) static inline notrace int hard_irqs_disabled_flags(unsigned long flags) { +#ifdef CONFIG_BF60x + return (flags & IMASK_IVG11) == 0; +#else return (flags & ~0x3f) == 0; +#endif } static inline notrace int hard_irqs_disabled(void) @@ -224,7 +228,7 @@ static inline notrace void hard_local_irq_restore(unsigned long flags) * Direct interface to linux/irqflags.h. */ #define arch_local_save_flags() hard_local_save_flags() -#define arch_local_irq_save(flags) __hard_local_irq_save() +#define arch_local_irq_save() __hard_local_irq_save() #define arch_local_irq_restore(flags) __hard_local_irq_restore(flags) #define arch_local_irq_enable() __hard_local_irq_enable() #define arch_local_irq_disable() __hard_local_irq_disable() diff --git a/arch/blackfin/include/asm/page.h b/arch/blackfin/include/asm/page.h index 7202404966f6..b93474d5be75 100644 --- a/arch/blackfin/include/asm/page.h +++ b/arch/blackfin/include/asm/page.h @@ -7,14 +7,15 @@ #ifndef _BLACKFIN_PAGE_H #define _BLACKFIN_PAGE_H -#include <asm-generic/page.h> -#define MAP_NR(addr) (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT) +#define ARCH_PFN_OFFSET (CONFIG_PHY_RAM_BASE_ADDRESS >> PAGE_SHIFT) +#define MAP_NR(addr) ((unsigned long)(addr) >> PAGE_SHIFT) #define VM_DATA_DEFAULT_FLAGS \ (VM_READ | VM_WRITE | \ ((current->personality & READ_IMPLIES_EXEC) ? VM_EXEC : 0 ) | \ VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) +#include <asm-generic/page.h> #include <asm-generic/memory_model.h> #include <asm-generic/getorder.h> diff --git a/arch/blackfin/include/asm/pda.h b/arch/blackfin/include/asm/pda.h index 28c2498c9c98..68d6f6618f2a 100644 --- a/arch/blackfin/include/asm/pda.h +++ b/arch/blackfin/include/asm/pda.h @@ -13,7 +13,9 @@ #ifndef __ASSEMBLY__ struct blackfin_pda { /* Per-processor Data Area */ +#ifdef CONFIG_SMP struct blackfin_pda *next; +#endif unsigned long syscfg; #ifdef CONFIG_SMP diff --git a/arch/blackfin/include/asm/pm.h b/arch/blackfin/include/asm/pm.h new file mode 100644 index 000000000000..f72239bf3638 --- /dev/null +++ b/arch/blackfin/include/asm/pm.h @@ -0,0 +1,31 @@ +/* + * Blackfin bf609 power management + * + * Copyright 2011 Analog Devices Inc. + * + * Licensed under the GPL-2 + */ + +#ifndef __PM_H__ +#define __PM_H__ + +#include <linux/suspend.h> + +struct bfin_cpu_pm_fns { + void (*save)(unsigned long *); + void (*restore)(unsigned long *); + int (*valid)(suspend_state_t state); + void (*enter)(suspend_state_t state); + int (*prepare)(void); + void (*finish)(void); +}; + +extern struct bfin_cpu_pm_fns *bfin_cpu_pm; + +# ifdef CONFIG_BFIN_COREB +void bfin_coreb_start(void); +void bfin_coreb_stop(void); +void bfin_coreb_reset(void); +# endif + +#endif diff --git a/arch/blackfin/include/asm/unistd.h b/arch/blackfin/include/asm/unistd.h index 75ec9df5318b..3287222cba34 100644 --- a/arch/blackfin/include/asm/unistd.h +++ b/arch/blackfin/include/asm/unistd.h @@ -11,7 +11,7 @@ */ #define __NR_restart_syscall 0 #define __NR_exit 1 -#define __NR_fork 2 + /* 2 __NR_fork not supported on nommu */ #define __NR_read 3 #define __NR_write 4 #define __NR_open 5 diff --git a/arch/blackfin/kernel/bfin_dma.c b/arch/blackfin/kernel/bfin_dma.c index 40c2ed61258e..c166939ffb2b 100644 --- a/arch/blackfin/kernel/bfin_dma.c +++ b/arch/blackfin/kernel/bfin_dma.c @@ -45,9 +45,15 @@ static int __init blackfin_dma_init(void) atomic_set(&dma_ch[i].chan_status, 0); dma_ch[i].regs = dma_io_base_addr[i]; } +#ifdef CH_MEM_STREAM3_SRC + /* Mark MEMDMA Channel 3 as requested since we're using it internally */ + request_dma(CH_MEM_STREAM3_DEST, "Blackfin dma_memcpy"); + request_dma(CH_MEM_STREAM3_SRC, "Blackfin dma_memcpy"); +#else /* Mark MEMDMA Channel 0 as requested since we're using it internally */ request_dma(CH_MEM_STREAM0_DEST, "Blackfin dma_memcpy"); request_dma(CH_MEM_STREAM0_SRC, "Blackfin dma_memcpy"); +#endif #if defined(CONFIG_DEB_DMA_URGENT) bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE() @@ -84,7 +90,8 @@ static const struct file_operations proc_dma_operations = { static int __init proc_dma_init(void) { - return proc_create("dma", 0, NULL, &proc_dma_operations) != NULL; + proc_create("dma", 0, NULL, &proc_dma_operations); + return 0; } late_initcall(proc_dma_init); #endif @@ -204,6 +211,7 @@ EXPORT_SYMBOL(free_dma); # ifndef MAX_DMA_SUSPEND_CHANNELS # define MAX_DMA_SUSPEND_CHANNELS MAX_DMA_CHANNELS # endif +# ifndef CONFIG_BF60x int blackfin_dma_suspend(void) { int i; @@ -213,7 +221,6 @@ int blackfin_dma_suspend(void) printk(KERN_ERR "DMA Channel %d failed to suspend\n", i); return -EBUSY; } - if (i < MAX_DMA_SUSPEND_CHANNELS) dma_ch[i].saved_peripheral_map = dma_ch[i].regs->peripheral_map; } @@ -230,7 +237,6 @@ void blackfin_dma_resume(void) for (i = 0; i < MAX_DMA_CHANNELS; ++i) { dma_ch[i].regs->cfg = 0; - if (i < MAX_DMA_SUSPEND_CHANNELS) dma_ch[i].regs->peripheral_map = dma_ch[i].saved_peripheral_map; } @@ -238,6 +244,16 @@ void blackfin_dma_resume(void) bfin_write_DMAC_TC_PER(0x0111); #endif } +# else +int blackfin_dma_suspend(void) +{ + return 0; +} + +void blackfin_dma_resume(void) +{ +} +#endif #endif /** @@ -279,10 +295,10 @@ void __init early_dma_memcpy(void *pdst, const void *psrc, size_t size) src_ch = (struct dma_register *)MDMA_S0_NEXT_DESC_PTR; } - if (!bfin_read16(&src_ch->cfg)) + if (!DMA_MMR_READ(&src_ch->cfg)) break; - else if (bfin_read16(&dst_ch->irq_status) & DMA_DONE) { - bfin_write16(&src_ch->cfg, 0); + else if (DMA_MMR_READ(&dst_ch->irq_status) & DMA_DONE) { + DMA_MMR_WRITE(&src_ch->cfg, 0); break; } } @@ -295,22 +311,31 @@ void __init early_dma_memcpy(void *pdst, const void *psrc, size_t size) /* Destination */ bfin_write32(&dst_ch->start_addr, dst); - bfin_write16(&dst_ch->x_count, size >> 2); - bfin_write16(&dst_ch->x_modify, 1 << 2); - bfin_write16(&dst_ch->irq_status, DMA_DONE | DMA_ERR); + DMA_MMR_WRITE(&dst_ch->x_count, size >> 2); + DMA_MMR_WRITE(&dst_ch->x_modify, 1 << 2); + DMA_MMR_WRITE(&dst_ch->irq_status, DMA_DONE | DMA_ERR); /* Source */ bfin_write32(&src_ch->start_addr, src); - bfin_write16(&src_ch->x_count, size >> 2); - bfin_write16(&src_ch->x_modify, 1 << 2); - bfin_write16(&src_ch->irq_status, DMA_DONE | DMA_ERR); + DMA_MMR_WRITE(&src_ch->x_count, size >> 2); + DMA_MMR_WRITE(&src_ch->x_modify, 1 << 2); + DMA_MMR_WRITE(&src_ch->irq_status, DMA_DONE | DMA_ERR); /* Enable */ - bfin_write16(&src_ch->cfg, DMAEN | WDSIZE_32); - bfin_write16(&dst_ch->cfg, WNR | DI_EN | DMAEN | WDSIZE_32); + DMA_MMR_WRITE(&src_ch->cfg, DMAEN | WDSIZE_32); + DMA_MMR_WRITE(&dst_ch->cfg, WNR | DI_EN_X | DMAEN | WDSIZE_32); /* Since we are atomic now, don't use the workaround ssync */ __builtin_bfin_ssync(); + +#ifdef CONFIG_BF60x + /* Work around a possible MDMA anomaly. Running 2 MDMA channels to + * transfer DDR data to L1 SRAM may corrupt data. + * Should be reverted after this issue is root caused. + */ + while (!(DMA_MMR_READ(&dst_ch->irq_status) & DMA_DONE)) + continue; +#endif } void __init early_dma_memcpy_done(void) @@ -336,6 +361,42 @@ void __init early_dma_memcpy_done(void) __builtin_bfin_ssync(); } +#ifdef CH_MEM_STREAM3_SRC +#define bfin_read_MDMA_S_CONFIG bfin_read_MDMA_S3_CONFIG +#define bfin_write_MDMA_S_CONFIG bfin_write_MDMA_S3_CONFIG +#define bfin_write_MDMA_S_START_ADDR bfin_write_MDMA_S3_START_ADDR +#define bfin_write_MDMA_S_IRQ_STATUS bfin_write_MDMA_S3_IRQ_STATUS +#define bfin_write_MDMA_S_X_COUNT bfin_write_MDMA_S3_X_COUNT +#define bfin_write_MDMA_S_X_MODIFY bfin_write_MDMA_S3_X_MODIFY +#define bfin_write_MDMA_S_Y_COUNT bfin_write_MDMA_S3_Y_COUNT +#define bfin_write_MDMA_S_Y_MODIFY bfin_write_MDMA_S3_Y_MODIFY +#define bfin_write_MDMA_D_CONFIG bfin_write_MDMA_D3_CONFIG +#define bfin_write_MDMA_D_START_ADDR bfin_write_MDMA_D3_START_ADDR +#define bfin_read_MDMA_D_IRQ_STATUS bfin_read_MDMA_D3_IRQ_STATUS +#define bfin_write_MDMA_D_IRQ_STATUS bfin_write_MDMA_D3_IRQ_STATUS +#define bfin_write_MDMA_D_X_COUNT bfin_write_MDMA_D3_X_COUNT +#define bfin_write_MDMA_D_X_MODIFY bfin_write_MDMA_D3_X_MODIFY +#define bfin_write_MDMA_D_Y_COUNT bfin_write_MDMA_D3_Y_COUNT +#define bfin_write_MDMA_D_Y_MODIFY bfin_write_MDMA_D3_Y_MODIFY +#else +#define bfin_read_MDMA_S_CONFIG bfin_read_MDMA_S0_CONFIG +#define bfin_write_MDMA_S_CONFIG bfin_write_MDMA_S0_CONFIG +#define bfin_write_MDMA_S_START_ADDR bfin_write_MDMA_S0_START_ADDR +#define bfin_write_MDMA_S_IRQ_STATUS bfin_write_MDMA_S0_IRQ_STATUS +#define bfin_write_MDMA_S_X_COUNT bfin_write_MDMA_S0_X_COUNT +#define bfin_write_MDMA_S_X_MODIFY bfin_write_MDMA_S0_X_MODIFY +#define bfin_write_MDMA_S_Y_COUNT bfin_write_MDMA_S0_Y_COUNT +#define bfin_write_MDMA_S_Y_MODIFY bfin_write_MDMA_S0_Y_MODIFY +#define bfin_write_MDMA_D_CONFIG bfin_write_MDMA_D0_CONFIG +#define bfin_write_MDMA_D_START_ADDR bfin_write_MDMA_D0_START_ADDR +#define bfin_read_MDMA_D_IRQ_STATUS bfin_read_MDMA_D0_IRQ_STATUS +#define bfin_write_MDMA_D_IRQ_STATUS bfin_write_MDMA_D0_IRQ_STATUS +#define bfin_write_MDMA_D_X_COUNT bfin_write_MDMA_D0_X_COUNT +#define bfin_write_MDMA_D_X_MODIFY bfin_write_MDMA_D0_X_MODIFY +#define bfin_write_MDMA_D_Y_COUNT bfin_write_MDMA_D0_Y_COUNT +#define bfin_write_MDMA_D_Y_MODIFY bfin_write_MDMA_D0_Y_MODIFY +#endif + /** * __dma_memcpy - program the MDMA registers * @@ -358,8 +419,8 @@ static void __dma_memcpy(u32 daddr, s16 dmod, u32 saddr, s16 smod, size_t cnt, u */ __builtin_bfin_ssync(); - if (bfin_read_MDMA_S0_CONFIG()) - while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE)) + if (bfin_read_MDMA_S_CONFIG()) + while (!(bfin_read_MDMA_D_IRQ_STATUS() & DMA_DONE)) continue; if (conf & DMA2D) { @@ -374,39 +435,42 @@ static void __dma_memcpy(u32 daddr, s16 dmod, u32 saddr, s16 smod, size_t cnt, u u32 shift = abs(dmod) >> 1; size_t ycnt = cnt >> (16 - shift); cnt = 1 << (16 - shift); - bfin_write_MDMA_D0_Y_COUNT(ycnt); - bfin_write_MDMA_S0_Y_COUNT(ycnt); - bfin_write_MDMA_D0_Y_MODIFY(dmod); - bfin_write_MDMA_S0_Y_MODIFY(smod); + bfin_write_MDMA_D_Y_COUNT(ycnt); + bfin_write_MDMA_S_Y_COUNT(ycnt); + bfin_write_MDMA_D_Y_MODIFY(dmod); + bfin_write_MDMA_S_Y_MODIFY(smod); } - bfin_write_MDMA_D0_START_ADDR(daddr); - bfin_write_MDMA_D0_X_COUNT(cnt); - bfin_write_MDMA_D0_X_MODIFY(dmod); - bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); + bfin_write_MDMA_D_START_ADDR(daddr); + bfin_write_MDMA_D_X_COUNT(cnt); + bfin_write_MDMA_D_X_MODIFY(dmod); + bfin_write_MDMA_D_IRQ_STATUS(DMA_DONE | DMA_ERR); - bfin_write_MDMA_S0_START_ADDR(saddr); - bfin_write_MDMA_S0_X_COUNT(cnt); - bfin_write_MDMA_S0_X_MODIFY(smod); - bfin_write_MDMA_S0_IRQ_STATUS(DMA_DONE | DMA_ERR); + bfin_write_MDMA_S_START_ADDR(saddr); + bfin_write_MDMA_S_X_COUNT(cnt); + bfin_write_MDMA_S_X_MODIFY(smod); + bfin_write_MDMA_S_IRQ_STATUS(DMA_DONE | DMA_ERR); - bfin_write_MDMA_S0_CONFIG(DMAEN | conf); - bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | conf); + bfin_write_MDMA_S_CONFIG(DMAEN | conf); + if (conf & DMA2D) + bfin_write_MDMA_D_CONFIG(WNR | DI_EN_Y | DMAEN | conf); + else + bfin_write_MDMA_D_CONFIG(WNR | DI_EN_X | DMAEN | conf); spin_unlock_irqrestore(&mdma_lock, flags); SSYNC(); - while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE)) - if (bfin_read_MDMA_S0_CONFIG()) + while (!(bfin_read_MDMA_D_IRQ_STATUS() & DMA_DONE)) + if (bfin_read_MDMA_S_CONFIG()) continue; else return; - bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); + bfin_write_MDMA_D_IRQ_STATUS(DMA_DONE | DMA_ERR); - bfin_write_MDMA_S0_CONFIG(0); - bfin_write_MDMA_D0_CONFIG(0); + bfin_write_MDMA_S_CONFIG(0); + bfin_write_MDMA_D_CONFIG(0); } /** @@ -448,8 +512,10 @@ static void *_dma_memcpy(void *pdst, const void *psrc, size_t size) } size >>= shift; +#ifndef DMA_MMR_SIZE_32 if (size > 0x10000) conf |= DMA2D; +#endif __dma_memcpy(dst, mod, src, mod, size, conf); @@ -488,6 +554,9 @@ EXPORT_SYMBOL(dma_memcpy); */ void *dma_memcpy_nocache(void *pdst, const void *psrc, size_t size) { +#ifdef DMA_MMR_SIZE_32 + _dma_memcpy(pdst, psrc, size); +#else size_t bulk, rest; bulk = size & ~0xffff; @@ -495,6 +564,7 @@ void *dma_memcpy_nocache(void *pdst, const void *psrc, size_t size) if (bulk) _dma_memcpy(pdst, psrc, bulk); _dma_memcpy(pdst + bulk, psrc + bulk, rest); +#endif return pdst; } EXPORT_SYMBOL(dma_memcpy_nocache); @@ -514,14 +584,14 @@ void *safe_dma_memcpy(void *dst, const void *src, size_t size) } EXPORT_SYMBOL(safe_dma_memcpy); -static void _dma_out(unsigned long addr, unsigned long buf, unsigned short len, +static void _dma_out(unsigned long addr, unsigned long buf, unsigned DMA_MMR_SIZE_TYPE len, u16 size, u16 dma_size) { blackfin_dcache_flush_range(buf, buf + len * size); __dma_memcpy(addr, 0, buf, size, len, dma_size); } -static void _dma_in(unsigned long addr, unsigned long buf, unsigned short len, +static void _dma_in(unsigned long addr, unsigned long buf, unsigned DMA_MMR_SIZE_TYPE len, u16 size, u16 dma_size) { blackfin_dcache_invalidate_range(buf, buf + len * size); @@ -529,7 +599,7 @@ static void _dma_in(unsigned long addr, unsigned long buf, unsigned short len, } #define MAKE_DMA_IO(io, bwl, isize, dmasize, cnst) \ -void dma_##io##s##bwl(unsigned long addr, cnst void *buf, unsigned short len) \ +void dma_##io##s##bwl(unsigned long addr, cnst void *buf, unsigned DMA_MMR_SIZE_TYPE len) \ { \ _dma_##io(addr, (unsigned long)buf, len, isize, WDSIZE_##dmasize); \ } \ diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c index 02796b88443d..83139aaf3072 100644 --- a/arch/blackfin/kernel/bfin_gpio.c +++ b/arch/blackfin/kernel/bfin_gpio.c @@ -58,7 +58,7 @@ static struct gpio_port_t * const gpio_array[] = { (struct gpio_port_t *) FIO0_FLAG_D, (struct gpio_port_t *) FIO1_FLAG_D, (struct gpio_port_t *) FIO2_FLAG_D, -#elif defined(CONFIG_BF54x) +#elif defined(CONFIG_BF54x) || defined(CONFIG_BF60x) (struct gpio_port_t *)PORTA_FER, (struct gpio_port_t *)PORTB_FER, (struct gpio_port_t *)PORTC_FER, @@ -66,9 +66,11 @@ static struct gpio_port_t * const gpio_array[] = { (struct gpio_port_t *)PORTE_FER, (struct gpio_port_t *)PORTF_FER, (struct gpio_port_t *)PORTG_FER, +# if defined(CONFIG_BF54x) (struct gpio_port_t *)PORTH_FER, (struct gpio_port_t *)PORTI_FER, (struct gpio_port_t *)PORTJ_FER, +# endif #else # error no gpio arrays defined #endif @@ -210,7 +212,7 @@ static void port_setup(unsigned gpio, unsigned short usage) else *port_fer[gpio_bank(gpio)] |= gpio_bit(gpio); SSYNC(); -#elif defined(CONFIG_BF54x) +#elif defined(CONFIG_BF54x) || defined(CONFIG_BF60x) if (usage == GPIO_USAGE) gpio_array[gpio_bank(gpio)]->port_fer &= ~gpio_bit(gpio); else @@ -299,7 +301,7 @@ static void portmux_setup(unsigned short per) pmux |= (function << offset); bfin_write_PORT_MUX(pmux); } -#elif defined(CONFIG_BF54x) +#elif defined(CONFIG_BF54x) || defined(CONFIG_BF60x) inline void portmux_setup(unsigned short per) { u16 ident = P_IDENT(per); @@ -377,7 +379,7 @@ static int portmux_group_check(unsigned short per) } #endif -#ifndef CONFIG_BF54x +#if !(defined(CONFIG_BF54x) || defined(CONFIG_BF60x)) /*********************************************************** * * FUNCTIONS: Blackfin General Purpose Ports Access Functions @@ -680,7 +682,7 @@ void bfin_gpio_pm_hibernate_restore(void) #endif -#else /* CONFIG_BF54x */ +#else /* CONFIG_BF54x || CONFIG_BF60x */ #ifdef CONFIG_PM int bfin_pm_standby_ctrl(unsigned ctrl) @@ -726,7 +728,7 @@ unsigned short get_gpio_dir(unsigned gpio) } EXPORT_SYMBOL(get_gpio_dir); -#endif /* CONFIG_BF54x */ +#endif /* CONFIG_BF54x || CONFIG_BF60x */ /*********************************************************** * @@ -783,7 +785,7 @@ int peripheral_request(unsigned short per, const char *label) * be requested and used by several drivers */ -#ifdef CONFIG_BF54x +#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x) if (!((per & P_MAYSHARE) && get_portmux(per) == P_FUNCT2MUX(per))) { #else if (!(per & P_MAYSHARE)) { @@ -937,7 +939,7 @@ int bfin_gpio_request(unsigned gpio, const char *label) printk(KERN_NOTICE "bfin-gpio: GPIO %d is already reserved as gpio-irq!" " (Documentation/blackfin/bfin-gpio-notes.txt)\n", gpio); } -#ifndef CONFIG_BF54x +#if !(defined(CONFIG_BF54x) || defined(CONFIG_BF60x)) else { /* Reset POLAR setting when acquiring a gpio for the first time */ set_gpio_polar(gpio, 0); } @@ -1110,7 +1112,7 @@ void bfin_gpio_irq_free(unsigned gpio) static inline void __bfin_gpio_direction_input(unsigned gpio) { -#ifdef CONFIG_BF54x +#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x) gpio_array[gpio_bank(gpio)]->dir_clear = gpio_bit(gpio); #else gpio_array[gpio_bank(gpio)]->dir &= ~gpio_bit(gpio); @@ -1138,13 +1140,13 @@ EXPORT_SYMBOL(bfin_gpio_direction_input); void bfin_gpio_irq_prepare(unsigned gpio) { -#ifdef CONFIG_BF54x +#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x) unsigned long flags; #endif port_setup(gpio, GPIO_USAGE); -#ifdef CONFIG_BF54x +#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x) flags = hard_local_irq_save(); __bfin_gpio_direction_input(gpio); hard_local_irq_restore(flags); @@ -1173,7 +1175,7 @@ int bfin_gpio_direction_output(unsigned gpio, int value) gpio_array[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio); gpio_set_value(gpio, value); -#ifdef CONFIG_BF54x +#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x) gpio_array[gpio_bank(gpio)]->dir_set = gpio_bit(gpio); #else gpio_array[gpio_bank(gpio)]->dir |= gpio_bit(gpio); @@ -1188,7 +1190,7 @@ EXPORT_SYMBOL(bfin_gpio_direction_output); int bfin_gpio_get_value(unsigned gpio) { -#ifdef CONFIG_BF54x +#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x) return (1 & (gpio_array[gpio_bank(gpio)]->data >> gpio_sub_n(gpio))); #else unsigned long flags; diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c index 886e00014d75..3e366dc2d6e1 100644 --- a/arch/blackfin/kernel/cplb-nompu/cplbinit.c +++ b/arch/blackfin/kernel/cplb-nompu/cplbinit.c @@ -139,7 +139,7 @@ void __init generate_cplb_tables_all(void) dcplb_bounds[i_d].eaddr = BOOT_ROM_START; dcplb_bounds[i_d++].data = 0; /* BootROM -- largest one should be less than 1 meg. */ - dcplb_bounds[i_d].eaddr = BOOT_ROM_START + (1 * 1024 * 1024); + dcplb_bounds[i_d].eaddr = BOOT_ROM_START + BOOT_ROM_LENGTH; dcplb_bounds[i_d++].data = SDRAM_DGENERIC; if (L2_LENGTH) { /* Addressing hole up to L2 SRAM. */ @@ -178,7 +178,7 @@ void __init generate_cplb_tables_all(void) icplb_bounds[i_i].eaddr = BOOT_ROM_START; icplb_bounds[i_i++].data = 0; /* BootROM -- largest one should be less than 1 meg. */ - icplb_bounds[i_i].eaddr = BOOT_ROM_START + (1 * 1024 * 1024); + icplb_bounds[i_i].eaddr = BOOT_ROM_START + BOOT_ROM_LENGTH; icplb_bounds[i_i++].data = SDRAM_IGENERIC; if (L2_LENGTH) { diff --git a/arch/blackfin/kernel/cplb-nompu/cplbmgr.c b/arch/blackfin/kernel/cplb-nompu/cplbmgr.c index 5b88861d6183..e854f9066cbd 100644 --- a/arch/blackfin/kernel/cplb-nompu/cplbmgr.c +++ b/arch/blackfin/kernel/cplb-nompu/cplbmgr.c @@ -179,6 +179,12 @@ MGR_ATTR static int dcplb_miss(int cpu) addr = addr1; } +#ifdef CONFIG_BF60x + if ((addr >= ASYNC_BANK0_BASE) + && (addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE)) + d_data |= PAGE_SIZE_64MB; +#endif + /* Pick entry to evict */ idx = evict_one_dcplb(cpu); diff --git a/arch/blackfin/kernel/debug-mmrs.c b/arch/blackfin/kernel/debug-mmrs.c index 92f664826281..01232a13470d 100644 --- a/arch/blackfin/kernel/debug-mmrs.c +++ b/arch/blackfin/kernel/debug-mmrs.c @@ -105,6 +105,7 @@ DEFINE_SYSREG(seqstat, , ); DEFINE_SYSREG(syscfg, , CSYNC()); #define D_SYSREG(sr) debugfs_create_file(#sr, S_IRUSR|S_IWUSR, parent, NULL, &fops_sysreg_##sr) +#ifndef CONFIG_BF60x /* * CAN */ @@ -223,8 +224,10 @@ bfin_debug_mmrs_dma(struct dentry *parent, unsigned long base, int num, char mdm __DMA(CURR_DESC_PTR, curr_desc_ptr); __DMA(CURR_ADDR, curr_addr); __DMA(IRQ_STATUS, irq_status); +#ifndef CONFIG_BF60x if (strcmp(pfx, "IMDMA") != 0) __DMA(PERIPHERAL_MAP, peripheral_map); +#endif __DMA(CURR_X_COUNT, curr_x_count); __DMA(CURR_Y_COUNT, curr_y_count); } @@ -568,7 +571,7 @@ bfin_debug_mmrs_uart(struct dentry *parent, unsigned long base, int num) #endif } #define UART(num) bfin_debug_mmrs_uart(parent, UART##num##_DLL, num) - +#endif /* CONFIG_BF60x */ /* * The actual debugfs generation */ @@ -740,7 +743,7 @@ static int __init bfin_debug_mmrs_init(void) D32(WPDACNT0); D32(WPDACNT1); D32(WPSTAT); - +#ifndef CONFIG_BF60x /* System MMRs */ #ifdef ATAPI_CONTROL parent = debugfs_create_dir("atapi", top); @@ -1873,7 +1876,7 @@ static int __init bfin_debug_mmrs_init(void) } #endif /* BF54x */ - +#endif /* CONFIG_BF60x */ debug_mmrs_dentry = top; return 0; diff --git a/arch/blackfin/kernel/entry.S b/arch/blackfin/kernel/entry.S index 686478f5f66b..f33792cc1a0d 100644 --- a/arch/blackfin/kernel/entry.S +++ b/arch/blackfin/kernel/entry.S @@ -64,16 +64,6 @@ ENTRY(_ret_from_fork) jump (p0); ENDPROC(_ret_from_fork) -ENTRY(_sys_fork) - r0 = -EINVAL; -#if (ANOMALY_05000371) - nop; - nop; - nop; -#endif - rts; -ENDPROC(_sys_fork) - ENTRY(_sys_vfork) r0 = sp; r0 += 24; diff --git a/arch/blackfin/kernel/gptimers.c b/arch/blackfin/kernel/gptimers.c index 06459f4bf43a..d776773d3869 100644 --- a/arch/blackfin/kernel/gptimers.c +++ b/arch/blackfin/kernel/gptimers.c @@ -23,7 +23,11 @@ printk(KERN_DEBUG "%s:%s:%i: Assertion failed: " #expr "\n", __FILE__, __func__, __LINE__); #endif -#define BFIN_TIMER_NUM_GROUP (BFIN_TIMER_OCTET(MAX_BLACKFIN_GPTIMERS - 1) + 1) +#ifndef CONFIG_BF60x +# define BFIN_TIMER_NUM_GROUP (BFIN_TIMER_OCTET(MAX_BLACKFIN_GPTIMERS - 1) + 1) +#else +# define BFIN_TIMER_NUM_GROUP 1 +#endif static struct bfin_gptimer_regs * const timer_regs[MAX_BLACKFIN_GPTIMERS] = { @@ -158,6 +162,74 @@ uint32_t get_gptimer_count(unsigned int timer_id) } EXPORT_SYMBOL(get_gptimer_count); +#ifdef CONFIG_BF60x +void set_gptimer_delay(unsigned int timer_id, uint32_t delay) +{ + tassert(timer_id < MAX_BLACKFIN_GPTIMERS); + bfin_write(&timer_regs[timer_id]->delay, delay); + SSYNC(); +} +EXPORT_SYMBOL(set_gptimer_delay); + +uint32_t get_gptimer_delay(unsigned int timer_id) +{ + tassert(timer_id < MAX_BLACKFIN_GPTIMERS); + return bfin_read(&timer_regs[timer_id]->delay); +} +EXPORT_SYMBOL(get_gptimer_delay); +#endif + +#ifdef CONFIG_BF60x +int get_gptimer_intr(unsigned int timer_id) +{ + tassert(timer_id < MAX_BLACKFIN_GPTIMERS); + return !!(bfin_read(&group_regs[BFIN_TIMER_OCTET(timer_id)]->data_ilat) & timil_mask[timer_id]); +} +EXPORT_SYMBOL(get_gptimer_intr); + +void clear_gptimer_intr(unsigned int timer_id) +{ + tassert(timer_id < MAX_BLACKFIN_GPTIMERS); + bfin_write(&group_regs[BFIN_TIMER_OCTET(timer_id)]->data_ilat, timil_mask[timer_id]); +} +EXPORT_SYMBOL(clear_gptimer_intr); + +int get_gptimer_over(unsigned int timer_id) +{ + tassert(timer_id < MAX_BLACKFIN_GPTIMERS); + return !!(bfin_read(&group_regs[BFIN_TIMER_OCTET(timer_id)]->stat_ilat) & tovf_mask[timer_id]); +} +EXPORT_SYMBOL(get_gptimer_over); + +void clear_gptimer_over(unsigned int timer_id) +{ + tassert(timer_id < MAX_BLACKFIN_GPTIMERS); + bfin_write(&group_regs[BFIN_TIMER_OCTET(timer_id)]->stat_ilat, tovf_mask[timer_id]); +} +EXPORT_SYMBOL(clear_gptimer_over); + +int get_gptimer_run(unsigned int timer_id) +{ + tassert(timer_id < MAX_BLACKFIN_GPTIMERS); + return !!(bfin_read(&group_regs[BFIN_TIMER_OCTET(timer_id)]->run) & trun_mask[timer_id]); +} +EXPORT_SYMBOL(get_gptimer_run); + +uint32_t get_gptimer_status(unsigned int group) +{ + tassert(group < BFIN_TIMER_NUM_GROUP); + return bfin_read(&group_regs[group]->data_ilat); +} +EXPORT_SYMBOL(get_gptimer_status); + +void set_gptimer_status(unsigned int group, uint32_t value) +{ + tassert(group < BFIN_TIMER_NUM_GROUP); + bfin_write(&group_regs[group]->data_ilat, value); + SSYNC(); +} +EXPORT_SYMBOL(set_gptimer_status); +#else uint32_t get_gptimer_status(unsigned int group) { tassert(group < BFIN_TIMER_NUM_GROUP); @@ -212,6 +284,7 @@ int get_gptimer_run(unsigned int timer_id) return !!(read_gptimer_status(timer_id) & trun_mask[timer_id]); } EXPORT_SYMBOL(get_gptimer_run); +#endif void set_gptimer_config(unsigned int timer_id, uint16_t config) { @@ -231,6 +304,12 @@ EXPORT_SYMBOL(get_gptimer_config); void enable_gptimers(uint16_t mask) { int i; +#ifdef CONFIG_BF60x + uint16_t imask; + imask = bfin_read16(TIMER_DATA_IMSK); + imask &= ~mask; + bfin_write16(TIMER_DATA_IMSK, imask); +#endif tassert((mask & ~BLACKFIN_GPTIMER_IDMASK) == 0); for (i = 0; i < BFIN_TIMER_NUM_GROUP; ++i) { bfin_write(&group_regs[i]->enable, mask & 0xFF); @@ -253,12 +332,16 @@ static void _disable_gptimers(uint16_t mask) void disable_gptimers(uint16_t mask) { +#ifndef CONFIG_BF60x int i; _disable_gptimers(mask); for (i = 0; i < MAX_BLACKFIN_GPTIMERS; ++i) if (mask & (1 << i)) bfin_write(&group_regs[BFIN_TIMER_OCTET(i)]->status, trun_mask[i]); SSYNC(); +#else + _disable_gptimers(mask); +#endif } EXPORT_SYMBOL(disable_gptimers); diff --git a/arch/blackfin/kernel/process.c b/arch/blackfin/kernel/process.c index c0f4fe287eb6..2e3994b20169 100644 --- a/arch/blackfin/kernel/process.c +++ b/arch/blackfin/kernel/process.c @@ -95,7 +95,9 @@ void cpu_idle(void) idle(); rcu_idle_exit(); tick_nohz_idle_exit(); - schedule_preempt_disabled(); + preempt_enable_no_resched(); + schedule(); + preempt_disable(); } } @@ -329,12 +331,16 @@ int in_mem_const(unsigned long addr, unsigned long size, { return in_mem_const_off(addr, size, 0, const_addr, const_size); } +#ifdef CONFIG_BF60x +#define ASYNC_ENABLED(bnum, bctlnum) 1 +#else #define ASYNC_ENABLED(bnum, bctlnum) \ ({ \ (bfin_read_EBIU_AMGCTL() & 0xe) < ((bnum + 1) << 1) ? 0 : \ bfin_read_EBIU_AMBCTL##bctlnum() & B##bnum##RDYEN ? 0 : \ 1; \ }) +#endif /* * We can't read EBIU banks that aren't enabled or we end up hanging * on the access to the async space. Make sure we validate accesses diff --git a/arch/blackfin/kernel/reboot.c b/arch/blackfin/kernel/reboot.c index b0434f89e8de..5272e6eefd92 100644 --- a/arch/blackfin/kernel/reboot.c +++ b/arch/blackfin/kernel/reboot.c @@ -22,6 +22,7 @@ __attribute__ ((__l1_text__, __noreturn__)) static void bfin_reset(void) { +#ifndef CONFIG_BF60x if (!ANOMALY_05000353 && !ANOMALY_05000386) bfrom_SoftReset((void *)(L1_SCRATCH_START + L1_SCRATCH_LENGTH - 20)); @@ -57,7 +58,6 @@ static void bfin_reset(void) if (__SILICON_REVISION__ < 1 && bfin_revid() < 1) bfin_read_SWRST(); #endif - /* Wait for the SWRST write to complete. Cannot rely on SSYNC * though as the System state is all reset now. */ @@ -72,6 +72,10 @@ static void bfin_reset(void) while (1) /* Issue core reset */ asm("raise 1"); +#else + while (1) + bfin_write_RCU0_CTL(0x1); +#endif } __attribute__((weak)) diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c index 2ad747e909fb..ada8f0fc71e4 100644 --- a/arch/blackfin/kernel/setup.c +++ b/arch/blackfin/kernel/setup.c @@ -25,12 +25,16 @@ #include <asm/cacheflush.h> #include <asm/blackfin.h> #include <asm/cplbinit.h> +#include <asm/clocks.h> #include <asm/div64.h> #include <asm/cpu.h> #include <asm/fixed_code.h> #include <asm/early_printk.h> #include <asm/irq_handler.h> #include <asm/pda.h> +#ifdef CONFIG_BF60x +#include <mach/pm.h> +#endif u16 _bfin_swrst; EXPORT_SYMBOL(_bfin_swrst); @@ -550,7 +554,6 @@ static __init void memory_setup(void) { #ifdef CONFIG_MTD_UCLINUX unsigned long mtd_phys = 0; - unsigned long n; #endif unsigned long max_mem; @@ -594,9 +597,9 @@ static __init void memory_setup(void) mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 8))); # if defined(CONFIG_EXT2_FS) || defined(CONFIG_EXT3_FS) - n = ext2_image_size((void *)(mtd_phys + 0x400)); - if (n) - mtd_size = PAGE_ALIGN(n * 1024); + if (*((unsigned short *)(mtd_phys + 0x438)) == EXT2_SUPER_MAGIC) + mtd_size = + PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x404)) << 10); # endif # if defined(CONFIG_CRAMFS) @@ -612,7 +615,8 @@ static __init void memory_setup(void) /* ROM_FS is XIP, so if we found it, we need to limit memory */ if (memory_end > max_mem) { - pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n", max_mem >> 20); + pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n", + (max_mem - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20); memory_end = max_mem; } } @@ -642,7 +646,8 @@ static __init void memory_setup(void) * doesn't exist, or we don't need to - then dont. */ if (memory_end > max_mem) { - pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n", max_mem >> 20); + pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n", + (max_mem - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20); memory_end = max_mem; } @@ -661,8 +666,8 @@ static __init void memory_setup(void) init_mm.end_data = (unsigned long)_edata; init_mm.brk = (unsigned long)0; - printk(KERN_INFO "Board Memory: %ldMB\n", physical_mem_end >> 20); - printk(KERN_INFO "Kernel Managed Memory: %ldMB\n", _ramend >> 20); + printk(KERN_INFO "Board Memory: %ldMB\n", (physical_mem_end - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20); + printk(KERN_INFO "Kernel Managed Memory: %ldMB\n", (_ramend - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20); printk(KERN_INFO "Memory map:\n" " fixedcode = 0x%p-0x%p\n" @@ -705,7 +710,7 @@ void __init find_min_max_pfn(void) int i; max_pfn = 0; - min_low_pfn = memory_end; + min_low_pfn = PFN_DOWN(memory_end); for (i = 0; i < bfin_memmap.nr_map; i++) { unsigned long start, end; @@ -748,8 +753,7 @@ static __init void setup_bootmem_allocator(void) /* pfn of the first usable page frame after kernel image*/ if (min_low_pfn < memory_start >> PAGE_SHIFT) min_low_pfn = memory_start >> PAGE_SHIFT; - - start_pfn = PAGE_OFFSET >> PAGE_SHIFT; + start_pfn = CONFIG_PHY_RAM_BASE_ADDRESS >> PAGE_SHIFT; end_pfn = memory_end >> PAGE_SHIFT; /* @@ -794,8 +798,8 @@ static __init void setup_bootmem_allocator(void) } /* reserve memory before memory_start, including bootmap */ - reserve_bootmem(PAGE_OFFSET, - memory_start + bootmap_size + PAGE_SIZE - 1 - PAGE_OFFSET, + reserve_bootmem(CONFIG_PHY_RAM_BASE_ADDRESS, + memory_start + bootmap_size + PAGE_SIZE - 1 - CONFIG_PHY_RAM_BASE_ADDRESS, BOOTMEM_DEFAULT); } @@ -844,13 +848,40 @@ static inline int __init get_mem_size(void) break; } switch (ddrctl & 0x30000) { - case DEVWD_4: ret *= 2; - case DEVWD_8: ret *= 2; - case DEVWD_16: break; + case DEVWD_4: + ret *= 2; + case DEVWD_8: + ret *= 2; + case DEVWD_16: + break; } if ((ddrctl & 0xc000) == 0x4000) ret *= 2; return ret; +#elif defined(CONFIG_BF60x) + u32 ddrctl = bfin_read_DMC0_CFG(); + int ret; + switch (ddrctl & 0xf00) { + case DEVSZ_64: + ret = 64 / 8; + break; + case DEVSZ_128: + ret = 128 / 8; + break; + case DEVSZ_256: + ret = 256 / 8; + break; + case DEVSZ_512: + ret = 512 / 8; + break; + case DEVSZ_1G: + ret = 1024 / 8; + break; + case DEVSZ_2G: + ret = 2048 / 8; + break; + } + return ret; #endif BUG(); } @@ -860,6 +891,22 @@ void __init native_machine_early_platform_add_devices(void) { } +#ifdef CONFIG_BF60x +static inline u_long bfin_get_clk(char *name) +{ + struct clk *clk; + u_long clk_rate; + + clk = clk_get(NULL, name); + if (IS_ERR(clk)) + return 0; + + clk_rate = clk_get_rate(clk); + clk_put(clk); + return clk_rate; +} +#endif + void __init setup_arch(char **cmdline_p) { u32 mmr; @@ -870,6 +917,7 @@ void __init setup_arch(char **cmdline_p) enable_shadow_console(); /* Check to make sure we are running on the right processor */ + mmr = bfin_cpuid(); if (unlikely(CPUID != bfin_cpuid())) printk(KERN_ERR "ERROR: Not running on ADSP-%s: unknown CPUID 0x%04x Rev 0.%d\n", CPU, bfin_cpuid(), bfin_revid()); @@ -890,6 +938,10 @@ void __init setup_arch(char **cmdline_p) memset(&bfin_memmap, 0, sizeof(bfin_memmap)); +#ifdef CONFIG_BF60x + /* Should init clock device before parse command early */ + clk_init(); +#endif /* If the user does not specify things on the command line, use * what the bootloader set things up as */ @@ -904,6 +956,7 @@ void __init setup_arch(char **cmdline_p) memory_setup(); +#ifndef CONFIG_BF60x /* Initialize Async memory banks */ bfin_write_EBIU_AMBCTL0(AMBCTL0VAL); bfin_write_EBIU_AMBCTL1(AMBCTL1VAL); @@ -913,6 +966,7 @@ void __init setup_arch(char **cmdline_p) bfin_write_EBIU_MODE(CONFIG_EBIU_MODEVAL); bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTLVAL); #endif +#endif #ifdef CONFIG_BFIN_HYSTERESIS_CONTROL bfin_write_PORTF_HYSTERESIS(HYST_PORTF_0_15); bfin_write_PORTG_HYSTERESIS(HYST_PORTG_0_15); @@ -938,7 +992,7 @@ void __init setup_arch(char **cmdline_p) printk(KERN_INFO "Hardware Trace %s and %sabled\n", (mmr & 0x1) ? "active" : "off", (mmr & 0x2) ? "en" : "dis"); - +#ifndef CONFIG_BF60x mmr = bfin_read_SYSCR(); printk(KERN_INFO "Boot Mode: %i\n", mmr & 0xF); @@ -980,7 +1034,7 @@ void __init setup_arch(char **cmdline_p) printk(KERN_INFO "Recovering from Watchdog event\n"); else if (_bfin_swrst & RESET_SOFTWARE) printk(KERN_NOTICE "Reset caused by Software reset\n"); - +#endif printk(KERN_INFO "Blackfin support (C) 2004-2010 Analog Devices, Inc.\n"); if (bfin_compiled_revid() == 0xffff) printk(KERN_INFO "Compiled for ADSP-%s Rev any, running on 0.%d\n", CPU, bfin_revid()); @@ -1008,8 +1062,13 @@ void __init setup_arch(char **cmdline_p) printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n"); +#ifdef CONFIG_BF60x + printk(KERN_INFO "Processor Speed: %lu MHz core clock, %lu MHz SCLk, %lu MHz SCLK0, %lu MHz SCLK1 and %lu MHz DCLK\n", + cclk / 1000000, bfin_get_clk("SYSCLK") / 1000000, get_sclk0() / 1000000, get_sclk1() / 1000000, get_dclk() / 1000000); +#else printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu MHz System Clock\n", cclk / 1000000, sclk / 1000000); +#endif setup_bootmem_allocator(); @@ -1060,10 +1119,12 @@ subsys_initcall(topology_init); /* Get the input clock frequency */ static u_long cached_clkin_hz = CONFIG_CLKIN_HZ; +#ifndef CONFIG_BF60x static u_long get_clkin_hz(void) { return cached_clkin_hz; } +#endif static int __init early_init_clkin_hz(char *buf) { cached_clkin_hz = simple_strtoul(buf, NULL, 0); @@ -1075,6 +1136,7 @@ static int __init early_init_clkin_hz(char *buf) } early_param("clkin_hz=", early_init_clkin_hz); +#ifndef CONFIG_BF60x /* Get the voltage input multiplier */ static u_long get_vco(void) { @@ -1097,10 +1159,14 @@ static u_long get_vco(void) cached_vco *= msel; return cached_vco; } +#endif /* Get the Core clock */ u_long get_cclk(void) { +#ifdef CONFIG_BF60x + return bfin_get_clk("CCLK"); +#else static u_long cached_cclk_pll_div, cached_cclk; u_long csel, ssel; @@ -1120,12 +1186,39 @@ u_long get_cclk(void) else cached_cclk = get_vco() >> csel; return cached_cclk; +#endif } EXPORT_SYMBOL(get_cclk); -/* Get the System clock */ +#ifdef CONFIG_BF60x +/* Get the bf60x clock of SCLK0 domain */ +u_long get_sclk0(void) +{ + return bfin_get_clk("SCLK0"); +} +EXPORT_SYMBOL(get_sclk0); + +/* Get the bf60x clock of SCLK1 domain */ +u_long get_sclk1(void) +{ + return bfin_get_clk("SCLK1"); +} +EXPORT_SYMBOL(get_sclk1); + +/* Get the bf60x DRAM clock */ +u_long get_dclk(void) +{ + return bfin_get_clk("DCLK"); +} +EXPORT_SYMBOL(get_dclk); +#endif + +/* Get the default system clock */ u_long get_sclk(void) { +#ifdef CONFIG_BF60x + return get_sclk0(); +#else static u_long cached_sclk; u_long ssel; @@ -1146,6 +1239,7 @@ u_long get_sclk(void) cached_sclk = get_vco() / ssel; return cached_sclk; +#endif } EXPORT_SYMBOL(get_sclk); diff --git a/arch/blackfin/kernel/shadow_console.c b/arch/blackfin/kernel/shadow_console.c index 557e9fef406a..aeb8343eeb03 100644 --- a/arch/blackfin/kernel/shadow_console.c +++ b/arch/blackfin/kernel/shadow_console.c @@ -15,9 +15,9 @@ #include <asm/irq_handler.h> #include <asm/early_printk.h> -#define SHADOW_CONSOLE_START (0x500) -#define SHADOW_CONSOLE_END (0x1000) -#define SHADOW_CONSOLE_MAGIC_LOC (0x4F0) +#define SHADOW_CONSOLE_START (CONFIG_PHY_RAM_BASE_ADDRESS + 0x500) +#define SHADOW_CONSOLE_END (CONFIG_PHY_RAM_BASE_ADDRESS + 0x1000) +#define SHADOW_CONSOLE_MAGIC_LOC (CONFIG_PHY_RAM_BASE_ADDRESS + 0x4F0) #define SHADOW_CONSOLE_MAGIC (0xDEADBEEF) static __initdata char *shadow_console_buffer = (char *)SHADOW_CONSOLE_START; diff --git a/arch/blackfin/kernel/time-ts.c b/arch/blackfin/kernel/time-ts.c index d98f2d69b0c4..f608f02f29a3 100644 --- a/arch/blackfin/kernel/time-ts.c +++ b/arch/blackfin/kernel/time-ts.c @@ -66,8 +66,14 @@ void __init setup_gptimer0(void) { disable_gptimers(TIMER0bit); +#ifdef CONFIG_BF60x + bfin_write16(TIMER_DATA_IMSK, 0); + set_gptimer_config(TIMER0_id, TIMER_OUT_DIS + | TIMER_MODE_PWM_CONT | TIMER_PULSE_HI | TIMER_IRQ_PER); +#else set_gptimer_config(TIMER0_id, \ TIMER_OUT_DIS | TIMER_PERIOD_CNT | TIMER_MODE_PWM); +#endif set_gptimer_period(TIMER0_id, -1); set_gptimer_pwidth(TIMER0_id, -2); SSYNC(); @@ -135,9 +141,15 @@ static void bfin_gptmr0_set_mode(enum clock_event_mode mode, { switch (mode) { case CLOCK_EVT_MODE_PERIODIC: { +#ifndef CONFIG_BF60x set_gptimer_config(TIMER0_id, \ TIMER_OUT_DIS | TIMER_IRQ_ENA | \ TIMER_PERIOD_CNT | TIMER_MODE_PWM); +#else + set_gptimer_config(TIMER0_id, TIMER_OUT_DIS + | TIMER_MODE_PWM_CONT | TIMER_PULSE_HI | TIMER_IRQ_PER); +#endif + set_gptimer_period(TIMER0_id, get_sclk() / HZ); set_gptimer_pwidth(TIMER0_id, get_sclk() / HZ - 1); enable_gptimers(TIMER0bit); @@ -145,8 +157,14 @@ static void bfin_gptmr0_set_mode(enum clock_event_mode mode, } case CLOCK_EVT_MODE_ONESHOT: disable_gptimers(TIMER0bit); +#ifndef CONFIG_BF60x set_gptimer_config(TIMER0_id, \ TIMER_OUT_DIS | TIMER_IRQ_ENA | TIMER_MODE_PWM); +#else + set_gptimer_config(TIMER0_id, TIMER_OUT_DIS | TIMER_MODE_PWM + | TIMER_PULSE_HI | TIMER_IRQ_WID_DLY); +#endif + set_gptimer_period(TIMER0_id, 0); break; case CLOCK_EVT_MODE_UNUSED: @@ -160,7 +178,7 @@ static void bfin_gptmr0_set_mode(enum clock_event_mode mode, static void bfin_gptmr0_ack(void) { - set_gptimer_status(TIMER_GROUP1, TIMER_STATUS_TIMIL0); + clear_gptimer_intr(TIMER0_id); } static void __init bfin_gptmr0_init(void) @@ -197,7 +215,7 @@ static struct clock_event_device clockevent_gptmr0 = { .rating = 300, .irq = IRQ_TIMER0, .shift = 32, - .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, .set_next_event = bfin_gptmr0_set_next_event, .set_mode = bfin_gptmr0_set_mode, }; @@ -312,6 +330,11 @@ void bfin_coretmr_clockevent_init(void) #endif +#ifdef CONFIG_SMP + evt->broadcast = smp_timer_broadcast; +#endif + + evt->name = "bfin_core_timer"; evt->rating = 350; evt->irq = -1; diff --git a/arch/blackfin/lib/divsi3.S b/arch/blackfin/lib/divsi3.S index f89c5a49c47b..ef2cd99efb89 100644 --- a/arch/blackfin/lib/divsi3.S +++ b/arch/blackfin/lib/divsi3.S @@ -1,7 +1,7 @@ /* * Copyright 2004-2009 Analog Devices Inc. * - * Licensed under the ADI BSD license or the GPL-2 (or later) + * Licensed under the Clear BSD license or the GPL-2 (or later) * * 16 / 32 bit signed division. * Special cases : diff --git a/arch/blackfin/lib/memchr.S b/arch/blackfin/lib/memchr.S index 542e40f8775f..bcfc8a14c3f2 100644 --- a/arch/blackfin/lib/memchr.S +++ b/arch/blackfin/lib/memchr.S @@ -1,7 +1,7 @@ /* * Copyright 2005-2009 Analog Devices Inc. * - * Licensed under the ADI BSD license or the GPL-2 (or later) + * Licensed under the Clear BSD license or the GPL-2 (or later) */ #include <linux/linkage.h> diff --git a/arch/blackfin/lib/memcmp.S b/arch/blackfin/lib/memcmp.S index ce5b9f1a8267..2e1c9477f2f7 100644 --- a/arch/blackfin/lib/memcmp.S +++ b/arch/blackfin/lib/memcmp.S @@ -1,7 +1,7 @@ /* * Copyright 2004-2009 Analog Devices Inc. * - * Licensed under the ADI BSD license or the GPL-2 (or later) + * Licensed under the Clear BSD license or the GPL-2 (or later) */ #include <linux/linkage.h> diff --git a/arch/blackfin/lib/memcpy.S b/arch/blackfin/lib/memcpy.S index c31bf22aab19..53cb3698ab33 100644 --- a/arch/blackfin/lib/memcpy.S +++ b/arch/blackfin/lib/memcpy.S @@ -7,7 +7,7 @@ * * Copyright 2004-2009 Analog Devices Inc. * - * Licensed under the ADI BSD license or the GPL-2 (or later) + * Licensed under the Clear BSD license or the GPL-2 (or later) */ #include <linux/linkage.h> diff --git a/arch/blackfin/lib/memmove.S b/arch/blackfin/lib/memmove.S index 4eca566237a4..e0b78208f1d6 100644 --- a/arch/blackfin/lib/memmove.S +++ b/arch/blackfin/lib/memmove.S @@ -1,7 +1,7 @@ /* * Copyright 2005-2009 Analog Devices Inc. * - * Licensed under the ADI BSD license or the GPL-2 (or later) + * Licensed under the Clear BSD license or the GPL-2 (or later) */ #include <linux/linkage.h> diff --git a/arch/blackfin/lib/memset.S b/arch/blackfin/lib/memset.S index eab1bef3f5bf..cdcf9148ea20 100644 --- a/arch/blackfin/lib/memset.S +++ b/arch/blackfin/lib/memset.S @@ -1,7 +1,7 @@ /* * Copyright 2004-2009 Analog Devices Inc. * - * Licensed under the ADI BSD license or the GPL-2 (or later) + * Licensed under the Clear BSD license or the GPL-2 (or later) */ #include <linux/linkage.h> diff --git a/arch/blackfin/lib/modsi3.S b/arch/blackfin/lib/modsi3.S index 8b0c7d4052af..f7026ce1fa0e 100644 --- a/arch/blackfin/lib/modsi3.S +++ b/arch/blackfin/lib/modsi3.S @@ -6,7 +6,7 @@ * * Copyright 2004-2009 Analog Devices Inc. * - * Licensed under the ADI BSD license or the GPL-2 (or later) + * Licensed under the Clear BSD license or the GPL-2 (or later) */ .global ___modsi3; diff --git a/arch/blackfin/lib/muldi3.S b/arch/blackfin/lib/muldi3.S index 953a38a1d1d1..abf9b2a515b2 100644 --- a/arch/blackfin/lib/muldi3.S +++ b/arch/blackfin/lib/muldi3.S @@ -1,7 +1,7 @@ /* * Copyright 2008 Analog Devices Inc. * - * Licensed under the ADI BSD license or the GPL-2 (or later) + * Licensed under the Clear BSD license or the GPL-2 (or later) */ .align 2 diff --git a/arch/blackfin/lib/smulsi3_highpart.S b/arch/blackfin/lib/smulsi3_highpart.S index 99ee8c5de38b..e50d6c4ac2a5 100644 --- a/arch/blackfin/lib/smulsi3_highpart.S +++ b/arch/blackfin/lib/smulsi3_highpart.S @@ -1,7 +1,7 @@ /* * Copyright 2007 Analog Devices Inc. * - * Licensed under the ADI BSD license or the GPL-2 (or later) + * Licensed under the Clear BSD license or the GPL-2 (or later) */ .align 2 diff --git a/arch/blackfin/lib/strcmp.S b/arch/blackfin/lib/strcmp.S index d7c1d158973b..9c8b9863713e 100644 --- a/arch/blackfin/lib/strcmp.S +++ b/arch/blackfin/lib/strcmp.S @@ -1,7 +1,7 @@ /* * Copyright 2005-2010 Analog Devices Inc. * - * Licensed under the ADI BSD license or the GPL-2 (or later) + * Licensed under the Clear BSD license or the GPL-2 (or later) */ #include <linux/linkage.h> diff --git a/arch/blackfin/lib/strcpy.S b/arch/blackfin/lib/strcpy.S index a6a0c6363806..9495aa77cc40 100644 --- a/arch/blackfin/lib/strcpy.S +++ b/arch/blackfin/lib/strcpy.S @@ -1,7 +1,7 @@ /* * Copyright 2005-2010 Analog Devices Inc. * - * Licensed under the ADI BSD license or the GPL-2 (or later) + * Licensed under the Clear BSD license or the GPL-2 (or later) */ #include <linux/linkage.h> diff --git a/arch/blackfin/lib/strncmp.S b/arch/blackfin/lib/strncmp.S index 6da37c34a847..3bfaedce893e 100644 --- a/arch/blackfin/lib/strncmp.S +++ b/arch/blackfin/lib/strncmp.S @@ -1,7 +1,7 @@ /* * Copyright 2005-2010 Analog Devices Inc. * - * Licensed under the ADI BSD license or the GPL-2 (or later) + * Licensed under the Clear BSD license or the GPL-2 (or later) */ #include <linux/linkage.h> diff --git a/arch/blackfin/lib/strncpy.S b/arch/blackfin/lib/strncpy.S index 2c07dddac995..92fd1823bbee 100644 --- a/arch/blackfin/lib/strncpy.S +++ b/arch/blackfin/lib/strncpy.S @@ -1,7 +1,7 @@ /* * Copyright 2005-2010 Analog Devices Inc. * - * Licensed under the ADI BSD license or the GPL-2 (or later) + * Licensed under the Clear BSD license or the GPL-2 (or later) */ #include <linux/linkage.h> diff --git a/arch/blackfin/lib/udivsi3.S b/arch/blackfin/lib/udivsi3.S index 97e904315ec6..748a6a2e8c17 100644 --- a/arch/blackfin/lib/udivsi3.S +++ b/arch/blackfin/lib/udivsi3.S @@ -1,7 +1,7 @@ /* * Copyright 2004-2009 Analog Devices Inc. * - * Licensed under the ADI BSD license or the GPL-2 (or later) + * Licensed under the Clear BSD license or the GPL-2 (or later) */ #include <linux/linkage.h> diff --git a/arch/blackfin/lib/umodsi3.S b/arch/blackfin/lib/umodsi3.S index 168eba7c64c8..3794c00d859d 100644 --- a/arch/blackfin/lib/umodsi3.S +++ b/arch/blackfin/lib/umodsi3.S @@ -3,7 +3,7 @@ * * Copyright 2004-2009 Analog Devices Inc. * - * Licensed under the ADI BSD license or the GPL-2 (or later) + * Licensed under the Clear BSD license or the GPL-2 (or later) */ #ifdef CONFIG_ARITHMETIC_OPS_L1 diff --git a/arch/blackfin/lib/umulsi3_highpart.S b/arch/blackfin/lib/umulsi3_highpart.S index 051824a6ed00..0dcace96e4e7 100644 --- a/arch/blackfin/lib/umulsi3_highpart.S +++ b/arch/blackfin/lib/umulsi3_highpart.S @@ -1,7 +1,7 @@ /* * Copyright 2007 Analog Devices Inc. * - * Licensed under the ADI BSD license or the GPL-2 (or later) + * Licensed under the Clear BSD license or the GPL-2 (or later) */ .align 2 diff --git a/arch/blackfin/mach-bf518/boards/ezbrd.c b/arch/blackfin/mach-bf518/boards/ezbrd.c index a17395727efa..f8047ca3b339 100644 --- a/arch/blackfin/mach-bf518/boards/ezbrd.c +++ b/arch/blackfin/mach-bf518/boards/ezbrd.c @@ -529,6 +529,8 @@ static struct platform_device bfin_i2s = { #endif #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) +static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0}; + static struct resource bfin_twi0_resource[] = { [0] = { .start = TWI0_REGBASE, @@ -547,6 +549,9 @@ static struct platform_device i2c_bfin_twi_device = { .id = 0, .num_resources = ARRAY_SIZE(bfin_twi0_resource), .resource = bfin_twi0_resource, + .dev = { + .platform_data = &bfin_twi0_pins, + }, }; #endif diff --git a/arch/blackfin/mach-bf518/boards/tcm-bf518.c b/arch/blackfin/mach-bf518/boards/tcm-bf518.c index 6eebee4e4217..0bedc737566b 100644 --- a/arch/blackfin/mach-bf518/boards/tcm-bf518.c +++ b/arch/blackfin/mach-bf518/boards/tcm-bf518.c @@ -455,6 +455,8 @@ static struct platform_device bfin_sir1_device = { #endif #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) +static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0}; + static struct resource bfin_twi0_resource[] = { [0] = { .start = TWI0_REGBASE, @@ -473,6 +475,9 @@ static struct platform_device i2c_bfin_twi_device = { .id = 0, .num_resources = ARRAY_SIZE(bfin_twi0_resource), .resource = bfin_twi0_resource, + .dev = { + .platform_data = &bfin_twi0_pins, + }, }; #endif diff --git a/arch/blackfin/mach-bf518/include/mach/anomaly.h b/arch/blackfin/mach-bf518/include/mach/anomaly.h index 56383f7cbc07..845e6bc8d633 100644 --- a/arch/blackfin/mach-bf518/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf518/include/mach/anomaly.h @@ -6,8 +6,7 @@ * DO NOT EDIT THIS FILE * * Copyright 2004-2011 Analog Devices Inc. - * Licensed under the ADI BSD license. - * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd + * Licensed under the Clear BSD license. */ /* This file should be up to date with: diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF512.h b/arch/blackfin/mach-bf518/include/mach/cdefBF512.h index bb79627f0929..1c03ad4bcb72 100644 --- a/arch/blackfin/mach-bf518/include/mach/cdefBF512.h +++ b/arch/blackfin/mach-bf518/include/mach/cdefBF512.h @@ -1,7 +1,7 @@ /* * Copyright 2008-2010 Analog Devices Inc. * - * Licensed under the ADI BSD license or the GPL-2 (or later) + * Licensed under the Clear BSD license or the GPL-2 (or later) */ #ifndef _CDEF_BF512_H diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF514.h b/arch/blackfin/mach-bf518/include/mach/cdefBF514.h index dc988668203e..861221d1dcc9 100644 --- a/arch/blackfin/mach-bf518/include/mach/cdefBF514.h +++ b/arch/blackfin/mach-bf518/include/mach/cdefBF514.h @@ -1,7 +1,7 @@ /* * Copyright 2008-2010 Analog Devices Inc. * - * Licensed under the ADI BSD license or the GPL-2 (or later) + * Licensed under the Clear BSD license or the GPL-2 (or later) */ #ifndef _CDEF_BF514_H diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF516.h b/arch/blackfin/mach-bf518/include/mach/cdefBF516.h index 142e45cbc253..cc9bf0d378c3 100644 --- a/arch/blackfin/mach-bf518/include/mach/cdefBF516.h +++ b/arch/blackfin/mach-bf518/include/mach/cdefBF516.h @@ -1,7 +1,7 @@ /* * Copyright 2008-2010 Analog Devices Inc. * - * Licensed under the ADI BSD license or the GPL-2 (or later) + * Licensed under the Clear BSD license or the GPL-2 (or later) */ #ifndef _CDEF_BF516_H diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF518.h b/arch/blackfin/mach-bf518/include/mach/cdefBF518.h index e638197bf8b1..96a82fd62ef1 100644 --- a/arch/blackfin/mach-bf518/include/mach/cdefBF518.h +++ b/arch/blackfin/mach-bf518/include/mach/cdefBF518.h @@ -1,7 +1,7 @@ /* * Copyright 2008-2010 Analog Devices Inc. * - * Licensed under the ADI BSD license or the GPL-2 (or later) + * Licensed under the Clear BSD license or the GPL-2 (or later) */ #ifndef _CDEF_BF518_H diff --git a/arch/blackfin/mach-bf518/include/mach/defBF512.h b/arch/blackfin/mach-bf518/include/mach/defBF512.h index 729704078cd7..e6a017faad01 100644 --- a/arch/blackfin/mach-bf518/include/mach/defBF512.h +++ b/arch/blackfin/mach-bf518/include/mach/defBF512.h @@ -1,7 +1,7 @@ /* * Copyright 2008-2010 Analog Devices Inc. * - * Licensed under the ADI BSD license or the GPL-2 (or later) + * Licensed under the Clear BSD license or the GPL-2 (or later) */ #ifndef _DEF_BF512_H @@ -1083,77 +1083,6 @@ #define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */ -/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/ -/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */ -#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */ -#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */ - -/* TWI_PRESCALE Masks */ -#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */ -#define TWI_ENA 0x0080 /* TWI Enable */ -#define SCCB 0x0200 /* SCCB Compatibility Enable */ - -/* TWI_SLAVE_CTL Masks */ -#define SEN 0x0001 /* Slave Enable */ -#define SADD_LEN 0x0002 /* Slave Address Length */ -#define STDVAL 0x0004 /* Slave Transmit Data Valid */ -#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */ -#define GEN 0x0010 /* General Call Adrress Matching Enabled */ - -/* TWI_SLAVE_STAT Masks */ -#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */ -#define GCALL 0x0002 /* General Call Indicator */ - -/* TWI_MASTER_CTL Masks */ -#define MEN 0x0001 /* Master Mode Enable */ -#define MADD_LEN 0x0002 /* Master Address Length */ -#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */ -#define FAST 0x0008 /* Use Fast Mode Timing Specs */ -#define STOP 0x0010 /* Issue Stop Condition */ -#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */ -#define DCNT 0x3FC0 /* Data Bytes To Transfer */ -#define SDAOVR 0x4000 /* Serial Data Override */ -#define SCLOVR 0x8000 /* Serial Clock Override */ - -/* TWI_MASTER_STAT Masks */ -#define MPROG 0x0001 /* Master Transfer In Progress */ -#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */ -#define ANAK 0x0004 /* Address Not Acknowledged */ -#define DNAK 0x0008 /* Data Not Acknowledged */ -#define BUFRDERR 0x0010 /* Buffer Read Error */ -#define BUFWRERR 0x0020 /* Buffer Write Error */ -#define SDASEN 0x0040 /* Serial Data Sense */ -#define SCLSEN 0x0080 /* Serial Clock Sense */ -#define BUSBUSY 0x0100 /* Bus Busy Indicator */ - -/* TWI_INT_SRC and TWI_INT_ENABLE Masks */ -#define SINIT 0x0001 /* Slave Transfer Initiated */ -#define SCOMP 0x0002 /* Slave Transfer Complete */ -#define SERR 0x0004 /* Slave Transfer Error */ -#define SOVF 0x0008 /* Slave Overflow */ -#define MCOMP 0x0010 /* Master Transfer Complete */ -#define MERR 0x0020 /* Master Transfer Error */ -#define XMTSERV 0x0040 /* Transmit FIFO Service */ -#define RCVSERV 0x0080 /* Receive FIFO Service */ - -/* TWI_FIFO_CTRL Masks */ -#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */ -#define RCVFLUSH 0x0002 /* Receive Buffer Flush */ -#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */ -#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */ - -/* TWI_FIFO_STAT Masks */ -#define XMTSTAT 0x0003 /* Transmit FIFO Status */ -#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */ -#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */ -#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */ - -#define RCVSTAT 0x000C /* Receive FIFO Status */ -#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */ -#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */ -#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */ - - /* ******************* PIN CONTROL REGISTER MASKS ************************/ /* PORT_MUX Masks */ #define PJSE 0x0001 /* Port J SPI/SPORT Enable */ diff --git a/arch/blackfin/mach-bf518/include/mach/defBF514.h b/arch/blackfin/mach-bf518/include/mach/defBF514.h index cfab428e577c..97feaa629ed7 100644 --- a/arch/blackfin/mach-bf518/include/mach/defBF514.h +++ b/arch/blackfin/mach-bf518/include/mach/defBF514.h @@ -1,7 +1,7 @@ /* * Copyright 2008-2009 Analog Devices Inc. * - * Licensed under the ADI BSD license or the GPL-2 (or later) + * Licensed under the Clear BSD license or the GPL-2 (or later) */ #ifndef _DEF_BF514_H diff --git a/arch/blackfin/mach-bf518/include/mach/defBF516.h b/arch/blackfin/mach-bf518/include/mach/defBF516.h index 22a3aa0d2629..7c79cb6a03b1 100644 --- a/arch/blackfin/mach-bf518/include/mach/defBF516.h +++ b/arch/blackfin/mach-bf518/include/mach/defBF516.h @@ -1,7 +1,7 @@ /* * Copyright 2008-2009 Analog Devices Inc. * - * Licensed under the ADI BSD license or the GPL-2 (or later) + * Licensed under the Clear BSD license or the GPL-2 (or later) */ #ifndef _DEF_BF516_H diff --git a/arch/blackfin/mach-bf518/include/mach/defBF518.h b/arch/blackfin/mach-bf518/include/mach/defBF518.h index cb18270e55c2..12042ff13601 100644 --- a/arch/blackfin/mach-bf518/include/mach/defBF518.h +++ b/arch/blackfin/mach-bf518/include/mach/defBF518.h @@ -1,7 +1,7 @@ /* * Copyright 2008-2009 Analog Devices Inc. * - * Licensed under the ADI BSD license or the GPL-2 (or later) + * Licensed under the Clear BSD license or the GPL-2 (or later) */ #ifndef _DEF_BF518_H diff --git a/arch/blackfin/mach-bf527/boards/ad7160eval.c b/arch/blackfin/mach-bf527/boards/ad7160eval.c index fad7fea1b0bf..d58f50e5aa4b 100644 --- a/arch/blackfin/mach-bf527/boards/ad7160eval.c +++ b/arch/blackfin/mach-bf527/boards/ad7160eval.c @@ -569,6 +569,8 @@ static const struct ad7160_platform_data bfin_ad7160_ts_info = { #endif #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) +static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0}; + static struct resource bfin_twi0_resource[] = { [0] = { .start = TWI0_REGBASE, @@ -587,6 +589,9 @@ static struct platform_device i2c_bfin_twi_device = { .id = 0, .num_resources = ARRAY_SIZE(bfin_twi0_resource), .resource = bfin_twi0_resource, + .dev = { + .platform_data = &bfin_twi0_pins, + }, }; #endif @@ -681,6 +686,7 @@ static struct bfin_rotary_platform_data bfin_rotary_data = { .rotary_button_key = KEY_ENTER, .debounce = 10, /* 0..17 */ .mode = ROT_QUAD_ENC | ROT_DEBE, + .pm_wakeup = 1, }; static struct resource bfin_rotary_resources[] = { diff --git a/arch/blackfin/mach-bf527/boards/cm_bf527.c b/arch/blackfin/mach-bf527/boards/cm_bf527.c index 65b7fbd30e16..413d0132b66f 100644 --- a/arch/blackfin/mach-bf527/boards/cm_bf527.c +++ b/arch/blackfin/mach-bf527/boards/cm_bf527.c @@ -698,6 +698,8 @@ static struct platform_device bfin_sir1_device = { #endif #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) +static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0}; + static struct resource bfin_twi0_resource[] = { [0] = { .start = TWI0_REGBASE, @@ -716,6 +718,9 @@ static struct platform_device i2c_bfin_twi_device = { .id = 0, .num_resources = ARRAY_SIZE(bfin_twi0_resource), .resource = bfin_twi0_resource, + .dev = { + .platform_data = &bfin_twi0_pins, + }, }; #endif diff --git a/arch/blackfin/mach-bf527/boards/ezbrd.c b/arch/blackfin/mach-bf527/boards/ezbrd.c index 17c6a24cc076..50bda79194e5 100644 --- a/arch/blackfin/mach-bf527/boards/ezbrd.c +++ b/arch/blackfin/mach-bf527/boards/ezbrd.c @@ -576,6 +576,8 @@ static struct platform_device bfin_sir1_device = { #endif #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) +static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0}; + static struct resource bfin_twi0_resource[] = { [0] = { .start = TWI0_REGBASE, @@ -594,6 +596,9 @@ static struct platform_device i2c_bfin_twi_device = { .id = 0, .num_resources = ARRAY_SIZE(bfin_twi0_resource), .resource = bfin_twi0_resource, + .dev = { + .platform_data = &bfin_twi0_pins, + }, }; #endif diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c index 2f9a2bd83ce4..af732eb3a687 100644 --- a/arch/blackfin/mach-bf527/boards/ezkit.c +++ b/arch/blackfin/mach-bf527/boards/ezkit.c @@ -869,6 +869,8 @@ static struct platform_device bfin_sir1_device = { #endif #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) +static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0}; + static struct resource bfin_twi0_resource[] = { [0] = { .start = TWI0_REGBASE, @@ -887,6 +889,9 @@ static struct platform_device i2c_bfin_twi_device = { .id = 0, .num_resources = ARRAY_SIZE(bfin_twi0_resource), .resource = bfin_twi0_resource, + .dev = { + .platform_data = &bfin_twi0_pins, + }, }; #endif @@ -1105,6 +1110,7 @@ static struct bfin_rotary_platform_data bfin_rotary_data = { .rotary_button_key = KEY_ENTER, .debounce = 10, /* 0..17 */ .mode = ROT_QUAD_ENC | ROT_DEBE, + .pm_wakeup = 1, }; static struct resource bfin_rotary_resources[] = { diff --git a/arch/blackfin/mach-bf527/boards/tll6527m.c b/arch/blackfin/mach-bf527/boards/tll6527m.c index d192c0ac941c..1509c5a8a3ff 100644 --- a/arch/blackfin/mach-bf527/boards/tll6527m.c +++ b/arch/blackfin/mach-bf527/boards/tll6527m.c @@ -656,6 +656,8 @@ static struct platform_device bfin_sir1_device = { #endif #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) +static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0}; + static struct resource bfin_twi0_resource[] = { [0] = { .start = TWI0_REGBASE, @@ -674,6 +676,9 @@ static struct platform_device i2c_bfin_twi_device = { .id = 0, .num_resources = ARRAY_SIZE(bfin_twi0_resource), .resource = bfin_twi0_resource, + .dev = { + .platform_data = &bfin_twi0_pins, + }, }; #endif diff --git a/arch/blackfin/mach-bf527/include/mach/anomaly.h b/arch/blackfin/mach-bf527/include/mach/anomaly.h index 688470611e15..aa14110be4c4 100644 --- a/arch/blackfin/mach-bf527/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf527/include/mach/anomaly.h @@ -6,8 +6,7 @@ * DO NOT EDIT THIS FILE * * Copyright 2004-2011 Analog Devices Inc. - * Licensed under the ADI BSD license. - * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd + * Licensed under the Clear BSD license. */ /* This file should be up to date with: diff --git a/arch/blackfin/mach-bf527/include/mach/defBF522.h b/arch/blackfin/mach-bf527/include/mach/defBF522.h index 37d353a19722..e007017cf958 100644 --- a/arch/blackfin/mach-bf527/include/mach/defBF522.h +++ b/arch/blackfin/mach-bf527/include/mach/defBF522.h @@ -1,7 +1,7 @@ /* * Copyright 2007-2010 Analog Devices Inc. * - * Licensed under the ADI BSD license or the GPL-2 (or later) + * Licensed under the Clear BSD license or the GPL-2 (or later) */ #ifndef _DEF_BF522_H @@ -1084,77 +1084,6 @@ #define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */ -/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/ -/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */ -#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */ -#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */ - -/* TWI_PRESCALE Masks */ -#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */ -#define TWI_ENA 0x0080 /* TWI Enable */ -#define SCCB 0x0200 /* SCCB Compatibility Enable */ - -/* TWI_SLAVE_CTL Masks */ -#define SEN 0x0001 /* Slave Enable */ -#define SADD_LEN 0x0002 /* Slave Address Length */ -#define STDVAL 0x0004 /* Slave Transmit Data Valid */ -#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */ -#define GEN 0x0010 /* General Call Adrress Matching Enabled */ - -/* TWI_SLAVE_STAT Masks */ -#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */ -#define GCALL 0x0002 /* General Call Indicator */ - -/* TWI_MASTER_CTL Masks */ -#define MEN 0x0001 /* Master Mode Enable */ -#define MADD_LEN 0x0002 /* Master Address Length */ -#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */ -#define FAST 0x0008 /* Use Fast Mode Timing Specs */ -#define STOP 0x0010 /* Issue Stop Condition */ -#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */ -#define DCNT 0x3FC0 /* Data Bytes To Transfer */ -#define SDAOVR 0x4000 /* Serial Data Override */ -#define SCLOVR 0x8000 /* Serial Clock Override */ - -/* TWI_MASTER_STAT Masks */ -#define MPROG 0x0001 /* Master Transfer In Progress */ -#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */ -#define ANAK 0x0004 /* Address Not Acknowledged */ -#define DNAK 0x0008 /* Data Not Acknowledged */ -#define BUFRDERR 0x0010 /* Buffer Read Error */ -#define BUFWRERR 0x0020 /* Buffer Write Error */ -#define SDASEN 0x0040 /* Serial Data Sense */ -#define SCLSEN 0x0080 /* Serial Clock Sense */ -#define BUSBUSY 0x0100 /* Bus Busy Indicator */ - -/* TWI_INT_SRC and TWI_INT_ENABLE Masks */ -#define SINIT 0x0001 /* Slave Transfer Initiated */ -#define SCOMP 0x0002 /* Slave Transfer Complete */ -#define SERR 0x0004 /* Slave Transfer Error */ -#define SOVF 0x0008 /* Slave Overflow */ -#define MCOMP 0x0010 /* Master Transfer Complete */ -#define MERR 0x0020 /* Master Transfer Error */ -#define XMTSERV 0x0040 /* Transmit FIFO Service */ -#define RCVSERV 0x0080 /* Receive FIFO Service */ - -/* TWI_FIFO_CTRL Masks */ -#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */ -#define RCVFLUSH 0x0002 /* Receive Buffer Flush */ -#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */ -#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */ - -/* TWI_FIFO_STAT Masks */ -#define XMTSTAT 0x0003 /* Transmit FIFO Status */ -#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */ -#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */ -#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */ - -#define RCVSTAT 0x000C /* Receive FIFO Status */ -#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */ -#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */ -#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */ - - /* Omit CAN masks from defBF534.h */ /* ******************* PIN CONTROL REGISTER MASKS ************************/ diff --git a/arch/blackfin/mach-bf527/include/mach/defBF525.h b/arch/blackfin/mach-bf527/include/mach/defBF525.h index aab80bb1a683..71578d964d00 100644 --- a/arch/blackfin/mach-bf527/include/mach/defBF525.h +++ b/arch/blackfin/mach-bf527/include/mach/defBF525.h @@ -1,7 +1,7 @@ /* * Copyright 2007-2010 Analog Devices Inc. * - * Licensed under the ADI BSD license or the GPL-2 (or later) + * Licensed under the Clear BSD license or the GPL-2 (or later) */ #ifndef _DEF_BF525_H diff --git a/arch/blackfin/mach-bf527/include/mach/defBF527.h b/arch/blackfin/mach-bf527/include/mach/defBF527.h index 05369a92fbc8..aeb84795b35e 100644 --- a/arch/blackfin/mach-bf527/include/mach/defBF527.h +++ b/arch/blackfin/mach-bf527/include/mach/defBF527.h @@ -1,7 +1,7 @@ /* * Copyright 2007-2010 Analog Devices Inc. * - * Licensed under the ADI BSD license or the GPL-2 (or later) + * Licensed under the Clear BSD license or the GPL-2 (or later) */ #ifndef _DEF_BF527_H diff --git a/arch/blackfin/mach-bf533/include/mach/anomaly.h b/arch/blackfin/mach-bf533/include/mach/anomaly.h index 03f2b40912a3..3a8f73a669f0 100644 --- a/arch/blackfin/mach-bf533/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf533/include/mach/anomaly.h @@ -6,8 +6,7 @@ * DO NOT EDIT THIS FILE * * Copyright 2004-2011 Analog Devices Inc. - * Licensed under the ADI BSD license. - * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd + * Licensed under the Clear BSD license. */ /* This file should be up to date with: diff --git a/arch/blackfin/mach-bf533/include/mach/defBF532.h b/arch/blackfin/mach-bf533/include/mach/defBF532.h index 2376d5393511..d438150b1025 100644 --- a/arch/blackfin/mach-bf533/include/mach/defBF532.h +++ b/arch/blackfin/mach-bf533/include/mach/defBF532.h @@ -3,7 +3,7 @@ * * Copyright 2005-2010 Analog Devices Inc. * - * Licensed under the ADI BSD license or the GPL-2 (or later) + * Licensed under the Clear BSD license or the GPL-2 (or later) */ #ifndef _DEF_BF532_H diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537e.c b/arch/blackfin/mach-bf537/boards/cm_bf537e.c index 27fd2c32ae9a..9408ab56d87f 100644 --- a/arch/blackfin/mach-bf537/boards/cm_bf537e.c +++ b/arch/blackfin/mach-bf537/boards/cm_bf537e.c @@ -486,6 +486,8 @@ static struct platform_device bfin_sir1_device = { #endif #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) +static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0}; + static struct resource bfin_twi0_resource[] = { [0] = { .start = TWI0_REGBASE, @@ -504,6 +506,9 @@ static struct platform_device i2c_bfin_twi_device = { .id = 0, .num_resources = ARRAY_SIZE(bfin_twi0_resource), .resource = bfin_twi0_resource, + .dev = { + .platform_data = &bfin_twi0_pins, + }, }; #endif diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537u.c b/arch/blackfin/mach-bf537/boards/cm_bf537u.c index 3f3abad86ec3..0143d8bef909 100644 --- a/arch/blackfin/mach-bf537/boards/cm_bf537u.c +++ b/arch/blackfin/mach-bf537/boards/cm_bf537u.c @@ -451,6 +451,8 @@ static struct platform_device bfin_sir1_device = { #endif #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) +static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0}; + static struct resource bfin_twi0_resource[] = { [0] = { .start = TWI0_REGBASE, @@ -469,6 +471,9 @@ static struct platform_device i2c_bfin_twi_device = { .id = 0, .num_resources = ARRAY_SIZE(bfin_twi0_resource), .resource = bfin_twi0_resource, + .dev = { + .platform_data = &bfin_twi0_pins, + }, }; #endif diff --git a/arch/blackfin/mach-bf537/boards/dnp5370.c b/arch/blackfin/mach-bf537/boards/dnp5370.c index 6f77bf708ec0..8bbf0a23fd49 100644 --- a/arch/blackfin/mach-bf537/boards/dnp5370.c +++ b/arch/blackfin/mach-bf537/boards/dnp5370.c @@ -329,6 +329,8 @@ static struct platform_device bfin_uart1_device = { #endif #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) +static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0}; + static struct resource bfin_twi0_resource[] = { [0] = { .start = TWI0_REGBASE, @@ -347,6 +349,9 @@ static struct platform_device i2c_bfin_twi_device = { .id = 0, .num_resources = ARRAY_SIZE(bfin_twi0_resource), .resource = bfin_twi0_resource, + .dev = { + .platform_data = &bfin_twi0_pins, + }, }; #endif diff --git a/arch/blackfin/mach-bf537/boards/minotaur.c b/arch/blackfin/mach-bf537/boards/minotaur.c index d2d71282618f..a10f90e444bc 100644 --- a/arch/blackfin/mach-bf537/boards/minotaur.c +++ b/arch/blackfin/mach-bf537/boards/minotaur.c @@ -386,6 +386,8 @@ static struct platform_device bfin_sir1_device = { #endif #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) +static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0}; + static struct resource bfin_twi0_resource[] = { [0] = { .start = TWI0_REGBASE, @@ -404,6 +406,9 @@ static struct platform_device i2c_bfin_twi_device = { .id = 0, .num_resources = ARRAY_SIZE(bfin_twi0_resource), .resource = bfin_twi0_resource, + .dev = { + .platform_data = &bfin_twi0_pins, + }, }; #endif diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c index f3562b0922af..c9d9473a5ab2 100644 --- a/arch/blackfin/mach-bf537/boards/stamp.c +++ b/arch/blackfin/mach-bf537/boards/stamp.c @@ -1790,6 +1790,8 @@ static struct platform_device bfin_sir1_device = { #endif #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) +static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0}; + static struct resource bfin_twi0_resource[] = { [0] = { .start = TWI0_REGBASE, @@ -1808,6 +1810,9 @@ static struct platform_device i2c_bfin_twi_device = { .id = 0, .num_resources = ARRAY_SIZE(bfin_twi0_resource), .resource = bfin_twi0_resource, + .dev = { + .platform_data = &bfin_twi0_pins, + }, }; #endif @@ -2361,7 +2366,13 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = { }, #endif }; - +#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) \ +|| defined(CONFIG_BFIN_SPORT) || defined(CONFIG_BFIN_SPORT_MODULE) +unsigned short bfin_sport0_peripherals[] = { + P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, + P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 +}; +#endif #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART static struct resource bfin_sport0_uart_resources[] = { @@ -2382,11 +2393,6 @@ static struct resource bfin_sport0_uart_resources[] = { }, }; -static unsigned short bfin_sport0_peripherals[] = { - P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, - P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0 -}; - static struct platform_device bfin_sport0_uart_device = { .name = "bfin-sport-uart", .id = 0, @@ -2432,7 +2438,49 @@ static struct platform_device bfin_sport1_uart_device = { }; #endif #endif - +#if defined(CONFIG_BFIN_SPORT) || defined(CONFIG_BFIN_SPORT_MODULE) +static struct resource bfin_sport0_resources[] = { + { + .start = SPORT0_TCR1, + .end = SPORT0_MRCS3+4, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_SPORT0_RX, + .end = IRQ_SPORT0_RX+1, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_SPORT0_TX, + .end = IRQ_SPORT0_TX+1, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_SPORT0_ERROR, + .end = IRQ_SPORT0_ERROR, + .flags = IORESOURCE_IRQ, + }, + { + .start = CH_SPORT0_TX, + .end = CH_SPORT0_TX, + .flags = IORESOURCE_DMA, + }, + { + .start = CH_SPORT0_RX, + .end = CH_SPORT0_RX, + .flags = IORESOURCE_DMA, + }, +}; +static struct platform_device bfin_sport0_device = { + .name = "bfin_sport_raw", + .id = 0, + .num_resources = ARRAY_SIZE(bfin_sport0_resources), + .resource = bfin_sport0_resources, + .dev = { + .platform_data = &bfin_sport0_peripherals, /* Passed to driver */ + }, +}; +#endif #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) #define CF_IDE_NAND_CARD_USE_HDD_INTERFACE /* #define CF_IDE_NAND_CARD_USE_CF_IN_COMMON_MEMORY_MODE */ @@ -2754,7 +2802,9 @@ static struct platform_device bf5xx_adau1701_device = { static struct platform_device *stamp_devices[] __initdata = { &bfin_dpmc, - +#if defined(CONFIG_BFIN_SPORT) || defined(CONFIG_BFIN_SPORT_MODULE) + &bfin_sport0_device, +#endif #if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE) &bfin_pcmcia_cf_device, #endif diff --git a/arch/blackfin/mach-bf537/boards/tcm_bf537.c b/arch/blackfin/mach-bf537/boards/tcm_bf537.c index 3fb421823857..e285c3675286 100644 --- a/arch/blackfin/mach-bf537/boards/tcm_bf537.c +++ b/arch/blackfin/mach-bf537/boards/tcm_bf537.c @@ -453,6 +453,8 @@ static struct platform_device bfin_sir1_device = { #endif #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) +static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0}; + static struct resource bfin_twi0_resource[] = { [0] = { .start = TWI0_REGBASE, @@ -471,6 +473,9 @@ static struct platform_device i2c_bfin_twi_device = { .id = 0, .num_resources = ARRAY_SIZE(bfin_twi0_resource), .resource = bfin_twi0_resource, + .dev = { + .platform_data = &bfin_twi0_pins, + }, }; #endif diff --git a/arch/blackfin/mach-bf537/include/mach/anomaly.h b/arch/blackfin/mach-bf537/include/mach/anomaly.h index 543cd3fb305e..df9212696397 100644 --- a/arch/blackfin/mach-bf537/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf537/include/mach/anomaly.h @@ -6,8 +6,7 @@ * DO NOT EDIT THIS FILE * * Copyright 2004-2011 Analog Devices Inc. - * Licensed under the ADI BSD license. - * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd + * Licensed under the Clear BSD license. */ /* This file should be up to date with: diff --git a/arch/blackfin/mach-bf537/include/mach/defBF534.h b/arch/blackfin/mach-bf537/include/mach/defBF534.h index 4a031dde173f..ef6a98cdfd44 100644 --- a/arch/blackfin/mach-bf537/include/mach/defBF534.h +++ b/arch/blackfin/mach-bf537/include/mach/defBF534.h @@ -1,7 +1,7 @@ /* * Copyright 2005-2010 Analog Devices Inc. * - * Licensed under the ADI BSD license or the GPL-2 (or later) + * Licensed under the Clear BSD license or the GPL-2 (or later) */ #ifndef _DEF_BF534_H @@ -1403,75 +1403,6 @@ #define ERR_DET 0x4000 /* Error Detected Indicator */ #define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */ -/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/ -/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */ -#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */ -#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */ - -/* TWI_PRESCALE Masks */ -#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */ -#define TWI_ENA 0x0080 /* TWI Enable */ -#define SCCB 0x0200 /* SCCB Compatibility Enable */ - -/* TWI_SLAVE_CTL Masks */ -#define SEN 0x0001 /* Slave Enable */ -#define SADD_LEN 0x0002 /* Slave Address Length */ -#define STDVAL 0x0004 /* Slave Transmit Data Valid */ -#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */ -#define GEN 0x0010 /* General Call Address Matching Enabled */ - -/* TWI_SLAVE_STAT Masks */ -#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */ -#define GCALL 0x0002 /* General Call Indicator */ - -/* TWI_MASTER_CTL Masks */ -#define MEN 0x0001 /* Master Mode Enable */ -#define MADD_LEN 0x0002 /* Master Address Length */ -#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */ -#define FAST 0x0008 /* Use Fast Mode Timing Specs */ -#define STOP 0x0010 /* Issue Stop Condition */ -#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */ -#define DCNT 0x3FC0 /* Data Bytes To Transfer */ -#define SDAOVR 0x4000 /* Serial Data Override */ -#define SCLOVR 0x8000 /* Serial Clock Override */ - -/* TWI_MASTER_STAT Masks */ -#define MPROG 0x0001 /* Master Transfer In Progress */ -#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */ -#define ANAK 0x0004 /* Address Not Acknowledged */ -#define DNAK 0x0008 /* Data Not Acknowledged */ -#define BUFRDERR 0x0010 /* Buffer Read Error */ -#define BUFWRERR 0x0020 /* Buffer Write Error */ -#define SDASEN 0x0040 /* Serial Data Sense */ -#define SCLSEN 0x0080 /* Serial Clock Sense */ -#define BUSBUSY 0x0100 /* Bus Busy Indicator */ - -/* TWI_INT_SRC and TWI_INT_ENABLE Masks */ -#define SINIT 0x0001 /* Slave Transfer Initiated */ -#define SCOMP 0x0002 /* Slave Transfer Complete */ -#define SERR 0x0004 /* Slave Transfer Error */ -#define SOVF 0x0008 /* Slave Overflow */ -#define MCOMP 0x0010 /* Master Transfer Complete */ -#define MERR 0x0020 /* Master Transfer Error */ -#define XMTSERV 0x0040 /* Transmit FIFO Service */ -#define RCVSERV 0x0080 /* Receive FIFO Service */ - -/* TWI_FIFO_CTRL Masks */ -#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */ -#define RCVFLUSH 0x0002 /* Receive Buffer Flush */ -#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */ -#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */ - -/* TWI_FIFO_STAT Masks */ -#define XMTSTAT 0x0003 /* Transmit FIFO Status */ -#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */ -#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */ -#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */ - -#define RCVSTAT 0x000C /* Receive FIFO Status */ -#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */ -#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */ -#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */ /* ******************* PIN CONTROL REGISTER MASKS ************************/ /* PORT_MUX Masks */ diff --git a/arch/blackfin/mach-bf537/include/mach/defBF537.h b/arch/blackfin/mach-bf537/include/mach/defBF537.h index 3d471d752684..e10332c9f660 100644 --- a/arch/blackfin/mach-bf537/include/mach/defBF537.h +++ b/arch/blackfin/mach-bf537/include/mach/defBF537.h @@ -1,7 +1,7 @@ /* * Copyright 2005-2010 Analog Devices Inc. * - * Licensed under the ADI BSD license or the GPL-2 (or later) + * Licensed under the Clear BSD license or the GPL-2 (or later) */ #ifndef _DEF_BF537_H diff --git a/arch/blackfin/mach-bf538/boards/ezkit.c b/arch/blackfin/mach-bf538/boards/ezkit.c index 1633a6f306c0..a4fce0370c1d 100644 --- a/arch/blackfin/mach-bf538/boards/ezkit.c +++ b/arch/blackfin/mach-bf538/boards/ezkit.c @@ -38,7 +38,7 @@ static struct platform_device rtc_device = { .name = "rtc-bfin", .id = -1, }; -#endif +#endif /* CONFIG_RTC_DRV_BFIN */ #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) #ifdef CONFIG_SERIAL_BFIN_UART0 @@ -100,7 +100,7 @@ static struct platform_device bfin_uart0_device = { .platform_data = &bfin_uart0_peripherals, /* Passed to driver */ }, }; -#endif +#endif /* CONFIG_SERIAL_BFIN_UART0 */ #ifdef CONFIG_SERIAL_BFIN_UART1 static struct resource bfin_uart1_resources[] = { { @@ -148,7 +148,7 @@ static struct platform_device bfin_uart1_device = { .platform_data = &bfin_uart1_peripherals, /* Passed to driver */ }, }; -#endif +#endif /* CONFIG_SERIAL_BFIN_UART1 */ #ifdef CONFIG_SERIAL_BFIN_UART2 static struct resource bfin_uart2_resources[] = { { @@ -196,8 +196,8 @@ static struct platform_device bfin_uart2_device = { .platform_data = &bfin_uart2_peripherals, /* Passed to driver */ }, }; -#endif -#endif +#endif /* CONFIG_SERIAL_BFIN_UART2 */ +#endif /* CONFIG_SERIAL_BFIN */ #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) #ifdef CONFIG_BFIN_SIR0 @@ -224,7 +224,7 @@ static struct platform_device bfin_sir0_device = { .num_resources = ARRAY_SIZE(bfin_sir0_resources), .resource = bfin_sir0_resources, }; -#endif +#endif /* CONFIG_BFIN_SIR0 */ #ifdef CONFIG_BFIN_SIR1 static struct resource bfin_sir1_resources[] = { { @@ -249,7 +249,7 @@ static struct platform_device bfin_sir1_device = { .num_resources = ARRAY_SIZE(bfin_sir1_resources), .resource = bfin_sir1_resources, }; -#endif +#endif /* CONFIG_BFIN_SIR1 */ #ifdef CONFIG_BFIN_SIR2 static struct resource bfin_sir2_resources[] = { { @@ -274,8 +274,8 @@ static struct platform_device bfin_sir2_device = { .num_resources = ARRAY_SIZE(bfin_sir2_resources), .resource = bfin_sir2_resources, }; -#endif -#endif +#endif /* CONFIG_BFIN_SIR2 */ +#endif /* CONFIG_BFIN_SIR */ #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART @@ -311,7 +311,7 @@ static struct platform_device bfin_sport0_uart_device = { .platform_data = &bfin_sport0_peripherals, /* Passed to driver */ }, }; -#endif +#endif /* CONFIG_SERIAL_BFIN_SPORT0_UART */ #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART static struct resource bfin_sport1_uart_resources[] = { { @@ -345,7 +345,7 @@ static struct platform_device bfin_sport1_uart_device = { .platform_data = &bfin_sport1_peripherals, /* Passed to driver */ }, }; -#endif +#endif /* CONFIG_SERIAL_BFIN_SPORT1_UART */ #ifdef CONFIG_SERIAL_BFIN_SPORT2_UART static struct resource bfin_sport2_uart_resources[] = { { @@ -379,7 +379,7 @@ static struct platform_device bfin_sport2_uart_device = { .platform_data = &bfin_sport2_peripherals, /* Passed to driver */ }, }; -#endif +#endif /* CONFIG_SERIAL_BFIN_SPORT2_UART */ #ifdef CONFIG_SERIAL_BFIN_SPORT3_UART static struct resource bfin_sport3_uart_resources[] = { { @@ -413,8 +413,8 @@ static struct platform_device bfin_sport3_uart_device = { .platform_data = &bfin_sport3_peripherals, /* Passed to driver */ }, }; -#endif -#endif +#endif /* CONFIG_SERIAL_BFIN_SPORT3_UART */ +#endif /* CONFIG_SERIAL_BFIN_SPORT */ #if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE) static unsigned short bfin_can_peripherals[] = { @@ -452,7 +452,7 @@ static struct platform_device bfin_can_device = { .platform_data = &bfin_can_peripherals, /* Passed to driver */ }, }; -#endif +#endif /* CONFIG_CAN_BFIN */ /* * USB-LAN EzExtender board @@ -488,7 +488,7 @@ static struct platform_device smc91x_device = { .platform_data = &smc91x_info, }, }; -#endif +#endif /* CONFIG_SMC91X */ #if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE) /* all SPI peripherals info goes here */ @@ -518,7 +518,8 @@ static struct flash_platform_data bfin_spi_flash_data = { static struct bfin5xx_spi_chip spi_flash_chip_info = { .enable_dma = 0, /* use dma transfer with this chip*/ }; -#endif +#endif /* CONFIG_MTD_M25P80 */ +#endif /* CONFIG_SPI_BFIN5XX */ #if defined(CONFIG_TOUCHSCREEN_AD7879) || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE) #include <linux/spi/ad7879.h> @@ -535,7 +536,7 @@ static const struct ad7879_platform_data bfin_ad7879_ts_info = { .gpio_export = 1, /* Export GPIO to gpiolib */ .gpio_base = -1, /* Dynamic allocation */ }; -#endif +#endif /* CONFIG_TOUCHSCREEN_AD7879 */ #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE) #include <asm/bfin-lq035q1.h> @@ -564,7 +565,7 @@ static struct platform_device bfin_lq035q1_device = { .platform_data = &bfin_lq035q1_data, }, }; -#endif +#endif /* CONFIG_FB_BFIN_LQ035Q1 */ static struct spi_board_info bf538_spi_board_info[] __initdata = { #if defined(CONFIG_MTD_M25P80) \ @@ -579,7 +580,7 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = { .controller_data = &spi_flash_chip_info, .mode = SPI_MODE_3, }, -#endif +#endif /* CONFIG_MTD_M25P80 */ #if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE) { .modalias = "ad7879", @@ -590,7 +591,7 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = { .chip_select = 1, .mode = SPI_CPHA | SPI_CPOL, }, -#endif +#endif /* CONFIG_TOUCHSCREEN_AD7879_SPI */ #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE) { .modalias = "bfin-lq035q1-spi", @@ -599,7 +600,7 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = { .chip_select = 2, .mode = SPI_CPHA | SPI_CPOL, }, -#endif +#endif /* CONFIG_FB_BFIN_LQ035Q1 */ #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) { .modalias = "spidev", @@ -607,7 +608,7 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = { .bus_num = 0, .chip_select = 1, }, -#endif +#endif /* CONFIG_SPI_SPIDEV */ }; /* SPI (0) */ @@ -716,9 +717,9 @@ static struct platform_device bf538_spi_master2 = { }, }; -#endif /* spi master and devices */ - #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) +static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0}; + static struct resource bfin_twi0_resource[] = { [0] = { .start = TWI0_REGBASE, @@ -737,9 +738,13 @@ static struct platform_device i2c_bfin_twi0_device = { .id = 0, .num_resources = ARRAY_SIZE(bfin_twi0_resource), .resource = bfin_twi0_resource, + .dev = { + .platform_data = &bfin_twi0_pins, + }, }; -#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */ +static const u16 bfin_twi1_pins[] = {P_TWI1_SCL, P_TWI1_SDA, 0}; + static struct resource bfin_twi1_resource[] = { [0] = { .start = TWI1_REGBASE, @@ -759,8 +764,8 @@ static struct platform_device i2c_bfin_twi1_device = { .num_resources = ARRAY_SIZE(bfin_twi1_resource), .resource = bfin_twi1_resource, }; -#endif -#endif +#endif /* CONFIG_BF542 */ +#endif /* CONFIG_I2C_BLACKFIN_TWI */ #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) #include <linux/gpio_keys.h> diff --git a/arch/blackfin/mach-bf538/include/mach/anomaly.h b/arch/blackfin/mach-bf538/include/mach/anomaly.h index b6ca99788710..318d922d11d4 100644 --- a/arch/blackfin/mach-bf538/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf538/include/mach/anomaly.h @@ -6,8 +6,7 @@ * DO NOT EDIT THIS FILE * * Copyright 2004-2011 Analog Devices Inc. - * Licensed under the ADI BSD license. - * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd + * Licensed under the Clear BSD license. */ /* This file should be up to date with: diff --git a/arch/blackfin/mach-bf538/include/mach/defBF538.h b/arch/blackfin/mach-bf538/include/mach/defBF538.h index d27f81d6c4b1..876a77028001 100644 --- a/arch/blackfin/mach-bf538/include/mach/defBF538.h +++ b/arch/blackfin/mach-bf538/include/mach/defBF538.h @@ -1,7 +1,7 @@ /* * Copyright 2008-2010 Analog Devices Inc. * - * Licensed under the ADI BSD license or the GPL-2 (or later) + * Licensed under the Clear BSD license or the GPL-2 (or later) */ #ifndef _DEF_BF538_H @@ -1746,80 +1746,4 @@ #define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */ #define BGSTAT 0x00000020 /* Bus granted */ - -/* ******************** TWO-WIRE INTERFACE (TWIx) MASKS ***********************/ -/* TWIx_CLKDIV Macros (Use: *pTWIx_CLKDIV = CLKLOW(x)|CLKHI(y); ) */ -#ifdef _MISRA_RULES -#define CLKLOW(x) ((x) & 0xFFu) /* Periods Clock Is Held Low */ -#define CLKHI(y) (((y)&0xFFu)<<0x8) /* Periods Before New Clock Low */ -#else -#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */ -#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */ -#endif /* _MISRA_RULES */ - -/* TWIx_PRESCALE Masks */ -#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */ -#define TWI_ENA 0x0080 /* TWI Enable */ -#define SCCB 0x0200 /* SCCB Compatibility Enable */ - -/* TWIx_SLAVE_CTRL Masks */ -#define SEN 0x0001 /* Slave Enable */ -#define SADD_LEN 0x0002 /* Slave Address Length */ -#define STDVAL 0x0004 /* Slave Transmit Data Valid */ -#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */ -#define GEN 0x0010 /* General Call Adrress Matching Enabled */ - -/* TWIx_SLAVE_STAT Masks */ -#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */ -#define GCALL 0x0002 /* General Call Indicator */ - -/* TWIx_MASTER_CTRL Masks */ -#define MEN 0x0001 /* Master Mode Enable */ -#define MADD_LEN 0x0002 /* Master Address Length */ -#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */ -#define FAST 0x0008 /* Use Fast Mode Timing Specs */ -#define STOP 0x0010 /* Issue Stop Condition */ -#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */ -#define DCNT 0x3FC0 /* Data Bytes To Transfer */ -#define SDAOVR 0x4000 /* Serial Data Override */ -#define SCLOVR 0x8000 /* Serial Clock Override */ - -/* TWIx_MASTER_STAT Masks */ -#define MPROG 0x0001 /* Master Transfer In Progress */ -#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */ -#define ANAK 0x0004 /* Address Not Acknowledged */ -#define DNAK 0x0008 /* Data Not Acknowledged */ -#define BUFRDERR 0x0010 /* Buffer Read Error */ -#define BUFWRERR 0x0020 /* Buffer Write Error */ -#define SDASEN 0x0040 /* Serial Data Sense */ -#define SCLSEN 0x0080 /* Serial Clock Sense */ -#define BUSBUSY 0x0100 /* Bus Busy Indicator */ - -/* TWIx_INT_SRC and TWIx_INT_ENABLE Masks */ -#define SINIT 0x0001 /* Slave Transfer Initiated */ -#define SCOMP 0x0002 /* Slave Transfer Complete */ -#define SERR 0x0004 /* Slave Transfer Error */ -#define SOVF 0x0008 /* Slave Overflow */ -#define MCOMP 0x0010 /* Master Transfer Complete */ -#define MERR 0x0020 /* Master Transfer Error */ -#define XMTSERV 0x0040 /* Transmit FIFO Service */ -#define RCVSERV 0x0080 /* Receive FIFO Service */ - -/* TWIx_FIFO_CTL Masks */ -#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */ -#define RCVFLUSH 0x0002 /* Receive Buffer Flush */ -#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */ -#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */ - -/* TWIx_FIFO_STAT Masks */ -#define XMTSTAT 0x0003 /* Transmit FIFO Status */ -#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */ -#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */ -#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */ - -#define RCVSTAT 0x000C /* Receive FIFO Status */ -#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */ -#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */ -#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */ - #endif diff --git a/arch/blackfin/mach-bf538/include/mach/defBF539.h b/arch/blackfin/mach-bf538/include/mach/defBF539.h index 8100bcd01a0d..199e871634b4 100644 --- a/arch/blackfin/mach-bf538/include/mach/defBF539.h +++ b/arch/blackfin/mach-bf538/include/mach/defBF539.h @@ -1,7 +1,7 @@ /* * Copyright 2008-2010 Analog Devices Inc. * - * Licensed under the ADI BSD license or the GPL-2 (or later) + * Licensed under the Clear BSD license or the GPL-2 (or later) */ #ifndef _DEF_BF539_H diff --git a/arch/blackfin/mach-bf548/boards/cm_bf548.c b/arch/blackfin/mach-bf548/boards/cm_bf548.c index 68af594db48e..e92543362f35 100644 --- a/arch/blackfin/mach-bf548/boards/cm_bf548.c +++ b/arch/blackfin/mach-bf548/boards/cm_bf548.c @@ -1007,6 +1007,8 @@ static struct platform_device bf54x_spi_master1 = { #endif /* spi master and devices */ #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) +static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0}; + static struct resource bfin_twi0_resource[] = { [0] = { .start = TWI0_REGBASE, @@ -1025,9 +1027,14 @@ static struct platform_device i2c_bfin_twi0_device = { .id = 0, .num_resources = ARRAY_SIZE(bfin_twi0_resource), .resource = bfin_twi0_resource, + .dev = { + .platform_data = &bfin_twi0_pins, + }, }; #if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */ +static const u16 bfin_twi1_pins[] = {P_TWI1_SCL, P_TWI1_SDA, 0}; + static struct resource bfin_twi1_resource[] = { [0] = { .start = TWI1_REGBASE, @@ -1046,6 +1053,9 @@ static struct platform_device i2c_bfin_twi1_device = { .id = 1, .num_resources = ARRAY_SIZE(bfin_twi1_resource), .resource = bfin_twi1_resource, + .dev = { + .platform_data = &bfin_twi1_pins, + }, }; #endif #endif diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c index 4cadaf8d0b56..3bd75bae750d 100644 --- a/arch/blackfin/mach-bf548/boards/ezkit.c +++ b/arch/blackfin/mach-bf548/boards/ezkit.c @@ -165,6 +165,7 @@ static struct bfin_rotary_platform_data bfin_rotary_data = { .rotary_button_key = KEY_ENTER, .debounce = 10, /* 0..17 */ .mode = ROT_QUAD_ENC | ROT_DEBE, + .pm_wakeup = 1, }; static struct resource bfin_rotary_resources[] = { @@ -1251,6 +1252,8 @@ static struct platform_device bfin_capture_device = { #endif #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) +static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0}; + static struct resource bfin_twi0_resource[] = { [0] = { .start = TWI0_REGBASE, @@ -1269,9 +1272,14 @@ static struct platform_device i2c_bfin_twi0_device = { .id = 0, .num_resources = ARRAY_SIZE(bfin_twi0_resource), .resource = bfin_twi0_resource, + .dev = { + .platform_data = &bfin_twi0_pins, + }, }; #if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */ +static const u16 bfin_twi1_pins[] = {P_TWI1_SCL, P_TWI1_SDA, 0}; + static struct resource bfin_twi1_resource[] = { [0] = { .start = TWI1_REGBASE, @@ -1290,6 +1298,9 @@ static struct platform_device i2c_bfin_twi1_device = { .id = 1, .num_resources = ARRAY_SIZE(bfin_twi1_resource), .resource = bfin_twi1_resource, + .dev = { + .platform_data = &bfin_twi1_pins, + }, }; #endif #endif diff --git a/arch/blackfin/mach-bf548/include/mach/anomaly.h b/arch/blackfin/mach-bf548/include/mach/anomaly.h index ac96ee83b00e..5b711d85b90b 100644 --- a/arch/blackfin/mach-bf548/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf548/include/mach/anomaly.h @@ -6,8 +6,7 @@ * DO NOT EDIT THIS FILE * * Copyright 2004-2011 Analog Devices Inc. - * Licensed under the ADI BSD license. - * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd + * Licensed under the Clear BSD license. */ /* This file should be up to date with: diff --git a/arch/blackfin/mach-bf548/include/mach/defBF542.h b/arch/blackfin/mach-bf548/include/mach/defBF542.h index 629bf216e2b5..51161575a163 100644 --- a/arch/blackfin/mach-bf548/include/mach/defBF542.h +++ b/arch/blackfin/mach-bf548/include/mach/defBF542.h @@ -1,7 +1,7 @@ /* * Copyright 2007-2010 Analog Devices Inc. * - * Licensed under the ADI BSD license or the GPL-2 (or later) + * Licensed under the Clear BSD license or the GPL-2 (or later) */ #ifndef _DEF_BF542_H diff --git a/arch/blackfin/mach-bf548/include/mach/defBF544.h b/arch/blackfin/mach-bf548/include/mach/defBF544.h index bcccab36629c..329b2c58228b 100644 --- a/arch/blackfin/mach-bf548/include/mach/defBF544.h +++ b/arch/blackfin/mach-bf548/include/mach/defBF544.h @@ -1,7 +1,7 @@ /* * Copyright 2007-2010 Analog Devices Inc. * - * Licensed under the ADI BSD license or the GPL-2 (or later) + * Licensed under the Clear BSD license or the GPL-2 (or later) */ #ifndef _DEF_BF544_H diff --git a/arch/blackfin/mach-bf548/include/mach/defBF547.h b/arch/blackfin/mach-bf548/include/mach/defBF547.h index 1fa41ec03f31..e18de212ba1a 100644 --- a/arch/blackfin/mach-bf548/include/mach/defBF547.h +++ b/arch/blackfin/mach-bf548/include/mach/defBF547.h @@ -1,7 +1,7 @@ /* * Copyright 2008-2010 Analog Devices Inc. * - * Licensed under the ADI BSD license or the GPL-2 (or later) + * Licensed under the Clear BSD license or the GPL-2 (or later) */ #ifndef _DEF_BF547_H diff --git a/arch/blackfin/mach-bf548/include/mach/defBF548.h b/arch/blackfin/mach-bf548/include/mach/defBF548.h index 3c7f1b69349e..27f29481e283 100644 --- a/arch/blackfin/mach-bf548/include/mach/defBF548.h +++ b/arch/blackfin/mach-bf548/include/mach/defBF548.h @@ -1,7 +1,7 @@ /* * Copyright 2007-2010 Analog Devices Inc. * - * Licensed under the ADI BSD license or the GPL-2 (or later) + * Licensed under the Clear BSD license or the GPL-2 (or later) */ #ifndef _DEF_BF548_H diff --git a/arch/blackfin/mach-bf548/include/mach/defBF549.h b/arch/blackfin/mach-bf548/include/mach/defBF549.h index 9a45cb6b30da..ac569fc12972 100644 --- a/arch/blackfin/mach-bf548/include/mach/defBF549.h +++ b/arch/blackfin/mach-bf548/include/mach/defBF549.h @@ -1,7 +1,7 @@ /* * Copyright 2007-2010 Analog Devices Inc. * - * Licensed under the ADI BSD license or the GPL-2 (or later) + * Licensed under the Clear BSD license or the GPL-2 (or later) */ #ifndef _DEF_BF549_H diff --git a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h index 0867c2bedb43..8f6e1925779d 100644 --- a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h +++ b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h @@ -1,7 +1,7 @@ /* * Copyright 2007-2010 Analog Devices Inc. * - * Licensed under the ADI BSD license or the GPL-2 (or later) + * Licensed under the Clear BSD license or the GPL-2 (or later) */ #ifndef _DEF_BF54X_H @@ -2062,115 +2062,6 @@ #define LOW_EVEN 0xff0000 /* Lower Limit for Even Bytes (Luma) */ #define HIGH_EVEN 0xff000000 /* Upper Limit for Even Bytes (Luma) */ -/* ************************************************ */ -/* The TWI bit masks fields are from the ADSP-BF538 */ -/* and they have not been verified as the final */ -/* ones for the Moab processors ... bz 1/19/2007 */ -/* ************************************************ */ - -/* Bit masks for TWIx_CONTROL */ - -#define PRESCALE 0x7f /* Prescale Value */ -#define TWI_ENA 0x80 /* TWI Enable */ -#define SCCB 0x200 /* Serial Camera Control Bus */ - -/* Bit maskes for TWIx_CLKDIV */ - -#define CLKLOW 0xff /* Clock Low */ -#define CLKHI 0xff00 /* Clock High */ - -/* Bit maskes for TWIx_SLAVE_CTL */ - -#define SEN 0x1 /* Slave Enable */ -#define STDVAL 0x4 /* Slave Transmit Data Valid */ -#define NAK 0x8 /* Not Acknowledge */ -#define GEN 0x10 /* General Call Enable */ - -/* Bit maskes for TWIx_SLAVE_ADDR */ - -#define SADDR 0x7f /* Slave Mode Address */ - -/* Bit maskes for TWIx_SLAVE_STAT */ - -#define SDIR 0x1 /* Slave Transfer Direction */ -#define GCALL 0x2 /* General Call */ - -/* Bit maskes for TWIx_MASTER_CTL */ - -#define MEN 0x1 /* Master Mode Enable */ -#define MDIR 0x4 /* Master Transfer Direction */ -#define FAST 0x8 /* Fast Mode */ -#define STOP 0x10 /* Issue Stop Condition */ -#define RSTART 0x20 /* Repeat Start */ -#define DCNT 0x3fc0 /* Data Transfer Count */ -#define SDAOVR 0x4000 /* Serial Data Override */ -#define SCLOVR 0x8000 /* Serial Clock Override */ - -/* Bit maskes for TWIx_MASTER_ADDR */ - -#define MADDR 0x7f /* Master Mode Address */ - -/* Bit maskes for TWIx_MASTER_STAT */ - -#define MPROG 0x1 /* Master Transfer in Progress */ -#define LOSTARB 0x2 /* Lost Arbitration */ -#define ANAK 0x4 /* Address Not Acknowledged */ -#define DNAK 0x8 /* Data Not Acknowledged */ -#define BUFRDERR 0x10 /* Buffer Read Error */ -#define BUFWRERR 0x20 /* Buffer Write Error */ -#define SDASEN 0x40 /* Serial Data Sense */ -#define SCLSEN 0x80 /* Serial Clock Sense */ -#define BUSBUSY 0x100 /* Bus Busy */ - -/* Bit maskes for TWIx_FIFO_CTL */ - -#define XMTFLUSH 0x1 /* Transmit Buffer Flush */ -#define RCVFLUSH 0x2 /* Receive Buffer Flush */ -#define XMTINTLEN 0x4 /* Transmit Buffer Interrupt Length */ -#define RCVINTLEN 0x8 /* Receive Buffer Interrupt Length */ - -/* Bit maskes for TWIx_FIFO_STAT */ - -#define XMTSTAT 0x3 /* Transmit FIFO Status */ -#define RCVSTAT 0xc /* Receive FIFO Status */ - -/* Bit maskes for TWIx_INT_MASK */ - -#define SINITM 0x1 /* Slave Transfer Initiated Interrupt Mask */ -#define SCOMPM 0x2 /* Slave Transfer Complete Interrupt Mask */ -#define SERRM 0x4 /* Slave Transfer Error Interrupt Mask */ -#define SOVFM 0x8 /* Slave Overflow Interrupt Mask */ -#define MCOMPM 0x10 /* Master Transfer Complete Interrupt Mask */ -#define MERRM 0x20 /* Master Transfer Error Interrupt Mask */ -#define XMTSERVM 0x40 /* Transmit FIFO Service Interrupt Mask */ -#define RCVSERVM 0x80 /* Receive FIFO Service Interrupt Mask */ - -/* Bit maskes for TWIx_INT_STAT */ - -#define SINIT 0x1 /* Slave Transfer Initiated */ -#define SCOMP 0x2 /* Slave Transfer Complete */ -#define SERR 0x4 /* Slave Transfer Error */ -#define SOVF 0x8 /* Slave Overflow */ -#define MCOMP 0x10 /* Master Transfer Complete */ -#define MERR 0x20 /* Master Transfer Error */ -#define XMTSERV 0x40 /* Transmit FIFO Service */ -#define RCVSERV 0x80 /* Receive FIFO Service */ - -/* Bit maskes for TWIx_XMT_DATA8 */ - -#define XMTDATA8 0xff /* Transmit FIFO 8-Bit Data */ - -/* Bit maskes for TWIx_XMT_DATA16 */ - -#define XMTDATA16 0xffff /* Transmit FIFO 16-Bit Data */ - -/* Bit maskes for TWIx_RCV_DATA8 */ - -#define RCVDATA8 0xff /* Receive FIFO 8-Bit Data */ - -/* Bit maskes for TWIx_RCV_DATA16 */ - -#define RCVDATA16 0xffff /* Receive FIFO 16-Bit Data */ /* ******************************************* */ /* MULTI BIT MACRO ENUMERATIONS */ diff --git a/arch/blackfin/mach-bf561/include/mach/anomaly.h b/arch/blackfin/mach-bf561/include/mach/anomaly.h index 836baeed303a..72476ff50335 100644 --- a/arch/blackfin/mach-bf561/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf561/include/mach/anomaly.h @@ -6,8 +6,7 @@ * DO NOT EDIT THIS FILE * * Copyright 2004-2011 Analog Devices Inc. - * Licensed under the ADI BSD license. - * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd + * Licensed under the Clear BSD license. */ /* This file should be up to date with: diff --git a/arch/blackfin/mach-bf561/include/mach/defBF561.h b/arch/blackfin/mach-bf561/include/mach/defBF561.h index 5f0ac5a77a37..9f21f768c63a 100644 --- a/arch/blackfin/mach-bf561/include/mach/defBF561.h +++ b/arch/blackfin/mach-bf561/include/mach/defBF561.h @@ -1,7 +1,7 @@ /* * Copyright 2005-2010 Analog Devices Inc. * - * Licensed under the ADI BSD license or the GPL-2 (or later) + * Licensed under the Clear BSD license or the GPL-2 (or later) */ #ifndef _DEF_BF561_H diff --git a/arch/blackfin/mach-bf609/Kconfig b/arch/blackfin/mach-bf609/Kconfig new file mode 100644 index 000000000000..2cb727243778 --- /dev/null +++ b/arch/blackfin/mach-bf609/Kconfig @@ -0,0 +1,56 @@ +config BF60x + def_bool y + depends on (BF609) + select IRQ_PREFLOW_FASTEOI + +if (BF60x) + +source "arch/blackfin/mach-bf609/boards/Kconfig" + +menu "BF609 Specific Configuration" + +comment "Pin Interrupt to Port Assignment" +menu "Assignment" + +config PINTx_REASSIGN + bool "Reprogram PINT Assignment" + default y + help + The interrupt assignment registers controls the pin-to-interrupt + assignment in a byte-wide manner. Each option allows you to select + a set of pins (High/Low Byte) of an specific Port being mapped + to one of the four PIN Interrupts IRQ_PINTx. + + You shouldn't change any of these unless you know exactly what you're doing. + Please consult the Blackfin BF60x Processor Hardware Reference Manual. + +config PINT0_ASSIGN + hex "PINT0_ASSIGN" + depends on PINTx_REASSIGN + default 0x00000101 +config PINT1_ASSIGN + hex "PINT1_ASSIGN" + depends on PINTx_REASSIGN + default 0x00000101 +config PINT2_ASSIGN + hex "PINT2_ASSIGN" + depends on PINTx_REASSIGN + default 0x00000101 +config PINT3_ASSIGN + hex "PINT3_ASSIGN" + depends on PINTx_REASSIGN + default 0x00000101 +config PINT4_ASSIGN + hex "PINT3_ASSIGN" + depends on PINTx_REASSIGN + default 0x00000101 +config PINT5_ASSIGN + hex "PINT3_ASSIGN" + depends on PINTx_REASSIGN + default 0x00000101 + +endmenu + +endmenu + +endif diff --git a/arch/blackfin/mach-bf609/Makefile b/arch/blackfin/mach-bf609/Makefile new file mode 100644 index 000000000000..2a27f8174543 --- /dev/null +++ b/arch/blackfin/mach-bf609/Makefile @@ -0,0 +1,6 @@ +# +# arch/blackfin/mach-bf609/Makefile +# + +obj-y := dma.o clock.o +obj-$(CONFIG_PM) += pm.o hibernate.o diff --git a/arch/blackfin/mach-bf609/boards/Kconfig b/arch/blackfin/mach-bf609/boards/Kconfig new file mode 100644 index 000000000000..30e8b6b0d2ed --- /dev/null +++ b/arch/blackfin/mach-bf609/boards/Kconfig @@ -0,0 +1,12 @@ +choice + prompt "System type" + default BFIN609_EZKIT + help + Select your board! + +config BFIN609_EZKIT + bool "BF609-EZKIT" + help + BFIN609-EZKIT board support. + +endchoice diff --git a/arch/blackfin/mach-bf609/boards/Makefile b/arch/blackfin/mach-bf609/boards/Makefile new file mode 100644 index 000000000000..11f98b0882ea --- /dev/null +++ b/arch/blackfin/mach-bf609/boards/Makefile @@ -0,0 +1,5 @@ +# +# arch/blackfin/mach-bf609/boards/Makefile +# + +obj-$(CONFIG_BFIN609_EZKIT) += ezkit.o diff --git a/arch/blackfin/mach-bf609/boards/ezkit.c b/arch/blackfin/mach-bf609/boards/ezkit.c new file mode 100644 index 000000000000..ac64f47217c1 --- /dev/null +++ b/arch/blackfin/mach-bf609/boards/ezkit.c @@ -0,0 +1,1340 @@ +/* + * Copyright 2004-2009 Analog Devices Inc. + * 2005 National ICT Australia (NICTA) + * Aidan Williams <[email protected]> + * + * Licensed under the GPL-2 or later. + */ + +#include <linux/device.h> +#include <linux/platform_device.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/mtd/physmap.h> +#include <linux/spi/spi.h> +#include <linux/spi/flash.h> +#include <linux/irq.h> +#include <linux/i2c.h> +#include <linux/interrupt.h> +#include <linux/usb/musb.h> +#include <asm/bfin6xx_spi.h> +#include <asm/dma.h> +#include <asm/gpio.h> +#include <asm/nand.h> +#include <asm/dpmc.h> +#include <asm/portmux.h> +#include <asm/bfin_sdh.h> +#include <linux/input.h> +#include <linux/spi/ad7877.h> + +/* + * Name the Board for the /proc/cpuinfo + */ +const char bfin_board_name[] = "ADI BF609-EZKIT"; + +/* + * Driver needs to know address, irq and flag pin. + */ + +#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE) +#include <linux/usb/isp1760.h> +static struct resource bfin_isp1760_resources[] = { + [0] = { + .start = 0x2C0C0000, + .end = 0x2C0C0000 + 0xfffff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_PG7, + .end = IRQ_PG7, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct isp1760_platform_data isp1760_priv = { + .is_isp1761 = 0, + .bus_width_16 = 1, + .port1_otg = 0, + .analog_oc = 0, + .dack_polarity_high = 0, + .dreq_polarity_high = 0, +}; + +static struct platform_device bfin_isp1760_device = { + .name = "isp1760", + .id = 0, + .dev = { + .platform_data = &isp1760_priv, + }, + .num_resources = ARRAY_SIZE(bfin_isp1760_resources), + .resource = bfin_isp1760_resources, +}; +#endif + +#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE) +#include <asm/bfin_rotary.h> + +static struct bfin_rotary_platform_data bfin_rotary_data = { + /*.rotary_up_key = KEY_UP,*/ + /*.rotary_down_key = KEY_DOWN,*/ + .rotary_rel_code = REL_WHEEL, + .rotary_button_key = KEY_ENTER, + .debounce = 10, /* 0..17 */ + .mode = ROT_QUAD_ENC | ROT_DEBE, +}; + +static struct resource bfin_rotary_resources[] = { + { + .start = IRQ_CNT, + .end = IRQ_CNT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device bfin_rotary_device = { + .name = "bfin-rotary", + .id = -1, + .num_resources = ARRAY_SIZE(bfin_rotary_resources), + .resource = bfin_rotary_resources, + .dev = { + .platform_data = &bfin_rotary_data, + }, +}; +#endif + +#if defined(CONFIG_STMMAC_ETH) || defined(CONFIG_STMMAC_ETH_MODULE) +#include <linux/stmmac.h> + +static unsigned short pins[] = P_RMII0; + +static struct stmmac_mdio_bus_data phy_private_data = { + .bus_id = 0, + .phy_mask = 1, +}; + +static struct plat_stmmacenet_data eth_private_data = { + .bus_id = 0, + .enh_desc = 1, + .phy_addr = 1, + .mdio_bus_data = &phy_private_data, +}; + +static struct platform_device bfin_eth_device = { + .name = "stmmaceth", + .id = 0, + .num_resources = 2, + .resource = (struct resource[]) { + { + .start = EMAC0_MACCFG, + .end = EMAC0_MACCFG + 0x1274, + .flags = IORESOURCE_MEM, + }, + { + .name = "macirq", + .start = IRQ_EMAC0_STAT, + .end = IRQ_EMAC0_STAT, + .flags = IORESOURCE_IRQ, + }, + }, + .dev = { + .power.can_wakeup = 1, + .platform_data = ð_private_data, + } +}; +#endif + +#if defined(CONFIG_INPUT_ADXL34X) || defined(CONFIG_INPUT_ADXL34X_MODULE) +#include <linux/input/adxl34x.h> +static const struct adxl34x_platform_data adxl34x_info = { + .x_axis_offset = 0, + .y_axis_offset = 0, + .z_axis_offset = 0, + .tap_threshold = 0x31, + .tap_duration = 0x10, + .tap_latency = 0x60, + .tap_window = 0xF0, + .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN, + .act_axis_control = 0xFF, + .activity_threshold = 5, + .inactivity_threshold = 3, + .inactivity_time = 4, + .free_fall_threshold = 0x7, + .free_fall_time = 0x20, + .data_rate = 0x8, + .data_range = ADXL_FULL_RES, + + .ev_type = EV_ABS, + .ev_code_x = ABS_X, /* EV_REL */ + .ev_code_y = ABS_Y, /* EV_REL */ + .ev_code_z = ABS_Z, /* EV_REL */ + + .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */ + +/* .ev_code_ff = KEY_F,*/ /* EV_KEY */ +/* .ev_code_act_inactivity = KEY_A,*/ /* EV_KEY */ + .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK, + .fifo_mode = ADXL_FIFO_STREAM, + .orientation_enable = ADXL_EN_ORIENTATION_3D, + .deadzone_angle = ADXL_DEADZONE_ANGLE_10p8, + .divisor_length = ADXL_LP_FILTER_DIVISOR_16, + /* EV_KEY {+Z, +Y, +X, -X, -Y, -Z} */ + .ev_codes_orient_3d = {BTN_Z, BTN_Y, BTN_X, BTN_A, BTN_B, BTN_C}, +}; +#endif + +#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) +static struct platform_device rtc_device = { + .name = "rtc-bfin", + .id = -1, +}; +#endif + +#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) +#ifdef CONFIG_SERIAL_BFIN_UART0 +static struct resource bfin_uart0_resources[] = { + { + .start = UART0_REVID, + .end = UART0_RXDIV+4, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_UART0_TX, + .end = IRQ_UART0_TX, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_UART0_RX, + .end = IRQ_UART0_RX, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_UART0_STAT, + .end = IRQ_UART0_STAT, + .flags = IORESOURCE_IRQ, + }, + { + .start = CH_UART0_TX, + .end = CH_UART0_TX, + .flags = IORESOURCE_DMA, + }, + { + .start = CH_UART0_RX, + .end = CH_UART0_RX, + .flags = IORESOURCE_DMA, + }, +#ifdef CONFIG_BFIN_UART0_CTSRTS + { /* CTS pin -- 0 means not supported */ + .start = GPIO_PD10, + .end = GPIO_PD10, + .flags = IORESOURCE_IO, + }, + { /* RTS pin -- 0 means not supported */ + .start = GPIO_PD9, + .end = GPIO_PD9, + .flags = IORESOURCE_IO, + }, +#endif +}; + +static unsigned short bfin_uart0_peripherals[] = { + P_UART0_TX, P_UART0_RX, +#ifdef CONFIG_BFIN_UART0_CTSRTS + P_UART0_RTS, P_UART0_CTS, +#endif + 0 +}; + +static struct platform_device bfin_uart0_device = { + .name = "bfin-uart", + .id = 0, + .num_resources = ARRAY_SIZE(bfin_uart0_resources), + .resource = bfin_uart0_resources, + .dev = { + .platform_data = &bfin_uart0_peripherals, /* Passed to driver */ + }, +}; +#endif +#ifdef CONFIG_SERIAL_BFIN_UART1 +static struct resource bfin_uart1_resources[] = { + { + .start = UART1_REVID, + .end = UART1_RXDIV+4, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_UART1_TX, + .end = IRQ_UART1_TX, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_UART1_RX, + .end = IRQ_UART1_RX, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_UART1_STAT, + .end = IRQ_UART1_STAT, + .flags = IORESOURCE_IRQ, + }, + { + .start = CH_UART1_TX, + .end = CH_UART1_TX, + .flags = IORESOURCE_DMA, + }, + { + .start = CH_UART1_RX, + .end = CH_UART1_RX, + .flags = IORESOURCE_DMA, + }, +#ifdef CONFIG_BFIN_UART1_CTSRTS + { /* CTS pin -- 0 means not supported */ + .start = GPIO_PG13, + .end = GPIO_PG13, + .flags = IORESOURCE_IO, + }, + { /* RTS pin -- 0 means not supported */ + .start = GPIO_PG10, + .end = GPIO_PG10, + .flags = IORESOURCE_IO, + }, +#endif +}; + +static unsigned short bfin_uart1_peripherals[] = { + P_UART1_TX, P_UART1_RX, +#ifdef CONFIG_BFIN_UART1_CTSRTS + P_UART1_RTS, P_UART1_CTS, +#endif + 0 +}; + +static struct platform_device bfin_uart1_device = { + .name = "bfin-uart", + .id = 1, + .num_resources = ARRAY_SIZE(bfin_uart1_resources), + .resource = bfin_uart1_resources, + .dev = { + .platform_data = &bfin_uart1_peripherals, /* Passed to driver */ + }, +}; +#endif +#endif + +#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) +#ifdef CONFIG_BFIN_SIR0 +static struct resource bfin_sir0_resources[] = { + { + .start = 0xFFC00400, + .end = 0xFFC004FF, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_UART0_TX, + .end = IRQ_UART0_TX+1, + .flags = IORESOURCE_IRQ, + }, + { + .start = CH_UART0_TX, + .end = CH_UART0_TX+1, + .flags = IORESOURCE_DMA, + }, +}; +static struct platform_device bfin_sir0_device = { + .name = "bfin_sir", + .id = 0, + .num_resources = ARRAY_SIZE(bfin_sir0_resources), + .resource = bfin_sir0_resources, +}; +#endif +#ifdef CONFIG_BFIN_SIR1 +static struct resource bfin_sir1_resources[] = { + { + .start = 0xFFC02000, + .end = 0xFFC020FF, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_UART1_TX, + .end = IRQ_UART1_TX+1, + .flags = IORESOURCE_IRQ, + }, + { + .start = CH_UART1_TX, + .end = CH_UART1_TX+1, + .flags = IORESOURCE_DMA, + }, +}; +static struct platform_device bfin_sir1_device = { + .name = "bfin_sir", + .id = 1, + .num_resources = ARRAY_SIZE(bfin_sir1_resources), + .resource = bfin_sir1_resources, +}; +#endif +#endif + +#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE) +static struct resource musb_resources[] = { + [0] = { + .start = 0xFFCC1000, + .end = 0xFFCC1398, + .flags = IORESOURCE_MEM, + }, + [1] = { /* general IRQ */ + .start = IRQ_USB_STAT, + .end = IRQ_USB_STAT, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + .name = "mc" + }, + [2] = { /* DMA IRQ */ + .start = IRQ_USB_DMA, + .end = IRQ_USB_DMA, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + .name = "dma" + }, +}; + +static struct musb_hdrc_config musb_config = { + .multipoint = 1, + .dyn_fifo = 0, + .dma = 1, + .num_eps = 16, + .dma_channels = 8, + .clkin = 48, /* musb CLKIN in MHZ */ +}; + +static struct musb_hdrc_platform_data musb_plat = { +#if defined(CONFIG_USB_MUSB_HDRC) && defined(CONFIG_USB_GADGET_MUSB_HDRC) + .mode = MUSB_OTG, +#elif defined(CONFIG_USB_MUSB_HDRC) + .mode = MUSB_HOST, +#elif defined(CONFIG_USB_GADGET_MUSB_HDRC) + .mode = MUSB_PERIPHERAL, +#endif + .config = &musb_config, +}; + +static u64 musb_dmamask = ~(u32)0; + +static struct platform_device musb_device = { + .name = "musb-blackfin", + .id = 0, + .dev = { + .dma_mask = &musb_dmamask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &musb_plat, + }, + .num_resources = ARRAY_SIZE(musb_resources), + .resource = musb_resources, +}; +#endif + +#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) +#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART +static struct resource bfin_sport0_uart_resources[] = { + { + .start = SPORT0_TCR1, + .end = SPORT0_MRCS3+4, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_SPORT0_RX, + .end = IRQ_SPORT0_RX+1, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_SPORT0_ERROR, + .end = IRQ_SPORT0_ERROR, + .flags = IORESOURCE_IRQ, + }, +}; + +static unsigned short bfin_sport0_peripherals[] = { + P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, + P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0 +}; + +static struct platform_device bfin_sport0_uart_device = { + .name = "bfin-sport-uart", + .id = 0, + .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources), + .resource = bfin_sport0_uart_resources, + .dev = { + .platform_data = &bfin_sport0_peripherals, /* Passed to driver */ + }, +}; +#endif +#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART +static struct resource bfin_sport1_uart_resources[] = { + { + .start = SPORT1_TCR1, + .end = SPORT1_MRCS3+4, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_SPORT1_RX, + .end = IRQ_SPORT1_RX+1, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_SPORT1_ERROR, + .end = IRQ_SPORT1_ERROR, + .flags = IORESOURCE_IRQ, + }, +}; + +static unsigned short bfin_sport1_peripherals[] = { + P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, + P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0 +}; + +static struct platform_device bfin_sport1_uart_device = { + .name = "bfin-sport-uart", + .id = 1, + .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources), + .resource = bfin_sport1_uart_resources, + .dev = { + .platform_data = &bfin_sport1_peripherals, /* Passed to driver */ + }, +}; +#endif +#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART +static struct resource bfin_sport2_uart_resources[] = { + { + .start = SPORT2_TCR1, + .end = SPORT2_MRCS3+4, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_SPORT2_RX, + .end = IRQ_SPORT2_RX+1, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_SPORT2_ERROR, + .end = IRQ_SPORT2_ERROR, + .flags = IORESOURCE_IRQ, + }, +}; + +static unsigned short bfin_sport2_peripherals[] = { + P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS, + P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0 +}; + +static struct platform_device bfin_sport2_uart_device = { + .name = "bfin-sport-uart", + .id = 2, + .num_resources = ARRAY_SIZE(bfin_sport2_uart_resources), + .resource = bfin_sport2_uart_resources, + .dev = { + .platform_data = &bfin_sport2_peripherals, /* Passed to driver */ + }, +}; +#endif +#endif + +#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE) + +static unsigned short bfin_can0_peripherals[] = { + P_CAN0_RX, P_CAN0_TX, 0 +}; + +static struct resource bfin_can0_resources[] = { + { + .start = 0xFFC00A00, + .end = 0xFFC00FFF, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_CAN0_RX, + .end = IRQ_CAN0_RX, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_CAN0_TX, + .end = IRQ_CAN0_TX, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_CAN0_STAT, + .end = IRQ_CAN0_STAT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device bfin_can0_device = { + .name = "bfin_can", + .id = 0, + .num_resources = ARRAY_SIZE(bfin_can0_resources), + .resource = bfin_can0_resources, + .dev = { + .platform_data = &bfin_can0_peripherals, /* Passed to driver */ + }, +}; + +#endif + +#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE) +static struct mtd_partition partition_info[] = { + { + .name = "bootloader(nand)", + .offset = 0, + .size = 0x80000, + }, { + .name = "linux kernel(nand)", + .offset = MTDPART_OFS_APPEND, + .size = 4 * 1024 * 1024, + }, + { + .name = "file system(nand)", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct bf5xx_nand_platform bfin_nand_platform = { + .data_width = NFC_NWIDTH_8, + .partitions = partition_info, + .nr_partitions = ARRAY_SIZE(partition_info), + .rd_dly = 3, + .wr_dly = 3, +}; + +static struct resource bfin_nand_resources[] = { + { + .start = 0xFFC03B00, + .end = 0xFFC03B4F, + .flags = IORESOURCE_MEM, + }, + { + .start = CH_NFC, + .end = CH_NFC, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device bfin_nand_device = { + .name = "bfin-nand", + .id = 0, + .num_resources = ARRAY_SIZE(bfin_nand_resources), + .resource = bfin_nand_resources, + .dev = { + .platform_data = &bfin_nand_platform, + }, +}; +#endif + +#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE) + +static struct bfin_sd_host bfin_sdh_data = { + .dma_chan = CH_RSI, + .irq_int0 = IRQ_RSI_INT0, + .pin_req = {P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0}, +}; + +static struct platform_device bfin_sdh_device = { + .name = "bfin-sdh", + .id = 0, + .dev = { + .platform_data = &bfin_sdh_data, + }, +}; +#endif + +#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) +static struct mtd_partition ezkit_partitions[] = { + { + .name = "bootloader(nor)", + .size = 0x80000, + .offset = 0, + }, { + .name = "linux kernel(nor)", + .size = 0x400000, + .offset = MTDPART_OFS_APPEND, + }, { + .name = "file system(nor)", + .size = 0x1000000 - 0x80000 - 0x400000, + .offset = MTDPART_OFS_APPEND, + }, +}; + +int bf609_nor_flash_init(struct platform_device *dev) +{ +#define CONFIG_SMC_GCTL_VAL 0x00000010 + const unsigned short pins[] = { + P_A3, P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12, + P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20, P_A21, + P_A22, P_A23, P_A24, P_A25, P_NORCK, 0, + }; + + peripheral_request_list(pins, "smc0"); + + bfin_write32(SMC_GCTL, CONFIG_SMC_GCTL_VAL); + bfin_write32(SMC_B0CTL, 0x01002011); + bfin_write32(SMC_B0TIM, 0x08170977); + bfin_write32(SMC_B0ETIM, 0x00092231); + return 0; +} + +static struct physmap_flash_data ezkit_flash_data = { + .width = 2, + .parts = ezkit_partitions, + .init = bf609_nor_flash_init, + .nr_parts = ARRAY_SIZE(ezkit_partitions), +}; + +static struct resource ezkit_flash_resource = { + .start = 0xb0000000, + .end = 0xb0ffffff, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device ezkit_flash_device = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &ezkit_flash_data, + }, + .num_resources = 1, + .resource = &ezkit_flash_resource, +}; +#endif + +#if defined(CONFIG_MTD_M25P80) \ + || defined(CONFIG_MTD_M25P80_MODULE) +/* SPI flash chip (w25q32) */ +static struct mtd_partition bfin_spi_flash_partitions[] = { + { + .name = "bootloader(spi)", + .size = 0x00080000, + .offset = 0, + .mask_flags = MTD_CAP_ROM + }, { + .name = "linux kernel(spi)", + .size = 0x00180000, + .offset = MTDPART_OFS_APPEND, + }, { + .name = "file system(spi)", + .size = MTDPART_SIZ_FULL, + .offset = MTDPART_OFS_APPEND, + } +}; + +static struct flash_platform_data bfin_spi_flash_data = { + .name = "m25p80", + .parts = bfin_spi_flash_partitions, + .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), + .type = "w25q32", +}; + +static struct bfin6xx_spi_chip spi_flash_chip_info = { + .enable_dma = true, /* use dma transfer with this chip*/ +}; +#endif + +#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) +static struct bfin6xx_spi_chip spidev_chip_info = { + .enable_dma = true, +}; +#endif + +#if defined(CONFIG_SND_BF6XX_I2S) || defined(CONFIG_SND_BF6XX_I2S_MODULE) +static struct platform_device bfin_i2s_pcm = { + .name = "bfin-i2s-pcm-audio", + .id = -1, +}; +#endif + +#if defined(CONFIG_SND_BF6XX_SOC_I2S) || \ + defined(CONFIG_SND_BF6XX_SOC_I2S_MODULE) +#include <asm/bfin_sport3.h> +static struct resource bfin_snd_resources[] = { + { + .start = SPORT0_CTL_A, + .end = SPORT0_CTL_A, + .flags = IORESOURCE_MEM, + }, + { + .start = SPORT0_CTL_B, + .end = SPORT0_CTL_B, + .flags = IORESOURCE_MEM, + }, + { + .start = CH_SPORT0_TX, + .end = CH_SPORT0_TX, + .flags = IORESOURCE_DMA, + }, + { + .start = CH_SPORT0_RX, + .end = CH_SPORT0_RX, + .flags = IORESOURCE_DMA, + }, + { + .start = IRQ_SPORT0_TX_STAT, + .end = IRQ_SPORT0_TX_STAT, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_SPORT0_RX_STAT, + .end = IRQ_SPORT0_RX_STAT, + .flags = IORESOURCE_IRQ, + }, +}; + +static const unsigned short bfin_snd_pin[] = { + P_SPORT0_ACLK, P_SPORT0_AFS, P_SPORT0_AD0, P_SPORT0_BCLK, + P_SPORT0_BFS, P_SPORT0_BD0, 0, +}; + +static struct bfin_snd_platform_data bfin_snd_data = { + .pin_req = bfin_snd_pin, +}; + +static struct platform_device bfin_i2s = { + .name = "bfin-i2s", + .num_resources = ARRAY_SIZE(bfin_snd_resources), + .resource = bfin_snd_resources, + .dev = { + .platform_data = &bfin_snd_data, + }, +}; +#endif + +#if defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61) || \ + defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61_MODULE) +static struct platform_device adau1761_device = { + .name = "bfin-eval-adau1x61", +}; +#endif + +#if defined(CONFIG_SND_SOC_ADAU1761) || defined(CONFIG_SND_SOC_ADAU1761_MODULE) +#include <sound/adau17x1.h> +static struct adau1761_platform_data adau1761_info = { + .lineout_mode = ADAU1761_OUTPUT_MODE_LINE, + .headphone_mode = ADAU1761_OUTPUT_MODE_HEADPHONE_CAPLESS, +}; +#endif + +#if defined(CONFIG_VIDEO_BLACKFIN_CAPTURE) \ + || defined(CONFIG_VIDEO_BLACKFIN_CAPTURE_MODULE) +#include <linux/videodev2.h> +#include <media/blackfin/bfin_capture.h> +#include <media/blackfin/ppi.h> + +static const unsigned short ppi_req[] = { + P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, + P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, + P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, + 0, +}; + +static const struct ppi_info ppi_info = { + .type = PPI_TYPE_EPPI3, + .dma_ch = CH_EPPI0_CH0, + .irq_err = IRQ_EPPI0_STAT, + .base = (void __iomem *)EPPI0_STAT, + .pin_req = ppi_req, +}; + +#if defined(CONFIG_VIDEO_VS6624) \ + || defined(CONFIG_VIDEO_VS6624_MODULE) +static struct v4l2_input vs6624_inputs[] = { + { + .index = 0, + .name = "Camera", + .type = V4L2_INPUT_TYPE_CAMERA, + .std = V4L2_STD_UNKNOWN, + }, +}; + +static struct bcap_route vs6624_routes[] = { + { + .input = 0, + .output = 0, + }, +}; + +static const unsigned vs6624_ce_pin = GPIO_PD1; + +static struct bfin_capture_config bfin_capture_data = { + .card_name = "BF609", + .inputs = vs6624_inputs, + .num_inputs = ARRAY_SIZE(vs6624_inputs), + .routes = vs6624_routes, + .i2c_adapter_id = 0, + .board_info = { + .type = "vs6624", + .addr = 0x10, + .platform_data = (void *)&vs6624_ce_pin, + }, + .ppi_info = &ppi_info, + .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FS1HI_FS2HI + | EPPI_CTL_POLC3 | EPPI_CTL_SYNC2 | EPPI_CTL_NON656), + .blank_clocks = 8, +}; +#endif + +static struct platform_device bfin_capture_device = { + .name = "bfin_capture", + .dev = { + .platform_data = &bfin_capture_data, + }, +}; +#endif + +#if defined(CONFIG_BFIN_CRC) +#define BFIN_CRC_NAME "bfin-crc" + +static struct resource bfin_crc0_resources[] = { + { + .start = REG_CRC0_CTL, + .end = REG_CRC0_REVID+4, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_CRC0_DCNTEXP, + .end = IRQ_CRC0_DCNTEXP, + .flags = IORESOURCE_IRQ, + }, + { + .start = CH_MEM_STREAM0_SRC_CRC0, + .end = CH_MEM_STREAM0_SRC_CRC0, + .flags = IORESOURCE_DMA, + }, + { + .start = CH_MEM_STREAM0_DEST_CRC0, + .end = CH_MEM_STREAM0_DEST_CRC0, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device bfin_crc0_device = { + .name = BFIN_CRC_NAME, + .id = 0, + .num_resources = ARRAY_SIZE(bfin_crc0_resources), + .resource = bfin_crc0_resources, +}; + +static struct resource bfin_crc1_resources[] = { + { + .start = REG_CRC1_CTL, + .end = REG_CRC1_REVID+4, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_CRC1_DCNTEXP, + .end = IRQ_CRC1_DCNTEXP, + .flags = IORESOURCE_IRQ, + }, + { + .start = CH_MEM_STREAM1_SRC_CRC1, + .end = CH_MEM_STREAM1_SRC_CRC1, + .flags = IORESOURCE_DMA, + }, + { + .start = CH_MEM_STREAM1_DEST_CRC1, + .end = CH_MEM_STREAM1_DEST_CRC1, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device bfin_crc1_device = { + .name = BFIN_CRC_NAME, + .id = 1, + .num_resources = ARRAY_SIZE(bfin_crc1_resources), + .resource = bfin_crc1_resources, +}; +#endif + +#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) +static const struct ad7877_platform_data bfin_ad7877_ts_info = { + .model = 7877, + .vref_delay_usecs = 50, /* internal, no capacitor */ + .x_plate_ohms = 419, + .y_plate_ohms = 486, + .pressure_max = 1000, + .pressure_min = 0, + .stopacq_polarity = 1, + .first_conversion_delay = 3, + .acquisition_time = 1, + .averaging = 1, + .pen_down_acc_interval = 1, +}; +#endif + +static struct spi_board_info bfin_spi_board_info[] __initdata = { +#if defined(CONFIG_MTD_M25P80) \ + || defined(CONFIG_MTD_M25P80_MODULE) + { + /* the modalias must be the same as spi device driver name */ + .modalias = "m25p80", /* Name of spi_driver for this device */ + .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, /* Framework bus number */ + .chip_select = 1, /* SPI_SSEL1*/ + .platform_data = &bfin_spi_flash_data, + .controller_data = &spi_flash_chip_info, + .mode = SPI_MODE_3, + }, +#endif +#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) + { + .modalias = "ad7877", + .platform_data = &bfin_ad7877_ts_info, + .irq = IRQ_PB4, /* old boards (<=Rev 1.3) use IRQ_PJ11 */ + .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 2, + }, +#endif +#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) + { + .modalias = "spidev", + .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 1, + .controller_data = &spidev_chip_info, + }, +#endif +#if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE) + { + .modalias = "adxl34x", + .platform_data = &adxl34x_info, + .irq = IRQ_PC5, + .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 1, + .chip_select = 2, + .mode = SPI_MODE_3, + }, +#endif +}; +#if defined(CONFIG_SPI_BFIN6XX) || defined(CONFIG_SPI_BFIN6XX_MODULE) +/* SPI (0) */ +static struct resource bfin_spi0_resource[] = { + { + .start = SPI0_REGBASE, + .end = SPI0_REGBASE + 0xFF, + .flags = IORESOURCE_MEM, + }, + { + .start = CH_SPI0_TX, + .end = CH_SPI0_TX, + .flags = IORESOURCE_DMA, + }, + { + .start = CH_SPI0_RX, + .end = CH_SPI0_RX, + .flags = IORESOURCE_DMA, + }, +}; + +/* SPI (1) */ +static struct resource bfin_spi1_resource[] = { + { + .start = SPI1_REGBASE, + .end = SPI1_REGBASE + 0xFF, + .flags = IORESOURCE_MEM, + }, + { + .start = CH_SPI1_TX, + .end = CH_SPI1_TX, + .flags = IORESOURCE_DMA, + }, + { + .start = CH_SPI1_RX, + .end = CH_SPI1_RX, + .flags = IORESOURCE_DMA, + }, + +}; + +/* SPI controller data */ +static struct bfin6xx_spi_master bf60x_spi_master_info0 = { + .num_chipselect = 4, + .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, +}; + +static struct platform_device bf60x_spi_master0 = { + .name = "bfin-spi", + .id = 0, /* Bus number */ + .num_resources = ARRAY_SIZE(bfin_spi0_resource), + .resource = bfin_spi0_resource, + .dev = { + .platform_data = &bf60x_spi_master_info0, /* Passed to driver */ + }, +}; + +static struct bfin6xx_spi_master bf60x_spi_master_info1 = { + .num_chipselect = 4, + .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0}, +}; + +static struct platform_device bf60x_spi_master1 = { + .name = "bfin-spi", + .id = 1, /* Bus number */ + .num_resources = ARRAY_SIZE(bfin_spi1_resource), + .resource = bfin_spi1_resource, + .dev = { + .platform_data = &bf60x_spi_master_info1, /* Passed to driver */ + }, +}; +#endif /* spi master and devices */ + +#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) +static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0}; + +static struct resource bfin_twi0_resource[] = { + [0] = { + .start = TWI0_CLKDIV, + .end = TWI0_CLKDIV + 0xFF, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_TWI0, + .end = IRQ_TWI0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device i2c_bfin_twi0_device = { + .name = "i2c-bfin-twi", + .id = 0, + .num_resources = ARRAY_SIZE(bfin_twi0_resource), + .resource = bfin_twi0_resource, + .dev = { + .platform_data = &bfin_twi0_pins, + }, +}; + +static const u16 bfin_twi1_pins[] = {P_TWI1_SCL, P_TWI1_SDA, 0}; + +static struct resource bfin_twi1_resource[] = { + [0] = { + .start = TWI1_CLKDIV, + .end = TWI1_CLKDIV + 0xFF, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_TWI1, + .end = IRQ_TWI1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device i2c_bfin_twi1_device = { + .name = "i2c-bfin-twi", + .id = 1, + .num_resources = ARRAY_SIZE(bfin_twi1_resource), + .resource = bfin_twi1_resource, + .dev = { + .platform_data = &bfin_twi1_pins, + }, +}; +#endif + +static struct i2c_board_info __initdata bfin_i2c_board_info0[] = { +#if defined(CONFIG_INPUT_ADXL34X_I2C) || defined(CONFIG_INPUT_ADXL34X_I2C_MODULE) + { + I2C_BOARD_INFO("adxl34x", 0x53), + .irq = IRQ_PC5, + .platform_data = (void *)&adxl34x_info, + }, +#endif +#if defined(CONFIG_SND_SOC_ADAU1761) || defined(CONFIG_SND_SOC_ADAU1761_MODULE) + { + I2C_BOARD_INFO("adau1761", 0x38), + .platform_data = (void *)&adau1761_info + }, +#endif +}; + +static struct i2c_board_info __initdata bfin_i2c_board_info1[] = { +}; + +static const unsigned int cclk_vlev_datasheet[] = +{ +/* + * Internal VLEV BF54XSBBC1533 + ****temporarily using these values until data sheet is updated + */ + VRPAIR(VLEV_085, 150000000), + VRPAIR(VLEV_090, 250000000), + VRPAIR(VLEV_110, 276000000), + VRPAIR(VLEV_115, 301000000), + VRPAIR(VLEV_120, 525000000), + VRPAIR(VLEV_125, 550000000), + VRPAIR(VLEV_130, 600000000), +}; + +static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { + .tuple_tab = cclk_vlev_datasheet, + .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), + .vr_settling_time = 25 /* us */, +}; + +static struct platform_device bfin_dpmc = { + .name = "bfin dpmc", + .dev = { + .platform_data = &bfin_dmpc_vreg_data, + }, +}; + +static struct platform_device *ezkit_devices[] __initdata = { + + &bfin_dpmc, + +#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) + &rtc_device, +#endif + +#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) +#ifdef CONFIG_SERIAL_BFIN_UART0 + &bfin_uart0_device, +#endif +#ifdef CONFIG_SERIAL_BFIN_UART1 + &bfin_uart1_device, +#endif +#endif + +#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) +#ifdef CONFIG_BFIN_SIR0 + &bfin_sir0_device, +#endif +#ifdef CONFIG_BFIN_SIR1 + &bfin_sir1_device, +#endif +#endif + +#if defined(CONFIG_STMMAC_ETH) || defined(CONFIG_STMMAC_ETH_MODULE) + &bfin_eth_device, +#endif + +#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE) + &musb_device, +#endif + +#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE) + &bfin_isp1760_device, +#endif + +#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) +#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART + &bfin_sport0_uart_device, +#endif +#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART + &bfin_sport1_uart_device, +#endif +#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART + &bfin_sport2_uart_device, +#endif +#endif + +#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE) + &bfin_can0_device, +#endif + +#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE) + &bfin_nand_device, +#endif + +#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE) + &bfin_sdh_device, +#endif + +#if defined(CONFIG_SPI_BFIN6XX) || defined(CONFIG_SPI_BFIN6XX_MODULE) + &bf60x_spi_master0, + &bf60x_spi_master1, +#endif + +#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE) + &bfin_rotary_device, +#endif + +#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) + &i2c_bfin_twi0_device, +#if !defined(CONFIG_BF542) + &i2c_bfin_twi1_device, +#endif +#endif + +#if defined(CONFIG_BFIN_CRC) + &bfin_crc0_device, + &bfin_crc1_device, +#endif + +#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) + &bfin_device_gpiokeys, +#endif + +#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) + &ezkit_flash_device, +#endif +#if defined(CONFIG_SND_BF6XX_I2S) || defined(CONFIG_SND_BF6XX_I2S_MODULE) + &bfin_i2s_pcm, +#endif +#if defined(CONFIG_SND_BF6XX_SOC_I2S) || \ + defined(CONFIG_SND_BF6XX_SOC_I2S_MODULE) + &bfin_i2s, +#endif +#if defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61) || \ + defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61_MODULE) + &adau1761_device, +#endif +#if defined(CONFIG_VIDEO_BLACKFIN_CAPTURE) \ + || defined(CONFIG_VIDEO_BLACKFIN_CAPTURE_MODULE) + &bfin_capture_device, +#endif +}; + +static int __init ezkit_init(void) +{ + printk(KERN_INFO "%s(): registering device resources\n", __func__); + + i2c_register_board_info(0, bfin_i2c_board_info0, + ARRAY_SIZE(bfin_i2c_board_info0)); + i2c_register_board_info(1, bfin_i2c_board_info1, + ARRAY_SIZE(bfin_i2c_board_info1)); + +#if defined(CONFIG_STMMAC_ETH) || defined(CONFIG_STMMAC_ETH_MODULE) + if (!peripheral_request_list(pins, "emac0")) + printk(KERN_ERR "%s(): request emac pins failed\n", __func__); +#endif + + platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices)); + + spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); + + return 0; +} + +arch_initcall(ezkit_init); + +static struct platform_device *ezkit_early_devices[] __initdata = { +#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) +#ifdef CONFIG_SERIAL_BFIN_UART0 + &bfin_uart0_device, +#endif +#ifdef CONFIG_SERIAL_BFIN_UART1 + &bfin_uart1_device, +#endif +#endif + +#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE) +#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART + &bfin_sport0_uart_device, +#endif +#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART + &bfin_sport1_uart_device, +#endif +#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART + &bfin_sport2_uart_device, +#endif +#endif +}; + +void __init native_machine_early_platform_add_devices(void) +{ + printk(KERN_INFO "register early platform devices\n"); + early_platform_add_devices(ezkit_early_devices, + ARRAY_SIZE(ezkit_early_devices)); +} diff --git a/arch/blackfin/mach-bf609/clock.c b/arch/blackfin/mach-bf609/clock.c new file mode 100644 index 000000000000..7f8f529693ae --- /dev/null +++ b/arch/blackfin/mach-bf609/clock.c @@ -0,0 +1,390 @@ +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/list.h> +#include <linux/errno.h> +#include <linux/err.h> +#include <linux/string.h> +#include <linux/clk.h> +#include <linux/mutex.h> +#include <linux/spinlock.h> +#include <linux/debugfs.h> +#include <linux/device.h> +#include <linux/init.h> +#include <linux/timer.h> +#include <linux/io.h> +#include <linux/seq_file.h> +#include <linux/clkdev.h> + +#include <asm/clocks.h> + +#define CGU0_CTL_DF (1 << 0) + +#define CGU0_CTL_MSEL_SHIFT 8 +#define CGU0_CTL_MSEL_MASK (0x7f << 8) + +#define CGU0_STAT_PLLEN (1 << 0) +#define CGU0_STAT_PLLBP (1 << 1) +#define CGU0_STAT_PLLLK (1 << 2) +#define CGU0_STAT_CLKSALGN (1 << 3) +#define CGU0_STAT_CCBF0 (1 << 4) +#define CGU0_STAT_CCBF1 (1 << 5) +#define CGU0_STAT_SCBF0 (1 << 6) +#define CGU0_STAT_SCBF1 (1 << 7) +#define CGU0_STAT_DCBF (1 << 8) +#define CGU0_STAT_OCBF (1 << 9) +#define CGU0_STAT_ADDRERR (1 << 16) +#define CGU0_STAT_LWERR (1 << 17) +#define CGU0_STAT_DIVERR (1 << 18) +#define CGU0_STAT_WDFMSERR (1 << 19) +#define CGU0_STAT_WDIVERR (1 << 20) +#define CGU0_STAT_PLOCKERR (1 << 21) + +#define CGU0_DIV_CSEL_SHIFT 0 +#define CGU0_DIV_CSEL_MASK 0x0000001F +#define CGU0_DIV_S0SEL_SHIFT 5 +#define CGU0_DIV_S0SEL_MASK (0x3 << CGU0_DIV_S0SEL_SHIFT) +#define CGU0_DIV_SYSSEL_SHIFT 8 +#define CGU0_DIV_SYSSEL_MASK (0x1f << CGU0_DIV_SYSSEL_SHIFT) +#define CGU0_DIV_S1SEL_SHIFT 13 +#define CGU0_DIV_S1SEL_MASK (0x3 << CGU0_DIV_S1SEL_SHIFT) +#define CGU0_DIV_DSEL_SHIFT 16 +#define CGU0_DIV_DSEL_MASK (0x1f << CGU0_DIV_DSEL_SHIFT) +#define CGU0_DIV_OSEL_SHIFT 22 +#define CGU0_DIV_OSEL_MASK (0x7f << CGU0_DIV_OSEL_SHIFT) + +#define CLK(_clk, _devname, _conname) \ + { \ + .clk = &_clk, \ + .dev_id = _devname, \ + .con_id = _conname, \ + } + +#define NEEDS_INITIALIZATION 0x11 + +static LIST_HEAD(clk_list); + +static void clk_reg_write_mask(u32 reg, uint32_t val, uint32_t mask) +{ + u32 val2; + + val2 = bfin_read32(reg); + val2 &= ~mask; + val2 |= val; + bfin_write32(reg, val2); +} + +static void clk_reg_set_bits(u32 reg, uint32_t mask) +{ + u32 val; + + val = bfin_read32(reg); + val |= mask; + bfin_write32(reg, val); +} + +static void clk_reg_clear_bits(u32 reg, uint32_t mask) +{ + u32 val; + + val = bfin_read32(reg); + val &= ~mask; + bfin_write32(reg, val); +} + +int wait_for_pll_align(void) +{ + int i = 10000; + while (i-- && (bfin_read32(CGU0_STAT) & CGU0_STAT_CLKSALGN)); + + if (bfin_read32(CGU0_STAT) & CGU0_STAT_CLKSALGN) { + printk(KERN_DEBUG "fail to align clk\n"); + return -1; + } + return 0; +} + +int clk_enable(struct clk *clk) +{ + int ret = -EIO; + if (clk->ops && clk->ops->enable) + ret = clk->ops->enable(clk); + return ret; +} +EXPORT_SYMBOL(clk_enable); + +void clk_disable(struct clk *clk) +{ + if (clk->ops && clk->ops->disable) + clk->ops->disable(clk); +} +EXPORT_SYMBOL(clk_disable); + +unsigned long clk_get_rate(struct clk *clk) +{ + unsigned long ret = 0; + if (clk->ops && clk->ops->get_rate) + ret = clk->ops->get_rate(clk); + return ret; +} +EXPORT_SYMBOL(clk_get_rate); + +long clk_round_rate(struct clk *clk, unsigned long rate) +{ + long ret = -EIO; + if (clk->ops && clk->ops->round_rate) + ret = clk->ops->round_rate(clk, rate); + return ret; +} +EXPORT_SYMBOL(clk_round_rate); + +int clk_set_rate(struct clk *clk, unsigned long rate) +{ + int ret = -EIO; + if (clk->ops && clk->ops->set_rate) + ret = clk->ops->set_rate(clk, rate); + return ret; +} +EXPORT_SYMBOL(clk_set_rate); + +unsigned long vco_get_rate(struct clk *clk) +{ + return clk->rate; +} + +unsigned long pll_get_rate(struct clk *clk) +{ + u32 df; + u32 msel; + u32 ctl = bfin_read32(CGU0_CTL); + u32 stat = bfin_read32(CGU0_STAT); + if (stat & CGU0_STAT_PLLBP) + return 0; + msel = (ctl & CGU0_CTL_MSEL_MASK) >> CGU0_CTL_MSEL_SHIFT; + df = (ctl & CGU0_CTL_DF); + clk->parent->rate = clk_get_rate(clk->parent); + return clk->parent->rate / (df + 1) * msel * 2; +} + +unsigned long pll_round_rate(struct clk *clk, unsigned long rate) +{ + u32 div; + div = rate / clk->parent->rate; + return clk->parent->rate * div; +} + +int pll_set_rate(struct clk *clk, unsigned long rate) +{ + u32 msel; + u32 stat = bfin_read32(CGU0_STAT); + if (!(stat & CGU0_STAT_PLLEN)) + return -EBUSY; + if (!(stat & CGU0_STAT_PLLLK)) + return -EBUSY; + if (wait_for_pll_align()) + return -EBUSY; + msel = rate / clk->parent->rate / 2; + clk_reg_write_mask(CGU0_CTL, msel << CGU0_CTL_MSEL_SHIFT, + CGU0_CTL_MSEL_MASK); + clk->rate = rate; + return 0; +} + +unsigned long cclk_get_rate(struct clk *clk) +{ + if (clk->parent) + return clk->parent->rate; + else + return 0; +} + +unsigned long sys_clk_get_rate(struct clk *clk) +{ + unsigned long drate; + u32 msel; + u32 df; + u32 ctl = bfin_read32(CGU0_CTL); + u32 div = bfin_read32(CGU0_DIV); + div = (div & clk->mask) >> clk->shift; + msel = (ctl & CGU0_CTL_MSEL_MASK) >> CGU0_CTL_MSEL_SHIFT; + df = (ctl & CGU0_CTL_DF); + + if (!strcmp(clk->parent->name, "SYS_CLKIN")) { + drate = clk->parent->rate / (df + 1); + drate *= msel; + drate /= div; + return drate; + } else { + clk->parent->rate = clk_get_rate(clk->parent); + return clk->parent->rate / div; + } +} + +unsigned long sys_clk_round_rate(struct clk *clk, unsigned long rate) +{ + unsigned long max_rate; + unsigned long drate; + int i; + u32 msel; + u32 df; + u32 ctl = bfin_read32(CGU0_CTL); + + msel = (ctl & CGU0_CTL_MSEL_MASK) >> CGU0_CTL_MSEL_SHIFT; + df = (ctl & CGU0_CTL_DF); + max_rate = clk->parent->rate / (df + 1) * msel; + + if (rate > max_rate) + return 0; + + for (i = 1; i < clk->mask; i++) { + drate = max_rate / i; + if (rate >= drate) + return drate; + } + return 0; +} + +int sys_clk_set_rate(struct clk *clk, unsigned long rate) +{ + u32 div = bfin_read32(CGU0_DIV); + div = (div & clk->mask) >> clk->shift; + + rate = clk_round_rate(clk, rate); + + if (!rate) + return -EINVAL; + + div = (clk_get_rate(clk) * div) / rate; + + if (wait_for_pll_align()) + return -EBUSY; + clk_reg_write_mask(CGU0_DIV, div << clk->shift, + clk->mask); + clk->rate = rate; + return 0; +} + +static struct clk_ops vco_ops = { + .get_rate = vco_get_rate, +}; + +static struct clk_ops pll_ops = { + .get_rate = pll_get_rate, + .set_rate = pll_set_rate, +}; + +static struct clk_ops cclk_ops = { + .get_rate = cclk_get_rate, +}; + +static struct clk_ops sys_clk_ops = { + .get_rate = sys_clk_get_rate, + .set_rate = sys_clk_set_rate, + .round_rate = sys_clk_round_rate, +}; + +static struct clk sys_clkin = { + .name = "SYS_CLKIN", + .rate = CONFIG_CLKIN_HZ, + .ops = &vco_ops, +}; + +static struct clk pll_clk = { + .name = "PLLCLK", + .rate = 500000000, + .parent = &sys_clkin, + .ops = &pll_ops, + .flags = NEEDS_INITIALIZATION, +}; + +static struct clk cclk = { + .name = "CCLK", + .rate = 500000000, + .mask = CGU0_DIV_CSEL_MASK, + .shift = CGU0_DIV_CSEL_SHIFT, + .parent = &sys_clkin, + .ops = &sys_clk_ops, + .flags = NEEDS_INITIALIZATION, +}; + +static struct clk cclk0 = { + .name = "CCLK0", + .parent = &cclk, + .ops = &cclk_ops, +}; + +static struct clk cclk1 = { + .name = "CCLK1", + .parent = &cclk, + .ops = &cclk_ops, +}; + +static struct clk sysclk = { + .name = "SYSCLK", + .rate = 500000000, + .mask = CGU0_DIV_SYSSEL_MASK, + .shift = CGU0_DIV_SYSSEL_SHIFT, + .parent = &sys_clkin, + .ops = &sys_clk_ops, + .flags = NEEDS_INITIALIZATION, +}; + +static struct clk sclk0 = { + .name = "SCLK0", + .rate = 500000000, + .mask = CGU0_DIV_S0SEL_MASK, + .shift = CGU0_DIV_S0SEL_SHIFT, + .parent = &sysclk, + .ops = &sys_clk_ops, +}; + +static struct clk sclk1 = { + .name = "SCLK1", + .rate = 500000000, + .mask = CGU0_DIV_S1SEL_MASK, + .shift = CGU0_DIV_S1SEL_SHIFT, + .parent = &sysclk, + .ops = &sys_clk_ops, +}; + +static struct clk dclk = { + .name = "DCLK", + .rate = 500000000, + .mask = CGU0_DIV_DSEL_MASK, + .shift = CGU0_DIV_DSEL_SHIFT, + .parent = &sys_clkin, + .ops = &sys_clk_ops, +}; + +static struct clk oclk = { + .name = "OCLK", + .rate = 500000000, + .mask = CGU0_DIV_OSEL_MASK, + .shift = CGU0_DIV_OSEL_SHIFT, + .parent = &pll_clk, +}; + +static struct clk_lookup bf609_clks[] = { + CLK(sys_clkin, NULL, "SYS_CLKIN"), + CLK(pll_clk, NULL, "PLLCLK"), + CLK(cclk, NULL, "CCLK"), + CLK(cclk0, NULL, "CCLK0"), + CLK(cclk1, NULL, "CCLK1"), + CLK(sysclk, NULL, "SYSCLK"), + CLK(sclk0, NULL, "SCLK0"), + CLK(sclk1, NULL, "SCLK1"), + CLK(dclk, NULL, "DCLK"), + CLK(oclk, NULL, "OCLK"), +}; + +int __init clk_init(void) +{ + int i; + struct clk *clkp; + for (i = 0; i < ARRAY_SIZE(bf609_clks); i++) { + clkp = bf609_clks[i].clk; + if (clkp->flags & NEEDS_INITIALIZATION) + clk_get_rate(clkp); + } + clkdev_add_table(bf609_clks, ARRAY_SIZE(bf609_clks)); + return 0; +} diff --git a/arch/blackfin/mach-bf609/dma.c b/arch/blackfin/mach-bf609/dma.c new file mode 100644 index 000000000000..1da4b38ac22c --- /dev/null +++ b/arch/blackfin/mach-bf609/dma.c @@ -0,0 +1,202 @@ +/* + * the simple DMA Implementation for Blackfin + * + * Copyright 2007-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include <linux/module.h> + +#include <asm/blackfin.h> +#include <asm/dma.h> + +struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = { + (struct dma_register *) DMA0_NEXT_DESC_PTR, + (struct dma_register *) DMA1_NEXT_DESC_PTR, + (struct dma_register *) DMA2_NEXT_DESC_PTR, + (struct dma_register *) DMA3_NEXT_DESC_PTR, + (struct dma_register *) DMA4_NEXT_DESC_PTR, + (struct dma_register *) DMA5_NEXT_DESC_PTR, + (struct dma_register *) DMA6_NEXT_DESC_PTR, + (struct dma_register *) DMA7_NEXT_DESC_PTR, + (struct dma_register *) DMA8_NEXT_DESC_PTR, + (struct dma_register *) DMA9_NEXT_DESC_PTR, + (struct dma_register *) DMA10_NEXT_DESC_PTR, + (struct dma_register *) DMA11_NEXT_DESC_PTR, + (struct dma_register *) DMA12_NEXT_DESC_PTR, + (struct dma_register *) DMA13_NEXT_DESC_PTR, + (struct dma_register *) DMA14_NEXT_DESC_PTR, + (struct dma_register *) DMA15_NEXT_DESC_PTR, + (struct dma_register *) DMA16_NEXT_DESC_PTR, + (struct dma_register *) DMA17_NEXT_DESC_PTR, + (struct dma_register *) DMA18_NEXT_DESC_PTR, + (struct dma_register *) DMA19_NEXT_DESC_PTR, + (struct dma_register *) DMA20_NEXT_DESC_PTR, + (struct dma_register *) MDMA0_SRC_CRC0_NEXT_DESC_PTR, + (struct dma_register *) MDMA0_DEST_CRC0_NEXT_DESC_PTR, + (struct dma_register *) MDMA1_SRC_CRC1_NEXT_DESC_PTR, + (struct dma_register *) MDMA1_DEST_CRC1_NEXT_DESC_PTR, + (struct dma_register *) MDMA2_SRC_NEXT_DESC_PTR, + (struct dma_register *) MDMA2_DEST_NEXT_DESC_PTR, + (struct dma_register *) MDMA3_SRC_NEXT_DESC_PTR, + (struct dma_register *) MDMA3_DEST_NEXT_DESC_PTR, + (struct dma_register *) DMA29_NEXT_DESC_PTR, + (struct dma_register *) DMA30_NEXT_DESC_PTR, + (struct dma_register *) DMA31_NEXT_DESC_PTR, + (struct dma_register *) DMA32_NEXT_DESC_PTR, + (struct dma_register *) DMA33_NEXT_DESC_PTR, + (struct dma_register *) DMA34_NEXT_DESC_PTR, + (struct dma_register *) DMA35_NEXT_DESC_PTR, + (struct dma_register *) DMA36_NEXT_DESC_PTR, + (struct dma_register *) DMA37_NEXT_DESC_PTR, + (struct dma_register *) DMA38_NEXT_DESC_PTR, + (struct dma_register *) DMA39_NEXT_DESC_PTR, + (struct dma_register *) DMA40_NEXT_DESC_PTR, + (struct dma_register *) DMA41_NEXT_DESC_PTR, + (struct dma_register *) DMA42_NEXT_DESC_PTR, + (struct dma_register *) DMA43_NEXT_DESC_PTR, + (struct dma_register *) DMA44_NEXT_DESC_PTR, + (struct dma_register *) DMA45_NEXT_DESC_PTR, + (struct dma_register *) DMA46_NEXT_DESC_PTR, +}; +EXPORT_SYMBOL(dma_io_base_addr); + +int channel2irq(unsigned int channel) +{ + int ret_irq = -1; + + switch (channel) { + case CH_SPORT0_RX: + ret_irq = IRQ_SPORT0_RX; + break; + case CH_SPORT0_TX: + ret_irq = IRQ_SPORT0_TX; + break; + case CH_SPORT1_RX: + ret_irq = IRQ_SPORT1_RX; + break; + case CH_SPORT1_TX: + ret_irq = IRQ_SPORT1_TX; + break; + case CH_SPORT2_RX: + ret_irq = IRQ_SPORT2_RX; + break; + case CH_SPORT2_TX: + ret_irq = IRQ_SPORT2_TX; + break; + case CH_SPI0_TX: + ret_irq = IRQ_SPI0_TX; + break; + case CH_SPI0_RX: + ret_irq = IRQ_SPI0_RX; + break; + case CH_SPI1_TX: + ret_irq = IRQ_SPI1_TX; + break; + case CH_SPI1_RX: + ret_irq = IRQ_SPI1_RX; + break; + case CH_RSI: + ret_irq = IRQ_RSI; + break; + case CH_SDU: + ret_irq = IRQ_SDU; + break; + case CH_LP0: + ret_irq = IRQ_LP0; + break; + case CH_LP1: + ret_irq = IRQ_LP1; + break; + case CH_LP2: + ret_irq = IRQ_LP2; + break; + case CH_LP3: + ret_irq = IRQ_LP3; + break; + case CH_UART0_RX: + ret_irq = IRQ_UART0_RX; + break; + case CH_UART0_TX: + ret_irq = IRQ_UART0_TX; + break; + case CH_UART1_RX: + ret_irq = IRQ_UART1_RX; + break; + case CH_UART1_TX: + ret_irq = IRQ_UART1_TX; + break; + case CH_EPPI0_CH0: + ret_irq = IRQ_EPPI0_CH0; + break; + case CH_EPPI0_CH1: + ret_irq = IRQ_EPPI0_CH1; + break; + case CH_EPPI1_CH0: + ret_irq = IRQ_EPPI1_CH0; + break; + case CH_EPPI1_CH1: + ret_irq = IRQ_EPPI1_CH1; + break; + case CH_EPPI2_CH0: + ret_irq = IRQ_EPPI2_CH0; + break; + case CH_EPPI2_CH1: + ret_irq = IRQ_EPPI2_CH1; + break; + case CH_PIXC_CH0: + ret_irq = IRQ_PIXC_CH0; + break; + case CH_PIXC_CH1: + ret_irq = IRQ_PIXC_CH1; + break; + case CH_PIXC_CH2: + ret_irq = IRQ_PIXC_CH2; + break; + case CH_PVP_CPDOB: + ret_irq = IRQ_PVP_CPDOB; + break; + case CH_PVP_CPDOC: + ret_irq = IRQ_PVP_CPDOC; + break; + case CH_PVP_CPSTAT: + ret_irq = IRQ_PVP_CPSTAT; + break; + case CH_PVP_CPCI: + ret_irq = IRQ_PVP_CPCI; + break; + case CH_PVP_MPDO: + ret_irq = IRQ_PVP_MPDO; + break; + case CH_PVP_MPDI: + ret_irq = IRQ_PVP_MPDI; + break; + case CH_PVP_MPSTAT: + ret_irq = IRQ_PVP_MPSTAT; + break; + case CH_PVP_MPCI: + ret_irq = IRQ_PVP_MPCI; + break; + case CH_PVP_CPDOA: + ret_irq = IRQ_PVP_CPDOA; + break; + case CH_MEM_STREAM0_SRC: + case CH_MEM_STREAM0_DEST: + ret_irq = IRQ_MDMAS0; + break; + case CH_MEM_STREAM1_SRC: + case CH_MEM_STREAM1_DEST: + ret_irq = IRQ_MDMAS1; + break; + case CH_MEM_STREAM2_SRC: + case CH_MEM_STREAM2_DEST: + ret_irq = IRQ_MDMAS2; + break; + case CH_MEM_STREAM3_SRC: + case CH_MEM_STREAM3_DEST: + ret_irq = IRQ_MDMAS3; + break; + } + return ret_irq; +} diff --git a/arch/blackfin/mach-bf609/hibernate.S b/arch/blackfin/mach-bf609/hibernate.S new file mode 100644 index 000000000000..d37a532519c8 --- /dev/null +++ b/arch/blackfin/mach-bf609/hibernate.S @@ -0,0 +1,65 @@ +#include <linux/linkage.h> +#include <asm/blackfin.h> +#include <asm/dpmc.h> + +#define PM_STACK (COREA_L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12) + +.section .l1.text +ENTRY(_enter_hibernate) + /* switch stack to L1 scratch, prepare for ddr srfr */ + P0.H = HI(PM_STACK); + P0.L = LO(PM_STACK); + SP = P0; + + call _bf609_ddr_sr; + call _bfin_hibernate_syscontrol; + + P0.H = HI(DPM0_RESTORE4); + P0.L = LO(DPM0_RESTORE4); + P1.H = _bf609_pm_data; + P1.L = _bf609_pm_data; + [P0] = P1; + + P0.H = HI(DPM0_CTL); + P0.L = LO(DPM0_CTL); + R3.H = HI(0x00000010); + R3.L = LO(0x00000010); + + bfin_init_pm_bench_cycles; + + [P0] = R3; + + SSYNC; +ENDPROC(_enter_hibernate_mode) + +.section .text +ENTRY(_bf609_hibernate) + bfin_cpu_reg_save; + bfin_core_mmr_save; + + P0.H = _bf609_pm_data; + P0.L = _bf609_pm_data; + R1.H = 0xDEAD; + R1.L = 0xBEEF; + R2.H = .Lpm_resume_here; + R2.L = .Lpm_resume_here; + [P0++] = R1; + [P0++] = R2; + [P0++] = SP; + + P1.H = _enter_hibernate; + P1.L = _enter_hibernate; + + call (P1); +.Lpm_resume_here: + + bfin_core_mmr_restore; + bfin_cpu_reg_restore; + + [--sp] = RETI; /* Clear Global Interrupt Disable */ + SP += 4; + + RTS; + +ENDPROC(_bf609_hibernate) + diff --git a/arch/blackfin/mach-bf609/include/mach/anomaly.h b/arch/blackfin/mach-bf609/include/mach/anomaly.h new file mode 100644 index 000000000000..bdd39aefb565 --- /dev/null +++ b/arch/blackfin/mach-bf609/include/mach/anomaly.h @@ -0,0 +1,130 @@ +/* + * DO NOT EDIT THIS FILE + * This file is under version control at + * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/ + * and can be replaced with that version at any time + * DO NOT EDIT THIS FILE + * + * Copyright 2004-2011 Analog Devices Inc. + * Licensed under the Clear BSD license. + */ + +/* This file should be up to date with: + */ + +#if __SILICON_REVISION__ < 0 +# error will not work on BF506 silicon version +#endif + +#ifndef _MACH_ANOMALY_H_ +#define _MACH_ANOMALY_H_ + +/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ +#define ANOMALY_05000074 (1) +/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ +#define ANOMALY_05000119 (1) +/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ +#define ANOMALY_05000122 (1) +/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ +#define ANOMALY_05000245 (1) +/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */ +#define ANOMALY_05000254 (1) +/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ +#define ANOMALY_05000265 (1) +/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ +#define ANOMALY_05000310 (1) +/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ +#define ANOMALY_05000366 (1) +/* Speculative Fetches Can Cause Undesired External FIFO Operations */ +#define ANOMALY_05000416 (1) +/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ +#define ANOMALY_05000426 (1) +/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ +#define ANOMALY_05000443 (1) +/* UART IrDA Receiver Fails on Extended Bit Pulses */ +#define ANOMALY_05000447 (1) +/* False Hardware Error when RETI Points to Invalid Memory */ +#define ANOMALY_05000461 (1) +/* PLL Latches Incorrect Settings During Reset */ +#define ANOMALY_05000469 (1) +/* Incorrect Default MSEL Value in PLL_CTL */ +#define ANOMALY_05000472 (1) +/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */ +#define ANOMALY_05000473 (1) +/* TESTSET Instruction Cannot Be Interrupted */ +#define ANOMALY_05000477 (1) +/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ +#define ANOMALY_05000481 (1) +/* IFLUSH sucks at life */ +#define ANOMALY_05000491 (1) +/* Tempopary anomaly ID for data loss in MMR read operation if interrupted */ +#define ANOMALY_05001001 (__SILICON_REVISION__ < 1) + +/* Anomalies that don't exist on this proc */ +#define ANOMALY_05000099 (0) +#define ANOMALY_05000120 (0) +#define ANOMALY_05000125 (0) +#define ANOMALY_05000149 (0) +#define ANOMALY_05000158 (0) +#define ANOMALY_05000171 (0) +#define ANOMALY_05000179 (0) +#define ANOMALY_05000182 (0) +#define ANOMALY_05000183 (0) +#define ANOMALY_05000189 (0) +#define ANOMALY_05000198 (0) +#define ANOMALY_05000202 (0) +#define ANOMALY_05000215 (0) +#define ANOMALY_05000219 (0) +#define ANOMALY_05000220 (0) +#define ANOMALY_05000227 (0) +#define ANOMALY_05000230 (0) +#define ANOMALY_05000231 (0) +#define ANOMALY_05000233 (0) +#define ANOMALY_05000234 (0) +#define ANOMALY_05000242 (0) +#define ANOMALY_05000244 (0) +#define ANOMALY_05000248 (0) +#define ANOMALY_05000250 (0) +#define ANOMALY_05000257 (0) +#define ANOMALY_05000261 (0) +#define ANOMALY_05000263 (0) +#define ANOMALY_05000266 (0) +#define ANOMALY_05000273 (0) +#define ANOMALY_05000274 (0) +#define ANOMALY_05000278 (0) +#define ANOMALY_05000281 (0) +#define ANOMALY_05000283 (0) +#define ANOMALY_05000285 (0) +#define ANOMALY_05000287 (0) +#define ANOMALY_05000301 (0) +#define ANOMALY_05000305 (0) +#define ANOMALY_05000307 (0) +#define ANOMALY_05000311 (0) +#define ANOMALY_05000312 (0) +#define ANOMALY_05000315 (0) +#define ANOMALY_05000323 (0) +#define ANOMALY_05000353 (1) +#define ANOMALY_05000357 (0) +#define ANOMALY_05000362 (1) +#define ANOMALY_05000363 (0) +#define ANOMALY_05000364 (0) +#define ANOMALY_05000371 (0) +#define ANOMALY_05000380 (0) +#define ANOMALY_05000386 (0) +#define ANOMALY_05000389 (0) +#define ANOMALY_05000400 (0) +#define ANOMALY_05000402 (0) +#define ANOMALY_05000412 (0) +#define ANOMALY_05000432 (0) +#define ANOMALY_05000440 (0) +#define ANOMALY_05000448 (0) +#define ANOMALY_05000456 (0) +#define ANOMALY_05000450 (0) +#define ANOMALY_05000465 (0) +#define ANOMALY_05000467 (0) +#define ANOMALY_05000474 (0) +#define ANOMALY_05000475 (0) +#define ANOMALY_05000480 (0) +#define ANOMALY_05000485 (0) + +#endif diff --git a/arch/blackfin/mach-bf609/include/mach/bf609.h b/arch/blackfin/mach-bf609/include/mach/bf609.h new file mode 100644 index 000000000000..c897c2a2fbfa --- /dev/null +++ b/arch/blackfin/mach-bf609/include/mach/bf609.h @@ -0,0 +1,93 @@ +/* + * Copyright 2011 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __MACH_BF609_H__ +#define __MACH_BF609_H__ + +#define OFFSET_(x) ((x) & 0x0000FFFF) + +/*some misc defines*/ +#define IMASK_IVG15 0x8000 +#define IMASK_IVG14 0x4000 +#define IMASK_IVG13 0x2000 +#define IMASK_IVG12 0x1000 + +#define IMASK_IVG11 0x0800 +#define IMASK_IVG10 0x0400 +#define IMASK_IVG9 0x0200 +#define IMASK_IVG8 0x0100 + +#define IMASK_IVG7 0x0080 +#define IMASK_IVGTMR 0x0040 +#define IMASK_IVGHW 0x0020 + +/***************************/ + + +#define BFIN_DSUBBANKS 4 +#define BFIN_DWAYS 2 +#define BFIN_DLINES 64 +#define BFIN_ISUBBANKS 4 +#define BFIN_IWAYS 4 +#define BFIN_ILINES 32 + +#define WAY0_L 0x1 +#define WAY1_L 0x2 +#define WAY01_L 0x3 +#define WAY2_L 0x4 +#define WAY02_L 0x5 +#define WAY12_L 0x6 +#define WAY012_L 0x7 + +#define WAY3_L 0x8 +#define WAY03_L 0x9 +#define WAY13_L 0xA +#define WAY013_L 0xB + +#define WAY32_L 0xC +#define WAY320_L 0xD +#define WAY321_L 0xE +#define WAYALL_L 0xF + +#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */ + +/********************************* EBIU Settings ************************************/ +#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0) +#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2) + +#ifdef CONFIG_C_AMBEN_ALL +#define V_AMBEN AMBEN_ALL +#endif +#ifdef CONFIG_C_AMBEN +#define V_AMBEN 0x0 +#endif +#ifdef CONFIG_C_AMBEN_B0 +#define V_AMBEN AMBEN_B0 +#endif +#ifdef CONFIG_C_AMBEN_B0_B1 +#define V_AMBEN AMBEN_B0_B1 +#endif +#ifdef CONFIG_C_AMBEN_B0_B1_B2 +#define V_AMBEN AMBEN_B0_B1_B2 +#endif +#ifdef CONFIG_C_AMCKEN +#define V_AMCKEN AMCKEN +#else +#define V_AMCKEN 0x0 +#endif + +#define AMGCTLVAL (V_AMBEN | V_AMCKEN) + +#if defined(CONFIG_BF609) +# define CPU "BF609" +# define CPUID 0x27fe /* temperary fake value */ +#endif + +#ifndef CPU +#error "Unknown CPU type - This kernel doesn't seem to be configured properly" +#endif + +#endif /* __MACH_BF609_H__ */ diff --git a/arch/blackfin/mach-bf609/include/mach/bfin_serial.h b/arch/blackfin/mach-bf609/include/mach/bfin_serial.h new file mode 100644 index 000000000000..1fd398147fd9 --- /dev/null +++ b/arch/blackfin/mach-bf609/include/mach/bfin_serial.h @@ -0,0 +1,17 @@ +/* + * mach/bfin_serial.h - Blackfin UART/Serial definitions + * + * Copyright 2011 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __BFIN_MACH_SERIAL_H__ +#define __BFIN_MACH_SERIAL_H__ + +#define BFIN_UART_NR_PORTS 2 +#define BFIN_UART_TX_FIFO_SIZE 8 + +#define BFIN_UART_BF60X_STYLE + +#endif diff --git a/arch/blackfin/mach-bf609/include/mach/blackfin.h b/arch/blackfin/mach-bf609/include/mach/blackfin.h new file mode 100644 index 000000000000..b1a48c410711 --- /dev/null +++ b/arch/blackfin/mach-bf609/include/mach/blackfin.h @@ -0,0 +1,25 @@ +/* + * Copyright 2011 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _MACH_BLACKFIN_H_ +#define _MACH_BLACKFIN_H_ + +#include "bf609.h" +#include "anomaly.h" + +#include <asm/def_LPBlackfin.h> +#ifdef CONFIG_BF609 +# include "defBF609.h" +#endif + +#ifndef __ASSEMBLY__ +# include <asm/cdef_LPBlackfin.h> +# ifdef CONFIG_BF609 +# include "cdefBF609.h" +# endif +#endif + +#endif diff --git a/arch/blackfin/mach-bf609/include/mach/cdefBF609.h b/arch/blackfin/mach-bf609/include/mach/cdefBF609.h new file mode 100644 index 000000000000..c4f3fe19acda --- /dev/null +++ b/arch/blackfin/mach-bf609/include/mach/cdefBF609.h @@ -0,0 +1,15 @@ +/* + * Copyright 2011 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _CDEF_BF609_H +#define _CDEF_BF609_H + +/* include cdefBF60x_base.h for the set of #defines that are common to all ADSP-BF60x bfin_read_()rocessors */ +#include "cdefBF60x_base.h" + +/* The following are the #defines needed by ADSP-BF609 that are not in the common header */ + +#endif /* _CDEF_BF609_H */ diff --git a/arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h b/arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h new file mode 100644 index 000000000000..4954cf3f7e16 --- /dev/null +++ b/arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h @@ -0,0 +1,3252 @@ +/* + * Copyright 2011 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _CDEF_BF60X_H +#define _CDEF_BF60X_H + +/* ************************************************************** */ +/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF60x */ +/* ************************************************************** */ + +/* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */ + +#define bfin_read_CHIPID() bfin_read32(CHIPID) +#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) + +/* System Reset and Interrubfin_read_()t Controller (0xFFC00100 - 0xFFC00104) */ + +/* SEC0 Registers */ +#define bfin_read_SEC0_CCTL() bfin_read32(SEC0_CCTL) +#define bfin_write_SEC0_CCTL(val) bfin_write32(SEC0_CCTL, val) +#define bfin_read_SEC0_CSID() bfin_read32(SEC0_CSID) +#define bfin_write_SEC0_CSID(val) bfin_write32(SEC0_CSID, val) +#define bfin_read_SEC_GCTL() bfin_read32(SEC_GCTL) +#define bfin_write_SEC_GCTL(val) bfin_write32(SEC_GCTL, val) + +#define bfin_read_SEC_FCTL() bfin_read32(SEC_FCTL) +#define bfin_write_SEC_FCTL(val) bfin_write32(SEC_FCTL, val) + +#define bfin_read_SEC_SCTL(sid) bfin_read32((SEC_SCTL0 + (sid) * 8)) +#define bfin_write_SEC_SCTL(sid, val) bfin_write32((SEC_SCTL0 + (sid) * 8), val) + +#define bfin_read_SEC_SSTAT(sid) bfin_read32((SEC_SSTAT0 + (sid) * 8)) +#define bfin_write_SEC_SSTAT(sid, val) bfin_write32((SEC_SSTAT0 + (sid) * 8), val) + +/* RCU0 Registers */ +#define bfin_read_RCU0_CTL() bfin_read32(RCU0_CTL) +#define bfin_write_RCU0_CTL(val) bfin_write32(RCU0_CTL, val) + +/* Watchdog Timer Registers */ +#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) +#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val) +#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) +#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val) +#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) +#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val) + +/* RTC Registers */ + +/* UART0 Registers */ + +#define bfin_read_UART0_REVID() bfin_read32(UART0_REVID) +#define bfin_write_UART0_REVID(val) bfin_write32(UART0_REVID, val) +#define bfin_read_UART0_GCTL() bfin_read32(UART0_GCTL) +#define bfin_write_UART0_GCTL(val) bfin_write32(UART0_GCTL, val) +#define bfin_read_UART0_STAT() bfin_read32(UART0_STAT) +#define bfin_write_UART0_STAT(val) bfin_write32(UART0_STAT, val) +#define bfin_read_UART0_SCR() bfin_read32(UART0_SCR) +#define bfin_write_UART0_SCR(val) bfin_write32(UART0_SCR, val) +#define bfin_read_UART0_CLK() bfin_read32(UART0_CLK) +#define bfin_write_UART0_CLK(val) bfin_write32(UART0_CLK, val) +#define bfin_read_UART0_IER() bfin_read32(UART0_IER) +#define bfin_write_UART0_IER(val) bfin_write32(UART0_IER, val) +#define bfin_read_UART0_IER_SET() bfin_read32(UART0_IER_SET) +#define bfin_write_UART0_IER_SET(val) bfin_write32(UART0_IER_SET, val) +#define bfin_read_UART0_IER_CLEAR() bfin_read32(UART0_IER_CLEAR) +#define bfin_write_UART0_IER_CLEAR(val) bfin_write32(UART0_IER_CLEAR, val) +#define bfin_read_UART0_RBR() bfin_read32(UART0_RBR) +#define bfin_write_UART0_RBR(val) bfin_write32(UART0_RBR, val) +#define bfin_read_UART0_THR() bfin_read32(UART0_THR) +#define bfin_write_UART0_THR(val) bfin_write32(UART0_THR, val) +#define bfin_read_UART0_TAIP() bfin_read32(UART0_TAIP) +#define bfin_write_UART0_TAIP(val) bfin_write32(UART0_TAIP, val) +#define bfin_read_UART0_TSR() bfin_read32(UART0_TSR) +#define bfin_write_UART0_TSR(val) bfin_write32(UART0_TSR, val) +#define bfin_read_UART0_RSR() bfin_read32(UART0_RSR) +#define bfin_write_UART0_RSR(val) bfin_write32(UART0_RSR, val) +#define bfin_read_UART0_TXCNT() bfin_read32(UART0_TXCNT) +#define bfin_write_UART0_TXCNT(val) bfin_write32(UART0_TXCNT, val) +#define bfin_read_UART0_RXCNT() bfin_read32(UART0_RXCNT) +#define bfin_write_UART0_RXCNT(val) bfin_write32(UART0_RXCNT, val) + +/* UART1 Registers */ + +#define bfin_read_UART1_REVID() bfin_read32(UART1_REVID) +#define bfin_write_UART1_REVID(val) bfin_write32(UART1_REVID, val) +#define bfin_read_UART1_GCTL() bfin_read32(UART1_GCTL) +#define bfin_write_UART1_GCTL(val) bfin_write32(UART1_GCTL, val) +#define bfin_read_UART1_STAT() bfin_read32(UART1_STAT) +#define bfin_write_UART1_STAT(val) bfin_write32(UART1_STAT, val) +#define bfin_read_UART1_SCR() bfin_read32(UART1_SCR) +#define bfin_write_UART1_SCR(val) bfin_write32(UART1_SCR, val) +#define bfin_read_UART1_CLK() bfin_read32(UART1_CLK) +#define bfin_write_UART1_CLK(val) bfin_write32(UART1_CLK, val) +#define bfin_read_UART1_IER() bfin_read32(UART1_IER) +#define bfin_write_UART1_IER(val) bfin_write32(UART1_IER, val) +#define bfin_read_UART1_IER_SET() bfin_read32(UART1_IER_SET) +#define bfin_write_UART1_IER_SET(val) bfin_write32(UART1_IER_SET, val) +#define bfin_read_UART1_IER_CLEAR() bfin_read32(UART1_IER_CLEAR) +#define bfin_write_UART1_IER_CLEAR(val) bfin_write32(UART1_IER_CLEAR, val) +#define bfin_read_UART1_RBR() bfin_read32(UART1_RBR) +#define bfin_write_UART1_RBR(val) bfin_write32(UART1_RBR, val) +#define bfin_read_UART1_THR() bfin_read32(UART1_THR) +#define bfin_write_UART1_THR(val) bfin_write32(UART1_THR, val) +#define bfin_read_UART1_TAIP() bfin_read32(UART1_TAIP) +#define bfin_write_UART1_TAIP(val) bfin_write32(UART1_TAIP, val) +#define bfin_read_UART1_TSR() bfin_read32(UART1_TSR) +#define bfin_write_UART1_TSR(val) bfin_write32(UART1_TSR, val) +#define bfin_read_UART1_RSR() bfin_read32(UART1_RSR) +#define bfin_write_UART1_RSR(val) bfin_write32(UART1_RSR, val) +#define bfin_read_UART1_TXCNT() bfin_read32(UART1_TXCNT) +#define bfin_write_UART1_TXCNT(val) bfin_write32(UART1_TXCNT, val) +#define bfin_read_UART1_RXCNT() bfin_read32(UART1_RXCNT) +#define bfin_write_UART1_RXCNT(val) bfin_write32(UART1_RXCNT, val) + + +/* SPI0 Registers */ + +#define bfin_read_SPI0_CTL() bfin_read32(SPI0_CTL) +#define bfin_write_SPI0_CTL(val) bfin_write32(SPI0_CTL, val) +#define bfin_read_SPI0_RXCTL() bfin_read32(SPI0_RXCTL) +#define bfin_write_SPI0_RXCTL(val) bfin_write32(SPI0_RXCTL, val) +#define bfin_read_SPI0_TXCTL() bfin_read32(SPI0_TXCTL) +#define bfin_write_SPI0_TXCTL(val) bfin_write32(SPI0_TXCTL, val) +#define bfin_read_SPI0_CLK() bfin_read32(SPI0_CLK) +#define bfin_write_SPI0_CLK(val) bfin_write32(SPI0_CLK, val) +#define bfin_read_SPI0_DLY() bfin_read32(SPI0_DLY) +#define bfin_write_SPI0_DLY(val) bfin_write32(SPI0_DLY, val) +#define bfin_read_SPI0_SLVSEL() bfin_read32(SPI0_SLVSEL) +#define bfin_write_SPI0_SLVSEL(val) bfin_write32(SPI0_SLVSEL, val) +#define bfin_read_SPI0_RWC() bfin_read32(SPI0_RWC) +#define bfin_write_SPI0_RWC(val) bfin_write32(SPI0_RWC, val) +#define bfin_read_SPI0_RWCR() bfin_read32(SPI0_RWCR) +#define bfin_write_SPI0_RWCR(val) bfin_write32(SPI0_RWCR, val) +#define bfin_read_SPI0_TWC() bfin_read32(SPI0_TWC) +#define bfin_write_SPI0_TWC(val) bfin_write32(SPI0_TWC, val) +#define bfin_read_SPI0_TWCR() bfin_read32(SPI0_TWCR) +#define bfin_write_SPI0_TWCR(val) bfin_write32(SPI0_TWCR, val) +#define bfin_read_SPI0_IMSK() bfin_read32(SPI0_IMSK) +#define bfin_write_SPI0_IMSK(val) bfin_write32(SPI0_IMSK, val) +#define bfin_read_SPI0_IMSK_CLR() bfin_read32(SPI0_IMSK_CLR) +#define bfin_write_SPI0_IMSK_CLR(val) bfin_write32(SPI0_IMSK_CLR, val) +#define bfin_read_SPI0_IMSK_SET() bfin_read32(SPI0_IMSK_SET) +#define bfin_write_SPI0_IMSK_SET(val) bfin_write32(SPI0_IMSK_SET, val) +#define bfin_read_SPI0_STAT() bfin_read32(SPI0_STAT) +#define bfin_write_SPI0_STAT(val) bfin_write32(SPI0_STAT, val) +#define bfin_read_SPI0_ILAT() bfin_read32(SPI0_ILAT) +#define bfin_write_SPI0_ILAT(val) bfin_write32(SPI0_ILAT, val) +#define bfin_read_SPI0_ILAT_CLR() bfin_read32(SPI0_ILAT_CLR) +#define bfin_write_SPI0_ILAT_CLR(val) bfin_write32(SPI0_ILAT_CLR, val) +#define bfin_read_SPI0_RFIFO() bfin_read32(SPI0_RFIFO) +#define bfin_write_SPI0_RFIFO(val) bfin_write32(SPI0_RFIFO, val) +#define bfin_read_SPI0_TFIFO() bfin_read32(SPI0_TFIFO) +#define bfin_write_SPI0_TFIFO(val) bfin_write32(SPI0_TFIFO, val) + +/* SPI1 Registers */ + +#define bfin_read_SPI1_CTL() bfin_read32(SPI1_CTL) +#define bfin_write_SPI1_CTL(val) bfin_write32(SPI1_CTL, val) +#define bfin_read_SPI1_RXCTL() bfin_read32(SPI1_RXCTL) +#define bfin_write_SPI1_RXCTL(val) bfin_write32(SPI1_RXCTL, val) +#define bfin_read_SPI1_TXCTL() bfin_read32(SPI1_TXCTL) +#define bfin_write_SPI1_TXCTL(val) bfin_write32(SPI1_TXCTL, val) +#define bfin_read_SPI1_CLK() bfin_read32(SPI1_CLK) +#define bfin_write_SPI1_CLK(val) bfin_write32(SPI1_CLK, val) +#define bfin_read_SPI1_DLY() bfin_read32(SPI1_DLY) +#define bfin_write_SPI1_DLY(val) bfin_write32(SPI1_DLY, val) +#define bfin_read_SPI1_SLVSEL() bfin_read32(SPI1_SLVSEL) +#define bfin_write_SPI1_SLVSEL(val) bfin_write32(SPI1_SLVSEL, val) +#define bfin_read_SPI1_RWC() bfin_read32(SPI1_RWC) +#define bfin_write_SPI1_RWC(val) bfin_write32(SPI1_RWC, val) +#define bfin_read_SPI1_RWCR() bfin_read32(SPI1_RWCR) +#define bfin_write_SPI1_RWCR(val) bfin_write32(SPI1_RWCR, val) +#define bfin_read_SPI1_TWC() bfin_read32(SPI1_TWC) +#define bfin_write_SPI1_TWC(val) bfin_write32(SPI1_TWC, val) +#define bfin_read_SPI1_TWCR() bfin_read32(SPI1_TWCR) +#define bfin_write_SPI1_TWCR(val) bfin_write32(SPI1_TWCR, val) +#define bfin_read_SPI1_IMSK() bfin_read32(SPI1_IMSK) +#define bfin_write_SPI1_IMSK(val) bfin_write32(SPI1_IMSK, val) +#define bfin_read_SPI1_IMSK_CLR() bfin_read32(SPI1_IMSK_CLR) +#define bfin_write_SPI1_IMSK_CLR(val) bfin_write32(SPI1_IMSK_CLR, val) +#define bfin_read_SPI1_IMSK_SET() bfin_read32(SPI1_IMSK_SET) +#define bfin_write_SPI1_IMSK_SET(val) bfin_write32(SPI1_IMSK_SET, val) +#define bfin_read_SPI1_STAT() bfin_read32(SPI1_STAT) +#define bfin_write_SPI1_STAT(val) bfin_write32(SPI1_STAT, val) +#define bfin_read_SPI1_ILAT() bfin_read32(SPI1_ILAT) +#define bfin_write_SPI1_ILAT(val) bfin_write32(SPI1_ILAT, val) +#define bfin_read_SPI1_ILAT_CLR() bfin_read32(SPI1_ILAT_CLR) +#define bfin_write_SPI1_ILAT_CLR(val) bfin_write32(SPI1_ILAT_CLR, val) +#define bfin_read_SPI1_RFIFO() bfin_read32(SPI1_RFIFO) +#define bfin_write_SPI1_RFIFO(val) bfin_write32(SPI1_RFIFO, val) +#define bfin_read_SPI1_TFIFO() bfin_read32(SPI1_TFIFO) +#define bfin_write_SPI1_TFIFO(val) bfin_write32(SPI1_TFIFO, val) + +/* Timer 0-7 registers */ +#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) +#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) +#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) +#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val) +#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) +#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val) +#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) +#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val) +#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) +#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val) +#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) +#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val) +#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) +#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val) +#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) +#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val) +#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) +#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val) +#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) +#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val) +#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) +#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val) +#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) +#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val) +#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG) +#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val) +#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER) +#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val) +#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD) +#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val) +#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH) +#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val) +#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG) +#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val) +#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER) +#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val) +#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD) +#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val) +#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH) +#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val) +#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG) +#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val) +#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER) +#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val) +#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD) +#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val) +#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH) +#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val) +#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG) +#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val) +#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER) +#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val) +#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD) +#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val) +#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH) +#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val) +#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG) +#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val) +#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER) +#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val) +#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD) +#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val) +#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH) +#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val) + + + + +/* Two Wire Interface Registers (TWI0) */ + +/* SPORT1 Registers */ + + +/* SMC Registers */ +#define bfin_read_SMC_GCTL() bfin_read32(SMC_GCTL) +#define bfin_write_SMC_GCTL(val) bfin_write32(SMC_GCTL, val) +#define bfin_read_SMC_GSTAT() bfin_read32(SMC_GSTAT) +#define bfin_read_SMC_B0CTL() bfin_read32(SMC_B0CTL) +#define bfin_write_SMC_B0CTL(val) bfin_write32(SMC_B0CTL, val) +#define bfin_read_SMC_B0TIM() bfin_read32(SMC_B0TIM) +#define bfin_write_SMC_B0TIM(val) bfin_write32(SMC_B0TIM, val) +#define bfin_read_SMC_B0ETIM() bfin_read32(SMC_B0ETIM) +#define bfin_write_SMC_B0ETIM(val) bfin_write32(SMC_B0ETIM, val) +#define bfin_read_SMC_B1CTL() bfin_read32(SMC_B1CTL) +#define bfin_write_SMC_B1CTL(val) bfin_write32(SMC_B1CTL, val) +#define bfin_read_SMC_B1TIM() bfin_read32(SMC_B1TIM) +#define bfin_write_SMC_B1TIM(val) bfin_write32(SMC_B1TIM, val) +#define bfin_read_SMC_B1ETIM() bfin_read32(SMC_B1ETIM) +#define bfin_write_SMC_B1ETIM(val) bfin_write32(SMC_B1ETIM, val) +#define bfin_read_SMC_B2CTL() bfin_read32(SMC_B2CTL) +#define bfin_write_SMC_B2CTL(val) bfin_write32(SMC_B2CTL, val) +#define bfin_read_SMC_B2TIM() bfin_read32(SMC_B2TIM) +#define bfin_write_SMC_B2TIM(val) bfin_write32(SMC_B2TIM, val) +#define bfin_read_SMC_B2ETIM() bfin_read32(SMC_B2ETIM) +#define bfin_write_SMC_B2ETIM(val) bfin_write32(SMC_B2ETIM, val) +#define bfin_read_SMC_B3CTL() bfin_read32(SMC_B3CTL) +#define bfin_write_SMC_B3CTL(val) bfin_write32(SMC_B3CTL, val) +#define bfin_read_SMC_B3TIM() bfin_read32(SMC_B3TIM) +#define bfin_write_SMC_B3TIM(val) bfin_write32(SMC_B3TIM, val) +#define bfin_read_SMC_B3ETIM() bfin_read32(SMC_B3ETIM) +#define bfin_write_SMC_B3ETIM(val) bfin_write32(SMC_B3ETIM, val) + +/* DDR2 Memory Control Registers */ +#define bfin_read_DMC0_CFG() bfin_read32(DMC0_CFG) +#define bfin_write_DMC0_CFG(val) bfin_write32(DMC0_CFG, val) +#define bfin_read_DMC0_TR0() bfin_read32(DMC0_TR0) +#define bfin_write_DMC0_TR0(val) bfin_write32(DMC0_TR0, val) +#define bfin_read_DMC0_TR1() bfin_read32(DMC0_TR1) +#define bfin_write_DMC0_TR1(val) bfin_write32(DMC0_TR1, val) +#define bfin_read_DMC0_TR2() bfin_read32(DMC0_TR2) +#define bfin_write_DMC0_TR2(val) bfin_write32(DMC0_TR2, val) +#define bfin_read_DMC0_MR() bfin_read32(DMC0_MR) +#define bfin_write_DMC0_MR(val) bfin_write32(DMC0_MR, val) +#define bfin_read_DMC0_EMR1() bfin_read32(DMC0_EMR1) +#define bfin_write_DMC0_EMR1(val) bfin_write32(DMC0_EMR1, val) +#define bfin_read_DMC0_CTL() bfin_read32(DMC0_CTL) +#define bfin_write_DMC0_CTL(val) bfin_write32(DMC0_CTL, val) +#define bfin_read_DMC0_STAT() bfin_read32(DMC0_STAT) +#define bfin_write_DMC0_STAT(val) bfin_write32(DMC0_STAT, val) +#define bfin_read_DMC0_DLLCTL() bfin_read32(DMC0_DLLCTL) +#define bfin_write_DMC0_DLLCTL(val) bfin_write32(DMC0_DLLCTL, val) + +/* DDR BankRead and Write Count Registers */ + + +/* DMA Channel 0 Registers */ + +#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR) +#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val) +#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR) +#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val) +#define bfin_read_DMA0_CONFIG() bfin_read32(DMA0_CONFIG) +#define bfin_write_DMA0_CONFIG(val) bfin_write32(DMA0_CONFIG, val) +#define bfin_read_DMA0_X_COUNT() bfin_read32(DMA0_X_COUNT) +#define bfin_write_DMA0_X_COUNT(val) bfin_write32(DMA0_X_COUNT, val) +#define bfin_read_DMA0_X_MODIFY() bfin_read32(DMA0_X_MODIFY) +#define bfin_write_DMA0_X_MODIFY(val) bfin_write32(DMA0_X_MODIFY, val) +#define bfin_read_DMA0_Y_COUNT() bfin_read32(DMA0_Y_COUNT) +#define bfin_write_DMA0_Y_COUNT(val) bfin_write32(DMA0_Y_COUNT, val) +#define bfin_read_DMA0_Y_MODIFY() bfin_read32(DMA0_Y_MODIFY) +#define bfin_write_DMA0_Y_MODIFY(val) bfin_write32(DMA0_Y_MODIFY, val) +#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR) +#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val) +#define bfin_read_DMA0_PREV_DESC_PTR() bfin_read32(DMA0_PREV_DESC_PTR) +#define bfin_write_DMA0_PREV_DESC_PTR(val) bfin_write32(DMA0_PREV_DESC_PTR, val) +#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR) +#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val) +#define bfin_read_DMA0_IRQ_STATUS() bfin_read32(DMA0_IRQ_STATUS) +#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write32(DMA0_IRQ_STATUS, val) +#define bfin_read_DMA0_CURR_X_COUNT() bfin_read32(DMA0_CURR_X_COUNT) +#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write32(DMA0_CURR_X_COUNT, val) +#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read32(DMA0_CURR_Y_COUNT) +#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write32(DMA0_CURR_Y_COUNT, val) +#define bfin_read_DMA0_BWL_COUNT() bfin_read32(DMA0_BWL_COUNT) +#define bfin_write_DMA0_BWL_COUNT(val) bfin_write32(DMA0_BWL_COUNT, val) +#define bfin_read_DMA0_CURR_BWL_COUNT() bfin_read32(DMA0_CURR_BWL_COUNT) +#define bfin_write_DMA0_CURR_BWL_COUNT(val) bfin_write32(DMA0_CURR_BWL_COUNT, val) +#define bfin_read_DMA0_BWM_COUNT() bfin_read32(DMA0_BWM_COUNT) +#define bfin_write_DMA0_BWM_COUNT(val) bfin_write32(DMA0_BWM_COUNT, val) +#define bfin_read_DMA0_CURR_BWM_COUNT() bfin_read32(DMA0_CURR_BWM_COUNT) +#define bfin_write_DMA0_CURR_BWM_COUNT(val) bfin_write32(DMA0_CURR_BWM_COUNT, val) + +/* DMA Channel 1 Registers */ + +#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR) +#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val) +#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR) +#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val) +#define bfin_read_DMA1_CONFIG() bfin_read32(DMA1_CONFIG) +#define bfin_write_DMA1_CONFIG(val) bfin_write32(DMA1_CONFIG, val) +#define bfin_read_DMA1_X_COUNT() bfin_read32(DMA1_X_COUNT) +#define bfin_write_DMA1_X_COUNT(val) bfin_write32(DMA1_X_COUNT, val) +#define bfin_read_DMA1_X_MODIFY() bfin_read32(DMA1_X_MODIFY) +#define bfin_write_DMA1_X_MODIFY(val) bfin_write32(DMA1_X_MODIFY, val) +#define bfin_read_DMA1_Y_COUNT() bfin_read32(DMA1_Y_COUNT) +#define bfin_write_DMA1_Y_COUNT(val) bfin_write32(DMA1_Y_COUNT, val) +#define bfin_read_DMA1_Y_MODIFY() bfin_read32(DMA1_Y_MODIFY) +#define bfin_write_DMA1_Y_MODIFY(val) bfin_write32(DMA1_Y_MODIFY, val) +#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR) +#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val) +#define bfin_read_DMA1_PREV_DESC_PTR() bfin_read32(DMA1_PREV_DESC_PTR) +#define bfin_write_DMA1_PREV_DESC_PTR(val) bfin_write32(DMA1_PREV_DESC_PTR, val) +#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR) +#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val) +#define bfin_read_DMA1_IRQ_STATUS() bfin_read32(DMA1_IRQ_STATUS) +#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write32(DMA1_IRQ_STATUS, val) +#define bfin_read_DMA1_CURR_X_COUNT() bfin_read32(DMA1_CURR_X_COUNT) +#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write32(DMA1_CURR_X_COUNT, val) +#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read32(DMA1_CURR_Y_COUNT) +#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write32(DMA1_CURR_Y_COUNT, val) +#define bfin_read_DMA1_BWL_COUNT() bfin_read32(DMA1_BWL_COUNT) +#define bfin_write_DMA1_BWL_COUNT(val) bfin_write32(DMA1_BWL_COUNT, val) +#define bfin_read_DMA1_CURR_BWL_COUNT() bfin_read32(DMA1_CURR_BWL_COUNT) +#define bfin_write_DMA1_CURR_BWL_COUNT(val) bfin_write32(DMA1_CURR_BWL_COUNT, val) +#define bfin_read_DMA1_BWM_COUNT() bfin_read32(DMA1_BWM_COUNT) +#define bfin_write_DMA1_BWM_COUNT(val) bfin_write32(DMA1_BWM_COUNT, val) +#define bfin_read_DMA1_CURR_BWM_COUNT() bfin_read32(DMA1_CURR_BWM_COUNT) +#define bfin_write_DMA1_CURR_BWM_COUNT(val) bfin_write32(DMA1_CURR_BWM_COUNT, val) + +/* DMA Channel 2 Registers */ + +#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR) +#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val) +#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR) +#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val) +#define bfin_read_DMA2_CONFIG() bfin_read32(DMA2_CONFIG) +#define bfin_write_DMA2_CONFIG(val) bfin_write32(DMA2_CONFIG, val) +#define bfin_read_DMA2_X_COUNT() bfin_read32(DMA2_X_COUNT) +#define bfin_write_DMA2_X_COUNT(val) bfin_write32(DMA2_X_COUNT, val) +#define bfin_read_DMA2_X_MODIFY() bfin_read32(DMA2_X_MODIFY) +#define bfin_write_DMA2_X_MODIFY(val) bfin_write32(DMA2_X_MODIFY, val) +#define bfin_read_DMA2_Y_COUNT() bfin_read32(DMA2_Y_COUNT) +#define bfin_write_DMA2_Y_COUNT(val) bfin_write32(DMA2_Y_COUNT, val) +#define bfin_read_DMA2_Y_MODIFY() bfin_read32(DMA2_Y_MODIFY) +#define bfin_write_DMA2_Y_MODIFY(val) bfin_write32(DMA2_Y_MODIFY, val) +#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR) +#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val) +#define bfin_read_DMA2_PREV_DESC_PTR() bfin_read32(DMA2_PREV_DESC_PTR) +#define bfin_write_DMA2_PREV_DESC_PTR(val) bfin_write32(DMA2_PREV_DESC_PTR, val) +#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR) +#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val) +#define bfin_read_DMA2_IRQ_STATUS() bfin_read32(DMA2_IRQ_STATUS) +#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write32(DMA2_IRQ_STATUS, val) +#define bfin_read_DMA2_CURR_X_COUNT() bfin_read32(DMA2_CURR_X_COUNT) +#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write32(DMA2_CURR_X_COUNT, val) +#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read32(DMA2_CURR_Y_COUNT) +#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write32(DMA2_CURR_Y_COUNT, val) +#define bfin_read_DMA2_BWL_COUNT() bfin_read32(DMA2_BWL_COUNT) +#define bfin_write_DMA2_BWL_COUNT(val) bfin_write32(DMA2_BWL_COUNT, val) +#define bfin_read_DMA2_CURR_BWL_COUNT() bfin_read32(DMA2_CURR_BWL_COUNT) +#define bfin_write_DMA2_CURR_BWL_COUNT(val) bfin_write32(DMA2_CURR_BWL_COUNT, val) +#define bfin_read_DMA2_BWM_COUNT() bfin_read32(DMA2_BWM_COUNT) +#define bfin_write_DMA2_BWM_COUNT(val) bfin_write32(DMA2_BWM_COUNT, val) +#define bfin_read_DMA2_CURR_BWM_COUNT() bfin_read32(DMA2_CURR_BWM_COUNT) +#define bfin_write_DMA2_CURR_BWM_COUNT(val) bfin_write32(DMA2_CURR_BWM_COUNT, val) + +/* DMA Channel 3 Registers */ + +#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR) +#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val) +#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR) +#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val) +#define bfin_read_DMA3_CONFIG() bfin_read32(DMA3_CONFIG) +#define bfin_write_DMA3_CONFIG(val) bfin_write32(DMA3_CONFIG, val) +#define bfin_read_DMA3_X_COUNT() bfin_read32(DMA3_X_COUNT) +#define bfin_write_DMA3_X_COUNT(val) bfin_write32(DMA3_X_COUNT, val) +#define bfin_read_DMA3_X_MODIFY() bfin_read32(DMA3_X_MODIFY) +#define bfin_write_DMA3_X_MODIFY(val) bfin_write32(DMA3_X_MODIFY, val) +#define bfin_read_DMA3_Y_COUNT() bfin_read32(DMA3_Y_COUNT) +#define bfin_write_DMA3_Y_COUNT(val) bfin_write32(DMA3_Y_COUNT, val) +#define bfin_read_DMA3_Y_MODIFY() bfin_read32(DMA3_Y_MODIFY) +#define bfin_write_DMA3_Y_MODIFY(val) bfin_write32(DMA3_Y_MODIFY, val) +#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR) +#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val) +#define bfin_read_DMA3_PREV_DESC_PTR() bfin_read32(DMA3_PREV_DESC_PTR) +#define bfin_write_DMA3_PREV_DESC_PTR(val) bfin_write32(DMA3_PREV_DESC_PTR, val) +#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR) +#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val) +#define bfin_read_DMA3_IRQ_STATUS() bfin_read32(DMA3_IRQ_STATUS) +#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write32(DMA3_IRQ_STATUS, val) +#define bfin_read_DMA3_CURR_X_COUNT() bfin_read32(DMA3_CURR_X_COUNT) +#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write32(DMA3_CURR_X_COUNT, val) +#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read32(DMA3_CURR_Y_COUNT) +#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write32(DMA3_CURR_Y_COUNT, val) +#define bfin_read_DMA3_BWL_COUNT() bfin_read32(DMA3_BWL_COUNT) +#define bfin_write_DMA3_BWL_COUNT(val) bfin_write32(DMA3_BWL_COUNT, val) +#define bfin_read_DMA3_CURR_BWL_COUNT() bfin_read32(DMA3_CURR_BWL_COUNT) +#define bfin_write_DMA3_CURR_BWL_COUNT(val) bfin_write32(DMA3_CURR_BWL_COUNT, val) +#define bfin_read_DMA3_BWM_COUNT() bfin_read32(DMA3_BWM_COUNT) +#define bfin_write_DMA3_BWM_COUNT(val) bfin_write32(DMA3_BWM_COUNT, val) +#define bfin_read_DMA3_CURR_BWM_COUNT() bfin_read32(DMA3_CURR_BWM_COUNT) +#define bfin_write_DMA3_CURR_BWM_COUNT(val) bfin_write32(DMA3_CURR_BWM_COUNT, val) + +/* DMA Channel 4 Registers */ + +#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR) +#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val) +#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR) +#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val) +#define bfin_read_DMA4_CONFIG() bfin_read32(DMA4_CONFIG) +#define bfin_write_DMA4_CONFIG(val) bfin_write32(DMA4_CONFIG, val) +#define bfin_read_DMA4_X_COUNT() bfin_read32(DMA4_X_COUNT) +#define bfin_write_DMA4_X_COUNT(val) bfin_write32(DMA4_X_COUNT, val) +#define bfin_read_DMA4_X_MODIFY() bfin_read32(DMA4_X_MODIFY) +#define bfin_write_DMA4_X_MODIFY(val) bfin_write32(DMA4_X_MODIFY, val) +#define bfin_read_DMA4_Y_COUNT() bfin_read32(DMA4_Y_COUNT) +#define bfin_write_DMA4_Y_COUNT(val) bfin_write32(DMA4_Y_COUNT, val) +#define bfin_read_DMA4_Y_MODIFY() bfin_read32(DMA4_Y_MODIFY) +#define bfin_write_DMA4_Y_MODIFY(val) bfin_write32(DMA4_Y_MODIFY, val) +#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR) +#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val) +#define bfin_read_DMA4_PREV_DESC_PTR() bfin_read32(DMA4_PREV_DESC_PTR) +#define bfin_write_DMA4_PREV_DESC_PTR(val) bfin_write32(DMA4_PREV_DESC_PTR, val) +#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR) +#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val) +#define bfin_read_DMA4_IRQ_STATUS() bfin_read32(DMA4_IRQ_STATUS) +#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write32(DMA4_IRQ_STATUS, val) +#define bfin_read_DMA4_CURR_X_COUNT() bfin_read32(DMA4_CURR_X_COUNT) +#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write32(DMA4_CURR_X_COUNT, val) +#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read32(DMA4_CURR_Y_COUNT) +#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write32(DMA4_CURR_Y_COUNT, val) +#define bfin_read_DMA4_BWL_COUNT() bfin_read32(DMA4_BWL_COUNT) +#define bfin_write_DMA4_BWL_COUNT(val) bfin_write32(DMA4_BWL_COUNT, val) +#define bfin_read_DMA4_CURR_BWL_COUNT() bfin_read32(DMA4_CURR_BWL_COUNT) +#define bfin_write_DMA4_CURR_BWL_COUNT(val) bfin_write32(DMA4_CURR_BWL_COUNT, val) +#define bfin_read_DMA4_BWM_COUNT() bfin_read32(DMA4_BWM_COUNT) +#define bfin_write_DMA4_BWM_COUNT(val) bfin_write32(DMA4_BWM_COUNT, val) +#define bfin_read_DMA4_CURR_BWM_COUNT() bfin_read32(DMA4_CURR_BWM_COUNT) +#define bfin_write_DMA4_CURR_BWM_COUNT(val) bfin_write32(DMA4_CURR_BWM_COUNT, val) + +/* DMA Channel 5 Registers */ + +#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR) +#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val) +#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR) +#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val) +#define bfin_read_DMA5_CONFIG() bfin_read32(DMA5_CONFIG) +#define bfin_write_DMA5_CONFIG(val) bfin_write32(DMA5_CONFIG, val) +#define bfin_read_DMA5_X_COUNT() bfin_read32(DMA5_X_COUNT) +#define bfin_write_DMA5_X_COUNT(val) bfin_write32(DMA5_X_COUNT, val) +#define bfin_read_DMA5_X_MODIFY() bfin_read32(DMA5_X_MODIFY) +#define bfin_write_DMA5_X_MODIFY(val) bfin_write32(DMA5_X_MODIFY, val) +#define bfin_read_DMA5_Y_COUNT() bfin_read32(DMA5_Y_COUNT) +#define bfin_write_DMA5_Y_COUNT(val) bfin_write32(DMA5_Y_COUNT, val) +#define bfin_read_DMA5_Y_MODIFY() bfin_read32(DMA5_Y_MODIFY) +#define bfin_write_DMA5_Y_MODIFY(val) bfin_write32(DMA5_Y_MODIFY, val) +#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR) +#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val) +#define bfin_read_DMA5_PREV_DESC_PTR() bfin_read32(DMA5_PREV_DESC_PTR) +#define bfin_write_DMA5_PREV_DESC_PTR(val) bfin_write32(DMA5_PREV_DESC_PTR, val) +#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR) +#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val) +#define bfin_read_DMA5_IRQ_STATUS() bfin_read32(DMA5_IRQ_STATUS) +#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write32(DMA5_IRQ_STATUS, val) +#define bfin_read_DMA5_CURR_X_COUNT() bfin_read32(DMA5_CURR_X_COUNT) +#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write32(DMA5_CURR_X_COUNT, val) +#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read32(DMA5_CURR_Y_COUNT) +#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write32(DMA5_CURR_Y_COUNT, val) +#define bfin_read_DMA5_BWL_COUNT() bfin_read32(DMA5_BWL_COUNT) +#define bfin_write_DMA5_BWL_COUNT(val) bfin_write32(DMA5_BWL_COUNT, val) +#define bfin_read_DMA5_CURR_BWL_COUNT() bfin_read32(DMA5_CURR_BWL_COUNT) +#define bfin_write_DMA5_CURR_BWL_COUNT(val) bfin_write32(DMA5_CURR_BWL_COUNT, val) +#define bfin_read_DMA5_BWM_COUNT() bfin_read32(DMA5_BWM_COUNT) +#define bfin_write_DMA5_BWM_COUNT(val) bfin_write32(DMA5_BWM_COUNT, val) +#define bfin_read_DMA5_CURR_BWM_COUNT() bfin_read32(DMA5_CURR_BWM_COUNT) +#define bfin_write_DMA5_CURR_BWM_COUNT(val) bfin_write32(DMA5_CURR_BWM_COUNT, val) + +/* DMA Channel 6 Registers */ + +#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR) +#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val) +#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR) +#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val) +#define bfin_read_DMA6_CONFIG() bfin_read32(DMA6_CONFIG) +#define bfin_write_DMA6_CONFIG(val) bfin_write32(DMA6_CONFIG, val) +#define bfin_read_DMA6_X_COUNT() bfin_read32(DMA6_X_COUNT) +#define bfin_write_DMA6_X_COUNT(val) bfin_write32(DMA6_X_COUNT, val) +#define bfin_read_DMA6_X_MODIFY() bfin_read32(DMA6_X_MODIFY) +#define bfin_write_DMA6_X_MODIFY(val) bfin_write32(DMA6_X_MODIFY, val) +#define bfin_read_DMA6_Y_COUNT() bfin_read32(DMA6_Y_COUNT) +#define bfin_write_DMA6_Y_COUNT(val) bfin_write32(DMA6_Y_COUNT, val) +#define bfin_read_DMA6_Y_MODIFY() bfin_read32(DMA6_Y_MODIFY) +#define bfin_write_DMA6_Y_MODIFY(val) bfin_write32(DMA6_Y_MODIFY, val) +#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR) +#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val) +#define bfin_read_DMA6_PREV_DESC_PTR() bfin_read32(DMA6_PREV_DESC_PTR) +#define bfin_write_DMA6_PREV_DESC_PTR(val) bfin_write32(DMA6_PREV_DESC_PTR, val) +#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR) +#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val) +#define bfin_read_DMA6_IRQ_STATUS() bfin_read32(DMA6_IRQ_STATUS) +#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write32(DMA6_IRQ_STATUS, val) +#define bfin_read_DMA6_CURR_X_COUNT() bfin_read32(DMA6_CURR_X_COUNT) +#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write32(DMA6_CURR_X_COUNT, val) +#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read32(DMA6_CURR_Y_COUNT) +#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write32(DMA6_CURR_Y_COUNT, val) +#define bfin_read_DMA6_BWL_COUNT() bfin_read32(DMA6_BWL_COUNT) +#define bfin_write_DMA6_BWL_COUNT(val) bfin_write32(DMA6_BWL_COUNT, val) +#define bfin_read_DMA6_CURR_BWL_COUNT() bfin_read32(DMA6_CURR_BWL_COUNT) +#define bfin_write_DMA6_CURR_BWL_COUNT(val) bfin_write32(DMA6_CURR_BWL_COUNT, val) +#define bfin_read_DMA6_BWM_COUNT() bfin_read32(DMA6_BWM_COUNT) +#define bfin_write_DMA6_BWM_COUNT(val) bfin_write32(DMA6_BWM_COUNT, val) +#define bfin_read_DMA6_CURR_BWM_COUNT() bfin_read32(DMA6_CURR_BWM_COUNT) +#define bfin_write_DMA6_CURR_BWM_COUNT(val) bfin_write32(DMA6_CURR_BWM_COUNT, val) + +/* DMA Channel 7 Registers */ + +#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR) +#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val) +#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR) +#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val) +#define bfin_read_DMA7_CONFIG() bfin_read32(DMA7_CONFIG) +#define bfin_write_DMA7_CONFIG(val) bfin_write32(DMA7_CONFIG, val) +#define bfin_read_DMA7_X_COUNT() bfin_read32(DMA7_X_COUNT) +#define bfin_write_DMA7_X_COUNT(val) bfin_write32(DMA7_X_COUNT, val) +#define bfin_read_DMA7_X_MODIFY() bfin_read32(DMA7_X_MODIFY) +#define bfin_write_DMA7_X_MODIFY(val) bfin_write32(DMA7_X_MODIFY, val) +#define bfin_read_DMA7_Y_COUNT() bfin_read32(DMA7_Y_COUNT) +#define bfin_write_DMA7_Y_COUNT(val) bfin_write32(DMA7_Y_COUNT, val) +#define bfin_read_DMA7_Y_MODIFY() bfin_read32(DMA7_Y_MODIFY) +#define bfin_write_DMA7_Y_MODIFY(val) bfin_write32(DMA7_Y_MODIFY, val) +#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR) +#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val) +#define bfin_read_DMA7_PREV_DESC_PTR() bfin_read32(DMA7_PREV_DESC_PTR) +#define bfin_write_DMA7_PREV_DESC_PTR(val) bfin_write32(DMA7_PREV_DESC_PTR, val) +#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR) +#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val) +#define bfin_read_DMA7_IRQ_STATUS() bfin_read32(DMA7_IRQ_STATUS) +#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write32(DMA7_IRQ_STATUS, val) +#define bfin_read_DMA7_CURR_X_COUNT() bfin_read32(DMA7_CURR_X_COUNT) +#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write32(DMA7_CURR_X_COUNT, val) +#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read32(DMA7_CURR_Y_COUNT) +#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write32(DMA7_CURR_Y_COUNT, val) +#define bfin_read_DMA7_BWL_COUNT() bfin_read32(DMA7_BWL_COUNT) +#define bfin_write_DMA7_BWL_COUNT(val) bfin_write32(DMA7_BWL_COUNT, val) +#define bfin_read_DMA7_CURR_BWL_COUNT() bfin_read32(DMA7_CURR_BWL_COUNT) +#define bfin_write_DMA7_CURR_BWL_COUNT(val) bfin_write32(DMA7_CURR_BWL_COUNT, val) +#define bfin_read_DMA7_BWM_COUNT() bfin_read32(DMA7_BWM_COUNT) +#define bfin_write_DMA7_BWM_COUNT(val) bfin_write32(DMA7_BWM_COUNT, val) +#define bfin_read_DMA7_CURR_BWM_COUNT() bfin_read32(DMA7_CURR_BWM_COUNT) +#define bfin_write_DMA7_CURR_BWM_COUNT(val) bfin_write32(DMA7_CURR_BWM_COUNT, val) + +/* DMA Channel 8 Registers */ + +#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR) +#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val) +#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR) +#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val) +#define bfin_read_DMA8_CONFIG() bfin_read32(DMA8_CONFIG) +#define bfin_write_DMA8_CONFIG(val) bfin_write32(DMA8_CONFIG, val) +#define bfin_read_DMA8_X_COUNT() bfin_read32(DMA8_X_COUNT) +#define bfin_write_DMA8_X_COUNT(val) bfin_write32(DMA8_X_COUNT, val) +#define bfin_read_DMA8_X_MODIFY() bfin_read32(DMA8_X_MODIFY) +#define bfin_write_DMA8_X_MODIFY(val) bfin_write32(DMA8_X_MODIFY, val) +#define bfin_read_DMA8_Y_COUNT() bfin_read32(DMA8_Y_COUNT) +#define bfin_write_DMA8_Y_COUNT(val) bfin_write32(DMA8_Y_COUNT, val) +#define bfin_read_DMA8_Y_MODIFY() bfin_read32(DMA8_Y_MODIFY) +#define bfin_write_DMA8_Y_MODIFY(val) bfin_write32(DMA8_Y_MODIFY, val) +#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR) +#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val) +#define bfin_read_DMA8_PREV_DESC_PTR() bfin_read32(DMA8_PREV_DESC_PTR) +#define bfin_write_DMA8_PREV_DESC_PTR(val) bfin_write32(DMA8_PREV_DESC_PTR, val) +#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR) +#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val) +#define bfin_read_DMA8_IRQ_STATUS() bfin_read32(DMA8_IRQ_STATUS) +#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write32(DMA8_IRQ_STATUS, val) +#define bfin_read_DMA8_CURR_X_COUNT() bfin_read32(DMA8_CURR_X_COUNT) +#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write32(DMA8_CURR_X_COUNT, val) +#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read32(DMA8_CURR_Y_COUNT) +#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write32(DMA8_CURR_Y_COUNT, val) +#define bfin_read_DMA8_BWL_COUNT() bfin_read32(DMA8_BWL_COUNT) +#define bfin_write_DMA8_BWL_COUNT(val) bfin_write32(DMA8_BWL_COUNT, val) +#define bfin_read_DMA8_CURR_BWL_COUNT() bfin_read32(DMA8_CURR_BWL_COUNT) +#define bfin_write_DMA8_CURR_BWL_COUNT(val) bfin_write32(DMA8_CURR_BWL_COUNT, val) +#define bfin_read_DMA8_BWM_COUNT() bfin_read32(DMA8_BWM_COUNT) +#define bfin_write_DMA8_BWM_COUNT(val) bfin_write32(DMA8_BWM_COUNT, val) +#define bfin_read_DMA8_CURR_BWM_COUNT() bfin_read32(DMA8_CURR_BWM_COUNT) +#define bfin_write_DMA8_CURR_BWM_COUNT(val) bfin_write32(DMA8_CURR_BWM_COUNT, val) + +/* DMA Channel 9 Registers */ + +#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR) +#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val) +#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR) +#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val) +#define bfin_read_DMA9_CONFIG() bfin_read32(DMA9_CONFIG) +#define bfin_write_DMA9_CONFIG(val) bfin_write32(DMA9_CONFIG, val) +#define bfin_read_DMA9_X_COUNT() bfin_read32(DMA9_X_COUNT) +#define bfin_write_DMA9_X_COUNT(val) bfin_write32(DMA9_X_COUNT, val) +#define bfin_read_DMA9_X_MODIFY() bfin_read32(DMA9_X_MODIFY) +#define bfin_write_DMA9_X_MODIFY(val) bfin_write32(DMA9_X_MODIFY, val) +#define bfin_read_DMA9_Y_COUNT() bfin_read32(DMA9_Y_COUNT) +#define bfin_write_DMA9_Y_COUNT(val) bfin_write32(DMA9_Y_COUNT, val) +#define bfin_read_DMA9_Y_MODIFY() bfin_read32(DMA9_Y_MODIFY) +#define bfin_write_DMA9_Y_MODIFY(val) bfin_write32(DMA9_Y_MODIFY, val) +#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR) +#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val) +#define bfin_read_DMA9_PREV_DESC_PTR() bfin_read32(DMA9_PREV_DESC_PTR) +#define bfin_write_DMA9_PREV_DESC_PTR(val) bfin_write32(DMA9_PREV_DESC_PTR, val) +#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR) +#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val) +#define bfin_read_DMA9_IRQ_STATUS() bfin_read32(DMA9_IRQ_STATUS) +#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write32(DMA9_IRQ_STATUS, val) +#define bfin_read_DMA9_CURR_X_COUNT() bfin_read32(DMA9_CURR_X_COUNT) +#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write32(DMA9_CURR_X_COUNT, val) +#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read32(DMA9_CURR_Y_COUNT) +#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write32(DMA9_CURR_Y_COUNT, val) +#define bfin_read_DMA9_BWL_COUNT() bfin_read32(DMA9_BWL_COUNT) +#define bfin_write_DMA9_BWL_COUNT(val) bfin_write32(DMA9_BWL_COUNT, val) +#define bfin_read_DMA9_CURR_BWL_COUNT() bfin_read32(DMA9_CURR_BWL_COUNT) +#define bfin_write_DMA9_CURR_BWL_COUNT(val) bfin_write32(DMA9_CURR_BWL_COUNT, val) +#define bfin_read_DMA9_BWM_COUNT() bfin_read32(DMA9_BWM_COUNT) +#define bfin_write_DMA9_BWM_COUNT(val) bfin_write32(DMA9_BWM_COUNT, val) +#define bfin_read_DMA9_CURR_BWM_COUNT() bfin_read32(DMA9_CURR_BWM_COUNT) +#define bfin_write_DMA9_CURR_BWM_COUNT(val) bfin_write32(DMA9_CURR_BWM_COUNT, val) + +/* DMA Channel 10 Registers */ + +#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR) +#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val) +#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR) +#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val) +#define bfin_read_DMA10_CONFIG() bfin_read32(DMA10_CONFIG) +#define bfin_write_DMA10_CONFIG(val) bfin_write32(DMA10_CONFIG, val) +#define bfin_read_DMA10_X_COUNT() bfin_read32(DMA10_X_COUNT) +#define bfin_write_DMA10_X_COUNT(val) bfin_write32(DMA10_X_COUNT, val) +#define bfin_read_DMA10_X_MODIFY() bfin_read32(DMA10_X_MODIFY) +#define bfin_write_DMA10_X_MODIFY(val) bfin_write32(DMA10_X_MODIFY, val) +#define bfin_read_DMA10_Y_COUNT() bfin_read32(DMA10_Y_COUNT) +#define bfin_write_DMA10_Y_COUNT(val) bfin_write32(DMA10_Y_COUNT, val) +#define bfin_read_DMA10_Y_MODIFY() bfin_read32(DMA10_Y_MODIFY) +#define bfin_write_DMA10_Y_MODIFY(val) bfin_write32(DMA10_Y_MODIFY, val) +#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR) +#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val) +#define bfin_read_DMA10_PREV_DESC_PTR() bfin_read32(DMA10_PREV_DESC_PTR) +#define bfin_write_DMA10_PREV_DESC_PTR(val) bfin_write32(DMA10_PREV_DESC_PTR, val) +#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR) +#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val) +#define bfin_read_DMA10_IRQ_STATUS() bfin_read32(DMA10_IRQ_STATUS) +#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write32(DMA10_IRQ_STATUS, val) +#define bfin_read_DMA10_CURR_X_COUNT() bfin_read32(DMA10_CURR_X_COUNT) +#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write32(DMA10_CURR_X_COUNT, val) +#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read32(DMA10_CURR_Y_COUNT) +#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write32(DMA10_CURR_Y_COUNT, val) +#define bfin_read_DMA10_BWL_COUNT() bfin_read32(DMA10_BWL_COUNT) +#define bfin_write_DMA10_BWL_COUNT(val) bfin_write32(DMA10_BWL_COUNT, val) +#define bfin_read_DMA10_CURR_BWL_COUNT() bfin_read32(DMA10_CURR_BWL_COUNT) +#define bfin_write_DMA10_CURR_BWL_COUNT(val) bfin_write32(DMA10_CURR_BWL_COUNT, val) +#define bfin_read_DMA10_BWM_COUNT() bfin_read32(DMA10_BWM_COUNT) +#define bfin_write_DMA10_BWM_COUNT(val) bfin_write32(DMA10_BWM_COUNT, val) +#define bfin_read_DMA10_CURR_BWM_COUNT() bfin_read32(DMA10_CURR_BWM_COUNT) +#define bfin_write_DMA10_CURR_BWM_COUNT(val) bfin_write32(DMA10_CURR_BWM_COUNT, val) + +/* DMA Channel 11 Registers */ + +#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR) +#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val) +#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR) +#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val) +#define bfin_read_DMA11_CONFIG() bfin_read32(DMA11_CONFIG) +#define bfin_write_DMA11_CONFIG(val) bfin_write32(DMA11_CONFIG, val) +#define bfin_read_DMA11_X_COUNT() bfin_read32(DMA11_X_COUNT) +#define bfin_write_DMA11_X_COUNT(val) bfin_write32(DMA11_X_COUNT, val) +#define bfin_read_DMA11_X_MODIFY() bfin_read32(DMA11_X_MODIFY) +#define bfin_write_DMA11_X_MODIFY(val) bfin_write32(DMA11_X_MODIFY, val) +#define bfin_read_DMA11_Y_COUNT() bfin_read32(DMA11_Y_COUNT) +#define bfin_write_DMA11_Y_COUNT(val) bfin_write32(DMA11_Y_COUNT, val) +#define bfin_read_DMA11_Y_MODIFY() bfin_read32(DMA11_Y_MODIFY) +#define bfin_write_DMA11_Y_MODIFY(val) bfin_write32(DMA11_Y_MODIFY, val) +#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR) +#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val) +#define bfin_read_DMA11_PREV_DESC_PTR() bfin_read32(DMA11_PREV_DESC_PTR) +#define bfin_write_DMA11_PREV_DESC_PTR(val) bfin_write32(DMA11_PREV_DESC_PTR, val) +#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR) +#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val) +#define bfin_read_DMA11_IRQ_STATUS() bfin_read32(DMA11_IRQ_STATUS) +#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write32(DMA11_IRQ_STATUS, val) +#define bfin_read_DMA11_CURR_X_COUNT() bfin_read32(DMA11_CURR_X_COUNT) +#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write32(DMA11_CURR_X_COUNT, val) +#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read32(DMA11_CURR_Y_COUNT) +#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write32(DMA11_CURR_Y_COUNT, val) +#define bfin_read_DMA11_BWL_COUNT() bfin_read32(DMA11_BWL_COUNT) +#define bfin_write_DMA11_BWL_COUNT(val) bfin_write32(DMA11_BWL_COUNT, val) +#define bfin_read_DMA11_CURR_BWL_COUNT() bfin_read32(DMA11_CURR_BWL_COUNT) +#define bfin_write_DMA11_CURR_BWL_COUNT(val) bfin_write32(DMA11_CURR_BWL_COUNT, val) +#define bfin_read_DMA11_BWM_COUNT() bfin_read32(DMA11_BWM_COUNT) +#define bfin_write_DMA11_BWM_COUNT(val) bfin_write32(DMA11_BWM_COUNT, val) +#define bfin_read_DMA11_CURR_BWM_COUNT() bfin_read32(DMA11_CURR_BWM_COUNT) +#define bfin_write_DMA11_CURR_BWM_COUNT(val) bfin_write32(DMA11_CURR_BWM_COUNT, val) + +/* DMA Channel 12 Registers */ + +#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_read32(DMA12_NEXT_DESC_PTR) +#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_write32(DMA12_NEXT_DESC_PTR, val) +#define bfin_read_DMA12_START_ADDR() bfin_read32(DMA12_START_ADDR) +#define bfin_write_DMA12_START_ADDR(val) bfin_write32(DMA12_START_ADDR, val) +#define bfin_read_DMA12_CONFIG() bfin_read32(DMA12_CONFIG) +#define bfin_write_DMA12_CONFIG(val) bfin_write32(DMA12_CONFIG, val) +#define bfin_read_DMA12_X_COUNT() bfin_read32(DMA12_X_COUNT) +#define bfin_write_DMA12_X_COUNT(val) bfin_write32(DMA12_X_COUNT, val) +#define bfin_read_DMA12_X_MODIFY() bfin_read32(DMA12_X_MODIFY) +#define bfin_write_DMA12_X_MODIFY(val) bfin_write32(DMA12_X_MODIFY, val) +#define bfin_read_DMA12_Y_COUNT() bfin_read32(DMA12_Y_COUNT) +#define bfin_write_DMA12_Y_COUNT(val) bfin_write32(DMA12_Y_COUNT, val) +#define bfin_read_DMA12_Y_MODIFY() bfin_read32(DMA12_Y_MODIFY) +#define bfin_write_DMA12_Y_MODIFY(val) bfin_write32(DMA12_Y_MODIFY, val) +#define bfin_read_DMA12_CURR_DESC_PTR() bfin_read32(DMA12_CURR_DESC_PTR) +#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_write32(DMA12_CURR_DESC_PTR, val) +#define bfin_read_DMA12_PREV_DESC_PTR() bfin_read32(DMA12_PREV_DESC_PTR) +#define bfin_write_DMA12_PREV_DESC_PTR(val) bfin_write32(DMA12_PREV_DESC_PTR, val) +#define bfin_read_DMA12_CURR_ADDR() bfin_read32(DMA12_CURR_ADDR) +#define bfin_write_DMA12_CURR_ADDR(val) bfin_write32(DMA12_CURR_ADDR, val) +#define bfin_read_DMA12_IRQ_STATUS() bfin_read32(DMA12_IRQ_STATUS) +#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write32(DMA12_IRQ_STATUS, val) +#define bfin_read_DMA12_CURR_X_COUNT() bfin_read32(DMA12_CURR_X_COUNT) +#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write32(DMA12_CURR_X_COUNT, val) +#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read32(DMA12_CURR_Y_COUNT) +#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write32(DMA12_CURR_Y_COUNT, val) +#define bfin_read_DMA12_BWL_COUNT() bfin_read32(DMA12_BWL_COUNT) +#define bfin_write_DMA12_BWL_COUNT(val) bfin_write32(DMA12_BWL_COUNT, val) +#define bfin_read_DMA12_CURR_BWL_COUNT() bfin_read32(DMA12_CURR_BWL_COUNT) +#define bfin_write_DMA12_CURR_BWL_COUNT(val) bfin_write32(DMA12_CURR_BWL_COUNT, val) +#define bfin_read_DMA12_BWM_COUNT() bfin_read32(DMA12_BWM_COUNT) +#define bfin_write_DMA12_BWM_COUNT(val) bfin_write32(DMA12_BWM_COUNT, val) +#define bfin_read_DMA12_CURR_BWM_COUNT() bfin_read32(DMA12_CURR_BWM_COUNT) +#define bfin_write_DMA12_CURR_BWM_COUNT(val) bfin_write32(DMA12_CURR_BWM_COUNT, val) + +/* DMA Channel 13 Registers */ + +#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_read32(DMA13_NEXT_DESC_PTR) +#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_write32(DMA13_NEXT_DESC_PTR, val) +#define bfin_read_DMA13_START_ADDR() bfin_read32(DMA13_START_ADDR) +#define bfin_write_DMA13_START_ADDR(val) bfin_write32(DMA13_START_ADDR, val) +#define bfin_read_DMA13_CONFIG() bfin_read32(DMA13_CONFIG) +#define bfin_write_DMA13_CONFIG(val) bfin_write32(DMA13_CONFIG, val) +#define bfin_read_DMA13_X_COUNT() bfin_read32(DMA13_X_COUNT) +#define bfin_write_DMA13_X_COUNT(val) bfin_write32(DMA13_X_COUNT, val) +#define bfin_read_DMA13_X_MODIFY() bfin_read32(DMA13_X_MODIFY) +#define bfin_write_DMA13_X_MODIFY(val) bfin_write32(DMA13_X_MODIFY, val) +#define bfin_read_DMA13_Y_COUNT() bfin_read32(DMA13_Y_COUNT) +#define bfin_write_DMA13_Y_COUNT(val) bfin_write32(DMA13_Y_COUNT, val) +#define bfin_read_DMA13_Y_MODIFY() bfin_read32(DMA13_Y_MODIFY) +#define bfin_write_DMA13_Y_MODIFY(val) bfin_write32(DMA13_Y_MODIFY, val) +#define bfin_read_DMA13_CURR_DESC_PTR() bfin_read32(DMA13_CURR_DESC_PTR) +#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_write32(DMA13_CURR_DESC_PTR, val) +#define bfin_read_DMA13_PREV_DESC_PTR() bfin_read32(DMA13_PREV_DESC_PTR) +#define bfin_write_DMA13_PREV_DESC_PTR(val) bfin_write32(DMA13_PREV_DESC_PTR, val) +#define bfin_read_DMA13_CURR_ADDR() bfin_read32(DMA13_CURR_ADDR) +#define bfin_write_DMA13_CURR_ADDR(val) bfin_write32(DMA13_CURR_ADDR, val) +#define bfin_read_DMA13_IRQ_STATUS() bfin_read32(DMA13_IRQ_STATUS) +#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write32(DMA13_IRQ_STATUS, val) +#define bfin_read_DMA13_CURR_X_COUNT() bfin_read32(DMA13_CURR_X_COUNT) +#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write32(DMA13_CURR_X_COUNT, val) +#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read32(DMA13_CURR_Y_COUNT) +#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write32(DMA13_CURR_Y_COUNT, val) +#define bfin_read_DMA13_BWL_COUNT() bfin_read32(DMA13_BWL_COUNT) +#define bfin_write_DMA13_BWL_COUNT(val) bfin_write32(DMA13_BWL_COUNT, val) +#define bfin_read_DMA13_CURR_BWL_COUNT() bfin_read32(DMA13_CURR_BWL_COUNT) +#define bfin_write_DMA13_CURR_BWL_COUNT(val) bfin_write32(DMA13_CURR_BWL_COUNT, val) +#define bfin_read_DMA13_BWM_COUNT() bfin_read32(DMA13_BWM_COUNT) +#define bfin_write_DMA13_BWM_COUNT(val) bfin_write32(DMA13_BWM_COUNT, val) +#define bfin_read_DMA13_CURR_BWM_COUNT() bfin_read32(DMA13_CURR_BWM_COUNT) +#define bfin_write_DMA13_CURR_BWM_COUNT(val) bfin_write32(DMA13_CURR_BWM_COUNT, val) + +/* DMA Channel 14 Registers */ + +#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_read32(DMA14_NEXT_DESC_PTR) +#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_write32(DMA14_NEXT_DESC_PTR, val) +#define bfin_read_DMA14_START_ADDR() bfin_read32(DMA14_START_ADDR) +#define bfin_write_DMA14_START_ADDR(val) bfin_write32(DMA14_START_ADDR, val) +#define bfin_read_DMA14_CONFIG() bfin_read32(DMA14_CONFIG) +#define bfin_write_DMA14_CONFIG(val) bfin_write32(DMA14_CONFIG, val) +#define bfin_read_DMA14_X_COUNT() bfin_read32(DMA14_X_COUNT) +#define bfin_write_DMA14_X_COUNT(val) bfin_write32(DMA14_X_COUNT, val) +#define bfin_read_DMA14_X_MODIFY() bfin_read32(DMA14_X_MODIFY) +#define bfin_write_DMA14_X_MODIFY(val) bfin_write32(DMA14_X_MODIFY, val) +#define bfin_read_DMA14_Y_COUNT() bfin_read32(DMA14_Y_COUNT) +#define bfin_write_DMA14_Y_COUNT(val) bfin_write32(DMA14_Y_COUNT, val) +#define bfin_read_DMA14_Y_MODIFY() bfin_read32(DMA14_Y_MODIFY) +#define bfin_write_DMA14_Y_MODIFY(val) bfin_write32(DMA14_Y_MODIFY, val) +#define bfin_read_DMA14_CURR_DESC_PTR() bfin_read32(DMA14_CURR_DESC_PTR) +#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_write32(DMA14_CURR_DESC_PTR, val) +#define bfin_read_DMA14_PREV_DESC_PTR() bfin_read32(DMA14_PREV_DESC_PTR) +#define bfin_write_DMA14_PREV_DESC_PTR(val) bfin_write32(DMA14_PREV_DESC_PTR, val) +#define bfin_read_DMA14_CURR_ADDR() bfin_read32(DMA14_CURR_ADDR) +#define bfin_write_DMA14_CURR_ADDR(val) bfin_write32(DMA14_CURR_ADDR, val) +#define bfin_read_DMA14_IRQ_STATUS() bfin_read32(DMA14_IRQ_STATUS) +#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write32(DMA14_IRQ_STATUS, val) +#define bfin_read_DMA14_CURR_X_COUNT() bfin_read32(DMA14_CURR_X_COUNT) +#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write32(DMA14_CURR_X_COUNT, val) +#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read32(DMA14_CURR_Y_COUNT) +#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write32(DMA14_CURR_Y_COUNT, val) +#define bfin_read_DMA14_BWL_COUNT() bfin_read32(DMA14_BWL_COUNT) +#define bfin_write_DMA14_BWL_COUNT(val) bfin_write32(DMA14_BWL_COUNT, val) +#define bfin_read_DMA14_CURR_BWL_COUNT() bfin_read32(DMA14_CURR_BWL_COUNT) +#define bfin_write_DMA14_CURR_BWL_COUNT(val) bfin_write32(DMA14_CURR_BWL_COUNT, val) +#define bfin_read_DMA14_BWM_COUNT() bfin_read32(DMA14_BWM_COUNT) +#define bfin_write_DMA14_BWM_COUNT(val) bfin_write32(DMA14_BWM_COUNT, val) +#define bfin_read_DMA14_CURR_BWM_COUNT() bfin_read32(DMA14_CURR_BWM_COUNT) +#define bfin_write_DMA14_CURR_BWM_COUNT(val) bfin_write32(DMA14_CURR_BWM_COUNT, val) + +/* DMA Channel 15 Registers */ + +#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_read32(DMA15_NEXT_DESC_PTR) +#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_write32(DMA15_NEXT_DESC_PTR, val) +#define bfin_read_DMA15_START_ADDR() bfin_read32(DMA15_START_ADDR) +#define bfin_write_DMA15_START_ADDR(val) bfin_write32(DMA15_START_ADDR, val) +#define bfin_read_DMA15_CONFIG() bfin_read32(DMA15_CONFIG) +#define bfin_write_DMA15_CONFIG(val) bfin_write32(DMA15_CONFIG, val) +#define bfin_read_DMA15_X_COUNT() bfin_read32(DMA15_X_COUNT) +#define bfin_write_DMA15_X_COUNT(val) bfin_write32(DMA15_X_COUNT, val) +#define bfin_read_DMA15_X_MODIFY() bfin_read32(DMA15_X_MODIFY) +#define bfin_write_DMA15_X_MODIFY(val) bfin_write32(DMA15_X_MODIFY, val) +#define bfin_read_DMA15_Y_COUNT() bfin_read32(DMA15_Y_COUNT) +#define bfin_write_DMA15_Y_COUNT(val) bfin_write32(DMA15_Y_COUNT, val) +#define bfin_read_DMA15_Y_MODIFY() bfin_read32(DMA15_Y_MODIFY) +#define bfin_write_DMA15_Y_MODIFY(val) bfin_write32(DMA15_Y_MODIFY, val) +#define bfin_read_DMA15_CURR_DESC_PTR() bfin_read32(DMA15_CURR_DESC_PTR) +#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_write32(DMA15_CURR_DESC_PTR, val) +#define bfin_read_DMA15_PREV_DESC_PTR() bfin_read32(DMA15_PREV_DESC_PTR) +#define bfin_write_DMA15_PREV_DESC_PTR(val) bfin_write32(DMA15_PREV_DESC_PTR, val) +#define bfin_read_DMA15_CURR_ADDR() bfin_read32(DMA15_CURR_ADDR) +#define bfin_write_DMA15_CURR_ADDR(val) bfin_write32(DMA15_CURR_ADDR, val) +#define bfin_read_DMA15_IRQ_STATUS() bfin_read32(DMA15_IRQ_STATUS) +#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write32(DMA15_IRQ_STATUS, val) +#define bfin_read_DMA15_CURR_X_COUNT() bfin_read32(DMA15_CURR_X_COUNT) +#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write32(DMA15_CURR_X_COUNT, val) +#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read32(DMA15_CURR_Y_COUNT) +#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write32(DMA15_CURR_Y_COUNT, val) +#define bfin_read_DMA15_BWL_COUNT() bfin_read32(DMA15_BWL_COUNT) +#define bfin_write_DMA15_BWL_COUNT(val) bfin_write32(DMA15_BWL_COUNT, val) +#define bfin_read_DMA15_CURR_BWL_COUNT() bfin_read32(DMA15_CURR_BWL_COUNT) +#define bfin_write_DMA15_CURR_BWL_COUNT(val) bfin_write32(DMA15_CURR_BWL_COUNT, val) +#define bfin_read_DMA15_BWM_COUNT() bfin_read32(DMA15_BWM_COUNT) +#define bfin_write_DMA15_BWM_COUNT(val) bfin_write32(DMA15_BWM_COUNT, val) +#define bfin_read_DMA15_CURR_BWM_COUNT() bfin_read32(DMA15_CURR_BWM_COUNT) +#define bfin_write_DMA15_CURR_BWM_COUNT(val) bfin_write32(DMA15_CURR_BWM_COUNT, val) + +/* DMA Channel 16 Registers */ + +#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_read32(DMA16_NEXT_DESC_PTR) +#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_write32(DMA16_NEXT_DESC_PTR, val) +#define bfin_read_DMA16_START_ADDR() bfin_read32(DMA16_START_ADDR) +#define bfin_write_DMA16_START_ADDR(val) bfin_write32(DMA16_START_ADDR, val) +#define bfin_read_DMA16_CONFIG() bfin_read32(DMA16_CONFIG) +#define bfin_write_DMA16_CONFIG(val) bfin_write32(DMA16_CONFIG, val) +#define bfin_read_DMA16_X_COUNT() bfin_read32(DMA16_X_COUNT) +#define bfin_write_DMA16_X_COUNT(val) bfin_write32(DMA16_X_COUNT, val) +#define bfin_read_DMA16_X_MODIFY() bfin_read32(DMA16_X_MODIFY) +#define bfin_write_DMA16_X_MODIFY(val) bfin_write32(DMA16_X_MODIFY, val) +#define bfin_read_DMA16_Y_COUNT() bfin_read32(DMA16_Y_COUNT) +#define bfin_write_DMA16_Y_COUNT(val) bfin_write32(DMA16_Y_COUNT, val) +#define bfin_read_DMA16_Y_MODIFY() bfin_read32(DMA16_Y_MODIFY) +#define bfin_write_DMA16_Y_MODIFY(val) bfin_write32(DMA16_Y_MODIFY, val) +#define bfin_read_DMA16_CURR_DESC_PTR() bfin_read32(DMA16_CURR_DESC_PTR) +#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_write32(DMA16_CURR_DESC_PTR, val) +#define bfin_read_DMA16_PREV_DESC_PTR() bfin_read32(DMA16_PREV_DESC_PTR) +#define bfin_write_DMA16_PREV_DESC_PTR(val) bfin_write32(DMA16_PREV_DESC_PTR, val) +#define bfin_read_DMA16_CURR_ADDR() bfin_read32(DMA16_CURR_ADDR) +#define bfin_write_DMA16_CURR_ADDR(val) bfin_write32(DMA16_CURR_ADDR, val) +#define bfin_read_DMA16_IRQ_STATUS() bfin_read32(DMA16_IRQ_STATUS) +#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write32(DMA16_IRQ_STATUS, val) +#define bfin_read_DMA16_CURR_X_COUNT() bfin_read32(DMA16_CURR_X_COUNT) +#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write32(DMA16_CURR_X_COUNT, val) +#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read32(DMA16_CURR_Y_COUNT) +#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write32(DMA16_CURR_Y_COUNT, val) +#define bfin_read_DMA16_BWL_COUNT() bfin_read32(DMA16_BWL_COUNT) +#define bfin_write_DMA16_BWL_COUNT(val) bfin_write32(DMA16_BWL_COUNT, val) +#define bfin_read_DMA16_CURR_BWL_COUNT() bfin_read32(DMA16_CURR_BWL_COUNT) +#define bfin_write_DMA16_CURR_BWL_COUNT(val) bfin_write32(DMA16_CURR_BWL_COUNT, val) +#define bfin_read_DMA16_BWM_COUNT() bfin_read32(DMA16_BWM_COUNT) +#define bfin_write_DMA16_BWM_COUNT(val) bfin_write32(DMA16_BWM_COUNT, val) +#define bfin_read_DMA16_CURR_BWM_COUNT() bfin_read32(DMA16_CURR_BWM_COUNT) +#define bfin_write_DMA16_CURR_BWM_COUNT(val) bfin_write32(DMA16_CURR_BWM_COUNT, val) + +/* DMA Channel 17 Registers */ + +#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_read32(DMA17_NEXT_DESC_PTR) +#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_write32(DMA17_NEXT_DESC_PTR, val) +#define bfin_read_DMA17_START_ADDR() bfin_read32(DMA17_START_ADDR) +#define bfin_write_DMA17_START_ADDR(val) bfin_write32(DMA17_START_ADDR, val) +#define bfin_read_DMA17_CONFIG() bfin_read32(DMA17_CONFIG) +#define bfin_write_DMA17_CONFIG(val) bfin_write32(DMA17_CONFIG, val) +#define bfin_read_DMA17_X_COUNT() bfin_read32(DMA17_X_COUNT) +#define bfin_write_DMA17_X_COUNT(val) bfin_write32(DMA17_X_COUNT, val) +#define bfin_read_DMA17_X_MODIFY() bfin_read32(DMA17_X_MODIFY) +#define bfin_write_DMA17_X_MODIFY(val) bfin_write32(DMA17_X_MODIFY, val) +#define bfin_read_DMA17_Y_COUNT() bfin_read32(DMA17_Y_COUNT) +#define bfin_write_DMA17_Y_COUNT(val) bfin_write32(DMA17_Y_COUNT, val) +#define bfin_read_DMA17_Y_MODIFY() bfin_read32(DMA17_Y_MODIFY) +#define bfin_write_DMA17_Y_MODIFY(val) bfin_write32(DMA17_Y_MODIFY, val) +#define bfin_read_DMA17_CURR_DESC_PTR() bfin_read32(DMA17_CURR_DESC_PTR) +#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_write32(DMA17_CURR_DESC_PTR, val) +#define bfin_read_DMA17_PREV_DESC_PTR() bfin_read32(DMA17_PREV_DESC_PTR) +#define bfin_write_DMA17_PREV_DESC_PTR(val) bfin_write32(DMA17_PREV_DESC_PTR, val) +#define bfin_read_DMA17_CURR_ADDR() bfin_read32(DMA17_CURR_ADDR) +#define bfin_write_DMA17_CURR_ADDR(val) bfin_write32(DMA17_CURR_ADDR, val) +#define bfin_read_DMA17_IRQ_STATUS() bfin_read32(DMA17_IRQ_STATUS) +#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write32(DMA17_IRQ_STATUS, val) +#define bfin_read_DMA17_CURR_X_COUNT() bfin_read32(DMA17_CURR_X_COUNT) +#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write32(DMA17_CURR_X_COUNT, val) +#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read32(DMA17_CURR_Y_COUNT) +#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write32(DMA17_CURR_Y_COUNT, val) +#define bfin_read_DMA17_BWL_COUNT() bfin_read32(DMA17_BWL_COUNT) +#define bfin_write_DMA17_BWL_COUNT(val) bfin_write32(DMA17_BWL_COUNT, val) +#define bfin_read_DMA17_CURR_BWL_COUNT() bfin_read32(DMA17_CURR_BWL_COUNT) +#define bfin_write_DMA17_CURR_BWL_COUNT(val) bfin_write32(DMA17_CURR_BWL_COUNT, val) +#define bfin_read_DMA17_BWM_COUNT() bfin_read32(DMA17_BWM_COUNT) +#define bfin_write_DMA17_BWM_COUNT(val) bfin_write32(DMA17_BWM_COUNT, val) +#define bfin_read_DMA17_CURR_BWM_COUNT() bfin_read32(DMA17_CURR_BWM_COUNT) +#define bfin_write_DMA17_CURR_BWM_COUNT(val) bfin_write32(DMA17_CURR_BWM_COUNT, val) + +/* DMA Channel 18 Registers */ + +#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_read32(DMA18_NEXT_DESC_PTR) +#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_write32(DMA18_NEXT_DESC_PTR, val) +#define bfin_read_DMA18_START_ADDR() bfin_read32(DMA18_START_ADDR) +#define bfin_write_DMA18_START_ADDR(val) bfin_write32(DMA18_START_ADDR, val) +#define bfin_read_DMA18_CONFIG() bfin_read32(DMA18_CONFIG) +#define bfin_write_DMA18_CONFIG(val) bfin_write32(DMA18_CONFIG, val) +#define bfin_read_DMA18_X_COUNT() bfin_read32(DMA18_X_COUNT) +#define bfin_write_DMA18_X_COUNT(val) bfin_write32(DMA18_X_COUNT, val) +#define bfin_read_DMA18_X_MODIFY() bfin_read32(DMA18_X_MODIFY) +#define bfin_write_DMA18_X_MODIFY(val) bfin_write32(DMA18_X_MODIFY, val) +#define bfin_read_DMA18_Y_COUNT() bfin_read32(DMA18_Y_COUNT) +#define bfin_write_DMA18_Y_COUNT(val) bfin_write32(DMA18_Y_COUNT, val) +#define bfin_read_DMA18_Y_MODIFY() bfin_read32(DMA18_Y_MODIFY) +#define bfin_write_DMA18_Y_MODIFY(val) bfin_write32(DMA18_Y_MODIFY, val) +#define bfin_read_DMA18_CURR_DESC_PTR() bfin_read32(DMA18_CURR_DESC_PTR) +#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_write32(DMA18_CURR_DESC_PTR, val) +#define bfin_read_DMA18_PREV_DESC_PTR() bfin_read32(DMA18_PREV_DESC_PTR) +#define bfin_write_DMA18_PREV_DESC_PTR(val) bfin_write32(DMA18_PREV_DESC_PTR, val) +#define bfin_read_DMA18_CURR_ADDR() bfin_read32(DMA18_CURR_ADDR) +#define bfin_write_DMA18_CURR_ADDR(val) bfin_write32(DMA18_CURR_ADDR, val) +#define bfin_read_DMA18_IRQ_STATUS() bfin_read32(DMA18_IRQ_STATUS) +#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write32(DMA18_IRQ_STATUS, val) +#define bfin_read_DMA18_CURR_X_COUNT() bfin_read32(DMA18_CURR_X_COUNT) +#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write32(DMA18_CURR_X_COUNT, val) +#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read32(DMA18_CURR_Y_COUNT) +#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write32(DMA18_CURR_Y_COUNT, val) +#define bfin_read_DMA18_BWL_COUNT() bfin_read32(DMA18_BWL_COUNT) +#define bfin_write_DMA18_BWL_COUNT(val) bfin_write32(DMA18_BWL_COUNT, val) +#define bfin_read_DMA18_CURR_BWL_COUNT() bfin_read32(DMA18_CURR_BWL_COUNT) +#define bfin_write_DMA18_CURR_BWL_COUNT(val) bfin_write32(DMA18_CURR_BWL_COUNT, val) +#define bfin_read_DMA18_BWM_COUNT() bfin_read32(DMA18_BWM_COUNT) +#define bfin_write_DMA18_BWM_COUNT(val) bfin_write32(DMA18_BWM_COUNT, val) +#define bfin_read_DMA18_CURR_BWM_COUNT() bfin_read32(DMA18_CURR_BWM_COUNT) +#define bfin_write_DMA18_CURR_BWM_COUNT(val) bfin_write32(DMA18_CURR_BWM_COUNT, val) + +/* DMA Channel 19 Registers */ + +#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_read32(DMA19_NEXT_DESC_PTR) +#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_write32(DMA19_NEXT_DESC_PTR, val) +#define bfin_read_DMA19_START_ADDR() bfin_read32(DMA19_START_ADDR) +#define bfin_write_DMA19_START_ADDR(val) bfin_write32(DMA19_START_ADDR, val) +#define bfin_read_DMA19_CONFIG() bfin_read32(DMA19_CONFIG) +#define bfin_write_DMA19_CONFIG(val) bfin_write32(DMA19_CONFIG, val) +#define bfin_read_DMA19_X_COUNT() bfin_read32(DMA19_X_COUNT) +#define bfin_write_DMA19_X_COUNT(val) bfin_write32(DMA19_X_COUNT, val) +#define bfin_read_DMA19_X_MODIFY() bfin_read32(DMA19_X_MODIFY) +#define bfin_write_DMA19_X_MODIFY(val) bfin_write32(DMA19_X_MODIFY, val) +#define bfin_read_DMA19_Y_COUNT() bfin_read32(DMA19_Y_COUNT) +#define bfin_write_DMA19_Y_COUNT(val) bfin_write32(DMA19_Y_COUNT, val) +#define bfin_read_DMA19_Y_MODIFY() bfin_read32(DMA19_Y_MODIFY) +#define bfin_write_DMA19_Y_MODIFY(val) bfin_write32(DMA19_Y_MODIFY, val) +#define bfin_read_DMA19_CURR_DESC_PTR() bfin_read32(DMA19_CURR_DESC_PTR) +#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_write32(DMA19_CURR_DESC_PTR, val) +#define bfin_read_DMA19_PREV_DESC_PTR() bfin_read32(DMA19_PREV_DESC_PTR) +#define bfin_write_DMA19_PREV_DESC_PTR(val) bfin_write32(DMA19_PREV_DESC_PTR, val) +#define bfin_read_DMA19_CURR_ADDR() bfin_read32(DMA19_CURR_ADDR) +#define bfin_write_DMA19_CURR_ADDR(val) bfin_write32(DMA19_CURR_ADDR, val) +#define bfin_read_DMA19_IRQ_STATUS() bfin_read32(DMA19_IRQ_STATUS) +#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write32(DMA19_IRQ_STATUS, val) +#define bfin_read_DMA19_CURR_X_COUNT() bfin_read32(DMA19_CURR_X_COUNT) +#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write32(DMA19_CURR_X_COUNT, val) +#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read32(DMA19_CURR_Y_COUNT) +#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write32(DMA19_CURR_Y_COUNT, val) +#define bfin_read_DMA19_BWL_COUNT() bfin_read32(DMA19_BWL_COUNT) +#define bfin_write_DMA19_BWL_COUNT(val) bfin_write32(DMA19_BWL_COUNT, val) +#define bfin_read_DMA19_CURR_BWL_COUNT() bfin_read32(DMA19_CURR_BWL_COUNT) +#define bfin_write_DMA19_CURR_BWL_COUNT(val) bfin_write32(DMA19_CURR_BWL_COUNT, val) +#define bfin_read_DMA19_BWM_COUNT() bfin_read32(DMA19_BWM_COUNT) +#define bfin_write_DMA19_BWM_COUNT(val) bfin_write32(DMA19_BWM_COUNT, val) +#define bfin_read_DMA19_CURR_BWM_COUNT() bfin_read32(DMA19_CURR_BWM_COUNT) +#define bfin_write_DMA19_CURR_BWM_COUNT(val) bfin_write32(DMA19_CURR_BWM_COUNT, val) + +/* DMA Channel 20 Registers */ + +#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_read32(DMA20_NEXT_DESC_PTR) +#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_write32(DMA20_NEXT_DESC_PTR, val) +#define bfin_read_DMA20_START_ADDR() bfin_read32(DMA20_START_ADDR) +#define bfin_write_DMA20_START_ADDR(val) bfin_write32(DMA20_START_ADDR, val) +#define bfin_read_DMA20_CONFIG() bfin_read32(DMA20_CONFIG) +#define bfin_write_DMA20_CONFIG(val) bfin_write32(DMA20_CONFIG, val) +#define bfin_read_DMA20_X_COUNT() bfin_read32(DMA20_X_COUNT) +#define bfin_write_DMA20_X_COUNT(val) bfin_write32(DMA20_X_COUNT, val) +#define bfin_read_DMA20_X_MODIFY() bfin_read32(DMA20_X_MODIFY) +#define bfin_write_DMA20_X_MODIFY(val) bfin_write32(DMA20_X_MODIFY, val) +#define bfin_read_DMA20_Y_COUNT() bfin_read32(DMA20_Y_COUNT) +#define bfin_write_DMA20_Y_COUNT(val) bfin_write32(DMA20_Y_COUNT, val) +#define bfin_read_DMA20_Y_MODIFY() bfin_read32(DMA20_Y_MODIFY) +#define bfin_write_DMA20_Y_MODIFY(val) bfin_write32(DMA20_Y_MODIFY, val) +#define bfin_read_DMA20_CURR_DESC_PTR() bfin_read32(DMA20_CURR_DESC_PTR) +#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_write32(DMA20_CURR_DESC_PTR, val) +#define bfin_read_DMA20_PREV_DESC_PTR() bfin_read32(DMA20_PREV_DESC_PTR) +#define bfin_write_DMA20_PREV_DESC_PTR(val) bfin_write32(DMA20_PREV_DESC_PTR, val) +#define bfin_read_DMA20_CURR_ADDR() bfin_read32(DMA20_CURR_ADDR) +#define bfin_write_DMA20_CURR_ADDR(val) bfin_write32(DMA20_CURR_ADDR, val) +#define bfin_read_DMA20_IRQ_STATUS() bfin_read32(DMA20_IRQ_STATUS) +#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write32(DMA20_IRQ_STATUS, val) +#define bfin_read_DMA20_CURR_X_COUNT() bfin_read32(DMA20_CURR_X_COUNT) +#define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write32(DMA20_CURR_X_COUNT, val) +#define bfin_read_DMA20_CURR_Y_COUNT() bfin_read32(DMA20_CURR_Y_COUNT) +#define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write32(DMA20_CURR_Y_COUNT, val) +#define bfin_read_DMA20_BWL_COUNT() bfin_read32(DMA20_BWL_COUNT) +#define bfin_write_DMA20_BWL_COUNT(val) bfin_write32(DMA20_BWL_COUNT, val) +#define bfin_read_DMA20_CURR_BWL_COUNT() bfin_read32(DMA20_CURR_BWL_COUNT) +#define bfin_write_DMA20_CURR_BWL_COUNT(val) bfin_write32(DMA20_CURR_BWL_COUNT, val) +#define bfin_read_DMA20_BWM_COUNT() bfin_read32(DMA20_BWM_COUNT) +#define bfin_write_DMA20_BWM_COUNT(val) bfin_write32(DMA20_BWM_COUNT, val) +#define bfin_read_DMA20_CURR_BWM_COUNT() bfin_read32(DMA20_CURR_BWM_COUNT) +#define bfin_write_DMA20_CURR_BWM_COUNT(val) bfin_write32(DMA20_CURR_BWM_COUNT, val) + + +/* MDMA Stream 0 Registers (DMA Channel 21 and 22) */ + +#define bfin_read_MDMA0_DEST_CRC0_NEXT_DESC_PTR() bfin_read32(MDMA0_DEST_CRC0_NEXT_DESC_PTR) +#define bfin_write_MDMA0_DEST_CRC0_NEXT_DESC_PTR(val) bfin_write32(MDMA0_DEST_CRC0_NEXT_DESC_PTR, val) +#define bfin_read_MDMA0_DEST_CRC0_START_ADDR() bfin_read32(MDMA0_DEST_CRC0_START_ADDR) +#define bfin_write_MDMA0_DEST_CRC0_START_ADDR(val) bfin_write32(MDMA0_DEST_CRC0_START_ADDR, val) +#define bfin_read_MDMA0_DEST_CRC0_CONFIG() bfin_read32(MDMA0_DEST_CRC0_CONFIG) +#define bfin_write_MDMA0_DEST_CRC0_CONFIG(val) bfin_write32(MDMA0_DEST_CRC0_CONFIG, val) +#define bfin_read_MDMA0_DEST_CRC0_X_COUNT() bfin_read32(MDMA0_DEST_CRC0_X_COUNT) +#define bfin_write_MDMA0_DEST_CRC0_X_COUNT(val) bfin_write32(MDMA0_DEST_CRC0_X_COUNT, val) +#define bfin_read_MDMA0_DEST_CRC0_X_MODIFY() bfin_read32(MDMA0_DEST_CRC0_X_MODIFY) +#define bfin_write_MDMA0_DEST_CRC0_X_MODIFY(val) bfin_write32(MDMA0_DEST_CRC0_X_MODIFY, val) +#define bfin_read_MDMA0_DEST_CRC0_Y_COUNT() bfin_read32(MDMA0_DEST_CRC0_Y_COUNT) +#define bfin_write_MDMA0_DEST_CRC0_Y_COUNT(val) bfin_write32(MDMA0_DEST_CRC0_Y_COUNT, val) +#define bfin_read_MDMA0_DEST_CRC0_Y_MODIFY() bfin_read32(MDMA0_DEST_CRC0_Y_MODIFY) +#define bfin_write_MDMA0_DEST_CRC0_Y_MODIFY(val) bfin_write32(MDMA0_DEST_CRC0_Y_MODIFY, val) +#define bfin_read_MDMA0_DEST_CRC0_CURR_DESC_PTR() bfin_read32(MDMA0_DEST_CRC0_CURR_DESC_PTR) +#define bfin_write_MDMA0_DEST_CRC0_CURR_DESC_PTR(val) bfin_write32(MDMA0_DEST_CRC0_CURR_DESC_PTR, val) +#define bfin_read_MDMA0_DEST_CRC0_PREV_DESC_PTR() bfin_read32(MDMA0_DEST_CRC0_PREV_DESC_PTR) +#define bfin_write_MDMA0_DEST_CRC0_PREV_DESC_PTR(val) bfin_write32(MDMA0_DEST_CRC0_PREV_DESC_PTR, val) +#define bfin_read_MDMA0_DEST_CRC0_CURR_ADDR() bfin_read32(MDMA0_DEST_CRC0_CURR_ADDR) +#define bfin_write_MDMA0_DEST_CRC0_CURR_ADDR(val) bfin_write32(MDMA0_DEST_CRC0_CURR_ADDR, val) +#define bfin_read_MDMA0_DEST_CRC0_IRQ_STATUS() bfin_read32(MDMA0_DEST_CRC0_IRQ_STATUS) +#define bfin_write_MDMA0_DEST_CRC0_IRQ_STATUS(val) bfin_write32(MDMA0_DEST_CRC0_IRQ_STATUS, val) +#define bfin_read_MDMA0_DEST_CRC0_CURR_X_COUNT() bfin_read32(MDMA0_DEST_CRC0_CURR_X_COUNT) +#define bfin_write_MDMA0_DEST_CRC0_CURR_X_COUNT(val) bfin_write32(MDMA0_DEST_CRC0_CURR_X_COUNT, val) +#define bfin_read_MDMA0_DEST_CRC0_CURR_Y_COUNT() bfin_read32(MDMA0_DEST_CRC0_CURR_Y_COUNT) +#define bfin_write_MDMA0_DEST_CRC0_CURR_Y_COUNT(val) bfin_write32(MDMA0_DEST_CRC0_CURR_Y_COUNT, val) +#define bfin_read_MDMA0_SRC_CRC0_NEXT_DESC_PTR() bfin_read32(MDMA0_SRC_CRC0_NEXT_DESC_PTR) +#define bfin_write_MDMA0_SRC_CRC0_NEXT_DESC_PTR(val) bfin_write32(MDMA0_SRC_CRC0_NEXT_DESC_PTR, val) +#define bfin_read_MDMA0_SRC_CRC0_START_ADDR() bfin_read32(MDMA0_SRC_CRC0_START_ADDR) +#define bfin_write_MDMA0_SRC_CRC0_START_ADDR(val) bfin_write32(MDMA0_SRC_CRC0_START_ADDR, val) +#define bfin_read_MDMA0_SRC_CRC0_CONFIG() bfin_read32(MDMA0_SRC_CRC0_CONFIG) +#define bfin_write_MDMA0_SRC_CRC0_CONFIG(val) bfin_write32(MDMA0_SRC_CRC0_CONFIG, val) +#define bfin_read_MDMA0_SRC_CRC0_X_COUNT() bfin_read32(MDMA0_SRC_CRC0_X_COUNT) +#define bfin_write_MDMA0_SRC_CRC0_X_COUNT(val) bfin_write32(MDMA0_SRC_CRC0_X_COUNT, val) +#define bfin_read_MDMA0_SRC_CRC0_X_MODIFY() bfin_read32(MDMA0_SRC_CRC0_X_MODIFY) +#define bfin_write_MDMA0_SRC_CRC0_X_MODIFY(val) bfin_write32(MDMA0_SRC_CRC0_X_MODIFY, val) +#define bfin_read_MDMA0_SRC_CRC0_Y_COUNT() bfin_read32(MDMA0_SRC_CRC0_Y_COUNT) +#define bfin_write_MDMA0_SRC_CRC0_Y_COUNT(val) bfin_write32(MDMA0_SRC_CRC0_Y_COUNT, val) +#define bfin_read_MDMA0_SRC_CRC0_Y_MODIFY() bfin_read32(MDMA0_SRC_CRC0_Y_MODIFY) +#define bfin_write_MDMA0_SRC_CRC0_Y_MODIFY(val) bfin_write32(MDMA0_SRC_CRC0_Y_MODIFY, val) +#define bfin_read_MDMA0_SRC_CRC0_CURR_DESC_PTR() bfin_read32(MDMA0_SRC_CRC0_CURR_DESC_PTR) +#define bfin_write_MDMA0_SRC_CRC0_CURR_DESC_PTR(val) bfin_write32(MDMA0_SRC_CRC0_CURR_DESC_PTR, val) +#define bfin_read_MDMA0_SRC_CRC0_PREV_DESC_PTR() bfin_read32(MDMA0_SRC_CRC0_PREV_DESC_PTR) +#define bfin_write_MDMA0_SRC_CRC0_PREV_DESC_PTR(val) bfin_write32(MDMA0_SRC_CRC0_PREV_DESC_PTR, val) +#define bfin_read_MDMA0_SRC_CRC0_CURR_ADDR() bfin_read32(MDMA0_SRC_CRC0_CURR_ADDR) +#define bfin_write_MDMA0_SRC_CRC0_CURR_ADDR(val) bfin_write32(MDMA0_SRC_CRC0_CURR_ADDR, val) +#define bfin_read_MDMA0_SRC_CRC0_IRQ_STATUS() bfin_read32(MDMA0_SRC_CRC0_IRQ_STATUS) +#define bfin_write_MDMA0_SRC_CRC0_IRQ_STATUS(val) bfin_write32(MDMA0_SRC_CRC0_IRQ_STATUS, val) +#define bfin_read_MDMA0_SRC_CRC0_CURR_X_COUNT() bfin_read32(MDMA0_SRC_CRC0_CURR_X_COUNT) +#define bfin_write_MDMA0_SRC_CRC0_CURR_X_COUNT(val) bfin_write32(MDMA0_SRC_CRC0_CURR_X_COUNT, val) +#define bfin_read_MDMA0_SRC_CRC0_CURR_Y_COUNT() bfin_read32(MDMA0_SRC_CRC0_CURR_Y_COUNT) +#define bfin_write_MDMA0_SRC_CRC0_CURR_Y_COUNT(val) bfin_write32(MDMA0_SRC_CRC0_CURR_Y_COUNT, val) + +/* MDMA Stream 1 Registers (DMA Channel 23 and 24) */ + +#define bfin_read_MDMA1_DEST_CRC1_NEXT_DESC_PTR() bfin_read32(MDMA1_DEST_CRC1_NEXT_DESC_PTR) +#define bfin_write_MDMA1_DEST_CRC1_NEXT_DESC_PTR(val) bfin_write32(MDMA1_DEST_CRC1_NEXT_DESC_PTR, val) +#define bfin_read_MDMA1_DEST_CRC1_START_ADDR() bfin_read32(MDMA1_DEST_CRC1_START_ADDR) +#define bfin_write_MDMA1_DEST_CRC1_START_ADDR(val) bfin_write32(MDMA1_DEST_CRC1_START_ADDR, val) +#define bfin_read_MDMA1_DEST_CRC1_CONFIG() bfin_read32(MDMA1_DEST_CRC1_CONFIG) +#define bfin_write_MDMA1_DEST_CRC1_CONFIG(val) bfin_write32(MDMA1_DEST_CRC1_CONFIG, val) +#define bfin_read_MDMA1_DEST_CRC1_X_COUNT() bfin_read32(MDMA1_DEST_CRC1_X_COUNT) +#define bfin_write_MDMA1_DEST_CRC1_X_COUNT(val) bfin_write32(MDMA1_DEST_CRC1_X_COUNT, val) +#define bfin_read_MDMA1_DEST_CRC1_X_MODIFY() bfin_read32(MDMA1_DEST_CRC1_X_MODIFY) +#define bfin_write_MDMA1_DEST_CRC1_X_MODIFY(val) bfin_write32(MDMA1_DEST_CRC1_X_MODIFY, val) +#define bfin_read_MDMA1_DEST_CRC1_Y_COUNT() bfin_read32(MDMA1_DEST_CRC1_Y_COUNT) +#define bfin_write_MDMA1_DEST_CRC1_Y_COUNT(val) bfin_write32(MDMA1_DEST_CRC1_Y_COUNT, val) +#define bfin_read_MDMA1_DEST_CRC1_Y_MODIFY() bfin_read32(MDMA1_DEST_CRC1_Y_MODIFY) +#define bfin_write_MDMA1_DEST_CRC1_Y_MODIFY(val) bfin_write32(MDMA1_DEST_CRC1_Y_MODIFY, val) +#define bfin_read_MDMA1_DEST_CRC1_CURR_DESC_PTR() bfin_read32(MDMA1_DEST_CRC1_CURR_DESC_PTR) +#define bfin_write_MDMA1_DEST_CRC1_CURR_DESC_PTR(val) bfin_write32(MDMA1_DEST_CRC1_CURR_DESC_PTR, val) +#define bfin_read_MDMA1_DEST_CRC1_PREV_DESC_PTR() bfin_read32(MDMA1_DEST_CRC1_PREV_DESC_PTR) +#define bfin_write_MDMA1_DEST_CRC1_PREV_DESC_PTR(val) bfin_write32(MDMA1_DEST_CRC1_PREV_DESC_PTR, val) +#define bfin_read_MDMA1_DEST_CRC1_CURR_ADDR() bfin_read32(MDMA1_DEST_CRC1_CURR_ADDR) +#define bfin_write_MDMA1_DEST_CRC1_CURR_ADDR(val) bfin_write32(MDMA1_DEST_CRC1_CURR_ADDR, val) +#define bfin_read_MDMA1_DEST_CRC1_IRQ_STATUS() bfin_read32(MDMA1_DEST_CRC1_IRQ_STATUS) +#define bfin_write_MDMA1_DEST_CRC1_IRQ_STATUS(val) bfin_write32(MDMA1_DEST_CRC1_IRQ_STATUS, val) +#define bfin_read_MDMA1_DEST_CRC1_CURR_X_COUNT() bfin_read32(MDMA1_DEST_CRC1_CURR_X_COUNT) +#define bfin_write_MDMA1_DEST_CRC1_CURR_X_COUNT(val) bfin_write32(MDMA1_DEST_CRC1_CURR_X_COUNT, val) +#define bfin_read_MDMA1_DEST_CRC1_CURR_Y_COUNT() bfin_read32(MDMA1_DEST_CRC1_CURR_Y_COUNT) +#define bfin_write_MDMA1_DEST_CRC1_CURR_Y_COUNT(val) bfin_write32(MDMA1_DEST_CRC1_CURR_Y_COUNT, val) +#define bfin_read_MDMA1_SRC_CRC1_NEXT_DESC_PTR() bfin_read32(MDMA1_SRC_CRC1_NEXT_DESC_PTR) +#define bfin_write_MDMA1_SRC_CRC1_NEXT_DESC_PTR(val) bfin_write32(MDMA1_SRC_CRC1_NEXT_DESC_PTR, val) +#define bfin_read_MDMA1_SRC_CRC1_START_ADDR() bfin_read32(MDMA1_SRC_CRC1_START_ADDR) +#define bfin_write_MDMA1_SRC_CRC1_START_ADDR(val) bfin_write32(MDMA1_SRC_CRC1_START_ADDR, val) +#define bfin_read_MDMA1_SRC_CRC1_CONFIG() bfin_read32(MDMA1_SRC_CRC1_CONFIG) +#define bfin_write_MDMA1_SRC_CRC1_CONFIG(val) bfin_write32(MDMA1_SRC_CRC1_CONFIG, val) +#define bfin_read_MDMA1_SRC_CRC1_X_COUNT() bfin_read32(MDMA1_SRC_CRC1_X_COUNT) +#define bfin_write_MDMA1_SRC_CRC1_X_COUNT(val) bfin_write32(MDMA1_SRC_CRC1_X_COUNT, val) +#define bfin_read_MDMA1_SRC_CRC1_X_MODIFY() bfin_read32(MDMA1_SRC_CRC1_X_MODIFY) +#define bfin_write_MDMA1_SRC_CRC1_X_MODIFY(val) bfin_write32(MDMA1_SRC_CRC1_X_MODIFY, val) +#define bfin_read_MDMA1_SRC_CRC1_Y_COUNT() bfin_read32(MDMA1_SRC_CRC1_Y_COUNT) +#define bfin_write_MDMA1_SRC_CRC1_Y_COUNT(val) bfin_write32(MDMA1_SRC_CRC1_Y_COUNT, val) +#define bfin_read_MDMA1_SRC_CRC1_Y_MODIFY() bfin_read32(MDMA1_SRC_CRC1_Y_MODIFY) +#define bfin_write_MDMA1_SRC_CRC1_Y_MODIFY(val) bfin_write32(MDMA1_SRC_CRC1_Y_MODIFY, val) +#define bfin_read_MDMA1_SRC_CRC1_CURR_DESC_PTR() bfin_read32(MDMA1_SRC_CRC1_CURR_DESC_PTR) +#define bfin_write_MDMA1_SRC_CRC1_CURR_DESC_PTR(val) bfin_write32(MDMA1_SRC_CRC1_CURR_DESC_PTR, val) +#define bfin_read_MDMA1_SRC_CRC1_PREV_DESC_PTR() bfin_read32(MDMA1_SRC_CRC1_PREV_DESC_PTR) +#define bfin_write_MDMA1_SRC_CRC1_PREV_DESC_PTR(val) bfin_write32(MDMA1_SRC_CRC1_PREV_DESC_PTR, val) +#define bfin_read_MDMA1_SRC_CRC1_CURR_ADDR() bfin_read32(MDMA1_SRC_CRC1_CURR_ADDR) +#define bfin_write_MDMA1_SRC_CRC1_CURR_ADDR(val) bfin_write32(MDMA1_SRC_CRC1_CURR_ADDR, val) +#define bfin_read_MDMA1_SRC_CRC1_IRQ_STATUS() bfin_read32(MDMA1_SRC_CRC1_IRQ_STATUS) +#define bfin_write_MDMA1_SRC_CRC1_IRQ_STATUS(val) bfin_write32(MDMA1_SRC_CRC1_IRQ_STATUS, val) +#define bfin_read_MDMA1_SRC_CRC1_CURR_X_COUNT() bfin_read32(MDMA1_SRC_CRC1_CURR_X_COUNT) +#define bfin_write_MDMA1_SRC_CRC1_CURR_X_COUNT(val) bfin_write32(MDMA1_SRC_CRC1_CURR_X_COUNT, val) +#define bfin_read_MDMA1_SRC_CRC1_CURR_Y_COUNT() bfin_read32(MDMA1_SRC_CRC1_CURR_Y_COUNT) +#define bfin_write_MDMA1_SRC_CRC1_CURR_Y_COUNT(val) bfin_write32(MDMA1_SRC_CRC1_CURR_Y_COUNT, val) + + +/* MDMA Stream 2 Registers (DMA Channel 25 and 26) */ + +#define bfin_read_MDMA2_DEST_NEXT_DESC_PTR() bfin_read32(MDMA2_DEST_NEXT_DESC_PTR) +#define bfin_write_MDMA2_DEST_NEXT_DESC_PTR(val) bfin_write32(MDMA2_DEST_NEXT_DESC_PTR, val) +#define bfin_read_MDMA2_DEST_START_ADDR() bfin_read32(MDMA2_DEST_START_ADDR) +#define bfin_write_MDMA2_DEST_START_ADDR(val) bfin_write32(MDMA2_DEST_START_ADDR, val) +#define bfin_read_MDMA2_DEST_CONFIG() bfin_read32(MDMA2_DEST_CONFIG) +#define bfin_write_MDMA2_DEST_CONFIG(val) bfin_write32(MDMA2_DEST_CONFIG, val) +#define bfin_read_MDMA2_DEST_X_COUNT() bfin_read32(MDMA2_DEST_X_COUNT) +#define bfin_write_MDMA2_DEST_X_COUNT(val) bfin_write32(MDMA2_DEST_X_COUNT, val) +#define bfin_read_MDMA2_DEST_X_MODIFY() bfin_read32(MDMA2_DEST_X_MODIFY) +#define bfin_write_MDMA2_DEST_X_MODIFY(val) bfin_write32(MDMA2_DEST_X_MODIFY, val) +#define bfin_read_MDMA2_DEST_Y_COUNT() bfin_read32(MDMA2_DEST_Y_COUNT) +#define bfin_write_MDMA2_DEST_Y_COUNT(val) bfin_write32(MDMA2_DEST_Y_COUNT, val) +#define bfin_read_MDMA2_DEST_Y_MODIFY() bfin_read32(MDMA2_DEST_Y_MODIFY) +#define bfin_write_MDMA2_DEST_Y_MODIFY(val) bfin_write32(MDMA2_DEST_Y_MODIFY, val) +#define bfin_read_MDMA2_DEST_CURR_DESC_PTR() bfin_read32(MDMA2_DEST_CURR_DESC_PTR) +#define bfin_write_MDMA2_DEST_CURR_DESC_PTR(val) bfin_write32(MDMA2_DEST_CURR_DESC_PTR, val) +#define bfin_read_MDMA2_DEST_PREV_DESC_PTR() bfin_read32(MDMA2_DEST_PREV_DESC_PTR) +#define bfin_write_MDMA2_DEST_PREV_DESC_PTR(val) bfin_write32(MDMA2_DEST_PREV_DESC_PTR, val) +#define bfin_read_MDMA2_DEST_CURR_ADDR() bfin_read32(MDMA2_DEST_CURR_ADDR) +#define bfin_write_MDMA2_DEST_CURR_ADDR(val) bfin_write32(MDMA2_DEST_CURR_ADDR, val) +#define bfin_read_MDMA2_DEST_IRQ_STATUS() bfin_read32(MDMA2_DEST_IRQ_STATUS) +#define bfin_write_MDMA2_DEST_IRQ_STATUS(val) bfin_write32(MDMA2_DEST_IRQ_STATUS, val) +#define bfin_read_MDMA2_DEST_CURR_X_COUNT() bfin_read32(MDMA2_DEST_CURR_X_COUNT) +#define bfin_write_MDMA2_DEST_CURR_X_COUNT(val) bfin_write32(MDMA2_DEST_CURR_X_COUNT, val) +#define bfin_read_MDMA2_DEST_CURR_Y_COUNT() bfin_read32(MDMA2_DEST_CURR_Y_COUNT) +#define bfin_write_MDMA2_DEST_CURR_Y_COUNT(val) bfin_write32(MDMA2_DEST_CURR_Y_COUNT, val) +#define bfin_read_MDMA2_SRC_NEXT_DESC_PTR() bfin_read32(MDMA2_SRC_NEXT_DESC_PTR) +#define bfin_write_MDMA2_SRC_NEXT_DESC_PTR(val) bfin_write32(MDMA2_SRC_NEXT_DESC_PTR, val) +#define bfin_read_MDMA2_SRC_START_ADDR() bfin_read32(MDMA2_SRC_START_ADDR) +#define bfin_write_MDMA2_SRC_START_ADDR(val) bfin_write32(MDMA2_SRC_START_ADDR, val) +#define bfin_read_MDMA2_SRC_CONFIG() bfin_read32(MDMA2_SRC_CONFIG) +#define bfin_write_MDMA2_SRC_CONFIG(val) bfin_write32(MDMA2_SRC_CONFIG, val) +#define bfin_read_MDMA2_SRC_X_COUNT() bfin_read32(MDMA2_SRC_X_COUNT) +#define bfin_write_MDMA2_SRC_X_COUNT(val) bfin_write32(MDMA2_SRC_X_COUNT, val) +#define bfin_read_MDMA2_SRC_X_MODIFY() bfin_read32(MDMA2_SRC_X_MODIFY) +#define bfin_write_MDMA2_SRC_X_MODIFY(val) bfin_write32(MDMA2_SRC_X_MODIFY, val) +#define bfin_read_MDMA2_SRC_Y_COUNT() bfin_read32(MDMA2_SRC_Y_COUNT) +#define bfin_write_MDMA2_SRC_Y_COUNT(val) bfin_write32(MDMA2_SRC_Y_COUNT, val) +#define bfin_read_MDMA2_SRC_Y_MODIFY() bfin_read32(MDMA2_SRC_Y_MODIFY) +#define bfin_write_MDMA2_SRC_Y_MODIFY(val) bfin_write32(MDMA2_SRC_Y_MODIFY, val) +#define bfin_read_MDMA2_SRC_CURR_DESC_PTR() bfin_read32(MDMA2_SRC_CURR_DESC_PTR) +#define bfin_write_MDMA2_SRC_CURR_DESC_PTR(val) bfin_write32(MDMA2_SRC_CURR_DESC_PTR, val) +#define bfin_read_MDMA2_SRC_PREV_DESC_PTR() bfin_read32(MDMA2_SRC_PREV_DESC_PTR) +#define bfin_write_MDMA2_SRC_PREV_DESC_PTR(val) bfin_write32(MDMA2_SRC_PREV_DESC_PTR, val) +#define bfin_read_MDMA2_SRC_CURR_ADDR() bfin_read32(MDMA2_SRC_CURR_ADDR) +#define bfin_write_MDMA2_SRC_CURR_ADDR(val) bfin_write32(MDMA2_SRC_CURR_ADDR, val) +#define bfin_read_MDMA2_SRC_IRQ_STATUS() bfin_read32(MDMA2_SRC_IRQ_STATUS) +#define bfin_write_MDMA2_SRC_IRQ_STATUS(val) bfin_write32(MDMA2_SRC_IRQ_STATUS, val) +#define bfin_read_MDMA2_SRC_CURR_X_COUNT() bfin_read32(MDMA2_SRC_CURR_X_COUNT) +#define bfin_write_MDMA2_SRC_CURR_X_COUNT(val) bfin_write32(MDMA2_SRC_CURR_X_COUNT, val) +#define bfin_read_MDMA2_SRC_CURR_Y_COUNT() bfin_read32(MDMA2_SRC_CURR_Y_COUNT) +#define bfin_write_MDMA2_SRC_CURR_Y_COUNT(val) bfin_write32(MDMA2_SRC_CURR_Y_COUNT, val) + +/* MDMA Stream 3 Registers (DMA Channel 27 and 28) */ + +#define bfin_read_MDMA3_DEST_NEXT_DESC_PTR() bfin_read32(MDMA3_DEST_NEXT_DESC_PTR) +#define bfin_write_MDMA3_DEST_NEXT_DESC_PTR(val) bfin_write32(MDMA3_DEST_NEXT_DESC_PTR, val) +#define bfin_read_MDMA3_DEST_START_ADDR() bfin_read32(MDMA3_DEST_START_ADDR) +#define bfin_write_MDMA3_DEST_START_ADDR(val) bfin_write32(MDMA3_DEST_START_ADDR, val) +#define bfin_read_MDMA3_DEST_CONFIG() bfin_read32(MDMA3_DEST_CONFIG) +#define bfin_write_MDMA3_DEST_CONFIG(val) bfin_write32(MDMA3_DEST_CONFIG, val) +#define bfin_read_MDMA3_DEST_X_COUNT() bfin_read32(MDMA3_DEST_X_COUNT) +#define bfin_write_MDMA3_DEST_X_COUNT(val) bfin_write32(MDMA3_DEST_X_COUNT, val) +#define bfin_read_MDMA3_DEST_X_MODIFY() bfin_read32(MDMA3_DEST_X_MODIFY) +#define bfin_write_MDMA3_DEST_X_MODIFY(val) bfin_write32(MDMA3_DEST_X_MODIFY, val) +#define bfin_read_MDMA3_DEST_Y_COUNT() bfin_read32(MDMA3_DEST_Y_COUNT) +#define bfin_write_MDMA3_DEST_Y_COUNT(val) bfin_write32(MDMA3_DEST_Y_COUNT, val) +#define bfin_read_MDMA3_DEST_Y_MODIFY() bfin_read32(MDMA3_DEST_Y_MODIFY) +#define bfin_write_MDMA3_DEST_Y_MODIFY(val) bfin_write32(MDMA3_DEST_Y_MODIFY, val) +#define bfin_read_MDMA3_DEST_CURR_DESC_PTR() bfin_read32(MDMA3_DEST_CURR_DESC_PTR) +#define bfin_write_MDMA3_DEST_CURR_DESC_PTR(val) bfin_write32(MDMA3_DEST_CURR_DESC_PTR, val) +#define bfin_read_MDMA3_DEST_PREV_DESC_PTR() bfin_read32(MDMA3_DEST_PREV_DESC_PTR) +#define bfin_write_MDMA3_DEST_PREV_DESC_PTR(val) bfin_write32(MDMA3_DEST_PREV_DESC_PTR, val) +#define bfin_read_MDMA3_DEST_CURR_ADDR() bfin_read32(MDMA3_DEST_CURR_ADDR) +#define bfin_write_MDMA3_DEST_CURR_ADDR(val) bfin_write32(MDMA3_DEST_CURR_ADDR, val) +#define bfin_read_MDMA3_DEST_IRQ_STATUS() bfin_read32(MDMA3_DEST_IRQ_STATUS) +#define bfin_write_MDMA3_DEST_IRQ_STATUS(val) bfin_write32(MDMA3_DEST_IRQ_STATUS, val) +#define bfin_read_MDMA3_DEST_CURR_X_COUNT() bfin_read32(MDMA3_DEST_CURR_X_COUNT) +#define bfin_write_MDMA3_DEST_CURR_X_COUNT(val) bfin_write32(MDMA3_DEST_CURR_X_COUNT, val) +#define bfin_read_MDMA3_DEST_CURR_Y_COUNT() bfin_read32(MDMA3_DEST_CURR_Y_COUNT) +#define bfin_write_MDMA3_DEST_CURR_Y_COUNT(val) bfin_write32(MDMA3_DEST_CURR_Y_COUNT, val) +#define bfin_read_MDMA3_SRC_NEXT_DESC_PTR() bfin_read32(MDMA3_SRC_NEXT_DESC_PTR) +#define bfin_write_MDMA3_SRC_NEXT_DESC_PTR(val) bfin_write32(MDMA3_SRC_NEXT_DESC_PTR, val) +#define bfin_read_MDMA3_SRC_START_ADDR() bfin_read32(MDMA3_SRC_START_ADDR) +#define bfin_write_MDMA3_SRC_START_ADDR(val) bfin_write32(MDMA3_SRC_START_ADDR, val) +#define bfin_read_MDMA3_SRC_CONFIG() bfin_read32(MDMA3_SRC_CONFIG) +#define bfin_write_MDMA3_SRC_CONFIG(val) bfin_write32(MDMA3_SRC_CONFIG, val) +#define bfin_read_MDMA3_SRC_X_COUNT() bfin_read32(MDMA3_SRC_X_COUNT) +#define bfin_write_MDMA3_SRC_X_COUNT(val) bfin_write32(MDMA3_SRC_X_COUNT, val) +#define bfin_read_MDMA3_SRC_X_MODIFY() bfin_read32(MDMA3_SRC_X_MODIFY) +#define bfin_write_MDMA3_SRC_X_MODIFY(val) bfin_write32(MDMA3_SRC_X_MODIFY, val) +#define bfin_read_MDMA3_SRC_Y_COUNT() bfin_read32(MDMA3_SRC_Y_COUNT) +#define bfin_write_MDMA3_SRC_Y_COUNT(val) bfin_write32(MDMA3_SRC_Y_COUNT, val) +#define bfin_read_MDMA3_SRC_Y_MODIFY() bfin_read32(MDMA3_SRC_Y_MODIFY) +#define bfin_write_MDMA3_SRC_Y_MODIFY(val) bfin_write32(MDMA3_SRC_Y_MODIFY, val) +#define bfin_read_MDMA3_SRC_CURR_DESC_PTR() bfin_read32(MDMA3_SRC_CURR_DESC_PTR) +#define bfin_write_MDMA3_SRC_CURR_DESC_PTR(val) bfin_write32(MDMA3_SRC_CURR_DESC_PTR, val) +#define bfin_read_MDMA3_SRC_PREV_DESC_PTR() bfin_read32(MDMA3_SRC_PREV_DESC_PTR) +#define bfin_write_MDMA3_SRC_PREV_DESC_PTR(val) bfin_write32(MDMA3_SRC_PREV_DESC_PTR, val) +#define bfin_read_MDMA3_SRC_CURR_ADDR() bfin_read32(MDMA3_SRC_CURR_ADDR) +#define bfin_write_MDMA3_SRC_CURR_ADDR(val) bfin_write32(MDMA3_SRC_CURR_ADDR, val) +#define bfin_read_MDMA3_SRC_IRQ_STATUS() bfin_read32(MDMA3_SRC_IRQ_STATUS) +#define bfin_write_MDMA3_SRC_IRQ_STATUS(val) bfin_write32(MDMA3_SRC_IRQ_STATUS, val) +#define bfin_read_MDMA3_SRC_CURR_X_COUNT() bfin_read32(MDMA3_SRC_CURR_X_COUNT) +#define bfin_write_MDMA3_SRC_CURR_X_COUNT(val) bfin_write32(MDMA3_SRC_CURR_X_COUNT, val) +#define bfin_read_MDMA3_SRC_CURR_Y_COUNT() bfin_read32(MDMA3_SRC_CURR_Y_COUNT) +#define bfin_write_MDMA3_SRC_CURR_Y_COUNT(val) bfin_write32(MDMA3_SRC_CURR_Y_COUNT, val) + + +/* DMA Channel 29 Registers */ + +#define bfin_read_DMA29_NEXT_DESC_PTR() bfin_read32(DMA29_NEXT_DESC_PTR) +#define bfin_write_DMA29_NEXT_DESC_PTR(val) bfin_write32(DMA29_NEXT_DESC_PTR, val) +#define bfin_read_DMA29_START_ADDR() bfin_read32(DMA29_START_ADDR) +#define bfin_write_DMA29_START_ADDR(val) bfin_write32(DMA29_START_ADDR, val) +#define bfin_read_DMA29_CONFIG() bfin_read32(DMA29_CONFIG) +#define bfin_write_DMA29_CONFIG(val) bfin_write32(DMA29_CONFIG, val) +#define bfin_read_DMA29_X_COUNT() bfin_read32(DMA29_X_COUNT) +#define bfin_write_DMA29_X_COUNT(val) bfin_write32(DMA29_X_COUNT, val) +#define bfin_read_DMA29_X_MODIFY() bfin_read32(DMA29_X_MODIFY) +#define bfin_write_DMA29_X_MODIFY(val) bfin_write32(DMA29_X_MODIFY, val) +#define bfin_read_DMA29_Y_COUNT() bfin_read32(DMA29_Y_COUNT) +#define bfin_write_DMA29_Y_COUNT(val) bfin_write32(DMA29_Y_COUNT, val) +#define bfin_read_DMA29_Y_MODIFY() bfin_read32(DMA29_Y_MODIFY) +#define bfin_write_DMA29_Y_MODIFY(val) bfin_write32(DMA29_Y_MODIFY, val) +#define bfin_read_DMA29_CURR_DESC_PTR() bfin_read32(DMA29_CURR_DESC_PTR) +#define bfin_write_DMA29_CURR_DESC_PTR(val) bfin_write32(DMA29_CURR_DESC_PTR, val) +#define bfin_read_DMA29_PREV_DESC_PTR() bfin_read32(DMA29_PREV_DESC_PTR) +#define bfin_write_DMA29_PREV_DESC_PTR(val) bfin_write32(DMA29_PREV_DESC_PTR, val) +#define bfin_read_DMA29_CURR_ADDR() bfin_read32(DMA29_CURR_ADDR) +#define bfin_write_DMA29_CURR_ADDR(val) bfin_write32(DMA29_CURR_ADDR, val) +#define bfin_read_DMA29_IRQ_STATUS() bfin_read32(DMA29_IRQ_STATUS) +#define bfin_write_DMA29_IRQ_STATUS(val) bfin_write32(DMA29_IRQ_STATUS, val) +#define bfin_read_DMA29_CURR_X_COUNT() bfin_read32(DMA29_CURR_X_COUNT) +#define bfin_write_DMA29_CURR_X_COUNT(val) bfin_write32(DMA29_CURR_X_COUNT, val) +#define bfin_read_DMA29_CURR_Y_COUNT() bfin_read32(DMA29_CURR_Y_COUNT) +#define bfin_write_DMA29_CURR_Y_COUNT(val) bfin_write32(DMA29_CURR_Y_COUNT, val) +#define bfin_read_DMA29_BWL_COUNT() bfin_read32(DMA29_BWL_COUNT) +#define bfin_write_DMA29_BWL_COUNT(val) bfin_write32(DMA29_BWL_COUNT, val) +#define bfin_read_DMA29_CURR_BWL_COUNT() bfin_read32(DMA29_CURR_BWL_COUNT) +#define bfin_write_DMA29_CURR_BWL_COUNT(val) bfin_write32(DMA29_CURR_BWL_COUNT, val) +#define bfin_read_DMA29_BWM_COUNT() bfin_read32(DMA29_BWM_COUNT) +#define bfin_write_DMA29_BWM_COUNT(val) bfin_write32(DMA29_BWM_COUNT, val) +#define bfin_read_DMA29_CURR_BWM_COUNT() bfin_read32(DMA29_CURR_BWM_COUNT) +#define bfin_write_DMA29_CURR_BWM_COUNT(val) bfin_write32(DMA29_CURR_BWM_COUNT, val) + +/* DMA Channel 30 Registers */ + +#define bfin_read_DMA30_NEXT_DESC_PTR() bfin_read32(DMA30_NEXT_DESC_PTR) +#define bfin_write_DMA30_NEXT_DESC_PTR(val) bfin_write32(DMA30_NEXT_DESC_PTR, val) +#define bfin_read_DMA30_START_ADDR() bfin_read32(DMA30_START_ADDR) +#define bfin_write_DMA30_START_ADDR(val) bfin_write32(DMA30_START_ADDR, val) +#define bfin_read_DMA30_CONFIG() bfin_read32(DMA30_CONFIG) +#define bfin_write_DMA30_CONFIG(val) bfin_write32(DMA30_CONFIG, val) +#define bfin_read_DMA30_X_COUNT() bfin_read32(DMA30_X_COUNT) +#define bfin_write_DMA30_X_COUNT(val) bfin_write32(DMA30_X_COUNT, val) +#define bfin_read_DMA30_X_MODIFY() bfin_read32(DMA30_X_MODIFY) +#define bfin_write_DMA30_X_MODIFY(val) bfin_write32(DMA30_X_MODIFY, val) +#define bfin_read_DMA30_Y_COUNT() bfin_read32(DMA30_Y_COUNT) +#define bfin_write_DMA30_Y_COUNT(val) bfin_write32(DMA30_Y_COUNT, val) +#define bfin_read_DMA30_Y_MODIFY() bfin_read32(DMA30_Y_MODIFY) +#define bfin_write_DMA30_Y_MODIFY(val) bfin_write32(DMA30_Y_MODIFY, val) +#define bfin_read_DMA30_CURR_DESC_PTR() bfin_read32(DMA30_CURR_DESC_PTR) +#define bfin_write_DMA30_CURR_DESC_PTR(val) bfin_write32(DMA30_CURR_DESC_PTR, val) +#define bfin_read_DMA30_PREV_DESC_PTR() bfin_read32(DMA30_PREV_DESC_PTR) +#define bfin_write_DMA30_PREV_DESC_PTR(val) bfin_write32(DMA30_PREV_DESC_PTR, val) +#define bfin_read_DMA30_CURR_ADDR() bfin_read32(DMA30_CURR_ADDR) +#define bfin_write_DMA30_CURR_ADDR(val) bfin_write32(DMA30_CURR_ADDR, val) +#define bfin_read_DMA30_IRQ_STATUS() bfin_read32(DMA30_IRQ_STATUS) +#define bfin_write_DMA30_IRQ_STATUS(val) bfin_write32(DMA30_IRQ_STATUS, val) +#define bfin_read_DMA30_CURR_X_COUNT() bfin_read32(DMA30_CURR_X_COUNT) +#define bfin_write_DMA30_CURR_X_COUNT(val) bfin_write32(DMA30_CURR_X_COUNT, val) +#define bfin_read_DMA30_CURR_Y_COUNT() bfin_read32(DMA30_CURR_Y_COUNT) +#define bfin_write_DMA30_CURR_Y_COUNT(val) bfin_write32(DMA30_CURR_Y_COUNT, val) +#define bfin_read_DMA30_BWL_COUNT() bfin_read32(DMA30_BWL_COUNT) +#define bfin_write_DMA30_BWL_COUNT(val) bfin_write32(DMA30_BWL_COUNT, val) +#define bfin_read_DMA30_CURR_BWL_COUNT() bfin_read32(DMA30_CURR_BWL_COUNT) +#define bfin_write_DMA30_CURR_BWL_COUNT(val) bfin_write32(DMA30_CURR_BWL_COUNT, val) +#define bfin_read_DMA30_BWM_COUNT() bfin_read32(DMA30_BWM_COUNT) +#define bfin_write_DMA30_BWM_COUNT(val) bfin_write32(DMA30_BWM_COUNT, val) +#define bfin_read_DMA30_CURR_BWM_COUNT() bfin_read32(DMA30_CURR_BWM_COUNT) +#define bfin_write_DMA30_CURR_BWM_COUNT(val) bfin_write32(DMA30_CURR_BWM_COUNT, val) + +/* DMA Channel 31 Registers */ + +#define bfin_read_DMA31_NEXT_DESC_PTR() bfin_read32(DMA31_NEXT_DESC_PTR) +#define bfin_write_DMA31_NEXT_DESC_PTR(val) bfin_write32(DMA31_NEXT_DESC_PTR, val) +#define bfin_read_DMA31_START_ADDR() bfin_read32(DMA31_START_ADDR) +#define bfin_write_DMA31_START_ADDR(val) bfin_write32(DMA31_START_ADDR, val) +#define bfin_read_DMA31_CONFIG() bfin_read32(DMA31_CONFIG) +#define bfin_write_DMA31_CONFIG(val) bfin_write32(DMA31_CONFIG, val) +#define bfin_read_DMA31_X_COUNT() bfin_read32(DMA31_X_COUNT) +#define bfin_write_DMA31_X_COUNT(val) bfin_write32(DMA31_X_COUNT, val) +#define bfin_read_DMA31_X_MODIFY() bfin_read32(DMA31_X_MODIFY) +#define bfin_write_DMA31_X_MODIFY(val) bfin_write32(DMA31_X_MODIFY, val) +#define bfin_read_DMA31_Y_COUNT() bfin_read32(DMA31_Y_COUNT) +#define bfin_write_DMA31_Y_COUNT(val) bfin_write32(DMA31_Y_COUNT, val) +#define bfin_read_DMA31_Y_MODIFY() bfin_read32(DMA31_Y_MODIFY) +#define bfin_write_DMA31_Y_MODIFY(val) bfin_write32(DMA31_Y_MODIFY, val) +#define bfin_read_DMA31_CURR_DESC_PTR() bfin_read32(DMA31_CURR_DESC_PTR) +#define bfin_write_DMA31_CURR_DESC_PTR(val) bfin_write32(DMA31_CURR_DESC_PTR, val) +#define bfin_read_DMA31_PREV_DESC_PTR() bfin_read32(DMA31_PREV_DESC_PTR) +#define bfin_write_DMA31_PREV_DESC_PTR(val) bfin_write32(DMA31_PREV_DESC_PTR, val) +#define bfin_read_DMA31_CURR_ADDR() bfin_read32(DMA31_CURR_ADDR) +#define bfin_write_DMA31_CURR_ADDR(val) bfin_write32(DMA31_CURR_ADDR, val) +#define bfin_read_DMA31_IRQ_STATUS() bfin_read32(DMA31_IRQ_STATUS) +#define bfin_write_DMA31_IRQ_STATUS(val) bfin_write32(DMA31_IRQ_STATUS, val) +#define bfin_read_DMA31_CURR_X_COUNT() bfin_read32(DMA31_CURR_X_COUNT) +#define bfin_write_DMA31_CURR_X_COUNT(val) bfin_write32(DMA31_CURR_X_COUNT, val) +#define bfin_read_DMA31_CURR_Y_COUNT() bfin_read32(DMA31_CURR_Y_COUNT) +#define bfin_write_DMA31_CURR_Y_COUNT(val) bfin_write32(DMA31_CURR_Y_COUNT, val) +#define bfin_read_DMA31_BWL_COUNT() bfin_read32(DMA31_BWL_COUNT) +#define bfin_write_DMA31_BWL_COUNT(val) bfin_write32(DMA31_BWL_COUNT, val) +#define bfin_read_DMA31_CURR_BWL_COUNT() bfin_read32(DMA31_CURR_BWL_COUNT) +#define bfin_write_DMA31_CURR_BWL_COUNT(val) bfin_write32(DMA31_CURR_BWL_COUNT, val) +#define bfin_read_DMA31_BWM_COUNT() bfin_read32(DMA31_BWM_COUNT) +#define bfin_write_DMA31_BWM_COUNT(val) bfin_write32(DMA31_BWM_COUNT, val) +#define bfin_read_DMA31_CURR_BWM_COUNT() bfin_read32(DMA31_CURR_BWM_COUNT) +#define bfin_write_DMA31_CURR_BWM_COUNT(val) bfin_write32(DMA31_CURR_BWM_COUNT, val) + +/* DMA Channel 32 Registers */ + +#define bfin_read_DMA32_NEXT_DESC_PTR() bfin_read32(DMA32_NEXT_DESC_PTR) +#define bfin_write_DMA32_NEXT_DESC_PTR(val) bfin_write32(DMA32_NEXT_DESC_PTR, val) +#define bfin_read_DMA32_START_ADDR() bfin_read32(DMA32_START_ADDR) +#define bfin_write_DMA32_START_ADDR(val) bfin_write32(DMA32_START_ADDR, val) +#define bfin_read_DMA32_CONFIG() bfin_read32(DMA32_CONFIG) +#define bfin_write_DMA32_CONFIG(val) bfin_write32(DMA32_CONFIG, val) +#define bfin_read_DMA32_X_COUNT() bfin_read32(DMA32_X_COUNT) +#define bfin_write_DMA32_X_COUNT(val) bfin_write32(DMA32_X_COUNT, val) +#define bfin_read_DMA32_X_MODIFY() bfin_read32(DMA32_X_MODIFY) +#define bfin_write_DMA32_X_MODIFY(val) bfin_write32(DMA32_X_MODIFY, val) +#define bfin_read_DMA32_Y_COUNT() bfin_read32(DMA32_Y_COUNT) +#define bfin_write_DMA32_Y_COUNT(val) bfin_write32(DMA32_Y_COUNT, val) +#define bfin_read_DMA32_Y_MODIFY() bfin_read32(DMA32_Y_MODIFY) +#define bfin_write_DMA32_Y_MODIFY(val) bfin_write32(DMA32_Y_MODIFY, val) +#define bfin_read_DMA32_CURR_DESC_PTR() bfin_read32(DMA32_CURR_DESC_PTR) +#define bfin_write_DMA32_CURR_DESC_PTR(val) bfin_write32(DMA32_CURR_DESC_PTR, val) +#define bfin_read_DMA32_PREV_DESC_PTR() bfin_read32(DMA32_PREV_DESC_PTR) +#define bfin_write_DMA32_PREV_DESC_PTR(val) bfin_write32(DMA32_PREV_DESC_PTR, val) +#define bfin_read_DMA32_CURR_ADDR() bfin_read32(DMA32_CURR_ADDR) +#define bfin_write_DMA32_CURR_ADDR(val) bfin_write32(DMA32_CURR_ADDR, val) +#define bfin_read_DMA32_IRQ_STATUS() bfin_read32(DMA32_IRQ_STATUS) +#define bfin_write_DMA32_IRQ_STATUS(val) bfin_write32(DMA32_IRQ_STATUS, val) +#define bfin_read_DMA32_CURR_X_COUNT() bfin_read32(DMA32_CURR_X_COUNT) +#define bfin_write_DMA32_CURR_X_COUNT(val) bfin_write32(DMA32_CURR_X_COUNT, val) +#define bfin_read_DMA32_CURR_Y_COUNT() bfin_read32(DMA32_CURR_Y_COUNT) +#define bfin_write_DMA32_CURR_Y_COUNT(val) bfin_write32(DMA32_CURR_Y_COUNT, val) +#define bfin_read_DMA32_BWL_COUNT() bfin_read32(DMA32_BWL_COUNT) +#define bfin_write_DMA32_BWL_COUNT(val) bfin_write32(DMA32_BWL_COUNT, val) +#define bfin_read_DMA32_CURR_BWL_COUNT() bfin_read32(DMA32_CURR_BWL_COUNT) +#define bfin_write_DMA32_CURR_BWL_COUNT(val) bfin_write32(DMA32_CURR_BWL_COUNT, val) +#define bfin_read_DMA32_BWM_COUNT() bfin_read32(DMA32_BWM_COUNT) +#define bfin_write_DMA32_BWM_COUNT(val) bfin_write32(DMA32_BWM_COUNT, val) +#define bfin_read_DMA32_CURR_BWM_COUNT() bfin_read32(DMA32_CURR_BWM_COUNT) +#define bfin_write_DMA32_CURR_BWM_COUNT(val) bfin_write32(DMA32_CURR_BWM_COUNT, val) + +/* DMA Channel 33 Registers */ + +#define bfin_read_DMA33_NEXT_DESC_PTR() bfin_read32(DMA33_NEXT_DESC_PTR) +#define bfin_write_DMA33_NEXT_DESC_PTR(val) bfin_write32(DMA33_NEXT_DESC_PTR, val) +#define bfin_read_DMA33_START_ADDR() bfin_read32(DMA33_START_ADDR) +#define bfin_write_DMA33_START_ADDR(val) bfin_write32(DMA33_START_ADDR, val) +#define bfin_read_DMA33_CONFIG() bfin_read32(DMA33_CONFIG) +#define bfin_write_DMA33_CONFIG(val) bfin_write32(DMA33_CONFIG, val) +#define bfin_read_DMA33_X_COUNT() bfin_read32(DMA33_X_COUNT) +#define bfin_write_DMA33_X_COUNT(val) bfin_write32(DMA33_X_COUNT, val) +#define bfin_read_DMA33_X_MODIFY() bfin_read32(DMA33_X_MODIFY) +#define bfin_write_DMA33_X_MODIFY(val) bfin_write32(DMA33_X_MODIFY, val) +#define bfin_read_DMA33_Y_COUNT() bfin_read32(DMA33_Y_COUNT) +#define bfin_write_DMA33_Y_COUNT(val) bfin_write32(DMA33_Y_COUNT, val) +#define bfin_read_DMA33_Y_MODIFY() bfin_read32(DMA33_Y_MODIFY) +#define bfin_write_DMA33_Y_MODIFY(val) bfin_write32(DMA33_Y_MODIFY, val) +#define bfin_read_DMA33_CURR_DESC_PTR() bfin_read32(DMA33_CURR_DESC_PTR) +#define bfin_write_DMA33_CURR_DESC_PTR(val) bfin_write32(DMA33_CURR_DESC_PTR, val) +#define bfin_read_DMA33_PREV_DESC_PTR() bfin_read32(DMA33_PREV_DESC_PTR) +#define bfin_write_DMA33_PREV_DESC_PTR(val) bfin_write32(DMA33_PREV_DESC_PTR, val) +#define bfin_read_DMA33_CURR_ADDR() bfin_read32(DMA33_CURR_ADDR) +#define bfin_write_DMA33_CURR_ADDR(val) bfin_write32(DMA33_CURR_ADDR, val) +#define bfin_read_DMA33_IRQ_STATUS() bfin_read32(DMA33_IRQ_STATUS) +#define bfin_write_DMA33_IRQ_STATUS(val) bfin_write32(DMA33_IRQ_STATUS, val) +#define bfin_read_DMA33_CURR_X_COUNT() bfin_read32(DMA33_CURR_X_COUNT) +#define bfin_write_DMA33_CURR_X_COUNT(val) bfin_write32(DMA33_CURR_X_COUNT, val) +#define bfin_read_DMA33_CURR_Y_COUNT() bfin_read32(DMA33_CURR_Y_COUNT) +#define bfin_write_DMA33_CURR_Y_COUNT(val) bfin_write32(DMA33_CURR_Y_COUNT, val) +#define bfin_read_DMA33_BWL_COUNT() bfin_read32(DMA33_BWL_COUNT) +#define bfin_write_DMA33_BWL_COUNT(val) bfin_write32(DMA33_BWL_COUNT, val) +#define bfin_read_DMA33_CURR_BWL_COUNT() bfin_read32(DMA33_CURR_BWL_COUNT) +#define bfin_write_DMA33_CURR_BWL_COUNT(val) bfin_write32(DMA33_CURR_BWL_COUNT, val) +#define bfin_read_DMA33_BWM_COUNT() bfin_read32(DMA33_BWM_COUNT) +#define bfin_write_DMA33_BWM_COUNT(val) bfin_write32(DMA33_BWM_COUNT, val) +#define bfin_read_DMA33_CURR_BWM_COUNT() bfin_read32(DMA33_CURR_BWM_COUNT) +#define bfin_write_DMA33_CURR_BWM_COUNT(val) bfin_write32(DMA33_CURR_BWM_COUNT, val) + +/* DMA Channel 34 Registers */ + +#define bfin_read_DMA34_NEXT_DESC_PTR() bfin_read32(DMA34_NEXT_DESC_PTR) +#define bfin_write_DMA34_NEXT_DESC_PTR(val) bfin_write32(DMA34_NEXT_DESC_PTR, val) +#define bfin_read_DMA34_START_ADDR() bfin_read32(DMA34_START_ADDR) +#define bfin_write_DMA34_START_ADDR(val) bfin_write32(DMA34_START_ADDR, val) +#define bfin_read_DMA34_CONFIG() bfin_read32(DMA34_CONFIG) +#define bfin_write_DMA34_CONFIG(val) bfin_write32(DMA34_CONFIG, val) +#define bfin_read_DMA34_X_COUNT() bfin_read32(DMA34_X_COUNT) +#define bfin_write_DMA34_X_COUNT(val) bfin_write32(DMA34_X_COUNT, val) +#define bfin_read_DMA34_X_MODIFY() bfin_read32(DMA34_X_MODIFY) +#define bfin_write_DMA34_X_MODIFY(val) bfin_write32(DMA34_X_MODIFY, val) +#define bfin_read_DMA34_Y_COUNT() bfin_read32(DMA34_Y_COUNT) +#define bfin_write_DMA34_Y_COUNT(val) bfin_write32(DMA34_Y_COUNT, val) +#define bfin_read_DMA34_Y_MODIFY() bfin_read32(DMA34_Y_MODIFY) +#define bfin_write_DMA34_Y_MODIFY(val) bfin_write32(DMA34_Y_MODIFY, val) +#define bfin_read_DMA34_CURR_DESC_PTR() bfin_read32(DMA34_CURR_DESC_PTR) +#define bfin_write_DMA34_CURR_DESC_PTR(val) bfin_write32(DMA34_CURR_DESC_PTR, val) +#define bfin_read_DMA34_PREV_DESC_PTR() bfin_read32(DMA34_PREV_DESC_PTR) +#define bfin_write_DMA34_PREV_DESC_PTR(val) bfin_write32(DMA34_PREV_DESC_PTR, val) +#define bfin_read_DMA34_CURR_ADDR() bfin_read32(DMA34_CURR_ADDR) +#define bfin_write_DMA34_CURR_ADDR(val) bfin_write32(DMA34_CURR_ADDR, val) +#define bfin_read_DMA34_IRQ_STATUS() bfin_read32(DMA34_IRQ_STATUS) +#define bfin_write_DMA34_IRQ_STATUS(val) bfin_write32(DMA34_IRQ_STATUS, val) +#define bfin_read_DMA34_CURR_X_COUNT() bfin_read32(DMA34_CURR_X_COUNT) +#define bfin_write_DMA34_CURR_X_COUNT(val) bfin_write32(DMA34_CURR_X_COUNT, val) +#define bfin_read_DMA34_CURR_Y_COUNT() bfin_read32(DMA34_CURR_Y_COUNT) +#define bfin_write_DMA34_CURR_Y_COUNT(val) bfin_write32(DMA34_CURR_Y_COUNT, val) +#define bfin_read_DMA34_BWL_COUNT() bfin_read32(DMA34_BWL_COUNT) +#define bfin_write_DMA34_BWL_COUNT(val) bfin_write32(DMA34_BWL_COUNT, val) +#define bfin_read_DMA34_CURR_BWL_COUNT() bfin_read32(DMA34_CURR_BWL_COUNT) +#define bfin_write_DMA34_CURR_BWL_COUNT(val) bfin_write32(DMA34_CURR_BWL_COUNT, val) +#define bfin_read_DMA34_BWM_COUNT() bfin_read32(DMA34_BWM_COUNT) +#define bfin_write_DMA34_BWM_COUNT(val) bfin_write32(DMA34_BWM_COUNT, val) +#define bfin_read_DMA34_CURR_BWM_COUNT() bfin_read32(DMA34_CURR_BWM_COUNT) +#define bfin_write_DMA34_CURR_BWM_COUNT(val) bfin_write32(DMA34_CURR_BWM_COUNT, val) + +/* DMA Channel 35 Registers */ + +#define bfin_read_DMA35_NEXT_DESC_PTR() bfin_read32(DMA35_NEXT_DESC_PTR) +#define bfin_write_DMA35_NEXT_DESC_PTR(val) bfin_write32(DMA35_NEXT_DESC_PTR, val) +#define bfin_read_DMA35_START_ADDR() bfin_read32(DMA35_START_ADDR) +#define bfin_write_DMA35_START_ADDR(val) bfin_write32(DMA35_START_ADDR, val) +#define bfin_read_DMA35_CONFIG() bfin_read32(DMA35_CONFIG) +#define bfin_write_DMA35_CONFIG(val) bfin_write32(DMA35_CONFIG, val) +#define bfin_read_DMA35_X_COUNT() bfin_read32(DMA35_X_COUNT) +#define bfin_write_DMA35_X_COUNT(val) bfin_write32(DMA35_X_COUNT, val) +#define bfin_read_DMA35_X_MODIFY() bfin_read32(DMA35_X_MODIFY) +#define bfin_write_DMA35_X_MODIFY(val) bfin_write32(DMA35_X_MODIFY, val) +#define bfin_read_DMA35_Y_COUNT() bfin_read32(DMA35_Y_COUNT) +#define bfin_write_DMA35_Y_COUNT(val) bfin_write32(DMA35_Y_COUNT, val) +#define bfin_read_DMA35_Y_MODIFY() bfin_read32(DMA35_Y_MODIFY) +#define bfin_write_DMA35_Y_MODIFY(val) bfin_write32(DMA35_Y_MODIFY, val) +#define bfin_read_DMA35_CURR_DESC_PTR() bfin_read32(DMA35_CURR_DESC_PTR) +#define bfin_write_DMA35_CURR_DESC_PTR(val) bfin_write32(DMA35_CURR_DESC_PTR, val) +#define bfin_read_DMA35_PREV_DESC_PTR() bfin_read32(DMA35_PREV_DESC_PTR) +#define bfin_write_DMA35_PREV_DESC_PTR(val) bfin_write32(DMA35_PREV_DESC_PTR, val) +#define bfin_read_DMA35_CURR_ADDR() bfin_read32(DMA35_CURR_ADDR) +#define bfin_write_DMA35_CURR_ADDR(val) bfin_write32(DMA35_CURR_ADDR, val) +#define bfin_read_DMA35_IRQ_STATUS() bfin_read32(DMA35_IRQ_STATUS) +#define bfin_write_DMA35_IRQ_STATUS(val) bfin_write32(DMA35_IRQ_STATUS, val) +#define bfin_read_DMA35_CURR_X_COUNT() bfin_read32(DMA35_CURR_X_COUNT) +#define bfin_write_DMA35_CURR_X_COUNT(val) bfin_write32(DMA35_CURR_X_COUNT, val) +#define bfin_read_DMA35_CURR_Y_COUNT() bfin_read32(DMA35_CURR_Y_COUNT) +#define bfin_write_DMA35_CURR_Y_COUNT(val) bfin_write32(DMA35_CURR_Y_COUNT, val) +#define bfin_read_DMA35_BWL_COUNT() bfin_read32(DMA35_BWL_COUNT) +#define bfin_write_DMA35_BWL_COUNT(val) bfin_write32(DMA35_BWL_COUNT, val) +#define bfin_read_DMA35_CURR_BWL_COUNT() bfin_read32(DMA35_CURR_BWL_COUNT) +#define bfin_write_DMA35_CURR_BWL_COUNT(val) bfin_write32(DMA35_CURR_BWL_COUNT, val) +#define bfin_read_DMA35_BWM_COUNT() bfin_read32(DMA35_BWM_COUNT) +#define bfin_write_DMA35_BWM_COUNT(val) bfin_write32(DMA35_BWM_COUNT, val) +#define bfin_read_DMA35_CURR_BWM_COUNT() bfin_read32(DMA35_CURR_BWM_COUNT) +#define bfin_write_DMA35_CURR_BWM_COUNT(val) bfin_write32(DMA35_CURR_BWM_COUNT, val) + +/* DMA Channel 36 Registers */ + +#define bfin_read_DMA36_NEXT_DESC_PTR() bfin_read32(DMA36_NEXT_DESC_PTR) +#define bfin_write_DMA36_NEXT_DESC_PTR(val) bfin_write32(DMA36_NEXT_DESC_PTR, val) +#define bfin_read_DMA36_START_ADDR() bfin_read32(DMA36_START_ADDR) +#define bfin_write_DMA36_START_ADDR(val) bfin_write32(DMA36_START_ADDR, val) +#define bfin_read_DMA36_CONFIG() bfin_read32(DMA36_CONFIG) +#define bfin_write_DMA36_CONFIG(val) bfin_write32(DMA36_CONFIG, val) +#define bfin_read_DMA36_X_COUNT() bfin_read32(DMA36_X_COUNT) +#define bfin_write_DMA36_X_COUNT(val) bfin_write32(DMA36_X_COUNT, val) +#define bfin_read_DMA36_X_MODIFY() bfin_read32(DMA36_X_MODIFY) +#define bfin_write_DMA36_X_MODIFY(val) bfin_write32(DMA36_X_MODIFY, val) +#define bfin_read_DMA36_Y_COUNT() bfin_read32(DMA36_Y_COUNT) +#define bfin_write_DMA36_Y_COUNT(val) bfin_write32(DMA36_Y_COUNT, val) +#define bfin_read_DMA36_Y_MODIFY() bfin_read32(DMA36_Y_MODIFY) +#define bfin_write_DMA36_Y_MODIFY(val) bfin_write32(DMA36_Y_MODIFY, val) +#define bfin_read_DMA36_CURR_DESC_PTR() bfin_read32(DMA36_CURR_DESC_PTR) +#define bfin_write_DMA36_CURR_DESC_PTR(val) bfin_write32(DMA36_CURR_DESC_PTR, val) +#define bfin_read_DMA36_PREV_DESC_PTR() bfin_read32(DMA36_PREV_DESC_PTR) +#define bfin_write_DMA36_PREV_DESC_PTR(val) bfin_write32(DMA36_PREV_DESC_PTR, val) +#define bfin_read_DMA36_CURR_ADDR() bfin_read32(DMA36_CURR_ADDR) +#define bfin_write_DMA36_CURR_ADDR(val) bfin_write32(DMA36_CURR_ADDR, val) +#define bfin_read_DMA36_IRQ_STATUS() bfin_read32(DMA36_IRQ_STATUS) +#define bfin_write_DMA36_IRQ_STATUS(val) bfin_write32(DMA36_IRQ_STATUS, val) +#define bfin_read_DMA36_CURR_X_COUNT() bfin_read32(DMA36_CURR_X_COUNT) +#define bfin_write_DMA36_CURR_X_COUNT(val) bfin_write32(DMA36_CURR_X_COUNT, val) +#define bfin_read_DMA36_CURR_Y_COUNT() bfin_read32(DMA36_CURR_Y_COUNT) +#define bfin_write_DMA36_CURR_Y_COUNT(val) bfin_write32(DMA36_CURR_Y_COUNT, val) +#define bfin_read_DMA36_BWL_COUNT() bfin_read32(DMA36_BWL_COUNT) +#define bfin_write_DMA36_BWL_COUNT(val) bfin_write32(DMA36_BWL_COUNT, val) +#define bfin_read_DMA36_CURR_BWL_COUNT() bfin_read32(DMA36_CURR_BWL_COUNT) +#define bfin_write_DMA36_CURR_BWL_COUNT(val) bfin_write32(DMA36_CURR_BWL_COUNT, val) +#define bfin_read_DMA36_BWM_COUNT() bfin_read32(DMA36_BWM_COUNT) +#define bfin_write_DMA36_BWM_COUNT(val) bfin_write32(DMA36_BWM_COUNT, val) +#define bfin_read_DMA36_CURR_BWM_COUNT() bfin_read32(DMA36_CURR_BWM_COUNT) +#define bfin_write_DMA36_CURR_BWM_COUNT(val) bfin_write32(DMA36_CURR_BWM_COUNT, val) + +/* DMA Channel 37 Registers */ + +#define bfin_read_DMA37_NEXT_DESC_PTR() bfin_read32(DMA37_NEXT_DESC_PTR) +#define bfin_write_DMA37_NEXT_DESC_PTR(val) bfin_write32(DMA37_NEXT_DESC_PTR, val) +#define bfin_read_DMA37_START_ADDR() bfin_read32(DMA37_START_ADDR) +#define bfin_write_DMA37_START_ADDR(val) bfin_write32(DMA37_START_ADDR, val) +#define bfin_read_DMA37_CONFIG() bfin_read32(DMA37_CONFIG) +#define bfin_write_DMA37_CONFIG(val) bfin_write32(DMA37_CONFIG, val) +#define bfin_read_DMA37_X_COUNT() bfin_read32(DMA37_X_COUNT) +#define bfin_write_DMA37_X_COUNT(val) bfin_write32(DMA37_X_COUNT, val) +#define bfin_read_DMA37_X_MODIFY() bfin_read32(DMA37_X_MODIFY) +#define bfin_write_DMA37_X_MODIFY(val) bfin_write32(DMA37_X_MODIFY, val) +#define bfin_read_DMA37_Y_COUNT() bfin_read32(DMA37_Y_COUNT) +#define bfin_write_DMA37_Y_COUNT(val) bfin_write32(DMA37_Y_COUNT, val) +#define bfin_read_DMA37_Y_MODIFY() bfin_read32(DMA37_Y_MODIFY) +#define bfin_write_DMA37_Y_MODIFY(val) bfin_write32(DMA37_Y_MODIFY, val) +#define bfin_read_DMA37_CURR_DESC_PTR() bfin_read32(DMA37_CURR_DESC_PTR) +#define bfin_write_DMA37_CURR_DESC_PTR(val) bfin_write32(DMA37_CURR_DESC_PTR, val) +#define bfin_read_DMA37_PREV_DESC_PTR() bfin_read32(DMA37_PREV_DESC_PTR) +#define bfin_write_DMA37_PREV_DESC_PTR(val) bfin_write32(DMA37_PREV_DESC_PTR, val) +#define bfin_read_DMA37_CURR_ADDR() bfin_read32(DMA37_CURR_ADDR) +#define bfin_write_DMA37_CURR_ADDR(val) bfin_write32(DMA37_CURR_ADDR, val) +#define bfin_read_DMA37_IRQ_STATUS() bfin_read32(DMA37_IRQ_STATUS) +#define bfin_write_DMA37_IRQ_STATUS(val) bfin_write32(DMA37_IRQ_STATUS, val) +#define bfin_read_DMA37_CURR_X_COUNT() bfin_read32(DMA37_CURR_X_COUNT) +#define bfin_write_DMA37_CURR_X_COUNT(val) bfin_write32(DMA37_CURR_X_COUNT, val) +#define bfin_read_DMA37_CURR_Y_COUNT() bfin_read32(DMA37_CURR_Y_COUNT) +#define bfin_write_DMA37_CURR_Y_COUNT(val) bfin_write32(DMA37_CURR_Y_COUNT, val) +#define bfin_read_DMA37_BWL_COUNT() bfin_read32(DMA37_BWL_COUNT) +#define bfin_write_DMA37_BWL_COUNT(val) bfin_write32(DMA37_BWL_COUNT, val) +#define bfin_read_DMA37_CURR_BWL_COUNT() bfin_read32(DMA37_CURR_BWL_COUNT) +#define bfin_write_DMA37_CURR_BWL_COUNT(val) bfin_write32(DMA37_CURR_BWL_COUNT, val) +#define bfin_read_DMA37_BWM_COUNT() bfin_read32(DMA37_BWM_COUNT) +#define bfin_write_DMA37_BWM_COUNT(val) bfin_write32(DMA37_BWM_COUNT, val) +#define bfin_read_DMA37_CURR_BWM_COUNT() bfin_read32(DMA37_CURR_BWM_COUNT) +#define bfin_write_DMA37_CURR_BWM_COUNT(val) bfin_write32(DMA37_CURR_BWM_COUNT, val) + +/* DMA Channel 38 Registers */ + +#define bfin_read_DMA38_NEXT_DESC_PTR() bfin_read32(DMA38_NEXT_DESC_PTR) +#define bfin_write_DMA38_NEXT_DESC_PTR(val) bfin_write32(DMA38_NEXT_DESC_PTR, val) +#define bfin_read_DMA38_START_ADDR() bfin_read32(DMA38_START_ADDR) +#define bfin_write_DMA38_START_ADDR(val) bfin_write32(DMA38_START_ADDR, val) +#define bfin_read_DMA38_CONFIG() bfin_read32(DMA38_CONFIG) +#define bfin_write_DMA38_CONFIG(val) bfin_write32(DMA38_CONFIG, val) +#define bfin_read_DMA38_X_COUNT() bfin_read32(DMA38_X_COUNT) +#define bfin_write_DMA38_X_COUNT(val) bfin_write32(DMA38_X_COUNT, val) +#define bfin_read_DMA38_X_MODIFY() bfin_read32(DMA38_X_MODIFY) +#define bfin_write_DMA38_X_MODIFY(val) bfin_write32(DMA38_X_MODIFY, val) +#define bfin_read_DMA38_Y_COUNT() bfin_read32(DMA38_Y_COUNT) +#define bfin_write_DMA38_Y_COUNT(val) bfin_write32(DMA38_Y_COUNT, val) +#define bfin_read_DMA38_Y_MODIFY() bfin_read32(DMA38_Y_MODIFY) +#define bfin_write_DMA38_Y_MODIFY(val) bfin_write32(DMA38_Y_MODIFY, val) +#define bfin_read_DMA38_CURR_DESC_PTR() bfin_read32(DMA38_CURR_DESC_PTR) +#define bfin_write_DMA38_CURR_DESC_PTR(val) bfin_write32(DMA38_CURR_DESC_PTR, val) +#define bfin_read_DMA38_PREV_DESC_PTR() bfin_read32(DMA38_PREV_DESC_PTR) +#define bfin_write_DMA38_PREV_DESC_PTR(val) bfin_write32(DMA38_PREV_DESC_PTR, val) +#define bfin_read_DMA38_CURR_ADDR() bfin_read32(DMA38_CURR_ADDR) +#define bfin_write_DMA38_CURR_ADDR(val) bfin_write32(DMA38_CURR_ADDR, val) +#define bfin_read_DMA38_IRQ_STATUS() bfin_read32(DMA38_IRQ_STATUS) +#define bfin_write_DMA38_IRQ_STATUS(val) bfin_write32(DMA38_IRQ_STATUS, val) +#define bfin_read_DMA38_CURR_X_COUNT() bfin_read32(DMA38_CURR_X_COUNT) +#define bfin_write_DMA38_CURR_X_COUNT(val) bfin_write32(DMA38_CURR_X_COUNT, val) +#define bfin_read_DMA38_CURR_Y_COUNT() bfin_read32(DMA38_CURR_Y_COUNT) +#define bfin_write_DMA38_CURR_Y_COUNT(val) bfin_write32(DMA38_CURR_Y_COUNT, val) +#define bfin_read_DMA38_BWL_COUNT() bfin_read32(DMA38_BWL_COUNT) +#define bfin_write_DMA38_BWL_COUNT(val) bfin_write32(DMA38_BWL_COUNT, val) +#define bfin_read_DMA38_CURR_BWL_COUNT() bfin_read32(DMA38_CURR_BWL_COUNT) +#define bfin_write_DMA38_CURR_BWL_COUNT(val) bfin_write32(DMA38_CURR_BWL_COUNT, val) +#define bfin_read_DMA38_BWM_COUNT() bfin_read32(DMA38_BWM_COUNT) +#define bfin_write_DMA38_BWM_COUNT(val) bfin_write32(DMA38_BWM_COUNT, val) +#define bfin_read_DMA38_CURR_BWM_COUNT() bfin_read32(DMA38_CURR_BWM_COUNT) +#define bfin_write_DMA38_CURR_BWM_COUNT(val) bfin_write32(DMA38_CURR_BWM_COUNT, val) + +/* DMA Channel 39 Registers */ + +#define bfin_read_DMA39_NEXT_DESC_PTR() bfin_read32(DMA39_NEXT_DESC_PTR) +#define bfin_write_DMA39_NEXT_DESC_PTR(val) bfin_write32(DMA39_NEXT_DESC_PTR, val) +#define bfin_read_DMA39_START_ADDR() bfin_read32(DMA39_START_ADDR) +#define bfin_write_DMA39_START_ADDR(val) bfin_write32(DMA39_START_ADDR, val) +#define bfin_read_DMA39_CONFIG() bfin_read32(DMA39_CONFIG) +#define bfin_write_DMA39_CONFIG(val) bfin_write32(DMA39_CONFIG, val) +#define bfin_read_DMA39_X_COUNT() bfin_read32(DMA39_X_COUNT) +#define bfin_write_DMA39_X_COUNT(val) bfin_write32(DMA39_X_COUNT, val) +#define bfin_read_DMA39_X_MODIFY() bfin_read32(DMA39_X_MODIFY) +#define bfin_write_DMA39_X_MODIFY(val) bfin_write32(DMA39_X_MODIFY, val) +#define bfin_read_DMA39_Y_COUNT() bfin_read32(DMA39_Y_COUNT) +#define bfin_write_DMA39_Y_COUNT(val) bfin_write32(DMA39_Y_COUNT, val) +#define bfin_read_DMA39_Y_MODIFY() bfin_read32(DMA39_Y_MODIFY) +#define bfin_write_DMA39_Y_MODIFY(val) bfin_write32(DMA39_Y_MODIFY, val) +#define bfin_read_DMA39_CURR_DESC_PTR() bfin_read32(DMA39_CURR_DESC_PTR) +#define bfin_write_DMA39_CURR_DESC_PTR(val) bfin_write32(DMA39_CURR_DESC_PTR, val) +#define bfin_read_DMA39_PREV_DESC_PTR() bfin_read32(DMA39_PREV_DESC_PTR) +#define bfin_write_DMA39_PREV_DESC_PTR(val) bfin_write32(DMA39_PREV_DESC_PTR, val) +#define bfin_read_DMA39_CURR_ADDR() bfin_read32(DMA39_CURR_ADDR) +#define bfin_write_DMA39_CURR_ADDR(val) bfin_write32(DMA39_CURR_ADDR, val) +#define bfin_read_DMA39_IRQ_STATUS() bfin_read32(DMA39_IRQ_STATUS) +#define bfin_write_DMA39_IRQ_STATUS(val) bfin_write32(DMA39_IRQ_STATUS, val) +#define bfin_read_DMA39_CURR_X_COUNT() bfin_read32(DMA39_CURR_X_COUNT) +#define bfin_write_DMA39_CURR_X_COUNT(val) bfin_write32(DMA39_CURR_X_COUNT, val) +#define bfin_read_DMA39_CURR_Y_COUNT() bfin_read32(DMA39_CURR_Y_COUNT) +#define bfin_write_DMA39_CURR_Y_COUNT(val) bfin_write32(DMA39_CURR_Y_COUNT, val) +#define bfin_read_DMA39_BWL_COUNT() bfin_read32(DMA39_BWL_COUNT) +#define bfin_write_DMA39_BWL_COUNT(val) bfin_write32(DMA39_BWL_COUNT, val) +#define bfin_read_DMA39_CURR_BWL_COUNT() bfin_read32(DMA39_CURR_BWL_COUNT) +#define bfin_write_DMA39_CURR_BWL_COUNT(val) bfin_write32(DMA39_CURR_BWL_COUNT, val) +#define bfin_read_DMA39_BWM_COUNT() bfin_read32(DMA39_BWM_COUNT) +#define bfin_write_DMA39_BWM_COUNT(val) bfin_write32(DMA39_BWM_COUNT, val) +#define bfin_read_DMA39_CURR_BWM_COUNT() bfin_read32(DMA39_CURR_BWM_COUNT) +#define bfin_write_DMA39_CURR_BWM_COUNT(val) bfin_write32(DMA39_CURR_BWM_COUNT, val) + +/* DMA Channel 40 Registers */ + +#define bfin_read_DMA40_NEXT_DESC_PTR() bfin_read32(DMA40_NEXT_DESC_PTR) +#define bfin_write_DMA40_NEXT_DESC_PTR(val) bfin_write32(DMA40_NEXT_DESC_PTR, val) +#define bfin_read_DMA40_START_ADDR() bfin_read32(DMA40_START_ADDR) +#define bfin_write_DMA40_START_ADDR(val) bfin_write32(DMA40_START_ADDR, val) +#define bfin_read_DMA40_CONFIG() bfin_read32(DMA40_CONFIG) +#define bfin_write_DMA40_CONFIG(val) bfin_write32(DMA40_CONFIG, val) +#define bfin_read_DMA40_X_COUNT() bfin_read32(DMA40_X_COUNT) +#define bfin_write_DMA40_X_COUNT(val) bfin_write32(DMA40_X_COUNT, val) +#define bfin_read_DMA40_X_MODIFY() bfin_read32(DMA40_X_MODIFY) +#define bfin_write_DMA40_X_MODIFY(val) bfin_write32(DMA40_X_MODIFY, val) +#define bfin_read_DMA40_Y_COUNT() bfin_read32(DMA40_Y_COUNT) +#define bfin_write_DMA40_Y_COUNT(val) bfin_write32(DMA40_Y_COUNT, val) +#define bfin_read_DMA40_Y_MODIFY() bfin_read32(DMA40_Y_MODIFY) +#define bfin_write_DMA40_Y_MODIFY(val) bfin_write32(DMA40_Y_MODIFY, val) +#define bfin_read_DMA40_CURR_DESC_PTR() bfin_read32(DMA40_CURR_DESC_PTR) +#define bfin_write_DMA40_CURR_DESC_PTR(val) bfin_write32(DMA40_CURR_DESC_PTR, val) +#define bfin_read_DMA40_PREV_DESC_PTR() bfin_read32(DMA40_PREV_DESC_PTR) +#define bfin_write_DMA40_PREV_DESC_PTR(val) bfin_write32(DMA40_PREV_DESC_PTR, val) +#define bfin_read_DMA40_CURR_ADDR() bfin_read32(DMA40_CURR_ADDR) +#define bfin_write_DMA40_CURR_ADDR(val) bfin_write32(DMA40_CURR_ADDR, val) +#define bfin_read_DMA40_IRQ_STATUS() bfin_read32(DMA40_IRQ_STATUS) +#define bfin_write_DMA40_IRQ_STATUS(val) bfin_write32(DMA40_IRQ_STATUS, val) +#define bfin_read_DMA40_CURR_X_COUNT() bfin_read32(DMA40_CURR_X_COUNT) +#define bfin_write_DMA40_CURR_X_COUNT(val) bfin_write32(DMA40_CURR_X_COUNT, val) +#define bfin_read_DMA40_CURR_Y_COUNT() bfin_read32(DMA40_CURR_Y_COUNT) +#define bfin_write_DMA40_CURR_Y_COUNT(val) bfin_write32(DMA40_CURR_Y_COUNT, val) +#define bfin_read_DMA40_BWL_COUNT() bfin_read32(DMA40_BWL_COUNT) +#define bfin_write_DMA40_BWL_COUNT(val) bfin_write32(DMA40_BWL_COUNT, val) +#define bfin_read_DMA40_CURR_BWL_COUNT() bfin_read32(DMA40_CURR_BWL_COUNT) +#define bfin_write_DMA40_CURR_BWL_COUNT(val) bfin_write32(DMA40_CURR_BWL_COUNT, val) +#define bfin_read_DMA40_BWM_COUNT() bfin_read32(DMA40_BWM_COUNT) +#define bfin_write_DMA40_BWM_COUNT(val) bfin_write32(DMA40_BWM_COUNT, val) +#define bfin_read_DMA40_CURR_BWM_COUNT() bfin_read32(DMA40_CURR_BWM_COUNT) +#define bfin_write_DMA40_CURR_BWM_COUNT(val) bfin_write32(DMA40_CURR_BWM_COUNT, val) + +/* DMA Channel 41 Registers */ + +#define bfin_read_DMA41_NEXT_DESC_PTR() bfin_read32(DMA41_NEXT_DESC_PTR) +#define bfin_write_DMA41_NEXT_DESC_PTR(val) bfin_write32(DMA41_NEXT_DESC_PTR, val) +#define bfin_read_DMA41_START_ADDR() bfin_read32(DMA41_START_ADDR) +#define bfin_write_DMA41_START_ADDR(val) bfin_write32(DMA41_START_ADDR, val) +#define bfin_read_DMA41_CONFIG() bfin_read32(DMA41_CONFIG) +#define bfin_write_DMA41_CONFIG(val) bfin_write32(DMA41_CONFIG, val) +#define bfin_read_DMA41_X_COUNT() bfin_read32(DMA41_X_COUNT) +#define bfin_write_DMA41_X_COUNT(val) bfin_write32(DMA41_X_COUNT, val) +#define bfin_read_DMA41_X_MODIFY() bfin_read32(DMA41_X_MODIFY) +#define bfin_write_DMA41_X_MODIFY(val) bfin_write32(DMA41_X_MODIFY, val) +#define bfin_read_DMA41_Y_COUNT() bfin_read32(DMA41_Y_COUNT) +#define bfin_write_DMA41_Y_COUNT(val) bfin_write32(DMA41_Y_COUNT, val) +#define bfin_read_DMA41_Y_MODIFY() bfin_read32(DMA41_Y_MODIFY) +#define bfin_write_DMA41_Y_MODIFY(val) bfin_write32(DMA41_Y_MODIFY, val) +#define bfin_read_DMA41_CURR_DESC_PTR() bfin_read32(DMA41_CURR_DESC_PTR) +#define bfin_write_DMA41_CURR_DESC_PTR(val) bfin_write32(DMA41_CURR_DESC_PTR, val) +#define bfin_read_DMA41_PREV_DESC_PTR() bfin_read32(DMA41_PREV_DESC_PTR) +#define bfin_write_DMA41_PREV_DESC_PTR(val) bfin_write32(DMA41_PREV_DESC_PTR, val) +#define bfin_read_DMA41_CURR_ADDR() bfin_read32(DMA41_CURR_ADDR) +#define bfin_write_DMA41_CURR_ADDR(val) bfin_write32(DMA41_CURR_ADDR, val) +#define bfin_read_DMA41_IRQ_STATUS() bfin_read32(DMA41_IRQ_STATUS) +#define bfin_write_DMA41_IRQ_STATUS(val) bfin_write32(DMA41_IRQ_STATUS, val) +#define bfin_read_DMA41_CURR_X_COUNT() bfin_read32(DMA41_CURR_X_COUNT) +#define bfin_write_DMA41_CURR_X_COUNT(val) bfin_write32(DMA41_CURR_X_COUNT, val) +#define bfin_read_DMA41_CURR_Y_COUNT() bfin_read32(DMA41_CURR_Y_COUNT) +#define bfin_write_DMA41_CURR_Y_COUNT(val) bfin_write32(DMA41_CURR_Y_COUNT, val) +#define bfin_read_DMA41_BWL_COUNT() bfin_read32(DMA41_BWL_COUNT) +#define bfin_write_DMA41_BWL_COUNT(val) bfin_write32(DMA41_BWL_COUNT, val) +#define bfin_read_DMA41_CURR_BWL_COUNT() bfin_read32(DMA41_CURR_BWL_COUNT) +#define bfin_write_DMA41_CURR_BWL_COUNT(val) bfin_write32(DMA41_CURR_BWL_COUNT, val) +#define bfin_read_DMA41_BWM_COUNT() bfin_read32(DMA41_BWM_COUNT) +#define bfin_write_DMA41_BWM_COUNT(val) bfin_write32(DMA41_BWM_COUNT, val) +#define bfin_read_DMA41_CURR_BWM_COUNT() bfin_read32(DMA41_CURR_BWM_COUNT) +#define bfin_write_DMA41_CURR_BWM_COUNT(val) bfin_write32(DMA41_CURR_BWM_COUNT, val) + +/* DMA Channel 42 Registers */ + +#define bfin_read_DMA42_NEXT_DESC_PTR() bfin_read32(DMA42_NEXT_DESC_PTR) +#define bfin_write_DMA42_NEXT_DESC_PTR(val) bfin_write32(DMA42_NEXT_DESC_PTR, val) +#define bfin_read_DMA42_START_ADDR() bfin_read32(DMA42_START_ADDR) +#define bfin_write_DMA42_START_ADDR(val) bfin_write32(DMA42_START_ADDR, val) +#define bfin_read_DMA42_CONFIG() bfin_read32(DMA42_CONFIG) +#define bfin_write_DMA42_CONFIG(val) bfin_write32(DMA42_CONFIG, val) +#define bfin_read_DMA42_X_COUNT() bfin_read32(DMA42_X_COUNT) +#define bfin_write_DMA42_X_COUNT(val) bfin_write32(DMA42_X_COUNT, val) +#define bfin_read_DMA42_X_MODIFY() bfin_read32(DMA42_X_MODIFY) +#define bfin_write_DMA42_X_MODIFY(val) bfin_write32(DMA42_X_MODIFY, val) +#define bfin_read_DMA42_Y_COUNT() bfin_read32(DMA42_Y_COUNT) +#define bfin_write_DMA42_Y_COUNT(val) bfin_write32(DMA42_Y_COUNT, val) +#define bfin_read_DMA42_Y_MODIFY() bfin_read32(DMA42_Y_MODIFY) +#define bfin_write_DMA42_Y_MODIFY(val) bfin_write32(DMA42_Y_MODIFY, val) +#define bfin_read_DMA42_CURR_DESC_PTR() bfin_read32(DMA42_CURR_DESC_PTR) +#define bfin_write_DMA42_CURR_DESC_PTR(val) bfin_write32(DMA42_CURR_DESC_PTR, val) +#define bfin_read_DMA42_PREV_DESC_PTR() bfin_read32(DMA42_PREV_DESC_PTR) +#define bfin_write_DMA42_PREV_DESC_PTR(val) bfin_write32(DMA42_PREV_DESC_PTR, val) +#define bfin_read_DMA42_CURR_ADDR() bfin_read32(DMA42_CURR_ADDR) +#define bfin_write_DMA42_CURR_ADDR(val) bfin_write32(DMA42_CURR_ADDR, val) +#define bfin_read_DMA42_IRQ_STATUS() bfin_read32(DMA42_IRQ_STATUS) +#define bfin_write_DMA42_IRQ_STATUS(val) bfin_write32(DMA42_IRQ_STATUS, val) +#define bfin_read_DMA42_CURR_X_COUNT() bfin_read32(DMA42_CURR_X_COUNT) +#define bfin_write_DMA42_CURR_X_COUNT(val) bfin_write32(DMA42_CURR_X_COUNT, val) +#define bfin_read_DMA42_CURR_Y_COUNT() bfin_read32(DMA42_CURR_Y_COUNT) +#define bfin_write_DMA42_CURR_Y_COUNT(val) bfin_write32(DMA42_CURR_Y_COUNT, val) +#define bfin_read_DMA42_BWL_COUNT() bfin_read32(DMA42_BWL_COUNT) +#define bfin_write_DMA42_BWL_COUNT(val) bfin_write32(DMA42_BWL_COUNT, val) +#define bfin_read_DMA42_CURR_BWL_COUNT() bfin_read32(DMA42_CURR_BWL_COUNT) +#define bfin_write_DMA42_CURR_BWL_COUNT(val) bfin_write32(DMA42_CURR_BWL_COUNT, val) +#define bfin_read_DMA42_BWM_COUNT() bfin_read32(DMA42_BWM_COUNT) +#define bfin_write_DMA42_BWM_COUNT(val) bfin_write32(DMA42_BWM_COUNT, val) +#define bfin_read_DMA42_CURR_BWM_COUNT() bfin_read32(DMA42_CURR_BWM_COUNT) +#define bfin_write_DMA42_CURR_BWM_COUNT(val) bfin_write32(DMA42_CURR_BWM_COUNT, val) + +/* DMA Channel 43 Registers */ + +#define bfin_read_DMA43_NEXT_DESC_PTR() bfin_read32(DMA43_NEXT_DESC_PTR) +#define bfin_write_DMA43_NEXT_DESC_PTR(val) bfin_write32(DMA43_NEXT_DESC_PTR, val) +#define bfin_read_DMA43_START_ADDR() bfin_read32(DMA43_START_ADDR) +#define bfin_write_DMA43_START_ADDR(val) bfin_write32(DMA43_START_ADDR, val) +#define bfin_read_DMA43_CONFIG() bfin_read32(DMA43_CONFIG) +#define bfin_write_DMA43_CONFIG(val) bfin_write32(DMA43_CONFIG, val) +#define bfin_read_DMA43_X_COUNT() bfin_read32(DMA43_X_COUNT) +#define bfin_write_DMA43_X_COUNT(val) bfin_write32(DMA43_X_COUNT, val) +#define bfin_read_DMA43_X_MODIFY() bfin_read32(DMA43_X_MODIFY) +#define bfin_write_DMA43_X_MODIFY(val) bfin_write32(DMA43_X_MODIFY, val) +#define bfin_read_DMA43_Y_COUNT() bfin_read32(DMA43_Y_COUNT) +#define bfin_write_DMA43_Y_COUNT(val) bfin_write32(DMA43_Y_COUNT, val) +#define bfin_read_DMA43_Y_MODIFY() bfin_read32(DMA43_Y_MODIFY) +#define bfin_write_DMA43_Y_MODIFY(val) bfin_write32(DMA43_Y_MODIFY, val) +#define bfin_read_DMA43_CURR_DESC_PTR() bfin_read32(DMA43_CURR_DESC_PTR) +#define bfin_write_DMA43_CURR_DESC_PTR(val) bfin_write32(DMA43_CURR_DESC_PTR, val) +#define bfin_read_DMA43_PREV_DESC_PTR() bfin_read32(DMA43_PREV_DESC_PTR) +#define bfin_write_DMA43_PREV_DESC_PTR(val) bfin_write32(DMA43_PREV_DESC_PTR, val) +#define bfin_read_DMA43_CURR_ADDR() bfin_read32(DMA43_CURR_ADDR) +#define bfin_write_DMA43_CURR_ADDR(val) bfin_write32(DMA43_CURR_ADDR, val) +#define bfin_read_DMA43_IRQ_STATUS() bfin_read32(DMA43_IRQ_STATUS) +#define bfin_write_DMA43_IRQ_STATUS(val) bfin_write32(DMA43_IRQ_STATUS, val) +#define bfin_read_DMA43_CURR_X_COUNT() bfin_read32(DMA43_CURR_X_COUNT) +#define bfin_write_DMA43_CURR_X_COUNT(val) bfin_write32(DMA43_CURR_X_COUNT, val) +#define bfin_read_DMA43_CURR_Y_COUNT() bfin_read32(DMA43_CURR_Y_COUNT) +#define bfin_write_DMA43_CURR_Y_COUNT(val) bfin_write32(DMA43_CURR_Y_COUNT, val) +#define bfin_read_DMA43_BWL_COUNT() bfin_read32(DMA43_BWL_COUNT) +#define bfin_write_DMA43_BWL_COUNT(val) bfin_write32(DMA43_BWL_COUNT, val) +#define bfin_read_DMA43_CURR_BWL_COUNT() bfin_read32(DMA43_CURR_BWL_COUNT) +#define bfin_write_DMA43_CURR_BWL_COUNT(val) bfin_write32(DMA43_CURR_BWL_COUNT, val) +#define bfin_read_DMA43_BWM_COUNT() bfin_read32(DMA43_BWM_COUNT) +#define bfin_write_DMA43_BWM_COUNT(val) bfin_write32(DMA43_BWM_COUNT, val) +#define bfin_read_DMA43_CURR_BWM_COUNT() bfin_read32(DMA43_CURR_BWM_COUNT) +#define bfin_write_DMA43_CURR_BWM_COUNT(val) bfin_write32(DMA43_CURR_BWM_COUNT, val) + +/* DMA Channel 44 Registers */ + +#define bfin_read_DMA44_NEXT_DESC_PTR() bfin_read32(DMA44_NEXT_DESC_PTR) +#define bfin_write_DMA44_NEXT_DESC_PTR(val) bfin_write32(DMA44_NEXT_DESC_PTR, val) +#define bfin_read_DMA44_START_ADDR() bfin_read32(DMA44_START_ADDR) +#define bfin_write_DMA44_START_ADDR(val) bfin_write32(DMA44_START_ADDR, val) +#define bfin_read_DMA44_CONFIG() bfin_read32(DMA44_CONFIG) +#define bfin_write_DMA44_CONFIG(val) bfin_write32(DMA44_CONFIG, val) +#define bfin_read_DMA44_X_COUNT() bfin_read32(DMA44_X_COUNT) +#define bfin_write_DMA44_X_COUNT(val) bfin_write32(DMA44_X_COUNT, val) +#define bfin_read_DMA44_X_MODIFY() bfin_read32(DMA44_X_MODIFY) +#define bfin_write_DMA44_X_MODIFY(val) bfin_write32(DMA44_X_MODIFY, val) +#define bfin_read_DMA44_Y_COUNT() bfin_read32(DMA44_Y_COUNT) +#define bfin_write_DMA44_Y_COUNT(val) bfin_write32(DMA44_Y_COUNT, val) +#define bfin_read_DMA44_Y_MODIFY() bfin_read32(DMA44_Y_MODIFY) +#define bfin_write_DMA44_Y_MODIFY(val) bfin_write32(DMA44_Y_MODIFY, val) +#define bfin_read_DMA44_CURR_DESC_PTR() bfin_read32(DMA44_CURR_DESC_PTR) +#define bfin_write_DMA44_CURR_DESC_PTR(val) bfin_write32(DMA44_CURR_DESC_PTR, val) +#define bfin_read_DMA44_PREV_DESC_PTR() bfin_read32(DMA44_PREV_DESC_PTR) +#define bfin_write_DMA44_PREV_DESC_PTR(val) bfin_write32(DMA44_PREV_DESC_PTR, val) +#define bfin_read_DMA44_CURR_ADDR() bfin_read32(DMA44_CURR_ADDR) +#define bfin_write_DMA44_CURR_ADDR(val) bfin_write32(DMA44_CURR_ADDR, val) +#define bfin_read_DMA44_IRQ_STATUS() bfin_read32(DMA44_IRQ_STATUS) +#define bfin_write_DMA44_IRQ_STATUS(val) bfin_write32(DMA44_IRQ_STATUS, val) +#define bfin_read_DMA44_CURR_X_COUNT() bfin_read32(DMA44_CURR_X_COUNT) +#define bfin_write_DMA44_CURR_X_COUNT(val) bfin_write32(DMA44_CURR_X_COUNT, val) +#define bfin_read_DMA44_CURR_Y_COUNT() bfin_read32(DMA44_CURR_Y_COUNT) +#define bfin_write_DMA44_CURR_Y_COUNT(val) bfin_write32(DMA44_CURR_Y_COUNT, val) +#define bfin_read_DMA44_BWL_COUNT() bfin_read32(DMA44_BWL_COUNT) +#define bfin_write_DMA44_BWL_COUNT(val) bfin_write32(DMA44_BWL_COUNT, val) +#define bfin_read_DMA44_CURR_BWL_COUNT() bfin_read32(DMA44_CURR_BWL_COUNT) +#define bfin_write_DMA44_CURR_BWL_COUNT(val) bfin_write32(DMA44_CURR_BWL_COUNT, val) +#define bfin_read_DMA44_BWM_COUNT() bfin_read32(DMA44_BWM_COUNT) +#define bfin_write_DMA44_BWM_COUNT(val) bfin_write32(DMA44_BWM_COUNT, val) +#define bfin_read_DMA44_CURR_BWM_COUNT() bfin_read32(DMA44_CURR_BWM_COUNT) +#define bfin_write_DMA44_CURR_BWM_COUNT(val) bfin_write32(DMA44_CURR_BWM_COUNT, val) + +/* DMA Channel 45 Registers */ + +#define bfin_read_DMA45_NEXT_DESC_PTR() bfin_read32(DMA45_NEXT_DESC_PTR) +#define bfin_write_DMA45_NEXT_DESC_PTR(val) bfin_write32(DMA45_NEXT_DESC_PTR, val) +#define bfin_read_DMA45_START_ADDR() bfin_read32(DMA45_START_ADDR) +#define bfin_write_DMA45_START_ADDR(val) bfin_write32(DMA45_START_ADDR, val) +#define bfin_read_DMA45_CONFIG() bfin_read32(DMA45_CONFIG) +#define bfin_write_DMA45_CONFIG(val) bfin_write32(DMA45_CONFIG, val) +#define bfin_read_DMA45_X_COUNT() bfin_read32(DMA45_X_COUNT) +#define bfin_write_DMA45_X_COUNT(val) bfin_write32(DMA45_X_COUNT, val) +#define bfin_read_DMA45_X_MODIFY() bfin_read32(DMA45_X_MODIFY) +#define bfin_write_DMA45_X_MODIFY(val) bfin_write32(DMA45_X_MODIFY, val) +#define bfin_read_DMA45_Y_COUNT() bfin_read32(DMA45_Y_COUNT) +#define bfin_write_DMA45_Y_COUNT(val) bfin_write32(DMA45_Y_COUNT, val) +#define bfin_read_DMA45_Y_MODIFY() bfin_read32(DMA45_Y_MODIFY) +#define bfin_write_DMA45_Y_MODIFY(val) bfin_write32(DMA45_Y_MODIFY, val) +#define bfin_read_DMA45_CURR_DESC_PTR() bfin_read32(DMA45_CURR_DESC_PTR) +#define bfin_write_DMA45_CURR_DESC_PTR(val) bfin_write32(DMA45_CURR_DESC_PTR, val) +#define bfin_read_DMA45_PREV_DESC_PTR() bfin_read32(DMA45_PREV_DESC_PTR) +#define bfin_write_DMA45_PREV_DESC_PTR(val) bfin_write32(DMA45_PREV_DESC_PTR, val) +#define bfin_read_DMA45_CURR_ADDR() bfin_read32(DMA45_CURR_ADDR) +#define bfin_write_DMA45_CURR_ADDR(val) bfin_write32(DMA45_CURR_ADDR, val) +#define bfin_read_DMA45_IRQ_STATUS() bfin_read32(DMA45_IRQ_STATUS) +#define bfin_write_DMA45_IRQ_STATUS(val) bfin_write32(DMA45_IRQ_STATUS, val) +#define bfin_read_DMA45_CURR_X_COUNT() bfin_read32(DMA45_CURR_X_COUNT) +#define bfin_write_DMA45_CURR_X_COUNT(val) bfin_write32(DMA45_CURR_X_COUNT, val) +#define bfin_read_DMA45_CURR_Y_COUNT() bfin_read32(DMA45_CURR_Y_COUNT) +#define bfin_write_DMA45_CURR_Y_COUNT(val) bfin_write32(DMA45_CURR_Y_COUNT, val) +#define bfin_read_DMA45_BWL_COUNT() bfin_read32(DMA45_BWL_COUNT) +#define bfin_write_DMA45_BWL_COUNT(val) bfin_write32(DMA45_BWL_COUNT, val) +#define bfin_read_DMA45_CURR_BWL_COUNT() bfin_read32(DMA45_CURR_BWL_COUNT) +#define bfin_write_DMA45_CURR_BWL_COUNT(val) bfin_write32(DMA45_CURR_BWL_COUNT, val) +#define bfin_read_DMA45_BWM_COUNT() bfin_read32(DMA45_BWM_COUNT) +#define bfin_write_DMA45_BWM_COUNT(val) bfin_write32(DMA45_BWM_COUNT, val) +#define bfin_read_DMA45_CURR_BWM_COUNT() bfin_read32(DMA45_CURR_BWM_COUNT) +#define bfin_write_DMA45_CURR_BWM_COUNT(val) bfin_write32(DMA45_CURR_BWM_COUNT, val) + +/* DMA Channel 46 Registers */ + +#define bfin_read_DMA46_NEXT_DESC_PTR() bfin_read32(DMA46_NEXT_DESC_PTR) +#define bfin_write_DMA46_NEXT_DESC_PTR(val) bfin_write32(DMA46_NEXT_DESC_PTR, val) +#define bfin_read_DMA46_START_ADDR() bfin_read32(DMA46_START_ADDR) +#define bfin_write_DMA46_START_ADDR(val) bfin_write32(DMA46_START_ADDR, val) +#define bfin_read_DMA46_CONFIG() bfin_read32(DMA46_CONFIG) +#define bfin_write_DMA46_CONFIG(val) bfin_write32(DMA46_CONFIG, val) +#define bfin_read_DMA46_X_COUNT() bfin_read32(DMA46_X_COUNT) +#define bfin_write_DMA46_X_COUNT(val) bfin_write32(DMA46_X_COUNT, val) +#define bfin_read_DMA46_X_MODIFY() bfin_read32(DMA46_X_MODIFY) +#define bfin_write_DMA46_X_MODIFY(val) bfin_write32(DMA46_X_MODIFY, val) +#define bfin_read_DMA46_Y_COUNT() bfin_read32(DMA46_Y_COUNT) +#define bfin_write_DMA46_Y_COUNT(val) bfin_write32(DMA46_Y_COUNT, val) +#define bfin_read_DMA46_Y_MODIFY() bfin_read32(DMA46_Y_MODIFY) +#define bfin_write_DMA46_Y_MODIFY(val) bfin_write32(DMA46_Y_MODIFY, val) +#define bfin_read_DMA46_CURR_DESC_PTR() bfin_read32(DMA46_CURR_DESC_PTR) +#define bfin_write_DMA46_CURR_DESC_PTR(val) bfin_write32(DMA46_CURR_DESC_PTR, val) +#define bfin_read_DMA46_PREV_DESC_PTR() bfin_read32(DMA46_PREV_DESC_PTR) +#define bfin_write_DMA46_PREV_DESC_PTR(val) bfin_write32(DMA46_PREV_DESC_PTR, val) +#define bfin_read_DMA46_CURR_ADDR() bfin_read32(DMA46_CURR_ADDR) +#define bfin_write_DMA46_CURR_ADDR(val) bfin_write32(DMA46_CURR_ADDR, val) +#define bfin_read_DMA46_IRQ_STATUS() bfin_read32(DMA46_IRQ_STATUS) +#define bfin_write_DMA46_IRQ_STATUS(val) bfin_write32(DMA46_IRQ_STATUS, val) +#define bfin_read_DMA46_CURR_X_COUNT() bfin_read32(DMA46_CURR_X_COUNT) +#define bfin_write_DMA46_CURR_X_COUNT(val) bfin_write32(DMA46_CURR_X_COUNT, val) +#define bfin_read_DMA46_CURR_Y_COUNT() bfin_read32(DMA46_CURR_Y_COUNT) +#define bfin_write_DMA46_CURR_Y_COUNT(val) bfin_write32(DMA46_CURR_Y_COUNT, val) +#define bfin_read_DMA46_BWL_COUNT() bfin_read32(DMA46_BWL_COUNT) +#define bfin_write_DMA46_BWL_COUNT(val) bfin_write32(DMA46_BWL_COUNT, val) +#define bfin_read_DMA46_CURR_BWL_COUNT() bfin_read32(DMA46_CURR_BWL_COUNT) +#define bfin_write_DMA46_CURR_BWL_COUNT(val) bfin_write32(DMA46_CURR_BWL_COUNT, val) +#define bfin_read_DMA46_BWM_COUNT() bfin_read32(DMA46_BWM_COUNT) +#define bfin_write_DMA46_BWM_COUNT(val) bfin_write32(DMA46_BWM_COUNT, val) +#define bfin_read_DMA46_CURR_BWM_COUNT() bfin_read32(DMA46_CURR_BWM_COUNT) +#define bfin_write_DMA46_CURR_BWM_COUNT(val) bfin_write32(DMA46_CURR_BWM_COUNT, val) + + +/* EPPI1 Registers */ + + +/* Port Interrubfin_read_()t 0 Registers (32-bit) */ + +#define bfin_read_PINT0_MASK_SET() bfin_read32(PINT0_MASK_SET) +#define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val) +#define bfin_read_PINT0_MASK_CLEAR() bfin_read32(PINT0_MASK_CLEAR) +#define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val) +#define bfin_read_PINT0_REQUEST() bfin_read32(PINT0_REQUEST) +#define bfin_write_PINT0_REQUEST(val) bfin_write32(PINT0_REQUEST, val) +#define bfin_read_PINT0_ASSIGN() bfin_read32(PINT0_ASSIGN) +#define bfin_write_PINT0_ASSIGN(val) bfin_write32(PINT0_ASSIGN, val) +#define bfin_read_PINT0_EDGE_SET() bfin_read32(PINT0_EDGE_SET) +#define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val) +#define bfin_read_PINT0_EDGE_CLEAR() bfin_read32(PINT0_EDGE_CLEAR) +#define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val) +#define bfin_read_PINT0_INVERT_SET() bfin_read32(PINT0_INVERT_SET) +#define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val) +#define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR) +#define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val) +#define bfin_read_PINT0_PINSTATE() bfin_read32(PINT0_PINSTATE) +#define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val) +#define bfin_read_PINT0_LATCH() bfin_read32(PINT0_LATCH) +#define bfin_write_PINT0_LATCH(val) bfin_write32(PINT0_LATCH, val) + +/* Port Interrubfin_read_()t 1 Registers (32-bit) */ + +#define bfin_read_PINT1_MASK_SET() bfin_read32(PINT1_MASK_SET) +#define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val) +#define bfin_read_PINT1_MASK_CLEAR() bfin_read32(PINT1_MASK_CLEAR) +#define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val) +#define bfin_read_PINT1_REQUEST() bfin_read32(PINT1_REQUEST) +#define bfin_write_PINT1_REQUEST(val) bfin_write32(PINT1_REQUEST, val) +#define bfin_read_PINT1_ASSIGN() bfin_read32(PINT1_ASSIGN) +#define bfin_write_PINT1_ASSIGN(val) bfin_write32(PINT1_ASSIGN, val) +#define bfin_read_PINT1_EDGE_SET() bfin_read32(PINT1_EDGE_SET) +#define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val) +#define bfin_read_PINT1_EDGE_CLEAR() bfin_read32(PINT1_EDGE_CLEAR) +#define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val) +#define bfin_read_PINT1_INVERT_SET() bfin_read32(PINT1_INVERT_SET) +#define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val) +#define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR) +#define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val) +#define bfin_read_PINT1_PINSTATE() bfin_read32(PINT1_PINSTATE) +#define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val) +#define bfin_read_PINT1_LATCH() bfin_read32(PINT1_LATCH) +#define bfin_write_PINT1_LATCH(val) bfin_write32(PINT1_LATCH, val) + +/* Port Interrubfin_read_()t 2 Registers (32-bit) */ + +#define bfin_read_PINT2_MASK_SET() bfin_read32(PINT2_MASK_SET) +#define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val) +#define bfin_read_PINT2_MASK_CLEAR() bfin_read32(PINT2_MASK_CLEAR) +#define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val) +#define bfin_read_PINT2_REQUEST() bfin_read32(PINT2_REQUEST) +#define bfin_write_PINT2_REQUEST(val) bfin_write32(PINT2_REQUEST, val) +#define bfin_read_PINT2_ASSIGN() bfin_read32(PINT2_ASSIGN) +#define bfin_write_PINT2_ASSIGN(val) bfin_write32(PINT2_ASSIGN, val) +#define bfin_read_PINT2_EDGE_SET() bfin_read32(PINT2_EDGE_SET) +#define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val) +#define bfin_read_PINT2_EDGE_CLEAR() bfin_read32(PINT2_EDGE_CLEAR) +#define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val) +#define bfin_read_PINT2_INVERT_SET() bfin_read32(PINT2_INVERT_SET) +#define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val) +#define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR) +#define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val) +#define bfin_read_PINT2_PINSTATE() bfin_read32(PINT2_PINSTATE) +#define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val) +#define bfin_read_PINT2_LATCH() bfin_read32(PINT2_LATCH) +#define bfin_write_PINT2_LATCH(val) bfin_write32(PINT2_LATCH, val) + +/* Port Interrubfin_read_()t 3 Registers (32-bit) */ + +#define bfin_read_PINT3_MASK_SET() bfin_read32(PINT3_MASK_SET) +#define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val) +#define bfin_read_PINT3_MASK_CLEAR() bfin_read32(PINT3_MASK_CLEAR) +#define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val) +#define bfin_read_PINT3_REQUEST() bfin_read32(PINT3_REQUEST) +#define bfin_write_PINT3_REQUEST(val) bfin_write32(PINT3_REQUEST, val) +#define bfin_read_PINT3_ASSIGN() bfin_read32(PINT3_ASSIGN) +#define bfin_write_PINT3_ASSIGN(val) bfin_write32(PINT3_ASSIGN, val) +#define bfin_read_PINT3_EDGE_SET() bfin_read32(PINT3_EDGE_SET) +#define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val) +#define bfin_read_PINT3_EDGE_CLEAR() bfin_read32(PINT3_EDGE_CLEAR) +#define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val) +#define bfin_read_PINT3_INVERT_SET() bfin_read32(PINT3_INVERT_SET) +#define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val) +#define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR) +#define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val) +#define bfin_read_PINT3_PINSTATE() bfin_read32(PINT3_PINSTATE) +#define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val) +#define bfin_read_PINT3_LATCH() bfin_read32(PINT3_LATCH) +#define bfin_write_PINT3_LATCH(val) bfin_write32(PINT3_LATCH, val) + +/* Port Interrubfin_read_()t 4 Registers (32-bit) */ + +#define bfin_read_PINT4_MASK_SET() bfin_read32(PINT4_MASK_SET) +#define bfin_write_PINT4_MASK_SET(val) bfin_write32(PINT4_MASK_SET, val) +#define bfin_read_PINT4_MASK_CLEAR() bfin_read32(PINT4_MASK_CLEAR) +#define bfin_write_PINT4_MASK_CLEAR(val) bfin_write32(PINT4_MASK_CLEAR, val) +#define bfin_read_PINT4_REQUEST() bfin_read32(PINT4_REQUEST) +#define bfin_write_PINT4_REQUEST(val) bfin_write32(PINT4_REQUEST, val) +#define bfin_read_PINT4_ASSIGN() bfin_read32(PINT4_ASSIGN) +#define bfin_write_PINT4_ASSIGN(val) bfin_write32(PINT4_ASSIGN, val) +#define bfin_read_PINT4_EDGE_SET() bfin_read32(PINT4_EDGE_SET) +#define bfin_write_PINT4_EDGE_SET(val) bfin_write32(PINT4_EDGE_SET, val) +#define bfin_read_PINT4_EDGE_CLEAR() bfin_read32(PINT4_EDGE_CLEAR) +#define bfin_write_PINT4_EDGE_CLEAR(val) bfin_write32(PINT4_EDGE_CLEAR, val) +#define bfin_read_PINT4_INVERT_SET() bfin_read32(PINT4_INVERT_SET) +#define bfin_write_PINT4_INVERT_SET(val) bfin_write32(PINT4_INVERT_SET, val) +#define bfin_read_PINT4_INVERT_CLEAR() bfin_read32(PINT4_INVERT_CLEAR) +#define bfin_write_PINT4_INVERT_CLEAR(val) bfin_write32(PINT4_INVERT_CLEAR, val) +#define bfin_read_PINT4_PINSTATE() bfin_read32(PINT4_PINSTATE) +#define bfin_write_PINT4_PINSTATE(val) bfin_write32(PINT4_PINSTATE, val) +#define bfin_read_PINT4_LATCH() bfin_read32(PINT4_LATCH) +#define bfin_write_PINT4_LATCH(val) bfin_write32(PINT4_LATCH, val) + +/* Port Interrubfin_read_()t 5 Registers (32-bit) */ + +#define bfin_read_PINT5_MASK_SET() bfin_read32(PINT5_MASK_SET) +#define bfin_write_PINT5_MASK_SET(val) bfin_write32(PINT5_MASK_SET, val) +#define bfin_read_PINT5_MASK_CLEAR() bfin_read32(PINT5_MASK_CLEAR) +#define bfin_write_PINT5_MASK_CLEAR(val) bfin_write32(PINT5_MASK_CLEAR, val) +#define bfin_read_PINT5_REQUEST() bfin_read32(PINT5_REQUEST) +#define bfin_write_PINT5_REQUEST(val) bfin_write32(PINT5_REQUEST, val) +#define bfin_read_PINT5_ASSIGN() bfin_read32(PINT5_ASSIGN) +#define bfin_write_PINT5_ASSIGN(val) bfin_write32(PINT5_ASSIGN, val) +#define bfin_read_PINT5_EDGE_SET() bfin_read32(PINT5_EDGE_SET) +#define bfin_write_PINT5_EDGE_SET(val) bfin_write32(PINT5_EDGE_SET, val) +#define bfin_read_PINT5_EDGE_CLEAR() bfin_read32(PINT5_EDGE_CLEAR) +#define bfin_write_PINT5_EDGE_CLEAR(val) bfin_write32(PINT5_EDGE_CLEAR, val) +#define bfin_read_PINT5_INVERT_SET() bfin_read32(PINT5_INVERT_SET) +#define bfin_write_PINT5_INVERT_SET(val) bfin_write32(PINT5_INVERT_SET, val) +#define bfin_read_PINT5_INVERT_CLEAR() bfin_read32(PINT5_INVERT_CLEAR) +#define bfin_write_PINT5_INVERT_CLEAR(val) bfin_write32(PINT5_INVERT_CLEAR, val) +#define bfin_read_PINT5_PINSTATE() bfin_read32(PINT5_PINSTATE) +#define bfin_write_PINT5_PINSTATE(val) bfin_write32(PINT5_PINSTATE, val) +#define bfin_read_PINT5_LATCH() bfin_read32(PINT5_LATCH) +#define bfin_write_PINT5_LATCH(val) bfin_write32(PINT5_LATCH, val) + +/* Port A Registers */ + +#define bfin_read_PORTA_FER() bfin_read32(PORTA_FER) +#define bfin_write_PORTA_FER(val) bfin_write32(PORTA_FER, val) +#define bfin_read_PORTA_FER_SET() bfin_read32(PORTA_FER_SET) +#define bfin_write_PORTA_FER_SET(val) bfin_write32(PORTA_FER_SET, val) +#define bfin_read_PORTA_FER_CLEAR() bfin_read32(PORTA_FER_CLEAR) +#define bfin_write_PORTA_FER_CLEAR(val) bfin_write32(PORTA_FER_CLEAR, val) +#define bfin_read_PORTA() bfin_read32(PORTA) +#define bfin_write_PORTA(val) bfin_write32(PORTA, val) +#define bfin_read_PORTA_SET() bfin_read32(PORTA_SET) +#define bfin_write_PORTA_SET(val) bfin_write32(PORTA_SET, val) +#define bfin_read_PORTA_CLEAR() bfin_read32(PORTA_CLEAR) +#define bfin_write_PORTA_CLEAR(val) bfin_write32(PORTA_CLEAR, val) +#define bfin_read_PORTA_DIR() bfin_read32(PORTA_DIR) +#define bfin_write_PORTA_DIR(val) bfin_write32(PORTA_DIR, val) +#define bfin_read_PORTA_DIR_SET() bfin_read32(PORTA_DIR_SET) +#define bfin_write_PORTA_DIR_SET(val) bfin_write32(PORTA_DIR_SET, val) +#define bfin_read_PORTA_DIR_CLEAR() bfin_read32(PORTA_DIR_CLEAR) +#define bfin_write_PORTA_DIR_CLEAR(val) bfin_write32(PORTA_DIR_CLEAR, val) +#define bfin_read_PORTA_INEN() bfin_read32(PORTA_INEN) +#define bfin_write_PORTA_INEN(val) bfin_write32(PORTA_INEN, val) +#define bfin_read_PORTA_INEN_SET() bfin_read32(PORTA_INEN_SET) +#define bfin_write_PORTA_INEN_SET(val) bfin_write32(PORTA_INEN_SET, val) +#define bfin_read_PORTA_INEN_CLEAR() bfin_read32(PORTA_INEN_CLEAR) +#define bfin_write_PORTA_INEN_CLEAR(val) bfin_write32(PORTA_INEN_CLEAR, val) +#define bfin_read_PORTA_MUX() bfin_read32(PORTA_MUX) +#define bfin_write_PORTA_MUX(val) bfin_write32(PORTA_MUX, val) +#define bfin_read_PORTA_DATA_TGL() bfin_read32(PORTA_DATA_TGL) +#define bfin_write_PORTA_DATA_TGL(val) bfin_write32(PORTA_DATA_TGL, val) +#define bfin_read_PORTA_POL() bfin_read32(PORTA_POL) +#define bfin_write_PORTA_POL(val) bfin_write32(PORTA_POL, val) +#define bfin_read_PORTA_POL_SET() bfin_read32(PORTA_POL_SET) +#define bfin_write_PORTA_POL_SET(val) bfin_write32(PORTA_POL_SET, val) +#define bfin_read_PORTA_POL_CLEAR() bfin_read32(PORTA_POL_CLEAR) +#define bfin_write_PORTA_POL_CLEAR(val) bfin_write32(PORTA_POL_CLEAR, val) +#define bfin_read_PORTA_LOCK() bfin_read32(PORTA_LOCK) +#define bfin_write_PORTA_LOCK(val) bfin_write32(PORTA_LOCK, val) +#define bfin_read_PORTA_REVID() bfin_read32(PORTA_REVID) +#define bfin_write_PORTA_REVID(val) bfin_write32(PORTA_REVID, val) + + + +/* Port B Registers */ +#define bfin_read_PORTB_FER() bfin_read32(PORTB_FER) +#define bfin_write_PORTB_FER(val) bfin_write32(PORTB_FER, val) +#define bfin_read_PORTB_FER_SET() bfin_read32(PORTB_FER_SET) +#define bfin_write_PORTB_FER_SET(val) bfin_write32(PORTB_FER_SET, val) +#define bfin_read_PORTB_FER_CLEAR() bfin_read32(PORTB_FER_CLEAR) +#define bfin_write_PORTB_FER_CLEAR(val) bfin_write32(PORTB_FER_CLEAR, val) +#define bfin_read_PORTB() bfin_read32(PORTB) +#define bfin_write_PORTB(val) bfin_write32(PORTB, val) +#define bfin_read_PORTB_SET() bfin_read32(PORTB_SET) +#define bfin_write_PORTB_SET(val) bfin_write32(PORTB_SET, val) +#define bfin_read_PORTB_CLEAR() bfin_read32(PORTB_CLEAR) +#define bfin_write_PORTB_CLEAR(val) bfin_write32(PORTB_CLEAR, val) +#define bfin_read_PORTB_DIR() bfin_read32(PORTB_DIR) +#define bfin_write_PORTB_DIR(val) bfin_write32(PORTB_DIR, val) +#define bfin_read_PORTB_DIR_SET() bfin_read32(PORTB_DIR_SET) +#define bfin_write_PORTB_DIR_SET(val) bfin_write32(PORTB_DIR_SET, val) +#define bfin_read_PORTB_DIR_CLEAR() bfin_read32(PORTB_DIR_CLEAR) +#define bfin_write_PORTB_DIR_CLEAR(val) bfin_write32(PORTB_DIR_CLEAR, val) +#define bfin_read_PORTB_INEN() bfin_read32(PORTB_INEN) +#define bfin_write_PORTB_INEN(val) bfin_write32(PORTB_INEN, val) +#define bfin_read_PORTB_INEN_SET() bfin_read32(PORTB_INEN_SET) +#define bfin_write_PORTB_INEN_SET(val) bfin_write32(PORTB_INEN_SET, val) +#define bfin_read_PORTB_INEN_CLEAR() bfin_read32(PORTB_INEN_CLEAR) +#define bfin_write_PORTB_INEN_CLEAR(val) bfin_write32(PORTB_INEN_CLEAR, val) +#define bfin_read_PORTB_MUX() bfin_read32(PORTB_MUX) +#define bfin_write_PORTB_MUX(val) bfin_write32(PORTB_MUX, val) +#define bfin_read_PORTB_DATA_TGL() bfin_read32(PORTB_DATA_TGL) +#define bfin_write_PORTB_DATA_TGL(val) bfin_write32(PORTB_DATA_TGL, val) +#define bfin_read_PORTB_POL() bfin_read32(PORTB_POL) +#define bfin_write_PORTB_POL(val) bfin_write32(PORTB_POL, val) +#define bfin_read_PORTB_POL_SET() bfin_read32(PORTB_POL_SET) +#define bfin_write_PORTB_POL_SET(val) bfin_write32(PORTB_POL_SET, val) +#define bfin_read_PORTB_POL_CLEAR() bfin_read32(PORTB_POL_CLEAR) +#define bfin_write_PORTB_POL_CLEAR(val) bfin_write32(PORTB_POL_CLEAR, val) +#define bfin_read_PORTB_LOCK() bfin_read32(PORTB_LOCK) +#define bfin_write_PORTB_LOCK(val) bfin_write32(PORTB_LOCK, val) +#define bfin_read_PORTB_REVID() bfin_read32(PORTB_REVID) +#define bfin_write_PORTB_REVID(val) bfin_write32(PORTB_REVID, val) + + +/* Port C Registers */ +#define bfin_read_PORTC_FER() bfin_read32(PORTC_FER) +#define bfin_write_PORTC_FER(val) bfin_write32(PORTC_FER, val) +#define bfin_read_PORTC_FER_SET() bfin_read32(PORTC_FER_SET) +#define bfin_write_PORTC_FER_SET(val) bfin_write32(PORTC_FER_SET, val) +#define bfin_read_PORTC_FER_CLEAR() bfin_read32(PORTC_FER_CLEAR) +#define bfin_write_PORTC_FER_CLEAR(val) bfin_write32(PORTC_FER_CLEAR, val) +#define bfin_read_PORTC() bfin_read32(PORTC) +#define bfin_write_PORTC(val) bfin_write32(PORTC, val) +#define bfin_read_PORTC_SET() bfin_read32(PORTC_SET) +#define bfin_write_PORTC_SET(val) bfin_write32(PORTC_SET, val) +#define bfin_read_PORTC_CLEAR() bfin_read32(PORTC_CLEAR) +#define bfin_write_PORTC_CLEAR(val) bfin_write32(PORTC_CLEAR, val) +#define bfin_read_PORTC_DIR() bfin_read32(PORTC_DIR) +#define bfin_write_PORTC_DIR(val) bfin_write32(PORTC_DIR, val) +#define bfin_read_PORTC_DIR_SET() bfin_read32(PORTC_DIR_SET) +#define bfin_write_PORTC_DIR_SET(val) bfin_write32(PORTC_DIR_SET, val) +#define bfin_read_PORTC_DIR_CLEAR() bfin_read32(PORTC_DIR_CLEAR) +#define bfin_write_PORTC_DIR_CLEAR(val) bfin_write32(PORTC_DIR_CLEAR, val) +#define bfin_read_PORTC_INEN() bfin_read32(PORTC_INEN) +#define bfin_write_PORTC_INEN(val) bfin_write32(PORTC_INEN, val) +#define bfin_read_PORTC_INEN_SET() bfin_read32(PORTC_INEN_SET) +#define bfin_write_PORTC_INEN_SET(val) bfin_write32(PORTC_INEN_SET, val) +#define bfin_read_PORTC_INEN_CLEAR() bfin_read32(PORTC_INEN_CLEAR) +#define bfin_write_PORTC_INEN_CLEAR(val) bfin_write32(PORTC_INEN_CLEAR, val) +#define bfin_read_PORTC_MUX() bfin_read32(PORTC_MUX) +#define bfin_write_PORTC_MUX(val) bfin_write32(PORTC_MUX, val) +#define bfin_read_PORTC_DATA_TGL() bfin_read32(PORTC_DATA_TGL) +#define bfin_write_PORTC_DATA_TGL(val) bfin_write32(PORTC_DATA_TGL, val) +#define bfin_read_PORTC_POL() bfin_read32(PORTC_POL) +#define bfin_write_PORTC_POL(val) bfin_write32(PORTC_POL, val) +#define bfin_read_PORTC_POL_SET() bfin_read32(PORTC_POL_SET) +#define bfin_write_PORTC_POL_SET(val) bfin_write32(PORTC_POL_SET, val) +#define bfin_read_PORTC_POL_CLEAR() bfin_read32(PORTC_POL_CLEAR) +#define bfin_write_PORTC_POL_CLEAR(val) bfin_write32(PORTC_POL_CLEAR, val) +#define bfin_read_PORTC_LOCK() bfin_read32(PORTC_LOCK) +#define bfin_write_PORTC_LOCK(val) bfin_write32(PORTC_LOCK, val) +#define bfin_read_PORTC_REVID() bfin_read32(PORTC_REVID) +#define bfin_write_PORTC_REVID(val) bfin_write32(PORTC_REVID, val) + + +/* Port D Registers */ +#define bfin_read_PORTD_FER() bfin_read32(PORTD_FER) +#define bfin_write_PORTD_FER(val) bfin_write32(PORTD_FER, val) +#define bfin_read_PORTD_FER_SET() bfin_read32(PORTD_FER_SET) +#define bfin_write_PORTD_FER_SET(val) bfin_write32(PORTD_FER_SET, val) +#define bfin_read_PORTD_FER_CLEAR() bfin_read32(PORTD_FER_CLEAR) +#define bfin_write_PORTD_FER_CLEAR(val) bfin_write32(PORTD_FER_CLEAR, val) +#define bfin_read_PORTD() bfin_read32(PORTD) +#define bfin_write_PORTD(val) bfin_write32(PORTD, val) +#define bfin_read_PORTD_SET() bfin_read32(PORTD_SET) +#define bfin_write_PORTD_SET(val) bfin_write32(PORTD_SET, val) +#define bfin_read_PORTD_CLEAR() bfin_read32(PORTD_CLEAR) +#define bfin_write_PORTD_CLEAR(val) bfin_write32(PORTD_CLEAR, val) +#define bfin_read_PORTD_DIR() bfin_read32(PORTD_DIR) +#define bfin_write_PORTD_DIR(val) bfin_write32(PORTD_DIR, val) +#define bfin_read_PORTD_DIR_SET() bfin_read32(PORTD_DIR_SET) +#define bfin_write_PORTD_DIR_SET(val) bfin_write32(PORTD_DIR_SET, val) +#define bfin_read_PORTD_DIR_CLEAR() bfin_read32(PORTD_DIR_CLEAR) +#define bfin_write_PORTD_DIR_CLEAR(val) bfin_write32(PORTD_DIR_CLEAR, val) +#define bfin_read_PORTD_INEN() bfin_read32(PORTD_INEN) +#define bfin_write_PORTD_INEN(val) bfin_write32(PORTD_INEN, val) +#define bfin_read_PORTD_INEN_SET() bfin_read32(PORTD_INEN_SET) +#define bfin_write_PORTD_INEN_SET(val) bfin_write32(PORTD_INEN_SET, val) +#define bfin_read_PORTD_INEN_CLEAR() bfin_read32(PORTD_INEN_CLEAR) +#define bfin_write_PORTD_INEN_CLEAR(val) bfin_write32(PORTD_INEN_CLEAR, val) +#define bfin_read_PORTD_MUX() bfin_read32(PORTD_MUX) +#define bfin_write_PORTD_MUX(val) bfin_write32(PORTD_MUX, val) +#define bfin_read_PORTD_DATA_TGL() bfin_read32(PORTD_DATA_TGL) +#define bfin_write_PORTD_DATA_TGL(val) bfin_write32(PORTD_DATA_TGL, val) +#define bfin_read_PORTD_POL() bfin_read32(PORTD_POL) +#define bfin_write_PORTD_POL(val) bfin_write32(PORTD_POL, val) +#define bfin_read_PORTD_POL_SET() bfin_read32(PORTD_POL_SET) +#define bfin_write_PORTD_POL_SET(val) bfin_write32(PORTD_POL_SET, val) +#define bfin_read_PORTD_POL_CLEAR() bfin_read32(PORTD_POL_CLEAR) +#define bfin_write_PORTD_POL_CLEAR(val) bfin_write32(PORTD_POL_CLEAR, val) +#define bfin_read_PORTD_LOCK() bfin_read32(PORTD_LOCK) +#define bfin_write_PORTD_LOCK(val) bfin_write32(PORTD_LOCK, val) +#define bfin_read_PORTD_REVID() bfin_read32(PORTD_REVID) +#define bfin_write_PORTD_REVID(val) bfin_write32(PORTD_REVID, val) + + +/* Port E Registers */ +#define bfin_read_PORTE_FER() bfin_read32(PORTE_FER) +#define bfin_write_PORTE_FER(val) bfin_write32(PORTE_FER, val) +#define bfin_read_PORTE_FER_SET() bfin_read32(PORTE_FER_SET) +#define bfin_write_PORTE_FER_SET(val) bfin_write32(PORTE_FER_SET, val) +#define bfin_read_PORTE_FER_CLEAR() bfin_read32(PORTE_FER_CLEAR) +#define bfin_write_PORTE_FER_CLEAR(val) bfin_write32(PORTE_FER_CLEAR, val) +#define bfin_read_PORTE() bfin_read32(PORTE) +#define bfin_write_PORTE(val) bfin_write32(PORTE, val) +#define bfin_read_PORTE_SET() bfin_read32(PORTE_SET) +#define bfin_write_PORTE_SET(val) bfin_write32(PORTE_SET, val) +#define bfin_read_PORTE_CLEAR() bfin_read32(PORTE_CLEAR) +#define bfin_write_PORTE_CLEAR(val) bfin_write32(PORTE_CLEAR, val) +#define bfin_read_PORTE_DIR() bfin_read32(PORTE_DIR) +#define bfin_write_PORTE_DIR(val) bfin_write32(PORTE_DIR, val) +#define bfin_read_PORTE_DIR_SET() bfin_read32(PORTE_DIR_SET) +#define bfin_write_PORTE_DIR_SET(val) bfin_write32(PORTE_DIR_SET, val) +#define bfin_read_PORTE_DIR_CLEAR() bfin_read32(PORTE_DIR_CLEAR) +#define bfin_write_PORTE_DIR_CLEAR(val) bfin_write32(PORTE_DIR_CLEAR, val) +#define bfin_read_PORTE_INEN() bfin_read32(PORTE_INEN) +#define bfin_write_PORTE_INEN(val) bfin_write32(PORTE_INEN, val) +#define bfin_read_PORTE_INEN_SET() bfin_read32(PORTE_INEN_SET) +#define bfin_write_PORTE_INEN_SET(val) bfin_write32(PORTE_INEN_SET, val) +#define bfin_read_PORTE_INEN_CLEAR() bfin_read32(PORTE_INEN_CLEAR) +#define bfin_write_PORTE_INEN_CLEAR(val) bfin_write32(PORTE_INEN_CLEAR, val) +#define bfin_read_PORTE_MUX() bfin_read32(PORTE_MUX) +#define bfin_write_PORTE_MUX(val) bfin_write32(PORTE_MUX, val) +#define bfin_read_PORTE_DATA_TGL() bfin_read32(PORTE_DATA_TGL) +#define bfin_write_PORTE_DATA_TGL(val) bfin_write32(PORTE_DATA_TGL, val) +#define bfin_read_PORTE_POL() bfin_read32(PORTE_POL) +#define bfin_write_PORTE_POL(val) bfin_write32(PORTE_POL, val) +#define bfin_read_PORTE_POL_SET() bfin_read32(PORTE_POL_SET) +#define bfin_write_PORTE_POL_SET(val) bfin_write32(PORTE_POL_SET, val) +#define bfin_read_PORTE_POL_CLEAR() bfin_read32(PORTE_POL_CLEAR) +#define bfin_write_PORTE_POL_CLEAR(val) bfin_write32(PORTE_POL_CLEAR, val) +#define bfin_read_PORTE_LOCK() bfin_read32(PORTE_LOCK) +#define bfin_write_PORTE_LOCK(val) bfin_write32(PORTE_LOCK, val) +#define bfin_read_PORTE_REVID() bfin_read32(PORTE_REVID) +#define bfin_write_PORTE_REVID(val) bfin_write32(PORTE_REVID, val) + + +/* Port F Registers */ +#define bfin_read_PORTF_FER() bfin_read32(PORTF_FER) +#define bfin_write_PORTF_FER(val) bfin_write32(PORTF_FER, val) +#define bfin_read_PORTF_FER_SET() bfin_read32(PORTF_FER_SET) +#define bfin_write_PORTF_FER_SET(val) bfin_write32(PORTF_FER_SET, val) +#define bfin_read_PORTF_FER_CLEAR() bfin_read32(PORTF_FER_CLEAR) +#define bfin_write_PORTF_FER_CLEAR(val) bfin_write32(PORTF_FER_CLEAR, val) +#define bfin_read_PORTF() bfin_read32(PORTF) +#define bfin_write_PORTF(val) bfin_write32(PORTF, val) +#define bfin_read_PORTF_SET() bfin_read32(PORTF_SET) +#define bfin_write_PORTF_SET(val) bfin_write32(PORTF_SET, val) +#define bfin_read_PORTF_CLEAR() bfin_read32(PORTF_CLEAR) +#define bfin_write_PORTF_CLEAR(val) bfin_write32(PORTF_CLEAR, val) +#define bfin_read_PORTF_DIR() bfin_read32(PORTF_DIR) +#define bfin_write_PORTF_DIR(val) bfin_write32(PORTF_DIR, val) +#define bfin_read_PORTF_DIR_SET() bfin_read32(PORTF_DIR_SET) +#define bfin_write_PORTF_DIR_SET(val) bfin_write32(PORTF_DIR_SET, val) +#define bfin_read_PORTF_DIR_CLEAR() bfin_read32(PORTF_DIR_CLEAR) +#define bfin_write_PORTF_DIR_CLEAR(val) bfin_write32(PORTF_DIR_CLEAR, val) +#define bfin_read_PORTF_INEN() bfin_read32(PORTF_INEN) +#define bfin_write_PORTF_INEN(val) bfin_write32(PORTF_INEN, val) +#define bfin_read_PORTF_INEN_SET() bfin_read32(PORTF_INEN_SET) +#define bfin_write_PORTF_INEN_SET(val) bfin_write32(PORTF_INEN_SET, val) +#define bfin_read_PORTF_INEN_CLEAR() bfin_read32(PORTF_INEN_CLEAR) +#define bfin_write_PORTF_INEN_CLEAR(val) bfin_write32(PORTF_INEN_CLEAR, val) +#define bfin_read_PORTF_MUX() bfin_read32(PORTF_MUX) +#define bfin_write_PORTF_MUX(val) bfin_write32(PORTF_MUX, val) +#define bfin_read_PORTF_DATA_TGL() bfin_read32(PORTF_DATA_TGL) +#define bfin_write_PORTF_DATA_TGL(val) bfin_write32(PORTF_DATA_TGL, val) +#define bfin_read_PORTF_POL() bfin_read32(PORTF_POL) +#define bfin_write_PORTF_POL(val) bfin_write32(PORTF_POL, val) +#define bfin_read_PORTF_POL_SET() bfin_read32(PORTF_POL_SET) +#define bfin_write_PORTF_POL_SET(val) bfin_write32(PORTF_POL_SET, val) +#define bfin_read_PORTF_POL_CLEAR() bfin_read32(PORTF_POL_CLEAR) +#define bfin_write_PORTF_POL_CLEAR(val) bfin_write32(PORTF_POL_CLEAR, val) +#define bfin_read_PORTF_LOCK() bfin_read32(PORTF_LOCK) +#define bfin_write_PORTF_LOCK(val) bfin_write32(PORTF_LOCK, val) +#define bfin_read_PORTF_REVID() bfin_read32(PORTF_REVID) +#define bfin_write_PORTF_REVID(val) bfin_write32(PORTF_REVID, val) + + +/* Port G Registers */ +#define bfin_read_PORTG_FER() bfin_read32(PORTG_FER) +#define bfin_write_PORTG_FER(val) bfin_write32(PORTG_FER, val) +#define bfin_read_PORTG_FER_SET() bfin_read32(PORTG_FER_SET) +#define bfin_write_PORTG_FER_SET(val) bfin_write32(PORTG_FER_SET, val) +#define bfin_read_PORTG_FER_CLEAR() bfin_read32(PORTG_FER_CLEAR) +#define bfin_write_PORTG_FER_CLEAR(val) bfin_write32(PORTG_FER_CLEAR, val) +#define bfin_read_PORTG() bfin_read32(PORTG) +#define bfin_write_PORTG(val) bfin_write32(PORTG, val) +#define bfin_read_PORTG_SET() bfin_read32(PORTG_SET) +#define bfin_write_PORTG_SET(val) bfin_write32(PORTG_SET, val) +#define bfin_read_PORTG_CLEAR() bfin_read32(PORTG_CLEAR) +#define bfin_write_PORTG_CLEAR(val) bfin_write32(PORTG_CLEAR, val) +#define bfin_read_PORTG_DIR() bfin_read32(PORTG_DIR) +#define bfin_write_PORTG_DIR(val) bfin_write32(PORTG_DIR, val) +#define bfin_read_PORTG_DIR_SET() bfin_read32(PORTG_DIR_SET) +#define bfin_write_PORTG_DIR_SET(val) bfin_write32(PORTG_DIR_SET, val) +#define bfin_read_PORTG_DIR_CLEAR() bfin_read32(PORTG_DIR_CLEAR) +#define bfin_write_PORTG_DIR_CLEAR(val) bfin_write32(PORTG_DIR_CLEAR, val) +#define bfin_read_PORTG_INEN() bfin_read32(PORTG_INEN) +#define bfin_write_PORTG_INEN(val) bfin_write32(PORTG_INEN, val) +#define bfin_read_PORTG_INEN_SET() bfin_read32(PORTG_INEN_SET) +#define bfin_write_PORTG_INEN_SET(val) bfin_write32(PORTG_INEN_SET, val) +#define bfin_read_PORTG_INEN_CLEAR() bfin_read32(PORTG_INEN_CLEAR) +#define bfin_write_PORTG_INEN_CLEAR(val) bfin_write32(PORTG_INEN_CLEAR, val) +#define bfin_read_PORTG_MUX() bfin_read32(PORTG_MUX) +#define bfin_write_PORTG_MUX(val) bfin_write32(PORTG_MUX, val) +#define bfin_read_PORTG_DATA_TGL() bfin_read32(PORTG_DATA_TGL) +#define bfin_write_PORTG_DATA_TGL(val) bfin_write32(PORTG_DATA_TGL, val) +#define bfin_read_PORTG_POL() bfin_read32(PORTG_POL) +#define bfin_write_PORTG_POL(val) bfin_write32(PORTG_POL, val) +#define bfin_read_PORTG_POL_SET() bfin_read32(PORTG_POL_SET) +#define bfin_write_PORTG_POL_SET(val) bfin_write32(PORTG_POL_SET, val) +#define bfin_read_PORTG_POL_CLEAR() bfin_read32(PORTG_POL_CLEAR) +#define bfin_write_PORTG_POL_CLEAR(val) bfin_write32(PORTG_POL_CLEAR, val) +#define bfin_read_PORTG_LOCK() bfin_read32(PORTG_LOCK) +#define bfin_write_PORTG_LOCK(val) bfin_write32(PORTG_LOCK, val) +#define bfin_read_PORTG_REVID() bfin_read32(PORTG_REVID) +#define bfin_write_PORTG_REVID(val) bfin_write32(PORTG_REVID, val) + + + + +/* CAN Controller 0 Config 1 Registers */ + +#define bfin_read_CAN0_MC1() bfin_read16(CAN0_MC1) +#define bfin_write_CAN0_MC1(val) bfin_write16(CAN0_MC1, val) +#define bfin_read_CAN0_MD1() bfin_read16(CAN0_MD1) +#define bfin_write_CAN0_MD1(val) bfin_write16(CAN0_MD1, val) +#define bfin_read_CAN0_TRS1() bfin_read16(CAN0_TRS1) +#define bfin_write_CAN0_TRS1(val) bfin_write16(CAN0_TRS1, val) +#define bfin_read_CAN0_TRR1() bfin_read16(CAN0_TRR1) +#define bfin_write_CAN0_TRR1(val) bfin_write16(CAN0_TRR1, val) +#define bfin_read_CAN0_TA1() bfin_read16(CAN0_TA1) +#define bfin_write_CAN0_TA1(val) bfin_write16(CAN0_TA1, val) +#define bfin_read_CAN0_AA1() bfin_read16(CAN0_AA1) +#define bfin_write_CAN0_AA1(val) bfin_write16(CAN0_AA1, val) +#define bfin_read_CAN0_RMP1() bfin_read16(CAN0_RMP1) +#define bfin_write_CAN0_RMP1(val) bfin_write16(CAN0_RMP1, val) +#define bfin_read_CAN0_RML1() bfin_read16(CAN0_RML1) +#define bfin_write_CAN0_RML1(val) bfin_write16(CAN0_RML1, val) +#define bfin_read_CAN0_MBTIF1() bfin_read16(CAN0_MBTIF1) +#define bfin_write_CAN0_MBTIF1(val) bfin_write16(CAN0_MBTIF1, val) +#define bfin_read_CAN0_MBRIF1() bfin_read16(CAN0_MBRIF1) +#define bfin_write_CAN0_MBRIF1(val) bfin_write16(CAN0_MBRIF1, val) +#define bfin_read_CAN0_MBIM1() bfin_read16(CAN0_MBIM1) +#define bfin_write_CAN0_MBIM1(val) bfin_write16(CAN0_MBIM1, val) +#define bfin_read_CAN0_RFH1() bfin_read16(CAN0_RFH1) +#define bfin_write_CAN0_RFH1(val) bfin_write16(CAN0_RFH1, val) +#define bfin_read_CAN0_OPSS1() bfin_read16(CAN0_OPSS1) +#define bfin_write_CAN0_OPSS1(val) bfin_write16(CAN0_OPSS1, val) + +/* CAN Controller 0 Config 2 Registers */ + +#define bfin_read_CAN0_MC2() bfin_read16(CAN0_MC2) +#define bfin_write_CAN0_MC2(val) bfin_write16(CAN0_MC2, val) +#define bfin_read_CAN0_MD2() bfin_read16(CAN0_MD2) +#define bfin_write_CAN0_MD2(val) bfin_write16(CAN0_MD2, val) +#define bfin_read_CAN0_TRS2() bfin_read16(CAN0_TRS2) +#define bfin_write_CAN0_TRS2(val) bfin_write16(CAN0_TRS2, val) +#define bfin_read_CAN0_TRR2() bfin_read16(CAN0_TRR2) +#define bfin_write_CAN0_TRR2(val) bfin_write16(CAN0_TRR2, val) +#define bfin_read_CAN0_TA2() bfin_read16(CAN0_TA2) +#define bfin_write_CAN0_TA2(val) bfin_write16(CAN0_TA2, val) +#define bfin_read_CAN0_AA2() bfin_read16(CAN0_AA2) +#define bfin_write_CAN0_AA2(val) bfin_write16(CAN0_AA2, val) +#define bfin_read_CAN0_RMP2() bfin_read16(CAN0_RMP2) +#define bfin_write_CAN0_RMP2(val) bfin_write16(CAN0_RMP2, val) +#define bfin_read_CAN0_RML2() bfin_read16(CAN0_RML2) +#define bfin_write_CAN0_RML2(val) bfin_write16(CAN0_RML2, val) +#define bfin_read_CAN0_MBTIF2() bfin_read16(CAN0_MBTIF2) +#define bfin_write_CAN0_MBTIF2(val) bfin_write16(CAN0_MBTIF2, val) +#define bfin_read_CAN0_MBRIF2() bfin_read16(CAN0_MBRIF2) +#define bfin_write_CAN0_MBRIF2(val) bfin_write16(CAN0_MBRIF2, val) +#define bfin_read_CAN0_MBIM2() bfin_read16(CAN0_MBIM2) +#define bfin_write_CAN0_MBIM2(val) bfin_write16(CAN0_MBIM2, val) +#define bfin_read_CAN0_RFH2() bfin_read16(CAN0_RFH2) +#define bfin_write_CAN0_RFH2(val) bfin_write16(CAN0_RFH2, val) +#define bfin_read_CAN0_OPSS2() bfin_read16(CAN0_OPSS2) +#define bfin_write_CAN0_OPSS2(val) bfin_write16(CAN0_OPSS2, val) + +/* CAN Controller 0 Clock/Interrubfin_read_()t/Counter Registers */ + +#define bfin_read_CAN0_CLOCK() bfin_read16(CAN0_CLOCK) +#define bfin_write_CAN0_CLOCK(val) bfin_write16(CAN0_CLOCK, val) +#define bfin_read_CAN0_TIMING() bfin_read16(CAN0_TIMING) +#define bfin_write_CAN0_TIMING(val) bfin_write16(CAN0_TIMING, val) +#define bfin_read_CAN0_DEBUG() bfin_read16(CAN0_DEBUG) +#define bfin_write_CAN0_DEBUG(val) bfin_write16(CAN0_DEBUG, val) +#define bfin_read_CAN0_STATUS() bfin_read16(CAN0_STATUS) +#define bfin_write_CAN0_STATUS(val) bfin_write16(CAN0_STATUS, val) +#define bfin_read_CAN0_CEC() bfin_read16(CAN0_CEC) +#define bfin_write_CAN0_CEC(val) bfin_write16(CAN0_CEC, val) +#define bfin_read_CAN0_GIS() bfin_read16(CAN0_GIS) +#define bfin_write_CAN0_GIS(val) bfin_write16(CAN0_GIS, val) +#define bfin_read_CAN0_GIM() bfin_read16(CAN0_GIM) +#define bfin_write_CAN0_GIM(val) bfin_write16(CAN0_GIM, val) +#define bfin_read_CAN0_GIF() bfin_read16(CAN0_GIF) +#define bfin_write_CAN0_GIF(val) bfin_write16(CAN0_GIF, val) +#define bfin_read_CAN0_CONTROL() bfin_read16(CAN0_CONTROL) +#define bfin_write_CAN0_CONTROL(val) bfin_write16(CAN0_CONTROL, val) +#define bfin_read_CAN0_INTR() bfin_read16(CAN0_INTR) +#define bfin_write_CAN0_INTR(val) bfin_write16(CAN0_INTR, val) +#define bfin_read_CAN0_MBTD() bfin_read16(CAN0_MBTD) +#define bfin_write_CAN0_MBTD(val) bfin_write16(CAN0_MBTD, val) +#define bfin_read_CAN0_EWR() bfin_read16(CAN0_EWR) +#define bfin_write_CAN0_EWR(val) bfin_write16(CAN0_EWR, val) +#define bfin_read_CAN0_ESR() bfin_read16(CAN0_ESR) +#define bfin_write_CAN0_ESR(val) bfin_write16(CAN0_ESR, val) +#define bfin_read_CAN0_UCCNT() bfin_read16(CAN0_UCCNT) +#define bfin_write_CAN0_UCCNT(val) bfin_write16(CAN0_UCCNT, val) +#define bfin_read_CAN0_UCRC() bfin_read16(CAN0_UCRC) +#define bfin_write_CAN0_UCRC(val) bfin_write16(CAN0_UCRC, val) +#define bfin_read_CAN0_UCCNF() bfin_read16(CAN0_UCCNF) +#define bfin_write_CAN0_UCCNF(val) bfin_write16(CAN0_UCCNF, val) + +/* CAN Controller 0 Accebfin_read_()tance Registers */ + +#define bfin_read_CAN0_AM00L() bfin_read16(CAN0_AM00L) +#define bfin_write_CAN0_AM00L(val) bfin_write16(CAN0_AM00L, val) +#define bfin_read_CAN0_AM00H() bfin_read16(CAN0_AM00H) +#define bfin_write_CAN0_AM00H(val) bfin_write16(CAN0_AM00H, val) +#define bfin_read_CAN0_AM01L() bfin_read16(CAN0_AM01L) +#define bfin_write_CAN0_AM01L(val) bfin_write16(CAN0_AM01L, val) +#define bfin_read_CAN0_AM01H() bfin_read16(CAN0_AM01H) +#define bfin_write_CAN0_AM01H(val) bfin_write16(CAN0_AM01H, val) +#define bfin_read_CAN0_AM02L() bfin_read16(CAN0_AM02L) +#define bfin_write_CAN0_AM02L(val) bfin_write16(CAN0_AM02L, val) +#define bfin_read_CAN0_AM02H() bfin_read16(CAN0_AM02H) +#define bfin_write_CAN0_AM02H(val) bfin_write16(CAN0_AM02H, val) +#define bfin_read_CAN0_AM03L() bfin_read16(CAN0_AM03L) +#define bfin_write_CAN0_AM03L(val) bfin_write16(CAN0_AM03L, val) +#define bfin_read_CAN0_AM03H() bfin_read16(CAN0_AM03H) +#define bfin_write_CAN0_AM03H(val) bfin_write16(CAN0_AM03H, val) +#define bfin_read_CAN0_AM04L() bfin_read16(CAN0_AM04L) +#define bfin_write_CAN0_AM04L(val) bfin_write16(CAN0_AM04L, val) +#define bfin_read_CAN0_AM04H() bfin_read16(CAN0_AM04H) +#define bfin_write_CAN0_AM04H(val) bfin_write16(CAN0_AM04H, val) +#define bfin_read_CAN0_AM05L() bfin_read16(CAN0_AM05L) +#define bfin_write_CAN0_AM05L(val) bfin_write16(CAN0_AM05L, val) +#define bfin_read_CAN0_AM05H() bfin_read16(CAN0_AM05H) +#define bfin_write_CAN0_AM05H(val) bfin_write16(CAN0_AM05H, val) +#define bfin_read_CAN0_AM06L() bfin_read16(CAN0_AM06L) +#define bfin_write_CAN0_AM06L(val) bfin_write16(CAN0_AM06L, val) +#define bfin_read_CAN0_AM06H() bfin_read16(CAN0_AM06H) +#define bfin_write_CAN0_AM06H(val) bfin_write16(CAN0_AM06H, val) +#define bfin_read_CAN0_AM07L() bfin_read16(CAN0_AM07L) +#define bfin_write_CAN0_AM07L(val) bfin_write16(CAN0_AM07L, val) +#define bfin_read_CAN0_AM07H() bfin_read16(CAN0_AM07H) +#define bfin_write_CAN0_AM07H(val) bfin_write16(CAN0_AM07H, val) +#define bfin_read_CAN0_AM08L() bfin_read16(CAN0_AM08L) +#define bfin_write_CAN0_AM08L(val) bfin_write16(CAN0_AM08L, val) +#define bfin_read_CAN0_AM08H() bfin_read16(CAN0_AM08H) +#define bfin_write_CAN0_AM08H(val) bfin_write16(CAN0_AM08H, val) +#define bfin_read_CAN0_AM09L() bfin_read16(CAN0_AM09L) +#define bfin_write_CAN0_AM09L(val) bfin_write16(CAN0_AM09L, val) +#define bfin_read_CAN0_AM09H() bfin_read16(CAN0_AM09H) +#define bfin_write_CAN0_AM09H(val) bfin_write16(CAN0_AM09H, val) +#define bfin_read_CAN0_AM10L() bfin_read16(CAN0_AM10L) +#define bfin_write_CAN0_AM10L(val) bfin_write16(CAN0_AM10L, val) +#define bfin_read_CAN0_AM10H() bfin_read16(CAN0_AM10H) +#define bfin_write_CAN0_AM10H(val) bfin_write16(CAN0_AM10H, val) +#define bfin_read_CAN0_AM11L() bfin_read16(CAN0_AM11L) +#define bfin_write_CAN0_AM11L(val) bfin_write16(CAN0_AM11L, val) +#define bfin_read_CAN0_AM11H() bfin_read16(CAN0_AM11H) +#define bfin_write_CAN0_AM11H(val) bfin_write16(CAN0_AM11H, val) +#define bfin_read_CAN0_AM12L() bfin_read16(CAN0_AM12L) +#define bfin_write_CAN0_AM12L(val) bfin_write16(CAN0_AM12L, val) +#define bfin_read_CAN0_AM12H() bfin_read16(CAN0_AM12H) +#define bfin_write_CAN0_AM12H(val) bfin_write16(CAN0_AM12H, val) +#define bfin_read_CAN0_AM13L() bfin_read16(CAN0_AM13L) +#define bfin_write_CAN0_AM13L(val) bfin_write16(CAN0_AM13L, val) +#define bfin_read_CAN0_AM13H() bfin_read16(CAN0_AM13H) +#define bfin_write_CAN0_AM13H(val) bfin_write16(CAN0_AM13H, val) +#define bfin_read_CAN0_AM14L() bfin_read16(CAN0_AM14L) +#define bfin_write_CAN0_AM14L(val) bfin_write16(CAN0_AM14L, val) +#define bfin_read_CAN0_AM14H() bfin_read16(CAN0_AM14H) +#define bfin_write_CAN0_AM14H(val) bfin_write16(CAN0_AM14H, val) +#define bfin_read_CAN0_AM15L() bfin_read16(CAN0_AM15L) +#define bfin_write_CAN0_AM15L(val) bfin_write16(CAN0_AM15L, val) +#define bfin_read_CAN0_AM15H() bfin_read16(CAN0_AM15H) +#define bfin_write_CAN0_AM15H(val) bfin_write16(CAN0_AM15H, val) + +/* CAN Controller 0 Accebfin_read_()tance Registers */ + +#define bfin_read_CAN0_AM16L() bfin_read16(CAN0_AM16L) +#define bfin_write_CAN0_AM16L(val) bfin_write16(CAN0_AM16L, val) +#define bfin_read_CAN0_AM16H() bfin_read16(CAN0_AM16H) +#define bfin_write_CAN0_AM16H(val) bfin_write16(CAN0_AM16H, val) +#define bfin_read_CAN0_AM17L() bfin_read16(CAN0_AM17L) +#define bfin_write_CAN0_AM17L(val) bfin_write16(CAN0_AM17L, val) +#define bfin_read_CAN0_AM17H() bfin_read16(CAN0_AM17H) +#define bfin_write_CAN0_AM17H(val) bfin_write16(CAN0_AM17H, val) +#define bfin_read_CAN0_AM18L() bfin_read16(CAN0_AM18L) +#define bfin_write_CAN0_AM18L(val) bfin_write16(CAN0_AM18L, val) +#define bfin_read_CAN0_AM18H() bfin_read16(CAN0_AM18H) +#define bfin_write_CAN0_AM18H(val) bfin_write16(CAN0_AM18H, val) +#define bfin_read_CAN0_AM19L() bfin_read16(CAN0_AM19L) +#define bfin_write_CAN0_AM19L(val) bfin_write16(CAN0_AM19L, val) +#define bfin_read_CAN0_AM19H() bfin_read16(CAN0_AM19H) +#define bfin_write_CAN0_AM19H(val) bfin_write16(CAN0_AM19H, val) +#define bfin_read_CAN0_AM20L() bfin_read16(CAN0_AM20L) +#define bfin_write_CAN0_AM20L(val) bfin_write16(CAN0_AM20L, val) +#define bfin_read_CAN0_AM20H() bfin_read16(CAN0_AM20H) +#define bfin_write_CAN0_AM20H(val) bfin_write16(CAN0_AM20H, val) +#define bfin_read_CAN0_AM21L() bfin_read16(CAN0_AM21L) +#define bfin_write_CAN0_AM21L(val) bfin_write16(CAN0_AM21L, val) +#define bfin_read_CAN0_AM21H() bfin_read16(CAN0_AM21H) +#define bfin_write_CAN0_AM21H(val) bfin_write16(CAN0_AM21H, val) +#define bfin_read_CAN0_AM22L() bfin_read16(CAN0_AM22L) +#define bfin_write_CAN0_AM22L(val) bfin_write16(CAN0_AM22L, val) +#define bfin_read_CAN0_AM22H() bfin_read16(CAN0_AM22H) +#define bfin_write_CAN0_AM22H(val) bfin_write16(CAN0_AM22H, val) +#define bfin_read_CAN0_AM23L() bfin_read16(CAN0_AM23L) +#define bfin_write_CAN0_AM23L(val) bfin_write16(CAN0_AM23L, val) +#define bfin_read_CAN0_AM23H() bfin_read16(CAN0_AM23H) +#define bfin_write_CAN0_AM23H(val) bfin_write16(CAN0_AM23H, val) +#define bfin_read_CAN0_AM24L() bfin_read16(CAN0_AM24L) +#define bfin_write_CAN0_AM24L(val) bfin_write16(CAN0_AM24L, val) +#define bfin_read_CAN0_AM24H() bfin_read16(CAN0_AM24H) +#define bfin_write_CAN0_AM24H(val) bfin_write16(CAN0_AM24H, val) +#define bfin_read_CAN0_AM25L() bfin_read16(CAN0_AM25L) +#define bfin_write_CAN0_AM25L(val) bfin_write16(CAN0_AM25L, val) +#define bfin_read_CAN0_AM25H() bfin_read16(CAN0_AM25H) +#define bfin_write_CAN0_AM25H(val) bfin_write16(CAN0_AM25H, val) +#define bfin_read_CAN0_AM26L() bfin_read16(CAN0_AM26L) +#define bfin_write_CAN0_AM26L(val) bfin_write16(CAN0_AM26L, val) +#define bfin_read_CAN0_AM26H() bfin_read16(CAN0_AM26H) +#define bfin_write_CAN0_AM26H(val) bfin_write16(CAN0_AM26H, val) +#define bfin_read_CAN0_AM27L() bfin_read16(CAN0_AM27L) +#define bfin_write_CAN0_AM27L(val) bfin_write16(CAN0_AM27L, val) +#define bfin_read_CAN0_AM27H() bfin_read16(CAN0_AM27H) +#define bfin_write_CAN0_AM27H(val) bfin_write16(CAN0_AM27H, val) +#define bfin_read_CAN0_AM28L() bfin_read16(CAN0_AM28L) +#define bfin_write_CAN0_AM28L(val) bfin_write16(CAN0_AM28L, val) +#define bfin_read_CAN0_AM28H() bfin_read16(CAN0_AM28H) +#define bfin_write_CAN0_AM28H(val) bfin_write16(CAN0_AM28H, val) +#define bfin_read_CAN0_AM29L() bfin_read16(CAN0_AM29L) +#define bfin_write_CAN0_AM29L(val) bfin_write16(CAN0_AM29L, val) +#define bfin_read_CAN0_AM29H() bfin_read16(CAN0_AM29H) +#define bfin_write_CAN0_AM29H(val) bfin_write16(CAN0_AM29H, val) +#define bfin_read_CAN0_AM30L() bfin_read16(CAN0_AM30L) +#define bfin_write_CAN0_AM30L(val) bfin_write16(CAN0_AM30L, val) +#define bfin_read_CAN0_AM30H() bfin_read16(CAN0_AM30H) +#define bfin_write_CAN0_AM30H(val) bfin_write16(CAN0_AM30H, val) +#define bfin_read_CAN0_AM31L() bfin_read16(CAN0_AM31L) +#define bfin_write_CAN0_AM31L(val) bfin_write16(CAN0_AM31L, val) +#define bfin_read_CAN0_AM31H() bfin_read16(CAN0_AM31H) +#define bfin_write_CAN0_AM31H(val) bfin_write16(CAN0_AM31H, val) + +/* CAN Controller 0 Mailbox Data Registers */ + +#define bfin_read_CAN0_MB00_DATA0() bfin_read16(CAN0_MB00_DATA0) +#define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val) +#define bfin_read_CAN0_MB00_DATA1() bfin_read16(CAN0_MB00_DATA1) +#define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val) +#define bfin_read_CAN0_MB00_DATA2() bfin_read16(CAN0_MB00_DATA2) +#define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val) +#define bfin_read_CAN0_MB00_DATA3() bfin_read16(CAN0_MB00_DATA3) +#define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val) +#define bfin_read_CAN0_MB00_LENGTH() bfin_read16(CAN0_MB00_LENGTH) +#define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val) +#define bfin_read_CAN0_MB00_TIMESTAMP() bfin_read16(CAN0_MB00_TIMESTAMP) +#define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val) +#define bfin_read_CAN0_MB00_ID0() bfin_read16(CAN0_MB00_ID0) +#define bfin_write_CAN0_MB00_ID0(val) bfin_write16(CAN0_MB00_ID0, val) +#define bfin_read_CAN0_MB00_ID1() bfin_read16(CAN0_MB00_ID1) +#define bfin_write_CAN0_MB00_ID1(val) bfin_write16(CAN0_MB00_ID1, val) +#define bfin_read_CAN0_MB01_DATA0() bfin_read16(CAN0_MB01_DATA0) +#define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val) +#define bfin_read_CAN0_MB01_DATA1() bfin_read16(CAN0_MB01_DATA1) +#define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val) +#define bfin_read_CAN0_MB01_DATA2() bfin_read16(CAN0_MB01_DATA2) +#define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val) +#define bfin_read_CAN0_MB01_DATA3() bfin_read16(CAN0_MB01_DATA3) +#define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val) +#define bfin_read_CAN0_MB01_LENGTH() bfin_read16(CAN0_MB01_LENGTH) +#define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val) +#define bfin_read_CAN0_MB01_TIMESTAMP() bfin_read16(CAN0_MB01_TIMESTAMP) +#define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val) +#define bfin_read_CAN0_MB01_ID0() bfin_read16(CAN0_MB01_ID0) +#define bfin_write_CAN0_MB01_ID0(val) bfin_write16(CAN0_MB01_ID0, val) +#define bfin_read_CAN0_MB01_ID1() bfin_read16(CAN0_MB01_ID1) +#define bfin_write_CAN0_MB01_ID1(val) bfin_write16(CAN0_MB01_ID1, val) +#define bfin_read_CAN0_MB02_DATA0() bfin_read16(CAN0_MB02_DATA0) +#define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val) +#define bfin_read_CAN0_MB02_DATA1() bfin_read16(CAN0_MB02_DATA1) +#define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val) +#define bfin_read_CAN0_MB02_DATA2() bfin_read16(CAN0_MB02_DATA2) +#define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val) +#define bfin_read_CAN0_MB02_DATA3() bfin_read16(CAN0_MB02_DATA3) +#define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val) +#define bfin_read_CAN0_MB02_LENGTH() bfin_read16(CAN0_MB02_LENGTH) +#define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val) +#define bfin_read_CAN0_MB02_TIMESTAMP() bfin_read16(CAN0_MB02_TIMESTAMP) +#define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val) +#define bfin_read_CAN0_MB02_ID0() bfin_read16(CAN0_MB02_ID0) +#define bfin_write_CAN0_MB02_ID0(val) bfin_write16(CAN0_MB02_ID0, val) +#define bfin_read_CAN0_MB02_ID1() bfin_read16(CAN0_MB02_ID1) +#define bfin_write_CAN0_MB02_ID1(val) bfin_write16(CAN0_MB02_ID1, val) +#define bfin_read_CAN0_MB03_DATA0() bfin_read16(CAN0_MB03_DATA0) +#define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val) +#define bfin_read_CAN0_MB03_DATA1() bfin_read16(CAN0_MB03_DATA1) +#define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val) +#define bfin_read_CAN0_MB03_DATA2() bfin_read16(CAN0_MB03_DATA2) +#define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val) +#define bfin_read_CAN0_MB03_DATA3() bfin_read16(CAN0_MB03_DATA3) +#define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val) +#define bfin_read_CAN0_MB03_LENGTH() bfin_read16(CAN0_MB03_LENGTH) +#define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val) +#define bfin_read_CAN0_MB03_TIMESTAMP() bfin_read16(CAN0_MB03_TIMESTAMP) +#define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val) +#define bfin_read_CAN0_MB03_ID0() bfin_read16(CAN0_MB03_ID0) +#define bfin_write_CAN0_MB03_ID0(val) bfin_write16(CAN0_MB03_ID0, val) +#define bfin_read_CAN0_MB03_ID1() bfin_read16(CAN0_MB03_ID1) +#define bfin_write_CAN0_MB03_ID1(val) bfin_write16(CAN0_MB03_ID1, val) +#define bfin_read_CAN0_MB04_DATA0() bfin_read16(CAN0_MB04_DATA0) +#define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val) +#define bfin_read_CAN0_MB04_DATA1() bfin_read16(CAN0_MB04_DATA1) +#define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val) +#define bfin_read_CAN0_MB04_DATA2() bfin_read16(CAN0_MB04_DATA2) +#define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val) +#define bfin_read_CAN0_MB04_DATA3() bfin_read16(CAN0_MB04_DATA3) +#define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val) +#define bfin_read_CAN0_MB04_LENGTH() bfin_read16(CAN0_MB04_LENGTH) +#define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val) +#define bfin_read_CAN0_MB04_TIMESTAMP() bfin_read16(CAN0_MB04_TIMESTAMP) +#define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val) +#define bfin_read_CAN0_MB04_ID0() bfin_read16(CAN0_MB04_ID0) +#define bfin_write_CAN0_MB04_ID0(val) bfin_write16(CAN0_MB04_ID0, val) +#define bfin_read_CAN0_MB04_ID1() bfin_read16(CAN0_MB04_ID1) +#define bfin_write_CAN0_MB04_ID1(val) bfin_write16(CAN0_MB04_ID1, val) +#define bfin_read_CAN0_MB05_DATA0() bfin_read16(CAN0_MB05_DATA0) +#define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val) +#define bfin_read_CAN0_MB05_DATA1() bfin_read16(CAN0_MB05_DATA1) +#define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val) +#define bfin_read_CAN0_MB05_DATA2() bfin_read16(CAN0_MB05_DATA2) +#define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val) +#define bfin_read_CAN0_MB05_DATA3() bfin_read16(CAN0_MB05_DATA3) +#define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val) +#define bfin_read_CAN0_MB05_LENGTH() bfin_read16(CAN0_MB05_LENGTH) +#define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val) +#define bfin_read_CAN0_MB05_TIMESTAMP() bfin_read16(CAN0_MB05_TIMESTAMP) +#define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val) +#define bfin_read_CAN0_MB05_ID0() bfin_read16(CAN0_MB05_ID0) +#define bfin_write_CAN0_MB05_ID0(val) bfin_write16(CAN0_MB05_ID0, val) +#define bfin_read_CAN0_MB05_ID1() bfin_read16(CAN0_MB05_ID1) +#define bfin_write_CAN0_MB05_ID1(val) bfin_write16(CAN0_MB05_ID1, val) +#define bfin_read_CAN0_MB06_DATA0() bfin_read16(CAN0_MB06_DATA0) +#define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val) +#define bfin_read_CAN0_MB06_DATA1() bfin_read16(CAN0_MB06_DATA1) +#define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val) +#define bfin_read_CAN0_MB06_DATA2() bfin_read16(CAN0_MB06_DATA2) +#define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val) +#define bfin_read_CAN0_MB06_DATA3() bfin_read16(CAN0_MB06_DATA3) +#define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val) +#define bfin_read_CAN0_MB06_LENGTH() bfin_read16(CAN0_MB06_LENGTH) +#define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val) +#define bfin_read_CAN0_MB06_TIMESTAMP() bfin_read16(CAN0_MB06_TIMESTAMP) +#define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val) +#define bfin_read_CAN0_MB06_ID0() bfin_read16(CAN0_MB06_ID0) +#define bfin_write_CAN0_MB06_ID0(val) bfin_write16(CAN0_MB06_ID0, val) +#define bfin_read_CAN0_MB06_ID1() bfin_read16(CAN0_MB06_ID1) +#define bfin_write_CAN0_MB06_ID1(val) bfin_write16(CAN0_MB06_ID1, val) +#define bfin_read_CAN0_MB07_DATA0() bfin_read16(CAN0_MB07_DATA0) +#define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val) +#define bfin_read_CAN0_MB07_DATA1() bfin_read16(CAN0_MB07_DATA1) +#define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val) +#define bfin_read_CAN0_MB07_DATA2() bfin_read16(CAN0_MB07_DATA2) +#define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val) +#define bfin_read_CAN0_MB07_DATA3() bfin_read16(CAN0_MB07_DATA3) +#define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val) +#define bfin_read_CAN0_MB07_LENGTH() bfin_read16(CAN0_MB07_LENGTH) +#define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val) +#define bfin_read_CAN0_MB07_TIMESTAMP() bfin_read16(CAN0_MB07_TIMESTAMP) +#define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val) +#define bfin_read_CAN0_MB07_ID0() bfin_read16(CAN0_MB07_ID0) +#define bfin_write_CAN0_MB07_ID0(val) bfin_write16(CAN0_MB07_ID0, val) +#define bfin_read_CAN0_MB07_ID1() bfin_read16(CAN0_MB07_ID1) +#define bfin_write_CAN0_MB07_ID1(val) bfin_write16(CAN0_MB07_ID1, val) +#define bfin_read_CAN0_MB08_DATA0() bfin_read16(CAN0_MB08_DATA0) +#define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val) +#define bfin_read_CAN0_MB08_DATA1() bfin_read16(CAN0_MB08_DATA1) +#define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val) +#define bfin_read_CAN0_MB08_DATA2() bfin_read16(CAN0_MB08_DATA2) +#define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val) +#define bfin_read_CAN0_MB08_DATA3() bfin_read16(CAN0_MB08_DATA3) +#define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val) +#define bfin_read_CAN0_MB08_LENGTH() bfin_read16(CAN0_MB08_LENGTH) +#define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val) +#define bfin_read_CAN0_MB08_TIMESTAMP() bfin_read16(CAN0_MB08_TIMESTAMP) +#define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val) +#define bfin_read_CAN0_MB08_ID0() bfin_read16(CAN0_MB08_ID0) +#define bfin_write_CAN0_MB08_ID0(val) bfin_write16(CAN0_MB08_ID0, val) +#define bfin_read_CAN0_MB08_ID1() bfin_read16(CAN0_MB08_ID1) +#define bfin_write_CAN0_MB08_ID1(val) bfin_write16(CAN0_MB08_ID1, val) +#define bfin_read_CAN0_MB09_DATA0() bfin_read16(CAN0_MB09_DATA0) +#define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val) +#define bfin_read_CAN0_MB09_DATA1() bfin_read16(CAN0_MB09_DATA1) +#define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val) +#define bfin_read_CAN0_MB09_DATA2() bfin_read16(CAN0_MB09_DATA2) +#define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val) +#define bfin_read_CAN0_MB09_DATA3() bfin_read16(CAN0_MB09_DATA3) +#define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val) +#define bfin_read_CAN0_MB09_LENGTH() bfin_read16(CAN0_MB09_LENGTH) +#define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val) +#define bfin_read_CAN0_MB09_TIMESTAMP() bfin_read16(CAN0_MB09_TIMESTAMP) +#define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val) +#define bfin_read_CAN0_MB09_ID0() bfin_read16(CAN0_MB09_ID0) +#define bfin_write_CAN0_MB09_ID0(val) bfin_write16(CAN0_MB09_ID0, val) +#define bfin_read_CAN0_MB09_ID1() bfin_read16(CAN0_MB09_ID1) +#define bfin_write_CAN0_MB09_ID1(val) bfin_write16(CAN0_MB09_ID1, val) +#define bfin_read_CAN0_MB10_DATA0() bfin_read16(CAN0_MB10_DATA0) +#define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val) +#define bfin_read_CAN0_MB10_DATA1() bfin_read16(CAN0_MB10_DATA1) +#define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val) +#define bfin_read_CAN0_MB10_DATA2() bfin_read16(CAN0_MB10_DATA2) +#define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val) +#define bfin_read_CAN0_MB10_DATA3() bfin_read16(CAN0_MB10_DATA3) +#define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val) +#define bfin_read_CAN0_MB10_LENGTH() bfin_read16(CAN0_MB10_LENGTH) +#define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val) +#define bfin_read_CAN0_MB10_TIMESTAMP() bfin_read16(CAN0_MB10_TIMESTAMP) +#define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val) +#define bfin_read_CAN0_MB10_ID0() bfin_read16(CAN0_MB10_ID0) +#define bfin_write_CAN0_MB10_ID0(val) bfin_write16(CAN0_MB10_ID0, val) +#define bfin_read_CAN0_MB10_ID1() bfin_read16(CAN0_MB10_ID1) +#define bfin_write_CAN0_MB10_ID1(val) bfin_write16(CAN0_MB10_ID1, val) +#define bfin_read_CAN0_MB11_DATA0() bfin_read16(CAN0_MB11_DATA0) +#define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val) +#define bfin_read_CAN0_MB11_DATA1() bfin_read16(CAN0_MB11_DATA1) +#define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val) +#define bfin_read_CAN0_MB11_DATA2() bfin_read16(CAN0_MB11_DATA2) +#define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val) +#define bfin_read_CAN0_MB11_DATA3() bfin_read16(CAN0_MB11_DATA3) +#define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val) +#define bfin_read_CAN0_MB11_LENGTH() bfin_read16(CAN0_MB11_LENGTH) +#define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val) +#define bfin_read_CAN0_MB11_TIMESTAMP() bfin_read16(CAN0_MB11_TIMESTAMP) +#define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val) +#define bfin_read_CAN0_MB11_ID0() bfin_read16(CAN0_MB11_ID0) +#define bfin_write_CAN0_MB11_ID0(val) bfin_write16(CAN0_MB11_ID0, val) +#define bfin_read_CAN0_MB11_ID1() bfin_read16(CAN0_MB11_ID1) +#define bfin_write_CAN0_MB11_ID1(val) bfin_write16(CAN0_MB11_ID1, val) +#define bfin_read_CAN0_MB12_DATA0() bfin_read16(CAN0_MB12_DATA0) +#define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val) +#define bfin_read_CAN0_MB12_DATA1() bfin_read16(CAN0_MB12_DATA1) +#define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val) +#define bfin_read_CAN0_MB12_DATA2() bfin_read16(CAN0_MB12_DATA2) +#define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val) +#define bfin_read_CAN0_MB12_DATA3() bfin_read16(CAN0_MB12_DATA3) +#define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val) +#define bfin_read_CAN0_MB12_LENGTH() bfin_read16(CAN0_MB12_LENGTH) +#define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val) +#define bfin_read_CAN0_MB12_TIMESTAMP() bfin_read16(CAN0_MB12_TIMESTAMP) +#define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val) +#define bfin_read_CAN0_MB12_ID0() bfin_read16(CAN0_MB12_ID0) +#define bfin_write_CAN0_MB12_ID0(val) bfin_write16(CAN0_MB12_ID0, val) +#define bfin_read_CAN0_MB12_ID1() bfin_read16(CAN0_MB12_ID1) +#define bfin_write_CAN0_MB12_ID1(val) bfin_write16(CAN0_MB12_ID1, val) +#define bfin_read_CAN0_MB13_DATA0() bfin_read16(CAN0_MB13_DATA0) +#define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val) +#define bfin_read_CAN0_MB13_DATA1() bfin_read16(CAN0_MB13_DATA1) +#define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val) +#define bfin_read_CAN0_MB13_DATA2() bfin_read16(CAN0_MB13_DATA2) +#define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val) +#define bfin_read_CAN0_MB13_DATA3() bfin_read16(CAN0_MB13_DATA3) +#define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val) +#define bfin_read_CAN0_MB13_LENGTH() bfin_read16(CAN0_MB13_LENGTH) +#define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val) +#define bfin_read_CAN0_MB13_TIMESTAMP() bfin_read16(CAN0_MB13_TIMESTAMP) +#define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val) +#define bfin_read_CAN0_MB13_ID0() bfin_read16(CAN0_MB13_ID0) +#define bfin_write_CAN0_MB13_ID0(val) bfin_write16(CAN0_MB13_ID0, val) +#define bfin_read_CAN0_MB13_ID1() bfin_read16(CAN0_MB13_ID1) +#define bfin_write_CAN0_MB13_ID1(val) bfin_write16(CAN0_MB13_ID1, val) +#define bfin_read_CAN0_MB14_DATA0() bfin_read16(CAN0_MB14_DATA0) +#define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val) +#define bfin_read_CAN0_MB14_DATA1() bfin_read16(CAN0_MB14_DATA1) +#define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val) +#define bfin_read_CAN0_MB14_DATA2() bfin_read16(CAN0_MB14_DATA2) +#define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val) +#define bfin_read_CAN0_MB14_DATA3() bfin_read16(CAN0_MB14_DATA3) +#define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val) +#define bfin_read_CAN0_MB14_LENGTH() bfin_read16(CAN0_MB14_LENGTH) +#define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val) +#define bfin_read_CAN0_MB14_TIMESTAMP() bfin_read16(CAN0_MB14_TIMESTAMP) +#define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val) +#define bfin_read_CAN0_MB14_ID0() bfin_read16(CAN0_MB14_ID0) +#define bfin_write_CAN0_MB14_ID0(val) bfin_write16(CAN0_MB14_ID0, val) +#define bfin_read_CAN0_MB14_ID1() bfin_read16(CAN0_MB14_ID1) +#define bfin_write_CAN0_MB14_ID1(val) bfin_write16(CAN0_MB14_ID1, val) +#define bfin_read_CAN0_MB15_DATA0() bfin_read16(CAN0_MB15_DATA0) +#define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val) +#define bfin_read_CAN0_MB15_DATA1() bfin_read16(CAN0_MB15_DATA1) +#define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val) +#define bfin_read_CAN0_MB15_DATA2() bfin_read16(CAN0_MB15_DATA2) +#define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val) +#define bfin_read_CAN0_MB15_DATA3() bfin_read16(CAN0_MB15_DATA3) +#define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val) +#define bfin_read_CAN0_MB15_LENGTH() bfin_read16(CAN0_MB15_LENGTH) +#define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val) +#define bfin_read_CAN0_MB15_TIMESTAMP() bfin_read16(CAN0_MB15_TIMESTAMP) +#define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val) +#define bfin_read_CAN0_MB15_ID0() bfin_read16(CAN0_MB15_ID0) +#define bfin_write_CAN0_MB15_ID0(val) bfin_write16(CAN0_MB15_ID0, val) +#define bfin_read_CAN0_MB15_ID1() bfin_read16(CAN0_MB15_ID1) +#define bfin_write_CAN0_MB15_ID1(val) bfin_write16(CAN0_MB15_ID1, val) + +/* CAN Controller 0 Mailbox Data Registers */ + +#define bfin_read_CAN0_MB16_DATA0() bfin_read16(CAN0_MB16_DATA0) +#define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val) +#define bfin_read_CAN0_MB16_DATA1() bfin_read16(CAN0_MB16_DATA1) +#define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val) +#define bfin_read_CAN0_MB16_DATA2() bfin_read16(CAN0_MB16_DATA2) +#define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val) +#define bfin_read_CAN0_MB16_DATA3() bfin_read16(CAN0_MB16_DATA3) +#define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val) +#define bfin_read_CAN0_MB16_LENGTH() bfin_read16(CAN0_MB16_LENGTH) +#define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val) +#define bfin_read_CAN0_MB16_TIMESTAMP() bfin_read16(CAN0_MB16_TIMESTAMP) +#define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val) +#define bfin_read_CAN0_MB16_ID0() bfin_read16(CAN0_MB16_ID0) +#define bfin_write_CAN0_MB16_ID0(val) bfin_write16(CAN0_MB16_ID0, val) +#define bfin_read_CAN0_MB16_ID1() bfin_read16(CAN0_MB16_ID1) +#define bfin_write_CAN0_MB16_ID1(val) bfin_write16(CAN0_MB16_ID1, val) +#define bfin_read_CAN0_MB17_DATA0() bfin_read16(CAN0_MB17_DATA0) +#define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val) +#define bfin_read_CAN0_MB17_DATA1() bfin_read16(CAN0_MB17_DATA1) +#define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val) +#define bfin_read_CAN0_MB17_DATA2() bfin_read16(CAN0_MB17_DATA2) +#define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val) +#define bfin_read_CAN0_MB17_DATA3() bfin_read16(CAN0_MB17_DATA3) +#define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val) +#define bfin_read_CAN0_MB17_LENGTH() bfin_read16(CAN0_MB17_LENGTH) +#define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val) +#define bfin_read_CAN0_MB17_TIMESTAMP() bfin_read16(CAN0_MB17_TIMESTAMP) +#define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val) +#define bfin_read_CAN0_MB17_ID0() bfin_read16(CAN0_MB17_ID0) +#define bfin_write_CAN0_MB17_ID0(val) bfin_write16(CAN0_MB17_ID0, val) +#define bfin_read_CAN0_MB17_ID1() bfin_read16(CAN0_MB17_ID1) +#define bfin_write_CAN0_MB17_ID1(val) bfin_write16(CAN0_MB17_ID1, val) +#define bfin_read_CAN0_MB18_DATA0() bfin_read16(CAN0_MB18_DATA0) +#define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val) +#define bfin_read_CAN0_MB18_DATA1() bfin_read16(CAN0_MB18_DATA1) +#define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val) +#define bfin_read_CAN0_MB18_DATA2() bfin_read16(CAN0_MB18_DATA2) +#define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val) +#define bfin_read_CAN0_MB18_DATA3() bfin_read16(CAN0_MB18_DATA3) +#define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val) +#define bfin_read_CAN0_MB18_LENGTH() bfin_read16(CAN0_MB18_LENGTH) +#define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val) +#define bfin_read_CAN0_MB18_TIMESTAMP() bfin_read16(CAN0_MB18_TIMESTAMP) +#define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val) +#define bfin_read_CAN0_MB18_ID0() bfin_read16(CAN0_MB18_ID0) +#define bfin_write_CAN0_MB18_ID0(val) bfin_write16(CAN0_MB18_ID0, val) +#define bfin_read_CAN0_MB18_ID1() bfin_read16(CAN0_MB18_ID1) +#define bfin_write_CAN0_MB18_ID1(val) bfin_write16(CAN0_MB18_ID1, val) +#define bfin_read_CAN0_MB19_DATA0() bfin_read16(CAN0_MB19_DATA0) +#define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val) +#define bfin_read_CAN0_MB19_DATA1() bfin_read16(CAN0_MB19_DATA1) +#define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val) +#define bfin_read_CAN0_MB19_DATA2() bfin_read16(CAN0_MB19_DATA2) +#define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val) +#define bfin_read_CAN0_MB19_DATA3() bfin_read16(CAN0_MB19_DATA3) +#define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val) +#define bfin_read_CAN0_MB19_LENGTH() bfin_read16(CAN0_MB19_LENGTH) +#define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val) +#define bfin_read_CAN0_MB19_TIMESTAMP() bfin_read16(CAN0_MB19_TIMESTAMP) +#define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val) +#define bfin_read_CAN0_MB19_ID0() bfin_read16(CAN0_MB19_ID0) +#define bfin_write_CAN0_MB19_ID0(val) bfin_write16(CAN0_MB19_ID0, val) +#define bfin_read_CAN0_MB19_ID1() bfin_read16(CAN0_MB19_ID1) +#define bfin_write_CAN0_MB19_ID1(val) bfin_write16(CAN0_MB19_ID1, val) +#define bfin_read_CAN0_MB20_DATA0() bfin_read16(CAN0_MB20_DATA0) +#define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val) +#define bfin_read_CAN0_MB20_DATA1() bfin_read16(CAN0_MB20_DATA1) +#define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val) +#define bfin_read_CAN0_MB20_DATA2() bfin_read16(CAN0_MB20_DATA2) +#define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val) +#define bfin_read_CAN0_MB20_DATA3() bfin_read16(CAN0_MB20_DATA3) +#define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val) +#define bfin_read_CAN0_MB20_LENGTH() bfin_read16(CAN0_MB20_LENGTH) +#define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val) +#define bfin_read_CAN0_MB20_TIMESTAMP() bfin_read16(CAN0_MB20_TIMESTAMP) +#define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val) +#define bfin_read_CAN0_MB20_ID0() bfin_read16(CAN0_MB20_ID0) +#define bfin_write_CAN0_MB20_ID0(val) bfin_write16(CAN0_MB20_ID0, val) +#define bfin_read_CAN0_MB20_ID1() bfin_read16(CAN0_MB20_ID1) +#define bfin_write_CAN0_MB20_ID1(val) bfin_write16(CAN0_MB20_ID1, val) +#define bfin_read_CAN0_MB21_DATA0() bfin_read16(CAN0_MB21_DATA0) +#define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val) +#define bfin_read_CAN0_MB21_DATA1() bfin_read16(CAN0_MB21_DATA1) +#define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val) +#define bfin_read_CAN0_MB21_DATA2() bfin_read16(CAN0_MB21_DATA2) +#define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val) +#define bfin_read_CAN0_MB21_DATA3() bfin_read16(CAN0_MB21_DATA3) +#define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val) +#define bfin_read_CAN0_MB21_LENGTH() bfin_read16(CAN0_MB21_LENGTH) +#define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val) +#define bfin_read_CAN0_MB21_TIMESTAMP() bfin_read16(CAN0_MB21_TIMESTAMP) +#define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val) +#define bfin_read_CAN0_MB21_ID0() bfin_read16(CAN0_MB21_ID0) +#define bfin_write_CAN0_MB21_ID0(val) bfin_write16(CAN0_MB21_ID0, val) +#define bfin_read_CAN0_MB21_ID1() bfin_read16(CAN0_MB21_ID1) +#define bfin_write_CAN0_MB21_ID1(val) bfin_write16(CAN0_MB21_ID1, val) +#define bfin_read_CAN0_MB22_DATA0() bfin_read16(CAN0_MB22_DATA0) +#define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val) +#define bfin_read_CAN0_MB22_DATA1() bfin_read16(CAN0_MB22_DATA1) +#define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val) +#define bfin_read_CAN0_MB22_DATA2() bfin_read16(CAN0_MB22_DATA2) +#define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val) +#define bfin_read_CAN0_MB22_DATA3() bfin_read16(CAN0_MB22_DATA3) +#define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val) +#define bfin_read_CAN0_MB22_LENGTH() bfin_read16(CAN0_MB22_LENGTH) +#define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val) +#define bfin_read_CAN0_MB22_TIMESTAMP() bfin_read16(CAN0_MB22_TIMESTAMP) +#define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val) +#define bfin_read_CAN0_MB22_ID0() bfin_read16(CAN0_MB22_ID0) +#define bfin_write_CAN0_MB22_ID0(val) bfin_write16(CAN0_MB22_ID0, val) +#define bfin_read_CAN0_MB22_ID1() bfin_read16(CAN0_MB22_ID1) +#define bfin_write_CAN0_MB22_ID1(val) bfin_write16(CAN0_MB22_ID1, val) +#define bfin_read_CAN0_MB23_DATA0() bfin_read16(CAN0_MB23_DATA0) +#define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val) +#define bfin_read_CAN0_MB23_DATA1() bfin_read16(CAN0_MB23_DATA1) +#define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val) +#define bfin_read_CAN0_MB23_DATA2() bfin_read16(CAN0_MB23_DATA2) +#define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val) +#define bfin_read_CAN0_MB23_DATA3() bfin_read16(CAN0_MB23_DATA3) +#define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val) +#define bfin_read_CAN0_MB23_LENGTH() bfin_read16(CAN0_MB23_LENGTH) +#define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val) +#define bfin_read_CAN0_MB23_TIMESTAMP() bfin_read16(CAN0_MB23_TIMESTAMP) +#define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val) +#define bfin_read_CAN0_MB23_ID0() bfin_read16(CAN0_MB23_ID0) +#define bfin_write_CAN0_MB23_ID0(val) bfin_write16(CAN0_MB23_ID0, val) +#define bfin_read_CAN0_MB23_ID1() bfin_read16(CAN0_MB23_ID1) +#define bfin_write_CAN0_MB23_ID1(val) bfin_write16(CAN0_MB23_ID1, val) +#define bfin_read_CAN0_MB24_DATA0() bfin_read16(CAN0_MB24_DATA0) +#define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val) +#define bfin_read_CAN0_MB24_DATA1() bfin_read16(CAN0_MB24_DATA1) +#define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val) +#define bfin_read_CAN0_MB24_DATA2() bfin_read16(CAN0_MB24_DATA2) +#define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val) +#define bfin_read_CAN0_MB24_DATA3() bfin_read16(CAN0_MB24_DATA3) +#define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val) +#define bfin_read_CAN0_MB24_LENGTH() bfin_read16(CAN0_MB24_LENGTH) +#define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val) +#define bfin_read_CAN0_MB24_TIMESTAMP() bfin_read16(CAN0_MB24_TIMESTAMP) +#define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val) +#define bfin_read_CAN0_MB24_ID0() bfin_read16(CAN0_MB24_ID0) +#define bfin_write_CAN0_MB24_ID0(val) bfin_write16(CAN0_MB24_ID0, val) +#define bfin_read_CAN0_MB24_ID1() bfin_read16(CAN0_MB24_ID1) +#define bfin_write_CAN0_MB24_ID1(val) bfin_write16(CAN0_MB24_ID1, val) +#define bfin_read_CAN0_MB25_DATA0() bfin_read16(CAN0_MB25_DATA0) +#define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val) +#define bfin_read_CAN0_MB25_DATA1() bfin_read16(CAN0_MB25_DATA1) +#define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val) +#define bfin_read_CAN0_MB25_DATA2() bfin_read16(CAN0_MB25_DATA2) +#define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val) +#define bfin_read_CAN0_MB25_DATA3() bfin_read16(CAN0_MB25_DATA3) +#define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val) +#define bfin_read_CAN0_MB25_LENGTH() bfin_read16(CAN0_MB25_LENGTH) +#define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val) +#define bfin_read_CAN0_MB25_TIMESTAMP() bfin_read16(CAN0_MB25_TIMESTAMP) +#define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val) +#define bfin_read_CAN0_MB25_ID0() bfin_read16(CAN0_MB25_ID0) +#define bfin_write_CAN0_MB25_ID0(val) bfin_write16(CAN0_MB25_ID0, val) +#define bfin_read_CAN0_MB25_ID1() bfin_read16(CAN0_MB25_ID1) +#define bfin_write_CAN0_MB25_ID1(val) bfin_write16(CAN0_MB25_ID1, val) +#define bfin_read_CAN0_MB26_DATA0() bfin_read16(CAN0_MB26_DATA0) +#define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val) +#define bfin_read_CAN0_MB26_DATA1() bfin_read16(CAN0_MB26_DATA1) +#define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val) +#define bfin_read_CAN0_MB26_DATA2() bfin_read16(CAN0_MB26_DATA2) +#define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val) +#define bfin_read_CAN0_MB26_DATA3() bfin_read16(CAN0_MB26_DATA3) +#define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val) +#define bfin_read_CAN0_MB26_LENGTH() bfin_read16(CAN0_MB26_LENGTH) +#define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val) +#define bfin_read_CAN0_MB26_TIMESTAMP() bfin_read16(CAN0_MB26_TIMESTAMP) +#define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val) +#define bfin_read_CAN0_MB26_ID0() bfin_read16(CAN0_MB26_ID0) +#define bfin_write_CAN0_MB26_ID0(val) bfin_write16(CAN0_MB26_ID0, val) +#define bfin_read_CAN0_MB26_ID1() bfin_read16(CAN0_MB26_ID1) +#define bfin_write_CAN0_MB26_ID1(val) bfin_write16(CAN0_MB26_ID1, val) +#define bfin_read_CAN0_MB27_DATA0() bfin_read16(CAN0_MB27_DATA0) +#define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val) +#define bfin_read_CAN0_MB27_DATA1() bfin_read16(CAN0_MB27_DATA1) +#define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val) +#define bfin_read_CAN0_MB27_DATA2() bfin_read16(CAN0_MB27_DATA2) +#define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val) +#define bfin_read_CAN0_MB27_DATA3() bfin_read16(CAN0_MB27_DATA3) +#define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val) +#define bfin_read_CAN0_MB27_LENGTH() bfin_read16(CAN0_MB27_LENGTH) +#define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val) +#define bfin_read_CAN0_MB27_TIMESTAMP() bfin_read16(CAN0_MB27_TIMESTAMP) +#define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val) +#define bfin_read_CAN0_MB27_ID0() bfin_read16(CAN0_MB27_ID0) +#define bfin_write_CAN0_MB27_ID0(val) bfin_write16(CAN0_MB27_ID0, val) +#define bfin_read_CAN0_MB27_ID1() bfin_read16(CAN0_MB27_ID1) +#define bfin_write_CAN0_MB27_ID1(val) bfin_write16(CAN0_MB27_ID1, val) +#define bfin_read_CAN0_MB28_DATA0() bfin_read16(CAN0_MB28_DATA0) +#define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val) +#define bfin_read_CAN0_MB28_DATA1() bfin_read16(CAN0_MB28_DATA1) +#define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val) +#define bfin_read_CAN0_MB28_DATA2() bfin_read16(CAN0_MB28_DATA2) +#define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val) +#define bfin_read_CAN0_MB28_DATA3() bfin_read16(CAN0_MB28_DATA3) +#define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val) +#define bfin_read_CAN0_MB28_LENGTH() bfin_read16(CAN0_MB28_LENGTH) +#define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val) +#define bfin_read_CAN0_MB28_TIMESTAMP() bfin_read16(CAN0_MB28_TIMESTAMP) +#define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val) +#define bfin_read_CAN0_MB28_ID0() bfin_read16(CAN0_MB28_ID0) +#define bfin_write_CAN0_MB28_ID0(val) bfin_write16(CAN0_MB28_ID0, val) +#define bfin_read_CAN0_MB28_ID1() bfin_read16(CAN0_MB28_ID1) +#define bfin_write_CAN0_MB28_ID1(val) bfin_write16(CAN0_MB28_ID1, val) +#define bfin_read_CAN0_MB29_DATA0() bfin_read16(CAN0_MB29_DATA0) +#define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val) +#define bfin_read_CAN0_MB29_DATA1() bfin_read16(CAN0_MB29_DATA1) +#define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val) +#define bfin_read_CAN0_MB29_DATA2() bfin_read16(CAN0_MB29_DATA2) +#define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val) +#define bfin_read_CAN0_MB29_DATA3() bfin_read16(CAN0_MB29_DATA3) +#define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val) +#define bfin_read_CAN0_MB29_LENGTH() bfin_read16(CAN0_MB29_LENGTH) +#define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val) +#define bfin_read_CAN0_MB29_TIMESTAMP() bfin_read16(CAN0_MB29_TIMESTAMP) +#define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val) +#define bfin_read_CAN0_MB29_ID0() bfin_read16(CAN0_MB29_ID0) +#define bfin_write_CAN0_MB29_ID0(val) bfin_write16(CAN0_MB29_ID0, val) +#define bfin_read_CAN0_MB29_ID1() bfin_read16(CAN0_MB29_ID1) +#define bfin_write_CAN0_MB29_ID1(val) bfin_write16(CAN0_MB29_ID1, val) +#define bfin_read_CAN0_MB30_DATA0() bfin_read16(CAN0_MB30_DATA0) +#define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val) +#define bfin_read_CAN0_MB30_DATA1() bfin_read16(CAN0_MB30_DATA1) +#define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val) +#define bfin_read_CAN0_MB30_DATA2() bfin_read16(CAN0_MB30_DATA2) +#define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val) +#define bfin_read_CAN0_MB30_DATA3() bfin_read16(CAN0_MB30_DATA3) +#define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val) +#define bfin_read_CAN0_MB30_LENGTH() bfin_read16(CAN0_MB30_LENGTH) +#define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val) +#define bfin_read_CAN0_MB30_TIMESTAMP() bfin_read16(CAN0_MB30_TIMESTAMP) +#define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val) +#define bfin_read_CAN0_MB30_ID0() bfin_read16(CAN0_MB30_ID0) +#define bfin_write_CAN0_MB30_ID0(val) bfin_write16(CAN0_MB30_ID0, val) +#define bfin_read_CAN0_MB30_ID1() bfin_read16(CAN0_MB30_ID1) +#define bfin_write_CAN0_MB30_ID1(val) bfin_write16(CAN0_MB30_ID1, val) +#define bfin_read_CAN0_MB31_DATA0() bfin_read16(CAN0_MB31_DATA0) +#define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val) +#define bfin_read_CAN0_MB31_DATA1() bfin_read16(CAN0_MB31_DATA1) +#define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val) +#define bfin_read_CAN0_MB31_DATA2() bfin_read16(CAN0_MB31_DATA2) +#define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val) +#define bfin_read_CAN0_MB31_DATA3() bfin_read16(CAN0_MB31_DATA3) +#define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val) +#define bfin_read_CAN0_MB31_LENGTH() bfin_read16(CAN0_MB31_LENGTH) +#define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val) +#define bfin_read_CAN0_MB31_TIMESTAMP() bfin_read16(CAN0_MB31_TIMESTAMP) +#define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val) +#define bfin_read_CAN0_MB31_ID0() bfin_read16(CAN0_MB31_ID0) +#define bfin_write_CAN0_MB31_ID0(val) bfin_write16(CAN0_MB31_ID0, val) +#define bfin_read_CAN0_MB31_ID1() bfin_read16(CAN0_MB31_ID1) +#define bfin_write_CAN0_MB31_ID1(val) bfin_write16(CAN0_MB31_ID1, val) + +/* Counter Registers */ + +#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG) +#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val) +#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK) +#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val) +#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS) +#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val) +#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND) +#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val) +#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE) +#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val) +#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER) +#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val) +#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX) +#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val) +#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN) +#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val) + +/* RSI Register */ +#define bfin_read_RSI_CLK_CTL() bfin_read16(RSI_CLK_CONTROL) +#define bfin_write_RSI_CLK_CTL(val) bfin_write16(RSI_CLK_CONTROL, val) +#define bfin_read_RSI_ARGUMENT() bfin_read32(RSI_ARGUMENT) +#define bfin_write_RSI_ARGUMENT(val) bfin_write32(RSI_ARGUMENT, val) +#define bfin_read_RSI_COMMAND() bfin_read16(RSI_COMMAND) +#define bfin_write_RSI_COMMAND(val) bfin_write16(RSI_COMMAND, val) +#define bfin_read_RSI_RESP_CMD() bfin_read16(RSI_RESP_CMD) +#define bfin_write_RSI_RESP_CMD(val) bfin_write16(RSI_RESP_CMD, val) +#define bfin_read_RSI_RESPONSE0() bfin_read32(RSI_RESPONSE0) +#define bfin_write_RSI_RESPONSE0(val) bfin_write32(RSI_RESPONSE0, val) +#define bfin_read_RSI_RESPONSE1() bfin_read32(RSI_RESPONSE1) +#define bfin_write_RSI_RESPONSE1(val) bfin_write32(RSI_RESPONSE1, val) +#define bfin_read_RSI_RESPONSE2() bfin_read32(RSI_RESPONSE2) +#define bfin_write_RSI_RESPONSE2(val) bfin_write32(RSI_RESPONSE2, val) +#define bfin_read_RSI_RESPONSE3() bfin_read32(RSI_RESPONSE3) +#define bfin_write_RSI_RESPONSE3(val) bfin_write32(RSI_RESPONSE3, val) +#define bfin_read_RSI_DATA_TIMER() bfin_read32(RSI_DATA_TIMER) +#define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val) +#define bfin_read_RSI_DATA_LGTH() bfin_read16(RSI_DATA_LGTH) +#define bfin_write_RSI_DATA_LGTH(val) bfin_write16(RSI_DATA_LGTH, val) +#define bfin_read_RSI_DATA_CTL() bfin_read16(RSI_DATA_CONTROL) +#define bfin_write_RSI_DATA_CTL(val) bfin_write16(RSI_DATA_CONTROL, val) +#define bfin_read_RSI_DATA_CNT() bfin_read16(RSI_DATA_CNT) +#define bfin_write_RSI_DATA_CNT(val) bfin_write16(RSI_DATA_CNT, val) +#define bfin_read_RSI_STATUS() bfin_read32(RSI_STATUS) +#define bfin_write_RSI_STATUS(val) bfin_write32(RSI_STATUS, val) +#define bfin_read_RSI_STATUS_CLR() bfin_read16(RSI_STATUSCL) +#define bfin_write_RSI_STATUS_CLR(val) bfin_write16(RSI_STATUSCL, val) +#define bfin_read_RSI_MASK0() bfin_read32(RSI_MASK0) +#define bfin_write_RSI_MASK0(val) bfin_write32(RSI_MASK0, val) +#define bfin_read_RSI_MASK1() bfin_read32(RSI_MASK1) +#define bfin_write_RSI_MASK1(val) bfin_write32(RSI_MASK1, val) +#define bfin_read_RSI_FIFO_CNT() bfin_read16(RSI_FIFO_CNT) +#define bfin_write_RSI_FIFO_CNT(val) bfin_write16(RSI_FIFO_CNT, val) +#define bfin_read_RSI_CEATA_CONTROL() bfin_read16(RSI_CEATA_CONTROL) +#define bfin_write_RSI_CEATA_CONTROL(val) bfin_write16(RSI_CEATA_CONTROL, val) +#define bfin_read_RSI_BLKSZ() bfin_read16(RSI_BLKSZ) +#define bfin_write_RSI_BLKSZ(val) bfin_write16(RSI_BLKSZ, val) +#define bfin_read_RSI_FIFO() bfin_read32(RSI_FIFO) +#define bfin_write_RSI_FIFO(val) bfin_write32(RSI_FIFO, val) +#define bfin_read_RSI_E_STATUS() bfin_read32(RSI_ESTAT) +#define bfin_write_RSI_E_STATUS(val) bfin_write32(RSI_ESTAT, val) +#define bfin_read_RSI_E_MASK() bfin_read32(RSI_EMASK) +#define bfin_write_RSI_E_MASK(val) bfin_write32(RSI_EMASK, val) +#define bfin_read_RSI_CFG() bfin_read16(RSI_CONFIG) +#define bfin_write_RSI_CFG(val) bfin_write16(RSI_CONFIG, val) +#define bfin_read_RSI_RD_WAIT_EN() bfin_read16(RSI_RD_WAIT_EN) +#define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val) +#define bfin_read_RSI_PID0() bfin_read16(RSI_PID0) +#define bfin_write_RSI_PID0(val) bfin_write16(RSI_PID0, val) +#define bfin_read_RSI_PID1() bfin_read16(RSI_PID1) +#define bfin_write_RSI_PID1(val) bfin_write16(RSI_PID1, val) +#define bfin_read_RSI_PID2() bfin_read16(RSI_PID2) +#define bfin_write_RSI_PID2(val) bfin_write16(RSI_PID2, val) +#define bfin_read_RSI_PID3() bfin_read16(RSI_PID3) +#define bfin_write_RSI_PID3(val) bfin_write16(RSI_PID3, val) + +/* usb register */ +#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLL_OSC) +#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLL_OSC, val) +#define bfin_write_USB_VBUS_CTL(val) bfin_write8(USB_VBUS_CTL, val) +#define bfin_write_USB_APHY_CNTRL(val) bfin_write8(USB_PHY_CTL, val) +#define bfin_read_USB_APHY_CNTRL() bfin_read8(USB_PHY_CTL) + +#endif /* _CDEF_BF60X_H */ + diff --git a/arch/blackfin/mach-bf609/include/mach/defBF609.h b/arch/blackfin/mach-bf609/include/mach/defBF609.h new file mode 100644 index 000000000000..19690cc42113 --- /dev/null +++ b/arch/blackfin/mach-bf609/include/mach/defBF609.h @@ -0,0 +1,15 @@ +/* + * Copyright 2011 Analog Devices Inc. + * + * Licensed under the Clear BSD license or the GPL-2 (or later) + */ + +#ifndef _DEF_BF609_H +#define _DEF_BF609_H + +/* Include defBF60x_base.h for the set of #defines that are common to all ADSP-BF60x processors */ +#include "defBF60x_base.h" + +/* The following are the #defines needed by ADSP-BF609 that are not in the common header */ + +#endif /* _DEF_BF609_H */ diff --git a/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h b/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h new file mode 100644 index 000000000000..6aac38544cc9 --- /dev/null +++ b/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h @@ -0,0 +1,3587 @@ +/* + * Copyright 2011 Analog Devices Inc. + * + * Licensed under the Clear BSD license or the GPL-2 (or later) + */ + +#ifndef _DEF_BF60X_H +#define _DEF_BF60X_H + + +/* ************************************************************** */ +/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF60x */ +/* ************************************************************** */ + + +/* ========================= + CNT Registers + ========================= */ + +/* ========================= + CNT0 + ========================= */ +#define CNT_CONFIG 0xFFC00400 /* CNT0 Configuration Register */ +#define CNT_IMASK 0xFFC00404 /* CNT0 Interrupt Mask Register */ +#define CNT_STATUS 0xFFC00408 /* CNT0 Status Register */ +#define CNT_COMMAND 0xFFC0040C /* CNT0 Command Register */ +#define CNT_DEBOUNCE 0xFFC00410 /* CNT0 Debounce Register */ +#define CNT_COUNTER 0xFFC00414 /* CNT0 Counter Register */ +#define CNT_MAX 0xFFC00418 /* CNT0 Maximum Count Register */ +#define CNT_MIN 0xFFC0041C /* CNT0 Minimum Count Register */ + + +/* ========================= + RSI Registers + ========================= */ + +#define RSI_CLK_CONTROL 0xFFC00604 /* RSI0 Clock Control Register */ +#define RSI_ARGUMENT 0xFFC00608 /* RSI0 Argument Register */ +#define RSI_COMMAND 0xFFC0060C /* RSI0 Command Register */ +#define RSI_RESP_CMD 0xFFC00610 /* RSI0 Response Command Register */ +#define RSI_RESPONSE0 0xFFC00614 /* RSI0 Response 0 Register */ +#define RSI_RESPONSE1 0xFFC00618 /* RSI0 Response 1 Register */ +#define RSI_RESPONSE2 0xFFC0061C /* RSI0 Response 2 Register */ +#define RSI_RESPONSE3 0xFFC00620 /* RSI0 Response 3 Register */ +#define RSI_DATA_TIMER 0xFFC00624 /* RSI0 Data Timer Register */ +#define RSI_DATA_LGTH 0xFFC00628 /* RSI0 Data Length Register */ +#define RSI_DATA_CONTROL 0xFFC0062C /* RSI0 Data Control Register */ +#define RSI_DATA_CNT 0xFFC00630 /* RSI0 Data Count Register */ +#define RSI_STATUS 0xFFC00634 /* RSI0 Status Register */ +#define RSI_STATUSCL 0xFFC00638 /* RSI0 Status Clear Register */ +#define RSI_MASK0 0xFFC0063C /* RSI0 Interrupt 0 Mask Register */ +#define RSI_MASK1 0xFFC00640 /* RSI0 Interrupt 1 Mask Register */ +#define RSI_FIFO_CNT 0xFFC00648 /* RSI0 FIFO Counter Register */ +#define RSI_CEATA_CONTROL 0xFFC0064C /* RSI0 This register contains bit to dis CCS gen */ +#define RSI_BOOT_TCNTR 0xFFC00650 /* RSI0 Boot Timing Counter Register */ +#define RSI_BACK_TOUT 0xFFC00654 /* RSI0 Boot Acknowledge Timeout Register */ +#define RSI_SLP_WKUP_TOUT 0xFFC00658 /* RSI0 Sleep Wakeup Timeout Register */ +#define RSI_BLKSZ 0xFFC0065C /* RSI0 Block Size Register */ +#define RSI_FIFO 0xFFC00680 /* RSI0 Data FIFO Register */ +#define RSI_ESTAT 0xFFC006C0 /* RSI0 Exception Status Register */ +#define RSI_EMASK 0xFFC006C4 /* RSI0 Exception Mask Register */ +#define RSI_CONFIG 0xFFC006C8 /* RSI0 Configuration Register */ +#define RSI_RD_WAIT_EN 0xFFC006CC /* RSI0 Read Wait Enable Register */ +#define RSI_PID0 0xFFC006D0 /* RSI0 Peripheral Identification Register */ +#define RSI_PID1 0xFFC006D4 /* RSI0 Peripheral Identification Register */ +#define RSI_PID2 0xFFC006D8 /* RSI0 Peripheral Identification Register */ +#define RSI_PID3 0xFFC006DC /* RSI0 Peripheral Identification Register */ + +/* ========================= + CAN Registers + ========================= */ + +/* ========================= + CAN0 + ========================= */ +#define CAN0_MC1 0xFFC00A00 /* CAN0 Mailbox Configuration Register 1 */ +#define CAN0_MD1 0xFFC00A04 /* CAN0 Mailbox Direction Register 1 */ +#define CAN0_TRS1 0xFFC00A08 /* CAN0 Transmission Request Set Register 1 */ +#define CAN0_TRR1 0xFFC00A0C /* CAN0 Transmission Request Reset Register 1 */ +#define CAN0_TA1 0xFFC00A10 /* CAN0 Transmission Acknowledge Register 1 */ +#define CAN0_AA1 0xFFC00A14 /* CAN0 Abort Acknowledge Register 1 */ +#define CAN0_RMP1 0xFFC00A18 /* CAN0 Receive Message Pending Register 1 */ +#define CAN0_RML1 0xFFC00A1C /* CAN0 Receive Message Lost Register 1 */ +#define CAN0_MBTIF1 0xFFC00A20 /* CAN0 Mailbox Transmit Interrupt Flag Register 1 */ +#define CAN0_MBRIF1 0xFFC00A24 /* CAN0 Mailbox Receive Interrupt Flag Register 1 */ +#define CAN0_MBIM1 0xFFC00A28 /* CAN0 Mailbox Interrupt Mask Register 1 */ +#define CAN0_RFH1 0xFFC00A2C /* CAN0 Remote Frame Handling Register 1 */ +#define CAN0_OPSS1 0xFFC00A30 /* CAN0 Overwrite Protection/Single Shot Transmission Register 1 */ +#define CAN0_MC2 0xFFC00A40 /* CAN0 Mailbox Configuration Register 2 */ +#define CAN0_MD2 0xFFC00A44 /* CAN0 Mailbox Direction Register 2 */ +#define CAN0_TRS2 0xFFC00A48 /* CAN0 Transmission Request Set Register 2 */ +#define CAN0_TRR2 0xFFC00A4C /* CAN0 Transmission Request Reset Register 2 */ +#define CAN0_TA2 0xFFC00A50 /* CAN0 Transmission Acknowledge Register 2 */ +#define CAN0_AA2 0xFFC00A54 /* CAN0 Abort Acknowledge Register 2 */ +#define CAN0_RMP2 0xFFC00A58 /* CAN0 Receive Message Pending Register 2 */ +#define CAN0_RML2 0xFFC00A5C /* CAN0 Receive Message Lost Register 2 */ +#define CAN0_MBTIF2 0xFFC00A60 /* CAN0 Mailbox Transmit Interrupt Flag Register 2 */ +#define CAN0_MBRIF2 0xFFC00A64 /* CAN0 Mailbox Receive Interrupt Flag Register 2 */ +#define CAN0_MBIM2 0xFFC00A68 /* CAN0 Mailbox Interrupt Mask Register 2 */ +#define CAN0_RFH2 0xFFC00A6C /* CAN0 Remote Frame Handling Register 2 */ +#define CAN0_OPSS2 0xFFC00A70 /* CAN0 Overwrite Protection/Single Shot Transmission Register 2 */ +#define CAN0_CLOCK 0xFFC00A80 /* CAN0 Clock Register */ +#define CAN0_TIMING 0xFFC00A84 /* CAN0 Timing Register */ +#define CAN0_DEBUG 0xFFC00A88 /* CAN0 Debug Register */ +#define CAN0_STATUS 0xFFC00A8C /* CAN0 Status Register */ +#define CAN0_CEC 0xFFC00A90 /* CAN0 Error Counter Register */ +#define CAN0_GIS 0xFFC00A94 /* CAN0 Global CAN Interrupt Status */ +#define CAN0_GIM 0xFFC00A98 /* CAN0 Global CAN Interrupt Mask */ +#define CAN0_GIF 0xFFC00A9C /* CAN0 Global CAN Interrupt Flag */ +#define CAN0_CONTROL 0xFFC00AA0 /* CAN0 CAN Master Control Register */ +#define CAN0_INTR 0xFFC00AA4 /* CAN0 Interrupt Pending Register */ +#define CAN0_MBTD 0xFFC00AAC /* CAN0 Temporary Mailbox Disable Register */ +#define CAN0_EWR 0xFFC00AB0 /* CAN0 Error Counter Warning Level Register */ +#define CAN0_ESR 0xFFC00AB4 /* CAN0 Error Status Register */ +#define CAN0_UCCNT 0xFFC00AC4 /* CAN0 Universal Counter Register */ +#define CAN0_UCRC 0xFFC00AC8 /* CAN0 Universal Counter Reload/Capture Register */ +#define CAN0_UCCNF 0xFFC00ACC /* CAN0 Universal Counter Configuration Mode Register */ +#define CAN0_AM00L 0xFFC00B00 /* CAN0 Acceptance Mask Register (L) */ +#define CAN0_AM01L 0xFFC00B08 /* CAN0 Acceptance Mask Register (L) */ +#define CAN0_AM02L 0xFFC00B10 /* CAN0 Acceptance Mask Register (L) */ +#define CAN0_AM03L 0xFFC00B18 /* CAN0 Acceptance Mask Register (L) */ +#define CAN0_AM04L 0xFFC00B20 /* CAN0 Acceptance Mask Register (L) */ +#define CAN0_AM05L 0xFFC00B28 /* CAN0 Acceptance Mask Register (L) */ +#define CAN0_AM06L 0xFFC00B30 /* CAN0 Acceptance Mask Register (L) */ +#define CAN0_AM07L 0xFFC00B38 /* CAN0 Acceptance Mask Register (L) */ +#define CAN0_AM08L 0xFFC00B40 /* CAN0 Acceptance Mask Register (L) */ +#define CAN0_AM09L 0xFFC00B48 /* CAN0 Acceptance Mask Register (L) */ +#define CAN0_AM10L 0xFFC00B50 /* CAN0 Acceptance Mask Register (L) */ +#define CAN0_AM11L 0xFFC00B58 /* CAN0 Acceptance Mask Register (L) */ +#define CAN0_AM12L 0xFFC00B60 /* CAN0 Acceptance Mask Register (L) */ +#define CAN0_AM13L 0xFFC00B68 /* CAN0 Acceptance Mask Register (L) */ +#define CAN0_AM14L 0xFFC00B70 /* CAN0 Acceptance Mask Register (L) */ +#define CAN0_AM15L 0xFFC00B78 /* CAN0 Acceptance Mask Register (L) */ +#define CAN0_AM16L 0xFFC00B80 /* CAN0 Acceptance Mask Register (L) */ +#define CAN0_AM17L 0xFFC00B88 /* CAN0 Acceptance Mask Register (L) */ +#define CAN0_AM18L 0xFFC00B90 /* CAN0 Acceptance Mask Register (L) */ +#define CAN0_AM19L 0xFFC00B98 /* CAN0 Acceptance Mask Register (L) */ +#define CAN0_AM20L 0xFFC00BA0 /* CAN0 Acceptance Mask Register (L) */ +#define CAN0_AM21L 0xFFC00BA8 /* CAN0 Acceptance Mask Register (L) */ +#define CAN0_AM22L 0xFFC00BB0 /* CAN0 Acceptance Mask Register (L) */ +#define CAN0_AM23L 0xFFC00BB8 /* CAN0 Acceptance Mask Register (L) */ +#define CAN0_AM24L 0xFFC00BC0 /* CAN0 Acceptance Mask Register (L) */ +#define CAN0_AM25L 0xFFC00BC8 /* CAN0 Acceptance Mask Register (L) */ +#define CAN0_AM26L 0xFFC00BD0 /* CAN0 Acceptance Mask Register (L) */ +#define CAN0_AM27L 0xFFC00BD8 /* CAN0 Acceptance Mask Register (L) */ +#define CAN0_AM28L 0xFFC00BE0 /* CAN0 Acceptance Mask Register (L) */ +#define CAN0_AM29L 0xFFC00BE8 /* CAN0 Acceptance Mask Register (L) */ +#define CAN0_AM30L 0xFFC00BF0 /* CAN0 Acceptance Mask Register (L) */ +#define CAN0_AM31L 0xFFC00BF8 /* CAN0 Acceptance Mask Register (L) */ +#define CAN0_AM00H 0xFFC00B04 /* CAN0 Acceptance Mask Register (H) */ +#define CAN0_AM01H 0xFFC00B0C /* CAN0 Acceptance Mask Register (H) */ +#define CAN0_AM02H 0xFFC00B14 /* CAN0 Acceptance Mask Register (H) */ +#define CAN0_AM03H 0xFFC00B1C /* CAN0 Acceptance Mask Register (H) */ +#define CAN0_AM04H 0xFFC00B24 /* CAN0 Acceptance Mask Register (H) */ +#define CAN0_AM05H 0xFFC00B2C /* CAN0 Acceptance Mask Register (H) */ +#define CAN0_AM06H 0xFFC00B34 /* CAN0 Acceptance Mask Register (H) */ +#define CAN0_AM07H 0xFFC00B3C /* CAN0 Acceptance Mask Register (H) */ +#define CAN0_AM08H 0xFFC00B44 /* CAN0 Acceptance Mask Register (H) */ +#define CAN0_AM09H 0xFFC00B4C /* CAN0 Acceptance Mask Register (H) */ +#define CAN0_AM10H 0xFFC00B54 /* CAN0 Acceptance Mask Register (H) */ +#define CAN0_AM11H 0xFFC00B5C /* CAN0 Acceptance Mask Register (H) */ +#define CAN0_AM12H 0xFFC00B64 /* CAN0 Acceptance Mask Register (H) */ +#define CAN0_AM13H 0xFFC00B6C /* CAN0 Acceptance Mask Register (H) */ +#define CAN0_AM14H 0xFFC00B74 /* CAN0 Acceptance Mask Register (H) */ +#define CAN0_AM15H 0xFFC00B7C /* CAN0 Acceptance Mask Register (H) */ +#define CAN0_AM16H 0xFFC00B84 /* CAN0 Acceptance Mask Register (H) */ +#define CAN0_AM17H 0xFFC00B8C /* CAN0 Acceptance Mask Register (H) */ +#define CAN0_AM18H 0xFFC00B94 /* CAN0 Acceptance Mask Register (H) */ +#define CAN0_AM19H 0xFFC00B9C /* CAN0 Acceptance Mask Register (H) */ +#define CAN0_AM20H 0xFFC00BA4 /* CAN0 Acceptance Mask Register (H) */ +#define CAN0_AM21H 0xFFC00BAC /* CAN0 Acceptance Mask Register (H) */ +#define CAN0_AM22H 0xFFC00BB4 /* CAN0 Acceptance Mask Register (H) */ +#define CAN0_AM23H 0xFFC00BBC /* CAN0 Acceptance Mask Register (H) */ +#define CAN0_AM24H 0xFFC00BC4 /* CAN0 Acceptance Mask Register (H) */ +#define CAN0_AM25H 0xFFC00BCC /* CAN0 Acceptance Mask Register (H) */ +#define CAN0_AM26H 0xFFC00BD4 /* CAN0 Acceptance Mask Register (H) */ +#define CAN0_AM27H 0xFFC00BDC /* CAN0 Acceptance Mask Register (H) */ +#define CAN0_AM28H 0xFFC00BE4 /* CAN0 Acceptance Mask Register (H) */ +#define CAN0_AM29H 0xFFC00BEC /* CAN0 Acceptance Mask Register (H) */ +#define CAN0_AM30H 0xFFC00BF4 /* CAN0 Acceptance Mask Register (H) */ +#define CAN0_AM31H 0xFFC00BFC /* CAN0 Acceptance Mask Register (H) */ +#define CAN0_MB00_DATA0 0xFFC00C00 /* CAN0 Mailbox Word 0 Register */ +#define CAN0_MB01_DATA0 0xFFC00C20 /* CAN0 Mailbox Word 0 Register */ +#define CAN0_MB02_DATA0 0xFFC00C40 /* CAN0 Mailbox Word 0 Register */ +#define CAN0_MB03_DATA0 0xFFC00C60 /* CAN0 Mailbox Word 0 Register */ +#define CAN0_MB04_DATA0 0xFFC00C80 /* CAN0 Mailbox Word 0 Register */ +#define CAN0_MB05_DATA0 0xFFC00CA0 /* CAN0 Mailbox Word 0 Register */ +#define CAN0_MB06_DATA0 0xFFC00CC0 /* CAN0 Mailbox Word 0 Register */ +#define CAN0_MB07_DATA0 0xFFC00CE0 /* CAN0 Mailbox Word 0 Register */ +#define CAN0_MB08_DATA0 0xFFC00D00 /* CAN0 Mailbox Word 0 Register */ +#define CAN0_MB09_DATA0 0xFFC00D20 /* CAN0 Mailbox Word 0 Register */ +#define CAN0_MB10_DATA0 0xFFC00D40 /* CAN0 Mailbox Word 0 Register */ +#define CAN0_MB11_DATA0 0xFFC00D60 /* CAN0 Mailbox Word 0 Register */ +#define CAN0_MB12_DATA0 0xFFC00D80 /* CAN0 Mailbox Word 0 Register */ +#define CAN0_MB13_DATA0 0xFFC00DA0 /* CAN0 Mailbox Word 0 Register */ +#define CAN0_MB14_DATA0 0xFFC00DC0 /* CAN0 Mailbox Word 0 Register */ +#define CAN0_MB15_DATA0 0xFFC00DE0 /* CAN0 Mailbox Word 0 Register */ +#define CAN0_MB16_DATA0 0xFFC00E00 /* CAN0 Mailbox Word 0 Register */ +#define CAN0_MB17_DATA0 0xFFC00E20 /* CAN0 Mailbox Word 0 Register */ +#define CAN0_MB18_DATA0 0xFFC00E40 /* CAN0 Mailbox Word 0 Register */ +#define CAN0_MB19_DATA0 0xFFC00E60 /* CAN0 Mailbox Word 0 Register */ +#define CAN0_MB20_DATA0 0xFFC00E80 /* CAN0 Mailbox Word 0 Register */ +#define CAN0_MB21_DATA0 0xFFC00EA0 /* CAN0 Mailbox Word 0 Register */ +#define CAN0_MB22_DATA0 0xFFC00EC0 /* CAN0 Mailbox Word 0 Register */ +#define CAN0_MB23_DATA0 0xFFC00EE0 /* CAN0 Mailbox Word 0 Register */ +#define CAN0_MB24_DATA0 0xFFC00F00 /* CAN0 Mailbox Word 0 Register */ +#define CAN0_MB25_DATA0 0xFFC00F20 /* CAN0 Mailbox Word 0 Register */ +#define CAN0_MB26_DATA0 0xFFC00F40 /* CAN0 Mailbox Word 0 Register */ +#define CAN0_MB27_DATA0 0xFFC00F60 /* CAN0 Mailbox Word 0 Register */ +#define CAN0_MB28_DATA0 0xFFC00F80 /* CAN0 Mailbox Word 0 Register */ +#define CAN0_MB29_DATA0 0xFFC00FA0 /* CAN0 Mailbox Word 0 Register */ +#define CAN0_MB30_DATA0 0xFFC00FC0 /* CAN0 Mailbox Word 0 Register */ +#define CAN0_MB31_DATA0 0xFFC00FE0 /* CAN0 Mailbox Word 0 Register */ +#define CAN0_MB00_DATA1 0xFFC00C04 /* CAN0 Mailbox Word 1 Register */ +#define CAN0_MB01_DATA1 0xFFC00C24 /* CAN0 Mailbox Word 1 Register */ +#define CAN0_MB02_DATA1 0xFFC00C44 /* CAN0 Mailbox Word 1 Register */ +#define CAN0_MB03_DATA1 0xFFC00C64 /* CAN0 Mailbox Word 1 Register */ +#define CAN0_MB04_DATA1 0xFFC00C84 /* CAN0 Mailbox Word 1 Register */ +#define CAN0_MB05_DATA1 0xFFC00CA4 /* CAN0 Mailbox Word 1 Register */ +#define CAN0_MB06_DATA1 0xFFC00CC4 /* CAN0 Mailbox Word 1 Register */ +#define CAN0_MB07_DATA1 0xFFC00CE4 /* CAN0 Mailbox Word 1 Register */ +#define CAN0_MB08_DATA1 0xFFC00D04 /* CAN0 Mailbox Word 1 Register */ +#define CAN0_MB09_DATA1 0xFFC00D24 /* CAN0 Mailbox Word 1 Register */ +#define CAN0_MB10_DATA1 0xFFC00D44 /* CAN0 Mailbox Word 1 Register */ +#define CAN0_MB11_DATA1 0xFFC00D64 /* CAN0 Mailbox Word 1 Register */ +#define CAN0_MB12_DATA1 0xFFC00D84 /* CAN0 Mailbox Word 1 Register */ +#define CAN0_MB13_DATA1 0xFFC00DA4 /* CAN0 Mailbox Word 1 Register */ +#define CAN0_MB14_DATA1 0xFFC00DC4 /* CAN0 Mailbox Word 1 Register */ +#define CAN0_MB15_DATA1 0xFFC00DE4 /* CAN0 Mailbox Word 1 Register */ +#define CAN0_MB16_DATA1 0xFFC00E04 /* CAN0 Mailbox Word 1 Register */ +#define CAN0_MB17_DATA1 0xFFC00E24 /* CAN0 Mailbox Word 1 Register */ +#define CAN0_MB18_DATA1 0xFFC00E44 /* CAN0 Mailbox Word 1 Register */ +#define CAN0_MB19_DATA1 0xFFC00E64 /* CAN0 Mailbox Word 1 Register */ +#define CAN0_MB20_DATA1 0xFFC00E84 /* CAN0 Mailbox Word 1 Register */ +#define CAN0_MB21_DATA1 0xFFC00EA4 /* CAN0 Mailbox Word 1 Register */ +#define CAN0_MB22_DATA1 0xFFC00EC4 /* CAN0 Mailbox Word 1 Register */ +#define CAN0_MB23_DATA1 0xFFC00EE4 /* CAN0 Mailbox Word 1 Register */ +#define CAN0_MB24_DATA1 0xFFC00F04 /* CAN0 Mailbox Word 1 Register */ +#define CAN0_MB25_DATA1 0xFFC00F24 /* CAN0 Mailbox Word 1 Register */ +#define CAN0_MB26_DATA1 0xFFC00F44 /* CAN0 Mailbox Word 1 Register */ +#define CAN0_MB27_DATA1 0xFFC00F64 /* CAN0 Mailbox Word 1 Register */ +#define CAN0_MB28_DATA1 0xFFC00F84 /* CAN0 Mailbox Word 1 Register */ +#define CAN0_MB29_DATA1 0xFFC00FA4 /* CAN0 Mailbox Word 1 Register */ +#define CAN0_MB30_DATA1 0xFFC00FC4 /* CAN0 Mailbox Word 1 Register */ +#define CAN0_MB31_DATA1 0xFFC00FE4 /* CAN0 Mailbox Word 1 Register */ +#define CAN0_MB00_DATA2 0xFFC00C08 /* CAN0 Mailbox Word 2 Register */ +#define CAN0_MB01_DATA2 0xFFC00C28 /* CAN0 Mailbox Word 2 Register */ +#define CAN0_MB02_DATA2 0xFFC00C48 /* CAN0 Mailbox Word 2 Register */ +#define CAN0_MB03_DATA2 0xFFC00C68 /* CAN0 Mailbox Word 2 Register */ +#define CAN0_MB04_DATA2 0xFFC00C88 /* CAN0 Mailbox Word 2 Register */ +#define CAN0_MB05_DATA2 0xFFC00CA8 /* CAN0 Mailbox Word 2 Register */ +#define CAN0_MB06_DATA2 0xFFC00CC8 /* CAN0 Mailbox Word 2 Register */ +#define CAN0_MB07_DATA2 0xFFC00CE8 /* CAN0 Mailbox Word 2 Register */ +#define CAN0_MB08_DATA2 0xFFC00D08 /* CAN0 Mailbox Word 2 Register */ +#define CAN0_MB09_DATA2 0xFFC00D28 /* CAN0 Mailbox Word 2 Register */ +#define CAN0_MB10_DATA2 0xFFC00D48 /* CAN0 Mailbox Word 2 Register */ +#define CAN0_MB11_DATA2 0xFFC00D68 /* CAN0 Mailbox Word 2 Register */ +#define CAN0_MB12_DATA2 0xFFC00D88 /* CAN0 Mailbox Word 2 Register */ +#define CAN0_MB13_DATA2 0xFFC00DA8 /* CAN0 Mailbox Word 2 Register */ +#define CAN0_MB14_DATA2 0xFFC00DC8 /* CAN0 Mailbox Word 2 Register */ +#define CAN0_MB15_DATA2 0xFFC00DE8 /* CAN0 Mailbox Word 2 Register */ +#define CAN0_MB16_DATA2 0xFFC00E08 /* CAN0 Mailbox Word 2 Register */ +#define CAN0_MB17_DATA2 0xFFC00E28 /* CAN0 Mailbox Word 2 Register */ +#define CAN0_MB18_DATA2 0xFFC00E48 /* CAN0 Mailbox Word 2 Register */ +#define CAN0_MB19_DATA2 0xFFC00E68 /* CAN0 Mailbox Word 2 Register */ +#define CAN0_MB20_DATA2 0xFFC00E88 /* CAN0 Mailbox Word 2 Register */ +#define CAN0_MB21_DATA2 0xFFC00EA8 /* CAN0 Mailbox Word 2 Register */ +#define CAN0_MB22_DATA2 0xFFC00EC8 /* CAN0 Mailbox Word 2 Register */ +#define CAN0_MB23_DATA2 0xFFC00EE8 /* CAN0 Mailbox Word 2 Register */ +#define CAN0_MB24_DATA2 0xFFC00F08 /* CAN0 Mailbox Word 2 Register */ +#define CAN0_MB25_DATA2 0xFFC00F28 /* CAN0 Mailbox Word 2 Register */ +#define CAN0_MB26_DATA2 0xFFC00F48 /* CAN0 Mailbox Word 2 Register */ +#define CAN0_MB27_DATA2 0xFFC00F68 /* CAN0 Mailbox Word 2 Register */ +#define CAN0_MB28_DATA2 0xFFC00F88 /* CAN0 Mailbox Word 2 Register */ +#define CAN0_MB29_DATA2 0xFFC00FA8 /* CAN0 Mailbox Word 2 Register */ +#define CAN0_MB30_DATA2 0xFFC00FC8 /* CAN0 Mailbox Word 2 Register */ +#define CAN0_MB31_DATA2 0xFFC00FE8 /* CAN0 Mailbox Word 2 Register */ +#define CAN0_MB00_DATA3 0xFFC00C0C /* CAN0 Mailbox Word 3 Register */ +#define CAN0_MB01_DATA3 0xFFC00C2C /* CAN0 Mailbox Word 3 Register */ +#define CAN0_MB02_DATA3 0xFFC00C4C /* CAN0 Mailbox Word 3 Register */ +#define CAN0_MB03_DATA3 0xFFC00C6C /* CAN0 Mailbox Word 3 Register */ +#define CAN0_MB04_DATA3 0xFFC00C8C /* CAN0 Mailbox Word 3 Register */ +#define CAN0_MB05_DATA3 0xFFC00CAC /* CAN0 Mailbox Word 3 Register */ +#define CAN0_MB06_DATA3 0xFFC00CCC /* CAN0 Mailbox Word 3 Register */ +#define CAN0_MB07_DATA3 0xFFC00CEC /* CAN0 Mailbox Word 3 Register */ +#define CAN0_MB08_DATA3 0xFFC00D0C /* CAN0 Mailbox Word 3 Register */ +#define CAN0_MB09_DATA3 0xFFC00D2C /* CAN0 Mailbox Word 3 Register */ +#define CAN0_MB10_DATA3 0xFFC00D4C /* CAN0 Mailbox Word 3 Register */ +#define CAN0_MB11_DATA3 0xFFC00D6C /* CAN0 Mailbox Word 3 Register */ +#define CAN0_MB12_DATA3 0xFFC00D8C /* CAN0 Mailbox Word 3 Register */ +#define CAN0_MB13_DATA3 0xFFC00DAC /* CAN0 Mailbox Word 3 Register */ +#define CAN0_MB14_DATA3 0xFFC00DCC /* CAN0 Mailbox Word 3 Register */ +#define CAN0_MB15_DATA3 0xFFC00DEC /* CAN0 Mailbox Word 3 Register */ +#define CAN0_MB16_DATA3 0xFFC00E0C /* CAN0 Mailbox Word 3 Register */ +#define CAN0_MB17_DATA3 0xFFC00E2C /* CAN0 Mailbox Word 3 Register */ +#define CAN0_MB18_DATA3 0xFFC00E4C /* CAN0 Mailbox Word 3 Register */ +#define CAN0_MB19_DATA3 0xFFC00E6C /* CAN0 Mailbox Word 3 Register */ +#define CAN0_MB20_DATA3 0xFFC00E8C /* CAN0 Mailbox Word 3 Register */ +#define CAN0_MB21_DATA3 0xFFC00EAC /* CAN0 Mailbox Word 3 Register */ +#define CAN0_MB22_DATA3 0xFFC00ECC /* CAN0 Mailbox Word 3 Register */ +#define CAN0_MB23_DATA3 0xFFC00EEC /* CAN0 Mailbox Word 3 Register */ +#define CAN0_MB24_DATA3 0xFFC00F0C /* CAN0 Mailbox Word 3 Register */ +#define CAN0_MB25_DATA3 0xFFC00F2C /* CAN0 Mailbox Word 3 Register */ +#define CAN0_MB26_DATA3 0xFFC00F4C /* CAN0 Mailbox Word 3 Register */ +#define CAN0_MB27_DATA3 0xFFC00F6C /* CAN0 Mailbox Word 3 Register */ +#define CAN0_MB28_DATA3 0xFFC00F8C /* CAN0 Mailbox Word 3 Register */ +#define CAN0_MB29_DATA3 0xFFC00FAC /* CAN0 Mailbox Word 3 Register */ +#define CAN0_MB30_DATA3 0xFFC00FCC /* CAN0 Mailbox Word 3 Register */ +#define CAN0_MB31_DATA3 0xFFC00FEC /* CAN0 Mailbox Word 3 Register */ +#define CAN0_MB00_LENGTH 0xFFC00C10 /* CAN0 Mailbox Word 4 Register */ +#define CAN0_MB01_LENGTH 0xFFC00C30 /* CAN0 Mailbox Word 4 Register */ +#define CAN0_MB02_LENGTH 0xFFC00C50 /* CAN0 Mailbox Word 4 Register */ +#define CAN0_MB03_LENGTH 0xFFC00C70 /* CAN0 Mailbox Word 4 Register */ +#define CAN0_MB04_LENGTH 0xFFC00C90 /* CAN0 Mailbox Word 4 Register */ +#define CAN0_MB05_LENGTH 0xFFC00CB0 /* CAN0 Mailbox Word 4 Register */ +#define CAN0_MB06_LENGTH 0xFFC00CD0 /* CAN0 Mailbox Word 4 Register */ +#define CAN0_MB07_LENGTH 0xFFC00CF0 /* CAN0 Mailbox Word 4 Register */ +#define CAN0_MB08_LENGTH 0xFFC00D10 /* CAN0 Mailbox Word 4 Register */ +#define CAN0_MB09_LENGTH 0xFFC00D30 /* CAN0 Mailbox Word 4 Register */ +#define CAN0_MB10_LENGTH 0xFFC00D50 /* CAN0 Mailbox Word 4 Register */ +#define CAN0_MB11_LENGTH 0xFFC00D70 /* CAN0 Mailbox Word 4 Register */ +#define CAN0_MB12_LENGTH 0xFFC00D90 /* CAN0 Mailbox Word 4 Register */ +#define CAN0_MB13_LENGTH 0xFFC00DB0 /* CAN0 Mailbox Word 4 Register */ +#define CAN0_MB14_LENGTH 0xFFC00DD0 /* CAN0 Mailbox Word 4 Register */ +#define CAN0_MB15_LENGTH 0xFFC00DF0 /* CAN0 Mailbox Word 4 Register */ +#define CAN0_MB16_LENGTH 0xFFC00E10 /* CAN0 Mailbox Word 4 Register */ +#define CAN0_MB17_LENGTH 0xFFC00E30 /* CAN0 Mailbox Word 4 Register */ +#define CAN0_MB18_LENGTH 0xFFC00E50 /* CAN0 Mailbox Word 4 Register */ +#define CAN0_MB19_LENGTH 0xFFC00E70 /* CAN0 Mailbox Word 4 Register */ +#define CAN0_MB20_LENGTH 0xFFC00E90 /* CAN0 Mailbox Word 4 Register */ +#define CAN0_MB21_LENGTH 0xFFC00EB0 /* CAN0 Mailbox Word 4 Register */ +#define CAN0_MB22_LENGTH 0xFFC00ED0 /* CAN0 Mailbox Word 4 Register */ +#define CAN0_MB23_LENGTH 0xFFC00EF0 /* CAN0 Mailbox Word 4 Register */ +#define CAN0_MB24_LENGTH 0xFFC00F10 /* CAN0 Mailbox Word 4 Register */ +#define CAN0_MB25_LENGTH 0xFFC00F30 /* CAN0 Mailbox Word 4 Register */ +#define CAN0_MB26_LENGTH 0xFFC00F50 /* CAN0 Mailbox Word 4 Register */ +#define CAN0_MB27_LENGTH 0xFFC00F70 /* CAN0 Mailbox Word 4 Register */ +#define CAN0_MB28_LENGTH 0xFFC00F90 /* CAN0 Mailbox Word 4 Register */ +#define CAN0_MB29_LENGTH 0xFFC00FB0 /* CAN0 Mailbox Word 4 Register */ +#define CAN0_MB30_LENGTH 0xFFC00FD0 /* CAN0 Mailbox Word 4 Register */ +#define CAN0_MB31_LENGTH 0xFFC00FF0 /* CAN0 Mailbox Word 4 Register */ +#define CAN0_MB00_TIMESTAMP 0xFFC00C14 /* CAN0 Mailbox Word 5 Register */ +#define CAN0_MB01_TIMESTAMP 0xFFC00C34 /* CAN0 Mailbox Word 5 Register */ +#define CAN0_MB02_TIMESTAMP 0xFFC00C54 /* CAN0 Mailbox Word 5 Register */ +#define CAN0_MB03_TIMESTAMP 0xFFC00C74 /* CAN0 Mailbox Word 5 Register */ +#define CAN0_MB04_TIMESTAMP 0xFFC00C94 /* CAN0 Mailbox Word 5 Register */ +#define CAN0_MB05_TIMESTAMP 0xFFC00CB4 /* CAN0 Mailbox Word 5 Register */ +#define CAN0_MB06_TIMESTAMP 0xFFC00CD4 /* CAN0 Mailbox Word 5 Register */ +#define CAN0_MB07_TIMESTAMP 0xFFC00CF4 /* CAN0 Mailbox Word 5 Register */ +#define CAN0_MB08_TIMESTAMP 0xFFC00D14 /* CAN0 Mailbox Word 5 Register */ +#define CAN0_MB09_TIMESTAMP 0xFFC00D34 /* CAN0 Mailbox Word 5 Register */ +#define CAN0_MB10_TIMESTAMP 0xFFC00D54 /* CAN0 Mailbox Word 5 Register */ +#define CAN0_MB11_TIMESTAMP 0xFFC00D74 /* CAN0 Mailbox Word 5 Register */ +#define CAN0_MB12_TIMESTAMP 0xFFC00D94 /* CAN0 Mailbox Word 5 Register */ +#define CAN0_MB13_TIMESTAMP 0xFFC00DB4 /* CAN0 Mailbox Word 5 Register */ +#define CAN0_MB14_TIMESTAMP 0xFFC00DD4 /* CAN0 Mailbox Word 5 Register */ +#define CAN0_MB15_TIMESTAMP 0xFFC00DF4 /* CAN0 Mailbox Word 5 Register */ +#define CAN0_MB16_TIMESTAMP 0xFFC00E14 /* CAN0 Mailbox Word 5 Register */ +#define CAN0_MB17_TIMESTAMP 0xFFC00E34 /* CAN0 Mailbox Word 5 Register */ +#define CAN0_MB18_TIMESTAMP 0xFFC00E54 /* CAN0 Mailbox Word 5 Register */ +#define CAN0_MB19_TIMESTAMP 0xFFC00E74 /* CAN0 Mailbox Word 5 Register */ +#define CAN0_MB20_TIMESTAMP 0xFFC00E94 /* CAN0 Mailbox Word 5 Register */ +#define CAN0_MB21_TIMESTAMP 0xFFC00EB4 /* CAN0 Mailbox Word 5 Register */ +#define CAN0_MB22_TIMESTAMP 0xFFC00ED4 /* CAN0 Mailbox Word 5 Register */ +#define CAN0_MB23_TIMESTAMP 0xFFC00EF4 /* CAN0 Mailbox Word 5 Register */ +#define CAN0_MB24_TIMESTAMP 0xFFC00F14 /* CAN0 Mailbox Word 5 Register */ +#define CAN0_MB25_TIMESTAMP 0xFFC00F34 /* CAN0 Mailbox Word 5 Register */ +#define CAN0_MB26_TIMESTAMP 0xFFC00F54 /* CAN0 Mailbox Word 5 Register */ +#define CAN0_MB27_TIMESTAMP 0xFFC00F74 /* CAN0 Mailbox Word 5 Register */ +#define CAN0_MB28_TIMESTAMP 0xFFC00F94 /* CAN0 Mailbox Word 5 Register */ +#define CAN0_MB29_TIMESTAMP 0xFFC00FB4 /* CAN0 Mailbox Word 5 Register */ +#define CAN0_MB30_TIMESTAMP 0xFFC00FD4 /* CAN0 Mailbox Word 5 Register */ +#define CAN0_MB31_TIMESTAMP 0xFFC00FF4 /* CAN0 Mailbox Word 5 Register */ +#define CAN0_MB00_ID0 0xFFC00C18 /* CAN0 Mailbox Word 6 Register */ +#define CAN0_MB01_ID0 0xFFC00C38 /* CAN0 Mailbox Word 6 Register */ +#define CAN0_MB02_ID0 0xFFC00C58 /* CAN0 Mailbox Word 6 Register */ +#define CAN0_MB03_ID0 0xFFC00C78 /* CAN0 Mailbox Word 6 Register */ +#define CAN0_MB04_ID0 0xFFC00C98 /* CAN0 Mailbox Word 6 Register */ +#define CAN0_MB05_ID0 0xFFC00CB8 /* CAN0 Mailbox Word 6 Register */ +#define CAN0_MB06_ID0 0xFFC00CD8 /* CAN0 Mailbox Word 6 Register */ +#define CAN0_MB07_ID0 0xFFC00CF8 /* CAN0 Mailbox Word 6 Register */ +#define CAN0_MB08_ID0 0xFFC00D18 /* CAN0 Mailbox Word 6 Register */ +#define CAN0_MB09_ID0 0xFFC00D38 /* CAN0 Mailbox Word 6 Register */ +#define CAN0_MB10_ID0 0xFFC00D58 /* CAN0 Mailbox Word 6 Register */ +#define CAN0_MB11_ID0 0xFFC00D78 /* CAN0 Mailbox Word 6 Register */ +#define CAN0_MB12_ID0 0xFFC00D98 /* CAN0 Mailbox Word 6 Register */ +#define CAN0_MB13_ID0 0xFFC00DB8 /* CAN0 Mailbox Word 6 Register */ +#define CAN0_MB14_ID0 0xFFC00DD8 /* CAN0 Mailbox Word 6 Register */ +#define CAN0_MB15_ID0 0xFFC00DF8 /* CAN0 Mailbox Word 6 Register */ +#define CAN0_MB16_ID0 0xFFC00E18 /* CAN0 Mailbox Word 6 Register */ +#define CAN0_MB17_ID0 0xFFC00E38 /* CAN0 Mailbox Word 6 Register */ +#define CAN0_MB18_ID0 0xFFC00E58 /* CAN0 Mailbox Word 6 Register */ +#define CAN0_MB19_ID0 0xFFC00E78 /* CAN0 Mailbox Word 6 Register */ +#define CAN0_MB20_ID0 0xFFC00E98 /* CAN0 Mailbox Word 6 Register */ +#define CAN0_MB21_ID0 0xFFC00EB8 /* CAN0 Mailbox Word 6 Register */ +#define CAN0_MB22_ID0 0xFFC00ED8 /* CAN0 Mailbox Word 6 Register */ +#define CAN0_MB23_ID0 0xFFC00EF8 /* CAN0 Mailbox Word 6 Register */ +#define CAN0_MB24_ID0 0xFFC00F18 /* CAN0 Mailbox Word 6 Register */ +#define CAN0_MB25_ID0 0xFFC00F38 /* CAN0 Mailbox Word 6 Register */ +#define CAN0_MB26_ID0 0xFFC00F58 /* CAN0 Mailbox Word 6 Register */ +#define CAN0_MB27_ID0 0xFFC00F78 /* CAN0 Mailbox Word 6 Register */ +#define CAN0_MB28_ID0 0xFFC00F98 /* CAN0 Mailbox Word 6 Register */ +#define CAN0_MB29_ID0 0xFFC00FB8 /* CAN0 Mailbox Word 6 Register */ +#define CAN0_MB30_ID0 0xFFC00FD8 /* CAN0 Mailbox Word 6 Register */ +#define CAN0_MB31_ID0 0xFFC00FF8 /* CAN0 Mailbox Word 6 Register */ +#define CAN0_MB00_ID1 0xFFC00C1C /* CAN0 Mailbox Word 7 Register */ +#define CAN0_MB01_ID1 0xFFC00C3C /* CAN0 Mailbox Word 7 Register */ +#define CAN0_MB02_ID1 0xFFC00C5C /* CAN0 Mailbox Word 7 Register */ +#define CAN0_MB03_ID1 0xFFC00C7C /* CAN0 Mailbox Word 7 Register */ +#define CAN0_MB04_ID1 0xFFC00C9C /* CAN0 Mailbox Word 7 Register */ +#define CAN0_MB05_ID1 0xFFC00CBC /* CAN0 Mailbox Word 7 Register */ +#define CAN0_MB06_ID1 0xFFC00CDC /* CAN0 Mailbox Word 7 Register */ +#define CAN0_MB07_ID1 0xFFC00CFC /* CAN0 Mailbox Word 7 Register */ +#define CAN0_MB08_ID1 0xFFC00D1C /* CAN0 Mailbox Word 7 Register */ +#define CAN0_MB09_ID1 0xFFC00D3C /* CAN0 Mailbox Word 7 Register */ +#define CAN0_MB10_ID1 0xFFC00D5C /* CAN0 Mailbox Word 7 Register */ +#define CAN0_MB11_ID1 0xFFC00D7C /* CAN0 Mailbox Word 7 Register */ +#define CAN0_MB12_ID1 0xFFC00D9C /* CAN0 Mailbox Word 7 Register */ +#define CAN0_MB13_ID1 0xFFC00DBC /* CAN0 Mailbox Word 7 Register */ +#define CAN0_MB14_ID1 0xFFC00DDC /* CAN0 Mailbox Word 7 Register */ +#define CAN0_MB15_ID1 0xFFC00DFC /* CAN0 Mailbox Word 7 Register */ +#define CAN0_MB16_ID1 0xFFC00E1C /* CAN0 Mailbox Word 7 Register */ +#define CAN0_MB17_ID1 0xFFC00E3C /* CAN0 Mailbox Word 7 Register */ +#define CAN0_MB18_ID1 0xFFC00E5C /* CAN0 Mailbox Word 7 Register */ +#define CAN0_MB19_ID1 0xFFC00E7C /* CAN0 Mailbox Word 7 Register */ +#define CAN0_MB20_ID1 0xFFC00E9C /* CAN0 Mailbox Word 7 Register */ +#define CAN0_MB21_ID1 0xFFC00EBC /* CAN0 Mailbox Word 7 Register */ +#define CAN0_MB22_ID1 0xFFC00EDC /* CAN0 Mailbox Word 7 Register */ +#define CAN0_MB23_ID1 0xFFC00EFC /* CAN0 Mailbox Word 7 Register */ +#define CAN0_MB24_ID1 0xFFC00F1C /* CAN0 Mailbox Word 7 Register */ +#define CAN0_MB25_ID1 0xFFC00F3C /* CAN0 Mailbox Word 7 Register */ +#define CAN0_MB26_ID1 0xFFC00F5C /* CAN0 Mailbox Word 7 Register */ +#define CAN0_MB27_ID1 0xFFC00F7C /* CAN0 Mailbox Word 7 Register */ +#define CAN0_MB28_ID1 0xFFC00F9C /* CAN0 Mailbox Word 7 Register */ +#define CAN0_MB29_ID1 0xFFC00FBC /* CAN0 Mailbox Word 7 Register */ +#define CAN0_MB30_ID1 0xFFC00FDC /* CAN0 Mailbox Word 7 Register */ +#define CAN0_MB31_ID1 0xFFC00FFC /* CAN0 Mailbox Word 7 Register */ + +/* ========================= + LINK PORT Registers + ========================= */ +#define LP0_CTL 0xFFC01000 /* LP0 Control Register */ +#define LP0_STAT 0xFFC01004 /* LP0 Status Register */ +#define LP0_DIV 0xFFC01008 /* LP0 Clock Divider Value */ +#define LP0_CNT 0xFFC0100C /* LP0 Current Count Value of Clock Divider */ +#define LP0_TX 0xFFC01010 /* LP0 Transmit Buffer */ +#define LP0_RX 0xFFC01014 /* LP0 Receive Buffer */ +#define LP0_TXIN_SHDW 0xFFC01018 /* LP0 Shadow Input Transmit Buffer */ +#define LP0_TXOUT_SHDW 0xFFC0101C /* LP0 Shadow Output Transmit Buffer */ +#define LP1_CTL 0xFFC01100 /* LP1 Control Register */ +#define LP1_STAT 0xFFC01104 /* LP1 Status Register */ +#define LP1_DIV 0xFFC01108 /* LP1 Clock Divider Value */ +#define LP1_CNT 0xFFC0110C /* LP1 Current Count Value of Clock Divider */ +#define LP1_TX 0xFFC01110 /* LP1 Transmit Buffer */ +#define LP1_RX 0xFFC01114 /* LP1 Receive Buffer */ +#define LP1_TXIN_SHDW 0xFFC01118 /* LP1 Shadow Input Transmit Buffer */ +#define LP1_TXOUT_SHDW 0xFFC0111C /* LP1 Shadow Output Transmit Buffer */ +#define LP2_CTL 0xFFC01200 /* LP2 Control Register */ +#define LP2_STAT 0xFFC01204 /* LP2 Status Register */ +#define LP2_DIV 0xFFC01208 /* LP2 Clock Divider Value */ +#define LP2_CNT 0xFFC0120C /* LP2 Current Count Value of Clock Divider */ +#define LP2_TX 0xFFC01210 /* LP2 Transmit Buffer */ +#define LP2_RX 0xFFC01214 /* LP2 Receive Buffer */ +#define LP2_TXIN_SHDW 0xFFC01218 /* LP2 Shadow Input Transmit Buffer */ +#define LP2_TXOUT_SHDW 0xFFC0121C /* LP2 Shadow Output Transmit Buffer */ +#define LP3_CTL 0xFFC01300 /* LP3 Control Register */ +#define LP3_STAT 0xFFC01304 /* LP3 Status Register */ +#define LP3_DIV 0xFFC01308 /* LP3 Clock Divider Value */ +#define LP3_CNT 0xFFC0130C /* LP3 Current Count Value of Clock Divider */ +#define LP3_TX 0xFFC01310 /* LP3 Transmit Buffer */ +#define LP3_RX 0xFFC01314 /* LP3 Receive Buffer */ +#define LP3_TXIN_SHDW 0xFFC01318 /* LP3 Shadow Input Transmit Buffer */ +#define LP3_TXOUT_SHDW 0xFFC0131C /* LP3 Shadow Output Transmit Buffer */ + +/* ========================= + TIMER Registers + ========================= */ +#define TIMER_REVID 0xFFC01400 /* GPTIMER Timer IP Version ID */ +#define TIMER_RUN 0xFFC01404 /* GPTIMER Timer Run Register */ +#define TIMER_RUN_SET 0xFFC01408 /* GPTIMER Run Register Alias to Set */ +#define TIMER_RUN_CLR 0xFFC0140C /* GPTIMER Run Register Alias to Clear */ +#define TIMER_STOP_CFG 0xFFC01410 /* GPTIMER Stop Config Register */ +#define TIMER_STOP_CFG_SET 0xFFC01414 /* GPTIMER Stop Config Alias to Set */ +#define TIMER_STOP_CFG_CLR 0xFFC01418 /* GPTIMER Stop Config Alias to Clear */ +#define TIMER_DATA_IMSK 0xFFC0141C /* GPTIMER Data Interrupt Mask register */ +#define TIMER_STAT_IMSK 0xFFC01420 /* GPTIMER Status Interrupt Mask register */ +#define TIMER_TRG_MSK 0xFFC01424 /* GPTIMER Output Trigger Mask register */ +#define TIMER_TRG_IE 0xFFC01428 /* GPTIMER Slave Trigger Enable register */ +#define TIMER_DATA_ILAT 0xFFC0142C /* GPTIMER Data Interrupt Register */ +#define TIMER_STAT_ILAT 0xFFC01430 /* GPTIMER Status (Error) Interrupt Register */ +#define TIMER_ERR_TYPE 0xFFC01434 /* GPTIMER Register Indicating Type of Error */ +#define TIMER_BCAST_PER 0xFFC01438 /* GPTIMER Broadcast Period */ +#define TIMER_BCAST_WID 0xFFC0143C /* GPTIMER Broadcast Width */ +#define TIMER_BCAST_DLY 0xFFC01440 /* GPTIMER Broadcast Delay */ + +/* ========================= + TIMER0~7 + ========================= */ +#define TIMER0_CONFIG 0xFFC01460 /* TIMER0 Per Timer Config Register */ +#define TIMER0_COUNTER 0xFFC01464 /* TIMER0 Per Timer Counter Register */ +#define TIMER0_PERIOD 0xFFC01468 /* TIMER0 Per Timer Period Register */ +#define TIMER0_WIDTH 0xFFC0146C /* TIMER0 Per Timer Width Register */ +#define TIMER0_DELAY 0xFFC01470 /* TIMER0 Per Timer Delay Register */ + +#define TIMER1_CONFIG 0xFFC01480 /* TIMER1 Per Timer Config Register */ +#define TIMER1_COUNTER 0xFFC01484 /* TIMER1 Per Timer Counter Register */ +#define TIMER1_PERIOD 0xFFC01488 /* TIMER1 Per Timer Period Register */ +#define TIMER1_WIDTH 0xFFC0148C /* TIMER1 Per Timer Width Register */ +#define TIMER1_DELAY 0xFFC01490 /* TIMER1 Per Timer Delay Register */ + +#define TIMER2_CONFIG 0xFFC014A0 /* TIMER2 Per Timer Config Register */ +#define TIMER2_COUNTER 0xFFC014A4 /* TIMER2 Per Timer Counter Register */ +#define TIMER2_PERIOD 0xFFC014A8 /* TIMER2 Per Timer Period Register */ +#define TIMER2_WIDTH 0xFFC014AC /* TIMER2 Per Timer Width Register */ +#define TIMER2_DELAY 0xFFC014B0 /* TIMER2 Per Timer Delay Register */ + +#define TIMER3_CONFIG 0xFFC014C0 /* TIMER3 Per Timer Config Register */ +#define TIMER3_COUNTER 0xFFC014C4 /* TIMER3 Per Timer Counter Register */ +#define TIMER3_PERIOD 0xFFC014C8 /* TIMER3 Per Timer Period Register */ +#define TIMER3_WIDTH 0xFFC014CC /* TIMER3 Per Timer Width Register */ +#define TIMER3_DELAY 0xFFC014D0 /* TIMER3 Per Timer Delay Register */ + +#define TIMER4_CONFIG 0xFFC014E0 /* TIMER4 Per Timer Config Register */ +#define TIMER4_COUNTER 0xFFC014E4 /* TIMER4 Per Timer Counter Register */ +#define TIMER4_PERIOD 0xFFC014E8 /* TIMER4 Per Timer Period Register */ +#define TIMER4_WIDTH 0xFFC014EC /* TIMER4 Per Timer Width Register */ +#define TIMER4_DELAY 0xFFC014F0 /* TIMER4 Per Timer Delay Register */ + +#define TIMER5_CONFIG 0xFFC01500 /* TIMER5 Per Timer Config Register */ +#define TIMER5_COUNTER 0xFFC01504 /* TIMER5 Per Timer Counter Register */ +#define TIMER5_PERIOD 0xFFC01508 /* TIMER5 Per Timer Period Register */ +#define TIMER5_WIDTH 0xFFC0150C /* TIMER5 Per Timer Width Register */ +#define TIMER5_DELAY 0xFFC01510 /* TIMER5 Per Timer Delay Register */ + +#define TIMER6_CONFIG 0xFFC01520 /* TIMER6 Per Timer Config Register */ +#define TIMER6_COUNTER 0xFFC01524 /* TIMER6 Per Timer Counter Register */ +#define TIMER6_PERIOD 0xFFC01528 /* TIMER6 Per Timer Period Register */ +#define TIMER6_WIDTH 0xFFC0152C /* TIMER6 Per Timer Width Register */ +#define TIMER6_DELAY 0xFFC01530 /* TIMER6 Per Timer Delay Register */ + +#define TIMER7_CONFIG 0xFFC01540 /* TIMER7 Per Timer Config Register */ +#define TIMER7_COUNTER 0xFFC01544 /* TIMER7 Per Timer Counter Register */ +#define TIMER7_PERIOD 0xFFC01548 /* TIMER7 Per Timer Period Register */ +#define TIMER7_WIDTH 0xFFC0154C /* TIMER7 Per Timer Width Register */ +#define TIMER7_DELAY 0xFFC01550 /* TIMER7 Per Timer Delay Register */ + +/* ========================= + CRC Registers + ========================= */ + +/* ========================= + CRC0 + ========================= */ +#define REG_CRC0_CTL 0xFFC01C00 /* CRC0 Control Register */ +#define REG_CRC0_DCNT 0xFFC01C04 /* CRC0 Data Word Count Register */ +#define REG_CRC0_DCNTRLD 0xFFC01C08 /* CRC0 Data Word Count Reload Register */ +#define REG_CRC0_COMP 0xFFC01C14 /* CRC0 DATA Compare Register */ +#define REG_CRC0_FILLVAL 0xFFC01C18 /* CRC0 Fill Value Register */ +#define REG_CRC0_DFIFO 0xFFC01C1C /* CRC0 DATA FIFO Register */ +#define REG_CRC0_INEN 0xFFC01C20 /* CRC0 Interrupt Enable Register */ +#define REG_CRC0_INEN_SET 0xFFC01C24 /* CRC0 Interrupt Enable Set Register */ +#define REG_CRC0_INEN_CLR 0xFFC01C28 /* CRC0 Interrupt Enable Clear Register */ +#define REG_CRC0_POLY 0xFFC01C2C /* CRC0 Polynomial Register */ +#define REG_CRC0_STAT 0xFFC01C40 /* CRC0 Status Register */ +#define REG_CRC0_DCNTCAP 0xFFC01C44 /* CRC0 DATA Count Capture Register */ +#define REG_CRC0_RESULT_FIN 0xFFC01C4C /* CRC0 Final CRC Result Register */ +#define REG_CRC0_RESULT_CUR 0xFFC01C50 /* CRC0 Current CRC Result Register */ +#define REG_CRC0_REVID 0xFFC01C60 /* CRC0 Revision ID Register */ + +/* ========================= + CRC1 + ========================= */ +#define REG_CRC1_CTL 0xFFC01D00 /* CRC1 Control Register */ +#define REG_CRC1_DCNT 0xFFC01D04 /* CRC1 Data Word Count Register */ +#define REG_CRC1_DCNTRLD 0xFFC01D08 /* CRC1 Data Word Count Reload Register */ +#define REG_CRC1_COMP 0xFFC01D14 /* CRC1 DATA Compare Register */ +#define REG_CRC1_FILLVAL 0xFFC01D18 /* CRC1 Fill Value Register */ +#define REG_CRC1_DFIFO 0xFFC01D1C /* CRC1 DATA FIFO Register */ +#define REG_CRC1_INEN 0xFFC01D20 /* CRC1 Interrupt Enable Register */ +#define REG_CRC1_INEN_SET 0xFFC01D24 /* CRC1 Interrupt Enable Set Register */ +#define REG_CRC1_INEN_CLR 0xFFC01D28 /* CRC1 Interrupt Enable Clear Register */ +#define REG_CRC1_POLY 0xFFC01D2C /* CRC1 Polynomial Register */ +#define REG_CRC1_STAT 0xFFC01D40 /* CRC1 Status Register */ +#define REG_CRC1_DCNTCAP 0xFFC01D44 /* CRC1 DATA Count Capture Register */ +#define REG_CRC1_RESULT_FIN 0xFFC01D4C /* CRC1 Final CRC Result Register */ +#define REG_CRC1_RESULT_CUR 0xFFC01D50 /* CRC1 Current CRC Result Register */ +#define REG_CRC1_REVID 0xFFC01D60 /* CRC1 Revision ID Register */ + +/* ========================= + TWI Registers + ========================= */ + +/* ========================= + TWI0 + ========================= */ +#define TWI0_CLKDIV 0xFFC01E00 /* TWI0 SCL Clock Divider */ +#define TWI0_CONTROL 0xFFC01E04 /* TWI0 Control Register */ +#define TWI0_SLAVE_CTL 0xFFC01E08 /* TWI0 Slave Mode Control Register */ +#define TWI0_SLAVE_STAT 0xFFC01E0C /* TWI0 Slave Mode Status Register */ +#define TWI0_SLAVE_ADDR 0xFFC01E10 /* TWI0 Slave Mode Address Register */ +#define TWI0_MASTER_CTL 0xFFC01E14 /* TWI0 Master Mode Control Registers */ +#define TWI0_MASTER_STAT 0xFFC01E18 /* TWI0 Master Mode Status Register */ +#define TWI0_MASTER_ADDR 0xFFC01E1C /* TWI0 Master Mode Address Register */ +#define TWI0_INT_STAT 0xFFC01E20 /* TWI0 Interrupt Status Register */ +#define TWI0_INT_MASK 0xFFC01E24 /* TWI0 Interrupt Mask Register */ +#define TWI0_FIFO_CTL 0xFFC01E28 /* TWI0 FIFO Control Register */ +#define TWI0_FIFO_STAT 0xFFC01E2C /* TWI0 FIFO Status Register */ +#define TWI0_XMT_DATA8 0xFFC01E80 /* TWI0 FIFO Transmit Data Single-Byte Register */ +#define TWI0_XMT_DATA16 0xFFC01E84 /* TWI0 FIFO Transmit Data Double-Byte Register */ +#define TWI0_RCV_DATA8 0xFFC01E88 /* TWI0 FIFO Transmit Data Single-Byte Register */ +#define TWI0_RCV_DATA16 0xFFC01E8C /* TWI0 FIFO Transmit Data Double-Byte Register */ + +/* ========================= + TWI1 + ========================= */ +#define TWI1_CLKDIV 0xFFC01F00 /* TWI1 SCL Clock Divider */ +#define TWI1_CONTROL 0xFFC01F04 /* TWI1 Control Register */ +#define TWI1_SLAVE_CTL 0xFFC01F08 /* TWI1 Slave Mode Control Register */ +#define TWI1_SLAVE_STAT 0xFFC01F0C /* TWI1 Slave Mode Status Register */ +#define TWI1_SLAVE_ADDR 0xFFC01F10 /* TWI1 Slave Mode Address Register */ +#define TWI1_MASTER_CTL 0xFFC01F14 /* TWI1 Master Mode Control Registers */ +#define TWI1_MASTER_STAT 0xFFC01F18 /* TWI1 Master Mode Status Register */ +#define TWI1_MASTER_ADDR 0xFFC01F1C /* TWI1 Master Mode Address Register */ +#define TWI1_INT_STAT 0xFFC01F20 /* TWI1 Interrupt Status Register */ +#define TWI1_INT_MASK 0xFFC01F24 /* TWI1 Interrupt Mask Register */ +#define TWI1_FIFO_CTL 0xFFC01F28 /* TWI1 FIFO Control Register */ +#define TWI1_FIFO_STAT 0xFFC01F2C /* TWI1 FIFO Status Register */ +#define TWI1_XMT_DATA8 0xFFC01F80 /* TWI1 FIFO Transmit Data Single-Byte Register */ +#define TWI1_XMT_DATA16 0xFFC01F84 /* TWI1 FIFO Transmit Data Double-Byte Register */ +#define TWI1_RCV_DATA8 0xFFC01F88 /* TWI1 FIFO Transmit Data Single-Byte Register */ +#define TWI1_RCV_DATA16 0xFFC01F8C /* TWI1 FIFO Transmit Data Double-Byte Register */ + + +/* ========================= + UART Registers + ========================= */ + +/* ========================= + UART0 + ========================= */ +#define UART0_REVID 0xFFC02000 /* UART0 Revision ID Register */ +#define UART0_CTL 0xFFC02004 /* UART0 Control Register */ +#define UART0_STAT 0xFFC02008 /* UART0 Status Register */ +#define UART0_SCR 0xFFC0200C /* UART0 Scratch Register */ +#define UART0_CLK 0xFFC02010 /* UART0 Clock Rate Register */ +#define UART0_IER 0xFFC02014 /* UART0 Interrupt Mask Register */ +#define UART0_IER_SET 0xFFC02018 /* UART0 Interrupt Mask Set Register */ +#define UART0_IER_CLR 0xFFC0201C /* UART0 Interrupt Mask Clear Register */ +#define UART0_RBR 0xFFC02020 /* UART0 Receive Buffer Register */ +#define UART0_THR 0xFFC02024 /* UART0 Transmit Hold Register */ +#define UART0_TAIP 0xFFC02028 /* UART0 Transmit Address/Insert Pulse Register */ +#define UART0_TSR 0xFFC0202C /* UART0 Transmit Shift Register */ +#define UART0_RSR 0xFFC02030 /* UART0 Receive Shift Register */ +#define UART0_TXDIV 0xFFC02034 /* UART0 Transmit Clock Devider Register */ +#define UART0_RXDIV 0xFFC02038 /* UART0 Receive Clock Devider Register */ + +/* ========================= + UART1 + ========================= */ +#define UART1_REVID 0xFFC02400 /* UART1 Revision ID Register */ +#define UART1_CTL 0xFFC02404 /* UART1 Control Register */ +#define UART1_STAT 0xFFC02408 /* UART1 Status Register */ +#define UART1_SCR 0xFFC0240C /* UART1 Scratch Register */ +#define UART1_CLK 0xFFC02410 /* UART1 Clock Rate Register */ +#define UART1_IER 0xFFC02414 /* UART1 Interrupt Mask Register */ +#define UART1_IER_SET 0xFFC02418 /* UART1 Interrupt Mask Set Register */ +#define UART1_IER_CLR 0xFFC0241C /* UART1 Interrupt Mask Clear Register */ +#define UART1_RBR 0xFFC02420 /* UART1 Receive Buffer Register */ +#define UART1_THR 0xFFC02424 /* UART1 Transmit Hold Register */ +#define UART1_TAIP 0xFFC02428 /* UART1 Transmit Address/Insert Pulse Register */ +#define UART1_TSR 0xFFC0242C /* UART1 Transmit Shift Register */ +#define UART1_RSR 0xFFC02430 /* UART1 Receive Shift Register */ +#define UART1_TXDIV 0xFFC02434 /* UART1 Transmit Clock Devider Register */ +#define UART1_RXDIV 0xFFC02438 /* UART1 Receive Clock Devider Register */ + + +/* ========================= + PORT Registers + ========================= */ + +/* ========================= + PORTA + ========================= */ +#define PORTA_FER 0xFFC03000 /* PORTA Port x Function Enable Register */ +#define PORTA_FER_SET 0xFFC03004 /* PORTA Port x Function Enable Set Register */ +#define PORTA_FER_CLEAR 0xFFC03008 /* PORTA Port x Function Enable Clear Register */ +#define PORTA_DATA 0xFFC0300C /* PORTA Port x GPIO Data Register */ +#define PORTA_DATA_SET 0xFFC03010 /* PORTA Port x GPIO Data Set Register */ +#define PORTA_DATA_CLEAR 0xFFC03014 /* PORTA Port x GPIO Data Clear Register */ +#define PORTA_DIR 0xFFC03018 /* PORTA Port x GPIO Direction Register */ +#define PORTA_DIR_SET 0xFFC0301C /* PORTA Port x GPIO Direction Set Register */ +#define PORTA_DIR_CLEAR 0xFFC03020 /* PORTA Port x GPIO Direction Clear Register */ +#define PORTA_INEN 0xFFC03024 /* PORTA Port x GPIO Input Enable Register */ +#define PORTA_INEN_SET 0xFFC03028 /* PORTA Port x GPIO Input Enable Set Register */ +#define PORTA_INEN_CLEAR 0xFFC0302C /* PORTA Port x GPIO Input Enable Clear Register */ +#define PORTA_MUX 0xFFC03030 /* PORTA Port x Multiplexer Control Register */ +#define PORTA_DATA_TGL 0xFFC03034 /* PORTA Port x GPIO Input Enable Toggle Register */ +#define PORTA_POL 0xFFC03038 /* PORTA Port x GPIO Programming Inversion Register */ +#define PORTA_POL_SET 0xFFC0303C /* PORTA Port x GPIO Programming Inversion Set Register */ +#define PORTA_POL_CLEAR 0xFFC03040 /* PORTA Port x GPIO Programming Inversion Clear Register */ +#define PORTA_LOCK 0xFFC03044 /* PORTA Port x GPIO Lock Register */ +#define PORTA_REVID 0xFFC0307C /* PORTA Port x GPIO Revision ID */ + +/* ========================= + PORTB + ========================= */ +#define PORTB_FER 0xFFC03080 /* PORTB Port x Function Enable Register */ +#define PORTB_FER_SET 0xFFC03084 /* PORTB Port x Function Enable Set Register */ +#define PORTB_FER_CLEAR 0xFFC03088 /* PORTB Port x Function Enable Clear Register */ +#define PORTB_DATA 0xFFC0308C /* PORTB Port x GPIO Data Register */ +#define PORTB_DATA_SET 0xFFC03090 /* PORTB Port x GPIO Data Set Register */ +#define PORTB_DATA_CLEAR 0xFFC03094 /* PORTB Port x GPIO Data Clear Register */ +#define PORTB_DIR 0xFFC03098 /* PORTB Port x GPIO Direction Register */ +#define PORTB_DIR_SET 0xFFC0309C /* PORTB Port x GPIO Direction Set Register */ +#define PORTB_DIR_CLEAR 0xFFC030A0 /* PORTB Port x GPIO Direction Clear Register */ +#define PORTB_INEN 0xFFC030A4 /* PORTB Port x GPIO Input Enable Register */ +#define PORTB_INEN_SET 0xFFC030A8 /* PORTB Port x GPIO Input Enable Set Register */ +#define PORTB_INEN_CLEAR 0xFFC030AC /* PORTB Port x GPIO Input Enable Clear Register */ +#define PORTB_MUX 0xFFC030B0 /* PORTB Port x Multiplexer Control Register */ +#define PORTB_DATA_TGL 0xFFC030B4 /* PORTB Port x GPIO Input Enable Toggle Register */ +#define PORTB_POL 0xFFC030B8 /* PORTB Port x GPIO Programming Inversion Register */ +#define PORTB_POL_SET 0xFFC030BC /* PORTB Port x GPIO Programming Inversion Set Register */ +#define PORTB_POL_CLEAR 0xFFC030C0 /* PORTB Port x GPIO Programming Inversion Clear Register */ +#define PORTB_LOCK 0xFFC030C4 /* PORTB Port x GPIO Lock Register */ +#define PORTB_REVID 0xFFC030FC /* PORTB Port x GPIO Revision ID */ + +/* ========================= + PORTC + ========================= */ +#define PORTC_FER 0xFFC03100 /* PORTC Port x Function Enable Register */ +#define PORTC_FER_SET 0xFFC03104 /* PORTC Port x Function Enable Set Register */ +#define PORTC_FER_CLEAR 0xFFC03108 /* PORTC Port x Function Enable Clear Register */ +#define PORTC_DATA 0xFFC0310C /* PORTC Port x GPIO Data Register */ +#define PORTC_DATA_SET 0xFFC03110 /* PORTC Port x GPIO Data Set Register */ +#define PORTC_DATA_CLEAR 0xFFC03114 /* PORTC Port x GPIO Data Clear Register */ +#define PORTC_DIR 0xFFC03118 /* PORTC Port x GPIO Direction Register */ +#define PORTC_DIR_SET 0xFFC0311C /* PORTC Port x GPIO Direction Set Register */ +#define PORTC_DIR_CLEAR 0xFFC03120 /* PORTC Port x GPIO Direction Clear Register */ +#define PORTC_INEN 0xFFC03124 /* PORTC Port x GPIO Input Enable Register */ +#define PORTC_INEN_SET 0xFFC03128 /* PORTC Port x GPIO Input Enable Set Register */ +#define PORTC_INEN_CLEAR 0xFFC0312C /* PORTC Port x GPIO Input Enable Clear Register */ +#define PORTC_MUX 0xFFC03130 /* PORTC Port x Multiplexer Control Register */ +#define PORTC_DATA_TGL 0xFFC03134 /* PORTC Port x GPIO Input Enable Toggle Register */ +#define PORTC_POL 0xFFC03138 /* PORTC Port x GPIO Programming Inversion Register */ +#define PORTC_POL_SET 0xFFC0313C /* PORTC Port x GPIO Programming Inversion Set Register */ +#define PORTC_POL_CLEAR 0xFFC03140 /* PORTC Port x GPIO Programming Inversion Clear Register */ +#define PORTC_LOCK 0xFFC03144 /* PORTC Port x GPIO Lock Register */ +#define PORTC_REVID 0xFFC0317C /* PORTC Port x GPIO Revision ID */ + +/* ========================= + PORTD + ========================= */ +#define PORTD_FER 0xFFC03180 /* PORTD Port x Function Enable Register */ +#define PORTD_FER_SET 0xFFC03184 /* PORTD Port x Function Enable Set Register */ +#define PORTD_FER_CLEAR 0xFFC03188 /* PORTD Port x Function Enable Clear Register */ +#define PORTD_DATA 0xFFC0318C /* PORTD Port x GPIO Data Register */ +#define PORTD_DATA_SET 0xFFC03190 /* PORTD Port x GPIO Data Set Register */ +#define PORTD_DATA_CLEAR 0xFFC03194 /* PORTD Port x GPIO Data Clear Register */ +#define PORTD_DIR 0xFFC03198 /* PORTD Port x GPIO Direction Register */ +#define PORTD_DIR_SET 0xFFC0319C /* PORTD Port x GPIO Direction Set Register */ +#define PORTD_DIR_CLEAR 0xFFC031A0 /* PORTD Port x GPIO Direction Clear Register */ +#define PORTD_INEN 0xFFC031A4 /* PORTD Port x GPIO Input Enable Register */ +#define PORTD_INEN_SET 0xFFC031A8 /* PORTD Port x GPIO Input Enable Set Register */ +#define PORTD_INEN_CLEAR 0xFFC031AC /* PORTD Port x GPIO Input Enable Clear Register */ +#define PORTD_MUX 0xFFC031B0 /* PORTD Port x Multiplexer Control Register */ +#define PORTD_DATA_TGL 0xFFC031B4 /* PORTD Port x GPIO Input Enable Toggle Register */ +#define PORTD_POL 0xFFC031B8 /* PORTD Port x GPIO Programming Inversion Register */ +#define PORTD_POL_SET 0xFFC031BC /* PORTD Port x GPIO Programming Inversion Set Register */ +#define PORTD_POL_CLEAR 0xFFC031C0 /* PORTD Port x GPIO Programming Inversion Clear Register */ +#define PORTD_LOCK 0xFFC031C4 /* PORTD Port x GPIO Lock Register */ +#define PORTD_REVID 0xFFC031FC /* PORTD Port x GPIO Revision ID */ + +/* ========================= + PORTE + ========================= */ +#define PORTE_FER 0xFFC03200 /* PORTE Port x Function Enable Register */ +#define PORTE_FER_SET 0xFFC03204 /* PORTE Port x Function Enable Set Register */ +#define PORTE_FER_CLEAR 0xFFC03208 /* PORTE Port x Function Enable Clear Register */ +#define PORTE_DATA 0xFFC0320C /* PORTE Port x GPIO Data Register */ +#define PORTE_DATA_SET 0xFFC03210 /* PORTE Port x GPIO Data Set Register */ +#define PORTE_DATA_CLEAR 0xFFC03214 /* PORTE Port x GPIO Data Clear Register */ +#define PORTE_DIR 0xFFC03218 /* PORTE Port x GPIO Direction Register */ +#define PORTE_DIR_SET 0xFFC0321C /* PORTE Port x GPIO Direction Set Register */ +#define PORTE_DIR_CLEAR 0xFFC03220 /* PORTE Port x GPIO Direction Clear Register */ +#define PORTE_INEN 0xFFC03224 /* PORTE Port x GPIO Input Enable Register */ +#define PORTE_INEN_SET 0xFFC03228 /* PORTE Port x GPIO Input Enable Set Register */ +#define PORTE_INEN_CLEAR 0xFFC0322C /* PORTE Port x GPIO Input Enable Clear Register */ +#define PORTE_MUX 0xFFC03230 /* PORTE Port x Multiplexer Control Register */ +#define PORTE_DATA_TGL 0xFFC03234 /* PORTE Port x GPIO Input Enable Toggle Register */ +#define PORTE_POL 0xFFC03238 /* PORTE Port x GPIO Programming Inversion Register */ +#define PORTE_POL_SET 0xFFC0323C /* PORTE Port x GPIO Programming Inversion Set Register */ +#define PORTE_POL_CLEAR 0xFFC03240 /* PORTE Port x GPIO Programming Inversion Clear Register */ +#define PORTE_LOCK 0xFFC03244 /* PORTE Port x GPIO Lock Register */ +#define PORTE_REVID 0xFFC0327C /* PORTE Port x GPIO Revision ID */ + +/* ========================= + PORTF + ========================= */ +#define PORTF_FER 0xFFC03280 /* PORTF Port x Function Enable Register */ +#define PORTF_FER_SET 0xFFC03284 /* PORTF Port x Function Enable Set Register */ +#define PORTF_FER_CLEAR 0xFFC03288 /* PORTF Port x Function Enable Clear Register */ +#define PORTF_DATA 0xFFC0328C /* PORTF Port x GPIO Data Register */ +#define PORTF_DATA_SET 0xFFC03290 /* PORTF Port x GPIO Data Set Register */ +#define PORTF_DATA_CLEAR 0xFFC03294 /* PORTF Port x GPIO Data Clear Register */ +#define PORTF_DIR 0xFFC03298 /* PORTF Port x GPIO Direction Register */ +#define PORTF_DIR_SET 0xFFC0329C /* PORTF Port x GPIO Direction Set Register */ +#define PORTF_DIR_CLEAR 0xFFC032A0 /* PORTF Port x GPIO Direction Clear Register */ +#define PORTF_INEN 0xFFC032A4 /* PORTF Port x GPIO Input Enable Register */ +#define PORTF_INEN_SET 0xFFC032A8 /* PORTF Port x GPIO Input Enable Set Register */ +#define PORTF_INEN_CLEAR 0xFFC032AC /* PORTF Port x GPIO Input Enable Clear Register */ +#define PORTF_MUX 0xFFC032B0 /* PORTF Port x Multiplexer Control Register */ +#define PORTF_DATA_TGL 0xFFC032B4 /* PORTF Port x GPIO Input Enable Toggle Register */ +#define PORTF_POL 0xFFC032B8 /* PORTF Port x GPIO Programming Inversion Register */ +#define PORTF_POL_SET 0xFFC032BC /* PORTF Port x GPIO Programming Inversion Set Register */ +#define PORTF_POL_CLEAR 0xFFC032C0 /* PORTF Port x GPIO Programming Inversion Clear Register */ +#define PORTF_LOCK 0xFFC032C4 /* PORTF Port x GPIO Lock Register */ +#define PORTF_REVID 0xFFC032FC /* PORTF Port x GPIO Revision ID */ + +/* ========================= + PORTG + ========================= */ +#define PORTG_FER 0xFFC03300 /* PORTG Port x Function Enable Register */ +#define PORTG_FER_SET 0xFFC03304 /* PORTG Port x Function Enable Set Register */ +#define PORTG_FER_CLEAR 0xFFC03308 /* PORTG Port x Function Enable Clear Register */ +#define PORTG_DATA 0xFFC0330C /* PORTG Port x GPIO Data Register */ +#define PORTG_DATA_SET 0xFFC03310 /* PORTG Port x GPIO Data Set Register */ +#define PORTG_DATA_CLEAR 0xFFC03314 /* PORTG Port x GPIO Data Clear Register */ +#define PORTG_DIR 0xFFC03318 /* PORTG Port x GPIO Direction Register */ +#define PORTG_DIR_SET 0xFFC0331C /* PORTG Port x GPIO Direction Set Register */ +#define PORTG_DIR_CLEAR 0xFFC03320 /* PORTG Port x GPIO Direction Clear Register */ +#define PORTG_INEN 0xFFC03324 /* PORTG Port x GPIO Input Enable Register */ +#define PORTG_INEN_SET 0xFFC03328 /* PORTG Port x GPIO Input Enable Set Register */ +#define PORTG_INEN_CLEAR 0xFFC0332C /* PORTG Port x GPIO Input Enable Clear Register */ +#define PORTG_MUX 0xFFC03330 /* PORTG Port x Multiplexer Control Register */ +#define PORTG_DATA_TGL 0xFFC03334 /* PORTG Port x GPIO Input Enable Toggle Register */ +#define PORTG_POL 0xFFC03338 /* PORTG Port x GPIO Programming Inversion Register */ +#define PORTG_POL_SET 0xFFC0333C /* PORTG Port x GPIO Programming Inversion Set Register */ +#define PORTG_POL_CLEAR 0xFFC03340 /* PORTG Port x GPIO Programming Inversion Clear Register */ +#define PORTG_LOCK 0xFFC03344 /* PORTG Port x GPIO Lock Register */ +#define PORTG_REVID 0xFFC0337C /* PORTG Port x GPIO Revision ID */ + + +/* ========================= + PINT Registers + ========================= */ + +/* ========================= + PINT0 + ========================= */ +#define PINT0_MASK_SET 0xFFC04000 /* PINT0 Pint Mask Set Register */ +#define PINT0_MASK_CLEAR 0xFFC04004 /* PINT0 Pint Mask Clear Register */ +#define PINT0_REQUEST 0xFFC04008 /* PINT0 Pint Request Register */ +#define PINT0_ASSIGN 0xFFC0400C /* PINT0 Pint Assign Register */ +#define PINT0_EDGE_SET 0xFFC04010 /* PINT0 Pint Edge Set Register */ +#define PINT0_EDGE_CLEAR 0xFFC04014 /* PINT0 Pint Edge Clear Register */ +#define PINT0_INVERT_SET 0xFFC04018 /* PINT0 Pint Invert Set Register */ +#define PINT0_INVERT_CLEAR 0xFFC0401C /* PINT0 Pint Invert Clear Register */ +#define PINT0_PINSTATE 0xFFC04020 /* PINT0 Pint Pinstate Register */ +#define PINT0_LATCH 0xFFC04024 /* PINT0 Pint Latch Register */ + +/* ========================= + PINT1 + ========================= */ +#define PINT1_MASK_SET 0xFFC04100 /* PINT1 Pint Mask Set Register */ +#define PINT1_MASK_CLEAR 0xFFC04104 /* PINT1 Pint Mask Clear Register */ +#define PINT1_REQUEST 0xFFC04108 /* PINT1 Pint Request Register */ +#define PINT1_ASSIGN 0xFFC0410C /* PINT1 Pint Assign Register */ +#define PINT1_EDGE_SET 0xFFC04110 /* PINT1 Pint Edge Set Register */ +#define PINT1_EDGE_CLEAR 0xFFC04114 /* PINT1 Pint Edge Clear Register */ +#define PINT1_INVERT_SET 0xFFC04118 /* PINT1 Pint Invert Set Register */ +#define PINT1_INVERT_CLEAR 0xFFC0411C /* PINT1 Pint Invert Clear Register */ +#define PINT1_PINSTATE 0xFFC04120 /* PINT1 Pint Pinstate Register */ +#define PINT1_LATCH 0xFFC04124 /* PINT1 Pint Latch Register */ + +/* ========================= + PINT2 + ========================= */ +#define PINT2_MASK_SET 0xFFC04200 /* PINT2 Pint Mask Set Register */ +#define PINT2_MASK_CLEAR 0xFFC04204 /* PINT2 Pint Mask Clear Register */ +#define PINT2_REQUEST 0xFFC04208 /* PINT2 Pint Request Register */ +#define PINT2_ASSIGN 0xFFC0420C /* PINT2 Pint Assign Register */ +#define PINT2_EDGE_SET 0xFFC04210 /* PINT2 Pint Edge Set Register */ +#define PINT2_EDGE_CLEAR 0xFFC04214 /* PINT2 Pint Edge Clear Register */ +#define PINT2_INVERT_SET 0xFFC04218 /* PINT2 Pint Invert Set Register */ +#define PINT2_INVERT_CLEAR 0xFFC0421C /* PINT2 Pint Invert Clear Register */ +#define PINT2_PINSTATE 0xFFC04220 /* PINT2 Pint Pinstate Register */ +#define PINT2_LATCH 0xFFC04224 /* PINT2 Pint Latch Register */ + +/* ========================= + PINT3 + ========================= */ +#define PINT3_MASK_SET 0xFFC04300 /* PINT3 Pint Mask Set Register */ +#define PINT3_MASK_CLEAR 0xFFC04304 /* PINT3 Pint Mask Clear Register */ +#define PINT3_REQUEST 0xFFC04308 /* PINT3 Pint Request Register */ +#define PINT3_ASSIGN 0xFFC0430C /* PINT3 Pint Assign Register */ +#define PINT3_EDGE_SET 0xFFC04310 /* PINT3 Pint Edge Set Register */ +#define PINT3_EDGE_CLEAR 0xFFC04314 /* PINT3 Pint Edge Clear Register */ +#define PINT3_INVERT_SET 0xFFC04318 /* PINT3 Pint Invert Set Register */ +#define PINT3_INVERT_CLEAR 0xFFC0431C /* PINT3 Pint Invert Clear Register */ +#define PINT3_PINSTATE 0xFFC04320 /* PINT3 Pint Pinstate Register */ +#define PINT3_LATCH 0xFFC04324 /* PINT3 Pint Latch Register */ + +/* ========================= + PINT4 + ========================= */ +#define PINT4_MASK_SET 0xFFC04400 /* PINT4 Pint Mask Set Register */ +#define PINT4_MASK_CLEAR 0xFFC04404 /* PINT4 Pint Mask Clear Register */ +#define PINT4_REQUEST 0xFFC04408 /* PINT4 Pint Request Register */ +#define PINT4_ASSIGN 0xFFC0440C /* PINT4 Pint Assign Register */ +#define PINT4_EDGE_SET 0xFFC04410 /* PINT4 Pint Edge Set Register */ +#define PINT4_EDGE_CLEAR 0xFFC04414 /* PINT4 Pint Edge Clear Register */ +#define PINT4_INVERT_SET 0xFFC04418 /* PINT4 Pint Invert Set Register */ +#define PINT4_INVERT_CLEAR 0xFFC0441C /* PINT4 Pint Invert Clear Register */ +#define PINT4_PINSTATE 0xFFC04420 /* PINT4 Pint Pinstate Register */ +#define PINT4_LATCH 0xFFC04424 /* PINT4 Pint Latch Register */ + +/* ========================= + PINT5 + ========================= */ +#define PINT5_MASK_SET 0xFFC04500 /* PINT5 Pint Mask Set Register */ +#define PINT5_MASK_CLEAR 0xFFC04504 /* PINT5 Pint Mask Clear Register */ +#define PINT5_REQUEST 0xFFC04508 /* PINT5 Pint Request Register */ +#define PINT5_ASSIGN 0xFFC0450C /* PINT5 Pint Assign Register */ +#define PINT5_EDGE_SET 0xFFC04510 /* PINT5 Pint Edge Set Register */ +#define PINT5_EDGE_CLEAR 0xFFC04514 /* PINT5 Pint Edge Clear Register */ +#define PINT5_INVERT_SET 0xFFC04518 /* PINT5 Pint Invert Set Register */ +#define PINT5_INVERT_CLEAR 0xFFC0451C /* PINT5 Pint Invert Clear Register */ +#define PINT5_PINSTATE 0xFFC04520 /* PINT5 Pint Pinstate Register */ +#define PINT5_LATCH 0xFFC04524 /* PINT5 Pint Latch Register */ + + +/* ========================= + SMC Registers + ========================= */ + +/* ========================= + SMC0 + ========================= */ +#define SMC_GCTL 0xFFC16004 /* SMC0 SMC Control Register */ +#define SMC_GSTAT 0xFFC16008 /* SMC0 SMC Status Register */ +#define SMC_B0CTL 0xFFC1600C /* SMC0 SMC Bank0 Control Register */ +#define SMC_B0TIM 0xFFC16010 /* SMC0 SMC Bank0 Timing Register */ +#define SMC_B0ETIM 0xFFC16014 /* SMC0 SMC Bank0 Extended Timing Register */ +#define SMC_B1CTL 0xFFC1601C /* SMC0 SMC BANK1 Control Register */ +#define SMC_B1TIM 0xFFC16020 /* SMC0 SMC BANK1 Timing Register */ +#define SMC_B1ETIM 0xFFC16024 /* SMC0 SMC BANK1 Extended Timing Register */ +#define SMC_B2CTL 0xFFC1602C /* SMC0 SMC BANK2 Control Register */ +#define SMC_B2TIM 0xFFC16030 /* SMC0 SMC BANK2 Timing Register */ +#define SMC_B2ETIM 0xFFC16034 /* SMC0 SMC BANK2 Extended Timing Register */ +#define SMC_B3CTL 0xFFC1603C /* SMC0 SMC BANK3 Control Register */ +#define SMC_B3TIM 0xFFC16040 /* SMC0 SMC BANK3 Timing Register */ +#define SMC_B3ETIM 0xFFC16044 /* SMC0 SMC BANK3 Extended Timing Register */ + + +/* ========================= + WDOG Registers + ========================= */ + +/* ========================= + WDOG0 + ========================= */ +#define WDOG0_CTL 0xFFC17000 /* WDOG0 Control Register */ +#define WDOG0_CNT 0xFFC17004 /* WDOG0 Count Register */ +#define WDOG0_STAT 0xFFC17008 /* WDOG0 Watchdog Timer Status Register */ +#define WDOG_CTL WDOG0_CTL +#define WDOG_CNT WDOG0_CNT +#define WDOG_STAT WDOG0_STAT + +/* ========================= + WDOG1 + ========================= */ +#define WDOG1_CTL 0xFFC17800 /* WDOG1 Control Register */ +#define WDOG1_CNT 0xFFC17804 /* WDOG1 Count Register */ +#define WDOG1_STAT 0xFFC17808 /* WDOG1 Watchdog Timer Status Register */ + + +/* ========================= + SDU Registers + ========================= */ + +/* ========================= + SDU0 + ========================= */ +#define SDU0_IDCODE 0xFFC1F020 /* SDU0 ID Code Register */ +#define SDU0_CTL 0xFFC1F050 /* SDU0 Control Register */ +#define SDU0_STAT 0xFFC1F054 /* SDU0 Status Register */ +#define SDU0_MACCTL 0xFFC1F058 /* SDU0 Memory Access Control Register */ +#define SDU0_MACADDR 0xFFC1F05C /* SDU0 Memory Access Address Register */ +#define SDU0_MACDATA 0xFFC1F060 /* SDU0 Memory Access Data Register */ +#define SDU0_DMARD 0xFFC1F064 /* SDU0 DMA Read Data Register */ +#define SDU0_DMAWD 0xFFC1F068 /* SDU0 DMA Write Data Register */ +#define SDU0_MSG 0xFFC1F080 /* SDU0 Message Register */ +#define SDU0_MSG_SET 0xFFC1F084 /* SDU0 Message Set Register */ +#define SDU0_MSG_CLR 0xFFC1F088 /* SDU0 Message Clear Register */ +#define SDU0_GHLT 0xFFC1F08C /* SDU0 Group Halt Register */ + + +/* ========================= + EMAC Registers + ========================= */ +/* ========================= + EMAC0 + ========================= */ +#define EMAC0_MACCFG 0xFFC20000 /* EMAC0 MAC Configuration Register */ +#define EMAC0_MACFRMFILT 0xFFC20004 /* EMAC0 Filter Register for filtering Received Frames */ +#define EMAC0_HASHTBL_HI 0xFFC20008 /* EMAC0 Contains the Upper 32 bits of the hash table */ +#define EMAC0_HASHTBL_LO 0xFFC2000C /* EMAC0 Contains the lower 32 bits of the hash table */ +#define EMAC0_GMII_ADDR 0xFFC20010 /* EMAC0 Management Address Register */ +#define EMAC0_GMII_DATA 0xFFC20014 /* EMAC0 Management Data Register */ +#define EMAC0_FLOWCTL 0xFFC20018 /* EMAC0 MAC FLow Control Register */ +#define EMAC0_VLANTAG 0xFFC2001C /* EMAC0 VLAN Tag Register */ +#define EMAC0_VER 0xFFC20020 /* EMAC0 EMAC Version Register */ +#define EMAC0_DBG 0xFFC20024 /* EMAC0 EMAC Debug Register */ +#define EMAC0_RMTWKUP 0xFFC20028 /* EMAC0 Remote wake up frame register */ +#define EMAC0_PMT_CTLSTAT 0xFFC2002C /* EMAC0 PMT Control and Status Register */ +#define EMAC0_ISTAT 0xFFC20038 /* EMAC0 EMAC Interrupt Status Register */ +#define EMAC0_IMSK 0xFFC2003C /* EMAC0 EMAC Interrupt Mask Register */ +#define EMAC0_ADDR0_HI 0xFFC20040 /* EMAC0 EMAC Address0 High Register */ +#define EMAC0_ADDR0_LO 0xFFC20044 /* EMAC0 EMAC Address0 Low Register */ +#define EMAC0_MMC_CTL 0xFFC20100 /* EMAC0 MMC Control Register */ +#define EMAC0_MMC_RXINT 0xFFC20104 /* EMAC0 MMC RX Interrupt Register */ +#define EMAC0_MMC_TXINT 0xFFC20108 /* EMAC0 MMC TX Interrupt Register */ +#define EMAC0_MMC_RXIMSK 0xFFC2010C /* EMAC0 MMC RX Interrupt Mask Register */ +#define EMAC0_MMC_TXIMSK 0xFFC20110 /* EMAC0 MMC TX Interrupt Mask Register */ +#define EMAC0_TXOCTCNT_GB 0xFFC20114 /* EMAC0 Num bytes transmitted exclusive of preamble */ +#define EMAC0_TXFRMCNT_GB 0xFFC20118 /* EMAC0 Num frames transmitted exclusive of retired */ +#define EMAC0_TXBCASTFRM_G 0xFFC2011C /* EMAC0 Number of good broadcast frames transmitted. */ +#define EMAC0_TXMCASTFRM_G 0xFFC20120 /* EMAC0 Number of good multicast frames transmitted. */ +#define EMAC0_TX64_GB 0xFFC20124 /* EMAC0 Number of 64 byte length frames */ +#define EMAC0_TX65TO127_GB 0xFFC20128 /* EMAC0 Number of frames of length b/w 65-127 (inclusive) bytes */ +#define EMAC0_TX128TO255_GB 0xFFC2012C /* EMAC0 Number of frames of length b/w 128-255 (inclusive) bytes */ +#define EMAC0_TX256TO511_GB 0xFFC20130 /* EMAC0 Number of frames of length b/w 256-511 (inclusive) bytes */ +#define EMAC0_TX512TO1023_GB 0xFFC20134 /* EMAC0 Number of frames of length b/w 512-1023 (inclusive) bytes */ +#define EMAC0_TX1024TOMAX_GB 0xFFC20138 /* EMAC0 Number of frames of length b/w 1024-max (inclusive) bytes */ +#define EMAC0_TXUCASTFRM_GB 0xFFC2013C /* EMAC0 Number of good and bad unicast frames transmitted */ +#define EMAC0_TXMCASTFRM_GB 0xFFC20140 /* EMAC0 Number of good and bad multicast frames transmitted */ +#define EMAC0_TXBCASTFRM_GB 0xFFC20144 /* EMAC0 Number of good and bad broadcast frames transmitted */ +#define EMAC0_TXUNDR_ERR 0xFFC20148 /* EMAC0 Number of frames aborted due to frame underflow error */ +#define EMAC0_TXSNGCOL_G 0xFFC2014C /* EMAC0 Number of transmitted frames after single collision */ +#define EMAC0_TXMULTCOL_G 0xFFC20150 /* EMAC0 Number of transmitted frames with more than one collision */ +#define EMAC0_TXDEFERRED 0xFFC20154 /* EMAC0 Number of transmitted frames after deferral */ +#define EMAC0_TXLATECOL 0xFFC20158 /* EMAC0 Number of frames aborted due to late collision error */ +#define EMAC0_TXEXCESSCOL 0xFFC2015C /* EMAC0 Number of aborted frames due to excessive collisions */ +#define EMAC0_TXCARR_ERR 0xFFC20160 /* EMAC0 Number of aborted frames due to carrier sense error */ +#define EMAC0_TXOCTCNT_G 0xFFC20164 /* EMAC0 Number of bytes transmitted in good frames only */ +#define EMAC0_TXFRMCNT_G 0xFFC20168 /* EMAC0 Number of good frames transmitted. */ +#define EMAC0_TXEXCESSDEF 0xFFC2016C /* EMAC0 Number of frames aborted due to excessive deferral */ +#define EMAC0_TXPAUSEFRM 0xFFC20170 /* EMAC0 Number of good PAUSE frames transmitted. */ +#define EMAC0_TXVLANFRM_G 0xFFC20174 /* EMAC0 Number of VLAN frames transmitted */ +#define EMAC0_RXFRMCNT_GB 0xFFC20180 /* EMAC0 Number of good and bad frames received. */ +#define EMAC0_RXOCTCNT_GB 0xFFC20184 /* EMAC0 Number of bytes received in good and bad frames */ +#define EMAC0_RXOCTCNT_G 0xFFC20188 /* EMAC0 Number of bytes received only in good frames */ +#define EMAC0_RXBCASTFRM_G 0xFFC2018C /* EMAC0 Number of good broadcast frames received. */ +#define EMAC0_RXMCASTFRM_G 0xFFC20190 /* EMAC0 Number of good multicast frames received */ +#define EMAC0_RXCRC_ERR 0xFFC20194 /* EMAC0 Number of frames received with CRC error */ +#define EMAC0_RXALIGN_ERR 0xFFC20198 /* EMAC0 Number of frames with alignment error */ +#define EMAC0_RXRUNT_ERR 0xFFC2019C /* EMAC0 Number of frames received with runt error. */ +#define EMAC0_RXJAB_ERR 0xFFC201A0 /* EMAC0 Number of frames received with length greater than 1518 */ +#define EMAC0_RXUSIZE_G 0xFFC201A4 /* EMAC0 Number of frames received with length 64 */ +#define EMAC0_RXOSIZE_G 0xFFC201A8 /* EMAC0 Number of frames received with length greater than maxium */ +#define EMAC0_RX64_GB 0xFFC201AC /* EMAC0 Number of good and bad frames of lengh 64 bytes */ +#define EMAC0_RX65TO127_GB 0xFFC201B0 /* EMAC0 Number of good and bad frame between 64-127(inclusive) */ +#define EMAC0_RX128TO255_GB 0xFFC201B4 /* EMAC0 Number of good and bad frames received with length between 128 and 255 (inclusive) bytes, exclusive of preamble. */ +#define EMAC0_RX256TO511_GB 0xFFC201B8 /* EMAC0 Number of good and bad frames between 256-511(inclusive) */ +#define EMAC0_RX512TO1023_GB 0xFFC201BC /* EMAC0 Number of good and bad frames received between 512-1023 */ +#define EMAC0_RX1024TOMAX_GB 0xFFC201C0 /* EMAC0 Number of frames received between 1024 and maxsize */ +#define EMAC0_RXUCASTFRM_G 0xFFC201C4 /* EMAC0 Number of good unicast frames received. */ +#define EMAC0_RXLEN_ERR 0xFFC201C8 /* EMAC0 Number of frames received with length error */ +#define EMAC0_RXOORTYPE 0xFFC201CC /* EMAC0 Number of frames with length not equal to valid frame size */ +#define EMAC0_RXPAUSEFRM 0xFFC201D0 /* EMAC0 Number of good and valid PAUSE frames received. */ +#define EMAC0_RXFIFO_OVF 0xFFC201D4 /* EMAC0 Number of missed received frames due to FIFO overflow. This counter is not present in the GMAC-CORE configuration. */ +#define EMAC0_RXVLANFRM_GB 0xFFC201D8 /* EMAC0 Number of good and bad VLAN frames received. */ +#define EMAC0_RXWDOG_ERR 0xFFC201DC /* EMAC0 Frames received with error due to watchdog timeout */ +#define EMAC0_IPC_RXIMSK 0xFFC20200 /* EMAC0 MMC IPC RX Interrupt Mask Register */ +#define EMAC0_IPC_RXINT 0xFFC20208 /* EMAC0 MMC IPC RX Interrupt Register */ +#define EMAC0_RXIPV4_GD_FRM 0xFFC20210 /* EMAC0 Number of good IPv4 datagrams */ +#define EMAC0_RXIPV4_HDR_ERR_FRM 0xFFC20214 /* EMAC0 Number of IPv4 datagrams with header errors */ +#define EMAC0_RXIPV4_NOPAY_FRM 0xFFC20218 /* EMAC0 Number of IPv4 datagrams without checksum */ +#define EMAC0_RXIPV4_FRAG_FRM 0xFFC2021C /* EMAC0 Number of good IPv4 datagrams with fragmentation */ +#define EMAC0_RXIPV4_UDSBL_FRM 0xFFC20220 /* EMAC0 Number of IPv4 UDP datagrams with disabled checksum */ +#define EMAC0_RXIPV6_GD_FRM 0xFFC20224 /* EMAC0 Number of IPv4 datagrams with TCP/UDP/ICMP payloads */ +#define EMAC0_RXIPV6_HDR_ERR_FRM 0xFFC20228 /* EMAC0 Number of IPv6 datagrams with header errors */ +#define EMAC0_RXIPV6_NOPAY_FRM 0xFFC2022C /* EMAC0 Number of IPv6 datagrams with no TCP/UDP/ICMP payload */ +#define EMAC0_RXUDP_GD_FRM 0xFFC20230 /* EMAC0 Number of good IP datagrames with good UDP payload */ +#define EMAC0_RXUDP_ERR_FRM 0xFFC20234 /* EMAC0 Number of good IP datagrams with UDP checksum errors */ +#define EMAC0_RXTCP_GD_FRM 0xFFC20238 /* EMAC0 Number of good IP datagrams with a good TCP payload */ +#define EMAC0_RXTCP_ERR_FRM 0xFFC2023C /* EMAC0 Number of good IP datagrams with TCP checksum errors */ +#define EMAC0_RXICMP_GD_FRM 0xFFC20240 /* EMAC0 Number of good IP datagrams with a good ICMP payload */ +#define EMAC0_RXICMP_ERR_FRM 0xFFC20244 /* EMAC0 Number of good IP datagrams with ICMP checksum errors */ +#define EMAC0_RXIPV4_GD_OCT 0xFFC20250 /* EMAC0 Bytes received in IPv4 datagrams including tcp,udp or icmp */ +#define EMAC0_RXIPV4_HDR_ERR_OCT 0xFFC20254 /* EMAC0 Bytes received in IPv4 datagrams with header errors */ +#define EMAC0_RXIPV4_NOPAY_OCT 0xFFC20258 /* EMAC0 Bytes received in IPv4 datagrams without tcp,udp,icmp load */ +#define EMAC0_RXIPV4_FRAG_OCT 0xFFC2025C /* EMAC0 Bytes received in fragmented IPv4 datagrams */ +#define EMAC0_RXIPV4_UDSBL_OCT 0xFFC20260 /* EMAC0 Bytes received in UDP segment with checksum disabled */ +#define EMAC0_RXIPV6_GD_OCT 0xFFC20264 /* EMAC0 Bytes received in good IPv6 including tcp,udp or icmp load */ +#define EMAC0_RXIPV6_HDR_ERR_OCT 0xFFC20268 /* EMAC0 Number of bytes received in IPv6 with header errors */ +#define EMAC0_RXIPV6_NOPAY_OCT 0xFFC2026C /* EMAC0 Bytes received in IPv6 without tcp,udp or icmp load */ +#define EMAC0_RXUDP_GD_OCT 0xFFC20270 /* EMAC0 Number of bytes received in good UDP segments */ +#define EMAC0_RXUDP_ERR_OCT 0xFFC20274 /* EMAC0 Number of bytes received in UDP segment with checksum err */ +#define EMAC0_RXTCP_GD_OCT 0xFFC20278 /* EMAC0 Number of bytes received in a good TCP segment */ +#define EMAC0_RXTCP_ERR_OCT 0xFFC2027C /* EMAC0 Number of bytes received in TCP segment with checksum err */ +#define EMAC0_RXICMP_GD_OCT 0xFFC20280 /* EMAC0 Number of bytes received in a good ICMP segment */ +#define EMAC0_RXICMP_ERR_OCT 0xFFC20284 /* EMAC0 Bytes received in an ICMP segment with checksum errors */ +#define EMAC0_TM_CTL 0xFFC20700 /* EMAC0 EMAC Time Stamp Control Register */ +#define EMAC0_TM_SUBSEC 0xFFC20704 /* EMAC0 EMAC Time Stamp Sub Second Increment */ +#define EMAC0_TM_SEC 0xFFC20708 /* EMAC0 EMAC Time Stamp Second Register */ +#define EMAC0_TM_NSEC 0xFFC2070C /* EMAC0 EMAC Time Stamp Nano Second Register */ +#define EMAC0_TM_SECUPDT 0xFFC20710 /* EMAC0 EMAC Time Stamp Seconds Update */ +#define EMAC0_TM_NSECUPDT 0xFFC20714 /* EMAC0 EMAC Time Stamp Nano Seconds Update */ +#define EMAC0_TM_ADDEND 0xFFC20718 /* EMAC0 EMAC Time Stamp Addend Register */ +#define EMAC0_TM_TGTM 0xFFC2071C /* EMAC0 EMAC Time Stamp Target Time Sec. */ +#define EMAC0_TM_NTGTM 0xFFC20720 /* EMAC0 EMAC Time Stamp Target Time Nanosec. */ +#define EMAC0_TM_HISEC 0xFFC20724 /* EMAC0 EMAC Time Stamp High Second Register */ +#define EMAC0_TM_STMPSTAT 0xFFC20728 /* EMAC0 EMAC Time Stamp Status Register */ +#define EMAC0_TM_PPSCTL 0xFFC2072C /* EMAC0 EMAC PPS Control Register */ +#define EMAC0_TM_AUXSTMP_NSEC 0xFFC20730 /* EMAC0 EMAC Auxillary Time Stamp Nano Register */ +#define EMAC0_TM_AUXSTMP_SEC 0xFFC20734 /* EMAC0 EMAC Auxillary Time Stamp Sec Register */ +#define EMAC0_DMA_BUSMODE 0xFFC21000 /* EMAC0 Bus Operating Modes for EMAC DMA */ +#define EMAC0_DMA_TXPOLL 0xFFC21004 /* EMAC0 TX DMA Poll demand register */ +#define EMAC0_DMA_RXPOLL 0xFFC21008 /* EMAC0 RX DMA Poll demand register */ +#define EMAC0_DMA_RXDSC_ADDR 0xFFC2100C /* EMAC0 RX Descriptor List Address */ +#define EMAC0_DMA_TXDSC_ADDR 0xFFC21010 /* EMAC0 TX Descriptor List Address */ +#define EMAC0_DMA_STAT 0xFFC21014 /* EMAC0 DMA Status Register */ +#define EMAC0_DMA_OPMODE 0xFFC21018 /* EMAC0 DMA Operation Mode Register */ +#define EMAC0_DMA_IEN 0xFFC2101C /* EMAC0 DMA Interrupt Enable Register */ +#define EMAC0_DMA_MISS_FRM 0xFFC21020 /* EMAC0 DMA missed frame and buffer overflow counter */ +#define EMAC0_DMA_RXIWDOG 0xFFC21024 /* EMAC0 DMA RX Interrupt Watch Dog timer */ +#define EMAC0_DMA_BMMODE 0xFFC21028 /* EMAC0 AXI Bus Mode Register */ +#define EMAC0_DMA_BMSTAT 0xFFC2102C /* EMAC0 AXI Status Register */ +#define EMAC0_DMA_TXDSC_CUR 0xFFC21048 /* EMAC0 TX current descriptor register */ +#define EMAC0_DMA_RXDSC_CUR 0xFFC2104C /* EMAC0 RX current descriptor register */ +#define EMAC0_DMA_TXBUF_CUR 0xFFC21050 /* EMAC0 TX current buffer pointer register */ +#define EMAC0_DMA_RXBUF_CUR 0xFFC21054 /* EMAC0 RX current buffer pointer register */ +#define EMAC0_HWFEAT 0xFFC21058 /* EMAC0 Hardware Feature Register */ + +/* ========================= + EMAC1 + ========================= */ +#define EMAC1_MACCFG 0xFFC22000 /* EMAC1 MAC Configuration Register */ +#define EMAC1_MACFRMFILT 0xFFC22004 /* EMAC1 Filter Register for filtering Received Frames */ +#define EMAC1_HASHTBL_HI 0xFFC22008 /* EMAC1 Contains the Upper 32 bits of the hash table */ +#define EMAC1_HASHTBL_LO 0xFFC2200C /* EMAC1 Contains the lower 32 bits of the hash table */ +#define EMAC1_GMII_ADDR 0xFFC22010 /* EMAC1 Management Address Register */ +#define EMAC1_GMII_DATA 0xFFC22014 /* EMAC1 Management Data Register */ +#define EMAC1_FLOWCTL 0xFFC22018 /* EMAC1 MAC FLow Control Register */ +#define EMAC1_VLANTAG 0xFFC2201C /* EMAC1 VLAN Tag Register */ +#define EMAC1_VER 0xFFC22020 /* EMAC1 EMAC Version Register */ +#define EMAC1_DBG 0xFFC22024 /* EMAC1 EMAC Debug Register */ +#define EMAC1_RMTWKUP 0xFFC22028 /* EMAC1 Remote wake up frame register */ +#define EMAC1_PMT_CTLSTAT 0xFFC2202C /* EMAC1 PMT Control and Status Register */ +#define EMAC1_ISTAT 0xFFC22038 /* EMAC1 EMAC Interrupt Status Register */ +#define EMAC1_IMSK 0xFFC2203C /* EMAC1 EMAC Interrupt Mask Register */ +#define EMAC1_ADDR0_HI 0xFFC22040 /* EMAC1 EMAC Address0 High Register */ +#define EMAC1_ADDR0_LO 0xFFC22044 /* EMAC1 EMAC Address0 Low Register */ +#define EMAC1_MMC_CTL 0xFFC22100 /* EMAC1 MMC Control Register */ +#define EMAC1_MMC_RXINT 0xFFC22104 /* EMAC1 MMC RX Interrupt Register */ +#define EMAC1_MMC_TXINT 0xFFC22108 /* EMAC1 MMC TX Interrupt Register */ +#define EMAC1_MMC_RXIMSK 0xFFC2210C /* EMAC1 MMC RX Interrupt Mask Register */ +#define EMAC1_MMC_TXIMSK 0xFFC22110 /* EMAC1 MMC TX Interrupt Mask Register */ +#define EMAC1_TXOCTCNT_GB 0xFFC22114 /* EMAC1 Num bytes transmitted exclusive of preamble */ +#define EMAC1_TXFRMCNT_GB 0xFFC22118 /* EMAC1 Num frames transmitted exclusive of retired */ +#define EMAC1_TXBCASTFRM_G 0xFFC2211C /* EMAC1 Number of good broadcast frames transmitted. */ +#define EMAC1_TXMCASTFRM_G 0xFFC22120 /* EMAC1 Number of good multicast frames transmitted. */ +#define EMAC1_TX64_GB 0xFFC22124 /* EMAC1 Number of 64 byte length frames */ +#define EMAC1_TX65TO127_GB 0xFFC22128 /* EMAC1 Number of frames of length b/w 65-127 (inclusive) bytes */ +#define EMAC1_TX128TO255_GB 0xFFC2212C /* EMAC1 Number of frames of length b/w 128-255 (inclusive) bytes */ +#define EMAC1_TX256TO511_GB 0xFFC22130 /* EMAC1 Number of frames of length b/w 256-511 (inclusive) bytes */ +#define EMAC1_TX512TO1023_GB 0xFFC22134 /* EMAC1 Number of frames of length b/w 512-1023 (inclusive) bytes */ +#define EMAC1_TX1024TOMAX_GB 0xFFC22138 /* EMAC1 Number of frames of length b/w 1024-max (inclusive) bytes */ +#define EMAC1_TXUCASTFRM_GB 0xFFC2213C /* EMAC1 Number of good and bad unicast frames transmitted */ +#define EMAC1_TXMCASTFRM_GB 0xFFC22140 /* EMAC1 Number of good and bad multicast frames transmitted */ +#define EMAC1_TXBCASTFRM_GB 0xFFC22144 /* EMAC1 Number of good and bad broadcast frames transmitted */ +#define EMAC1_TXUNDR_ERR 0xFFC22148 /* EMAC1 Number of frames aborted due to frame underflow error */ +#define EMAC1_TXSNGCOL_G 0xFFC2214C /* EMAC1 Number of transmitted frames after single collision */ +#define EMAC1_TXMULTCOL_G 0xFFC22150 /* EMAC1 Number of transmitted frames with more than one collision */ +#define EMAC1_TXDEFERRED 0xFFC22154 /* EMAC1 Number of transmitted frames after deferral */ +#define EMAC1_TXLATECOL 0xFFC22158 /* EMAC1 Number of frames aborted due to late collision error */ +#define EMAC1_TXEXCESSCOL 0xFFC2215C /* EMAC1 Number of aborted frames due to excessive collisions */ +#define EMAC1_TXCARR_ERR 0xFFC22160 /* EMAC1 Number of aborted frames due to carrier sense error */ +#define EMAC1_TXOCTCNT_G 0xFFC22164 /* EMAC1 Number of bytes transmitted in good frames only */ +#define EMAC1_TXFRMCNT_G 0xFFC22168 /* EMAC1 Number of good frames transmitted. */ +#define EMAC1_TXEXCESSDEF 0xFFC2216C /* EMAC1 Number of frames aborted due to excessive deferral */ +#define EMAC1_TXPAUSEFRM 0xFFC22170 /* EMAC1 Number of good PAUSE frames transmitted. */ +#define EMAC1_TXVLANFRM_G 0xFFC22174 /* EMAC1 Number of VLAN frames transmitted */ +#define EMAC1_RXFRMCNT_GB 0xFFC22180 /* EMAC1 Number of good and bad frames received. */ +#define EMAC1_RXOCTCNT_GB 0xFFC22184 /* EMAC1 Number of bytes received in good and bad frames */ +#define EMAC1_RXOCTCNT_G 0xFFC22188 /* EMAC1 Number of bytes received only in good frames */ +#define EMAC1_RXBCASTFRM_G 0xFFC2218C /* EMAC1 Number of good broadcast frames received. */ +#define EMAC1_RXMCASTFRM_G 0xFFC22190 /* EMAC1 Number of good multicast frames received */ +#define EMAC1_RXCRC_ERR 0xFFC22194 /* EMAC1 Number of frames received with CRC error */ +#define EMAC1_RXALIGN_ERR 0xFFC22198 /* EMAC1 Number of frames with alignment error */ +#define EMAC1_RXRUNT_ERR 0xFFC2219C /* EMAC1 Number of frames received with runt error. */ +#define EMAC1_RXJAB_ERR 0xFFC221A0 /* EMAC1 Number of frames received with length greater than 1518 */ +#define EMAC1_RXUSIZE_G 0xFFC221A4 /* EMAC1 Number of frames received with length 64 */ +#define EMAC1_RXOSIZE_G 0xFFC221A8 /* EMAC1 Number of frames received with length greater than maxium */ +#define EMAC1_RX64_GB 0xFFC221AC /* EMAC1 Number of good and bad frames of lengh 64 bytes */ +#define EMAC1_RX65TO127_GB 0xFFC221B0 /* EMAC1 Number of good and bad frame between 64-127(inclusive) */ +#define EMAC1_RX128TO255_GB 0xFFC221B4 /* EMAC1 Number of good and bad frames received with length between 128 and 255 (inclusive) bytes, exclusive of preamble. */ +#define EMAC1_RX256TO511_GB 0xFFC221B8 /* EMAC1 Number of good and bad frames between 256-511(inclusive) */ +#define EMAC1_RX512TO1023_GB 0xFFC221BC /* EMAC1 Number of good and bad frames received between 512-1023 */ +#define EMAC1_RX1024TOMAX_GB 0xFFC221C0 /* EMAC1 Number of frames received between 1024 and maxsize */ +#define EMAC1_RXUCASTFRM_G 0xFFC221C4 /* EMAC1 Number of good unicast frames received. */ +#define EMAC1_RXLEN_ERR 0xFFC221C8 /* EMAC1 Number of frames received with length error */ +#define EMAC1_RXOORTYPE 0xFFC221CC /* EMAC1 Number of frames with length not equal to valid frame size */ +#define EMAC1_RXPAUSEFRM 0xFFC221D0 /* EMAC1 Number of good and valid PAUSE frames received. */ +#define EMAC1_RXFIFO_OVF 0xFFC221D4 /* EMAC1 Number of missed received frames due to FIFO overflow. This counter is not present in the GMAC-CORE configuration. */ +#define EMAC1_RXVLANFRM_GB 0xFFC221D8 /* EMAC1 Number of good and bad VLAN frames received. */ +#define EMAC1_RXWDOG_ERR 0xFFC221DC /* EMAC1 Frames received with error due to watchdog timeout */ +#define EMAC1_IPC_RXIMSK 0xFFC22200 /* EMAC1 MMC IPC RX Interrupt Mask Register */ +#define EMAC1_IPC_RXINT 0xFFC22208 /* EMAC1 MMC IPC RX Interrupt Register */ +#define EMAC1_RXIPV4_GD_FRM 0xFFC22210 /* EMAC1 Number of good IPv4 datagrams */ +#define EMAC1_RXIPV4_HDR_ERR_FRM 0xFFC22214 /* EMAC1 Number of IPv4 datagrams with header errors */ +#define EMAC1_RXIPV4_NOPAY_FRM 0xFFC22218 /* EMAC1 Number of IPv4 datagrams without checksum */ +#define EMAC1_RXIPV4_FRAG_FRM 0xFFC2221C /* EMAC1 Number of good IPv4 datagrams with fragmentation */ +#define EMAC1_RXIPV4_UDSBL_FRM 0xFFC22220 /* EMAC1 Number of IPv4 UDP datagrams with disabled checksum */ +#define EMAC1_RXIPV6_GD_FRM 0xFFC22224 /* EMAC1 Number of IPv4 datagrams with TCP/UDP/ICMP payloads */ +#define EMAC1_RXIPV6_HDR_ERR_FRM 0xFFC22228 /* EMAC1 Number of IPv6 datagrams with header errors */ +#define EMAC1_RXIPV6_NOPAY_FRM 0xFFC2222C /* EMAC1 Number of IPv6 datagrams with no TCP/UDP/ICMP payload */ +#define EMAC1_RXUDP_GD_FRM 0xFFC22230 /* EMAC1 Number of good IP datagrames with good UDP payload */ +#define EMAC1_RXUDP_ERR_FRM 0xFFC22234 /* EMAC1 Number of good IP datagrams with UDP checksum errors */ +#define EMAC1_RXTCP_GD_FRM 0xFFC22238 /* EMAC1 Number of good IP datagrams with a good TCP payload */ +#define EMAC1_RXTCP_ERR_FRM 0xFFC2223C /* EMAC1 Number of good IP datagrams with TCP checksum errors */ +#define EMAC1_RXICMP_GD_FRM 0xFFC22240 /* EMAC1 Number of good IP datagrams with a good ICMP payload */ +#define EMAC1_RXICMP_ERR_FRM 0xFFC22244 /* EMAC1 Number of good IP datagrams with ICMP checksum errors */ +#define EMAC1_RXIPV4_GD_OCT 0xFFC22250 /* EMAC1 Bytes received in IPv4 datagrams including tcp,udp or icmp */ +#define EMAC1_RXIPV4_HDR_ERR_OCT 0xFFC22254 /* EMAC1 Bytes received in IPv4 datagrams with header errors */ +#define EMAC1_RXIPV4_NOPAY_OCT 0xFFC22258 /* EMAC1 Bytes received in IPv4 datagrams without tcp,udp,icmp load */ +#define EMAC1_RXIPV4_FRAG_OCT 0xFFC2225C /* EMAC1 Bytes received in fragmented IPv4 datagrams */ +#define EMAC1_RXIPV4_UDSBL_OCT 0xFFC22260 /* EMAC1 Bytes received in UDP segment with checksum disabled */ +#define EMAC1_RXIPV6_GD_OCT 0xFFC22264 /* EMAC1 Bytes received in good IPv6 including tcp,udp or icmp load */ +#define EMAC1_RXIPV6_HDR_ERR_OCT 0xFFC22268 /* EMAC1 Number of bytes received in IPv6 with header errors */ +#define EMAC1_RXIPV6_NOPAY_OCT 0xFFC2226C /* EMAC1 Bytes received in IPv6 without tcp,udp or icmp load */ +#define EMAC1_RXUDP_GD_OCT 0xFFC22270 /* EMAC1 Number of bytes received in good UDP segments */ +#define EMAC1_RXUDP_ERR_OCT 0xFFC22274 /* EMAC1 Number of bytes received in UDP segment with checksum err */ +#define EMAC1_RXTCP_GD_OCT 0xFFC22278 /* EMAC1 Number of bytes received in a good TCP segment */ +#define EMAC1_RXTCP_ERR_OCT 0xFFC2227C /* EMAC1 Number of bytes received in TCP segment with checksum err */ +#define EMAC1_RXICMP_GD_OCT 0xFFC22280 /* EMAC1 Number of bytes received in a good ICMP segment */ +#define EMAC1_RXICMP_ERR_OCT 0xFFC22284 /* EMAC1 Bytes received in an ICMP segment with checksum errors */ +#define EMAC1_TM_CTL 0xFFC22700 /* EMAC1 EMAC Time Stamp Control Register */ +#define EMAC1_TM_SUBSEC 0xFFC22704 /* EMAC1 EMAC Time Stamp Sub Second Increment */ +#define EMAC1_TM_SEC 0xFFC22708 /* EMAC1 EMAC Time Stamp Second Register */ +#define EMAC1_TM_NSEC 0xFFC2270C /* EMAC1 EMAC Time Stamp Nano Second Register */ +#define EMAC1_TM_SECUPDT 0xFFC22710 /* EMAC1 EMAC Time Stamp Seconds Update */ +#define EMAC1_TM_NSECUPDT 0xFFC22714 /* EMAC1 EMAC Time Stamp Nano Seconds Update */ +#define EMAC1_TM_ADDEND 0xFFC22718 /* EMAC1 EMAC Time Stamp Addend Register */ +#define EMAC1_TM_TGTM 0xFFC2271C /* EMAC1 EMAC Time Stamp Target Time Sec. */ +#define EMAC1_TM_NTGTM 0xFFC22720 /* EMAC1 EMAC Time Stamp Target Time Nanosec. */ +#define EMAC1_TM_HISEC 0xFFC22724 /* EMAC1 EMAC Time Stamp High Second Register */ +#define EMAC1_TM_STMPSTAT 0xFFC22728 /* EMAC1 EMAC Time Stamp Status Register */ +#define EMAC1_TM_PPSCTL 0xFFC2272C /* EMAC1 EMAC PPS Control Register */ +#define EMAC1_TM_AUXSTMP_NSEC 0xFFC22730 /* EMAC1 EMAC Auxillary Time Stamp Nano Register */ +#define EMAC1_TM_AUXSTMP_SEC 0xFFC22734 /* EMAC1 EMAC Auxillary Time Stamp Sec Register */ +#define EMAC1_DMA_BUSMODE 0xFFC23000 /* EMAC1 Bus Operating Modes for EMAC DMA */ +#define EMAC1_DMA_TXPOLL 0xFFC23004 /* EMAC1 TX DMA Poll demand register */ +#define EMAC1_DMA_RXPOLL 0xFFC23008 /* EMAC1 RX DMA Poll demand register */ +#define EMAC1_DMA_RXDSC_ADDR 0xFFC2300C /* EMAC1 RX Descriptor List Address */ +#define EMAC1_DMA_TXDSC_ADDR 0xFFC23010 /* EMAC1 TX Descriptor List Address */ +#define EMAC1_DMA_STAT 0xFFC23014 /* EMAC1 DMA Status Register */ +#define EMAC1_DMA_OPMODE 0xFFC23018 /* EMAC1 DMA Operation Mode Register */ +#define EMAC1_DMA_IEN 0xFFC2301C /* EMAC1 DMA Interrupt Enable Register */ +#define EMAC1_DMA_MISS_FRM 0xFFC23020 /* EMAC1 DMA missed frame and buffer overflow counter */ +#define EMAC1_DMA_RXIWDOG 0xFFC23024 /* EMAC1 DMA RX Interrupt Watch Dog timer */ +#define EMAC1_DMA_BMMODE 0xFFC23028 /* EMAC1 AXI Bus Mode Register */ +#define EMAC1_DMA_BMSTAT 0xFFC2302C /* EMAC1 AXI Status Register */ +#define EMAC1_DMA_TXDSC_CUR 0xFFC23048 /* EMAC1 TX current descriptor register */ +#define EMAC1_DMA_RXDSC_CUR 0xFFC2304C /* EMAC1 RX current descriptor register */ +#define EMAC1_DMA_TXBUF_CUR 0xFFC23050 /* EMAC1 TX current buffer pointer register */ +#define EMAC1_DMA_RXBUF_CUR 0xFFC23054 /* EMAC1 RX current buffer pointer register */ +#define EMAC1_HWFEAT 0xFFC23058 /* EMAC1 Hardware Feature Register */ + + +/* ========================= + SPI Registers + ========================= */ + +/* ========================= + SPI0 + ========================= */ +#define SPI0_REGBASE 0xFFC40400 +#define SPI0_CTL 0xFFC40404 /* SPI0 Control Register */ +#define SPI0_RXCTL 0xFFC40408 /* SPI0 RX Control Register */ +#define SPI0_TXCTL 0xFFC4040C /* SPI0 TX Control Register */ +#define SPI0_CLK 0xFFC40410 /* SPI0 Clock Rate Register */ +#define SPI0_DLY 0xFFC40414 /* SPI0 Delay Register */ +#define SPI0_SLVSEL 0xFFC40418 /* SPI0 Slave Select Register */ +#define SPI0_RWC 0xFFC4041C /* SPI0 Received Word-Count Register */ +#define SPI0_RWCR 0xFFC40420 /* SPI0 Received Word-Count Reload Register */ +#define SPI0_TWC 0xFFC40424 /* SPI0 Transmitted Word-Count Register */ +#define SPI0_TWCR 0xFFC40428 /* SPI0 Transmitted Word-Count Reload Register */ +#define SPI0_IMSK 0xFFC40430 /* SPI0 Interrupt Mask Register */ +#define SPI0_IMSK_CLR 0xFFC40434 /* SPI0 Interrupt Mask Clear Register */ +#define SPI0_IMSK_SET 0xFFC40438 /* SPI0 Interrupt Mask Set Register */ +#define SPI0_STAT 0xFFC40440 /* SPI0 Status Register */ +#define SPI0_ILAT 0xFFC40444 /* SPI0 Masked Interrupt Condition Register */ +#define SPI0_ILAT_CLR 0xFFC40448 /* SPI0 Masked Interrupt Clear Register */ +#define SPI0_RFIFO 0xFFC40450 /* SPI0 Receive FIFO Data Register */ +#define SPI0_TFIFO 0xFFC40458 /* SPI0 Transmit FIFO Data Register */ + +/* ========================= + SPI1 + ========================= */ +#define SPI1_REGBASE 0xFFC40500 +#define SPI1_CTL 0xFFC40504 /* SPI1 Control Register */ +#define SPI1_RXCTL 0xFFC40508 /* SPI1 RX Control Register */ +#define SPI1_TXCTL 0xFFC4050C /* SPI1 TX Control Register */ +#define SPI1_CLK 0xFFC40510 /* SPI1 Clock Rate Register */ +#define SPI1_DLY 0xFFC40514 /* SPI1 Delay Register */ +#define SPI1_SLVSEL 0xFFC40518 /* SPI1 Slave Select Register */ +#define SPI1_RWC 0xFFC4051C /* SPI1 Received Word-Count Register */ +#define SPI1_RWCR 0xFFC40520 /* SPI1 Received Word-Count Reload Register */ +#define SPI1_TWC 0xFFC40524 /* SPI1 Transmitted Word-Count Register */ +#define SPI1_TWCR 0xFFC40528 /* SPI1 Transmitted Word-Count Reload Register */ +#define SPI1_IMSK 0xFFC40530 /* SPI1 Interrupt Mask Register */ +#define SPI1_IMSK_CLR 0xFFC40534 /* SPI1 Interrupt Mask Clear Register */ +#define SPI1_IMSK_SET 0xFFC40538 /* SPI1 Interrupt Mask Set Register */ +#define SPI1_STAT 0xFFC40540 /* SPI1 Status Register */ +#define SPI1_ILAT 0xFFC40544 /* SPI1 Masked Interrupt Condition Register */ +#define SPI1_ILAT_CLR 0xFFC40548 /* SPI1 Masked Interrupt Clear Register */ +#define SPI1_RFIFO 0xFFC40550 /* SPI1 Receive FIFO Data Register */ +#define SPI1_TFIFO 0xFFC40558 /* SPI1 Transmit FIFO Data Register */ + +/* ========================= + SPORT Registers + ========================= */ + +/* ========================= + SPORT0 + ========================= */ +#define SPORT0_CTL_A 0xFFC40000 /* SPORT0 'A' Control Register */ +#define SPORT0_DIV_A 0xFFC40004 /* SPORT0 'A' Clock and FS Divide Register */ +#define SPORT0_MCTL_A 0xFFC40008 /* SPORT0 'A' Multichannel Control Register */ +#define SPORT0_CS0_A 0xFFC4000C /* SPORT0 'A' Multichannel Select Register (Channels 0-31) */ +#define SPORT0_CS1_A 0xFFC40010 /* SPORT0 'A' Multichannel Select Register (Channels 32-63) */ +#define SPORT0_CS2_A 0xFFC40014 /* SPORT0 'A' Multichannel Select Register (Channels 64-95) */ +#define SPORT0_CS3_A 0xFFC40018 /* SPORT0 'A' Multichannel Select Register (Channels 96-127) */ +#define SPORT0_CNT_A 0xFFC4001C /* SPORT0 'A' Frame Sync And Clock Divisor Current Count */ +#define SPORT0_ERR_A 0xFFC40020 /* SPORT0 'A' Error Register */ +#define SPORT0_MSTAT_A 0xFFC40024 /* SPORT0 'A' Multichannel Mode Status Register */ +#define SPORT0_CTL2_A 0xFFC40028 /* SPORT0 'A' Control Register 2 */ +#define SPORT0_TXPRI_A 0xFFC40040 /* SPORT0 'A' Primary Channel Transmit Buffer Register */ +#define SPORT0_RXPRI_A 0xFFC40044 /* SPORT0 'A' Primary Channel Receive Buffer Register */ +#define SPORT0_TXSEC_A 0xFFC40048 /* SPORT0 'A' Secondary Channel Transmit Buffer Register */ +#define SPORT0_RXSEC_A 0xFFC4004C /* SPORT0 'A' Secondary Channel Receive Buffer Register */ +#define SPORT0_CTL_B 0xFFC40080 /* SPORT0 'B' Control Register */ +#define SPORT0_DIV_B 0xFFC40084 /* SPORT0 'B' Clock and FS Divide Register */ +#define SPORT0_MCTL_B 0xFFC40088 /* SPORT0 'B' Multichannel Control Register */ +#define SPORT0_CS0_B 0xFFC4008C /* SPORT0 'B' Multichannel Select Register (Channels 0-31) */ +#define SPORT0_CS1_B 0xFFC40090 /* SPORT0 'B' Multichannel Select Register (Channels 32-63) */ +#define SPORT0_CS2_B 0xFFC40094 /* SPORT0 'B' Multichannel Select Register (Channels 64-95) */ +#define SPORT0_CS3_B 0xFFC40098 /* SPORT0 'B' Multichannel Select Register (Channels 96-127) */ +#define SPORT0_CNT_B 0xFFC4009C /* SPORT0 'B' Frame Sync And Clock Divisor Current Count */ +#define SPORT0_ERR_B 0xFFC400A0 /* SPORT0 'B' Error Register */ +#define SPORT0_MSTAT_B 0xFFC400A4 /* SPORT0 'B' Multichannel Mode Status Register */ +#define SPORT0_CTL2_B 0xFFC400A8 /* SPORT0 'B' Control Register 2 */ +#define SPORT0_TXPRI_B 0xFFC400C0 /* SPORT0 'B' Primary Channel Transmit Buffer Register */ +#define SPORT0_RXPRI_B 0xFFC400C4 /* SPORT0 'B' Primary Channel Receive Buffer Register */ +#define SPORT0_TXSEC_B 0xFFC400C8 /* SPORT0 'B' Secondary Channel Transmit Buffer Register */ +#define SPORT0_RXSEC_B 0xFFC400CC /* SPORT0 'B' Secondary Channel Receive Buffer Register */ + +/* ========================= + SPORT1 + ========================= */ +#define SPORT1_CTL_A 0xFFC40100 /* SPORT1 'A' Control Register */ +#define SPORT1_DIV_A 0xFFC40104 /* SPORT1 'A' Clock and FS Divide Register */ +#define SPORT1_MCTL_A 0xFFC40108 /* SPORT1 'A' Multichannel Control Register */ +#define SPORT1_CS0_A 0xFFC4010C /* SPORT1 'A' Multichannel Select Register (Channels 0-31) */ +#define SPORT1_CS1_A 0xFFC40110 /* SPORT1 'A' Multichannel Select Register (Channels 32-63) */ +#define SPORT1_CS2_A 0xFFC40114 /* SPORT1 'A' Multichannel Select Register (Channels 64-95) */ +#define SPORT1_CS3_A 0xFFC40118 /* SPORT1 'A' Multichannel Select Register (Channels 96-127) */ +#define SPORT1_CNT_A 0xFFC4011C /* SPORT1 'A' Frame Sync And Clock Divisor Current Count */ +#define SPORT1_ERR_A 0xFFC40120 /* SPORT1 'A' Error Register */ +#define SPORT1_MSTAT_A 0xFFC40124 /* SPORT1 'A' Multichannel Mode Status Register */ +#define SPORT1_CTL2_A 0xFFC40128 /* SPORT1 'A' Control Register 2 */ +#define SPORT1_TXPRI_A 0xFFC40140 /* SPORT1 'A' Primary Channel Transmit Buffer Register */ +#define SPORT1_RXPRI_A 0xFFC40144 /* SPORT1 'A' Primary Channel Receive Buffer Register */ +#define SPORT1_TXSEC_A 0xFFC40148 /* SPORT1 'A' Secondary Channel Transmit Buffer Register */ +#define SPORT1_RXSEC_A 0xFFC4014C /* SPORT1 'A' Secondary Channel Receive Buffer Register */ +#define SPORT1_CTL_B 0xFFC40180 /* SPORT1 'B' Control Register */ +#define SPORT1_DIV_B 0xFFC40184 /* SPORT1 'B' Clock and FS Divide Register */ +#define SPORT1_MCTL_B 0xFFC40188 /* SPORT1 'B' Multichannel Control Register */ +#define SPORT1_CS0_B 0xFFC4018C /* SPORT1 'B' Multichannel Select Register (Channels 0-31) */ +#define SPORT1_CS1_B 0xFFC40190 /* SPORT1 'B' Multichannel Select Register (Channels 32-63) */ +#define SPORT1_CS2_B 0xFFC40194 /* SPORT1 'B' Multichannel Select Register (Channels 64-95) */ +#define SPORT1_CS3_B 0xFFC40198 /* SPORT1 'B' Multichannel Select Register (Channels 96-127) */ +#define SPORT1_CNT_B 0xFFC4019C /* SPORT1 'B' Frame Sync And Clock Divisor Current Count */ +#define SPORT1_ERR_B 0xFFC401A0 /* SPORT1 'B' Error Register */ +#define SPORT1_MSTAT_B 0xFFC401A4 /* SPORT1 'B' Multichannel Mode Status Register */ +#define SPORT1_CTL2_B 0xFFC401A8 /* SPORT1 'B' Control Register 2 */ +#define SPORT1_TXPRI_B 0xFFC401C0 /* SPORT1 'B' Primary Channel Transmit Buffer Register */ +#define SPORT1_RXPRI_B 0xFFC401C4 /* SPORT1 'B' Primary Channel Receive Buffer Register */ +#define SPORT1_TXSEC_B 0xFFC401C8 /* SPORT1 'B' Secondary Channel Transmit Buffer Register */ +#define SPORT1_RXSEC_B 0xFFC401CC /* SPORT1 'B' Secondary Channel Receive Buffer Register */ + +/* ========================= + SPORT2 + ========================= */ +#define SPORT2_CTL_A 0xFFC40200 /* SPORT2 'A' Control Register */ +#define SPORT2_DIV_A 0xFFC40204 /* SPORT2 'A' Clock and FS Divide Register */ +#define SPORT2_MCTL_A 0xFFC40208 /* SPORT2 'A' Multichannel Control Register */ +#define SPORT2_CS0_A 0xFFC4020C /* SPORT2 'A' Multichannel Select Register (Channels 0-31) */ +#define SPORT2_CS1_A 0xFFC40210 /* SPORT2 'A' Multichannel Select Register (Channels 32-63) */ +#define SPORT2_CS2_A 0xFFC40214 /* SPORT2 'A' Multichannel Select Register (Channels 64-95) */ +#define SPORT2_CS3_A 0xFFC40218 /* SPORT2 'A' Multichannel Select Register (Channels 96-127) */ +#define SPORT2_CNT_A 0xFFC4021C /* SPORT2 'A' Frame Sync And Clock Divisor Current Count */ +#define SPORT2_ERR_A 0xFFC40220 /* SPORT2 'A' Error Register */ +#define SPORT2_MSTAT_A 0xFFC40224 /* SPORT2 'A' Multichannel Mode Status Register */ +#define SPORT2_CTL2_A 0xFFC40228 /* SPORT2 'A' Control Register 2 */ +#define SPORT2_TXPRI_A 0xFFC40240 /* SPORT2 'A' Primary Channel Transmit Buffer Register */ +#define SPORT2_RXPRI_A 0xFFC40244 /* SPORT2 'A' Primary Channel Receive Buffer Register */ +#define SPORT2_TXSEC_A 0xFFC40248 /* SPORT2 'A' Secondary Channel Transmit Buffer Register */ +#define SPORT2_RXSEC_A 0xFFC4024C /* SPORT2 'A' Secondary Channel Receive Buffer Register */ +#define SPORT2_CTL_B 0xFFC40280 /* SPORT2 'B' Control Register */ +#define SPORT2_DIV_B 0xFFC40284 /* SPORT2 'B' Clock and FS Divide Register */ +#define SPORT2_MCTL_B 0xFFC40288 /* SPORT2 'B' Multichannel Control Register */ +#define SPORT2_CS0_B 0xFFC4028C /* SPORT2 'B' Multichannel Select Register (Channels 0-31) */ +#define SPORT2_CS1_B 0xFFC40290 /* SPORT2 'B' Multichannel Select Register (Channels 32-63) */ +#define SPORT2_CS2_B 0xFFC40294 /* SPORT2 'B' Multichannel Select Register (Channels 64-95) */ +#define SPORT2_CS3_B 0xFFC40298 /* SPORT2 'B' Multichannel Select Register (Channels 96-127) */ +#define SPORT2_CNT_B 0xFFC4029C /* SPORT2 'B' Frame Sync And Clock Divisor Current Count */ +#define SPORT2_ERR_B 0xFFC402A0 /* SPORT2 'B' Error Register */ +#define SPORT2_MSTAT_B 0xFFC402A4 /* SPORT2 'B' Multichannel Mode Status Register */ +#define SPORT2_CTL2_B 0xFFC402A8 /* SPORT2 'B' Control Register 2 */ +#define SPORT2_TXPRI_B 0xFFC402C0 /* SPORT2 'B' Primary Channel Transmit Buffer Register */ +#define SPORT2_RXPRI_B 0xFFC402C4 /* SPORT2 'B' Primary Channel Receive Buffer Register */ +#define SPORT2_TXSEC_B 0xFFC402C8 /* SPORT2 'B' Secondary Channel Transmit Buffer Register */ +#define SPORT2_RXSEC_B 0xFFC402CC /* SPORT2 'B' Secondary Channel Receive Buffer Register */ + +/* ========================= + EPPI Registers + ========================= */ + +/* ========================= + EPPI0 + ========================= */ +#define EPPI0_STAT 0xFFC18000 /* EPPI0 Status Register */ +#define EPPI0_HCNT 0xFFC18004 /* EPPI0 Horizontal Transfer Count Register */ +#define EPPI0_HDLY 0xFFC18008 /* EPPI0 Horizontal Delay Count Register */ +#define EPPI0_VCNT 0xFFC1800C /* EPPI0 Vertical Transfer Count Register */ +#define EPPI0_VDLY 0xFFC18010 /* EPPI0 Vertical Delay Count Register */ +#define EPPI0_FRAME 0xFFC18014 /* EPPI0 Lines Per Frame Register */ +#define EPPI0_LINE 0xFFC18018 /* EPPI0 Samples Per Line Register */ +#define EPPI0_CLKDIV 0xFFC1801C /* EPPI0 Clock Divide Register */ +#define EPPI0_CTL 0xFFC18020 /* EPPI0 Control Register */ +#define EPPI0_FS1_WLHB 0xFFC18024 /* EPPI0 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */ +#define EPPI0_FS1_PASPL 0xFFC18028 /* EPPI0 FS1 Period Register / EPPI Active Samples Per Line Register */ +#define EPPI0_FS2_WLVB 0xFFC1802C /* EPPI0 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */ +#define EPPI0_FS2_PALPF 0xFFC18030 /* EPPI0 FS2 Period Register / EPPI Active Lines Per Field Register */ +#define EPPI0_IMSK 0xFFC18034 /* EPPI0 Interrupt Mask Register */ +#define EPPI0_ODDCLIP 0xFFC1803C /* EPPI0 Clipping Register for ODD (Chroma) Data */ +#define EPPI0_EVENCLIP 0xFFC18040 /* EPPI0 Clipping Register for EVEN (Luma) Data */ +#define EPPI0_FS1_DLY 0xFFC18044 /* EPPI0 Frame Sync 1 Delay Value */ +#define EPPI0_FS2_DLY 0xFFC18048 /* EPPI0 Frame Sync 2 Delay Value */ +#define EPPI0_CTL2 0xFFC1804C /* EPPI0 Control Register 2 */ + +/* ========================= + EPPI1 + ========================= */ +#define EPPI1_STAT 0xFFC18400 /* EPPI1 Status Register */ +#define EPPI1_HCNT 0xFFC18404 /* EPPI1 Horizontal Transfer Count Register */ +#define EPPI1_HDLY 0xFFC18408 /* EPPI1 Horizontal Delay Count Register */ +#define EPPI1_VCNT 0xFFC1840C /* EPPI1 Vertical Transfer Count Register */ +#define EPPI1_VDLY 0xFFC18410 /* EPPI1 Vertical Delay Count Register */ +#define EPPI1_FRAME 0xFFC18414 /* EPPI1 Lines Per Frame Register */ +#define EPPI1_LINE 0xFFC18418 /* EPPI1 Samples Per Line Register */ +#define EPPI1_CLKDIV 0xFFC1841C /* EPPI1 Clock Divide Register */ +#define EPPI1_CTL 0xFFC18420 /* EPPI1 Control Register */ +#define EPPI1_FS1_WLHB 0xFFC18424 /* EPPI1 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */ +#define EPPI1_FS1_PASPL 0xFFC18428 /* EPPI1 FS1 Period Register / EPPI Active Samples Per Line Register */ +#define EPPI1_FS2_WLVB 0xFFC1842C /* EPPI1 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */ +#define EPPI1_FS2_PALPF 0xFFC18430 /* EPPI1 FS2 Period Register / EPPI Active Lines Per Field Register */ +#define EPPI1_IMSK 0xFFC18434 /* EPPI1 Interrupt Mask Register */ +#define EPPI1_ODDCLIP 0xFFC1843C /* EPPI1 Clipping Register for ODD (Chroma) Data */ +#define EPPI1_EVENCLIP 0xFFC18440 /* EPPI1 Clipping Register for EVEN (Luma) Data */ +#define EPPI1_FS1_DLY 0xFFC18444 /* EPPI1 Frame Sync 1 Delay Value */ +#define EPPI1_FS2_DLY 0xFFC18448 /* EPPI1 Frame Sync 2 Delay Value */ +#define EPPI1_CTL2 0xFFC1844C /* EPPI1 Control Register 2 */ + +/* ========================= + EPPI2 + ========================= */ +#define EPPI2_STAT 0xFFC18800 /* EPPI2 Status Register */ +#define EPPI2_HCNT 0xFFC18804 /* EPPI2 Horizontal Transfer Count Register */ +#define EPPI2_HDLY 0xFFC18808 /* EPPI2 Horizontal Delay Count Register */ +#define EPPI2_VCNT 0xFFC1880C /* EPPI2 Vertical Transfer Count Register */ +#define EPPI2_VDLY 0xFFC18810 /* EPPI2 Vertical Delay Count Register */ +#define EPPI2_FRAME 0xFFC18814 /* EPPI2 Lines Per Frame Register */ +#define EPPI2_LINE 0xFFC18818 /* EPPI2 Samples Per Line Register */ +#define EPPI2_CLKDIV 0xFFC1881C /* EPPI2 Clock Divide Register */ +#define EPPI2_CTL 0xFFC18820 /* EPPI2 Control Register */ +#define EPPI2_FS1_WLHB 0xFFC18824 /* EPPI2 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */ +#define EPPI2_FS1_PASPL 0xFFC18828 /* EPPI2 FS1 Period Register / EPPI Active Samples Per Line Register */ +#define EPPI2_FS2_WLVB 0xFFC1882C /* EPPI2 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */ +#define EPPI2_FS2_PALPF 0xFFC18830 /* EPPI2 FS2 Period Register / EPPI Active Lines Per Field Register */ +#define EPPI2_IMSK 0xFFC18834 /* EPPI2 Interrupt Mask Register */ +#define EPPI2_ODDCLIP 0xFFC1883C /* EPPI2 Clipping Register for ODD (Chroma) Data */ +#define EPPI2_EVENCLIP 0xFFC18840 /* EPPI2 Clipping Register for EVEN (Luma) Data */ +#define EPPI2_FS1_DLY 0xFFC18844 /* EPPI2 Frame Sync 1 Delay Value */ +#define EPPI2_FS2_DLY 0xFFC18848 /* EPPI2 Frame Sync 2 Delay Value */ +#define EPPI2_CTL2 0xFFC1884C /* EPPI2 Control Register 2 */ + + + +/* ========================= + DDE Registers + ========================= */ + +/* ========================= + DMA0 + ========================= */ +#define DMA0_NEXT_DESC_PTR 0xFFC41000 /* DMA0 Pointer to Next Initial Descriptor */ +#define DMA0_START_ADDR 0xFFC41004 /* DMA0 Start Address of Current Buffer */ +#define DMA0_CONFIG 0xFFC41008 /* DMA0 Configuration Register */ +#define DMA0_X_COUNT 0xFFC4100C /* DMA0 Inner Loop Count Start Value */ +#define DMA0_X_MODIFY 0xFFC41010 /* DMA0 Inner Loop Address Increment */ +#define DMA0_Y_COUNT 0xFFC41014 /* DMA0 Outer Loop Count Start Value (2D only) */ +#define DMA0_Y_MODIFY 0xFFC41018 /* DMA0 Outer Loop Address Increment (2D only) */ +#define DMA0_CURR_DESC_PTR 0xFFC41024 /* DMA0 Current Descriptor Pointer */ +#define DMA0_PREV_DESC_PTR 0xFFC41028 /* DMA0 Previous Initial Descriptor Pointer */ +#define DMA0_CURR_ADDR 0xFFC4102C /* DMA0 Current Address */ +#define DMA0_IRQ_STATUS 0xFFC41030 /* DMA0 Status Register */ +#define DMA0_CURR_X_COUNT 0xFFC41034 /* DMA0 Current Count(1D) or intra-row XCNT (2D) */ +#define DMA0_CURR_Y_COUNT 0xFFC41038 /* DMA0 Current Row Count (2D only) */ +#define DMA0_BWL_COUNT 0xFFC41040 /* DMA0 Bandwidth Limit Count */ +#define DMA0_CURR_BWL_COUNT 0xFFC41044 /* DMA0 Bandwidth Limit Count Current */ +#define DMA0_BWM_COUNT 0xFFC41048 /* DMA0 Bandwidth Monitor Count */ +#define DMA0_CURR_BWM_COUNT 0xFFC4104C /* DMA0 Bandwidth Monitor Count Current */ + +/* ========================= + DMA1 + ========================= */ +#define DMA1_NEXT_DESC_PTR 0xFFC41080 /* DMA1 Pointer to Next Initial Descriptor */ +#define DMA1_START_ADDR 0xFFC41084 /* DMA1 Start Address of Current Buffer */ +#define DMA1_CONFIG 0xFFC41088 /* DMA1 Configuration Register */ +#define DMA1_X_COUNT 0xFFC4108C /* DMA1 Inner Loop Count Start Value */ +#define DMA1_X_MODIFY 0xFFC41090 /* DMA1 Inner Loop Address Increment */ +#define DMA1_Y_COUNT 0xFFC41094 /* DMA1 Outer Loop Count Start Value (2D only) */ +#define DMA1_Y_MODIFY 0xFFC41098 /* DMA1 Outer Loop Address Increment (2D only) */ +#define DMA1_CURR_DESC_PTR 0xFFC410A4 /* DMA1 Current Descriptor Pointer */ +#define DMA1_PREV_DESC_PTR 0xFFC410A8 /* DMA1 Previous Initial Descriptor Pointer */ +#define DMA1_CURR_ADDR 0xFFC410AC /* DMA1 Current Address */ +#define DMA1_IRQ_STATUS 0xFFC410B0 /* DMA1 Status Register */ +#define DMA1_CURR_X_COUNT 0xFFC410B4 /* DMA1 Current Count(1D) or intra-row XCNT (2D) */ +#define DMA1_CURR_Y_COUNT 0xFFC410B8 /* DMA1 Current Row Count (2D only) */ +#define DMA1_BWL_COUNT 0xFFC410C0 /* DMA1 Bandwidth Limit Count */ +#define DMA1_CURR_BWL_COUNT 0xFFC410C4 /* DMA1 Bandwidth Limit Count Current */ +#define DMA1_BWM_COUNT 0xFFC410C8 /* DMA1 Bandwidth Monitor Count */ +#define DMA1_CURR_BWM_COUNT 0xFFC410CC /* DMA1 Bandwidth Monitor Count Current */ + +/* ========================= + DMA2 + ========================= */ +#define DMA2_NEXT_DESC_PTR 0xFFC41100 /* DMA2 Pointer to Next Initial Descriptor */ +#define DMA2_START_ADDR 0xFFC41104 /* DMA2 Start Address of Current Buffer */ +#define DMA2_CONFIG 0xFFC41108 /* DMA2 Configuration Register */ +#define DMA2_X_COUNT 0xFFC4110C /* DMA2 Inner Loop Count Start Value */ +#define DMA2_X_MODIFY 0xFFC41110 /* DMA2 Inner Loop Address Increment */ +#define DMA2_Y_COUNT 0xFFC41114 /* DMA2 Outer Loop Count Start Value (2D only) */ +#define DMA2_Y_MODIFY 0xFFC41118 /* DMA2 Outer Loop Address Increment (2D only) */ +#define DMA2_CURR_DESC_PTR 0xFFC41124 /* DMA2 Current Descriptor Pointer */ +#define DMA2_PREV_DESC_PTR 0xFFC41128 /* DMA2 Previous Initial Descriptor Pointer */ +#define DMA2_CURR_ADDR 0xFFC4112C /* DMA2 Current Address */ +#define DMA2_IRQ_STATUS 0xFFC41130 /* DMA2 Status Register */ +#define DMA2_CURR_X_COUNT 0xFFC41134 /* DMA2 Current Count(1D) or intra-row XCNT (2D) */ +#define DMA2_CURR_Y_COUNT 0xFFC41138 /* DMA2 Current Row Count (2D only) */ +#define DMA2_BWL_COUNT 0xFFC41140 /* DMA2 Bandwidth Limit Count */ +#define DMA2_CURR_BWL_COUNT 0xFFC41144 /* DMA2 Bandwidth Limit Count Current */ +#define DMA2_BWM_COUNT 0xFFC41148 /* DMA2 Bandwidth Monitor Count */ +#define DMA2_CURR_BWM_COUNT 0xFFC4114C /* DMA2 Bandwidth Monitor Count Current */ + +/* ========================= + DMA3 + ========================= */ +#define DMA3_NEXT_DESC_PTR 0xFFC41180 /* DMA3 Pointer to Next Initial Descriptor */ +#define DMA3_START_ADDR 0xFFC41184 /* DMA3 Start Address of Current Buffer */ +#define DMA3_CONFIG 0xFFC41188 /* DMA3 Configuration Register */ +#define DMA3_X_COUNT 0xFFC4118C /* DMA3 Inner Loop Count Start Value */ +#define DMA3_X_MODIFY 0xFFC41190 /* DMA3 Inner Loop Address Increment */ +#define DMA3_Y_COUNT 0xFFC41194 /* DMA3 Outer Loop Count Start Value (2D only) */ +#define DMA3_Y_MODIFY 0xFFC41198 /* DMA3 Outer Loop Address Increment (2D only) */ +#define DMA3_CURR_DESC_PTR 0xFFC411A4 /* DMA3 Current Descriptor Pointer */ +#define DMA3_PREV_DESC_PTR 0xFFC411A8 /* DMA3 Previous Initial Descriptor Pointer */ +#define DMA3_CURR_ADDR 0xFFC411AC /* DMA3 Current Address */ +#define DMA3_IRQ_STATUS 0xFFC411B0 /* DMA3 Status Register */ +#define DMA3_CURR_X_COUNT 0xFFC411B4 /* DMA3 Current Count(1D) or intra-row XCNT (2D) */ +#define DMA3_CURR_Y_COUNT 0xFFC411B8 /* DMA3 Current Row Count (2D only) */ +#define DMA3_BWL_COUNT 0xFFC411C0 /* DMA3 Bandwidth Limit Count */ +#define DMA3_CURR_BWL_COUNT 0xFFC411C4 /* DMA3 Bandwidth Limit Count Current */ +#define DMA3_BWM_COUNT 0xFFC411C8 /* DMA3 Bandwidth Monitor Count */ +#define DMA3_CURR_BWM_COUNT 0xFFC411CC /* DMA3 Bandwidth Monitor Count Current */ + +/* ========================= + DMA4 + ========================= */ +#define DMA4_NEXT_DESC_PTR 0xFFC41200 /* DMA4 Pointer to Next Initial Descriptor */ +#define DMA4_START_ADDR 0xFFC41204 /* DMA4 Start Address of Current Buffer */ +#define DMA4_CONFIG 0xFFC41208 /* DMA4 Configuration Register */ +#define DMA4_X_COUNT 0xFFC4120C /* DMA4 Inner Loop Count Start Value */ +#define DMA4_X_MODIFY 0xFFC41210 /* DMA4 Inner Loop Address Increment */ +#define DMA4_Y_COUNT 0xFFC41214 /* DMA4 Outer Loop Count Start Value (2D only) */ +#define DMA4_Y_MODIFY 0xFFC41218 /* DMA4 Outer Loop Address Increment (2D only) */ +#define DMA4_CURR_DESC_PTR 0xFFC41224 /* DMA4 Current Descriptor Pointer */ +#define DMA4_PREV_DESC_PTR 0xFFC41228 /* DMA4 Previous Initial Descriptor Pointer */ +#define DMA4_CURR_ADDR 0xFFC4122C /* DMA4 Current Address */ +#define DMA4_IRQ_STATUS 0xFFC41230 /* DMA4 Status Register */ +#define DMA4_CURR_X_COUNT 0xFFC41234 /* DMA4 Current Count(1D) or intra-row XCNT (2D) */ +#define DMA4_CURR_Y_COUNT 0xFFC41238 /* DMA4 Current Row Count (2D only) */ +#define DMA4_BWL_COUNT 0xFFC41240 /* DMA4 Bandwidth Limit Count */ +#define DMA4_CURR_BWL_COUNT 0xFFC41244 /* DMA4 Bandwidth Limit Count Current */ +#define DMA4_BWM_COUNT 0xFFC41248 /* DMA4 Bandwidth Monitor Count */ +#define DMA4_CURR_BWM_COUNT 0xFFC4124C /* DMA4 Bandwidth Monitor Count Current */ + +/* ========================= + DMA5 + ========================= */ +#define DMA5_NEXT_DESC_PTR 0xFFC41280 /* DMA5 Pointer to Next Initial Descriptor */ +#define DMA5_START_ADDR 0xFFC41284 /* DMA5 Start Address of Current Buffer */ +#define DMA5_CONFIG 0xFFC41288 /* DMA5 Configuration Register */ +#define DMA5_X_COUNT 0xFFC4128C /* DMA5 Inner Loop Count Start Value */ +#define DMA5_X_MODIFY 0xFFC41290 /* DMA5 Inner Loop Address Increment */ +#define DMA5_Y_COUNT 0xFFC41294 /* DMA5 Outer Loop Count Start Value (2D only) */ +#define DMA5_Y_MODIFY 0xFFC41298 /* DMA5 Outer Loop Address Increment (2D only) */ +#define DMA5_CURR_DESC_PTR 0xFFC412A4 /* DMA5 Current Descriptor Pointer */ +#define DMA5_PREV_DESC_PTR 0xFFC412A8 /* DMA5 Previous Initial Descriptor Pointer */ +#define DMA5_CURR_ADDR 0xFFC412AC /* DMA5 Current Address */ +#define DMA5_IRQ_STATUS 0xFFC412B0 /* DMA5 Status Register */ +#define DMA5_CURR_X_COUNT 0xFFC412B4 /* DMA5 Current Count(1D) or intra-row XCNT (2D) */ +#define DMA5_CURR_Y_COUNT 0xFFC412B8 /* DMA5 Current Row Count (2D only) */ +#define DMA5_BWL_COUNT 0xFFC412C0 /* DMA5 Bandwidth Limit Count */ +#define DMA5_CURR_BWL_COUNT 0xFFC412C4 /* DMA5 Bandwidth Limit Count Current */ +#define DMA5_BWM_COUNT 0xFFC412C8 /* DMA5 Bandwidth Monitor Count */ +#define DMA5_CURR_BWM_COUNT 0xFFC412CC /* DMA5 Bandwidth Monitor Count Current */ + +/* ========================= + DMA6 + ========================= */ +#define DMA6_NEXT_DESC_PTR 0xFFC41300 /* DMA6 Pointer to Next Initial Descriptor */ +#define DMA6_START_ADDR 0xFFC41304 /* DMA6 Start Address of Current Buffer */ +#define DMA6_CONFIG 0xFFC41308 /* DMA6 Configuration Register */ +#define DMA6_X_COUNT 0xFFC4130C /* DMA6 Inner Loop Count Start Value */ +#define DMA6_X_MODIFY 0xFFC41310 /* DMA6 Inner Loop Address Increment */ +#define DMA6_Y_COUNT 0xFFC41314 /* DMA6 Outer Loop Count Start Value (2D only) */ +#define DMA6_Y_MODIFY 0xFFC41318 /* DMA6 Outer Loop Address Increment (2D only) */ +#define DMA6_CURR_DESC_PTR 0xFFC41324 /* DMA6 Current Descriptor Pointer */ +#define DMA6_PREV_DESC_PTR 0xFFC41328 /* DMA6 Previous Initial Descriptor Pointer */ +#define DMA6_CURR_ADDR 0xFFC4132C /* DMA6 Current Address */ +#define DMA6_IRQ_STATUS 0xFFC41330 /* DMA6 Status Register */ +#define DMA6_CURR_X_COUNT 0xFFC41334 /* DMA6 Current Count(1D) or intra-row XCNT (2D) */ +#define DMA6_CURR_Y_COUNT 0xFFC41338 /* DMA6 Current Row Count (2D only) */ +#define DMA6_BWL_COUNT 0xFFC41340 /* DMA6 Bandwidth Limit Count */ +#define DMA6_CURR_BWL_COUNT 0xFFC41344 /* DMA6 Bandwidth Limit Count Current */ +#define DMA6_BWM_COUNT 0xFFC41348 /* DMA6 Bandwidth Monitor Count */ +#define DMA6_CURR_BWM_COUNT 0xFFC4134C /* DMA6 Bandwidth Monitor Count Current */ + +/* ========================= + DMA7 + ========================= */ +#define DMA7_NEXT_DESC_PTR 0xFFC41380 /* DMA7 Pointer to Next Initial Descriptor */ +#define DMA7_START_ADDR 0xFFC41384 /* DMA7 Start Address of Current Buffer */ +#define DMA7_CONFIG 0xFFC41388 /* DMA7 Configuration Register */ +#define DMA7_X_COUNT 0xFFC4138C /* DMA7 Inner Loop Count Start Value */ +#define DMA7_X_MODIFY 0xFFC41390 /* DMA7 Inner Loop Address Increment */ +#define DMA7_Y_COUNT 0xFFC41394 /* DMA7 Outer Loop Count Start Value (2D only) */ +#define DMA7_Y_MODIFY 0xFFC41398 /* DMA7 Outer Loop Address Increment (2D only) */ +#define DMA7_CURR_DESC_PTR 0xFFC413A4 /* DMA7 Current Descriptor Pointer */ +#define DMA7_PREV_DESC_PTR 0xFFC413A8 /* DMA7 Previous Initial Descriptor Pointer */ +#define DMA7_CURR_ADDR 0xFFC413AC /* DMA7 Current Address */ +#define DMA7_IRQ_STATUS 0xFFC413B0 /* DMA7 Status Register */ +#define DMA7_CURR_X_COUNT 0xFFC413B4 /* DMA7 Current Count(1D) or intra-row XCNT (2D) */ +#define DMA7_CURR_Y_COUNT 0xFFC413B8 /* DMA7 Current Row Count (2D only) */ +#define DMA7_BWL_COUNT 0xFFC413C0 /* DMA7 Bandwidth Limit Count */ +#define DMA7_CURR_BWL_COUNT 0xFFC413C4 /* DMA7 Bandwidth Limit Count Current */ +#define DMA7_BWM_COUNT 0xFFC413C8 /* DMA7 Bandwidth Monitor Count */ +#define DMA7_CURR_BWM_COUNT 0xFFC413CC /* DMA7 Bandwidth Monitor Count Current */ + +/* ========================= + DMA8 + ========================= */ +#define DMA8_NEXT_DESC_PTR 0xFFC41400 /* DMA8 Pointer to Next Initial Descriptor */ +#define DMA8_START_ADDR 0xFFC41404 /* DMA8 Start Address of Current Buffer */ +#define DMA8_CONFIG 0xFFC41408 /* DMA8 Configuration Register */ +#define DMA8_X_COUNT 0xFFC4140C /* DMA8 Inner Loop Count Start Value */ +#define DMA8_X_MODIFY 0xFFC41410 /* DMA8 Inner Loop Address Increment */ +#define DMA8_Y_COUNT 0xFFC41414 /* DMA8 Outer Loop Count Start Value (2D only) */ +#define DMA8_Y_MODIFY 0xFFC41418 /* DMA8 Outer Loop Address Increment (2D only) */ +#define DMA8_CURR_DESC_PTR 0xFFC41424 /* DMA8 Current Descriptor Pointer */ +#define DMA8_PREV_DESC_PTR 0xFFC41428 /* DMA8 Previous Initial Descriptor Pointer */ +#define DMA8_CURR_ADDR 0xFFC4142C /* DMA8 Current Address */ +#define DMA8_IRQ_STATUS 0xFFC41430 /* DMA8 Status Register */ +#define DMA8_CURR_X_COUNT 0xFFC41434 /* DMA8 Current Count(1D) or intra-row XCNT (2D) */ +#define DMA8_CURR_Y_COUNT 0xFFC41438 /* DMA8 Current Row Count (2D only) */ +#define DMA8_BWL_COUNT 0xFFC41440 /* DMA8 Bandwidth Limit Count */ +#define DMA8_CURR_BWL_COUNT 0xFFC41444 /* DMA8 Bandwidth Limit Count Current */ +#define DMA8_BWM_COUNT 0xFFC41448 /* DMA8 Bandwidth Monitor Count */ +#define DMA8_CURR_BWM_COUNT 0xFFC4144C /* DMA8 Bandwidth Monitor Count Current */ + +/* ========================= + DMA9 + ========================= */ +#define DMA9_NEXT_DESC_PTR 0xFFC41480 /* DMA9 Pointer to Next Initial Descriptor */ +#define DMA9_START_ADDR 0xFFC41484 /* DMA9 Start Address of Current Buffer */ +#define DMA9_CONFIG 0xFFC41488 /* DMA9 Configuration Register */ +#define DMA9_X_COUNT 0xFFC4148C /* DMA9 Inner Loop Count Start Value */ +#define DMA9_X_MODIFY 0xFFC41490 /* DMA9 Inner Loop Address Increment */ +#define DMA9_Y_COUNT 0xFFC41494 /* DMA9 Outer Loop Count Start Value (2D only) */ +#define DMA9_Y_MODIFY 0xFFC41498 /* DMA9 Outer Loop Address Increment (2D only) */ +#define DMA9_CURR_DESC_PTR 0xFFC414A4 /* DMA9 Current Descriptor Pointer */ +#define DMA9_PREV_DESC_PTR 0xFFC414A8 /* DMA9 Previous Initial Descriptor Pointer */ +#define DMA9_CURR_ADDR 0xFFC414AC /* DMA9 Current Address */ +#define DMA9_IRQ_STATUS 0xFFC414B0 /* DMA9 Status Register */ +#define DMA9_CURR_X_COUNT 0xFFC414B4 /* DMA9 Current Count(1D) or intra-row XCNT (2D) */ +#define DMA9_CURR_Y_COUNT 0xFFC414B8 /* DMA9 Current Row Count (2D only) */ +#define DMA9_BWL_COUNT 0xFFC414C0 /* DMA9 Bandwidth Limit Count */ +#define DMA9_CURR_BWL_COUNT 0xFFC414C4 /* DMA9 Bandwidth Limit Count Current */ +#define DMA9_BWM_COUNT 0xFFC414C8 /* DMA9 Bandwidth Monitor Count */ +#define DMA9_CURR_BWM_COUNT 0xFFC414CC /* DMA9 Bandwidth Monitor Count Current */ + +/* ========================= + DMA10 + ========================= */ +#define DMA10_NEXT_DESC_PTR 0xFFC05000 /* DMA10 Pointer to Next Initial Descriptor */ +#define DMA10_START_ADDR 0xFFC05004 /* DMA10 Start Address of Current Buffer */ +#define DMA10_CONFIG 0xFFC05008 /* DMA10 Configuration Register */ +#define DMA10_X_COUNT 0xFFC0500C /* DMA10 Inner Loop Count Start Value */ +#define DMA10_X_MODIFY 0xFFC05010 /* DMA10 Inner Loop Address Increment */ +#define DMA10_Y_COUNT 0xFFC05014 /* DMA10 Outer Loop Count Start Value (2D only) */ +#define DMA10_Y_MODIFY 0xFFC05018 /* DMA10 Outer Loop Address Increment (2D only) */ +#define DMA10_CURR_DESC_PTR 0xFFC05024 /* DMA10 Current Descriptor Pointer */ +#define DMA10_PREV_DESC_PTR 0xFFC05028 /* DMA10 Previous Initial Descriptor Pointer */ +#define DMA10_CURR_ADDR 0xFFC0502C /* DMA10 Current Address */ +#define DMA10_IRQ_STATUS 0xFFC05030 /* DMA10 Status Register */ +#define DMA10_CURR_X_COUNT 0xFFC05034 /* DMA10 Current Count(1D) or intra-row XCNT (2D) */ +#define DMA10_CURR_Y_COUNT 0xFFC05038 /* DMA10 Current Row Count (2D only) */ +#define DMA10_BWL_COUNT 0xFFC05040 /* DMA10 Bandwidth Limit Count */ +#define DMA10_CURR_BWL_COUNT 0xFFC05044 /* DMA10 Bandwidth Limit Count Current */ +#define DMA10_BWM_COUNT 0xFFC05048 /* DMA10 Bandwidth Monitor Count */ +#define DMA10_CURR_BWM_COUNT 0xFFC0504C /* DMA10 Bandwidth Monitor Count Current */ + +/* ========================= + DMA11 + ========================= */ +#define DMA11_NEXT_DESC_PTR 0xFFC05080 /* DMA11 Pointer to Next Initial Descriptor */ +#define DMA11_START_ADDR 0xFFC05084 /* DMA11 Start Address of Current Buffer */ +#define DMA11_CONFIG 0xFFC05088 /* DMA11 Configuration Register */ +#define DMA11_X_COUNT 0xFFC0508C /* DMA11 Inner Loop Count Start Value */ +#define DMA11_X_MODIFY 0xFFC05090 /* DMA11 Inner Loop Address Increment */ +#define DMA11_Y_COUNT 0xFFC05094 /* DMA11 Outer Loop Count Start Value (2D only) */ +#define DMA11_Y_MODIFY 0xFFC05098 /* DMA11 Outer Loop Address Increment (2D only) */ +#define DMA11_CURR_DESC_PTR 0xFFC050A4 /* DMA11 Current Descriptor Pointer */ +#define DMA11_PREV_DESC_PTR 0xFFC050A8 /* DMA11 Previous Initial Descriptor Pointer */ +#define DMA11_CURR_ADDR 0xFFC050AC /* DMA11 Current Address */ +#define DMA11_IRQ_STATUS 0xFFC050B0 /* DMA11 Status Register */ +#define DMA11_CURR_X_COUNT 0xFFC050B4 /* DMA11 Current Count(1D) or intra-row XCNT (2D) */ +#define DMA11_CURR_Y_COUNT 0xFFC050B8 /* DMA11 Current Row Count (2D only) */ +#define DMA11_BWL_COUNT 0xFFC050C0 /* DMA11 Bandwidth Limit Count */ +#define DMA11_CURR_BWL_COUNT 0xFFC050C4 /* DMA11 Bandwidth Limit Count Current */ +#define DMA11_BWM_COUNT 0xFFC050C8 /* DMA11 Bandwidth Monitor Count */ +#define DMA11_CURR_BWM_COUNT 0xFFC050CC /* DMA11 Bandwidth Monitor Count Current */ + +/* ========================= + DMA12 + ========================= */ +#define DMA12_NEXT_DESC_PTR 0xFFC05100 /* DMA12 Pointer to Next Initial Descriptor */ +#define DMA12_START_ADDR 0xFFC05104 /* DMA12 Start Address of Current Buffer */ +#define DMA12_CONFIG 0xFFC05108 /* DMA12 Configuration Register */ +#define DMA12_X_COUNT 0xFFC0510C /* DMA12 Inner Loop Count Start Value */ +#define DMA12_X_MODIFY 0xFFC05110 /* DMA12 Inner Loop Address Increment */ +#define DMA12_Y_COUNT 0xFFC05114 /* DMA12 Outer Loop Count Start Value (2D only) */ +#define DMA12_Y_MODIFY 0xFFC05118 /* DMA12 Outer Loop Address Increment (2D only) */ +#define DMA12_CURR_DESC_PTR 0xFFC05124 /* DMA12 Current Descriptor Pointer */ +#define DMA12_PREV_DESC_PTR 0xFFC05128 /* DMA12 Previous Initial Descriptor Pointer */ +#define DMA12_CURR_ADDR 0xFFC0512C /* DMA12 Current Address */ +#define DMA12_IRQ_STATUS 0xFFC05130 /* DMA12 Status Register */ +#define DMA12_CURR_X_COUNT 0xFFC05134 /* DMA12 Current Count(1D) or intra-row XCNT (2D) */ +#define DMA12_CURR_Y_COUNT 0xFFC05138 /* DMA12 Current Row Count (2D only) */ +#define DMA12_BWL_COUNT 0xFFC05140 /* DMA12 Bandwidth Limit Count */ +#define DMA12_CURR_BWL_COUNT 0xFFC05144 /* DMA12 Bandwidth Limit Count Current */ +#define DMA12_BWM_COUNT 0xFFC05148 /* DMA12 Bandwidth Monitor Count */ +#define DMA12_CURR_BWM_COUNT 0xFFC0514C /* DMA12 Bandwidth Monitor Count Current */ + +/* ========================= + DMA13 + ========================= */ +#define DMA13_NEXT_DESC_PTR 0xFFC07000 /* DMA13 Pointer to Next Initial Descriptor */ +#define DMA13_START_ADDR 0xFFC07004 /* DMA13 Start Address of Current Buffer */ +#define DMA13_CONFIG 0xFFC07008 /* DMA13 Configuration Register */ +#define DMA13_X_COUNT 0xFFC0700C /* DMA13 Inner Loop Count Start Value */ +#define DMA13_X_MODIFY 0xFFC07010 /* DMA13 Inner Loop Address Increment */ +#define DMA13_Y_COUNT 0xFFC07014 /* DMA13 Outer Loop Count Start Value (2D only) */ +#define DMA13_Y_MODIFY 0xFFC07018 /* DMA13 Outer Loop Address Increment (2D only) */ +#define DMA13_CURR_DESC_PTR 0xFFC07024 /* DMA13 Current Descriptor Pointer */ +#define DMA13_PREV_DESC_PTR 0xFFC07028 /* DMA13 Previous Initial Descriptor Pointer */ +#define DMA13_CURR_ADDR 0xFFC0702C /* DMA13 Current Address */ +#define DMA13_IRQ_STATUS 0xFFC07030 /* DMA13 Status Register */ +#define DMA13_CURR_X_COUNT 0xFFC07034 /* DMA13 Current Count(1D) or intra-row XCNT (2D) */ +#define DMA13_CURR_Y_COUNT 0xFFC07038 /* DMA13 Current Row Count (2D only) */ +#define DMA13_BWL_COUNT 0xFFC07040 /* DMA13 Bandwidth Limit Count */ +#define DMA13_CURR_BWL_COUNT 0xFFC07044 /* DMA13 Bandwidth Limit Count Current */ +#define DMA13_BWM_COUNT 0xFFC07048 /* DMA13 Bandwidth Monitor Count */ +#define DMA13_CURR_BWM_COUNT 0xFFC0704C /* DMA13 Bandwidth Monitor Count Current */ + +/* ========================= + DMA14 + ========================= */ +#define DMA14_NEXT_DESC_PTR 0xFFC07080 /* DMA14 Pointer to Next Initial Descriptor */ +#define DMA14_START_ADDR 0xFFC07084 /* DMA14 Start Address of Current Buffer */ +#define DMA14_CONFIG 0xFFC07088 /* DMA14 Configuration Register */ +#define DMA14_X_COUNT 0xFFC0708C /* DMA14 Inner Loop Count Start Value */ +#define DMA14_X_MODIFY 0xFFC07090 /* DMA14 Inner Loop Address Increment */ +#define DMA14_Y_COUNT 0xFFC07094 /* DMA14 Outer Loop Count Start Value (2D only) */ +#define DMA14_Y_MODIFY 0xFFC07098 /* DMA14 Outer Loop Address Increment (2D only) */ +#define DMA14_CURR_DESC_PTR 0xFFC070A4 /* DMA14 Current Descriptor Pointer */ +#define DMA14_PREV_DESC_PTR 0xFFC070A8 /* DMA14 Previous Initial Descriptor Pointer */ +#define DMA14_CURR_ADDR 0xFFC070AC /* DMA14 Current Address */ +#define DMA14_IRQ_STATUS 0xFFC070B0 /* DMA14 Status Register */ +#define DMA14_CURR_X_COUNT 0xFFC070B4 /* DMA14 Current Count(1D) or intra-row XCNT (2D) */ +#define DMA14_CURR_Y_COUNT 0xFFC070B8 /* DMA14 Current Row Count (2D only) */ +#define DMA14_BWL_COUNT 0xFFC070C0 /* DMA14 Bandwidth Limit Count */ +#define DMA14_CURR_BWL_COUNT 0xFFC070C4 /* DMA14 Bandwidth Limit Count Current */ +#define DMA14_BWM_COUNT 0xFFC070C8 /* DMA14 Bandwidth Monitor Count */ +#define DMA14_CURR_BWM_COUNT 0xFFC070CC /* DMA14 Bandwidth Monitor Count Current */ + +/* ========================= + DMA15 + ========================= */ +#define DMA15_NEXT_DESC_PTR 0xFFC07100 /* DMA15 Pointer to Next Initial Descriptor */ +#define DMA15_START_ADDR 0xFFC07104 /* DMA15 Start Address of Current Buffer */ +#define DMA15_CONFIG 0xFFC07108 /* DMA15 Configuration Register */ +#define DMA15_X_COUNT 0xFFC0710C /* DMA15 Inner Loop Count Start Value */ +#define DMA15_X_MODIFY 0xFFC07110 /* DMA15 Inner Loop Address Increment */ +#define DMA15_Y_COUNT 0xFFC07114 /* DMA15 Outer Loop Count Start Value (2D only) */ +#define DMA15_Y_MODIFY 0xFFC07118 /* DMA15 Outer Loop Address Increment (2D only) */ +#define DMA15_CURR_DESC_PTR 0xFFC07124 /* DMA15 Current Descriptor Pointer */ +#define DMA15_PREV_DESC_PTR 0xFFC07128 /* DMA15 Previous Initial Descriptor Pointer */ +#define DMA15_CURR_ADDR 0xFFC0712C /* DMA15 Current Address */ +#define DMA15_IRQ_STATUS 0xFFC07130 /* DMA15 Status Register */ +#define DMA15_CURR_X_COUNT 0xFFC07134 /* DMA15 Current Count(1D) or intra-row XCNT (2D) */ +#define DMA15_CURR_Y_COUNT 0xFFC07138 /* DMA15 Current Row Count (2D only) */ +#define DMA15_BWL_COUNT 0xFFC07140 /* DMA15 Bandwidth Limit Count */ +#define DMA15_CURR_BWL_COUNT 0xFFC07144 /* DMA15 Bandwidth Limit Count Current */ +#define DMA15_BWM_COUNT 0xFFC07148 /* DMA15 Bandwidth Monitor Count */ +#define DMA15_CURR_BWM_COUNT 0xFFC0714C /* DMA15 Bandwidth Monitor Count Current */ + +/* ========================= + DMA16 + ========================= */ +#define DMA16_NEXT_DESC_PTR 0xFFC07180 /* DMA16 Pointer to Next Initial Descriptor */ +#define DMA16_START_ADDR 0xFFC07184 /* DMA16 Start Address of Current Buffer */ +#define DMA16_CONFIG 0xFFC07188 /* DMA16 Configuration Register */ +#define DMA16_X_COUNT 0xFFC0718C /* DMA16 Inner Loop Count Start Value */ +#define DMA16_X_MODIFY 0xFFC07190 /* DMA16 Inner Loop Address Increment */ +#define DMA16_Y_COUNT 0xFFC07194 /* DMA16 Outer Loop Count Start Value (2D only) */ +#define DMA16_Y_MODIFY 0xFFC07198 /* DMA16 Outer Loop Address Increment (2D only) */ +#define DMA16_CURR_DESC_PTR 0xFFC071A4 /* DMA16 Current Descriptor Pointer */ +#define DMA16_PREV_DESC_PTR 0xFFC071A8 /* DMA16 Previous Initial Descriptor Pointer */ +#define DMA16_CURR_ADDR 0xFFC071AC /* DMA16 Current Address */ +#define DMA16_IRQ_STATUS 0xFFC071B0 /* DMA16 Status Register */ +#define DMA16_CURR_X_COUNT 0xFFC071B4 /* DMA16 Current Count(1D) or intra-row XCNT (2D) */ +#define DMA16_CURR_Y_COUNT 0xFFC071B8 /* DMA16 Current Row Count (2D only) */ +#define DMA16_BWL_COUNT 0xFFC071C0 /* DMA16 Bandwidth Limit Count */ +#define DMA16_CURR_BWL_COUNT 0xFFC071C4 /* DMA16 Bandwidth Limit Count Current */ +#define DMA16_BWM_COUNT 0xFFC071C8 /* DMA16 Bandwidth Monitor Count */ +#define DMA16_CURR_BWM_COUNT 0xFFC071CC /* DMA16 Bandwidth Monitor Count Current */ + +/* ========================= + DMA17 + ========================= */ +#define DMA17_NEXT_DESC_PTR 0xFFC07200 /* DMA17 Pointer to Next Initial Descriptor */ +#define DMA17_START_ADDR 0xFFC07204 /* DMA17 Start Address of Current Buffer */ +#define DMA17_CONFIG 0xFFC07208 /* DMA17 Configuration Register */ +#define DMA17_X_COUNT 0xFFC0720C /* DMA17 Inner Loop Count Start Value */ +#define DMA17_X_MODIFY 0xFFC07210 /* DMA17 Inner Loop Address Increment */ +#define DMA17_Y_COUNT 0xFFC07214 /* DMA17 Outer Loop Count Start Value (2D only) */ +#define DMA17_Y_MODIFY 0xFFC07218 /* DMA17 Outer Loop Address Increment (2D only) */ +#define DMA17_CURR_DESC_PTR 0xFFC07224 /* DMA17 Current Descriptor Pointer */ +#define DMA17_PREV_DESC_PTR 0xFFC07228 /* DMA17 Previous Initial Descriptor Pointer */ +#define DMA17_CURR_ADDR 0xFFC0722C /* DMA17 Current Address */ +#define DMA17_IRQ_STATUS 0xFFC07230 /* DMA17 Status Register */ +#define DMA17_CURR_X_COUNT 0xFFC07234 /* DMA17 Current Count(1D) or intra-row XCNT (2D) */ +#define DMA17_CURR_Y_COUNT 0xFFC07238 /* DMA17 Current Row Count (2D only) */ +#define DMA17_BWL_COUNT 0xFFC07240 /* DMA17 Bandwidth Limit Count */ +#define DMA17_CURR_BWL_COUNT 0xFFC07244 /* DMA17 Bandwidth Limit Count Current */ +#define DMA17_BWM_COUNT 0xFFC07248 /* DMA17 Bandwidth Monitor Count */ +#define DMA17_CURR_BWM_COUNT 0xFFC0724C /* DMA17 Bandwidth Monitor Count Current */ + +/* ========================= + DMA18 + ========================= */ +#define DMA18_NEXT_DESC_PTR 0xFFC07280 /* DMA18 Pointer to Next Initial Descriptor */ +#define DMA18_START_ADDR 0xFFC07284 /* DMA18 Start Address of Current Buffer */ +#define DMA18_CONFIG 0xFFC07288 /* DMA18 Configuration Register */ +#define DMA18_X_COUNT 0xFFC0728C /* DMA18 Inner Loop Count Start Value */ +#define DMA18_X_MODIFY 0xFFC07290 /* DMA18 Inner Loop Address Increment */ +#define DMA18_Y_COUNT 0xFFC07294 /* DMA18 Outer Loop Count Start Value (2D only) */ +#define DMA18_Y_MODIFY 0xFFC07298 /* DMA18 Outer Loop Address Increment (2D only) */ +#define DMA18_CURR_DESC_PTR 0xFFC072A4 /* DMA18 Current Descriptor Pointer */ +#define DMA18_PREV_DESC_PTR 0xFFC072A8 /* DMA18 Previous Initial Descriptor Pointer */ +#define DMA18_CURR_ADDR 0xFFC072AC /* DMA18 Current Address */ +#define DMA18_IRQ_STATUS 0xFFC072B0 /* DMA18 Status Register */ +#define DMA18_CURR_X_COUNT 0xFFC072B4 /* DMA18 Current Count(1D) or intra-row XCNT (2D) */ +#define DMA18_CURR_Y_COUNT 0xFFC072B8 /* DMA18 Current Row Count (2D only) */ +#define DMA18_BWL_COUNT 0xFFC072C0 /* DMA18 Bandwidth Limit Count */ +#define DMA18_CURR_BWL_COUNT 0xFFC072C4 /* DMA18 Bandwidth Limit Count Current */ +#define DMA18_BWM_COUNT 0xFFC072C8 /* DMA18 Bandwidth Monitor Count */ +#define DMA18_CURR_BWM_COUNT 0xFFC072CC /* DMA18 Bandwidth Monitor Count Current */ + +/* ========================= + DMA19 + ========================= */ +#define DMA19_NEXT_DESC_PTR 0xFFC07300 /* DMA19 Pointer to Next Initial Descriptor */ +#define DMA19_START_ADDR 0xFFC07304 /* DMA19 Start Address of Current Buffer */ +#define DMA19_CONFIG 0xFFC07308 /* DMA19 Configuration Register */ +#define DMA19_X_COUNT 0xFFC0730C /* DMA19 Inner Loop Count Start Value */ +#define DMA19_X_MODIFY 0xFFC07310 /* DMA19 Inner Loop Address Increment */ +#define DMA19_Y_COUNT 0xFFC07314 /* DMA19 Outer Loop Count Start Value (2D only) */ +#define DMA19_Y_MODIFY 0xFFC07318 /* DMA19 Outer Loop Address Increment (2D only) */ +#define DMA19_CURR_DESC_PTR 0xFFC07324 /* DMA19 Current Descriptor Pointer */ +#define DMA19_PREV_DESC_PTR 0xFFC07328 /* DMA19 Previous Initial Descriptor Pointer */ +#define DMA19_CURR_ADDR 0xFFC0732C /* DMA19 Current Address */ +#define DMA19_IRQ_STATUS 0xFFC07330 /* DMA19 Status Register */ +#define DMA19_CURR_X_COUNT 0xFFC07334 /* DMA19 Current Count(1D) or intra-row XCNT (2D) */ +#define DMA19_CURR_Y_COUNT 0xFFC07338 /* DMA19 Current Row Count (2D only) */ +#define DMA19_BWL_COUNT 0xFFC07340 /* DMA19 Bandwidth Limit Count */ +#define DMA19_CURR_BWL_COUNT 0xFFC07344 /* DMA19 Bandwidth Limit Count Current */ +#define DMA19_BWM_COUNT 0xFFC07348 /* DMA19 Bandwidth Monitor Count */ +#define DMA19_CURR_BWM_COUNT 0xFFC0734C /* DMA19 Bandwidth Monitor Count Current */ + +/* ========================= + DMA20 + ========================= */ +#define DMA20_NEXT_DESC_PTR 0xFFC07380 /* DMA20 Pointer to Next Initial Descriptor */ +#define DMA20_START_ADDR 0xFFC07384 /* DMA20 Start Address of Current Buffer */ +#define DMA20_CONFIG 0xFFC07388 /* DMA20 Configuration Register */ +#define DMA20_X_COUNT 0xFFC0738C /* DMA20 Inner Loop Count Start Value */ +#define DMA20_X_MODIFY 0xFFC07390 /* DMA20 Inner Loop Address Increment */ +#define DMA20_Y_COUNT 0xFFC07394 /* DMA20 Outer Loop Count Start Value (2D only) */ +#define DMA20_Y_MODIFY 0xFFC07398 /* DMA20 Outer Loop Address Increment (2D only) */ +#define DMA20_CURR_DESC_PTR 0xFFC073A4 /* DMA20 Current Descriptor Pointer */ +#define DMA20_PREV_DESC_PTR 0xFFC073A8 /* DMA20 Previous Initial Descriptor Pointer */ +#define DMA20_CURR_ADDR 0xFFC073AC /* DMA20 Current Address */ +#define DMA20_IRQ_STATUS 0xFFC073B0 /* DMA20 Status Register */ +#define DMA20_CURR_X_COUNT 0xFFC073B4 /* DMA20 Current Count(1D) or intra-row XCNT (2D) */ +#define DMA20_CURR_Y_COUNT 0xFFC073B8 /* DMA20 Current Row Count (2D only) */ +#define DMA20_BWL_COUNT 0xFFC073C0 /* DMA20 Bandwidth Limit Count */ +#define DMA20_CURR_BWL_COUNT 0xFFC073C4 /* DMA20 Bandwidth Limit Count Current */ +#define DMA20_BWM_COUNT 0xFFC073C8 /* DMA20 Bandwidth Monitor Count */ +#define DMA20_CURR_BWM_COUNT 0xFFC073CC /* DMA20 Bandwidth Monitor Count Current */ + +/* ========================= + DMA21 + ========================= */ +#define DMA21_NEXT_DESC_PTR 0xFFC09000 /* DMA21 Pointer to Next Initial Descriptor */ +#define DMA21_START_ADDR 0xFFC09004 /* DMA21 Start Address of Current Buffer */ +#define DMA21_CONFIG 0xFFC09008 /* DMA21 Configuration Register */ +#define DMA21_X_COUNT 0xFFC0900C /* DMA21 Inner Loop Count Start Value */ +#define DMA21_X_MODIFY 0xFFC09010 /* DMA21 Inner Loop Address Increment */ +#define DMA21_Y_COUNT 0xFFC09014 /* DMA21 Outer Loop Count Start Value (2D only) */ +#define DMA21_Y_MODIFY 0xFFC09018 /* DMA21 Outer Loop Address Increment (2D only) */ +#define DMA21_CURR_DESC_PTR 0xFFC09024 /* DMA21 Current Descriptor Pointer */ +#define DMA21_PREV_DESC_PTR 0xFFC09028 /* DMA21 Previous Initial Descriptor Pointer */ +#define DMA21_CURR_ADDR 0xFFC0902C /* DMA21 Current Address */ +#define DMA21_IRQ_STATUS 0xFFC09030 /* DMA21 Status Register */ +#define DMA21_CURR_X_COUNT 0xFFC09034 /* DMA21 Current Count(1D) or intra-row XCNT (2D) */ +#define DMA21_CURR_Y_COUNT 0xFFC09038 /* DMA21 Current Row Count (2D only) */ +#define DMA21_BWL_COUNT 0xFFC09040 /* DMA21 Bandwidth Limit Count */ +#define DMA21_CURR_BWL_COUNT 0xFFC09044 /* DMA21 Bandwidth Limit Count Current */ +#define DMA21_BWM_COUNT 0xFFC09048 /* DMA21 Bandwidth Monitor Count */ +#define DMA21_CURR_BWM_COUNT 0xFFC0904C /* DMA21 Bandwidth Monitor Count Current */ + +/* ========================= + DMA22 + ========================= */ +#define DMA22_NEXT_DESC_PTR 0xFFC09080 /* DMA22 Pointer to Next Initial Descriptor */ +#define DMA22_START_ADDR 0xFFC09084 /* DMA22 Start Address of Current Buffer */ +#define DMA22_CONFIG 0xFFC09088 /* DMA22 Configuration Register */ +#define DMA22_X_COUNT 0xFFC0908C /* DMA22 Inner Loop Count Start Value */ +#define DMA22_X_MODIFY 0xFFC09090 /* DMA22 Inner Loop Address Increment */ +#define DMA22_Y_COUNT 0xFFC09094 /* DMA22 Outer Loop Count Start Value (2D only) */ +#define DMA22_Y_MODIFY 0xFFC09098 /* DMA22 Outer Loop Address Increment (2D only) */ +#define DMA22_CURR_DESC_PTR 0xFFC090A4 /* DMA22 Current Descriptor Pointer */ +#define DMA22_PREV_DESC_PTR 0xFFC090A8 /* DMA22 Previous Initial Descriptor Pointer */ +#define DMA22_CURR_ADDR 0xFFC090AC /* DMA22 Current Address */ +#define DMA22_IRQ_STATUS 0xFFC090B0 /* DMA22 Status Register */ +#define DMA22_CURR_X_COUNT 0xFFC090B4 /* DMA22 Current Count(1D) or intra-row XCNT (2D) */ +#define DMA22_CURR_Y_COUNT 0xFFC090B8 /* DMA22 Current Row Count (2D only) */ +#define DMA22_BWL_COUNT 0xFFC090C0 /* DMA22 Bandwidth Limit Count */ +#define DMA22_CURR_BWL_COUNT 0xFFC090C4 /* DMA22 Bandwidth Limit Count Current */ +#define DMA22_BWM_COUNT 0xFFC090C8 /* DMA22 Bandwidth Monitor Count */ +#define DMA22_CURR_BWM_COUNT 0xFFC090CC /* DMA22 Bandwidth Monitor Count Current */ + +/* ========================= + DMA23 + ========================= */ +#define DMA23_NEXT_DESC_PTR 0xFFC09100 /* DMA23 Pointer to Next Initial Descriptor */ +#define DMA23_START_ADDR 0xFFC09104 /* DMA23 Start Address of Current Buffer */ +#define DMA23_CONFIG 0xFFC09108 /* DMA23 Configuration Register */ +#define DMA23_X_COUNT 0xFFC0910C /* DMA23 Inner Loop Count Start Value */ +#define DMA23_X_MODIFY 0xFFC09110 /* DMA23 Inner Loop Address Increment */ +#define DMA23_Y_COUNT 0xFFC09114 /* DMA23 Outer Loop Count Start Value (2D only) */ +#define DMA23_Y_MODIFY 0xFFC09118 /* DMA23 Outer Loop Address Increment (2D only) */ +#define DMA23_CURR_DESC_PTR 0xFFC09124 /* DMA23 Current Descriptor Pointer */ +#define DMA23_PREV_DESC_PTR 0xFFC09128 /* DMA23 Previous Initial Descriptor Pointer */ +#define DMA23_CURR_ADDR 0xFFC0912C /* DMA23 Current Address */ +#define DMA23_IRQ_STATUS 0xFFC09130 /* DMA23 Status Register */ +#define DMA23_CURR_X_COUNT 0xFFC09134 /* DMA23 Current Count(1D) or intra-row XCNT (2D) */ +#define DMA23_CURR_Y_COUNT 0xFFC09138 /* DMA23 Current Row Count (2D only) */ +#define DMA23_BWL_COUNT 0xFFC09140 /* DMA23 Bandwidth Limit Count */ +#define DMA23_CURR_BWL_COUNT 0xFFC09144 /* DMA23 Bandwidth Limit Count Current */ +#define DMA23_BWM_COUNT 0xFFC09148 /* DMA23 Bandwidth Monitor Count */ +#define DMA23_CURR_BWM_COUNT 0xFFC0914C /* DMA23 Bandwidth Monitor Count Current */ + +/* ========================= + DMA24 + ========================= */ +#define DMA24_NEXT_DESC_PTR 0xFFC09180 /* DMA24 Pointer to Next Initial Descriptor */ +#define DMA24_START_ADDR 0xFFC09184 /* DMA24 Start Address of Current Buffer */ +#define DMA24_CONFIG 0xFFC09188 /* DMA24 Configuration Register */ +#define DMA24_X_COUNT 0xFFC0918C /* DMA24 Inner Loop Count Start Value */ +#define DMA24_X_MODIFY 0xFFC09190 /* DMA24 Inner Loop Address Increment */ +#define DMA24_Y_COUNT 0xFFC09194 /* DMA24 Outer Loop Count Start Value (2D only) */ +#define DMA24_Y_MODIFY 0xFFC09198 /* DMA24 Outer Loop Address Increment (2D only) */ +#define DMA24_CURR_DESC_PTR 0xFFC091A4 /* DMA24 Current Descriptor Pointer */ +#define DMA24_PREV_DESC_PTR 0xFFC091A8 /* DMA24 Previous Initial Descriptor Pointer */ +#define DMA24_CURR_ADDR 0xFFC091AC /* DMA24 Current Address */ +#define DMA24_IRQ_STATUS 0xFFC091B0 /* DMA24 Status Register */ +#define DMA24_CURR_X_COUNT 0xFFC091B4 /* DMA24 Current Count(1D) or intra-row XCNT (2D) */ +#define DMA24_CURR_Y_COUNT 0xFFC091B8 /* DMA24 Current Row Count (2D only) */ +#define DMA24_BWL_COUNT 0xFFC091C0 /* DMA24 Bandwidth Limit Count */ +#define DMA24_CURR_BWL_COUNT 0xFFC091C4 /* DMA24 Bandwidth Limit Count Current */ +#define DMA24_BWM_COUNT 0xFFC091C8 /* DMA24 Bandwidth Monitor Count */ +#define DMA24_CURR_BWM_COUNT 0xFFC091CC /* DMA24 Bandwidth Monitor Count Current */ + +/* ========================= + DMA25 + ========================= */ +#define DMA25_NEXT_DESC_PTR 0xFFC09200 /* DMA25 Pointer to Next Initial Descriptor */ +#define DMA25_START_ADDR 0xFFC09204 /* DMA25 Start Address of Current Buffer */ +#define DMA25_CONFIG 0xFFC09208 /* DMA25 Configuration Register */ +#define DMA25_X_COUNT 0xFFC0920C /* DMA25 Inner Loop Count Start Value */ +#define DMA25_X_MODIFY 0xFFC09210 /* DMA25 Inner Loop Address Increment */ +#define DMA25_Y_COUNT 0xFFC09214 /* DMA25 Outer Loop Count Start Value (2D only) */ +#define DMA25_Y_MODIFY 0xFFC09218 /* DMA25 Outer Loop Address Increment (2D only) */ +#define DMA25_CURR_DESC_PTR 0xFFC09224 /* DMA25 Current Descriptor Pointer */ +#define DMA25_PREV_DESC_PTR 0xFFC09228 /* DMA25 Previous Initial Descriptor Pointer */ +#define DMA25_CURR_ADDR 0xFFC0922C /* DMA25 Current Address */ +#define DMA25_IRQ_STATUS 0xFFC09230 /* DMA25 Status Register */ +#define DMA25_CURR_X_COUNT 0xFFC09234 /* DMA25 Current Count(1D) or intra-row XCNT (2D) */ +#define DMA25_CURR_Y_COUNT 0xFFC09238 /* DMA25 Current Row Count (2D only) */ +#define DMA25_BWL_COUNT 0xFFC09240 /* DMA25 Bandwidth Limit Count */ +#define DMA25_CURR_BWL_COUNT 0xFFC09244 /* DMA25 Bandwidth Limit Count Current */ +#define DMA25_BWM_COUNT 0xFFC09248 /* DMA25 Bandwidth Monitor Count */ +#define DMA25_CURR_BWM_COUNT 0xFFC0924C /* DMA25 Bandwidth Monitor Count Current */ + +/* ========================= + DMA26 + ========================= */ +#define DMA26_NEXT_DESC_PTR 0xFFC09280 /* DMA26 Pointer to Next Initial Descriptor */ +#define DMA26_START_ADDR 0xFFC09284 /* DMA26 Start Address of Current Buffer */ +#define DMA26_CONFIG 0xFFC09288 /* DMA26 Configuration Register */ +#define DMA26_X_COUNT 0xFFC0928C /* DMA26 Inner Loop Count Start Value */ +#define DMA26_X_MODIFY 0xFFC09290 /* DMA26 Inner Loop Address Increment */ +#define DMA26_Y_COUNT 0xFFC09294 /* DMA26 Outer Loop Count Start Value (2D only) */ +#define DMA26_Y_MODIFY 0xFFC09298 /* DMA26 Outer Loop Address Increment (2D only) */ +#define DMA26_CURR_DESC_PTR 0xFFC092A4 /* DMA26 Current Descriptor Pointer */ +#define DMA26_PREV_DESC_PTR 0xFFC092A8 /* DMA26 Previous Initial Descriptor Pointer */ +#define DMA26_CURR_ADDR 0xFFC092AC /* DMA26 Current Address */ +#define DMA26_IRQ_STATUS 0xFFC092B0 /* DMA26 Status Register */ +#define DMA26_CURR_X_COUNT 0xFFC092B4 /* DMA26 Current Count(1D) or intra-row XCNT (2D) */ +#define DMA26_CURR_Y_COUNT 0xFFC092B8 /* DMA26 Current Row Count (2D only) */ +#define DMA26_BWL_COUNT 0xFFC092C0 /* DMA26 Bandwidth Limit Count */ +#define DMA26_CURR_BWL_COUNT 0xFFC092C4 /* DMA26 Bandwidth Limit Count Current */ +#define DMA26_BWM_COUNT 0xFFC092C8 /* DMA26 Bandwidth Monitor Count */ +#define DMA26_CURR_BWM_COUNT 0xFFC092CC /* DMA26 Bandwidth Monitor Count Current */ + +/* ========================= + DMA27 + ========================= */ +#define DMA27_NEXT_DESC_PTR 0xFFC09300 /* DMA27 Pointer to Next Initial Descriptor */ +#define DMA27_START_ADDR 0xFFC09304 /* DMA27 Start Address of Current Buffer */ +#define DMA27_CONFIG 0xFFC09308 /* DMA27 Configuration Register */ +#define DMA27_X_COUNT 0xFFC0930C /* DMA27 Inner Loop Count Start Value */ +#define DMA27_X_MODIFY 0xFFC09310 /* DMA27 Inner Loop Address Increment */ +#define DMA27_Y_COUNT 0xFFC09314 /* DMA27 Outer Loop Count Start Value (2D only) */ +#define DMA27_Y_MODIFY 0xFFC09318 /* DMA27 Outer Loop Address Increment (2D only) */ +#define DMA27_CURR_DESC_PTR 0xFFC09324 /* DMA27 Current Descriptor Pointer */ +#define DMA27_PREV_DESC_PTR 0xFFC09328 /* DMA27 Previous Initial Descriptor Pointer */ +#define DMA27_CURR_ADDR 0xFFC0932C /* DMA27 Current Address */ +#define DMA27_IRQ_STATUS 0xFFC09330 /* DMA27 Status Register */ +#define DMA27_CURR_X_COUNT 0xFFC09334 /* DMA27 Current Count(1D) or intra-row XCNT (2D) */ +#define DMA27_CURR_Y_COUNT 0xFFC09338 /* DMA27 Current Row Count (2D only) */ +#define DMA27_BWL_COUNT 0xFFC09340 /* DMA27 Bandwidth Limit Count */ +#define DMA27_CURR_BWL_COUNT 0xFFC09344 /* DMA27 Bandwidth Limit Count Current */ +#define DMA27_BWM_COUNT 0xFFC09348 /* DMA27 Bandwidth Monitor Count */ +#define DMA27_CURR_BWM_COUNT 0xFFC0934C /* DMA27 Bandwidth Monitor Count Current */ + +/* ========================= + DMA28 + ========================= */ +#define DMA28_NEXT_DESC_PTR 0xFFC09380 /* DMA28 Pointer to Next Initial Descriptor */ +#define DMA28_START_ADDR 0xFFC09384 /* DMA28 Start Address of Current Buffer */ +#define DMA28_CONFIG 0xFFC09388 /* DMA28 Configuration Register */ +#define DMA28_X_COUNT 0xFFC0938C /* DMA28 Inner Loop Count Start Value */ +#define DMA28_X_MODIFY 0xFFC09390 /* DMA28 Inner Loop Address Increment */ +#define DMA28_Y_COUNT 0xFFC09394 /* DMA28 Outer Loop Count Start Value (2D only) */ +#define DMA28_Y_MODIFY 0xFFC09398 /* DMA28 Outer Loop Address Increment (2D only) */ +#define DMA28_CURR_DESC_PTR 0xFFC093A4 /* DMA28 Current Descriptor Pointer */ +#define DMA28_PREV_DESC_PTR 0xFFC093A8 /* DMA28 Previous Initial Descriptor Pointer */ +#define DMA28_CURR_ADDR 0xFFC093AC /* DMA28 Current Address */ +#define DMA28_IRQ_STATUS 0xFFC093B0 /* DMA28 Status Register */ +#define DMA28_CURR_X_COUNT 0xFFC093B4 /* DMA28 Current Count(1D) or intra-row XCNT (2D) */ +#define DMA28_CURR_Y_COUNT 0xFFC093B8 /* DMA28 Current Row Count (2D only) */ +#define DMA28_BWL_COUNT 0xFFC093C0 /* DMA28 Bandwidth Limit Count */ +#define DMA28_CURR_BWL_COUNT 0xFFC093C4 /* DMA28 Bandwidth Limit Count Current */ +#define DMA28_BWM_COUNT 0xFFC093C8 /* DMA28 Bandwidth Monitor Count */ +#define DMA28_CURR_BWM_COUNT 0xFFC093CC /* DMA28 Bandwidth Monitor Count Current */ + +/* ========================= + DMA29 + ========================= */ +#define DMA29_NEXT_DESC_PTR 0xFFC0B000 /* DMA29 Pointer to Next Initial Descriptor */ +#define DMA29_START_ADDR 0xFFC0B004 /* DMA29 Start Address of Current Buffer */ +#define DMA29_CONFIG 0xFFC0B008 /* DMA29 Configuration Register */ +#define DMA29_X_COUNT 0xFFC0B00C /* DMA29 Inner Loop Count Start Value */ +#define DMA29_X_MODIFY 0xFFC0B010 /* DMA29 Inner Loop Address Increment */ +#define DMA29_Y_COUNT 0xFFC0B014 /* DMA29 Outer Loop Count Start Value (2D only) */ +#define DMA29_Y_MODIFY 0xFFC0B018 /* DMA29 Outer Loop Address Increment (2D only) */ +#define DMA29_CURR_DESC_PTR 0xFFC0B024 /* DMA29 Current Descriptor Pointer */ +#define DMA29_PREV_DESC_PTR 0xFFC0B028 /* DMA29 Previous Initial Descriptor Pointer */ +#define DMA29_CURR_ADDR 0xFFC0B02C /* DMA29 Current Address */ +#define DMA29_IRQ_STATUS 0xFFC0B030 /* DMA29 Status Register */ +#define DMA29_CURR_X_COUNT 0xFFC0B034 /* DMA29 Current Count(1D) or intra-row XCNT (2D) */ +#define DMA29_CURR_Y_COUNT 0xFFC0B038 /* DMA29 Current Row Count (2D only) */ +#define DMA29_BWL_COUNT 0xFFC0B040 /* DMA29 Bandwidth Limit Count */ +#define DMA29_CURR_BWL_COUNT 0xFFC0B044 /* DMA29 Bandwidth Limit Count Current */ +#define DMA29_BWM_COUNT 0xFFC0B048 /* DMA29 Bandwidth Monitor Count */ +#define DMA29_CURR_BWM_COUNT 0xFFC0B04C /* DMA29 Bandwidth Monitor Count Current */ + +/* ========================= + DMA30 + ========================= */ +#define DMA30_NEXT_DESC_PTR 0xFFC0B080 /* DMA30 Pointer to Next Initial Descriptor */ +#define DMA30_START_ADDR 0xFFC0B084 /* DMA30 Start Address of Current Buffer */ +#define DMA30_CONFIG 0xFFC0B088 /* DMA30 Configuration Register */ +#define DMA30_X_COUNT 0xFFC0B08C /* DMA30 Inner Loop Count Start Value */ +#define DMA30_X_MODIFY 0xFFC0B090 /* DMA30 Inner Loop Address Increment */ +#define DMA30_Y_COUNT 0xFFC0B094 /* DMA30 Outer Loop Count Start Value (2D only) */ +#define DMA30_Y_MODIFY 0xFFC0B098 /* DMA30 Outer Loop Address Increment (2D only) */ +#define DMA30_CURR_DESC_PTR 0xFFC0B0A4 /* DMA30 Current Descriptor Pointer */ +#define DMA30_PREV_DESC_PTR 0xFFC0B0A8 /* DMA30 Previous Initial Descriptor Pointer */ +#define DMA30_CURR_ADDR 0xFFC0B0AC /* DMA30 Current Address */ +#define DMA30_IRQ_STATUS 0xFFC0B0B0 /* DMA30 Status Register */ +#define DMA30_CURR_X_COUNT 0xFFC0B0B4 /* DMA30 Current Count(1D) or intra-row XCNT (2D) */ +#define DMA30_CURR_Y_COUNT 0xFFC0B0B8 /* DMA30 Current Row Count (2D only) */ +#define DMA30_BWL_COUNT 0xFFC0B0C0 /* DMA30 Bandwidth Limit Count */ +#define DMA30_CURR_BWL_COUNT 0xFFC0B0C4 /* DMA30 Bandwidth Limit Count Current */ +#define DMA30_BWM_COUNT 0xFFC0B0C8 /* DMA30 Bandwidth Monitor Count */ +#define DMA30_CURR_BWM_COUNT 0xFFC0B0CC /* DMA30 Bandwidth Monitor Count Current */ + +/* ========================= + DMA31 + ========================= */ +#define DMA31_NEXT_DESC_PTR 0xFFC0B100 /* DMA31 Pointer to Next Initial Descriptor */ +#define DMA31_START_ADDR 0xFFC0B104 /* DMA31 Start Address of Current Buffer */ +#define DMA31_CONFIG 0xFFC0B108 /* DMA31 Configuration Register */ +#define DMA31_X_COUNT 0xFFC0B10C /* DMA31 Inner Loop Count Start Value */ +#define DMA31_X_MODIFY 0xFFC0B110 /* DMA31 Inner Loop Address Increment */ +#define DMA31_Y_COUNT 0xFFC0B114 /* DMA31 Outer Loop Count Start Value (2D only) */ +#define DMA31_Y_MODIFY 0xFFC0B118 /* DMA31 Outer Loop Address Increment (2D only) */ +#define DMA31_CURR_DESC_PTR 0xFFC0B124 /* DMA31 Current Descriptor Pointer */ +#define DMA31_PREV_DESC_PTR 0xFFC0B128 /* DMA31 Previous Initial Descriptor Pointer */ +#define DMA31_CURR_ADDR 0xFFC0B12C /* DMA31 Current Address */ +#define DMA31_IRQ_STATUS 0xFFC0B130 /* DMA31 Status Register */ +#define DMA31_CURR_X_COUNT 0xFFC0B134 /* DMA31 Current Count(1D) or intra-row XCNT (2D) */ +#define DMA31_CURR_Y_COUNT 0xFFC0B138 /* DMA31 Current Row Count (2D only) */ +#define DMA31_BWL_COUNT 0xFFC0B140 /* DMA31 Bandwidth Limit Count */ +#define DMA31_CURR_BWL_COUNT 0xFFC0B144 /* DMA31 Bandwidth Limit Count Current */ +#define DMA31_BWM_COUNT 0xFFC0B148 /* DMA31 Bandwidth Monitor Count */ +#define DMA31_CURR_BWM_COUNT 0xFFC0B14C /* DMA31 Bandwidth Monitor Count Current */ + +/* ========================= + DMA32 + ========================= */ +#define DMA32_NEXT_DESC_PTR 0xFFC0B180 /* DMA32 Pointer to Next Initial Descriptor */ +#define DMA32_START_ADDR 0xFFC0B184 /* DMA32 Start Address of Current Buffer */ +#define DMA32_CONFIG 0xFFC0B188 /* DMA32 Configuration Register */ +#define DMA32_X_COUNT 0xFFC0B18C /* DMA32 Inner Loop Count Start Value */ +#define DMA32_X_MODIFY 0xFFC0B190 /* DMA32 Inner Loop Address Increment */ +#define DMA32_Y_COUNT 0xFFC0B194 /* DMA32 Outer Loop Count Start Value (2D only) */ +#define DMA32_Y_MODIFY 0xFFC0B198 /* DMA32 Outer Loop Address Increment (2D only) */ +#define DMA32_CURR_DESC_PTR 0xFFC0B1A4 /* DMA32 Current Descriptor Pointer */ +#define DMA32_PREV_DESC_PTR 0xFFC0B1A8 /* DMA32 Previous Initial Descriptor Pointer */ +#define DMA32_CURR_ADDR 0xFFC0B1AC /* DMA32 Current Address */ +#define DMA32_IRQ_STATUS 0xFFC0B1B0 /* DMA32 Status Register */ +#define DMA32_CURR_X_COUNT 0xFFC0B1B4 /* DMA32 Current Count(1D) or intra-row XCNT (2D) */ +#define DMA32_CURR_Y_COUNT 0xFFC0B1B8 /* DMA32 Current Row Count (2D only) */ +#define DMA32_BWL_COUNT 0xFFC0B1C0 /* DMA32 Bandwidth Limit Count */ +#define DMA32_CURR_BWL_COUNT 0xFFC0B1C4 /* DMA32 Bandwidth Limit Count Current */ +#define DMA32_BWM_COUNT 0xFFC0B1C8 /* DMA32 Bandwidth Monitor Count */ +#define DMA32_CURR_BWM_COUNT 0xFFC0B1CC /* DMA32 Bandwidth Monitor Count Current */ + +/* ========================= + DMA33 + ========================= */ +#define DMA33_NEXT_DESC_PTR 0xFFC0D000 /* DMA33 Pointer to Next Initial Descriptor */ +#define DMA33_START_ADDR 0xFFC0D004 /* DMA33 Start Address of Current Buffer */ +#define DMA33_CONFIG 0xFFC0D008 /* DMA33 Configuration Register */ +#define DMA33_X_COUNT 0xFFC0D00C /* DMA33 Inner Loop Count Start Value */ +#define DMA33_X_MODIFY 0xFFC0D010 /* DMA33 Inner Loop Address Increment */ +#define DMA33_Y_COUNT 0xFFC0D014 /* DMA33 Outer Loop Count Start Value (2D only) */ +#define DMA33_Y_MODIFY 0xFFC0D018 /* DMA33 Outer Loop Address Increment (2D only) */ +#define DMA33_CURR_DESC_PTR 0xFFC0D024 /* DMA33 Current Descriptor Pointer */ +#define DMA33_PREV_DESC_PTR 0xFFC0D028 /* DMA33 Previous Initial Descriptor Pointer */ +#define DMA33_CURR_ADDR 0xFFC0D02C /* DMA33 Current Address */ +#define DMA33_IRQ_STATUS 0xFFC0D030 /* DMA33 Status Register */ +#define DMA33_CURR_X_COUNT 0xFFC0D034 /* DMA33 Current Count(1D) or intra-row XCNT (2D) */ +#define DMA33_CURR_Y_COUNT 0xFFC0D038 /* DMA33 Current Row Count (2D only) */ +#define DMA33_BWL_COUNT 0xFFC0D040 /* DMA33 Bandwidth Limit Count */ +#define DMA33_CURR_BWL_COUNT 0xFFC0D044 /* DMA33 Bandwidth Limit Count Current */ +#define DMA33_BWM_COUNT 0xFFC0D048 /* DMA33 Bandwidth Monitor Count */ +#define DMA33_CURR_BWM_COUNT 0xFFC0D04C /* DMA33 Bandwidth Monitor Count Current */ + +/* ========================= + DMA34 + ========================= */ +#define DMA34_NEXT_DESC_PTR 0xFFC0D080 /* DMA34 Pointer to Next Initial Descriptor */ +#define DMA34_START_ADDR 0xFFC0D084 /* DMA34 Start Address of Current Buffer */ +#define DMA34_CONFIG 0xFFC0D088 /* DMA34 Configuration Register */ +#define DMA34_X_COUNT 0xFFC0D08C /* DMA34 Inner Loop Count Start Value */ +#define DMA34_X_MODIFY 0xFFC0D090 /* DMA34 Inner Loop Address Increment */ +#define DMA34_Y_COUNT 0xFFC0D094 /* DMA34 Outer Loop Count Start Value (2D only) */ +#define DMA34_Y_MODIFY 0xFFC0D098 /* DMA34 Outer Loop Address Increment (2D only) */ +#define DMA34_CURR_DESC_PTR 0xFFC0D0A4 /* DMA34 Current Descriptor Pointer */ +#define DMA34_PREV_DESC_PTR 0xFFC0D0A8 /* DMA34 Previous Initial Descriptor Pointer */ +#define DMA34_CURR_ADDR 0xFFC0D0AC /* DMA34 Current Address */ +#define DMA34_IRQ_STATUS 0xFFC0D0B0 /* DMA34 Status Register */ +#define DMA34_CURR_X_COUNT 0xFFC0D0B4 /* DMA34 Current Count(1D) or intra-row XCNT (2D) */ +#define DMA34_CURR_Y_COUNT 0xFFC0D0B8 /* DMA34 Current Row Count (2D only) */ +#define DMA34_BWL_COUNT 0xFFC0D0C0 /* DMA34 Bandwidth Limit Count */ +#define DMA34_CURR_BWL_COUNT 0xFFC0D0C4 /* DMA34 Bandwidth Limit Count Current */ +#define DMA34_BWM_COUNT 0xFFC0D0C8 /* DMA34 Bandwidth Monitor Count */ +#define DMA34_CURR_BWM_COUNT 0xFFC0D0CC /* DMA34 Bandwidth Monitor Count Current */ + +/* ========================= + DMA35 + ========================= */ +#define DMA35_NEXT_DESC_PTR 0xFFC10000 /* DMA35 Pointer to Next Initial Descriptor */ +#define DMA35_START_ADDR 0xFFC10004 /* DMA35 Start Address of Current Buffer */ +#define DMA35_CONFIG 0xFFC10008 /* DMA35 Configuration Register */ +#define DMA35_X_COUNT 0xFFC1000C /* DMA35 Inner Loop Count Start Value */ +#define DMA35_X_MODIFY 0xFFC10010 /* DMA35 Inner Loop Address Increment */ +#define DMA35_Y_COUNT 0xFFC10014 /* DMA35 Outer Loop Count Start Value (2D only) */ +#define DMA35_Y_MODIFY 0xFFC10018 /* DMA35 Outer Loop Address Increment (2D only) */ +#define DMA35_CURR_DESC_PTR 0xFFC10024 /* DMA35 Current Descriptor Pointer */ +#define DMA35_PREV_DESC_PTR 0xFFC10028 /* DMA35 Previous Initial Descriptor Pointer */ +#define DMA35_CURR_ADDR 0xFFC1002C /* DMA35 Current Address */ +#define DMA35_IRQ_STATUS 0xFFC10030 /* DMA35 Status Register */ +#define DMA35_CURR_X_COUNT 0xFFC10034 /* DMA35 Current Count(1D) or intra-row XCNT (2D) */ +#define DMA35_CURR_Y_COUNT 0xFFC10038 /* DMA35 Current Row Count (2D only) */ +#define DMA35_BWL_COUNT 0xFFC10040 /* DMA35 Bandwidth Limit Count */ +#define DMA35_CURR_BWL_COUNT 0xFFC10044 /* DMA35 Bandwidth Limit Count Current */ +#define DMA35_BWM_COUNT 0xFFC10048 /* DMA35 Bandwidth Monitor Count */ +#define DMA35_CURR_BWM_COUNT 0xFFC1004C /* DMA35 Bandwidth Monitor Count Current */ + +/* ========================= + DMA36 + ========================= */ +#define DMA36_NEXT_DESC_PTR 0xFFC10080 /* DMA36 Pointer to Next Initial Descriptor */ +#define DMA36_START_ADDR 0xFFC10084 /* DMA36 Start Address of Current Buffer */ +#define DMA36_CONFIG 0xFFC10088 /* DMA36 Configuration Register */ +#define DMA36_X_COUNT 0xFFC1008C /* DMA36 Inner Loop Count Start Value */ +#define DMA36_X_MODIFY 0xFFC10090 /* DMA36 Inner Loop Address Increment */ +#define DMA36_Y_COUNT 0xFFC10094 /* DMA36 Outer Loop Count Start Value (2D only) */ +#define DMA36_Y_MODIFY 0xFFC10098 /* DMA36 Outer Loop Address Increment (2D only) */ +#define DMA36_CURR_DESC_PTR 0xFFC100A4 /* DMA36 Current Descriptor Pointer */ +#define DMA36_PREV_DESC_PTR 0xFFC100A8 /* DMA36 Previous Initial Descriptor Pointer */ +#define DMA36_CURR_ADDR 0xFFC100AC /* DMA36 Current Address */ +#define DMA36_IRQ_STATUS 0xFFC100B0 /* DMA36 Status Register */ +#define DMA36_CURR_X_COUNT 0xFFC100B4 /* DMA36 Current Count(1D) or intra-row XCNT (2D) */ +#define DMA36_CURR_Y_COUNT 0xFFC100B8 /* DMA36 Current Row Count (2D only) */ +#define DMA36_BWL_COUNT 0xFFC100C0 /* DMA36 Bandwidth Limit Count */ +#define DMA36_CURR_BWL_COUNT 0xFFC100C4 /* DMA36 Bandwidth Limit Count Current */ +#define DMA36_BWM_COUNT 0xFFC100C8 /* DMA36 Bandwidth Monitor Count */ +#define DMA36_CURR_BWM_COUNT 0xFFC100CC /* DMA36 Bandwidth Monitor Count Current */ + +/* ========================= + DMA37 + ========================= */ +#define DMA37_NEXT_DESC_PTR 0xFFC10100 /* DMA37 Pointer to Next Initial Descriptor */ +#define DMA37_START_ADDR 0xFFC10104 /* DMA37 Start Address of Current Buffer */ +#define DMA37_CONFIG 0xFFC10108 /* DMA37 Configuration Register */ +#define DMA37_X_COUNT 0xFFC1010C /* DMA37 Inner Loop Count Start Value */ +#define DMA37_X_MODIFY 0xFFC10110 /* DMA37 Inner Loop Address Increment */ +#define DMA37_Y_COUNT 0xFFC10114 /* DMA37 Outer Loop Count Start Value (2D only) */ +#define DMA37_Y_MODIFY 0xFFC10118 /* DMA37 Outer Loop Address Increment (2D only) */ +#define DMA37_CURR_DESC_PTR 0xFFC10124 /* DMA37 Current Descriptor Pointer */ +#define DMA37_PREV_DESC_PTR 0xFFC10128 /* DMA37 Previous Initial Descriptor Pointer */ +#define DMA37_CURR_ADDR 0xFFC1012C /* DMA37 Current Address */ +#define DMA37_IRQ_STATUS 0xFFC10130 /* DMA37 Status Register */ +#define DMA37_CURR_X_COUNT 0xFFC10134 /* DMA37 Current Count(1D) or intra-row XCNT (2D) */ +#define DMA37_CURR_Y_COUNT 0xFFC10138 /* DMA37 Current Row Count (2D only) */ +#define DMA37_BWL_COUNT 0xFFC10140 /* DMA37 Bandwidth Limit Count */ +#define DMA37_CURR_BWL_COUNT 0xFFC10144 /* DMA37 Bandwidth Limit Count Current */ +#define DMA37_BWM_COUNT 0xFFC10148 /* DMA37 Bandwidth Monitor Count */ +#define DMA37_CURR_BWM_COUNT 0xFFC1014C /* DMA37 Bandwidth Monitor Count Current */ + +/* ========================= + DMA38 + ========================= */ +#define DMA38_NEXT_DESC_PTR 0xFFC12000 /* DMA38 Pointer to Next Initial Descriptor */ +#define DMA38_START_ADDR 0xFFC12004 /* DMA38 Start Address of Current Buffer */ +#define DMA38_CONFIG 0xFFC12008 /* DMA38 Configuration Register */ +#define DMA38_X_COUNT 0xFFC1200C /* DMA38 Inner Loop Count Start Value */ +#define DMA38_X_MODIFY 0xFFC12010 /* DMA38 Inner Loop Address Increment */ +#define DMA38_Y_COUNT 0xFFC12014 /* DMA38 Outer Loop Count Start Value (2D only) */ +#define DMA38_Y_MODIFY 0xFFC12018 /* DMA38 Outer Loop Address Increment (2D only) */ +#define DMA38_CURR_DESC_PTR 0xFFC12024 /* DMA38 Current Descriptor Pointer */ +#define DMA38_PREV_DESC_PTR 0xFFC12028 /* DMA38 Previous Initial Descriptor Pointer */ +#define DMA38_CURR_ADDR 0xFFC1202C /* DMA38 Current Address */ +#define DMA38_IRQ_STATUS 0xFFC12030 /* DMA38 Status Register */ +#define DMA38_CURR_X_COUNT 0xFFC12034 /* DMA38 Current Count(1D) or intra-row XCNT (2D) */ +#define DMA38_CURR_Y_COUNT 0xFFC12038 /* DMA38 Current Row Count (2D only) */ +#define DMA38_BWL_COUNT 0xFFC12040 /* DMA38 Bandwidth Limit Count */ +#define DMA38_CURR_BWL_COUNT 0xFFC12044 /* DMA38 Bandwidth Limit Count Current */ +#define DMA38_BWM_COUNT 0xFFC12048 /* DMA38 Bandwidth Monitor Count */ +#define DMA38_CURR_BWM_COUNT 0xFFC1204C /* DMA38 Bandwidth Monitor Count Current */ + +/* ========================= + DMA39 + ========================= */ +#define DMA39_NEXT_DESC_PTR 0xFFC12080 /* DMA39 Pointer to Next Initial Descriptor */ +#define DMA39_START_ADDR 0xFFC12084 /* DMA39 Start Address of Current Buffer */ +#define DMA39_CONFIG 0xFFC12088 /* DMA39 Configuration Register */ +#define DMA39_X_COUNT 0xFFC1208C /* DMA39 Inner Loop Count Start Value */ +#define DMA39_X_MODIFY 0xFFC12090 /* DMA39 Inner Loop Address Increment */ +#define DMA39_Y_COUNT 0xFFC12094 /* DMA39 Outer Loop Count Start Value (2D only) */ +#define DMA39_Y_MODIFY 0xFFC12098 /* DMA39 Outer Loop Address Increment (2D only) */ +#define DMA39_CURR_DESC_PTR 0xFFC120A4 /* DMA39 Current Descriptor Pointer */ +#define DMA39_PREV_DESC_PTR 0xFFC120A8 /* DMA39 Previous Initial Descriptor Pointer */ +#define DMA39_CURR_ADDR 0xFFC120AC /* DMA39 Current Address */ +#define DMA39_IRQ_STATUS 0xFFC120B0 /* DMA39 Status Register */ +#define DMA39_CURR_X_COUNT 0xFFC120B4 /* DMA39 Current Count(1D) or intra-row XCNT (2D) */ +#define DMA39_CURR_Y_COUNT 0xFFC120B8 /* DMA39 Current Row Count (2D only) */ +#define DMA39_BWL_COUNT 0xFFC120C0 /* DMA39 Bandwidth Limit Count */ +#define DMA39_CURR_BWL_COUNT 0xFFC120C4 /* DMA39 Bandwidth Limit Count Current */ +#define DMA39_BWM_COUNT 0xFFC120C8 /* DMA39 Bandwidth Monitor Count */ +#define DMA39_CURR_BWM_COUNT 0xFFC120CC /* DMA39 Bandwidth Monitor Count Current */ + +/* ========================= + DMA40 + ========================= */ +#define DMA40_NEXT_DESC_PTR 0xFFC12100 /* DMA40 Pointer to Next Initial Descriptor */ +#define DMA40_START_ADDR 0xFFC12104 /* DMA40 Start Address of Current Buffer */ +#define DMA40_CONFIG 0xFFC12108 /* DMA40 Configuration Register */ +#define DMA40_X_COUNT 0xFFC1210C /* DMA40 Inner Loop Count Start Value */ +#define DMA40_X_MODIFY 0xFFC12110 /* DMA40 Inner Loop Address Increment */ +#define DMA40_Y_COUNT 0xFFC12114 /* DMA40 Outer Loop Count Start Value (2D only) */ +#define DMA40_Y_MODIFY 0xFFC12118 /* DMA40 Outer Loop Address Increment (2D only) */ +#define DMA40_CURR_DESC_PTR 0xFFC12124 /* DMA40 Current Descriptor Pointer */ +#define DMA40_PREV_DESC_PTR 0xFFC12128 /* DMA40 Previous Initial Descriptor Pointer */ +#define DMA40_CURR_ADDR 0xFFC1212C /* DMA40 Current Address */ +#define DMA40_IRQ_STATUS 0xFFC12130 /* DMA40 Status Register */ +#define DMA40_CURR_X_COUNT 0xFFC12134 /* DMA40 Current Count(1D) or intra-row XCNT (2D) */ +#define DMA40_CURR_Y_COUNT 0xFFC12138 /* DMA40 Current Row Count (2D only) */ +#define DMA40_BWL_COUNT 0xFFC12140 /* DMA40 Bandwidth Limit Count */ +#define DMA40_CURR_BWL_COUNT 0xFFC12144 /* DMA40 Bandwidth Limit Count Current */ +#define DMA40_BWM_COUNT 0xFFC12148 /* DMA40 Bandwidth Monitor Count */ +#define DMA40_CURR_BWM_COUNT 0xFFC1214C /* DMA40 Bandwidth Monitor Count Current */ + +/* ========================= + DMA41 + ========================= */ +#define DMA41_NEXT_DESC_PTR 0xFFC12180 /* DMA41 Pointer to Next Initial Descriptor */ +#define DMA41_START_ADDR 0xFFC12184 /* DMA41 Start Address of Current Buffer */ +#define DMA41_CONFIG 0xFFC12188 /* DMA41 Configuration Register */ +#define DMA41_X_COUNT 0xFFC1218C /* DMA41 Inner Loop Count Start Value */ +#define DMA41_X_MODIFY 0xFFC12190 /* DMA41 Inner Loop Address Increment */ +#define DMA41_Y_COUNT 0xFFC12194 /* DMA41 Outer Loop Count Start Value (2D only) */ +#define DMA41_Y_MODIFY 0xFFC12198 /* DMA41 Outer Loop Address Increment (2D only) */ +#define DMA41_CURR_DESC_PTR 0xFFC121A4 /* DMA41 Current Descriptor Pointer */ +#define DMA41_PREV_DESC_PTR 0xFFC121A8 /* DMA41 Previous Initial Descriptor Pointer */ +#define DMA41_CURR_ADDR 0xFFC121AC /* DMA41 Current Address */ +#define DMA41_IRQ_STATUS 0xFFC121B0 /* DMA41 Status Register */ +#define DMA41_CURR_X_COUNT 0xFFC121B4 /* DMA41 Current Count(1D) or intra-row XCNT (2D) */ +#define DMA41_CURR_Y_COUNT 0xFFC121B8 /* DMA41 Current Row Count (2D only) */ +#define DMA41_BWL_COUNT 0xFFC121C0 /* DMA41 Bandwidth Limit Count */ +#define DMA41_CURR_BWL_COUNT 0xFFC121C4 /* DMA41 Bandwidth Limit Count Current */ +#define DMA41_BWM_COUNT 0xFFC121C8 /* DMA41 Bandwidth Monitor Count */ +#define DMA41_CURR_BWM_COUNT 0xFFC121CC /* DMA41 Bandwidth Monitor Count Current */ + +/* ========================= + DMA42 + ========================= */ +#define DMA42_NEXT_DESC_PTR 0xFFC14000 /* DMA42 Pointer to Next Initial Descriptor */ +#define DMA42_START_ADDR 0xFFC14004 /* DMA42 Start Address of Current Buffer */ +#define DMA42_CONFIG 0xFFC14008 /* DMA42 Configuration Register */ +#define DMA42_X_COUNT 0xFFC1400C /* DMA42 Inner Loop Count Start Value */ +#define DMA42_X_MODIFY 0xFFC14010 /* DMA42 Inner Loop Address Increment */ +#define DMA42_Y_COUNT 0xFFC14014 /* DMA42 Outer Loop Count Start Value (2D only) */ +#define DMA42_Y_MODIFY 0xFFC14018 /* DMA42 Outer Loop Address Increment (2D only) */ +#define DMA42_CURR_DESC_PTR 0xFFC14024 /* DMA42 Current Descriptor Pointer */ +#define DMA42_PREV_DESC_PTR 0xFFC14028 /* DMA42 Previous Initial Descriptor Pointer */ +#define DMA42_CURR_ADDR 0xFFC1402C /* DMA42 Current Address */ +#define DMA42_IRQ_STATUS 0xFFC14030 /* DMA42 Status Register */ +#define DMA42_CURR_X_COUNT 0xFFC14034 /* DMA42 Current Count(1D) or intra-row XCNT (2D) */ +#define DMA42_CURR_Y_COUNT 0xFFC14038 /* DMA42 Current Row Count (2D only) */ +#define DMA42_BWL_COUNT 0xFFC14040 /* DMA42 Bandwidth Limit Count */ +#define DMA42_CURR_BWL_COUNT 0xFFC14044 /* DMA42 Bandwidth Limit Count Current */ +#define DMA42_BWM_COUNT 0xFFC14048 /* DMA42 Bandwidth Monitor Count */ +#define DMA42_CURR_BWM_COUNT 0xFFC1404C /* DMA42 Bandwidth Monitor Count Current */ + +/* ========================= + DMA43 + ========================= */ +#define DMA43_NEXT_DESC_PTR 0xFFC14080 /* DMA43 Pointer to Next Initial Descriptor */ +#define DMA43_START_ADDR 0xFFC14084 /* DMA43 Start Address of Current Buffer */ +#define DMA43_CONFIG 0xFFC14088 /* DMA43 Configuration Register */ +#define DMA43_X_COUNT 0xFFC1408C /* DMA43 Inner Loop Count Start Value */ +#define DMA43_X_MODIFY 0xFFC14090 /* DMA43 Inner Loop Address Increment */ +#define DMA43_Y_COUNT 0xFFC14094 /* DMA43 Outer Loop Count Start Value (2D only) */ +#define DMA43_Y_MODIFY 0xFFC14098 /* DMA43 Outer Loop Address Increment (2D only) */ +#define DMA43_CURR_DESC_PTR 0xFFC140A4 /* DMA43 Current Descriptor Pointer */ +#define DMA43_PREV_DESC_PTR 0xFFC140A8 /* DMA43 Previous Initial Descriptor Pointer */ +#define DMA43_CURR_ADDR 0xFFC140AC /* DMA43 Current Address */ +#define DMA43_IRQ_STATUS 0xFFC140B0 /* DMA43 Status Register */ +#define DMA43_CURR_X_COUNT 0xFFC140B4 /* DMA43 Current Count(1D) or intra-row XCNT (2D) */ +#define DMA43_CURR_Y_COUNT 0xFFC140B8 /* DMA43 Current Row Count (2D only) */ +#define DMA43_BWL_COUNT 0xFFC140C0 /* DMA43 Bandwidth Limit Count */ +#define DMA43_CURR_BWL_COUNT 0xFFC140C4 /* DMA43 Bandwidth Limit Count Current */ +#define DMA43_BWM_COUNT 0xFFC140C8 /* DMA43 Bandwidth Monitor Count */ +#define DMA43_CURR_BWM_COUNT 0xFFC140CC /* DMA43 Bandwidth Monitor Count Current */ + +/* ========================= + DMA44 + ========================= */ +#define DMA44_NEXT_DESC_PTR 0xFFC14100 /* DMA44 Pointer to Next Initial Descriptor */ +#define DMA44_START_ADDR 0xFFC14104 /* DMA44 Start Address of Current Buffer */ +#define DMA44_CONFIG 0xFFC14108 /* DMA44 Configuration Register */ +#define DMA44_X_COUNT 0xFFC1410C /* DMA44 Inner Loop Count Start Value */ +#define DMA44_X_MODIFY 0xFFC14110 /* DMA44 Inner Loop Address Increment */ +#define DMA44_Y_COUNT 0xFFC14114 /* DMA44 Outer Loop Count Start Value (2D only) */ +#define DMA44_Y_MODIFY 0xFFC14118 /* DMA44 Outer Loop Address Increment (2D only) */ +#define DMA44_CURR_DESC_PTR 0xFFC14124 /* DMA44 Current Descriptor Pointer */ +#define DMA44_PREV_DESC_PTR 0xFFC14128 /* DMA44 Previous Initial Descriptor Pointer */ +#define DMA44_CURR_ADDR 0xFFC1412C /* DMA44 Current Address */ +#define DMA44_IRQ_STATUS 0xFFC14130 /* DMA44 Status Register */ +#define DMA44_CURR_X_COUNT 0xFFC14134 /* DMA44 Current Count(1D) or intra-row XCNT (2D) */ +#define DMA44_CURR_Y_COUNT 0xFFC14138 /* DMA44 Current Row Count (2D only) */ +#define DMA44_BWL_COUNT 0xFFC14140 /* DMA44 Bandwidth Limit Count */ +#define DMA44_CURR_BWL_COUNT 0xFFC14144 /* DMA44 Bandwidth Limit Count Current */ +#define DMA44_BWM_COUNT 0xFFC14148 /* DMA44 Bandwidth Monitor Count */ +#define DMA44_CURR_BWM_COUNT 0xFFC1414C /* DMA44 Bandwidth Monitor Count Current */ + +/* ========================= + DMA45 + ========================= */ +#define DMA45_NEXT_DESC_PTR 0xFFC14180 /* DMA45 Pointer to Next Initial Descriptor */ +#define DMA45_START_ADDR 0xFFC14184 /* DMA45 Start Address of Current Buffer */ +#define DMA45_CONFIG 0xFFC14188 /* DMA45 Configuration Register */ +#define DMA45_X_COUNT 0xFFC1418C /* DMA45 Inner Loop Count Start Value */ +#define DMA45_X_MODIFY 0xFFC14190 /* DMA45 Inner Loop Address Increment */ +#define DMA45_Y_COUNT 0xFFC14194 /* DMA45 Outer Loop Count Start Value (2D only) */ +#define DMA45_Y_MODIFY 0xFFC14198 /* DMA45 Outer Loop Address Increment (2D only) */ +#define DMA45_CURR_DESC_PTR 0xFFC141A4 /* DMA45 Current Descriptor Pointer */ +#define DMA45_PREV_DESC_PTR 0xFFC141A8 /* DMA45 Previous Initial Descriptor Pointer */ +#define DMA45_CURR_ADDR 0xFFC141AC /* DMA45 Current Address */ +#define DMA45_IRQ_STATUS 0xFFC141B0 /* DMA45 Status Register */ +#define DMA45_CURR_X_COUNT 0xFFC141B4 /* DMA45 Current Count(1D) or intra-row XCNT (2D) */ +#define DMA45_CURR_Y_COUNT 0xFFC141B8 /* DMA45 Current Row Count (2D only) */ +#define DMA45_BWL_COUNT 0xFFC141C0 /* DMA45 Bandwidth Limit Count */ +#define DMA45_CURR_BWL_COUNT 0xFFC141C4 /* DMA45 Bandwidth Limit Count Current */ +#define DMA45_BWM_COUNT 0xFFC141C8 /* DMA45 Bandwidth Monitor Count */ +#define DMA45_CURR_BWM_COUNT 0xFFC141CC /* DMA45 Bandwidth Monitor Count Current */ + +/* ========================= + DMA46 + ========================= */ +#define DMA46_NEXT_DESC_PTR 0xFFC14200 /* DMA46 Pointer to Next Initial Descriptor */ +#define DMA46_START_ADDR 0xFFC14204 /* DMA46 Start Address of Current Buffer */ +#define DMA46_CONFIG 0xFFC14208 /* DMA46 Configuration Register */ +#define DMA46_X_COUNT 0xFFC1420C /* DMA46 Inner Loop Count Start Value */ +#define DMA46_X_MODIFY 0xFFC14210 /* DMA46 Inner Loop Address Increment */ +#define DMA46_Y_COUNT 0xFFC14214 /* DMA46 Outer Loop Count Start Value (2D only) */ +#define DMA46_Y_MODIFY 0xFFC14218 /* DMA46 Outer Loop Address Increment (2D only) */ +#define DMA46_CURR_DESC_PTR 0xFFC14224 /* DMA46 Current Descriptor Pointer */ +#define DMA46_PREV_DESC_PTR 0xFFC14228 /* DMA46 Previous Initial Descriptor Pointer */ +#define DMA46_CURR_ADDR 0xFFC1422C /* DMA46 Current Address */ +#define DMA46_IRQ_STATUS 0xFFC14230 /* DMA46 Status Register */ +#define DMA46_CURR_X_COUNT 0xFFC14234 /* DMA46 Current Count(1D) or intra-row XCNT (2D) */ +#define DMA46_CURR_Y_COUNT 0xFFC14238 /* DMA46 Current Row Count (2D only) */ +#define DMA46_BWL_COUNT 0xFFC14240 /* DMA46 Bandwidth Limit Count */ +#define DMA46_CURR_BWL_COUNT 0xFFC14244 /* DMA46 Bandwidth Limit Count Current */ +#define DMA46_BWM_COUNT 0xFFC14248 /* DMA46 Bandwidth Monitor Count */ +#define DMA46_CURR_BWM_COUNT 0xFFC1424C /* DMA46 Bandwidth Monitor Count Current */ + + +/******************************************************************************** + DMA Alias Definitions + ********************************************************************************/ +#define MDMA0_DEST_CRC0_NEXT_DESC_PTR (DMA22_NEXT_DESC_PTR) +#define MDMA0_DEST_CRC0_START_ADDR (DMA22_START_ADDR) +#define MDMA0_DEST_CRC0_CONFIG (DMA22_CONFIG) +#define MDMA0_DEST_CRC0_X_COUNT (DMA22_X_COUNT) +#define MDMA0_DEST_CRC0_X_MODIFY (DMA22_X_MODIFY) +#define MDMA0_DEST_CRC0_Y_COUNT (DMA22_Y_COUNT) +#define MDMA0_DEST_CRC0_Y_MODIFY (DMA22_Y_MODIFY) +#define MDMA0_DEST_CRC0_CURR_DESC_PTR (DMA22_CURR_DESC_PTR) +#define MDMA0_DEST_CRC0_PREV_DESC_PTR (DMA22_PREV_DESC_PTR) +#define MDMA0_DEST_CRC0_CURR_ADDR (DMA22_CURR_ADDR) +#define MDMA0_DEST_CRC0_IRQ_STATUS (DMA22_IRQ_STATUS) +#define MDMA0_DEST_CRC0_CURR_X_COUNT (DMA22_CURR_X_COUNT) +#define MDMA0_DEST_CRC0_CURR_Y_COUNT (DMA22_CURR_Y_COUNT) +#define MDMA0_DEST_CRC0_BWL_COUNT (DMA22_BWL_COUNT) +#define MDMA0_DEST_CRC0_CURR_BWL_COUNT (DMA22_CURR_BWL_COUNT) +#define MDMA0_DEST_CRC0_BWM_COUNT (DMA22_BWM_COUNT) +#define MDMA0_DEST_CRC0_CURR_BWM_COUNT (DMA22_CURR_BWM_COUNT) +#define MDMA0_SRC_CRC0_NEXT_DESC_PTR (DMA21_NEXT_DESC_PTR) +#define MDMA0_SRC_CRC0_START_ADDR (DMA21_START_ADDR) +#define MDMA0_SRC_CRC0_CONFIG (DMA21_CONFIG) +#define MDMA0_SRC_CRC0_X_COUNT (DMA21_X_COUNT) +#define MDMA0_SRC_CRC0_X_MODIFY (DMA21_X_MODIFY) +#define MDMA0_SRC_CRC0_Y_COUNT (DMA21_Y_COUNT) +#define MDMA0_SRC_CRC0_Y_MODIFY (DMA21_Y_MODIFY) +#define MDMA0_SRC_CRC0_CURR_DESC_PTR (DMA21_CURR_DESC_PTR) +#define MDMA0_SRC_CRC0_PREV_DESC_PTR (DMA21_PREV_DESC_PTR) +#define MDMA0_SRC_CRC0_CURR_ADDR (DMA21_CURR_ADDR) +#define MDMA0_SRC_CRC0_IRQ_STATUS (DMA21_IRQ_STATUS) +#define MDMA0_SRC_CRC0_CURR_X_COUNT (DMA21_CURR_X_COUNT) +#define MDMA0_SRC_CRC0_CURR_Y_COUNT (DMA21_CURR_Y_COUNT) +#define MDMA0_SRC_CRC0_BWL_COUNT (DMA21_BWL_COUNT) +#define MDMA0_SRC_CRC0_CURR_BWL_COUNT (DMA21_CURR_BWL_COUNT) +#define MDMA0_SRC_CRC0_BWM_COUNT (DMA21_BWM_COUNT) +#define MDMA0_SRC_CRC0_CURR_BWM_COUNT (DMA21_CURR_BWM_COUNT) +#define MDMA1_DEST_CRC1_NEXT_DESC_PTR (DMA24_NEXT_DESC_PTR) +#define MDMA1_DEST_CRC1_START_ADDR (DMA24_START_ADDR) +#define MDMA1_DEST_CRC1_CONFIG (DMA24_CONFIG) +#define MDMA1_DEST_CRC1_X_COUNT (DMA24_X_COUNT) +#define MDMA1_DEST_CRC1_X_MODIFY (DMA24_X_MODIFY) +#define MDMA1_DEST_CRC1_Y_COUNT (DMA24_Y_COUNT) +#define MDMA1_DEST_CRC1_Y_MODIFY (DMA24_Y_MODIFY) +#define MDMA1_DEST_CRC1_CURR_DESC_PTR (DMA24_CURR_DESC_PTR) +#define MDMA1_DEST_CRC1_PREV_DESC_PTR (DMA24_PREV_DESC_PTR) +#define MDMA1_DEST_CRC1_CURR_ADDR (DMA24_CURR_ADDR) +#define MDMA1_DEST_CRC1_IRQ_STATUS (DMA24_IRQ_STATUS) +#define MDMA1_DEST_CRC1_CURR_X_COUNT (DMA24_CURR_X_COUNT) +#define MDMA1_DEST_CRC1_CURR_Y_COUNT (DMA24_CURR_Y_COUNT) +#define MDMA1_DEST_CRC1_BWL_COUNT (DMA24_BWL_COUNT) +#define MDMA1_DEST_CRC1_CURR_BWL_COUNT (DMA24_CURR_BWL_COUNT) +#define MDMA1_DEST_CRC1_BWM_COUNT (DMA24_BWM_COUNT) +#define MDMA1_DEST_CRC1_CURR_BWM_COUNT (DMA24_CURR_BWM_COUNT) +#define MDMA1_SRC_CRC1_NEXT_DESC_PTR (DMA23_NEXT_DESC_PTR) +#define MDMA1_SRC_CRC1_START_ADDR (DMA23_START_ADDR) +#define MDMA1_SRC_CRC1_CONFIG (DMA23_CONFIG) +#define MDMA1_SRC_CRC1_X_COUNT (DMA23_X_COUNT) +#define MDMA1_SRC_CRC1_X_MODIFY (DMA23_X_MODIFY) +#define MDMA1_SRC_CRC1_Y_COUNT (DMA23_Y_COUNT) +#define MDMA1_SRC_CRC1_Y_MODIFY (DMA23_Y_MODIFY) +#define MDMA1_SRC_CRC1_CURR_DESC_PTR (DMA23_CURR_DESC_PTR) +#define MDMA1_SRC_CRC1_PREV_DESC_PTR (DMA23_PREV_DESC_PTR) +#define MDMA1_SRC_CRC1_CURR_ADDR (DMA23_CURR_ADDR) +#define MDMA1_SRC_CRC1_IRQ_STATUS (DMA23_IRQ_STATUS) +#define MDMA1_SRC_CRC1_CURR_X_COUNT (DMA23_CURR_X_COUNT) +#define MDMA1_SRC_CRC1_CURR_Y_COUNT (DMA23_CURR_Y_COUNT) +#define MDMA1_SRC_CRC1_BWL_COUNT (DMA23_BWL_COUNT) +#define MDMA1_SRC_CRC1_CURR_BWL_COUNT (DMA23_CURR_BWL_COUNT) +#define MDMA1_SRC_CRC1_BWM_COUNT (DMA23_BWM_COUNT) +#define MDMA1_SRC_CRC1_CURR_BWM_COUNT (DMA23_CURR_BWM_COUNT) +#define MDMA2_DEST_NEXT_DESC_PTR (DMA26_NEXT_DESC_PTR) +#define MDMA2_DEST_START_ADDR (DMA26_START_ADDR) +#define MDMA2_DEST_CONFIG (DMA26_CONFIG) +#define MDMA2_DEST_X_COUNT (DMA26_X_COUNT) +#define MDMA2_DEST_X_MODIFY (DMA26_X_MODIFY) +#define MDMA2_DEST_Y_COUNT (DMA26_Y_COUNT) +#define MDMA2_DEST_Y_MODIFY (DMA26_Y_MODIFY) +#define MDMA2_DEST_CURR_DESC_PTR (DMA26_CURR_DESC_PTR) +#define MDMA2_DEST_PREV_DESC_PTR (DMA26_PREV_DESC_PTR) +#define MDMA2_DEST_CURR_ADDR (DMA26_CURR_ADDR) +#define MDMA2_DEST_IRQ_STATUS (DMA26_IRQ_STATUS) +#define MDMA2_DEST_CURR_X_COUNT (DMA26_CURR_X_COUNT) +#define MDMA2_DEST_CURR_Y_COUNT (DMA26_CURR_Y_COUNT) +#define MDMA2_DEST_BWL_COUNT (DMA26_BWL_COUNT) +#define MDMA2_DEST_CURR_BWL_COUNT (DMA26_CURR_BWL_COUNT) +#define MDMA2_DEST_BWM_COUNT (DMA26_BWM_COUNT) +#define MDMA2_DEST_CURR_BWM_COUNT (DMA26_CURR_BWM_COUNT) +#define MDMA2_SRC_NEXT_DESC_PTR (DMA25_NEXT_DESC_PTR) +#define MDMA2_SRC_START_ADDR (DMA25_START_ADDR) +#define MDMA2_SRC_CONFIG (DMA25_CONFIG) +#define MDMA2_SRC_X_COUNT (DMA25_X_COUNT) +#define MDMA2_SRC_X_MODIFY (DMA25_X_MODIFY) +#define MDMA2_SRC_Y_COUNT (DMA25_Y_COUNT) +#define MDMA2_SRC_Y_MODIFY (DMA25_Y_MODIFY) +#define MDMA2_SRC_CURR_DESC_PTR (DMA25_CURR_DESC_PTR) +#define MDMA2_SRC_PREV_DESC_PTR (DMA25_PREV_DESC_PTR) +#define MDMA2_SRC_CURR_ADDR (DMA25_CURR_ADDR) +#define MDMA2_SRC_IRQ_STATUS (DMA25_IRQ_STATUS) +#define MDMA2_SRC_CURR_X_COUNT (DMA25_CURR_X_COUNT) +#define MDMA2_SRC_CURR_Y_COUNT (DMA25_CURR_Y_COUNT) +#define MDMA2_SRC_BWL_COUNT (DMA25_BWL_COUNT) +#define MDMA2_SRC_CURR_BWL_COUNT (DMA25_CURR_BWL_COUNT) +#define MDMA2_SRC_BWM_COUNT (DMA25_BWM_COUNT) +#define MDMA2_SRC_CURR_BWM_COUNT (DMA25_CURR_BWM_COUNT) +#define MDMA3_DEST_NEXT_DESC_PTR (DMA28_NEXT_DESC_PTR) +#define MDMA3_DEST_START_ADDR (DMA28_START_ADDR) +#define MDMA3_DEST_CONFIG (DMA28_CONFIG) +#define MDMA3_DEST_X_COUNT (DMA28_X_COUNT) +#define MDMA3_DEST_X_MODIFY (DMA28_X_MODIFY) +#define MDMA3_DEST_Y_COUNT (DMA28_Y_COUNT) +#define MDMA3_DEST_Y_MODIFY (DMA28_Y_MODIFY) +#define MDMA3_DEST_CURR_DESC_PTR (DMA28_CURR_DESC_PTR) +#define MDMA3_DEST_PREV_DESC_PTR (DMA28_PREV_DESC_PTR) +#define MDMA3_DEST_CURR_ADDR (DMA28_CURR_ADDR) +#define MDMA3_DEST_IRQ_STATUS (DMA28_IRQ_STATUS) +#define MDMA3_DEST_CURR_X_COUNT (DMA28_CURR_X_COUNT) +#define MDMA3_DEST_CURR_Y_COUNT (DMA28_CURR_Y_COUNT) +#define MDMA3_DEST_BWL_COUNT (DMA28_BWL_COUNT) +#define MDMA3_DEST_CURR_BWL_COUNT (DMA28_CURR_BWL_COUNT) +#define MDMA3_DEST_BWM_COUNT (DMA28_BWM_COUNT) +#define MDMA3_DEST_CURR_BWM_COUNT (DMA28_CURR_BWM_COUNT) +#define MDMA3_SRC_NEXT_DESC_PTR (DMA27_NEXT_DESC_PTR) +#define MDMA3_SRC_START_ADDR (DMA27_START_ADDR) +#define MDMA3_SRC_CONFIG (DMA27_CONFIG) +#define MDMA3_SRC_X_COUNT (DMA27_X_COUNT) +#define MDMA3_SRC_X_MODIFY (DMA27_X_MODIFY) +#define MDMA3_SRC_Y_COUNT (DMA27_Y_COUNT) +#define MDMA3_SRC_Y_MODIFY (DMA27_Y_MODIFY) +#define MDMA3_SRC_CURR_DESC_PTR (DMA27_CURR_DESC_PTR) +#define MDMA3_SRC_PREV_DESC_PTR (DMA27_PREV_DESC_PTR) +#define MDMA3_SRC_CURR_ADDR (DMA27_CURR_ADDR) +#define MDMA3_SRC_IRQ_STATUS (DMA27_IRQ_STATUS) +#define MDMA3_SRC_CURR_X_COUNT (DMA27_CURR_X_COUNT) +#define MDMA3_SRC_CURR_Y_COUNT (DMA27_CURR_Y_COUNT) +#define MDMA3_SRC_BWL_COUNT (DMA27_BWL_COUNT) +#define MDMA3_SRC_CURR_BWL_COUNT (DMA27_CURR_BWL_COUNT) +#define MDMA3_SRC_BWM_COUNT (DMA27_BWM_COUNT) +#define MDMA3_SRC_CURR_BWM_COUNT (DMA27_CURR_BWM_COUNT) + + +/* ========================= + DMC Registers + ========================= */ + +/* ========================= + DMC0 + ========================= */ +#define DMC0_ID 0xFFC80000 /* DMC0 Identification Register */ +#define DMC0_CTL 0xFFC80004 /* DMC0 Control Register */ +#define DMC0_STAT 0xFFC80008 /* DMC0 Status Register */ +#define DMC0_EFFCTL 0xFFC8000C /* DMC0 Efficiency Controller */ +#define DMC0_PRIO 0xFFC80010 /* DMC0 Priority ID Register */ +#define DMC0_PRIOMSK 0xFFC80014 /* DMC0 Priority ID Mask */ +#define DMC0_CFG 0xFFC80040 /* DMC0 SDRAM Configuration */ +#define DMC0_TR0 0xFFC80044 /* DMC0 Timing Register 0 */ +#define DMC0_TR1 0xFFC80048 /* DMC0 Timing Register 1 */ +#define DMC0_TR2 0xFFC8004C /* DMC0 Timing Register 2 */ +#define DMC0_MSK 0xFFC8005C /* DMC0 Mode Register Mask */ +#define DMC0_MR 0xFFC80060 /* DMC0 Mode Shadow register */ +#define DMC0_EMR1 0xFFC80064 /* DMC0 EMR1 Shadow Register */ +#define DMC0_EMR2 0xFFC80068 /* DMC0 EMR2 Shadow Register */ +#define DMC0_EMR3 0xFFC8006C /* DMC0 EMR3 Shadow Register */ +#define DMC0_DLLCTL 0xFFC80080 /* DMC0 DLL Control Register */ +#define DMC0_PADCTL 0xFFC800C0 /* DMC0 PAD Control Register 0 */ + +#define DEVSZ_64 0x000 /* DMC External Bank Size = 64Mbit */ +#define DEVSZ_128 0x100 /* DMC External Bank Size = 128Mbit */ +#define DEVSZ_256 0x200 /* DMC External Bank Size = 256Mbit */ +#define DEVSZ_512 0x300 /* DMC External Bank Size = 512Mbit */ +#define DEVSZ_1G 0x400 /* DMC External Bank Size = 1Gbit */ +#define DEVSZ_2G 0x500 /* DMC External Bank Size = 2Gbit */ + + +/* ========================= + L2CTL Registers + ========================= */ + +/* ========================= + L2CTL0 + ========================= */ +#define L2CTL0_CTL 0xFFCA3000 /* L2CTL0 L2 Control Register */ +#define L2CTL0_ACTL_C0 0xFFCA3004 /* L2CTL0 L2 Core 0 Access Control Register */ +#define L2CTL0_ACTL_C1 0xFFCA3008 /* L2CTL0 L2 Core 1 Access Control Register */ +#define L2CTL0_ACTL_SYS 0xFFCA300C /* L2CTL0 L2 System Access Control Register */ +#define L2CTL0_STAT 0xFFCA3010 /* L2CTL0 L2 Status Register */ +#define L2CTL0_RPCR 0xFFCA3014 /* L2CTL0 L2 Read Priority Count Register */ +#define L2CTL0_WPCR 0xFFCA3018 /* L2CTL0 L2 Write Priority Count Register */ +#define L2CTL0_RFA 0xFFCA3024 /* L2CTL0 L2 Refresh Address Regsiter */ +#define L2CTL0_ERRADDR0 0xFFCA3040 /* L2CTL0 L2 Bank 0 ECC Error Address Register */ +#define L2CTL0_ERRADDR1 0xFFCA3044 /* L2CTL0 L2 Bank 1 ECC Error Address Register */ +#define L2CTL0_ERRADDR2 0xFFCA3048 /* L2CTL0 L2 Bank 2 ECC Error Address Register */ +#define L2CTL0_ERRADDR3 0xFFCA304C /* L2CTL0 L2 Bank 3 ECC Error Address Register */ +#define L2CTL0_ERRADDR4 0xFFCA3050 /* L2CTL0 L2 Bank 4 ECC Error Address Register */ +#define L2CTL0_ERRADDR5 0xFFCA3054 /* L2CTL0 L2 Bank 5 ECC Error Address Register */ +#define L2CTL0_ERRADDR6 0xFFCA3058 /* L2CTL0 L2 Bank 6 ECC Error Address Register */ +#define L2CTL0_ERRADDR7 0xFFCA305C /* L2CTL0 L2 Bank 7 ECC Error Address Register */ +#define L2CTL0_ET0 0xFFCA3080 /* L2CTL0 L2 AXI Error 0 Type Register */ +#define L2CTL0_EADDR0 0xFFCA3084 /* L2CTL0 L2 AXI Error 0 Address Register */ +#define L2CTL0_ET1 0xFFCA3088 /* L2CTL0 L2 AXI Error 1 Type Register */ +#define L2CTL0_EADDR1 0xFFCA308C /* L2CTL0 L2 AXI Error 1 Address Register */ + + +/* ========================= + SEC Registers + ========================= */ +/* ------------------------------------------------------------------------------------------------------------------------ + SEC Core Interface (SCI) Register Definitions + ------------------------------------------------------------------------------------------------------------------------ */ + +#define SEC_SCI_BASE 0xFFCA4400 +#define SEC_SCI_OFF 0x40 +#define SEC_CCTL 0x0 /* SEC Core Control Register n */ +#define SEC_CSTAT 0x4 /* SEC Core Status Register n */ +#define SEC_CPND 0x8 /* SEC Core Pending IRQ Register n */ +#define SEC_CACT 0xC /* SEC Core Active IRQ Register n */ +#define SEC_CPMSK 0x10 /* SEC Core IRQ Priority Mask Register n */ +#define SEC_CGMSK 0x14 /* SEC Core IRQ Group Mask Register n */ +#define SEC_CPLVL 0x18 /* SEC Core IRQ Priority Level Register n */ +#define SEC_CSID 0x1C /* SEC Core IRQ Source ID Register n */ + +#define bfin_read_SEC_SCI(n, reg) bfin_read32(SEC_SCI_BASE + (n) * SEC_SCI_OFF + reg) +#define bfin_write_SEC_SCI(n, reg, val) \ + bfin_write32(SEC_SCI_BASE + (n) * SEC_SCI_OFF + reg, val) + +/* ------------------------------------------------------------------------------------------------------------------------ + SEC Fault Management Interface (SFI) Register Definitions + ------------------------------------------------------------------------------------------------------------------------ */ +#define SEC_FCTL 0xFFCA4010 /* SEC Fault Control Register */ +#define SEC_FSTAT 0xFFCA4014 /* SEC Fault Status Register */ +#define SEC_FSID 0xFFCA4018 /* SEC Fault Source ID Register */ +#define SEC_FEND 0xFFCA401C /* SEC Fault End Register */ +#define SEC_FDLY 0xFFCA4020 /* SEC Fault Delay Register */ +#define SEC_FDLY_CUR 0xFFCA4024 /* SEC Fault Delay Current Register */ +#define SEC_FSRDLY 0xFFCA4028 /* SEC Fault System Reset Delay Register */ +#define SEC_FSRDLY_CUR 0xFFCA402C /* SEC Fault System Reset Delay Current Register */ +#define SEC_FCOPP 0xFFCA4030 /* SEC Fault COP Period Register */ +#define SEC_FCOPP_CUR 0xFFCA4034 /* SEC Fault COP Period Current Register */ + +/* ------------------------------------------------------------------------------------------------------------------------ + SEC Global Register Definitions + ------------------------------------------------------------------------------------------------------------------------ */ +#define SEC_GCTL 0xFFCA4000 /* SEC Global Control Register */ +#define SEC_GSTAT 0xFFCA4004 /* SEC Global Status Register */ +#define SEC_RAISE 0xFFCA4008 /* SEC Global Raise Register */ +#define SEC_END 0xFFCA400C /* SEC Global End Register */ + +/* ------------------------------------------------------------------------------------------------------------------------ + SEC Source Interface (SSI) Register Definitions + ------------------------------------------------------------------------------------------------------------------------ */ +#define SEC_SCTL0 0xFFCA4800 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL1 0xFFCA4808 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL2 0xFFCA4810 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL3 0xFFCA4818 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL4 0xFFCA4820 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL5 0xFFCA4828 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL6 0xFFCA4830 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL7 0xFFCA4838 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL8 0xFFCA4840 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL9 0xFFCA4848 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL10 0xFFCA4850 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL11 0xFFCA4858 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL12 0xFFCA4860 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL13 0xFFCA4868 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL14 0xFFCA4870 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL15 0xFFCA4878 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL16 0xFFCA4880 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL17 0xFFCA4888 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL18 0xFFCA4890 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL19 0xFFCA4898 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL20 0xFFCA48A0 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL21 0xFFCA48A8 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL22 0xFFCA48B0 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL23 0xFFCA48B8 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL24 0xFFCA48C0 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL25 0xFFCA48C8 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL26 0xFFCA48D0 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL27 0xFFCA48D8 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL28 0xFFCA48E0 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL29 0xFFCA48E8 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL30 0xFFCA48F0 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL31 0xFFCA48F8 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL32 0xFFCA4900 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL33 0xFFCA4908 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL34 0xFFCA4910 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL35 0xFFCA4918 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL36 0xFFCA4920 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL37 0xFFCA4928 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL38 0xFFCA4930 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL39 0xFFCA4938 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL40 0xFFCA4940 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL41 0xFFCA4948 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL42 0xFFCA4950 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL43 0xFFCA4958 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL44 0xFFCA4960 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL45 0xFFCA4968 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL46 0xFFCA4970 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL47 0xFFCA4978 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL48 0xFFCA4980 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL49 0xFFCA4988 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL50 0xFFCA4990 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL51 0xFFCA4998 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL52 0xFFCA49A0 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL53 0xFFCA49A8 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL54 0xFFCA49B0 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL55 0xFFCA49B8 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL56 0xFFCA49C0 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL57 0xFFCA49C8 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL58 0xFFCA49D0 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL59 0xFFCA49D8 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL60 0xFFCA49E0 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL61 0xFFCA49E8 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL62 0xFFCA49F0 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL63 0xFFCA49F8 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL64 0xFFCA4A00 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL65 0xFFCA4A08 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL66 0xFFCA4A10 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL67 0xFFCA4A18 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL68 0xFFCA4A20 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL69 0xFFCA4A28 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL70 0xFFCA4A30 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL71 0xFFCA4A38 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL72 0xFFCA4A40 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL73 0xFFCA4A48 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL74 0xFFCA4A50 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL75 0xFFCA4A58 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL76 0xFFCA4A60 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL77 0xFFCA4A68 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL78 0xFFCA4A70 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL79 0xFFCA4A78 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL80 0xFFCA4A80 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL81 0xFFCA4A88 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL82 0xFFCA4A90 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL83 0xFFCA4A98 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL84 0xFFCA4AA0 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL85 0xFFCA4AA8 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL86 0xFFCA4AB0 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL87 0xFFCA4AB8 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL88 0xFFCA4AC0 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL89 0xFFCA4AC8 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL90 0xFFCA4AD0 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL91 0xFFCA4AD8 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL92 0xFFCA4AE0 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL93 0xFFCA4AE8 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL94 0xFFCA4AF0 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL95 0xFFCA4AF8 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL96 0xFFCA4B00 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL97 0xFFCA4B08 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL98 0xFFCA4B10 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL99 0xFFCA4B18 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL100 0xFFCA4B20 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL101 0xFFCA4B28 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL102 0xFFCA4B30 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL103 0xFFCA4B38 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL104 0xFFCA4B40 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL105 0xFFCA4B48 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL106 0xFFCA4B50 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL107 0xFFCA4B58 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL108 0xFFCA4B60 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL109 0xFFCA4B68 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL110 0xFFCA4B70 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL111 0xFFCA4B78 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL112 0xFFCA4B80 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL113 0xFFCA4B88 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL114 0xFFCA4B90 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL115 0xFFCA4B98 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL116 0xFFCA4BA0 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL117 0xFFCA4BA8 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL118 0xFFCA4BB0 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL119 0xFFCA4BB8 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL120 0xFFCA4BC0 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL121 0xFFCA4BC8 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL122 0xFFCA4BD0 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL123 0xFFCA4BD8 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL124 0xFFCA4BE0 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL125 0xFFCA4BE8 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL126 0xFFCA4BF0 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL127 0xFFCA4BF8 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL128 0xFFCA4C00 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL129 0xFFCA4C08 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL130 0xFFCA4C10 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL131 0xFFCA4C18 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL132 0xFFCA4C20 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL133 0xFFCA4C28 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL134 0xFFCA4C30 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL135 0xFFCA4C38 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL136 0xFFCA4C40 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL137 0xFFCA4C48 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL138 0xFFCA4C50 /* SEC IRQ Source Control Register n */ +#define SEC_SCTL139 0xFFCA4C58 /* SEC IRQ Source Control Register n */ +#define SEC_SSTAT0 0xFFCA4804 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT1 0xFFCA480C /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT2 0xFFCA4814 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT3 0xFFCA481C /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT4 0xFFCA4824 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT5 0xFFCA482C /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT6 0xFFCA4834 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT7 0xFFCA483C /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT8 0xFFCA4844 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT9 0xFFCA484C /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT10 0xFFCA4854 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT11 0xFFCA485C /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT12 0xFFCA4864 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT13 0xFFCA486C /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT14 0xFFCA4874 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT15 0xFFCA487C /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT16 0xFFCA4884 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT17 0xFFCA488C /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT18 0xFFCA4894 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT19 0xFFCA489C /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT20 0xFFCA48A4 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT21 0xFFCA48AC /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT22 0xFFCA48B4 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT23 0xFFCA48BC /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT24 0xFFCA48C4 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT25 0xFFCA48CC /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT26 0xFFCA48D4 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT27 0xFFCA48DC /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT28 0xFFCA48E4 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT29 0xFFCA48EC /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT30 0xFFCA48F4 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT31 0xFFCA48FC /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT32 0xFFCA4904 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT33 0xFFCA490C /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT34 0xFFCA4914 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT35 0xFFCA491C /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT36 0xFFCA4924 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT37 0xFFCA492C /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT38 0xFFCA4934 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT39 0xFFCA493C /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT40 0xFFCA4944 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT41 0xFFCA494C /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT42 0xFFCA4954 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT43 0xFFCA495C /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT44 0xFFCA4964 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT45 0xFFCA496C /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT46 0xFFCA4974 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT47 0xFFCA497C /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT48 0xFFCA4984 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT49 0xFFCA498C /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT50 0xFFCA4994 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT51 0xFFCA499C /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT52 0xFFCA49A4 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT53 0xFFCA49AC /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT54 0xFFCA49B4 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT55 0xFFCA49BC /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT56 0xFFCA49C4 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT57 0xFFCA49CC /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT58 0xFFCA49D4 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT59 0xFFCA49DC /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT60 0xFFCA49E4 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT61 0xFFCA49EC /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT62 0xFFCA49F4 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT63 0xFFCA49FC /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT64 0xFFCA4A04 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT65 0xFFCA4A0C /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT66 0xFFCA4A14 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT67 0xFFCA4A1C /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT68 0xFFCA4A24 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT69 0xFFCA4A2C /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT70 0xFFCA4A34 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT71 0xFFCA4A3C /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT72 0xFFCA4A44 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT73 0xFFCA4A4C /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT74 0xFFCA4A54 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT75 0xFFCA4A5C /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT76 0xFFCA4A64 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT77 0xFFCA4A6C /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT78 0xFFCA4A74 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT79 0xFFCA4A7C /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT80 0xFFCA4A84 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT81 0xFFCA4A8C /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT82 0xFFCA4A94 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT83 0xFFCA4A9C /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT84 0xFFCA4AA4 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT85 0xFFCA4AAC /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT86 0xFFCA4AB4 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT87 0xFFCA4ABC /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT88 0xFFCA4AC4 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT89 0xFFCA4ACC /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT90 0xFFCA4AD4 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT91 0xFFCA4ADC /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT92 0xFFCA4AE4 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT93 0xFFCA4AEC /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT94 0xFFCA4AF4 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT95 0xFFCA4AFC /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT96 0xFFCA4B04 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT97 0xFFCA4B0C /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT98 0xFFCA4B14 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT99 0xFFCA4B1C /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT100 0xFFCA4B24 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT101 0xFFCA4B2C /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT102 0xFFCA4B34 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT103 0xFFCA4B3C /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT104 0xFFCA4B44 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT105 0xFFCA4B4C /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT106 0xFFCA4B54 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT107 0xFFCA4B5C /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT108 0xFFCA4B64 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT109 0xFFCA4B6C /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT110 0xFFCA4B74 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT111 0xFFCA4B7C /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT112 0xFFCA4B84 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT113 0xFFCA4B8C /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT114 0xFFCA4B94 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT115 0xFFCA4B9C /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT116 0xFFCA4BA4 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT117 0xFFCA4BAC /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT118 0xFFCA4BB4 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT119 0xFFCA4BBC /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT120 0xFFCA4BC4 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT121 0xFFCA4BCC /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT122 0xFFCA4BD4 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT123 0xFFCA4BDC /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT124 0xFFCA4BE4 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT125 0xFFCA4BEC /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT126 0xFFCA4BF4 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT127 0xFFCA4BFC /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT128 0xFFCA4C04 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT129 0xFFCA4C0C /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT130 0xFFCA4C14 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT131 0xFFCA4C1C /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT132 0xFFCA4C24 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT133 0xFFCA4C2C /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT134 0xFFCA4C34 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT135 0xFFCA4C3C /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT136 0xFFCA4C44 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT137 0xFFCA4C4C /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT138 0xFFCA4C54 /* SEC IRQ Source Status Register n */ +#define SEC_SSTAT139 0xFFCA4C5C /* SEC IRQ Source Status Register n */ + +/* ------------------------------------------------------------------------------------------------------------------------ + SEC_CCTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------ */ +#define SEC_CCTL_LOCK 0x80000000 /* LOCK: Lock */ +#define SEC_CCTL_NMI_EN 0x00010000 /* NMIEN: Enable */ +#define SEC_CCTL_WAITIDLE 0x00001000 /* WFI: Wait for Idle */ +#define SEC_CCTL_RESET 0x00000002 /* RESET: Reset */ +#define SEC_CCTL_EN 0x00000001 /* EN: Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------ + SEC_CSTAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------ */ +#define SEC_CSTAT_NMI 0x00010000 /* NMI Status */ +#define SEC_CSTAT_WAITING 0x00001000 /* WFI: Waiting */ +#define SEC_CSTAT_VALID_SID 0x00000400 /* SIDV: Valid */ +#define SEC_CSTAT_VALID_ACT 0x00000200 /* ACTV: Valid */ +#define SEC_CSTAT_VALID_PND 0x00000100 /* PNDV: Valid */ +#define SEC_CSTAT_ERRC 0x00000030 /* Error Cause */ +#define SEC_CSTAT_ACKERR 0x00000010 /* ERRC: Acknowledge Error */ +#define SEC_CSTAT_ERR 0x00000002 /* ERR: Error Occurred */ + +/* ------------------------------------------------------------------------------------------------------------------------ + SEC_CPND Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------ */ +#define SEC_CPND_PRIO 0x0000FF00 /* Highest Pending IRQ Priority */ +#define SEC_CPND_SID 0x000000FF /* Highest Pending IRQ Source ID */ + +/* ------------------------------------------------------------------------------------------------------------------------ + SEC_CACT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------ */ +#define SEC_CACT_PRIO 0x0000FF00 /* Highest Active IRQ Priority */ +#define SEC_CACT_SID 0x000000FF /* Highest Active IRQ Source ID */ + +/* ------------------------------------------------------------------------------------------------------------------------ + SEC_CPMSK Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------ */ +#define SEC_CPMSK_LOCK 0x80000000 /* LOCK: Lock */ +#define SEC_CPMSK_PRIO 0x000000FF /* IRQ Priority Mask */ + +/* ------------------------------------------------------------------------------------------------------------------------ + SEC_CGMSK Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------ */ +#define SEC_CGMSK_LOCK 0x80000000 /* LOCK: Lock */ +#define SEC_CGMSK_MASK 0x00000100 /* UGRP: Mask Ungrouped Sources */ +#define SEC_CGMSK_GRP 0x0000000F /* Grouped Mask */ + +/* ------------------------------------------------------------------------------------------------------------------------ + SEC_CPLVL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------ */ +#define SEC_CPLVL_LOCK 0x80000000 /* LOCK: Lock */ +#define SEC_CPLVL_PLVL 0x00000007 /* Priority Levels */ + +/* ------------------------------------------------------------------------------------------------------------------------ + SEC_CSID Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------ */ +#define SEC_CSID_SID 0x000000FF /* Source ID */ + + +/* ------------------------------------------------------------------------------------------------------------------------ + SEC_FCTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------ */ +#define SEC_FCTL_LOCK 0x80000000 /* LOCK: Lock */ +#define SEC_FCTL_FLTPND_MODE 0x00002000 /* TES: Fault Pending Mode */ +#define SEC_FCTL_COP_MODE 0x00001000 /* CMS: COP Mode */ +#define SEC_FCTL_FLTIN_EN 0x00000080 /* FIEN: Enable */ +#define SEC_FCTL_SYSRST_EN 0x00000040 /* SREN: Enable */ +#define SEC_FCTL_TRGOUT_EN 0x00000020 /* TOEN: Enable */ +#define SEC_FCTL_FLTOUT_EN 0x00000010 /* FOEN: Enable */ +#define SEC_FCTL_RESET 0x00000002 /* RESET: Reset */ +#define SEC_FCTL_EN 0x00000001 /* EN: Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------ + SEC_FSTAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------ */ +#define SEC_FSTAT_NXTFLT 0x00000400 /* NPND: Pending */ +#define SEC_FSTAT_FLTACT 0x00000200 /* ACT: Active Fault */ +#define SEC_FSTAT_FLTPND 0x00000100 /* PND: Pending */ +#define SEC_FSTAT_ERRC 0x00000030 /* Error Cause */ +#define SEC_FSTAT_ENDERR 0x00000020 /* ERRC: End Error */ +#define SEC_FSTAT_ERR 0x00000002 /* ERR: Error Occurred */ + +/* ------------------------------------------------------------------------------------------------------------------------ + SEC_FSID Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------ */ +#define SEC_FSID_SRC_EXTFLT 0x00010000 /* FEXT: Fault External */ +#define SEC_FSID_SID 0x000000FF /* Source ID */ + +/* ------------------------------------------------------------------------------------------------------------------------ + SEC_FEND Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------ */ +#define SEC_FEND_END_EXTFLT 0x00010000 /* FEXT: Fault External */ +#define SEC_FEND_SID 0x000000FF /* Source ID */ + + +/* ------------------------------------------------------------------------------------------------------------------------ + SEC_GCTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------ */ +#define SEC_GCTL_LOCK 0x80000000 /* Lock */ +#define SEC_GCTL_RESET 0x00000002 /* Reset */ +#define SEC_GCTL_EN 0x00000001 /* Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------ + SEC_GSTAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------ */ +#define SEC_GSTAT_LWERR 0x80000000 /* LWERR: Error Occurred */ +#define SEC_GSTAT_ADRERR 0x40000000 /* ADRERR: Error Occurred */ +#define SEC_GSTAT_SID 0x00FF0000 /* Source ID for SSI Error */ +#define SEC_GSTAT_SCI 0x00000F00 /* SCI ID for SCI Error */ +#define SEC_GSTAT_ERRC 0x00000030 /* Error Cause */ +#define SEC_GSTAT_SCIERR 0x00000010 /* ERRC: SCI Error */ +#define SEC_GSTAT_SSIERR 0x00000020 /* ERRC: SSI Error */ +#define SEC_GSTAT_ERR 0x00000002 /* ERR: Error Occurred */ + +/* ------------------------------------------------------------------------------------------------------------------------ + SEC_RAISE Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------ */ +#define SEC_RAISE_SID 0x000000FF /* Source ID IRQ Set to Pending */ + +/* ------------------------------------------------------------------------------------------------------------------------ + SEC_END Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------ */ +#define SEC_END_SID 0x000000FF /* Source ID IRQ to End */ + + +/* ------------------------------------------------------------------------------------------------------------------------ + SEC_SCTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------ */ +#define SEC_SCTL_LOCK 0x80000000 /* Lock */ +#define SEC_SCTL_CTG 0x0F000000 /* Core Target Select */ +#define SEC_SCTL_GRP 0x000F0000 /* Group Select */ +#define SEC_SCTL_PRIO 0x0000FF00 /* Priority Level Select */ +#define SEC_SCTL_ERR_EN 0x00000010 /* ERREN: Enable */ +#define SEC_SCTL_EDGE 0x00000008 /* ES: Edge Sensitive */ +#define SEC_SCTL_SRC_EN 0x00000004 /* SEN: Enable */ +#define SEC_SCTL_FAULT_EN 0x00000002 /* FEN: Enable */ +#define SEC_SCTL_INT_EN 0x00000001 /* IEN: Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------ + SEC_SSTAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------ */ +#define SEC_SSTAT_CHID 0x00FF0000 /* Channel ID */ +#define SEC_SSTAT_ACTIVE_SRC 0x00000200 /* ACT: Active Source */ +#define SEC_SSTAT_PENDING 0x00000100 /* PND: Pending */ +#define SEC_SSTAT_ERRC 0x00000030 /* Error Cause */ +#define SEC_SSTAT_ENDERR 0x00000020 /* ERRC: End Error */ +#define SEC_SSTAT_ERR 0x00000002 /* Error */ + + +/* ========================= + RCU Registers + ========================= */ + +/* ========================= + RCU0 + ========================= */ +#define RCU0_CTL 0xFFCA6000 /* RCU0 Control Register */ +#define RCU0_STAT 0xFFCA6004 /* RCU0 Status Register */ +#define RCU0_CRCTL 0xFFCA6008 /* RCU0 Core Reset Control Register */ +#define RCU0_CRSTAT 0xFFCA600C /* RCU0 Core Reset Status Register */ +#define RCU0_SIDIS 0xFFCA6010 /* RCU0 System Interface Disable Register */ +#define RCU0_SISTAT 0xFFCA6014 /* RCU0 System Interface Status Register */ +#define RCU0_SVECT_LCK 0xFFCA6018 /* RCU0 SVECT Lock Register */ +#define RCU0_BCODE 0xFFCA601C /* RCU0 Boot Code Register */ +#define RCU0_SVECT0 0xFFCA6020 /* RCU0 Software Vector Register n */ +#define RCU0_SVECT1 0xFFCA6024 /* RCU0 Software Vector Register n */ + + +/* ========================= + CGU0 + ========================= */ +#define CGU0_CTL 0xFFCA8000 /* CGU0 Control Register */ +#define CGU0_STAT 0xFFCA8004 /* CGU0 Status Register */ +#define CGU0_DIV 0xFFCA8008 /* CGU0 Divisor Register */ +#define CGU0_CLKOUTSEL 0xFFCA800C /* CGU0 CLKOUT Select Register */ + + +/* ========================= + DPM Registers + ========================= */ + +/* ========================= + DPM0 + ========================= */ +#define DPM0_CTL 0xFFCA9000 /* DPM0 Control Register */ +#define DPM0_STAT 0xFFCA9004 /* DPM0 Status Register */ +#define DPM0_CCBF_DIS 0xFFCA9008 /* DPM0 Core Clock Buffer Disable Register */ +#define DPM0_CCBF_EN 0xFFCA900C /* DPM0 Core Clock Buffer Enable Register */ +#define DPM0_CCBF_STAT 0xFFCA9010 /* DPM0 Core Clock Buffer Status Register */ +#define DPM0_CCBF_STAT_STKY 0xFFCA9014 /* DPM0 Core Clock Buffer Status Sticky Register */ +#define DPM0_SCBF_DIS 0xFFCA9018 /* DPM0 System Clock Buffer Disable Register */ +#define DPM0_WAKE_EN 0xFFCA901C /* DPM0 Wakeup Enable Register */ +#define DPM0_WAKE_POL 0xFFCA9020 /* DPM0 Wakeup Polarity Register */ +#define DPM0_WAKE_STAT 0xFFCA9024 /* DPM0 Wakeup Status Register */ +#define DPM0_HIB_DIS 0xFFCA9028 /* DPM0 Hibernate Disable Register */ +#define DPM0_PGCNTR 0xFFCA902C /* DPM0 Power Good Counter Register */ +#define DPM0_RESTORE0 0xFFCA9030 /* DPM0 Restore Register */ +#define DPM0_RESTORE1 0xFFCA9034 /* DPM0 Restore Register */ +#define DPM0_RESTORE2 0xFFCA9038 /* DPM0 Restore Register */ +#define DPM0_RESTORE3 0xFFCA903C /* DPM0 Restore Register */ +#define DPM0_RESTORE4 0xFFCA9040 /* DPM0 Restore Register */ +#define DPM0_RESTORE5 0xFFCA9044 /* DPM0 Restore Register */ +#define DPM0_RESTORE6 0xFFCA9048 /* DPM0 Restore Register */ +#define DPM0_RESTORE7 0xFFCA904C /* DPM0 Restore Register */ +#define DPM0_RESTORE8 0xFFCA9050 /* DPM0 Restore Register */ +#define DPM0_RESTORE9 0xFFCA9054 /* DPM0 Restore Register */ +#define DPM0_RESTORE10 0xFFCA9058 /* DPM0 Restore Register */ +#define DPM0_RESTORE11 0xFFCA905C /* DPM0 Restore Register */ +#define DPM0_RESTORE12 0xFFCA9060 /* DPM0 Restore Register */ +#define DPM0_RESTORE13 0xFFCA9064 /* DPM0 Restore Register */ +#define DPM0_RESTORE14 0xFFCA9068 /* DPM0 Restore Register */ +#define DPM0_RESTORE15 0xFFCA906C /* DPM0 Restore Register */ + + +/* ========================= + DBG Registers + ========================= */ + +/* USB register */ +#define USB_FADDR 0xFFCC1000 /* USB Device Address in Peripheral Mode */ +#define USB_POWER 0xFFCC1001 /* USB Power and Device Control */ +#define USB_INTRTX 0xFFCC1002 /* USB Transmit Interrupt */ +#define USB_INTRRX 0xFFCC1004 /* USB Receive Interrupts */ +#define USB_INTRTXE 0xFFCC1006 /* USB Transmit Interrupt Enable */ +#define USB_INTRRXE 0xFFCC1008 /* USB Receive Interrupt Enable */ +#define USB_INTRUSB 0xFFCC100A /* USB USB Interrupts */ +#define USB_INTRUSBE 0xFFCC100B /* USB USB Interrupt Enable */ +#define USB_FRAME 0xFFCC100C /* USB Frame Number */ +#define USB_INDEX 0xFFCC100E /* USB Index */ +#define USB_TESTMODE 0xFFCC100F /* USB Testmodes */ +#define USB_EPI_TXMAXP0 0xFFCC1010 /* USB Transmit Maximum Packet Length */ +#define USB_EP_NI0_TXMAXP 0xFFCC1010 +#define USB_EP0I_CSR0_H 0xFFCC1012 /* USB Config and Status EP0 */ +#define USB_EPI_TXCSR0_H 0xFFCC1012 /* USB Transmit Configuration and Status */ +#define USB_EP0I_CSR0_P 0xFFCC1012 /* USB Config and Status EP0 */ +#define USB_EPI_TXCSR0_P 0xFFCC1012 /* USB Transmit Configuration and Status */ +#define USB_EPI_RXMAXP0 0xFFCC1014 /* USB Receive Maximum Packet Length */ +#define USB_EPI_RXCSR0_H 0xFFCC1016 /* USB Receive Configuration and Status Register */ +#define USB_EPI_RXCSR0_P 0xFFCC1016 /* USB Receive Configuration and Status Register */ +#define USB_EP0I_CNT0 0xFFCC1018 /* USB Number of Received Bytes for Endpoint 0 */ +#define USB_EPI_RXCNT0 0xFFCC1018 /* USB Number of Byte Received */ +#define USB_EP0I_TYPE0 0xFFCC101A /* USB Speed for Endpoint 0 */ +#define USB_EPI_TXTYPE0 0xFFCC101A /* USB Transmit Type */ +#define USB_EP0I_NAKLIMIT0 0xFFCC101B /* USB NAK Response Timeout for Endpoint 0 */ +#define USB_EPI_TXINTERVAL0 0xFFCC101B /* USB Transmit Polling Interval */ +#define USB_EPI_RXTYPE0 0xFFCC101C /* USB Receive Type */ +#define USB_EPI_RXINTERVAL0 0xFFCC101D /* USB Receive Polling Interval */ +#define USB_EP0I_CFGDATA0 0xFFCC101F /* USB Configuration Information */ +#define USB_FIFOB0 0xFFCC1020 /* USB FIFO Data */ +#define USB_FIFOB1 0xFFCC1024 /* USB FIFO Data */ +#define USB_FIFOB2 0xFFCC1028 /* USB FIFO Data */ +#define USB_FIFOB3 0xFFCC102C /* USB FIFO Data */ +#define USB_FIFOB4 0xFFCC1030 /* USB FIFO Data */ +#define USB_FIFOB5 0xFFCC1034 /* USB FIFO Data */ +#define USB_FIFOB6 0xFFCC1038 /* USB FIFO Data */ +#define USB_FIFOB7 0xFFCC103C /* USB FIFO Data */ +#define USB_FIFOB8 0xFFCC1040 /* USB FIFO Data */ +#define USB_FIFOB9 0xFFCC1044 /* USB FIFO Data */ +#define USB_FIFOB10 0xFFCC1048 /* USB FIFO Data */ +#define USB_FIFOB11 0xFFCC104C /* USB FIFO Data */ +#define USB_FIFOH0 0xFFCC1020 /* USB FIFO Data */ +#define USB_FIFOH1 0xFFCC1024 /* USB FIFO Data */ +#define USB_FIFOH2 0xFFCC1028 /* USB FIFO Data */ +#define USB_FIFOH3 0xFFCC102C /* USB FIFO Data */ +#define USB_FIFOH4 0xFFCC1030 /* USB FIFO Data */ +#define USB_FIFOH5 0xFFCC1034 /* USB FIFO Data */ +#define USB_FIFOH6 0xFFCC1038 /* USB FIFO Data */ +#define USB_FIFOH7 0xFFCC103C /* USB FIFO Data */ +#define USB_FIFOH8 0xFFCC1040 /* USB FIFO Data */ +#define USB_FIFOH9 0xFFCC1044 /* USB FIFO Data */ +#define USB_FIFOH10 0xFFCC1048 /* USB FIFO Data */ +#define USB_FIFOH11 0xFFCC104C /* USB FIFO Data */ +#define USB_FIFO0 0xFFCC1020 /* USB FIFO Data */ +#define USB_EP0_FIFO 0xFFCC1020 +#define USB_FIFO1 0xFFCC1024 /* USB FIFO Data */ +#define USB_FIFO2 0xFFCC1028 /* USB FIFO Data */ +#define USB_FIFO3 0xFFCC102C /* USB FIFO Data */ +#define USB_FIFO4 0xFFCC1030 /* USB FIFO Data */ +#define USB_FIFO5 0xFFCC1034 /* USB FIFO Data */ +#define USB_FIFO6 0xFFCC1038 /* USB FIFO Data */ +#define USB_FIFO7 0xFFCC103C /* USB FIFO Data */ +#define USB_FIFO8 0xFFCC1040 /* USB FIFO Data */ +#define USB_FIFO9 0xFFCC1044 /* USB FIFO Data */ +#define USB_FIFO10 0xFFCC1048 /* USB FIFO Data */ +#define USB_FIFO11 0xFFCC104C /* USB FIFO Data */ +#define USB_OTG_DEV_CTL 0xFFCC1060 /* USB Device Control */ +#define USB_TXFIFOSZ 0xFFCC1062 /* USB Transmit FIFO Size */ +#define USB_RXFIFOSZ 0xFFCC1063 /* USB Receive FIFO Size */ +#define USB_TXFIFOADDR 0xFFCC1064 /* USB Transmit FIFO Address */ +#define USB_RXFIFOADDR 0xFFCC1066 /* USB Receive FIFO Address */ +#define USB_VENDSTAT 0xFFCC1068 /* USB Vendor Status */ +#define USB_HWVERS 0xFFCC106C /* USB Hardware Version */ +#define USB_EPINFO 0xFFCC1078 /* USB Endpoint Info */ +#define USB_RAMINFO 0xFFCC1079 /* USB Ram Information */ +#define USB_LINKINFO 0xFFCC107A /* USB Programmable Delay Values */ +#define USB_VPLEN 0xFFCC107B /* USB VBus Pulse Duration */ +#define USB_HS_EOF1 0xFFCC107C /* USB High Speed End of Frame Remaining */ +#define USB_FS_EOF1 0xFFCC107D /* USB Full Speed End of Frame Remaining */ +#define USB_LS_EOF1 0xFFCC107E /* USB Low Speed End of Frame Remaining */ +#define USB_SOFT_RST 0xFFCC107F /* USB Software Reset */ +#define USB_TXFUNCADDR0 0xFFCC1080 /* USB Transmit Function Address */ +#define USB_TXFUNCADDR1 0xFFCC1088 /* USB Transmit Function Address */ +#define USB_TXFUNCADDR2 0xFFCC1090 /* USB Transmit Function Address */ +#define USB_TXFUNCADDR3 0xFFCC1098 /* USB Transmit Function Address */ +#define USB_TXFUNCADDR4 0xFFCC10A0 /* USB Transmit Function Address */ +#define USB_TXFUNCADDR5 0xFFCC10A8 /* USB Transmit Function Address */ +#define USB_TXFUNCADDR6 0xFFCC10B0 /* USB Transmit Function Address */ +#define USB_TXFUNCADDR7 0xFFCC10B8 /* USB Transmit Function Address */ +#define USB_TXFUNCADDR8 0xFFCC10C0 /* USB Transmit Function Address */ +#define USB_TXFUNCADDR9 0xFFCC10C8 /* USB Transmit Function Address */ +#define USB_TXFUNCADDR10 0xFFCC10D0 /* USB Transmit Function Address */ +#define USB_TXFUNCADDR11 0xFFCC10D8 /* USB Transmit Function Address */ +#define USB_TXHUBADDR0 0xFFCC1082 /* USB Transmit Hub Address */ +#define USB_TXHUBADDR1 0xFFCC108A /* USB Transmit Hub Address */ +#define USB_TXHUBADDR2 0xFFCC1092 /* USB Transmit Hub Address */ +#define USB_TXHUBADDR3 0xFFCC109A /* USB Transmit Hub Address */ +#define USB_TXHUBADDR4 0xFFCC10A2 /* USB Transmit Hub Address */ +#define USB_TXHUBADDR5 0xFFCC10AA /* USB Transmit Hub Address */ +#define USB_TXHUBADDR6 0xFFCC10B2 /* USB Transmit Hub Address */ +#define USB_TXHUBADDR7 0xFFCC10BA /* USB Transmit Hub Address */ +#define USB_TXHUBADDR8 0xFFCC10C2 /* USB Transmit Hub Address */ +#define USB_TXHUBADDR9 0xFFCC10CA /* USB Transmit Hub Address */ +#define USB_TXHUBADDR10 0xFFCC10D2 /* USB Transmit Hub Address */ +#define USB_TXHUBADDR11 0xFFCC10DA /* USB Transmit Hub Address */ +#define USB_TXHUBPORT0 0xFFCC1083 /* USB Transmit Hub Port */ +#define USB_TXHUBPORT1 0xFFCC108B /* USB Transmit Hub Port */ +#define USB_TXHUBPORT2 0xFFCC1093 /* USB Transmit Hub Port */ +#define USB_TXHUBPORT3 0xFFCC109B /* USB Transmit Hub Port */ +#define USB_TXHUBPORT4 0xFFCC10A3 /* USB Transmit Hub Port */ +#define USB_TXHUBPORT5 0xFFCC10AB /* USB Transmit Hub Port */ +#define USB_TXHUBPORT6 0xFFCC10B3 /* USB Transmit Hub Port */ +#define USB_TXHUBPORT7 0xFFCC10BB /* USB Transmit Hub Port */ +#define USB_TXHUBPORT8 0xFFCC10C3 /* USB Transmit Hub Port */ +#define USB_TXHUBPORT9 0xFFCC10CB /* USB Transmit Hub Port */ +#define USB_TXHUBPORT10 0xFFCC10D3 /* USB Transmit Hub Port */ +#define USB_TXHUBPORT11 0xFFCC10DB /* USB Transmit Hub Port */ +#define USB_RXFUNCADDR0 0xFFCC1084 /* USB Receive Function Address */ +#define USB_RXFUNCADDR1 0xFFCC108C /* USB Receive Function Address */ +#define USB_RXFUNCADDR2 0xFFCC1094 /* USB Receive Function Address */ +#define USB_RXFUNCADDR3 0xFFCC109C /* USB Receive Function Address */ +#define USB_RXFUNCADDR4 0xFFCC10A4 /* USB Receive Function Address */ +#define USB_RXFUNCADDR5 0xFFCC10AC /* USB Receive Function Address */ +#define USB_RXFUNCADDR6 0xFFCC10B4 /* USB Receive Function Address */ +#define USB_RXFUNCADDR7 0xFFCC10BC /* USB Receive Function Address */ +#define USB_RXFUNCADDR8 0xFFCC10C4 /* USB Receive Function Address */ +#define USB_RXFUNCADDR9 0xFFCC10CC /* USB Receive Function Address */ +#define USB_RXFUNCADDR10 0xFFCC10D4 /* USB Receive Function Address */ +#define USB_RXFUNCADDR11 0xFFCC10DC /* USB Receive Function Address */ +#define USB_RXHUBADDR0 0xFFCC1086 /* USB Receive Hub Address */ +#define USB_RXHUBADDR1 0xFFCC108E /* USB Receive Hub Address */ +#define USB_RXHUBADDR2 0xFFCC1096 /* USB Receive Hub Address */ +#define USB_RXHUBADDR3 0xFFCC109E /* USB Receive Hub Address */ +#define USB_RXHUBADDR4 0xFFCC10A6 /* USB Receive Hub Address */ +#define USB_RXHUBADDR5 0xFFCC10AE /* USB Receive Hub Address */ +#define USB_RXHUBADDR6 0xFFCC10B6 /* USB Receive Hub Address */ +#define USB_RXHUBADDR7 0xFFCC10BE /* USB Receive Hub Address */ +#define USB_RXHUBADDR8 0xFFCC10C6 /* USB Receive Hub Address */ +#define USB_RXHUBADDR9 0xFFCC10CE /* USB Receive Hub Address */ +#define USB_RXHUBADDR10 0xFFCC10D6 /* USB Receive Hub Address */ +#define USB_RXHUBADDR11 0xFFCC10DE /* USB Receive Hub Address */ +#define USB_RXHUBPORT0 0xFFCC1087 /* USB Receive Hub Port */ +#define USB_RXHUBPORT1 0xFFCC108F /* USB Receive Hub Port */ +#define USB_RXHUBPORT2 0xFFCC1097 /* USB Receive Hub Port */ +#define USB_RXHUBPORT3 0xFFCC109F /* USB Receive Hub Port */ +#define USB_RXHUBPORT4 0xFFCC10A7 /* USB Receive Hub Port */ +#define USB_RXHUBPORT5 0xFFCC10AF /* USB Receive Hub Port */ +#define USB_RXHUBPORT6 0xFFCC10B7 /* USB Receive Hub Port */ +#define USB_RXHUBPORT7 0xFFCC10BF /* USB Receive Hub Port */ +#define USB_RXHUBPORT8 0xFFCC10C7 /* USB Receive Hub Port */ +#define USB_RXHUBPORT9 0xFFCC10CF /* USB Receive Hub Port */ +#define USB_RXHUBPORT10 0xFFCC10D7 /* USB Receive Hub Port */ +#define USB_RXHUBPORT11 0xFFCC10DF /* USB Receive Hub Port */ +#define USB_EP0_CSR0_H 0xFFCC1102 /* USB Config and Status EP0 */ +#define USB_EP0_CSR0_P 0xFFCC1102 /* USB Config and Status EP0 */ +#define USB_EP0_CNT0 0xFFCC1108 /* USB Number of Received Bytes for Endpoint 0 */ +#define USB_EP0_TYPE0 0xFFCC110A /* USB Speed for Endpoint 0 */ +#define USB_EP0_NAKLIMIT0 0xFFCC110B /* USB NAK Response Timeout for Endpoint 0 */ +#define USB_EP0_CFGDATA0 0xFFCC110F /* USB Configuration Information */ +#define USB_EP_TXMAXP0 0xFFCC1110 /* USB Transmit Maximum Packet Length */ +#define USB_EP_TXMAXP1 0xFFCC1120 /* USB Transmit Maximum Packet Length */ +#define USB_EP_TXMAXP2 0xFFCC1130 /* USB Transmit Maximum Packet Length */ +#define USB_EP_TXMAXP3 0xFFCC1140 /* USB Transmit Maximum Packet Length */ +#define USB_EP_TXMAXP4 0xFFCC1150 /* USB Transmit Maximum Packet Length */ +#define USB_EP_TXMAXP5 0xFFCC1160 /* USB Transmit Maximum Packet Length */ +#define USB_EP_TXMAXP6 0xFFCC1170 /* USB Transmit Maximum Packet Length */ +#define USB_EP_TXMAXP7 0xFFCC1180 /* USB Transmit Maximum Packet Length */ +#define USB_EP_TXMAXP8 0xFFCC1190 /* USB Transmit Maximum Packet Length */ +#define USB_EP_TXMAXP9 0xFFCC11A0 /* USB Transmit Maximum Packet Length */ +#define USB_EP_TXMAXP10 0xFFCC11B0 /* USB Transmit Maximum Packet Length */ +#define USB_EP_TXCSR0_H 0xFFCC1112 /* USB Transmit Configuration and Status */ +#define USB_EP_TXCSR1_H 0xFFCC1122 /* USB Transmit Configuration and Status */ +#define USB_EP_TXCSR2_H 0xFFCC1132 /* USB Transmit Configuration and Status */ +#define USB_EP_TXCSR3_H 0xFFCC1142 /* USB Transmit Configuration and Status */ +#define USB_EP_TXCSR4_H 0xFFCC1152 /* USB Transmit Configuration and Status */ +#define USB_EP_TXCSR5_H 0xFFCC1162 /* USB Transmit Configuration and Status */ +#define USB_EP_TXCSR6_H 0xFFCC1172 /* USB Transmit Configuration and Status */ +#define USB_EP_TXCSR7_H 0xFFCC1182 /* USB Transmit Configuration and Status */ +#define USB_EP_TXCSR8_H 0xFFCC1192 /* USB Transmit Configuration and Status */ +#define USB_EP_TXCSR9_H 0xFFCC11A2 /* USB Transmit Configuration and Status */ +#define USB_EP_TXCSR10_H 0xFFCC11B2 /* USB Transmit Configuration and Status */ +#define USB_EP_TXCSR0_P 0xFFCC1112 /* USB Transmit Configuration and Status */ +#define USB_EP_TXCSR1_P 0xFFCC1122 /* USB Transmit Configuration and Status */ +#define USB_EP_TXCSR2_P 0xFFCC1132 /* USB Transmit Configuration and Status */ +#define USB_EP_TXCSR3_P 0xFFCC1142 /* USB Transmit Configuration and Status */ +#define USB_EP_TXCSR4_P 0xFFCC1152 /* USB Transmit Configuration and Status */ +#define USB_EP_TXCSR5_P 0xFFCC1162 /* USB Transmit Configuration and Status */ +#define USB_EP_TXCSR6_P 0xFFCC1172 /* USB Transmit Configuration and Status */ +#define USB_EP_TXCSR7_P 0xFFCC1182 /* USB Transmit Configuration and Status */ +#define USB_EP_TXCSR8_P 0xFFCC1192 /* USB Transmit Configuration and Status */ +#define USB_EP_TXCSR9_P 0xFFCC11A2 /* USB Transmit Configuration and Status */ +#define USB_EP_TXCSR10_P 0xFFCC11B2 /* USB Transmit Configuration and Status */ +#define USB_EP_RXMAXP0 0xFFCC1114 /* USB Receive Maximum Packet Length */ +#define USB_EP_RXMAXP1 0xFFCC1124 /* USB Receive Maximum Packet Length */ +#define USB_EP_RXMAXP2 0xFFCC1134 /* USB Receive Maximum Packet Length */ +#define USB_EP_RXMAXP3 0xFFCC1144 /* USB Receive Maximum Packet Length */ +#define USB_EP_RXMAXP4 0xFFCC1154 /* USB Receive Maximum Packet Length */ +#define USB_EP_RXMAXP5 0xFFCC1164 /* USB Receive Maximum Packet Length */ +#define USB_EP_RXMAXP6 0xFFCC1174 /* USB Receive Maximum Packet Length */ +#define USB_EP_RXMAXP7 0xFFCC1184 /* USB Receive Maximum Packet Length */ +#define USB_EP_RXMAXP8 0xFFCC1194 /* USB Receive Maximum Packet Length */ +#define USB_EP_RXMAXP9 0xFFCC11A4 /* USB Receive Maximum Packet Length */ +#define USB_EP_RXMAXP10 0xFFCC11B4 /* USB Receive Maximum Packet Length */ +#define USB_EP_RXCSR0_H 0xFFCC1116 /* USB Receive Configuration and Status Register */ +#define USB_EP_RXCSR1_H 0xFFCC1126 /* USB Receive Configuration and Status Register */ +#define USB_EP_RXCSR2_H 0xFFCC1136 /* USB Receive Configuration and Status Register */ +#define USB_EP_RXCSR3_H 0xFFCC1146 /* USB Receive Configuration and Status Register */ +#define USB_EP_RXCSR4_H 0xFFCC1156 /* USB Receive Configuration and Status Register */ +#define USB_EP_RXCSR5_H 0xFFCC1166 /* USB Receive Configuration and Status Register */ +#define USB_EP_RXCSR6_H 0xFFCC1176 /* USB Receive Configuration and Status Register */ +#define USB_EP_RXCSR7_H 0xFFCC1186 /* USB Receive Configuration and Status Register */ +#define USB_EP_RXCSR8_H 0xFFCC1196 /* USB Receive Configuration and Status Register */ +#define USB_EP_RXCSR9_H 0xFFCC11A6 /* USB Receive Configuration and Status Register */ +#define USB_EP_RXCSR10_H 0xFFCC11B6 /* USB Receive Configuration and Status Register */ +#define USB_EP_RXCSR0_P 0xFFCC1116 /* USB Receive Configuration and Status Register */ +#define USB_EP_RXCSR1_P 0xFFCC1126 /* USB Receive Configuration and Status Register */ +#define USB_EP_RXCSR2_P 0xFFCC1136 /* USB Receive Configuration and Status Register */ +#define USB_EP_RXCSR3_P 0xFFCC1146 /* USB Receive Configuration and Status Register */ +#define USB_EP_RXCSR4_P 0xFFCC1156 /* USB Receive Configuration and Status Register */ +#define USB_EP_RXCSR5_P 0xFFCC1166 /* USB Receive Configuration and Status Register */ +#define USB_EP_RXCSR6_P 0xFFCC1176 /* USB Receive Configuration and Status Register */ +#define USB_EP_RXCSR7_P 0xFFCC1186 /* USB Receive Configuration and Status Register */ +#define USB_EP_RXCSR8_P 0xFFCC1196 /* USB Receive Configuration and Status Register */ +#define USB_EP_RXCSR9_P 0xFFCC11A6 /* USB Receive Configuration and Status Register */ +#define USB_EP_RXCSR10_P 0xFFCC11B6 /* USB Receive Configuration and Status Register */ +#define USB_EP_RXCNT0 0xFFCC1118 /* USB Number of Byte Received */ +#define USB_EP_RXCNT1 0xFFCC1128 /* USB Number of Byte Received */ +#define USB_EP_RXCNT2 0xFFCC1138 /* USB Number of Byte Received */ +#define USB_EP_RXCNT3 0xFFCC1148 /* USB Number of Byte Received */ +#define USB_EP_RXCNT4 0xFFCC1158 /* USB Number of Byte Received */ +#define USB_EP_RXCNT5 0xFFCC1168 /* USB Number of Byte Received */ +#define USB_EP_RXCNT6 0xFFCC1178 /* USB Number of Byte Received */ +#define USB_EP_RXCNT7 0xFFCC1188 /* USB Number of Byte Received */ +#define USB_EP_RXCNT8 0xFFCC1198 /* USB Number of Byte Received */ +#define USB_EP_RXCNT9 0xFFCC11A8 /* USB Number of Byte Received */ +#define USB_EP_RXCNT10 0xFFCC11B8 /* USB Number of Byte Received */ +#define USB_EP_TXTYPE0 0xFFCC111A /* USB Transmit Type */ +#define USB_EP_TXTYPE1 0xFFCC112A /* USB Transmit Type */ +#define USB_EP_TXTYPE2 0xFFCC113A /* USB Transmit Type */ +#define USB_EP_TXTYPE3 0xFFCC114A /* USB Transmit Type */ +#define USB_EP_TXTYPE4 0xFFCC115A /* USB Transmit Type */ +#define USB_EP_TXTYPE5 0xFFCC116A /* USB Transmit Type */ +#define USB_EP_TXTYPE6 0xFFCC117A /* USB Transmit Type */ +#define USB_EP_TXTYPE7 0xFFCC118A /* USB Transmit Type */ +#define USB_EP_TXTYPE8 0xFFCC119A /* USB Transmit Type */ +#define USB_EP_TXTYPE9 0xFFCC11AA /* USB Transmit Type */ +#define USB_EP_TXTYPE10 0xFFCC11BA /* USB Transmit Type */ +#define USB_EP_TXINTERVAL0 0xFFCC111B /* USB Transmit Polling Interval */ +#define USB_EP_TXINTERVAL1 0xFFCC112B /* USB Transmit Polling Interval */ +#define USB_EP_TXINTERVAL2 0xFFCC113B /* USB Transmit Polling Interval */ +#define USB_EP_TXINTERVAL3 0xFFCC114B /* USB Transmit Polling Interval */ +#define USB_EP_TXINTERVAL4 0xFFCC115B /* USB Transmit Polling Interval */ +#define USB_EP_TXINTERVAL5 0xFFCC116B /* USB Transmit Polling Interval */ +#define USB_EP_TXINTERVAL6 0xFFCC117B /* USB Transmit Polling Interval */ +#define USB_EP_TXINTERVAL7 0xFFCC118B /* USB Transmit Polling Interval */ +#define USB_EP_TXINTERVAL8 0xFFCC119B /* USB Transmit Polling Interval */ +#define USB_EP_TXINTERVAL9 0xFFCC11AB /* USB Transmit Polling Interval */ +#define USB_EP_TXINTERVAL10 0xFFCC11BB /* USB Transmit Polling Interval */ +#define USB_EP_RXTYPE0 0xFFCC111C /* USB Receive Type */ +#define USB_EP_RXTYPE1 0xFFCC112C /* USB Receive Type */ +#define USB_EP_RXTYPE2 0xFFCC113C /* USB Receive Type */ +#define USB_EP_RXTYPE3 0xFFCC114C /* USB Receive Type */ +#define USB_EP_RXTYPE4 0xFFCC115C /* USB Receive Type */ +#define USB_EP_RXTYPE5 0xFFCC116C /* USB Receive Type */ +#define USB_EP_RXTYPE6 0xFFCC117C /* USB Receive Type */ +#define USB_EP_RXTYPE7 0xFFCC118C /* USB Receive Type */ +#define USB_EP_RXTYPE8 0xFFCC119C /* USB Receive Type */ +#define USB_EP_RXTYPE9 0xFFCC11AC /* USB Receive Type */ +#define USB_EP_RXTYPE10 0xFFCC11BC /* USB Receive Type */ +#define USB_EP_RXINTERVAL0 0xFFCC111D /* USB Receive Polling Interval */ +#define USB_EP_RXINTERVAL1 0xFFCC112D /* USB Receive Polling Interval */ +#define USB_EP_RXINTERVAL2 0xFFCC113D /* USB Receive Polling Interval */ +#define USB_EP_RXINTERVAL3 0xFFCC114D /* USB Receive Polling Interval */ +#define USB_EP_RXINTERVAL4 0xFFCC115D /* USB Receive Polling Interval */ +#define USB_EP_RXINTERVAL5 0xFFCC116D /* USB Receive Polling Interval */ +#define USB_EP_RXINTERVAL6 0xFFCC117D /* USB Receive Polling Interval */ +#define USB_EP_RXINTERVAL7 0xFFCC118D /* USB Receive Polling Interval */ +#define USB_EP_RXINTERVAL8 0xFFCC119D /* USB Receive Polling Interval */ +#define USB_EP_RXINTERVAL9 0xFFCC11AD /* USB Receive Polling Interval */ +#define USB_EP_RXINTERVAL10 0xFFCC11BD /* USB Receive Polling Interval */ +#define USB_DMA_IRQ 0xFFCC1200 /* USB Interrupt Register */ +#define USB_DMA_CTL0 0xFFCC1204 /* USB DMA Control */ +#define USB_DMA_CTL1 0xFFCC1214 /* USB DMA Control */ +#define USB_DMA_CTL2 0xFFCC1224 /* USB DMA Control */ +#define USB_DMA_CTL3 0xFFCC1234 /* USB DMA Control */ +#define USB_DMA_CTL4 0xFFCC1244 /* USB DMA Control */ +#define USB_DMA_CTL5 0xFFCC1254 /* USB DMA Control */ +#define USB_DMA_CTL6 0xFFCC1264 /* USB DMA Control */ +#define USB_DMA_CTL7 0xFFCC1274 /* USB DMA Control */ +#define USB_DMA_ADDR0 0xFFCC1208 /* USB DMA Address */ +#define USB_DMA_ADDR1 0xFFCC1218 /* USB DMA Address */ +#define USB_DMA_ADDR2 0xFFCC1228 /* USB DMA Address */ +#define USB_DMA_ADDR3 0xFFCC1238 /* USB DMA Address */ +#define USB_DMA_ADDR4 0xFFCC1248 /* USB DMA Address */ +#define USB_DMA_ADDR5 0xFFCC1258 /* USB DMA Address */ +#define USB_DMA_ADDR6 0xFFCC1268 /* USB DMA Address */ +#define USB_DMA_ADDR7 0xFFCC1278 /* USB DMA Address */ +#define USB_DMA_CNT0 0xFFCC120C /* USB DMA Count */ +#define USB_DMA_CNT1 0xFFCC121C /* USB DMA Count */ +#define USB_DMA_CNT2 0xFFCC122C /* USB DMA Count */ +#define USB_DMA_CNT3 0xFFCC123C /* USB DMA Count */ +#define USB_DMA_CNT4 0xFFCC124C /* USB DMA Count */ +#define USB_DMA_CNT5 0xFFCC125C /* USB DMA Count */ +#define USB_DMA_CNT6 0xFFCC126C /* USB DMA Count */ +#define USB_DMA_CNT7 0xFFCC127C /* USB DMA Count */ +#define USB_RQPKTCNT0 0xFFCC1300 /* USB Request Packet Count */ +#define USB_RQPKTCNT1 0xFFCC1304 /* USB Request Packet Count */ +#define USB_RQPKTCNT2 0xFFCC1308 /* USB Request Packet Count */ +#define USB_RQPKTCNT3 0xFFCC130C /* USB Request Packet Count */ +#define USB_RQPKTCNT4 0xFFCC1310 /* USB Request Packet Count */ +#define USB_RQPKTCNT5 0xFFCC1314 /* USB Request Packet Count */ +#define USB_RQPKTCNT6 0xFFCC1318 /* USB Request Packet Count */ +#define USB_RQPKTCNT7 0xFFCC131C /* USB Request Packet Count */ +#define USB_RQPKTCNT8 0xFFCC1320 /* USB Request Packet Count */ +#define USB_RQPKTCNT9 0xFFCC1324 /* USB Request Packet Count */ +#define USB_RQPKTCNT10 0xFFCC1328 /* USB Request Packet Count */ +#define USB_CT_UCH 0xFFCC1344 /* USB Chirp Timeout */ +#define USB_CT_HHSRTN 0xFFCC1346 /* USB High Speed Resume Return to Normal */ +#define USB_CT_HSBT 0xFFCC1348 /* USB High Speed Timeout */ +#define USB_LPM_ATTR 0xFFCC1360 /* USB LPM Attribute */ +#define USB_LPM_CTL 0xFFCC1362 /* USB LPM Control */ +#define USB_LPM_IEN 0xFFCC1363 /* USB LPM Interrupt Enable */ +#define USB_LPM_IRQ 0xFFCC1364 /* USB LPM Interrupt */ +#define USB_LPM_FADDR 0xFFCC1365 /* USB LPM Function Address */ +#define USB_VBUS_CTL 0xFFCC1380 /* USB VBus Control */ +#define USB_BAT_CHG 0xFFCC1381 /* USB Battery Charging */ +#define USB_PHY_CTL 0xFFCC1394 /* USB PHY Control */ +#define USB_TESTCTL 0xFFCC1397 /* USB Test Control */ +#define USB_PLL_OSC 0xFFCC1398 /* USB PLL and Oscillator Control */ + + + +/* ========================= + CHIPID + ========================= */ + +#define CHIPID 0xffc00014 +/* CHIPID Masks */ +#define CHIPID_VERSION 0xF0000000 +#define CHIPID_FAMILY 0x0FFFF000 +#define CHIPID_MANUFACTURE 0x00000FFE + + +#endif /* _DEF_BF60X_H */ diff --git a/arch/blackfin/mach-bf609/include/mach/dma.h b/arch/blackfin/mach-bf609/include/mach/dma.h new file mode 100644 index 000000000000..872d141ca119 --- /dev/null +++ b/arch/blackfin/mach-bf609/include/mach/dma.h @@ -0,0 +1,116 @@ +/* mach/dma.h - arch-specific DMA defines + * + * Copyright 2011 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _MACH_DMA_H_ +#define _MACH_DMA_H_ + +#define CH_SPORT0_TX 0 +#define CH_SPORT0_RX 1 +#define CH_SPORT1_TX 2 +#define CH_SPORT1_RX 3 +#define CH_SPORT2_TX 4 +#define CH_SPORT2_RX 5 +#define CH_SPI0_TX 6 +#define CH_SPI0_RX 7 +#define CH_SPI1_TX 8 +#define CH_SPI1_RX 9 +#define CH_RSI 10 +#define CH_SDU 11 +#define CH_LP0 13 +#define CH_LP1 14 +#define CH_LP2 15 +#define CH_LP3 16 +#define CH_UART0_TX 17 +#define CH_UART0_RX 18 +#define CH_UART1_TX 19 +#define CH_UART1_RX 20 +#define CH_MEM_STREAM0_SRC_CRC0 21 +#define CH_MEM_STREAM0_SRC CH_MEM_STREAM0_SRC_CRC0 +#define CH_MEM_STREAM0_DEST_CRC0 22 +#define CH_MEM_STREAM0_DEST CH_MEM_STREAM0_DEST_CRC0 +#define CH_MEM_STREAM1_SRC_CRC1 23 +#define CH_MEM_STREAM1_SRC CH_MEM_STREAM1_SRC_CRC1 +#define CH_MEM_STREAM1_DEST_CRC1 24 +#define CH_MEM_STREAM1_DEST CH_MEM_STREAM1_DEST_CRC1 +#define CH_MEM_STREAM2_SRC 25 +#define CH_MEM_STREAM2_DEST 26 +#define CH_MEM_STREAM3_SRC 27 +#define CH_MEM_STREAM3_DEST 28 +#define CH_EPPI0_CH0 29 +#define CH_EPPI0_CH1 30 +#define CH_EPPI1_CH0 31 +#define CH_EPPI1_CH1 32 +#define CH_EPPI2_CH0 33 +#define CH_EPPI2_CH1 34 +#define CH_PIXC_CH0 35 +#define CH_PIXC_CH1 36 +#define CH_PIXC_CH2 37 +#define CH_PVP_CPDOB 38 +#define CH_PVP_CPDOC 39 +#define CH_PVP_CPSTAT 40 +#define CH_PVP_CPCI 41 +#define CH_PVP_MPDO 42 +#define CH_PVP_MPDI 43 +#define CH_PVP_MPSTAT 44 +#define CH_PVP_MPCI 45 +#define CH_PVP_CPDOA 46 + +#define MAX_DMA_CHANNELS 47 +#define MAX_DMA_SUSPEND_CHANNELS 0 +#define DMA_MMR_SIZE_32 + +#define bfin_read_MDMA_S0_CONFIG bfin_read_MDMA0_SRC_CRC0_CONFIG +#define bfin_write_MDMA_S0_CONFIG bfin_write_MDMA0_SRC_CRC0_CONFIG +#define bfin_read_MDMA_S0_IRQ_STATUS bfin_read_MDMA0_SRC_CRC0_IRQ_STATUS +#define bfin_write_MDMA_S0_IRQ_STATUS bfin_write_MDMA0_SRC_CRC0_IRQ_STATUS +#define bfin_write_MDMA_S0_START_ADDR bfin_write_MDMA0_SRC_CRC0_START_ADDR +#define bfin_write_MDMA_S0_X_COUNT bfin_write_MDMA0_SRC_CRC0_X_COUNT +#define bfin_write_MDMA_S0_X_MODIFY bfin_write_MDMA0_SRC_CRC0_X_MODIFY +#define bfin_write_MDMA_S0_Y_COUNT bfin_write_MDMA0_SRC_CRC0_Y_COUNT +#define bfin_write_MDMA_S0_Y_MODIFY bfin_write_MDMA0_SRC_CRC0_Y_MODIFY +#define bfin_read_MDMA_D0_CONFIG bfin_read_MDMA0_DEST_CRC0_CONFIG +#define bfin_write_MDMA_D0_CONFIG bfin_write_MDMA0_DEST_CRC0_CONFIG +#define bfin_read_MDMA_D0_IRQ_STATUS bfin_read_MDMA0_DEST_CRC0_IRQ_STATUS +#define bfin_write_MDMA_D0_IRQ_STATUS bfin_write_MDMA0_DEST_CRC0_IRQ_STATUS +#define bfin_write_MDMA_D0_START_ADDR bfin_write_MDMA0_DEST_CRC0_START_ADDR +#define bfin_write_MDMA_D0_X_COUNT bfin_write_MDMA0_DEST_CRC0_X_COUNT +#define bfin_write_MDMA_D0_X_MODIFY bfin_write_MDMA0_DEST_CRC0_X_MODIFY +#define bfin_write_MDMA_D0_Y_COUNT bfin_write_MDMA0_DEST_CRC0_Y_COUNT +#define bfin_write_MDMA_D0_Y_MODIFY bfin_write_MDMA0_DEST_CRC0_Y_MODIFY + +#define bfin_read_MDMA_S1_CONFIG bfin_read_MDMA1_SRC_CRC1_CONFIG +#define bfin_write_MDMA_S1_CONFIG bfin_write_MDMA1_SRC_CRC1_CONFIG +#define bfin_read_MDMA_D1_CONFIG bfin_read_MDMA1_DEST_CRC1_CONFIG +#define bfin_write_MDMA_D1_CONFIG bfin_write_MDMA1_DEST_CRC1_CONFIG +#define bfin_read_MDMA_D1_IRQ_STATUS bfin_read_MDMA1_DEST_CRC1_IRQ_STATUS +#define bfin_write_MDMA_D1_IRQ_STATUS bfin_write_MDMA1_DEST_CRC1_IRQ_STATUS + +#define bfin_read_MDMA_S3_CONFIG bfin_read_MDMA3_SRC_CONFIG +#define bfin_write_MDMA_S3_CONFIG bfin_write_MDMA3_SRC_CONFIG +#define bfin_read_MDMA_S3_IRQ_STATUS bfin_read_MDMA3_SRC_IRQ_STATUS +#define bfin_write_MDMA_S3_IRQ_STATUS bfin_write_MDMA3_SRC_IRQ_STATUS +#define bfin_write_MDMA_S3_START_ADDR bfin_write_MDMA3_SRC_START_ADDR +#define bfin_write_MDMA_S3_X_COUNT bfin_write_MDMA3_SRC_X_COUNT +#define bfin_write_MDMA_S3_X_MODIFY bfin_write_MDMA3_SRC_X_MODIFY +#define bfin_write_MDMA_S3_Y_COUNT bfin_write_MDMA3_SRC_Y_COUNT +#define bfin_write_MDMA_S3_Y_MODIFY bfin_write_MDMA3_SRC_Y_MODIFY +#define bfin_read_MDMA_D3_CONFIG bfin_read_MDMA3_DEST_CONFIG +#define bfin_write_MDMA_D3_CONFIG bfin_write_MDMA3_DEST_CONFIG +#define bfin_read_MDMA_D3_IRQ_STATUS bfin_read_MDMA3_DEST_IRQ_STATUS +#define bfin_write_MDMA_D3_IRQ_STATUS bfin_write_MDMA3_DEST_IRQ_STATUS +#define bfin_write_MDMA_D3_START_ADDR bfin_write_MDMA3_DEST_START_ADDR +#define bfin_write_MDMA_D3_X_COUNT bfin_write_MDMA3_DEST_X_COUNT +#define bfin_write_MDMA_D3_X_MODIFY bfin_write_MDMA3_DEST_X_MODIFY +#define bfin_write_MDMA_D3_Y_COUNT bfin_write_MDMA3_DEST_Y_COUNT +#define bfin_write_MDMA_D3_Y_MODIFY bfin_write_MDMA3_DEST_Y_MODIFY + +#define MDMA_S0_NEXT_DESC_PTR MDMA0_SRC_CRC0_NEXT_DESC_PTR +#define MDMA_D0_NEXT_DESC_PTR MDMA0_DEST_CRC0_NEXT_DESC_PTR +#define MDMA_S1_NEXT_DESC_PTR MDMA1_SRC_CRC1_NEXT_DESC_PTR +#define MDMA_D1_NEXT_DESC_PTR MDMA1_DEST_CRC1_NEXT_DESC_PTR + +#endif diff --git a/arch/blackfin/mach-bf609/include/mach/gpio.h b/arch/blackfin/mach-bf609/include/mach/gpio.h new file mode 100644 index 000000000000..127586b1e04a --- /dev/null +++ b/arch/blackfin/mach-bf609/include/mach/gpio.h @@ -0,0 +1,171 @@ +/* + * Copyright 2007-2009 Analog Devices Inc. + * Licensed under the GPL-2 or later. + */ + +#ifndef _MACH_GPIO_H_ +#define _MACH_GPIO_H_ + +#define MAX_BLACKFIN_GPIOS 112 + +#define GPIO_PA0 0 +#define GPIO_PA1 1 +#define GPIO_PA2 2 +#define GPIO_PA3 3 +#define GPIO_PA4 4 +#define GPIO_PA5 5 +#define GPIO_PA6 6 +#define GPIO_PA7 7 +#define GPIO_PA8 8 +#define GPIO_PA9 9 +#define GPIO_PA10 10 +#define GPIO_PA11 11 +#define GPIO_PA12 12 +#define GPIO_PA13 13 +#define GPIO_PA14 14 +#define GPIO_PA15 15 +#define GPIO_PB0 16 +#define GPIO_PB1 17 +#define GPIO_PB2 18 +#define GPIO_PB3 19 +#define GPIO_PB4 20 +#define GPIO_PB5 21 +#define GPIO_PB6 22 +#define GPIO_PB7 23 +#define GPIO_PB8 24 +#define GPIO_PB9 25 +#define GPIO_PB10 26 +#define GPIO_PB11 27 +#define GPIO_PB12 28 +#define GPIO_PB13 29 +#define GPIO_PB14 30 +#define GPIO_PB15 31 +#define GPIO_PC0 32 +#define GPIO_PC1 33 +#define GPIO_PC2 34 +#define GPIO_PC3 35 +#define GPIO_PC4 36 +#define GPIO_PC5 37 +#define GPIO_PC6 38 +#define GPIO_PC7 39 +#define GPIO_PC8 40 +#define GPIO_PC9 41 +#define GPIO_PC10 42 +#define GPIO_PC11 43 +#define GPIO_PC12 44 +#define GPIO_PC13 45 +#define GPIO_PC14 46 +#define GPIO_PC15 47 +#define GPIO_PD0 48 +#define GPIO_PD1 49 +#define GPIO_PD2 50 +#define GPIO_PD3 51 +#define GPIO_PD4 52 +#define GPIO_PD5 53 +#define GPIO_PD6 54 +#define GPIO_PD7 55 +#define GPIO_PD8 56 +#define GPIO_PD9 57 +#define GPIO_PD10 58 +#define GPIO_PD11 59 +#define GPIO_PD12 60 +#define GPIO_PD13 61 +#define GPIO_PD14 62 +#define GPIO_PD15 63 +#define GPIO_PE0 64 +#define GPIO_PE1 65 +#define GPIO_PE2 66 +#define GPIO_PE3 67 +#define GPIO_PE4 68 +#define GPIO_PE5 69 +#define GPIO_PE6 70 +#define GPIO_PE7 71 +#define GPIO_PE8 72 +#define GPIO_PE9 73 +#define GPIO_PE10 74 +#define GPIO_PE11 75 +#define GPIO_PE12 76 +#define GPIO_PE13 77 +#define GPIO_PE14 78 +#define GPIO_PE15 79 +#define GPIO_PF0 80 +#define GPIO_PF1 81 +#define GPIO_PF2 82 +#define GPIO_PF3 83 +#define GPIO_PF4 84 +#define GPIO_PF5 85 +#define GPIO_PF6 86 +#define GPIO_PF7 87 +#define GPIO_PF8 88 +#define GPIO_PF9 89 +#define GPIO_PF10 90 +#define GPIO_PF11 91 +#define GPIO_PF12 92 +#define GPIO_PF13 93 +#define GPIO_PF14 94 +#define GPIO_PF15 95 +#define GPIO_PG0 96 +#define GPIO_PG1 97 +#define GPIO_PG2 98 +#define GPIO_PG3 99 +#define GPIO_PG4 100 +#define GPIO_PG5 101 +#define GPIO_PG6 102 +#define GPIO_PG7 103 +#define GPIO_PG8 104 +#define GPIO_PG9 105 +#define GPIO_PG10 106 +#define GPIO_PG11 107 +#define GPIO_PG12 108 +#define GPIO_PG13 109 +#define GPIO_PG14 110 +#define GPIO_PG15 111 + + +#define BFIN_GPIO_PINT 1 + + +#ifndef __ASSEMBLY__ + +struct gpio_port_t { + unsigned long port_fer; + unsigned long port_fer_set; + unsigned long port_fer_clear; + unsigned long data; + unsigned long data_set; + unsigned long data_clear; + unsigned long dir; + unsigned long dir_set; + unsigned long dir_clear; + unsigned long inen; + unsigned long inen_set; + unsigned long inen_clear; + unsigned long port_mux; + unsigned long toggle; + unsigned long polar; + unsigned long polar_set; + unsigned long polar_clear; + unsigned long lock; + unsigned long spare; + unsigned long revid; +}; + +struct gpio_port_s { + unsigned short fer; + unsigned short data; + unsigned short dir; + unsigned short inen; + unsigned int mux; +}; + +#endif + +#include <mach-common/ports-a.h> +#include <mach-common/ports-b.h> +#include <mach-common/ports-c.h> +#include <mach-common/ports-d.h> +#include <mach-common/ports-e.h> +#include <mach-common/ports-f.h> +#include <mach-common/ports-g.h> + +#endif /* _MACH_GPIO_H_ */ diff --git a/arch/blackfin/mach-bf609/include/mach/irq.h b/arch/blackfin/mach-bf609/include/mach/irq.h new file mode 100644 index 000000000000..0004552433b2 --- /dev/null +++ b/arch/blackfin/mach-bf609/include/mach/irq.h @@ -0,0 +1,318 @@ +/* + * Copyright 2011 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _BF60x_IRQ_H_ +#define _BF60x_IRQ_H_ + +#include <mach-common/irq.h> + +#undef BFIN_IRQ +#define BFIN_IRQ(x) ((x) + IVG15) + +#define NR_PERI_INTS (5 * 32) + +#define IRQ_SEC_ERR BFIN_IRQ(0) /* SEC Error */ +#define IRQ_CGU_EVT BFIN_IRQ(1) /* CGU Event */ +#define IRQ_WATCH0 BFIN_IRQ(2) /* Watchdog0 Interrupt */ +#define IRQ_WATCH1 BFIN_IRQ(3) /* Watchdog1 Interrupt */ +#define IRQ_L2CTL0_ECC_ERR BFIN_IRQ(4) /* L2 ECC Error */ +#define IRQ_L2CTL0_ECC_WARN BFIN_IRQ(5) /* L2 ECC Waring */ +#define IRQ_C0_DBL_FAULT BFIN_IRQ(6) /* Core 0 Double Fault */ +#define IRQ_C1_DBL_FAULT BFIN_IRQ(7) /* Core 1 Double Fault */ +#define IRQ_C0_HW_ERR BFIN_IRQ(8) /* Core 0 Hardware Error */ +#define IRQ_C1_HW_ERR BFIN_IRQ(9) /* Core 1 Hardware Error */ +#define IRQ_C0_NMI_L1_PARITY_ERR BFIN_IRQ(10) /* Core 0 Unhandled NMI or L1 Memory Parity Error */ +#define IRQ_C1_NMI_L1_PARITY_ERR BFIN_IRQ(11) /* Core 1 Unhandled NMI or L1 Memory Parity Error */ +#define CORE_IRQS (IRQ_C1_NMI_L1_PARITY_ERR + 1) + +#define IRQ_TIMER0 BFIN_IRQ(12) /* Timer 0 Interrupt */ +#define IRQ_TIMER1 BFIN_IRQ(13) /* Timer 1 Interrupt */ +#define IRQ_TIMER2 BFIN_IRQ(14) /* Timer 2 Interrupt */ +#define IRQ_TIMER3 BFIN_IRQ(15) /* Timer 3 Interrupt */ +#define IRQ_TIMER4 BFIN_IRQ(16) /* Timer 4 Interrupt */ +#define IRQ_TIMER5 BFIN_IRQ(17) /* Timer 5 Interrupt */ +#define IRQ_TIMER6 BFIN_IRQ(18) /* Timer 6 Interrupt */ +#define IRQ_TIMER7 BFIN_IRQ(19) /* Timer 7 Interrupt */ +#define IRQ_TIMER_STAT BFIN_IRQ(20) /* Timer Block Status */ +#define IRQ_PINT0 BFIN_IRQ(21) /* PINT0 Interrupt */ +#define IRQ_PINT1 BFIN_IRQ(22) /* PINT1 Interrupt */ +#define IRQ_PINT2 BFIN_IRQ(23) /* PINT2 Interrupt */ +#define IRQ_PINT3 BFIN_IRQ(24) /* PINT3 Interrupt */ +#define IRQ_PINT4 BFIN_IRQ(25) /* PINT4 Interrupt */ +#define IRQ_PINT5 BFIN_IRQ(26) /* PINT5 Interrupt */ +#define IRQ_CNT BFIN_IRQ(27) /* CNT Interrupt */ +#define IRQ_PWM0_TRIP BFIN_IRQ(28) /* PWM0 Trip Interrupt */ +#define IRQ_PWM0_SYNC BFIN_IRQ(29) /* PWM0 Sync Interrupt */ +#define IRQ_PWM1_TRIP BFIN_IRQ(30) /* PWM1 Trip Interrupt */ +#define IRQ_PWM1_SYNC BFIN_IRQ(31) /* PWM1 Sync Interrupt */ +#define IRQ_TWI0 BFIN_IRQ(32) /* TWI0 Interrupt */ +#define IRQ_TWI1 BFIN_IRQ(33) /* TWI1 Interrupt */ +#define IRQ_SOFT0 BFIN_IRQ(34) /* Software-Driven Interrupt 0 */ +#define IRQ_SOFT1 BFIN_IRQ(35) /* Software-Driven Interrupt 1 */ +#define IRQ_SOFT2 BFIN_IRQ(36) /* Software-Driven Interrupt 2 */ +#define IRQ_SOFT3 BFIN_IRQ(37) /* Software-Driven Interrupt 3 */ +#define IRQ_ACM_EVT_MISS BFIN_IRQ(38) /* ACM Event Miss */ +#define IRQ_ACM_EVT_COMPLETE BFIN_IRQ(39) /* ACM Event Complete */ +#define IRQ_CAN0_RX BFIN_IRQ(40) /* CAN0 Receive Interrupt */ +#define IRQ_CAN0_TX BFIN_IRQ(41) /* CAN0 Transmit Interrupt */ +#define IRQ_CAN0_STAT BFIN_IRQ(42) /* CAN0 Status */ +#define IRQ_SPORT0_TX BFIN_IRQ(43) /* SPORT0 TX Interrupt (DMA0) */ +#define IRQ_SPORT0_TX_STAT BFIN_IRQ(44) /* SPORT0 TX Status Interrupt */ +#define IRQ_SPORT0_RX BFIN_IRQ(45) /* SPORT0 RX Interrupt (DMA1) */ +#define IRQ_SPORT0_RX_STAT BFIN_IRQ(46) /* SPORT0 RX Status Interrupt */ +#define IRQ_SPORT1_TX BFIN_IRQ(47) /* SPORT1 TX Interrupt (DMA2) */ +#define IRQ_SPORT1_TX_STAT BFIN_IRQ(48) /* SPORT1 TX Status Interrupt */ +#define IRQ_SPORT1_RX BFIN_IRQ(49) /* SPORT1 RX Interrupt (DMA3) */ +#define IRQ_SPORT1_RX_STAT BFIN_IRQ(50) /* SPORT1 RX Status Interrupt */ +#define IRQ_SPORT2_TX BFIN_IRQ(51) /* SPORT2 TX Interrupt (DMA4) */ +#define IRQ_SPORT2_TX_STAT BFIN_IRQ(52) /* SPORT2 TX Status Interrupt */ +#define IRQ_SPORT2_RX BFIN_IRQ(53) /* SPORT2 RX Interrupt (DMA5) */ +#define IRQ_SPORT2_RX_STAT BFIN_IRQ(54) /* SPORT2 RX Status Interrupt */ +#define IRQ_SPI0_TX BFIN_IRQ(55) /* SPI0 TX Interrupt (DMA6) */ +#define IRQ_SPI0_RX BFIN_IRQ(56) /* SPI0 RX Interrupt (DMA7) */ +#define IRQ_SPI0_STAT BFIN_IRQ(57) /* SPI0 Status Interrupt */ +#define IRQ_SPI1_TX BFIN_IRQ(58) /* SPI1 TX Interrupt (DMA8) */ +#define IRQ_SPI1_RX BFIN_IRQ(59) /* SPI1 RX Interrupt (DMA9) */ +#define IRQ_SPI1_STAT BFIN_IRQ(60) /* SPI1 Status Interrupt */ +#define IRQ_RSI BFIN_IRQ(61) /* RSI (DMA10) Interrupt */ +#define IRQ_RSI_INT0 BFIN_IRQ(62) /* RSI Interrupt0 */ +#define IRQ_RSI_INT1 BFIN_IRQ(63) /* RSI Interrupt1 */ +#define IRQ_SDU BFIN_IRQ(64) /* DMA11 Data (SDU) */ +/* -- RESERVED -- 65 DMA12 Data (Reserved) */ +/* -- RESERVED -- 66 Reserved */ +/* -- RESERVED -- 67 Reserved */ +#define IRQ_EMAC0_STAT BFIN_IRQ(68) /* EMAC0 Status */ +/* -- RESERVED -- 69 EMAC0 Power (Reserved) */ +#define IRQ_EMAC1_STAT BFIN_IRQ(70) /* EMAC1 Status */ +/* -- RESERVED -- 71 EMAC1 Power (Reserved) */ +#define IRQ_LP0 BFIN_IRQ(72) /* DMA13 Data (Link Port 0) */ +#define IRQ_LP0_STAT BFIN_IRQ(73) /* Link Port 0 Status */ +#define IRQ_LP1 BFIN_IRQ(74) /* DMA14 Data (Link Port 1) */ +#define IRQ_LP1_STAT BFIN_IRQ(75) /* Link Port 1 Status */ +#define IRQ_LP2 BFIN_IRQ(76) /* DMA15 Data (Link Port 2) */ +#define IRQ_LP2_STAT BFIN_IRQ(77) /* Link Port 2 Status */ +#define IRQ_LP3 BFIN_IRQ(78) /* DMA16 Data(Link Port 3) */ +#define IRQ_LP3_STAT BFIN_IRQ(79) /* Link Port 3 Status */ +#define IRQ_UART0_TX BFIN_IRQ(80) /* UART0 TX Interrupt (DMA17) */ +#define IRQ_UART0_RX BFIN_IRQ(81) /* UART0 RX Interrupt (DMA18) */ +#define IRQ_UART0_STAT BFIN_IRQ(82) /* UART0 Status(Error) Interrupt */ +#define IRQ_UART1_TX BFIN_IRQ(83) /* UART1 TX Interrupt (DMA19) */ +#define IRQ_UART1_RX BFIN_IRQ(84) /* UART1 RX Interrupt (DMA20) */ +#define IRQ_UART1_STAT BFIN_IRQ(85) /* UART1 Status(Error) Interrupt */ +#define IRQ_MDMA0_SRC_CRC0 BFIN_IRQ(86) /* DMA21 Data (MDMA Stream 0 Source/CRC0 Input Channel) */ +#define IRQ_MDMA0_DEST_CRC0 BFIN_IRQ(87) /* DMA22 Data (MDMA Stream 0 Destination/CRC0 Output Channel) */ +#define IRQ_MDMAS0 IRQ_MDMA0_DEST_CRC0 +#define IRQ_CRC0_DCNTEXP BFIN_IRQ(88) /* CRC0 DATACOUNT Expiration */ +#define IRQ_CRC0_ERR BFIN_IRQ(89) /* CRC0 Error */ +#define IRQ_MDMA1_SRC_CRC1 BFIN_IRQ(90) /* DMA23 Data (MDMA Stream 1 Source/CRC1 Input Channel) */ +#define IRQ_MDMA1_DEST_CRC1 BFIN_IRQ(91) /* DMA24 Data (MDMA Stream 1 Destination/CRC1 Output Channel) */ +#define IRQ_MDMAS1 IRQ_MDMA1_DEST_CRC1 +#define IRQ_CRC1_DCNTEXP BFIN_IRQ(92) /* CRC1 DATACOUNT Expiration */ +#define IRQ_CRC1_ERR BFIN_IRQ(93) /* CRC1 Error */ +#define IRQ_MDMA2_SRC BFIN_IRQ(94) /* DMA25 Data (MDMA Stream 2 Source Channel) */ +#define IRQ_MDMA2_DEST BFIN_IRQ(95) /* DMA26 Data (MDMA Stream 2 Destination Channel) */ +#define IRQ_MDMAS2 IRQ_MDMA2_DEST +#define IRQ_MDMA3_SRC BFIN_IRQ(96) /* DMA27 Data (MDMA Stream 3 Source Channel) */ +#define IRQ_MDMA3_DEST BFIN_IRQ(97) /* DMA28 Data (MDMA Stream 3 Destination Channel) */ +#define IRQ_MDMAS3 IRQ_MDMA3_DEST +#define IRQ_EPPI0_CH0 BFIN_IRQ(98) /* DMA29 Data (EPPI0 Channel 0) */ +#define IRQ_EPPI0_CH1 BFIN_IRQ(99) /* DMA30 Data (EPPI0 Channel 1) */ +#define IRQ_EPPI0_STAT BFIN_IRQ(100) /* EPPI0 Status */ +#define IRQ_EPPI2_CH0 BFIN_IRQ(101) /* DMA31 Data (EPPI2 Channel 0) */ +#define IRQ_EPPI2_CH1 BFIN_IRQ(102) /* DMA32 Data (EPPI2 Channel 1) */ +#define IRQ_EPPI2_STAT BFIN_IRQ(103) /* EPPI2 Status */ +#define IRQ_EPPI1_CH0 BFIN_IRQ(104) /* DMA33 Data (EPPI1 Channel 0) */ +#define IRQ_EPPI1_CH1 BFIN_IRQ(105) /* DMA34 Data (EPPI1 Channel 1) */ +#define IRQ_EPPI1_STAT BFIN_IRQ(106) /* EPPI1 Status */ +#define IRQ_PIXC_CH0 BFIN_IRQ(107) /* DMA35 Data (PIXC Channel 0) */ +#define IRQ_PIXC_CH1 BFIN_IRQ(108) /* DMA36 Data (PIXC Channel 1) */ +#define IRQ_PIXC_CH2 BFIN_IRQ(109) /* DMA37 Data (PIXC Channel 2) */ +#define IRQ_PIXC_STAT BFIN_IRQ(110) /* PIXC Status */ +#define IRQ_PVP_CPDOB BFIN_IRQ(111) /* DMA38 Data (PVP0 Camera Pipe Data Out B) */ +#define IRQ_PVP_CPDOC BFIN_IRQ(112) /* DMA39 Data (PVP0 Camera Pipe Data Out C) */ +#define IRQ_PVP_CPSTAT BFIN_IRQ(113) /* DMA40 Data (PVP0 Camera Pipe Status Out) */ +#define IRQ_PVP_CPCI BFIN_IRQ(114) /* DMA41 Data (PVP0 Camera Pipe Control In) */ +#define IRQ_PVP_STAT0 BFIN_IRQ(115) /* PVP0 Status 0 */ +#define IRQ_PVP_MPDO BFIN_IRQ(116) /* DMA42 Data (PVP0 Memory Pipe Data Out) */ +#define IRQ_PVP_MPDI BFIN_IRQ(117) /* DMA43 Data (PVP0 Memory Pipe Data In) */ +#define IRQ_PVP_MPSTAT BFIN_IRQ(118) /* DMA44 Data (PVP0 Memory Pipe Status Out) */ +#define IRQ_PVP_MPCI BFIN_IRQ(119) /* DMA45 Data (PVP0 Memory Pipe Control In) */ +#define IRQ_PVP_CPDOA BFIN_IRQ(120) /* DMA46 Data (PVP0 Camera Pipe Data Out A) */ +#define IRQ_PVP_STAT1 BFIN_IRQ(121) /* PVP0 Status 1 */ +#define IRQ_USB_STAT BFIN_IRQ(122) /* USB Status Interrupt */ +#define IRQ_USB_DMA BFIN_IRQ(123) /* USB DMA Interrupt */ +#define IRQ_TRU_INT0 BFIN_IRQ(124) /* TRU0 Interrupt 0 */ +#define IRQ_TRU_INT1 BFIN_IRQ(125) /* TRU0 Interrupt 1 */ +#define IRQ_TRU_INT2 BFIN_IRQ(126) /* TRU0 Interrupt 2 */ +#define IRQ_TRU_INT3 BFIN_IRQ(127) /* TRU0 Interrupt 3 */ +#define IRQ_DMAC0_ERROR BFIN_IRQ(128) /* DMAC0 Status Interrupt */ +#define IRQ_CGU0_ERROR BFIN_IRQ(129) /* CGU0 Error */ +/* -- RESERVED -- 130 Reserved */ +#define IRQ_DPM BFIN_IRQ(131) /* DPM0 Event */ +/* -- RESERVED -- 132 Reserved */ +#define IRQ_SWU0 BFIN_IRQ(133) /* SWU0 */ +#define IRQ_SWU1 BFIN_IRQ(134) /* SWU1 */ +#define IRQ_SWU2 BFIN_IRQ(135) /* SWU2 */ +#define IRQ_SWU3 BFIN_IRQ(136) /* SWU3 */ +#define IRQ_SWU4 BFIN_IRQ(137) /* SWU4 */ +#define IRQ_SWU5 BFIN_IRQ(138) /* SWU5 */ +#define IRQ_SWU6 BFIN_IRQ(139) /* SWU6 */ + +#define SYS_IRQS IRQ_SWU6 + +#define BFIN_PA_IRQ(x) ((x) + SYS_IRQS + 1) +#define IRQ_PA0 BFIN_PA_IRQ(0) +#define IRQ_PA1 BFIN_PA_IRQ(1) +#define IRQ_PA2 BFIN_PA_IRQ(2) +#define IRQ_PA3 BFIN_PA_IRQ(3) +#define IRQ_PA4 BFIN_PA_IRQ(4) +#define IRQ_PA5 BFIN_PA_IRQ(5) +#define IRQ_PA6 BFIN_PA_IRQ(6) +#define IRQ_PA7 BFIN_PA_IRQ(7) +#define IRQ_PA8 BFIN_PA_IRQ(8) +#define IRQ_PA9 BFIN_PA_IRQ(9) +#define IRQ_PA10 BFIN_PA_IRQ(10) +#define IRQ_PA11 BFIN_PA_IRQ(11) +#define IRQ_PA12 BFIN_PA_IRQ(12) +#define IRQ_PA13 BFIN_PA_IRQ(13) +#define IRQ_PA14 BFIN_PA_IRQ(14) +#define IRQ_PA15 BFIN_PA_IRQ(15) + +#define BFIN_PB_IRQ(x) ((x) + IRQ_PA15 + 1) +#define IRQ_PB0 BFIN_PB_IRQ(0) +#define IRQ_PB1 BFIN_PB_IRQ(1) +#define IRQ_PB2 BFIN_PB_IRQ(2) +#define IRQ_PB3 BFIN_PB_IRQ(3) +#define IRQ_PB4 BFIN_PB_IRQ(4) +#define IRQ_PB5 BFIN_PB_IRQ(5) +#define IRQ_PB6 BFIN_PB_IRQ(6) +#define IRQ_PB7 BFIN_PB_IRQ(7) +#define IRQ_PB8 BFIN_PB_IRQ(8) +#define IRQ_PB9 BFIN_PB_IRQ(9) +#define IRQ_PB10 BFIN_PB_IRQ(10) +#define IRQ_PB11 BFIN_PB_IRQ(11) +#define IRQ_PB12 BFIN_PB_IRQ(12) +#define IRQ_PB13 BFIN_PB_IRQ(13) +#define IRQ_PB14 BFIN_PB_IRQ(14) +#define IRQ_PB15 BFIN_PB_IRQ(15) /* N/A */ + +#define BFIN_PC_IRQ(x) ((x) + IRQ_PB15 + 1) +#define IRQ_PC0 BFIN_PC_IRQ(0) +#define IRQ_PC1 BFIN_PC_IRQ(1) +#define IRQ_PC2 BFIN_PC_IRQ(2) +#define IRQ_PC3 BFIN_PC_IRQ(3) +#define IRQ_PC4 BFIN_PC_IRQ(4) +#define IRQ_PC5 BFIN_PC_IRQ(5) +#define IRQ_PC6 BFIN_PC_IRQ(6) +#define IRQ_PC7 BFIN_PC_IRQ(7) +#define IRQ_PC8 BFIN_PC_IRQ(8) +#define IRQ_PC9 BFIN_PC_IRQ(9) +#define IRQ_PC10 BFIN_PC_IRQ(10) +#define IRQ_PC11 BFIN_PC_IRQ(11) +#define IRQ_PC12 BFIN_PC_IRQ(12) +#define IRQ_PC13 BFIN_PC_IRQ(13) +#define IRQ_PC14 BFIN_PC_IRQ(14) /* N/A */ +#define IRQ_PC15 BFIN_PC_IRQ(15) /* N/A */ + +#define BFIN_PD_IRQ(x) ((x) + IRQ_PC15 + 1) +#define IRQ_PD0 BFIN_PD_IRQ(0) +#define IRQ_PD1 BFIN_PD_IRQ(1) +#define IRQ_PD2 BFIN_PD_IRQ(2) +#define IRQ_PD3 BFIN_PD_IRQ(3) +#define IRQ_PD4 BFIN_PD_IRQ(4) +#define IRQ_PD5 BFIN_PD_IRQ(5) +#define IRQ_PD6 BFIN_PD_IRQ(6) +#define IRQ_PD7 BFIN_PD_IRQ(7) +#define IRQ_PD8 BFIN_PD_IRQ(8) +#define IRQ_PD9 BFIN_PD_IRQ(9) +#define IRQ_PD10 BFIN_PD_IRQ(10) +#define IRQ_PD11 BFIN_PD_IRQ(11) +#define IRQ_PD12 BFIN_PD_IRQ(12) +#define IRQ_PD13 BFIN_PD_IRQ(13) +#define IRQ_PD14 BFIN_PD_IRQ(14) +#define IRQ_PD15 BFIN_PD_IRQ(15) + +#define BFIN_PE_IRQ(x) ((x) + IRQ_PD15 + 1) +#define IRQ_PE0 BFIN_PE_IRQ(0) +#define IRQ_PE1 BFIN_PE_IRQ(1) +#define IRQ_PE2 BFIN_PE_IRQ(2) +#define IRQ_PE3 BFIN_PE_IRQ(3) +#define IRQ_PE4 BFIN_PE_IRQ(4) +#define IRQ_PE5 BFIN_PE_IRQ(5) +#define IRQ_PE6 BFIN_PE_IRQ(6) +#define IRQ_PE7 BFIN_PE_IRQ(7) +#define IRQ_PE8 BFIN_PE_IRQ(8) +#define IRQ_PE9 BFIN_PE_IRQ(9) +#define IRQ_PE10 BFIN_PE_IRQ(10) +#define IRQ_PE11 BFIN_PE_IRQ(11) +#define IRQ_PE12 BFIN_PE_IRQ(12) +#define IRQ_PE13 BFIN_PE_IRQ(13) +#define IRQ_PE14 BFIN_PE_IRQ(14) +#define IRQ_PE15 BFIN_PE_IRQ(15) + +#define BFIN_PF_IRQ(x) ((x) + IRQ_PE15 + 1) +#define IRQ_PF0 BFIN_PF_IRQ(0) +#define IRQ_PF1 BFIN_PF_IRQ(1) +#define IRQ_PF2 BFIN_PF_IRQ(2) +#define IRQ_PF3 BFIN_PF_IRQ(3) +#define IRQ_PF4 BFIN_PF_IRQ(4) +#define IRQ_PF5 BFIN_PF_IRQ(5) +#define IRQ_PF6 BFIN_PF_IRQ(6) +#define IRQ_PF7 BFIN_PF_IRQ(7) +#define IRQ_PF8 BFIN_PF_IRQ(8) +#define IRQ_PF9 BFIN_PF_IRQ(9) +#define IRQ_PF10 BFIN_PF_IRQ(10) +#define IRQ_PF11 BFIN_PF_IRQ(11) +#define IRQ_PF12 BFIN_PF_IRQ(12) +#define IRQ_PF13 BFIN_PF_IRQ(13) +#define IRQ_PF14 BFIN_PF_IRQ(14) +#define IRQ_PF15 BFIN_PF_IRQ(15) + +#define BFIN_PG_IRQ(x) ((x) + IRQ_PF15 + 1) +#define IRQ_PG0 BFIN_PG_IRQ(0) +#define IRQ_PG1 BFIN_PG_IRQ(1) +#define IRQ_PG2 BFIN_PG_IRQ(2) +#define IRQ_PG3 BFIN_PG_IRQ(3) +#define IRQ_PG4 BFIN_PG_IRQ(4) +#define IRQ_PG5 BFIN_PG_IRQ(5) +#define IRQ_PG6 BFIN_PG_IRQ(6) +#define IRQ_PG7 BFIN_PG_IRQ(7) +#define IRQ_PG8 BFIN_PG_IRQ(8) +#define IRQ_PG9 BFIN_PG_IRQ(9) +#define IRQ_PG10 BFIN_PG_IRQ(10) +#define IRQ_PG11 BFIN_PG_IRQ(11) +#define IRQ_PG12 BFIN_PG_IRQ(12) +#define IRQ_PG13 BFIN_PG_IRQ(13) +#define IRQ_PG14 BFIN_PG_IRQ(14) +#define IRQ_PG15 BFIN_PG_IRQ(15) + +#define GPIO_IRQ_BASE IRQ_PA0 + +#define NR_MACH_IRQS (IRQ_PG15 + 1) + +#ifndef __ASSEMBLY__ +#include <linux/types.h> + +/* + * bfin pint registers layout + */ +struct bfin_pint_regs { + u32 mask_set; + u32 mask_clear; + u32 request; + u32 assign; + u32 edge_set; + u32 edge_clear; + u32 invert_set; + u32 invert_clear; + u32 pinstate; + u32 latch; + u32 __pad0[2]; +}; + +#endif + +#endif diff --git a/arch/blackfin/mach-bf609/include/mach/mem_map.h b/arch/blackfin/mach-bf609/include/mach/mem_map.h new file mode 100644 index 000000000000..20b65bfc5311 --- /dev/null +++ b/arch/blackfin/mach-bf609/include/mach/mem_map.h @@ -0,0 +1,86 @@ +/* + * BF60x memory map + * + * Copyright 2011 Analog Devices Inc. + * Licensed under the GPL-2 or later. + */ + +#ifndef __BFIN_MACH_MEM_MAP_H__ +#define __BFIN_MACH_MEM_MAP_H__ + +#ifndef __BFIN_MEM_MAP_H__ +# error "do not include mach/mem_map.h directly -- use asm/mem_map.h" +#endif + +/* Async Memory Banks */ +#define ASYNC_BANK3_BASE 0xBC000000 /* Async Bank 3 */ +#define ASYNC_BANK3_SIZE 0x04000000 /* 64M */ +#define ASYNC_BANK2_BASE 0xB8000000 /* Async Bank 2 */ +#define ASYNC_BANK2_SIZE 0x04000000 /* 64M */ +#define ASYNC_BANK1_BASE 0xB4000000 /* Async Bank 1 */ +#define ASYNC_BANK1_SIZE 0x04000000 /* 64M */ +#define ASYNC_BANK0_BASE 0xB0000000 /* Async Bank 0 */ +#define ASYNC_BANK0_SIZE 0x04000000 /* 64M */ + +/* Boot ROM Memory */ + +#define BOOT_ROM_START 0xC8000000 +#define BOOT_ROM_LENGTH 0x8000 + +/* Level 1 Memory */ + +/* Memory Map for ADSP-BF60x processors */ +#ifdef CONFIG_BFIN_ICACHE +#define BFIN_ICACHESIZE (16*1024) +#define L1_CODE_LENGTH 0x10000 +#else +#define BFIN_ICACHESIZE (0*1024) +#define L1_CODE_LENGTH 0x14000 +#endif + +#define L1_CODE_START 0xFFA00000 +#define L1_DATA_A_START 0xFF800000 +#define L1_DATA_B_START 0xFF900000 + + +#define COREA_L1_SCRATCH_START 0xFFB00000 +#define COREB_L1_SCRATCH_START 0xFF700000 + +#define COREB_L1_CODE_START 0xFF600000 +#define COREB_L1_DATA_A_START 0xFF400000 +#define COREB_L1_DATA_B_START 0xFF500000 + +#define COREB_L1_CODE_LENGTH 0x14000 +#define COREB_L1_DATA_A_LENGTH 0x8000 +#define COREB_L1_DATA_B_LENGTH 0x8000 + + +#ifdef CONFIG_BFIN_DCACHE + +#ifdef CONFIG_BFIN_DCACHE_BANKA +#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) +#define L1_DATA_A_LENGTH (0x8000 - 0x4000) +#define L1_DATA_B_LENGTH 0x8000 +#define BFIN_DCACHESIZE (16*1024) +#define BFIN_DSUPBANKS 1 +#else +#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) +#define L1_DATA_A_LENGTH (0x8000 - 0x4000) +#define L1_DATA_B_LENGTH (0x8000 - 0x4000) +#define BFIN_DCACHESIZE (32*1024) +#define BFIN_DSUPBANKS 2 +#endif + +#else +#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) +#define L1_DATA_A_LENGTH 0x8000 +#define L1_DATA_B_LENGTH 0x8000 +#define BFIN_DCACHESIZE (0*1024) +#define BFIN_DSUPBANKS 0 +#endif /*CONFIG_BFIN_DCACHE*/ + +/* Level 2 Memory */ +#define L2_START 0xC8080000 +#define L2_LENGTH 0x40000 + +#endif diff --git a/arch/blackfin/mach-bf609/include/mach/pll.h b/arch/blackfin/mach-bf609/include/mach/pll.h new file mode 100644 index 000000000000..1857a4a0f262 --- /dev/null +++ b/arch/blackfin/mach-bf609/include/mach/pll.h @@ -0,0 +1 @@ +/* #include <mach-common/pll.h> */ diff --git a/arch/blackfin/mach-bf609/include/mach/pm.h b/arch/blackfin/mach-bf609/include/mach/pm.h new file mode 100644 index 000000000000..036d9bdc889e --- /dev/null +++ b/arch/blackfin/mach-bf609/include/mach/pm.h @@ -0,0 +1,21 @@ +/* + * Blackfin bf609 power management + * + * Copyright 2011 Analog Devices Inc. + * + * Licensed under the GPL-2 + */ + +#ifndef __MACH_BF609_PM_H__ +#define __MACH_BF609_PM_H__ + +#include <linux/suspend.h> + +int bfin609_pm_enter(suspend_state_t state); +int bf609_pm_prepare(void); +void bf609_pm_finish(void); + +void bf609_hibernate(void); +void bfin_sec_raise_irq(unsigned int sid); +void coreb_enable(void); +#endif diff --git a/arch/blackfin/mach-bf609/include/mach/portmux.h b/arch/blackfin/mach-bf609/include/mach/portmux.h new file mode 100644 index 000000000000..2e1a51c25098 --- /dev/null +++ b/arch/blackfin/mach-bf609/include/mach/portmux.h @@ -0,0 +1,347 @@ +/* + * Copyright 2011 Analog Devices Inc. + * + * Licensed under the GPL-2 or later + */ + +#ifndef _MACH_PORTMUX_H_ +#define _MACH_PORTMUX_H_ + +#define MAX_RESOURCES MAX_BLACKFIN_GPIOS + +/* EMAC RMII Port Mux */ +#define P_MII0_MDC (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(0)) +#define P_MII0_MDIO (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(0)) +#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(0)) +#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(0)) +#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(0)) +#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(0)) +#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(0)) +#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(0)) +#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(0)) +#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(0)) +#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(0)) + +#define P_RMII0 {\ + P_MII0_ETxD0, \ + P_MII0_ETxD1, \ + P_MII0_ETxEN, \ + P_MII0_ERxD0, \ + P_MII0_ERxD1, \ + P_MII0_ERxER, \ + P_MII0_TxCLK, \ + P_MII0_PHYINT, \ + P_MII0_CRS, \ + P_MII0_MDC, \ + P_MII0_MDIO, 0} + +#define P_MII1_MDC (P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(0)) +#define P_MII1_MDIO (P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(0)) +#define P_MII1_ETxD0 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0)) +#define P_MII1_ERxD0 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0)) +#define P_MII1_ETxD1 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0)) +#define P_MII1_ERxD1 (P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(0)) +#define P_MII1_ETxEN (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0)) +#define P_MII1_PHYINT (P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(0)) +#define P_MII1_CRS (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(0)) +#define P_MII1_ERxER (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(0)) +#define P_MII1_TxCLK (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0)) + +#define P_RMII1 {\ + P_MII1_ETxD0, \ + P_MII1_ETxD1, \ + P_MII1_ETxEN, \ + P_MII1_ERxD0, \ + P_MII1_ERxD1, \ + P_MII1_ERxER, \ + P_MII1_TxCLK, \ + P_MII1_PHYINT, \ + P_MII1_CRS, \ + P_MII1_MDC, \ + P_MII1_MDIO, 0} + +/* PPI Port Mux */ +#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1)) +#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1)) +#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1)) +#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1)) +#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1)) +#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1)) +#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1)) +#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1)) +#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1)) +#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1)) +#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1)) +#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1)) +#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1)) +#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1)) +#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1)) +#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1)) +#define P_PPI0_D16 (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(1)) +#define P_PPI0_D17 (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(1)) +#define P_PPI0_D18 (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(1)) +#define P_PPI0_D19 (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(1)) +#define P_PPI0_D20 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(1)) +#define P_PPI0_D21 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(1)) +#define P_PPI0_D22 (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(1)) +#define P_PPI0_D23 (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(1)) +#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PE9) | P_FUNCT(1)) +#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PE8) | P_FUNCT(1)) +#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(1)) +#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(1)) + +#define P_PPI1_D0 (P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(1)) +#define P_PPI1_D1 (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(1)) +#define P_PPI1_D2 (P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(1)) +#define P_PPI1_D3 (P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(1)) +#define P_PPI1_D4 (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(1)) +#define P_PPI1_D5 (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(1)) +#define P_PPI1_D6 (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(1)) +#define P_PPI1_D7 (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(1)) +#define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PC8) | P_FUNCT(1)) +#define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(1)) +#define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PC10) | P_FUNCT(1)) +#define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(1)) +#define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(1)) +#define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(1)) +#define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PC14) | P_FUNCT(1)) +#define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PC15) | P_FUNCT(1)) +#define P_PPI1_D16 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(1)) +#define P_PPI1_D17 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(1)) +#define P_PPI1_CLK (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(1)) +#define P_PPI1_FS1 (P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(1)) +#define P_PPI1_FS2 (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(1)) +#define P_PPI1_FS3 (P_DEFINED | P_IDENT(GPIO_PB15) | P_FUNCT(1)) + +#define P_PPI2_D0 (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(1)) +#define P_PPI2_D1 (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(1)) +#define P_PPI2_D2 (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(1)) +#define P_PPI2_D3 (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(1)) +#define P_PPI2_D4 (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(1)) +#define P_PPI2_D5 (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(1)) +#define P_PPI2_D6 (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(1)) +#define P_PPI2_D7 (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(1)) +#define P_PPI2_D8 (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(1)) +#define P_PPI2_D9 (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(1)) +#define P_PPI2_D10 (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(1)) +#define P_PPI2_D11 (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(1)) +#define P_PPI2_D12 (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(1)) +#define P_PPI2_D13 (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(1)) +#define P_PPI2_D14 (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(1)) +#define P_PPI2_D15 (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(1)) +#define P_PPI2_D16 (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(1)) +#define P_PPI2_D17 (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(1)) +#define P_PPI2_CLK (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(1)) +#define P_PPI2_FS1 (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(1)) +#define P_PPI2_FS2 (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(1)) +#define P_PPI2_FS3 (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(1)) + +/* SPI Port Mux */ +#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(3)) +#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(0)) +#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(0)) +#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(0)) +#define P_SPI0_RDY (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(0)) +#define P_SPI0_D2 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(0)) +#define P_SPI0_D3 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(0)) + +#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(0)) +#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(2)) +#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(2)) +#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PC15) | P_FUNCT(0)) +#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(0)) +#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(0)) +#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(0)) + +#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(3)) +#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(0)) +#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(0)) +#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(0)) +#define P_SPI1_RDY (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(0)) +#define P_SPI1_D2 (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(0)) +#define P_SPI1_D3 (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(0)) + +#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(0)) +#define P_SPI1_SSEL2 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(2)) +#define P_SPI1_SSEL3 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(2)) +#define P_SPI1_SSEL4 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(2)) +#define P_SPI1_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0)) +#define P_SPI1_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0)) +#define P_SPI1_SSEL7 (P_DEFINED | P_IDENT(GPIO_PC14) | P_FUNCT(0)) + +#define GPIO_DEFAULT_BOOT_SPI_CS +#define P_DEFAULT_BOOT_SPI_CS + +/* CORE IDLE */ +#define P_IDLEA (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1)) +#define P_IDLEB (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1)) +#define P_SLEEP (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2)) + +/* UART Port Mux */ +#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(1)) +#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(1)) +#define P_UART0_RTS (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(1)) +#define P_UART0_CTS (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(1)) + +#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0)) +#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0)) +#define P_UART1_RTS (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0)) +#define P_UART1_CTS (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0)) + +/* Timer */ +#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(3)) +#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(2)) +#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1)) +#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(1)) +#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1)) +#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1)) +#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1)) +#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1)) +#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1)) + +/* RSI */ +#define P_RSI_DATA0 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2)) +#define P_RSI_DATA1 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2)) +#define P_RSI_DATA2 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(2)) +#define P_RSI_DATA3 (P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(2)) +#define P_RSI_DATA4 (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(2)) +#define P_RSI_DATA5 (P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(2)) +#define P_RSI_DATA6 (P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(2)) +#define P_RSI_DATA7 (P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(2)) +#define P_RSI_CMD (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1)) +#define P_RSI_CLK (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1)) + +/* PTP */ +#define P_PTP0_PPS (P_DEFINED | P_IDENT(GPIO_PB15) | P_FUNCT(0)) +#define P_PTP0_CLKIN (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(2)) +#define P_PTP0_AUXIN (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(2)) + +#define P_PTP1_PPS (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(0)) +#define P_PTP1_CLKIN (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(2)) +#define P_PTP1_AUXIN (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(2)) + +/* SMC Port Mux */ +#define P_A3 (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0)) +#define P_A4 (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0)) +#define P_A5 (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0)) +#define P_A6 (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(0)) +#define P_A7 (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(0)) +#define P_A8 (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(0)) +#define P_A9 (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(0)) +#define P_A10 (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(0)) +#define P_A11 (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(0)) +#define P_A12 (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(0)) +#define P_A13 (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(0)) +#define P_A14 (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(0)) +#define P_A15 (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(0)) +#define P_A16 (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(0)) +#define P_A17 (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(0)) +#define P_A18 (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(0)) +#define P_A19 (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(0)) +#define P_A20 (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(0)) +#define P_A21 (P_DEFINED | P_IDENT(GPIO_PB6) | P_FUNCT(0)) +#define P_A22 (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(0)) +#define P_A23 (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(0)) +#define P_A24 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(0)) +#define P_A25 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(0)) +#define P_NORCK (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(0)) + +#define P_AMS1 (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(0)) +#define P_AMS2 (P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(0)) +#define P_AMS3 (P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(0)) + +/* CAN */ +#define P_CAN0_TX (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2)) +#define P_CAN0_RX (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2)) + +/* SPORT */ +#define P_SPORT0_ACLK (P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(2)) +#define P_SPORT0_AFS (P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(2)) +#define P_SPORT0_AD0 (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(2)) +#define P_SPORT0_AD1 (P_DEFINED | P_IDENT(GPIO_PB12) | P_FUNCT(2)) +#define P_SPORT0_ATDV (P_DEFINED | P_IDENT(GPIO_PB6) | P_FUNCT(1)) +#define P_SPORT0_BCLK (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(2)) +#define P_SPORT0_BFS (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(2)) +#define P_SPORT0_BD0 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(2)) +#define P_SPORT0_BD1 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(2)) +#define P_SPORT0_BTDV (P_DEFINED | P_IDENT(GPIO_PB12) | P_FUNCT(1)) + +#define P_SPORT1_ACLK (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(2)) +#define P_SPORT1_AFS (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(2)) +#define P_SPORT1_AD0 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(2)) +#define P_SPORT1_AD1 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(2)) +#define P_SPORT1_ATDV (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(0)) +#define P_SPORT1_BCLK (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(2)) +#define P_SPORT1_BFS (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(2)) +#define P_SPORT1_BD0 (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(2)) +#define P_SPORT1_BD1 (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(2)) +#define P_SPORT1_BTDV (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(0)) + +#define P_SPORT2_ACLK (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0)) +#define P_SPORT2_AFS (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0)) +#define P_SPORT2_AD0 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0)) +#define P_SPORT2_AD1 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0)) +#define P_SPORT2_ATDV (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(1)) +#define P_SPORT2_BCLK (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1)) +#define P_SPORT2_BFS (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0)) +#define P_SPORT2_BD0 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0)) +#define P_SPORT2_BD1 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0)) +#define P_SPORT2_BTDV (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2)) + +/* LINK PORT */ +#define P_LP0_CLK (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(2)) +#define P_LP0_ACK (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(2)) +#define P_LP0_D0 (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(2)) +#define P_LP0_D1 (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(2)) +#define P_LP0_D2 (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(2)) +#define P_LP0_D3 (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(2)) +#define P_LP0_D4 (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(2)) +#define P_LP0_D5 (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(2)) +#define P_LP0_D6 (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(2)) +#define P_LP0_D7 (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(2)) + +#define P_LP1_CLK (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(2)) +#define P_LP1_ACK (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(2)) +#define P_LP1_D0 (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(2)) +#define P_LP1_D1 (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(2)) +#define P_LP1_D2 (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(2)) +#define P_LP1_D3 (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(2)) +#define P_LP1_D4 (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(2)) +#define P_LP1_D5 (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(2)) +#define P_LP1_D6 (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(2)) +#define P_LP1_D7 (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(2)) + +#define P_LP2_CLK (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(2)) +#define P_LP2_ACK (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(2)) +#define P_LP2_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2)) +#define P_LP2_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2)) +#define P_LP2_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2)) +#define P_LP2_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2)) +#define P_LP2_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2)) +#define P_LP2_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2)) +#define P_LP2_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2)) +#define P_LP2_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2)) + +#define P_LP3_CLK (P_DEFINED | P_IDENT(GPIO_PE9) | P_FUNCT(2)) +#define P_LP3_ACK (P_DEFINED | P_IDENT(GPIO_PE8) | P_FUNCT(2)) +#define P_LP3_D0 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(2)) +#define P_LP3_D1 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2)) +#define P_LP3_D2 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2)) +#define P_LP3_D3 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(2)) +#define P_LP3_D4 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2)) +#define P_LP3_D5 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2)) +#define P_LP3_D6 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2)) +#define P_LP3_D7 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2)) + +/* TWI */ +#define P_TWI0_SCL (P_DONTCARE) +#define P_TWI0_SDA (P_DONTCARE) +#define P_TWI1_SCL (P_DONTCARE) +#define P_TWI1_SDA (P_DONTCARE) + +/* Rotary Encoder */ +#define P_CNT_CZM (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(3)) +#define P_CNT_CUD (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(3)) +#define P_CNT_CDG (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(3)) + +#endif /* _MACH_PORTMUX_H_ */ diff --git a/arch/blackfin/mach-bf609/pm.c b/arch/blackfin/mach-bf609/pm.c new file mode 100644 index 000000000000..b76966eb16ad --- /dev/null +++ b/arch/blackfin/mach-bf609/pm.c @@ -0,0 +1,362 @@ +/* + * Blackfin bf609 power management + * + * Copyright 2011 Analog Devices Inc. + * + * Licensed under the GPL-2 + */ + +#include <linux/suspend.h> +#include <linux/io.h> +#include <linux/interrupt.h> +#include <linux/gpio.h> +#include <linux/irq.h> + +#include <linux/delay.h> + +#include <asm/dpmc.h> +#include <asm/pm.h> +#include <mach/pm.h> +#include <asm/blackfin.h> + +/***********************************************************/ +/* */ +/* Wakeup Actions for DPM_RESTORE */ +/* */ +/***********************************************************/ +#define BITP_ROM_WUA_CHKHDR 24 +#define BITP_ROM_WUA_DDRLOCK 7 +#define BITP_ROM_WUA_DDRDLLEN 6 +#define BITP_ROM_WUA_DDR 5 +#define BITP_ROM_WUA_CGU 4 +#define BITP_ROM_WUA_MEMBOOT 2 +#define BITP_ROM_WUA_EN 1 + +#define BITM_ROM_WUA_CHKHDR (0xFF000000) +#define ENUM_ROM_WUA_CHKHDR_AD 0xAD000000 + +#define BITM_ROM_WUA_DDRLOCK (0x00000080) +#define BITM_ROM_WUA_DDRDLLEN (0x00000040) +#define BITM_ROM_WUA_DDR (0x00000020) +#define BITM_ROM_WUA_CGU (0x00000010) +#define BITM_ROM_WUA_MEMBOOT (0x00000002) +#define BITM_ROM_WUA_EN (0x00000001) + +/***********************************************************/ +/* */ +/* Syscontrol */ +/* */ +/***********************************************************/ +#define BITP_ROM_SYSCTRL_CGU_LOCKINGEN 28 /* unlocks CGU_CTL register */ +#define BITP_ROM_SYSCTRL_WUA_OVERRIDE 24 +#define BITP_ROM_SYSCTRL_WUA_DDRDLLEN 20 /* Saves the DDR DLL and PADS registers to the DPM registers */ +#define BITP_ROM_SYSCTRL_WUA_DDR 19 /* Saves the DDR registers to the DPM registers */ +#define BITP_ROM_SYSCTRL_WUA_CGU 18 /* Saves the CGU registers into DPM registers */ +#define BITP_ROM_SYSCTRL_WUA_DPMWRITE 17 /* Saves the Syscontrol structure structure contents into DPM registers */ +#define BITP_ROM_SYSCTRL_WUA_EN 16 /* reads current PLL and DDR configuration into structure */ +#define BITP_ROM_SYSCTRL_DDR_WRITE 13 /* writes the DDR registers from Syscontrol structure for wakeup initialization of DDR */ +#define BITP_ROM_SYSCTRL_DDR_READ 12 /* Read the DDR registers into the Syscontrol structure for storing prior to hibernate */ +#define BITP_ROM_SYSCTRL_CGU_AUTODIS 11 /* Disables auto handling of UPDT and ALGN fields */ +#define BITP_ROM_SYSCTRL_CGU_CLKOUTSEL 7 /* access CGU_CLKOUTSEL register */ +#define BITP_ROM_SYSCTRL_CGU_DIV 6 /* access CGU_DIV register */ +#define BITP_ROM_SYSCTRL_CGU_STAT 5 /* access CGU_STAT register */ +#define BITP_ROM_SYSCTRL_CGU_CTL 4 /* access CGU_CTL register */ +#define BITP_ROM_SYSCTRL_CGU_RTNSTAT 2 /* Update structure STAT field upon error */ +#define BITP_ROM_SYSCTRL_WRITE 1 /* write registers */ +#define BITP_ROM_SYSCTRL_READ 0 /* read registers */ + +#define BITM_ROM_SYSCTRL_CGU_READ (0x00000001) /* Read CGU registers */ +#define BITM_ROM_SYSCTRL_CGU_WRITE (0x00000002) /* Write registers */ +#define BITM_ROM_SYSCTRL_CGU_RTNSTAT (0x00000004) /* Update structure STAT field upon error or after a write operation */ +#define BITM_ROM_SYSCTRL_CGU_CTL (0x00000010) /* Access CGU_CTL register */ +#define BITM_ROM_SYSCTRL_CGU_STAT (0x00000020) /* Access CGU_STAT register */ +#define BITM_ROM_SYSCTRL_CGU_DIV (0x00000040) /* Access CGU_DIV register */ +#define BITM_ROM_SYSCTRL_CGU_CLKOUTSEL (0x00000080) /* Access CGU_CLKOUTSEL register */ +#define BITM_ROM_SYSCTRL_CGU_AUTODIS (0x00000800) /* Disables auto handling of UPDT and ALGN fields */ +#define BITM_ROM_SYSCTRL_DDR_READ (0x00001000) /* Reads the contents of the DDR registers and stores them into the structure */ +#define BITM_ROM_SYSCTRL_DDR_WRITE (0x00002000) /* Writes the DDR registers from the structure, only really intented for wakeup functionality and not for full DDR configuration */ +#define BITM_ROM_SYSCTRL_WUA_EN (0x00010000) /* Wakeup entry or exit opertation enable */ +#define BITM_ROM_SYSCTRL_WUA_DPMWRITE (0x00020000) /* When set indicates a restore of the PLL and DDR is to be performed otherwise a save is required */ +#define BITM_ROM_SYSCTRL_WUA_CGU (0x00040000) /* Only applicable for a PLL and DDR save operation to the DPM, saves the current settings if cleared or the contents of the structure if set */ +#define BITM_ROM_SYSCTRL_WUA_DDR (0x00080000) /* Only applicable for a PLL and DDR save operation to the DPM, saves the current settings if cleared or the contents of the structure if set */ +#define BITM_ROM_SYSCTRL_WUA_DDRDLLEN (0x00100000) /* Enables saving/restoring of the DDR DLLCTL register */ +#define BITM_ROM_SYSCTRL_WUA_OVERRIDE (0x01000000) +#define BITM_ROM_SYSCTRL_CGU_LOCKINGEN (0x10000000) /* Unlocks the CGU_CTL register */ + + +/* Structures for the syscontrol() function */ +struct STRUCT_ROM_SYSCTRL { + uint32_t ulCGU_CTL; + uint32_t ulCGU_STAT; + uint32_t ulCGU_DIV; + uint32_t ulCGU_CLKOUTSEL; + uint32_t ulWUA_Flags; + uint32_t ulWUA_BootAddr; + uint32_t ulWUA_User; + uint32_t ulDDR_CTL; + uint32_t ulDDR_CFG; + uint32_t ulDDR_TR0; + uint32_t ulDDR_TR1; + uint32_t ulDDR_TR2; + uint32_t ulDDR_MR; + uint32_t ulDDR_EMR1; + uint32_t ulDDR_EMR2; + uint32_t ulDDR_PADCTL; + uint32_t ulDDR_DLLCTL; + uint32_t ulReserved; +}; + +struct bfin_pm_data { + uint32_t magic; + uint32_t resume_addr; + uint32_t sp; +}; + +struct bfin_pm_data bf609_pm_data; + +struct STRUCT_ROM_SYSCTRL configvalues; +uint32_t dactionflags; + +#define FUNC_ROM_SYSCONTROL 0xC8000080 +__attribute__((l1_data)) +static uint32_t (* const bfrom_SysControl)(uint32_t action_flags, struct STRUCT_ROM_SYSCTRL *settings, void *reserved) = (void *)FUNC_ROM_SYSCONTROL; + +__attribute__((l1_text)) +void bfin_cpu_suspend(void) +{ + __asm__ __volatile__( \ + ".align 8;" \ + "idle;" \ + : : \ + ); +} + +__attribute__((l1_text)) +void bfin_deepsleep(unsigned long mask) +{ + uint32_t dpm0_ctl; + + bfin_write32(DPM0_WAKE_EN, 0x10); + bfin_write32(DPM0_WAKE_POL, 0x10); + dpm0_ctl = 0x00000008; + bfin_write32(DPM0_CTL, dpm0_ctl); + SSYNC(); + __asm__ __volatile__( \ + ".align 8;" \ + "idle;" \ + : : \ + ); +#ifdef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH + __asm__ __volatile__( + "R0 = 0;" + "CYCLES = R0;" + "CYCLES2 = R0;" + "R0 = SYSCFG;" + "BITSET(R0, 1);" + "SYSCFG = R0;" + : : : "R0" + ); +#endif + +} + +__attribute__((l1_text)) +void bf609_ddr_sr(void) +{ + uint32_t reg; + + reg = bfin_read_DMC0_CTL(); + reg |= 0x8; + bfin_write_DMC0_CTL(reg); + + while (!(bfin_read_DMC0_STAT() & 0x8)) + continue; +} + +__attribute__((l1_text)) +void bf609_ddr_sr_exit(void) +{ + uint32_t reg; + while (!(bfin_read_DMC0_STAT() & 0x1)) + continue; + + reg = bfin_read_DMC0_CTL(); + reg &= ~0x8; + bfin_write_DMC0_CTL(reg); + + while ((bfin_read_DMC0_STAT() & 0x8)) + continue; +} + +__attribute__((l1_text)) +void bfin_hibernate_syscontrol(void) +{ + configvalues.ulWUA_Flags = (0xAD000000 | BITM_ROM_WUA_EN + | BITM_ROM_WUA_CGU | BITM_ROM_WUA_DDR | BITM_ROM_WUA_DDRDLLEN); + + dactionflags = (BITM_ROM_SYSCTRL_WUA_EN + | BITM_ROM_SYSCTRL_WUA_DPMWRITE | BITM_ROM_SYSCTRL_WUA_CGU + | BITM_ROM_SYSCTRL_WUA_DDR | BITM_ROM_SYSCTRL_WUA_DDRDLLEN); + + bfrom_SysControl(dactionflags, &configvalues, NULL); + + bfin_write32(DPM0_RESTORE5, bfin_read32(DPM0_RESTORE5) | 4); +} + +#ifndef CONFIG_BF60x +# define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1)) +#else +# define SIC_SYSIRQ(irq) ((irq) - IVG15) +#endif +void bfin_hibernate(unsigned long mask) +{ + bfin_write32(DPM0_WAKE_EN, 0x10); + bfin_write32(DPM0_WAKE_POL, 0x10); + bfin_write32(DPM0_PGCNTR, 0x0000FFFF); + bfin_write32(DPM0_HIB_DIS, 0xFFFF); + + printk(KERN_DEBUG "hibernate: restore %x pgcnt %x\n", bfin_read32(DPM0_RESTORE0), bfin_read32(DPM0_PGCNTR)); + + bf609_hibernate(); +} + +void bf609_cpu_pm_enter(suspend_state_t state) +{ + int error; + unsigned long wakeup = 0; + unsigned long wakeup_pol = 0; + +#ifdef CONFIG_PM_BFIN_WAKE_PA15 + wakeup |= PA15WE; +# if CONFIG_PM_BFIN_WAKE_PA15_POL + wakeup_pol |= PA15WE; +# endif +#endif + +#ifdef CONFIG_PM_BFIN_WAKE_PB15 + wakeup |= PB15WE; +# if CONFIG_PM_BFIN_WAKE_PA15_POL + wakeup_pol |= PB15WE; +# endif +#endif + +#ifdef CONFIG_PM_BFIN_WAKE_PC15 + wakeup |= PC15WE; +# if CONFIG_PM_BFIN_WAKE_PC15_POL + wakeup_pol |= PC15WE; +# endif +#endif + +#ifdef CONFIG_PM_BFIN_WAKE_PD06 + wakeup |= PD06WE; +# if CONFIG_PM_BFIN_WAKE_PD06_POL + wakeup_pol |= PD06WE; +# endif +#endif + +#ifdef CONFIG_PM_BFIN_WAKE_PE12 + wakeup |= PE12WE; +# if CONFIG_PM_BFIN_WAKE_PE12_POL + wakeup_pol |= PE12WE; +# endif +#endif + +#ifdef CONFIG_PM_BFIN_WAKE_PG04 + wakeup |= PG04WE; +# if CONFIG_PM_BFIN_WAKE_PG04_POL + wakeup_pol |= PG04WE; +# endif +#endif + +#ifdef CONFIG_PM_BFIN_WAKE_PG13 + wakeup |= PG13WE; +# if CONFIG_PM_BFIN_WAKE_PG13_POL + wakeup_pol |= PG13WE; +# endif +#endif + +#ifdef CONFIG_PM_BFIN_WAKE_USB + wakeup |= USBWE; +# if CONFIG_PM_BFIN_WAKE_USB_POL + wakeup_pol |= USBWE; +# endif +#endif + + error = irq_set_irq_wake(255, 1); + if(error < 0) + printk(KERN_DEBUG "Unable to get irq wake\n"); + error = irq_set_irq_wake(231, 1); + if (error < 0) + printk(KERN_DEBUG "Unable to get irq wake\n"); + + if (state == PM_SUSPEND_STANDBY) + bfin_deepsleep(wakeup); + else { + bfin_hibernate(wakeup); + } +} + +int bf609_cpu_pm_prepare(void) +{ + return 0; +} + +void bf609_cpu_pm_finish(void) +{ + +} + +static struct bfin_cpu_pm_fns bf609_cpu_pm = { + .enter = bf609_cpu_pm_enter, + .prepare = bf609_cpu_pm_prepare, + .finish = bf609_cpu_pm_finish, +}; + +static irqreturn_t test_isr(int irq, void *dev_id) +{ + printk(KERN_DEBUG "gpio irq %d\n", irq); + return IRQ_HANDLED; +} + +static irqreturn_t dpm0_isr(int irq, void *dev_id) +{ + uint32_t wake_stat; + + wake_stat = bfin_read32(DPM0_WAKE_STAT); + printk(KERN_DEBUG "enter %s wake stat %08x\n", __func__, wake_stat); + + bfin_write32(DPM0_WAKE_STAT, wake_stat); + return IRQ_HANDLED; +} + +static int __init bf609_init_pm(void) +{ + int irq; + int error; + +#if CONFIG_PM_BFIN_WAKE_PE12 + irq = gpio_to_irq(GPIO_PE12); + if (irq < 0) { + error = irq; + printk(KERN_DEBUG "Unable to get irq number for GPIO %d, error %d\n", + GPIO_PE12, error); + } + + error = request_irq(irq, test_isr, IRQF_TRIGGER_RISING | IRQF_NO_SUSPEND, "gpiope12", NULL); + if(error < 0) + printk(KERN_DEBUG "Unable to get irq\n"); +#endif + + error = request_irq(IRQ_CGU_EVT, dpm0_isr, IRQF_NO_SUSPEND, "cgu0 event", NULL); + if(error < 0) + printk(KERN_DEBUG "Unable to get irq\n"); + + error = request_irq(IRQ_DPM, dpm0_isr, IRQF_NO_SUSPEND, "dpm0 event", NULL); + if (error < 0) + printk(KERN_DEBUG "Unable to get irq\n"); + + bfin_cpu_pm = &bf609_cpu_pm; + return 0; +} + +late_initcall(bf609_init_pm); diff --git a/arch/blackfin/mach-common/Makefile b/arch/blackfin/mach-common/Makefile index ff299f24aba0..75f0ba29ebb9 100644 --- a/arch/blackfin/mach-common/Makefile +++ b/arch/blackfin/mach-common/Makefile @@ -6,7 +6,10 @@ obj-y := \ cache.o cache-c.o entry.o head.o \ interrupt.o arch_checks.o ints-priority.o -obj-$(CONFIG_PM) += pm.o dpmc_modes.o +obj-$(CONFIG_PM) += pm.o +ifneq ($(CONFIG_BF60x),y) +obj-$(CONFIG_PM) += dpmc_modes.o +endif obj-$(CONFIG_CPU_FREQ) += cpufreq.o obj-$(CONFIG_CPU_VOLTAGE) += dpmc.o obj-$(CONFIG_SMP) += smp.o diff --git a/arch/blackfin/mach-common/clock.h b/arch/blackfin/mach-common/clock.h new file mode 100644 index 000000000000..645ff460a1f2 --- /dev/null +++ b/arch/blackfin/mach-common/clock.h @@ -0,0 +1,27 @@ +#ifndef __MACH_COMMON_CLKDEV_H +#define __MACH_COMMON_CLKDEV_H + +#include <linux/clk.h> + +struct clk_ops { + unsigned long (*get_rate)(struct clk *clk); + unsigned long (*round_rate)(struct clk *clk, unsigned long rate); + int (*set_rate)(struct clk *clk, unsigned long rate); + int (*enable)(struct clk *clk); + int (*disable)(struct clk *clk); +}; + +struct clk { + const char *name; + unsigned long rate; + spinlock_t lock; + u32 flags; + const struct clk_ops *ops; + const struct params *params; + void __iomem *reg; + u32 mask; + u32 shift; +}; + +#endif + diff --git a/arch/blackfin/mach-common/clocks-init.c b/arch/blackfin/mach-common/clocks-init.c index d5cfe611b778..7ad2407d1571 100644 --- a/arch/blackfin/mach-common/clocks-init.c +++ b/arch/blackfin/mach-common/clocks-init.c @@ -15,10 +15,121 @@ #include <asm/mem_init.h> #include <asm/dpmc.h> +#ifdef CONFIG_BF60x +#define CSEL_P 0 +#define S0SEL_P 5 +#define SYSSEL_P 8 +#define S1SEL_P 13 +#define DSEL_P 16 +#define OSEL_P 22 +#define ALGN_P 29 +#define UPDT_P 30 +#define LOCK_P 31 + +#define CGU_CTL_VAL ((CONFIG_VCO_MULT << 8) | CLKIN_HALF) +#define CGU_DIV_VAL \ + ((CONFIG_CCLK_DIV << CSEL_P) | \ + (CONFIG_SCLK_DIV << SYSSEL_P) | \ + (CONFIG_SCLK0_DIV << S0SEL_P) | \ + (CONFIG_SCLK1_DIV << S1SEL_P) | \ + (CONFIG_DCLK_DIV << DSEL_P)) + +#define CONFIG_BFIN_DCLK (((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_DCLK_DIV) / 1000000) +#if ((CONFIG_BFIN_DCLK != 125) && \ + (CONFIG_BFIN_DCLK != 133) && (CONFIG_BFIN_DCLK != 150) && \ + (CONFIG_BFIN_DCLK != 166) && (CONFIG_BFIN_DCLK != 200) && \ + (CONFIG_BFIN_DCLK != 225) && (CONFIG_BFIN_DCLK != 250)) +#error "DCLK must be in (125, 133, 150, 166, 200, 225, 250)MHz" +#endif +struct ddr_config { + u32 ddr_clk; + u32 dmc_ddrctl; + u32 dmc_ddrcfg; + u32 dmc_ddrtr0; + u32 dmc_ddrtr1; + u32 dmc_ddrtr2; + u32 dmc_ddrmr; + u32 dmc_ddrmr1; +}; + +struct ddr_config ddr_config_table[] __attribute__((section(".data_l1"))) = { + [0] = { + .ddr_clk = 125, + .dmc_ddrctl = 0x00000904, + .dmc_ddrcfg = 0x00000422, + .dmc_ddrtr0 = 0x20705212, + .dmc_ddrtr1 = 0x201003CF, + .dmc_ddrtr2 = 0x00320107, + .dmc_ddrmr = 0x00000422, + .dmc_ddrmr1 = 0x4, + }, + [1] = { + .ddr_clk = 133, + .dmc_ddrctl = 0x00000904, + .dmc_ddrcfg = 0x00000422, + .dmc_ddrtr0 = 0x20806313, + .dmc_ddrtr1 = 0x2013040D, + .dmc_ddrtr2 = 0x00320108, + .dmc_ddrmr = 0x00000632, + .dmc_ddrmr1 = 0x4, + }, + [2] = { + .ddr_clk = 150, + .dmc_ddrctl = 0x00000904, + .dmc_ddrcfg = 0x00000422, + .dmc_ddrtr0 = 0x20A07323, + .dmc_ddrtr1 = 0x20160492, + .dmc_ddrtr2 = 0x00320209, + .dmc_ddrmr = 0x00000632, + .dmc_ddrmr1 = 0x4, + }, + [3] = { + .ddr_clk = 166, + .dmc_ddrctl = 0x00000904, + .dmc_ddrcfg = 0x00000422, + .dmc_ddrtr0 = 0x20A07323, + .dmc_ddrtr1 = 0x2016050E, + .dmc_ddrtr2 = 0x00320209, + .dmc_ddrmr = 0x00000632, + .dmc_ddrmr1 = 0x4, + }, + [4] = { + .ddr_clk = 200, + .dmc_ddrctl = 0x00000904, + .dmc_ddrcfg = 0x00000422, + .dmc_ddrtr0 = 0x20a07323, + .dmc_ddrtr1 = 0x2016050f, + .dmc_ddrtr2 = 0x00320509, + .dmc_ddrmr = 0x00000632, + .dmc_ddrmr1 = 0x4, + }, + [5] = { + .ddr_clk = 225, + .dmc_ddrctl = 0x00000904, + .dmc_ddrcfg = 0x00000422, + .dmc_ddrtr0 = 0x20E0A424, + .dmc_ddrtr1 = 0x302006DB, + .dmc_ddrtr2 = 0x0032020D, + .dmc_ddrmr = 0x00000842, + .dmc_ddrmr1 = 0x4, + }, + [6] = { + .ddr_clk = 250, + .dmc_ddrctl = 0x00000904, + .dmc_ddrcfg = 0x00000422, + .dmc_ddrtr0 = 0x20E0A424, + .dmc_ddrtr1 = 0x3020079E, + .dmc_ddrtr2 = 0x0032020D, + .dmc_ddrmr = 0x00000842, + .dmc_ddrmr1 = 0x4, + }, +}; +#else #define SDGCTL_WIDTH (1 << 31) /* SDRAM external data path width */ #define PLL_CTL_VAL \ (((CONFIG_VCO_MULT & 63) << 9) | CLKIN_HALF | \ - (PLL_BYPASS << 8) | (ANOMALY_05000305 ? 0 : 0x8000)) + (PLL_BYPASS << 8) | (ANOMALY_05000305 ? 0 : 0x8000)) +#endif __attribute__((l1_text)) static void do_sync(void) @@ -33,6 +144,44 @@ void init_clocks(void) * in the middle of reprogramming things, and that'll screw us up. * For example, any automatic DMAs left by U-Boot for splash screens. */ + +#ifdef CONFIG_BF60x + int i, dlldatacycle, dll_ctl; + bfin_write32(CGU0_DIV, CGU_DIV_VAL); + bfin_write32(CGU0_CTL, CGU_CTL_VAL); + while ((bfin_read32(CGU0_STAT) & 0x8) || !(bfin_read32(CGU0_STAT) & 0x4)) + continue; + + bfin_write32(CGU0_DIV, CGU_DIV_VAL | (1 << UPDT_P)); + while (bfin_read32(CGU0_STAT) & (1 << 3)) + continue; + + for (i = 0; i < 7; i++) { + if (ddr_config_table[i].ddr_clk == CONFIG_BFIN_DCLK) { + bfin_write_DDR0_CFG(ddr_config_table[i].dmc_ddrcfg); + bfin_write_DDR0_TR0(ddr_config_table[i].dmc_ddrtr0); + bfin_write_DDR0_TR1(ddr_config_table[i].dmc_ddrtr1); + bfin_write_DDR0_TR2(ddr_config_table[i].dmc_ddrtr2); + bfin_write_DDR0_MR(ddr_config_table[i].dmc_ddrmr); + bfin_write_DDR0_EMR1(ddr_config_table[i].dmc_ddrmr1); + bfin_write_DDR0_CTL(ddr_config_table[i].dmc_ddrctl); + break; + } + } + + do_sync(); + while (!(bfin_read_DDR0_STAT() & 0x4)) + continue; + + dlldatacycle = (bfin_read_DDR0_STAT() & 0x00f00000) >> 20; + dll_ctl = bfin_read_DDR0_DLLCTL(); + dll_ctl &= 0x0ff; + bfin_write_DDR0_DLLCTL(dll_ctl | (dlldatacycle << 8)); + + do_sync(); + while (!(bfin_read_DDR0_STAT() & 0x2000)) + continue; +#else size_t i; for (i = 0; i < MAX_DMA_CHANNELS; ++i) { struct dma_register *dma = dma_io_base_addr[i]; @@ -91,6 +240,8 @@ void init_clocks(void) bfin_write_EBIU_DDRQUE(CONFIG_MEM_EBIU_DDRQUE); #endif #endif +#endif do_sync(); bfin_read16(0); + } diff --git a/arch/blackfin/mach-common/cpufreq.c b/arch/blackfin/mach-common/cpufreq.c index 2e6eefd812f4..6e87dc13f6bf 100644 --- a/arch/blackfin/mach-common/cpufreq.c +++ b/arch/blackfin/mach-common/cpufreq.c @@ -10,6 +10,7 @@ #include <linux/module.h> #include <linux/types.h> #include <linux/init.h> +#include <linux/clk.h> #include <linux/cpufreq.h> #include <linux/fs.h> #include <linux/delay.h> @@ -17,6 +18,7 @@ #include <asm/time.h> #include <asm/dpmc.h> + /* this is the table of CCLK frequencies, in Hz */ /* .index is the entry in the auxiliary dpm_state_table[] */ static struct cpufreq_frequency_table bfin_freq_table[] = { @@ -67,12 +69,22 @@ static void __init bfin_init_tables(unsigned long cclk, unsigned long sclk) #else min_cclk = sclk; #endif + +#ifndef CONFIG_BF60x csel = ((bfin_read_PLL_DIV() & CSEL) >> 4); +#else + csel = bfin_read32(CGU0_DIV) & 0x1F; +#endif for (index = 0; (cclk >> index) >= min_cclk && csel <= 3; index++, csel++) { bfin_freq_table[index].frequency = cclk >> index; +#ifndef CONFIG_BF60x dpm_state_table[index].csel = csel << 4; /* Shift now into PLL_DIV bitpos */ dpm_state_table[index].tscale = (TIME_SCALE / (1 << csel)) - 1; +#else + dpm_state_table[index].csel = csel; + dpm_state_table[index].tscale = TIME_SCALE >> index; +#endif pr_debug("cpufreq: freq:%d csel:0x%x tscale:%d\n", bfin_freq_table[index].frequency, @@ -99,14 +111,34 @@ static unsigned int bfin_getfreq_khz(unsigned int cpu) return get_cclk() / 1000; } +#ifdef CONFIG_BF60x +unsigned long cpu_set_cclk(int cpu, unsigned long new) +{ + struct clk *clk; + int ret; + + clk = clk_get(NULL, "CCLK"); + if (IS_ERR(clk)) + return -ENODEV; + + ret = clk_set_rate(clk, new); + clk_put(clk); + return ret; +} +#endif + static int bfin_target(struct cpufreq_policy *poli, unsigned int target_freq, unsigned int relation) { - unsigned int index, plldiv, cpu; +#ifndef CONFIG_BF60x + unsigned int plldiv; +#endif + unsigned int index, cpu; unsigned long flags, cclk_hz; struct cpufreq_freqs freqs; static unsigned long lpj_ref; static unsigned int lpj_ref_freq; + int ret = 0; #if defined(CONFIG_CYCLES_CLOCKSOURCE) cycles_t cycles; @@ -134,9 +166,17 @@ static int bfin_target(struct cpufreq_policy *poli, cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); if (cpu == CPUFREQ_CPU) { flags = hard_local_irq_save(); +#ifndef CONFIG_BF60x plldiv = (bfin_read_PLL_DIV() & SSEL) | dpm_state_table[index].csel; bfin_write_PLL_DIV(plldiv); +#else + ret = cpu_set_cclk(cpu, freqs.new * 1000); + if (ret != 0) { + pr_debug("cpufreq set freq failed %d\n", ret); + break; + } +#endif on_each_cpu(bfin_adjust_core_timer, &index, 1); #if defined(CONFIG_CYCLES_CLOCKSOURCE) cycles = get_cycles(); @@ -161,7 +201,7 @@ static int bfin_target(struct cpufreq_policy *poli, } pr_debug("cpufreq: done\n"); - return 0; + return ret; } static int bfin_verify_speed(struct cpufreq_policy *policy) @@ -169,7 +209,7 @@ static int bfin_verify_speed(struct cpufreq_policy *policy) return cpufreq_frequency_table_verify(policy, bfin_freq_table); } -static int __init __bfin_cpu_init(struct cpufreq_policy *policy) +static int __bfin_cpu_init(struct cpufreq_policy *policy) { unsigned long cclk, sclk; diff --git a/arch/blackfin/mach-common/dpmc_modes.S b/arch/blackfin/mach-common/dpmc_modes.S index 1c534d298de4..de99f3aac2c5 100644 --- a/arch/blackfin/mach-common/dpmc_modes.S +++ b/arch/blackfin/mach-common/dpmc_modes.S @@ -10,7 +10,6 @@ #include <asm/dpmc.h> .section .l1.text - ENTRY(_sleep_mode) [--SP] = (R7:4, P5:3); [--SP] = RETS; @@ -43,6 +42,9 @@ ENTRY(_sleep_mode) BITCLR (R7, 5); w[p0] = R7.L; IDLE; + + bfin_init_pm_bench_cycles; + call _test_pll_locked; RETS = [SP++]; @@ -58,12 +60,13 @@ ENDPROC(_sleep_mode) * * We accept just one argument -- the value to write to VR_CTL. */ + ENTRY(_hibernate_mode) /* Save/setup the regs we need early for minor pipeline optimization */ R4 = R0; + P3.H = hi(VR_CTL); P3.L = lo(VR_CTL); - /* Disable all wakeup sources */ R0 = IWR_DISABLE_ALL; R1 = IWR_DISABLE_ALL; @@ -74,6 +77,9 @@ ENTRY(_hibernate_mode) /* Finally, we climb into our cave to hibernate */ W[P3] = R4.L; + + bfin_init_pm_bench_cycles; + CLI R2; IDLE; .Lforever: @@ -158,6 +164,8 @@ ENTRY(_sleep_deeper) SSYNC; IDLE; + bfin_init_pm_bench_cycles; + call _test_pll_locked; P0.H = hi(PLL_DIV); @@ -276,327 +284,10 @@ ENTRY(_test_pll_locked) ENDPROC(_test_pll_locked) .section .text - -#define PM_REG0 R7 -#define PM_REG1 R6 -#define PM_REG2 R5 -#define PM_REG3 R4 -#define PM_REG4 R3 -#define PM_REG5 R2 -#define PM_REG6 R1 -#define PM_REG7 R0 -#define PM_REG8 P5 -#define PM_REG9 P4 -#define PM_REG10 P3 -#define PM_REG11 P2 -#define PM_REG12 P1 -#define PM_REG13 P0 - -#define PM_REGSET0 R7:7 -#define PM_REGSET1 R7:6 -#define PM_REGSET2 R7:5 -#define PM_REGSET3 R7:4 -#define PM_REGSET4 R7:3 -#define PM_REGSET5 R7:2 -#define PM_REGSET6 R7:1 -#define PM_REGSET7 R7:0 -#define PM_REGSET8 R7:0, P5:5 -#define PM_REGSET9 R7:0, P5:4 -#define PM_REGSET10 R7:0, P5:3 -#define PM_REGSET11 R7:0, P5:2 -#define PM_REGSET12 R7:0, P5:1 -#define PM_REGSET13 R7:0, P5:0 - -#define _PM_PUSH(n, x, w, base) PM_REG##n = w[FP + ((x) - (base))]; -#define _PM_POP(n, x, w, base) w[FP + ((x) - (base))] = PM_REG##n; -#define PM_PUSH_SYNC(n) [--sp] = (PM_REGSET##n); -#define PM_POP_SYNC(n) (PM_REGSET##n) = [sp++]; -#define PM_PUSH(n, x) PM_REG##n = [FP++]; -#define PM_POP(n, x) [FP--] = PM_REG##n; -#define PM_CORE_PUSH(n, x) _PM_PUSH(n, x, , COREMMR_BASE) -#define PM_CORE_POP(n, x) _PM_POP(n, x, , COREMMR_BASE) -#define PM_SYS_PUSH(n, x) _PM_PUSH(n, x, , SYSMMR_BASE) -#define PM_SYS_POP(n, x) _PM_POP(n, x, , SYSMMR_BASE) -#define PM_SYS_PUSH16(n, x) _PM_PUSH(n, x, w, SYSMMR_BASE) -#define PM_SYS_POP16(n, x) _PM_POP(n, x, w, SYSMMR_BASE) - ENTRY(_do_hibernate) - /* - * Save the core regs early so we can blow them away when - * saving/restoring MMR states - */ - [--sp] = (R7:0, P5:0); - [--sp] = fp; - [--sp] = usp; - - [--sp] = i0; - [--sp] = i1; - [--sp] = i2; - [--sp] = i3; - - [--sp] = m0; - [--sp] = m1; - [--sp] = m2; - [--sp] = m3; - - [--sp] = l0; - [--sp] = l1; - [--sp] = l2; - [--sp] = l3; - - [--sp] = b0; - [--sp] = b1; - [--sp] = b2; - [--sp] = b3; - [--sp] = a0.x; - [--sp] = a0.w; - [--sp] = a1.x; - [--sp] = a1.w; - - [--sp] = LC0; - [--sp] = LC1; - [--sp] = LT0; - [--sp] = LT1; - [--sp] = LB0; - [--sp] = LB1; - - /* We can't push RETI directly as that'll change IPEND[4] */ - r7 = RETI; - [--sp] = RETS; - [--sp] = ASTAT; - [--sp] = CYCLES; - [--sp] = CYCLES2; - [--sp] = SYSCFG; - [--sp] = RETX; - [--sp] = SEQSTAT; - [--sp] = r7; - - /* Save first func arg in M3 */ - M3 = R0; - - /* Save system MMRs */ - FP.H = hi(SYSMMR_BASE); - FP.L = lo(SYSMMR_BASE); - -#ifdef SIC_IMASK0 - PM_SYS_PUSH(0, SIC_IMASK0) - PM_SYS_PUSH(1, SIC_IMASK1) -# ifdef SIC_IMASK2 - PM_SYS_PUSH(2, SIC_IMASK2) -# endif -#else - PM_SYS_PUSH(0, SIC_IMASK) -#endif -#ifdef SIC_IAR0 - PM_SYS_PUSH(3, SIC_IAR0) - PM_SYS_PUSH(4, SIC_IAR1) - PM_SYS_PUSH(5, SIC_IAR2) -#endif -#ifdef SIC_IAR3 - PM_SYS_PUSH(6, SIC_IAR3) -#endif -#ifdef SIC_IAR4 - PM_SYS_PUSH(7, SIC_IAR4) - PM_SYS_PUSH(8, SIC_IAR5) - PM_SYS_PUSH(9, SIC_IAR6) -#endif -#ifdef SIC_IAR7 - PM_SYS_PUSH(10, SIC_IAR7) -#endif -#ifdef SIC_IAR8 - PM_SYS_PUSH(11, SIC_IAR8) - PM_SYS_PUSH(12, SIC_IAR9) - PM_SYS_PUSH(13, SIC_IAR10) -#endif - PM_PUSH_SYNC(13) -#ifdef SIC_IAR11 - PM_SYS_PUSH(0, SIC_IAR11) -#endif - -#ifdef SIC_IWR - PM_SYS_PUSH(1, SIC_IWR) -#endif -#ifdef SIC_IWR0 - PM_SYS_PUSH(1, SIC_IWR0) -#endif -#ifdef SIC_IWR1 - PM_SYS_PUSH(2, SIC_IWR1) -#endif -#ifdef SIC_IWR2 - PM_SYS_PUSH(3, SIC_IWR2) -#endif - -#ifdef PINT0_ASSIGN - PM_SYS_PUSH(4, PINT0_MASK_SET) - PM_SYS_PUSH(5, PINT1_MASK_SET) - PM_SYS_PUSH(6, PINT2_MASK_SET) - PM_SYS_PUSH(7, PINT3_MASK_SET) - PM_SYS_PUSH(8, PINT0_ASSIGN) - PM_SYS_PUSH(9, PINT1_ASSIGN) - PM_SYS_PUSH(10, PINT2_ASSIGN) - PM_SYS_PUSH(11, PINT3_ASSIGN) - PM_SYS_PUSH(12, PINT0_INVERT_SET) - PM_SYS_PUSH(13, PINT1_INVERT_SET) - PM_PUSH_SYNC(13) - PM_SYS_PUSH(0, PINT2_INVERT_SET) - PM_SYS_PUSH(1, PINT3_INVERT_SET) - PM_SYS_PUSH(2, PINT0_EDGE_SET) - PM_SYS_PUSH(3, PINT1_EDGE_SET) - PM_SYS_PUSH(4, PINT2_EDGE_SET) - PM_SYS_PUSH(5, PINT3_EDGE_SET) -#endif - - PM_SYS_PUSH16(6, SYSCR) - - PM_SYS_PUSH16(7, EBIU_AMGCTL) - PM_SYS_PUSH(8, EBIU_AMBCTL0) - PM_SYS_PUSH(9, EBIU_AMBCTL1) -#ifdef EBIU_FCTL - PM_SYS_PUSH(10, EBIU_MBSCTL) - PM_SYS_PUSH(11, EBIU_MODE) - PM_SYS_PUSH(12, EBIU_FCTL) - PM_PUSH_SYNC(12) -#else - PM_PUSH_SYNC(9) -#endif - - /* Save Core MMRs */ - I0.H = hi(COREMMR_BASE); - I0.L = lo(COREMMR_BASE); - I1 = I0; - I2 = I0; - I3 = I0; - B0 = I0; - B1 = I0; - B2 = I0; - B3 = I0; - I1.L = lo(DCPLB_ADDR0); - I2.L = lo(DCPLB_DATA0); - I3.L = lo(ICPLB_ADDR0); - B0.L = lo(ICPLB_DATA0); - B1.L = lo(EVT2); - B2.L = lo(IMASK); - B3.L = lo(TCNTL); - - /* DCPLB Addr */ - FP = I1; - PM_PUSH(0, DCPLB_ADDR0) - PM_PUSH(1, DCPLB_ADDR1) - PM_PUSH(2, DCPLB_ADDR2) - PM_PUSH(3, DCPLB_ADDR3) - PM_PUSH(4, DCPLB_ADDR4) - PM_PUSH(5, DCPLB_ADDR5) - PM_PUSH(6, DCPLB_ADDR6) - PM_PUSH(7, DCPLB_ADDR7) - PM_PUSH(8, DCPLB_ADDR8) - PM_PUSH(9, DCPLB_ADDR9) - PM_PUSH(10, DCPLB_ADDR10) - PM_PUSH(11, DCPLB_ADDR11) - PM_PUSH(12, DCPLB_ADDR12) - PM_PUSH(13, DCPLB_ADDR13) - PM_PUSH_SYNC(13) - PM_PUSH(0, DCPLB_ADDR14) - PM_PUSH(1, DCPLB_ADDR15) - - /* DCPLB Data */ - FP = I2; - PM_PUSH(2, DCPLB_DATA0) - PM_PUSH(3, DCPLB_DATA1) - PM_PUSH(4, DCPLB_DATA2) - PM_PUSH(5, DCPLB_DATA3) - PM_PUSH(6, DCPLB_DATA4) - PM_PUSH(7, DCPLB_DATA5) - PM_PUSH(8, DCPLB_DATA6) - PM_PUSH(9, DCPLB_DATA7) - PM_PUSH(10, DCPLB_DATA8) - PM_PUSH(11, DCPLB_DATA9) - PM_PUSH(12, DCPLB_DATA10) - PM_PUSH(13, DCPLB_DATA11) - PM_PUSH_SYNC(13) - PM_PUSH(0, DCPLB_DATA12) - PM_PUSH(1, DCPLB_DATA13) - PM_PUSH(2, DCPLB_DATA14) - PM_PUSH(3, DCPLB_DATA15) - - /* ICPLB Addr */ - FP = I3; - PM_PUSH(4, ICPLB_ADDR0) - PM_PUSH(5, ICPLB_ADDR1) - PM_PUSH(6, ICPLB_ADDR2) - PM_PUSH(7, ICPLB_ADDR3) - PM_PUSH(8, ICPLB_ADDR4) - PM_PUSH(9, ICPLB_ADDR5) - PM_PUSH(10, ICPLB_ADDR6) - PM_PUSH(11, ICPLB_ADDR7) - PM_PUSH(12, ICPLB_ADDR8) - PM_PUSH(13, ICPLB_ADDR9) - PM_PUSH_SYNC(13) - PM_PUSH(0, ICPLB_ADDR10) - PM_PUSH(1, ICPLB_ADDR11) - PM_PUSH(2, ICPLB_ADDR12) - PM_PUSH(3, ICPLB_ADDR13) - PM_PUSH(4, ICPLB_ADDR14) - PM_PUSH(5, ICPLB_ADDR15) - - /* ICPLB Data */ - FP = B0; - PM_PUSH(6, ICPLB_DATA0) - PM_PUSH(7, ICPLB_DATA1) - PM_PUSH(8, ICPLB_DATA2) - PM_PUSH(9, ICPLB_DATA3) - PM_PUSH(10, ICPLB_DATA4) - PM_PUSH(11, ICPLB_DATA5) - PM_PUSH(12, ICPLB_DATA6) - PM_PUSH(13, ICPLB_DATA7) - PM_PUSH_SYNC(13) - PM_PUSH(0, ICPLB_DATA8) - PM_PUSH(1, ICPLB_DATA9) - PM_PUSH(2, ICPLB_DATA10) - PM_PUSH(3, ICPLB_DATA11) - PM_PUSH(4, ICPLB_DATA12) - PM_PUSH(5, ICPLB_DATA13) - PM_PUSH(6, ICPLB_DATA14) - PM_PUSH(7, ICPLB_DATA15) - - /* Event Vectors */ - FP = B1; - PM_PUSH(8, EVT2) - PM_PUSH(9, EVT3) - FP += 4; /* EVT4 */ - PM_PUSH(10, EVT5) - PM_PUSH(11, EVT6) - PM_PUSH(12, EVT7) - PM_PUSH(13, EVT8) - PM_PUSH_SYNC(13) - PM_PUSH(0, EVT9) - PM_PUSH(1, EVT10) - PM_PUSH(2, EVT11) - PM_PUSH(3, EVT12) - PM_PUSH(4, EVT13) - PM_PUSH(5, EVT14) - PM_PUSH(6, EVT15) - - /* CEC */ - FP = B2; - PM_PUSH(7, IMASK) - FP += 4; /* IPEND */ - PM_PUSH(8, ILAT) - PM_PUSH(9, IPRIO) - - /* Core Timer */ - FP = B3; - PM_PUSH(10, TCNTL) - PM_PUSH(11, TPERIOD) - PM_PUSH(12, TSCALE) - PM_PUSH(13, TCOUNT) - PM_PUSH_SYNC(13) - - /* Misc non-contiguous registers */ - FP = I0; - PM_CORE_PUSH(0, DMEM_CONTROL); - PM_CORE_PUSH(1, IMEM_CONTROL); - PM_CORE_PUSH(2, TBUFCTL); - PM_PUSH_SYNC(2) + bfin_cpu_reg_save; + bfin_sys_mmr_save; + bfin_core_mmr_save; /* Setup args to hibernate mode early for pipeline optimization */ R0 = M3; @@ -618,274 +309,9 @@ ENTRY(_do_hibernate) .Lpm_resume_here: - /* Restore Core MMRs */ - I0.H = hi(COREMMR_BASE); - I0.L = lo(COREMMR_BASE); - I1 = I0; - I2 = I0; - I3 = I0; - B0 = I0; - B1 = I0; - B2 = I0; - B3 = I0; - I1.L = lo(DCPLB_ADDR15); - I2.L = lo(DCPLB_DATA15); - I3.L = lo(ICPLB_ADDR15); - B0.L = lo(ICPLB_DATA15); - B1.L = lo(EVT15); - B2.L = lo(IPRIO); - B3.L = lo(TCOUNT); - - /* Misc non-contiguous registers */ - FP = I0; - PM_POP_SYNC(2) - PM_CORE_POP(2, TBUFCTL) - PM_CORE_POP(1, IMEM_CONTROL) - PM_CORE_POP(0, DMEM_CONTROL) - - /* Core Timer */ - PM_POP_SYNC(13) - FP = B3; - PM_POP(13, TCOUNT) - PM_POP(12, TSCALE) - PM_POP(11, TPERIOD) - PM_POP(10, TCNTL) - - /* CEC */ - FP = B2; - PM_POP(9, IPRIO) - PM_POP(8, ILAT) - FP += -4; /* IPEND */ - PM_POP(7, IMASK) - - /* Event Vectors */ - FP = B1; - PM_POP(6, EVT15) - PM_POP(5, EVT14) - PM_POP(4, EVT13) - PM_POP(3, EVT12) - PM_POP(2, EVT11) - PM_POP(1, EVT10) - PM_POP(0, EVT9) - PM_POP_SYNC(13) - PM_POP(13, EVT8) - PM_POP(12, EVT7) - PM_POP(11, EVT6) - PM_POP(10, EVT5) - FP += -4; /* EVT4 */ - PM_POP(9, EVT3) - PM_POP(8, EVT2) - - /* ICPLB Data */ - FP = B0; - PM_POP(7, ICPLB_DATA15) - PM_POP(6, ICPLB_DATA14) - PM_POP(5, ICPLB_DATA13) - PM_POP(4, ICPLB_DATA12) - PM_POP(3, ICPLB_DATA11) - PM_POP(2, ICPLB_DATA10) - PM_POP(1, ICPLB_DATA9) - PM_POP(0, ICPLB_DATA8) - PM_POP_SYNC(13) - PM_POP(13, ICPLB_DATA7) - PM_POP(12, ICPLB_DATA6) - PM_POP(11, ICPLB_DATA5) - PM_POP(10, ICPLB_DATA4) - PM_POP(9, ICPLB_DATA3) - PM_POP(8, ICPLB_DATA2) - PM_POP(7, ICPLB_DATA1) - PM_POP(6, ICPLB_DATA0) - - /* ICPLB Addr */ - FP = I3; - PM_POP(5, ICPLB_ADDR15) - PM_POP(4, ICPLB_ADDR14) - PM_POP(3, ICPLB_ADDR13) - PM_POP(2, ICPLB_ADDR12) - PM_POP(1, ICPLB_ADDR11) - PM_POP(0, ICPLB_ADDR10) - PM_POP_SYNC(13) - PM_POP(13, ICPLB_ADDR9) - PM_POP(12, ICPLB_ADDR8) - PM_POP(11, ICPLB_ADDR7) - PM_POP(10, ICPLB_ADDR6) - PM_POP(9, ICPLB_ADDR5) - PM_POP(8, ICPLB_ADDR4) - PM_POP(7, ICPLB_ADDR3) - PM_POP(6, ICPLB_ADDR2) - PM_POP(5, ICPLB_ADDR1) - PM_POP(4, ICPLB_ADDR0) - - /* DCPLB Data */ - FP = I2; - PM_POP(3, DCPLB_DATA15) - PM_POP(2, DCPLB_DATA14) - PM_POP(1, DCPLB_DATA13) - PM_POP(0, DCPLB_DATA12) - PM_POP_SYNC(13) - PM_POP(13, DCPLB_DATA11) - PM_POP(12, DCPLB_DATA10) - PM_POP(11, DCPLB_DATA9) - PM_POP(10, DCPLB_DATA8) - PM_POP(9, DCPLB_DATA7) - PM_POP(8, DCPLB_DATA6) - PM_POP(7, DCPLB_DATA5) - PM_POP(6, DCPLB_DATA4) - PM_POP(5, DCPLB_DATA3) - PM_POP(4, DCPLB_DATA2) - PM_POP(3, DCPLB_DATA1) - PM_POP(2, DCPLB_DATA0) - - /* DCPLB Addr */ - FP = I1; - PM_POP(1, DCPLB_ADDR15) - PM_POP(0, DCPLB_ADDR14) - PM_POP_SYNC(13) - PM_POP(13, DCPLB_ADDR13) - PM_POP(12, DCPLB_ADDR12) - PM_POP(11, DCPLB_ADDR11) - PM_POP(10, DCPLB_ADDR10) - PM_POP(9, DCPLB_ADDR9) - PM_POP(8, DCPLB_ADDR8) - PM_POP(7, DCPLB_ADDR7) - PM_POP(6, DCPLB_ADDR6) - PM_POP(5, DCPLB_ADDR5) - PM_POP(4, DCPLB_ADDR4) - PM_POP(3, DCPLB_ADDR3) - PM_POP(2, DCPLB_ADDR2) - PM_POP(1, DCPLB_ADDR1) - PM_POP(0, DCPLB_ADDR0) - - /* Restore System MMRs */ - FP.H = hi(SYSMMR_BASE); - FP.L = lo(SYSMMR_BASE); - -#ifdef EBIU_FCTL - PM_POP_SYNC(12) - PM_SYS_POP(12, EBIU_FCTL) - PM_SYS_POP(11, EBIU_MODE) - PM_SYS_POP(10, EBIU_MBSCTL) -#else - PM_POP_SYNC(9) -#endif - PM_SYS_POP(9, EBIU_AMBCTL1) - PM_SYS_POP(8, EBIU_AMBCTL0) - PM_SYS_POP16(7, EBIU_AMGCTL) - - PM_SYS_POP16(6, SYSCR) - -#ifdef PINT0_ASSIGN - PM_SYS_POP(5, PINT3_EDGE_SET) - PM_SYS_POP(4, PINT2_EDGE_SET) - PM_SYS_POP(3, PINT1_EDGE_SET) - PM_SYS_POP(2, PINT0_EDGE_SET) - PM_SYS_POP(1, PINT3_INVERT_SET) - PM_SYS_POP(0, PINT2_INVERT_SET) - PM_POP_SYNC(13) - PM_SYS_POP(13, PINT1_INVERT_SET) - PM_SYS_POP(12, PINT0_INVERT_SET) - PM_SYS_POP(11, PINT3_ASSIGN) - PM_SYS_POP(10, PINT2_ASSIGN) - PM_SYS_POP(9, PINT1_ASSIGN) - PM_SYS_POP(8, PINT0_ASSIGN) - PM_SYS_POP(7, PINT3_MASK_SET) - PM_SYS_POP(6, PINT2_MASK_SET) - PM_SYS_POP(5, PINT1_MASK_SET) - PM_SYS_POP(4, PINT0_MASK_SET) -#endif - -#ifdef SIC_IWR2 - PM_SYS_POP(3, SIC_IWR2) -#endif -#ifdef SIC_IWR1 - PM_SYS_POP(2, SIC_IWR1) -#endif -#ifdef SIC_IWR0 - PM_SYS_POP(1, SIC_IWR0) -#endif -#ifdef SIC_IWR - PM_SYS_POP(1, SIC_IWR) -#endif - -#ifdef SIC_IAR11 - PM_SYS_POP(0, SIC_IAR11) -#endif - PM_POP_SYNC(13) -#ifdef SIC_IAR8 - PM_SYS_POP(13, SIC_IAR10) - PM_SYS_POP(12, SIC_IAR9) - PM_SYS_POP(11, SIC_IAR8) -#endif -#ifdef SIC_IAR7 - PM_SYS_POP(10, SIC_IAR7) -#endif -#ifdef SIC_IAR6 - PM_SYS_POP(9, SIC_IAR6) - PM_SYS_POP(8, SIC_IAR5) - PM_SYS_POP(7, SIC_IAR4) -#endif -#ifdef SIC_IAR3 - PM_SYS_POP(6, SIC_IAR3) -#endif -#ifdef SIC_IAR0 - PM_SYS_POP(5, SIC_IAR2) - PM_SYS_POP(4, SIC_IAR1) - PM_SYS_POP(3, SIC_IAR0) -#endif -#ifdef SIC_IMASK0 -# ifdef SIC_IMASK2 - PM_SYS_POP(2, SIC_IMASK2) -# endif - PM_SYS_POP(1, SIC_IMASK1) - PM_SYS_POP(0, SIC_IMASK0) -#else - PM_SYS_POP(0, SIC_IMASK) -#endif - - /* Restore Core Registers */ - RETI = [sp++]; - SEQSTAT = [sp++]; - RETX = [sp++]; - SYSCFG = [sp++]; - CYCLES2 = [sp++]; - CYCLES = [sp++]; - ASTAT = [sp++]; - RETS = [sp++]; - - LB1 = [sp++]; - LB0 = [sp++]; - LT1 = [sp++]; - LT0 = [sp++]; - LC1 = [sp++]; - LC0 = [sp++]; - - a1.w = [sp++]; - a1.x = [sp++]; - a0.w = [sp++]; - a0.x = [sp++]; - b3 = [sp++]; - b2 = [sp++]; - b1 = [sp++]; - b0 = [sp++]; - - l3 = [sp++]; - l2 = [sp++]; - l1 = [sp++]; - l0 = [sp++]; - - m3 = [sp++]; - m2 = [sp++]; - m1 = [sp++]; - m0 = [sp++]; - - i3 = [sp++]; - i2 = [sp++]; - i1 = [sp++]; - i0 = [sp++]; - - usp = [sp++]; - fp = [sp++]; - (R7:0, P5:0) = [sp++]; + bfin_core_mmr_restore; + bfin_sys_mmr_restore; + bfin_cpu_reg_restore; [--sp] = RETI; /* Clear Global Interrupt Disable */ SP += 4; diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S index 4698a9800522..80aa2535e2c9 100644 --- a/arch/blackfin/mach-common/entry.S +++ b/arch/blackfin/mach-common/entry.S @@ -1141,7 +1141,8 @@ ENTRY(_schedule_and_signal_from_int) sti r0; /* finish the userspace "atomic" functions for it */ - r1 = FIXED_CODE_END; + r1.l = lo(FIXED_CODE_END); + r1.h = hi(FIXED_CODE_END); r2 = [sp + PT_PC]; cc = r1 <= r2; if cc jump .Lresume_userspace (bp); @@ -1376,7 +1377,7 @@ END(_ex_table) ENTRY(_sys_call_table) .long _sys_restart_syscall /* 0 */ .long _sys_exit - .long _sys_fork + .long _sys_ni_syscall /* fork */ .long _sys_read .long _sys_write .long _sys_open /* 5 */ diff --git a/arch/blackfin/mach-common/head.S b/arch/blackfin/mach-common/head.S index 8b4d98854403..31515f0146f9 100644 --- a/arch/blackfin/mach-common/head.S +++ b/arch/blackfin/mach-common/head.S @@ -210,14 +210,12 @@ ENDPROC(__start) ENTRY(_real_start) /* Enable nested interrupts */ [--sp] = reti; - /* watchdog off for now */ p0.l = lo(WDOG_CTL); p0.h = hi(WDOG_CTL); r0 = 0xAD6(z); w[p0] = r0; ssync; - /* Pass the u-boot arguments to the global value command line */ R0 = R7; call _cmdline_init; diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c index 332dace6af34..2729cba715b0 100644 --- a/arch/blackfin/mach-common/ints-priority.c +++ b/arch/blackfin/mach-common/ints-priority.c @@ -16,6 +16,8 @@ #include <linux/seq_file.h> #include <linux/irq.h> #include <linux/sched.h> +#include <linux/syscore_ops.h> +#include <asm/delay.h> #ifdef CONFIG_IPIPE #include <linux/ipipe.h> #endif @@ -25,7 +27,11 @@ #include <asm/irq_handler.h> #include <asm/dpmc.h> -#define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1)) +#ifndef CONFIG_BF60x +# define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1)) +#else +# define SIC_SYSIRQ(irq) ((irq) - IVG15) +#endif /* * NOTES: @@ -50,6 +56,7 @@ unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */ unsigned vr_wakeup; #endif +#ifndef CONFIG_BF60x static struct ivgx { /* irq number for request_irq, available in mach-bf5xx/irq.h */ unsigned int irqno; @@ -78,7 +85,8 @@ static void __init search_IAR(void) for (irqN = 0; irqN < NR_PERI_INTS; irqN += 4) { int irqn; - u32 iar = bfin_read32((unsigned long *)SIC_IAR0 + + u32 iar = + bfin_read32((unsigned long *)SIC_IAR0 + #if defined(CONFIG_BF51x) || defined(CONFIG_BF52x) || \ defined(CONFIG_BF538) || defined(CONFIG_BF539) ((irqN % 32) >> 3) + ((irqN / 32) * ((SIC_IAR4 - SIC_IAR0) / 4)) @@ -86,7 +94,6 @@ static void __init search_IAR(void) (irqN >> 3) #endif ); - for (irqn = irqN; irqn < irqN + 4; ++irqn) { int iar_shift = (irqn & 7) * 4; if (ivg == (0xf & (iar >> iar_shift))) { @@ -99,11 +106,11 @@ static void __init search_IAR(void) } } } +#endif /* * This is for core internal IRQs */ - void bfin_ack_noop(struct irq_data *d) { /* Dummy function. */ @@ -136,21 +143,21 @@ static void bfin_core_unmask_irq(struct irq_data *d) void bfin_internal_mask_irq(unsigned int irq) { unsigned long flags = hard_local_irq_save(); - +#ifndef CONFIG_BF60x #ifdef SIC_IMASK0 unsigned mask_bank = SIC_SYSIRQ(irq) / 32; unsigned mask_bit = SIC_SYSIRQ(irq) % 32; bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) & - ~(1 << mask_bit)); -# ifdef CONFIG_SMP + ~(1 << mask_bit)); +# if defined(CONFIG_SMP) || defined(CONFIG_ICC) bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) & - ~(1 << mask_bit)); + ~(1 << mask_bit)); # endif #else bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() & - ~(1 << SIC_SYSIRQ(irq))); + ~(1 << SIC_SYSIRQ(irq))); +#endif /* end of SIC_IMASK0 */ #endif - hard_local_irq_restore(flags); } @@ -160,7 +167,7 @@ static void bfin_internal_mask_irq_chip(struct irq_data *d) } #ifdef CONFIG_SMP -static void bfin_internal_unmask_irq_affinity(unsigned int irq, +void bfin_internal_unmask_irq_affinity(unsigned int irq, const struct cpumask *affinity) #else void bfin_internal_unmask_irq(unsigned int irq) @@ -168,6 +175,7 @@ void bfin_internal_unmask_irq(unsigned int irq) { unsigned long flags = hard_local_irq_save(); +#ifndef CONFIG_BF60x #ifdef SIC_IMASK0 unsigned mask_bank = SIC_SYSIRQ(irq) / 32; unsigned mask_bit = SIC_SYSIRQ(irq) % 32; @@ -175,22 +183,239 @@ void bfin_internal_unmask_irq(unsigned int irq) if (cpumask_test_cpu(0, affinity)) # endif bfin_write_SIC_IMASK(mask_bank, - bfin_read_SIC_IMASK(mask_bank) | - (1 << mask_bit)); + bfin_read_SIC_IMASK(mask_bank) | + (1 << mask_bit)); # ifdef CONFIG_SMP if (cpumask_test_cpu(1, affinity)) bfin_write_SICB_IMASK(mask_bank, - bfin_read_SICB_IMASK(mask_bank) | - (1 << mask_bit)); + bfin_read_SICB_IMASK(mask_bank) | + (1 << mask_bit)); # endif #else bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() | - (1 << SIC_SYSIRQ(irq))); + (1 << SIC_SYSIRQ(irq))); +#endif #endif + hard_local_irq_restore(flags); +} + +#ifdef CONFIG_BF60x +static void bfin_sec_preflow_handler(struct irq_data *d) +{ + unsigned long flags = hard_local_irq_save(); + unsigned int sid = SIC_SYSIRQ(d->irq); + + bfin_write_SEC_SCI(0, SEC_CSID, sid); + + hard_local_irq_restore(flags); +} + +static void bfin_sec_mask_ack_irq(struct irq_data *d) +{ + unsigned long flags = hard_local_irq_save(); + unsigned int sid = SIC_SYSIRQ(d->irq); + + bfin_write_SEC_SCI(0, SEC_CSID, sid); hard_local_irq_restore(flags); } +static void bfin_sec_unmask_irq(struct irq_data *d) +{ + unsigned long flags = hard_local_irq_save(); + unsigned int sid = SIC_SYSIRQ(d->irq); + + bfin_write32(SEC_END, sid); + + hard_local_irq_restore(flags); +} + +static void bfin_sec_enable_ssi(unsigned int sid) +{ + unsigned long flags = hard_local_irq_save(); + uint32_t reg_sctl = bfin_read_SEC_SCTL(sid); + + reg_sctl |= SEC_SCTL_SRC_EN; + bfin_write_SEC_SCTL(sid, reg_sctl); + + hard_local_irq_restore(flags); +} + +static void bfin_sec_disable_ssi(unsigned int sid) +{ + unsigned long flags = hard_local_irq_save(); + uint32_t reg_sctl = bfin_read_SEC_SCTL(sid); + + reg_sctl &= ((uint32_t)~SEC_SCTL_SRC_EN); + bfin_write_SEC_SCTL(sid, reg_sctl); + + hard_local_irq_restore(flags); +} + +static void bfin_sec_set_ssi_coreid(unsigned int sid, unsigned int coreid) +{ + unsigned long flags = hard_local_irq_save(); + uint32_t reg_sctl = bfin_read_SEC_SCTL(sid); + + reg_sctl &= ((uint32_t)~SEC_SCTL_CTG); + bfin_write_SEC_SCTL(sid, reg_sctl | ((coreid << 20) & SEC_SCTL_CTG)); + + hard_local_irq_restore(flags); +} + +static void bfin_sec_enable_sci(unsigned int sid) +{ + unsigned long flags = hard_local_irq_save(); + uint32_t reg_sctl = bfin_read_SEC_SCTL(sid); + + if (sid == SIC_SYSIRQ(IRQ_WATCH0)) + reg_sctl |= SEC_SCTL_FAULT_EN; + else + reg_sctl |= SEC_SCTL_INT_EN; + bfin_write_SEC_SCTL(sid, reg_sctl); + + hard_local_irq_restore(flags); +} + +static void bfin_sec_disable_sci(unsigned int sid) +{ + unsigned long flags = hard_local_irq_save(); + uint32_t reg_sctl = bfin_read_SEC_SCTL(sid); + + reg_sctl &= ((uint32_t)~SEC_SCTL_INT_EN); + bfin_write_SEC_SCTL(sid, reg_sctl); + + hard_local_irq_restore(flags); +} + +static void bfin_sec_enable(struct irq_data *d) +{ + unsigned long flags = hard_local_irq_save(); + unsigned int sid = SIC_SYSIRQ(d->irq); + + bfin_sec_enable_sci(sid); + bfin_sec_enable_ssi(sid); + + hard_local_irq_restore(flags); +} + +static void bfin_sec_disable(struct irq_data *d) +{ + unsigned long flags = hard_local_irq_save(); + unsigned int sid = SIC_SYSIRQ(d->irq); + + bfin_sec_disable_sci(sid); + bfin_sec_disable_ssi(sid); + + hard_local_irq_restore(flags); +} + +static void bfin_sec_raise_irq(unsigned int sid) +{ + unsigned long flags = hard_local_irq_save(); + + bfin_write32(SEC_RAISE, sid); + + hard_local_irq_restore(flags); +} + +static void init_software_driven_irq(void) +{ + bfin_sec_set_ssi_coreid(34, 0); + bfin_sec_set_ssi_coreid(35, 1); + bfin_sec_set_ssi_coreid(36, 0); + bfin_sec_set_ssi_coreid(37, 1); +} + +void bfin_sec_resume(void) +{ + bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET); + udelay(100); + bfin_write_SEC_GCTL(SEC_GCTL_EN); + bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN); +} + +void handle_sec_sfi_fault(uint32_t gstat) +{ + +} + +void handle_sec_sci_fault(uint32_t gstat) +{ + uint32_t core_id; + uint32_t cstat; + + core_id = gstat & SEC_GSTAT_SCI; + cstat = bfin_read_SEC_SCI(core_id, SEC_CSTAT); + if (cstat & SEC_CSTAT_ERR) { + switch (cstat & SEC_CSTAT_ERRC) { + case SEC_CSTAT_ACKERR: + printk(KERN_DEBUG "sec ack err\n"); + break; + default: + printk(KERN_DEBUG "sec sci unknow err\n"); + } + } + +} + +void handle_sec_ssi_fault(uint32_t gstat) +{ + uint32_t sid; + uint32_t sstat; + + sid = gstat & SEC_GSTAT_SID; + sstat = bfin_read_SEC_SSTAT(sid); + +} + +void handle_sec_fault(unsigned int irq, struct irq_desc *desc) +{ + uint32_t sec_gstat; + + raw_spin_lock(&desc->lock); + + sec_gstat = bfin_read32(SEC_GSTAT); + if (sec_gstat & SEC_GSTAT_ERR) { + + switch (sec_gstat & SEC_GSTAT_ERRC) { + case 0: + handle_sec_sfi_fault(sec_gstat); + break; + case SEC_GSTAT_SCIERR: + handle_sec_sci_fault(sec_gstat); + break; + case SEC_GSTAT_SSIERR: + handle_sec_ssi_fault(sec_gstat); + break; + } + + + } + + raw_spin_unlock(&desc->lock); +} + +static int sec_suspend(void) +{ + return 0; +} + +static void sec_resume(void) +{ + bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET); + udelay(100); + bfin_write_SEC_GCTL(SEC_GCTL_EN); + bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN); +} + +static struct syscore_ops sec_pm_syscore_ops = { + .suspend = sec_suspend, + .resume = sec_resume, +}; + +#endif + #ifdef CONFIG_SMP static void bfin_internal_unmask_irq_chip(struct irq_data *d) { @@ -212,7 +437,7 @@ static void bfin_internal_unmask_irq_chip(struct irq_data *d) } #endif -#ifdef CONFIG_PM +#if defined(CONFIG_PM) && !defined(CONFIG_BF60x) int bfin_internal_set_wake(unsigned int irq, unsigned int state) { u32 bank, bit, wakeup = 0; @@ -271,22 +496,20 @@ static int bfin_internal_set_wake_chip(struct irq_data *d, unsigned int state) return bfin_internal_set_wake(d->irq, state); } #else +# define bfin_internal_set_wake(irq, state) # define bfin_internal_set_wake_chip NULL #endif static struct irq_chip bfin_core_irqchip = { .name = "CORE", - .irq_ack = bfin_ack_noop, .irq_mask = bfin_core_mask_irq, .irq_unmask = bfin_core_unmask_irq, }; static struct irq_chip bfin_internal_irqchip = { .name = "INTN", - .irq_ack = bfin_ack_noop, .irq_mask = bfin_internal_mask_irq_chip, .irq_unmask = bfin_internal_unmask_irq_chip, - .irq_mask_ack = bfin_internal_mask_irq_chip, .irq_disable = bfin_internal_mask_irq_chip, .irq_enable = bfin_internal_unmask_irq_chip, #ifdef CONFIG_SMP @@ -295,6 +518,18 @@ static struct irq_chip bfin_internal_irqchip = { .irq_set_wake = bfin_internal_set_wake_chip, }; +#ifdef CONFIG_BF60x +static struct irq_chip bfin_sec_irqchip = { + .name = "SEC", + .irq_mask_ack = bfin_sec_mask_ack_irq, + .irq_mask = bfin_sec_mask_ack_irq, + .irq_unmask = bfin_sec_unmask_irq, + .irq_eoi = bfin_sec_unmask_irq, + .irq_disable = bfin_sec_disable, + .irq_enable = bfin_sec_enable, +}; +#endif + void bfin_handle_irq(unsigned irq) { #ifdef CONFIG_IPIPE @@ -396,8 +631,6 @@ int bfin_mac_status_set_wake(struct irq_data *d, unsigned int state) static struct irq_chip bfin_mac_status_irqchip = { .name = "MACST", - .irq_ack = bfin_ack_noop, - .irq_mask_ack = bfin_mac_status_mask_irq, .irq_mask = bfin_mac_status_mask_irq, .irq_unmask = bfin_mac_status_unmask_irq, .irq_set_wake = bfin_mac_status_set_wake, @@ -421,15 +654,15 @@ void bfin_demux_mac_status_irq(unsigned int int_err_irq, } else { bfin_mac_status_ack_irq(irq); pr_debug("IRQ %d:" - " MASKED MAC ERROR INTERRUPT ASSERTED\n", - irq); + " MASKED MAC ERROR INTERRUPT ASSERTED\n", + irq); } } else printk(KERN_ERR - "%s : %s : LINE %d :\nIRQ ?: MAC ERROR" - " INTERRUPT ASSERTED BUT NO SOURCE FOUND" - "(EMAC_SYSTAT=0x%X)\n", - __func__, __FILE__, __LINE__, status); + "%s : %s : LINE %d :\nIRQ ?: MAC ERROR" + " INTERRUPT ASSERTED BUT NO SOURCE FOUND" + "(EMAC_SYSTAT=0x%X)\n", + __func__, __FILE__, __LINE__, status); } #endif @@ -583,7 +816,7 @@ static void bfin_demux_gpio_block(unsigned int irq) } void bfin_demux_gpio_irq(unsigned int inta_irq, - struct irq_desc *desc) + struct irq_desc *desc) { unsigned int irq; @@ -635,9 +868,15 @@ void bfin_demux_gpio_irq(unsigned int inta_irq, #else +# ifndef CONFIG_BF60x #define NR_PINT_SYS_IRQS 4 -#define NR_PINT_BITS 32 #define NR_PINTS 160 +# else +#define NR_PINT_SYS_IRQS 6 +#define NR_PINTS 112 +#endif + +#define NR_PINT_BITS 32 #define IRQ_NOT_AVAIL 0xFF #define PINT_2_BANK(x) ((x) >> 5) @@ -652,8 +891,13 @@ static struct bfin_pint_regs * const pint[NR_PINT_SYS_IRQS] = { (struct bfin_pint_regs *)PINT1_MASK_SET, (struct bfin_pint_regs *)PINT2_MASK_SET, (struct bfin_pint_regs *)PINT3_MASK_SET, +#ifdef CONFIG_BF60x + (struct bfin_pint_regs *)PINT4_MASK_SET, + (struct bfin_pint_regs *)PINT5_MASK_SET, +#endif }; +#ifndef CONFIG_BF60x inline unsigned int get_irq_base(u32 bank, u8 bmap) { unsigned int irq_base; @@ -666,6 +910,16 @@ inline unsigned int get_irq_base(u32 bank, u8 bmap) return irq_base; } +#else +inline unsigned int get_irq_base(u32 bank, u8 bmap) +{ + unsigned int irq_base; + + irq_base = IRQ_PA0 + bank * 16 + bmap * 16; + + return irq_base; +} +#endif /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */ void init_pint_lut(void) @@ -854,6 +1108,14 @@ static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state) case 1: pint_irq = IRQ_PINT1; break; +#ifdef CONFIG_BF60x + case 4: + pint_irq = IRQ_PINT4; + break; + case 5: + pint_irq = IRQ_PINT5; + break; +#endif default: return -EINVAL; } @@ -867,10 +1129,21 @@ static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state) #endif void bfin_demux_gpio_irq(unsigned int inta_irq, - struct irq_desc *desc) + struct irq_desc *desc) { u32 bank, pint_val; u32 request, irq; + u32 level_mask; + int umask = 0; + struct irq_chip *chip = irq_desc_get_chip(desc); + + if (chip->irq_mask_ack) { + chip->irq_mask_ack(&desc->irq_data); + } else { + chip->irq_mask(&desc->irq_data); + if (chip->irq_ack) + chip->irq_ack(&desc->irq_data); + } switch (inta_irq) { case IRQ_PINT0: @@ -885,6 +1158,14 @@ void bfin_demux_gpio_irq(unsigned int inta_irq, case IRQ_PINT1: bank = 1; break; +#ifdef CONFIG_BF60x + case IRQ_PINT4: + bank = 4; + break; + case IRQ_PINT5: + bank = 5; + break; +#endif default: return; } @@ -893,15 +1174,23 @@ void bfin_demux_gpio_irq(unsigned int inta_irq, request = pint[bank]->request; + level_mask = pint[bank]->edge_set & request; + while (request) { if (request & 1) { irq = pint2irq_lut[pint_val] + SYS_IRQS; + if (level_mask & PINT_BIT(pint_val)) { + umask = 1; + chip->irq_unmask(&desc->irq_data); + } bfin_handle_irq(irq); } pint_val++; request >>= 1; } + if (!umask) + chip->irq_unmask(&desc->irq_data); } #endif @@ -951,6 +1240,7 @@ int __init init_arch_irq(void) int irq; unsigned long ilat = 0; +#ifndef CONFIG_BF60x /* Disable all the peripheral intrs - page 4-29 HW Ref manual */ #ifdef SIC_IMASK0 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL); @@ -958,13 +1248,16 @@ int __init init_arch_irq(void) # ifdef SIC_IMASK2 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL); # endif -# ifdef CONFIG_SMP +# if defined(CONFIG_SMP) || defined(CONFIG_ICC) bfin_write_SICB_IMASK0(SIC_UNMASK_ALL); bfin_write_SICB_IMASK1(SIC_UNMASK_ALL); # endif #else bfin_write_SIC_IMASK(SIC_UNMASK_ALL); #endif +#else /* CONFIG_BF60x */ + bfin_write_SEC_GCTL(SEC_GCTL_RESET); +#endif local_irq_disable(); @@ -974,6 +1267,10 @@ int __init init_arch_irq(void) pint[1]->assign = CONFIG_PINT1_ASSIGN; pint[2]->assign = CONFIG_PINT2_ASSIGN; pint[3]->assign = CONFIG_PINT3_ASSIGN; +# ifdef CONFIG_BF60x + pint[4]->assign = CONFIG_PINT4_ASSIGN; + pint[5]->assign = CONFIG_PINT5_ASSIGN; +# endif # endif /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */ init_pint_lut(); @@ -986,6 +1283,7 @@ int __init init_arch_irq(void) irq_set_chip(irq, &bfin_internal_irqchip); switch (irq) { +#ifndef CONFIG_BF60x #if BFIN_GPIO_PINT case IRQ_PINT0: case IRQ_PINT1: @@ -1015,12 +1313,13 @@ int __init init_arch_irq(void) bfin_demux_mac_status_irq); break; #endif -#ifdef CONFIG_SMP +#if defined(CONFIG_SMP) || defined(CONFIG_ICC) case IRQ_SUPPLE_0: case IRQ_SUPPLE_1: irq_set_handler(irq, handle_percpu_irq); break; #endif +#endif #ifdef CONFIG_TICKSOURCE_CORETMR case IRQ_CORETMR: @@ -1050,7 +1349,8 @@ int __init init_arch_irq(void) init_mach_irq(); -#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) +#ifndef CONFIG_BF60x +#if (defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)) && !defined(CONFIG_BF60x) for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++) irq_set_chip_and_handler(irq, &bfin_mac_status_irqchip, handle_level_irq); @@ -1060,7 +1360,28 @@ int __init init_arch_irq(void) irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++) irq_set_chip_and_handler(irq, &bfin_gpio_irqchip, handle_level_irq); - +#else + for (irq = BFIN_IRQ(0); irq <= SYS_IRQS; irq++) { + if (irq < CORE_IRQS) { + irq_set_chip(irq, &bfin_sec_irqchip); + __irq_set_handler(irq, handle_sec_fault, 0, NULL); + } else if (irq >= BFIN_IRQ(21) && irq <= BFIN_IRQ(26)) { + irq_set_chip(irq, &bfin_sec_irqchip); + irq_set_chained_handler(irq, bfin_demux_gpio_irq); + } else if (irq >= BFIN_IRQ(34) && irq <= BFIN_IRQ(37)) { + irq_set_chip(irq, &bfin_sec_irqchip); + irq_set_handler(irq, handle_percpu_irq); + } else { + irq_set_chip_and_handler(irq, &bfin_sec_irqchip, + handle_fasteoi_irq); + __irq_set_preflow_handler(irq, bfin_sec_preflow_handler); + } + } + for (irq = GPIO_IRQ_BASE; + irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++) + irq_set_chip_and_handler(irq, &bfin_gpio_irqchip, + handle_level_irq); +#endif bfin_write_IMASK(0); CSYNC(); ilat = bfin_read_ILAT(); @@ -1072,14 +1393,17 @@ int __init init_arch_irq(void) /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx, * local_irq_enable() */ +#ifndef CONFIG_BF60x program_IAR(); /* Therefore it's better to setup IARs before interrupts enabled */ search_IAR(); /* Enable interrupts IVG7-15 */ bfin_irq_flags |= IMASK_IVG15 | - IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 | - IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW; + IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 | + IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW; + + bfin_sti(bfin_irq_flags); /* This implicitly covers ANOMALY_05000171 * Boot-ROM code modifies SICA_IWRx wakeup registers @@ -1103,7 +1427,23 @@ int __init init_arch_irq(void) #else bfin_write_SIC_IWR(IWR_DISABLE_ALL); #endif +#else /* CONFIG_BF60x */ + /* Enable interrupts IVG7-15 */ + bfin_irq_flags |= IMASK_IVG15 | + IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 | + IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW; + + bfin_write_SEC_FCTL(SEC_FCTL_EN | SEC_FCTL_SYSRST_EN | SEC_FCTL_FLTIN_EN); + bfin_sec_enable_sci(SIC_SYSIRQ(IRQ_WATCH0)); + bfin_sec_enable_ssi(SIC_SYSIRQ(IRQ_WATCH0)); + bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET); + udelay(100); + bfin_write_SEC_GCTL(SEC_GCTL_EN); + bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN); + init_software_driven_irq(); + register_syscore_ops(&sec_pm_syscore_ops); +#endif return 0; } @@ -1112,13 +1452,14 @@ __attribute__((l1_text)) #endif static int vec_to_irq(int vec) { +#ifndef CONFIG_BF60x struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst; struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop; unsigned long sic_status[3]; - +#endif if (likely(vec == EVT_IVTMR_P)) return IRQ_CORETMR; - +#ifndef CONFIG_BF60x #ifdef SIC_ISR sic_status[0] = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR(); #else @@ -1147,6 +1488,10 @@ static int vec_to_irq(int vec) #endif return ivg->irqno; } +#else + /* for bf60x read */ + return BFIN_IRQ(bfin_read_SEC_SCI(0, SEC_CSID)); +#endif /* end of CONFIG_BF60x */ } #ifdef CONFIG_DO_IRQ_L1 diff --git a/arch/blackfin/mach-common/pm.c b/arch/blackfin/mach-common/pm.c index 3c648a077e75..ca6655e0d653 100644 --- a/arch/blackfin/mach-common/pm.c +++ b/arch/blackfin/mach-common/pm.c @@ -19,20 +19,33 @@ #include <asm/gpio.h> #include <asm/dma.h> #include <asm/dpmc.h> +#include <asm/pm.h> +#ifdef CONFIG_BF60x +struct bfin_cpu_pm_fns *bfin_cpu_pm; +#endif void bfin_pm_suspend_standby_enter(void) { +#ifndef CONFIG_BF60x bfin_pm_standby_setup(); +#endif -#ifdef CONFIG_PM_BFIN_SLEEP_DEEPER - sleep_deeper(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]); +#ifdef CONFIG_BF60x + bfin_cpu_pm->enter(PM_SUSPEND_STANDBY); #else +# ifdef CONFIG_PM_BFIN_SLEEP_DEEPER + sleep_deeper(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]); +# else sleep_mode(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]); +# endif #endif +#ifndef CONFIG_BF60x bfin_pm_standby_restore(); +#endif +#ifndef CONFIG_BF60x #ifdef SIC_IWR0 bfin_write_SIC_IWR0(IWR_DISABLE_ALL); # ifdef SIC_IWR1 @@ -52,6 +65,8 @@ void bfin_pm_suspend_standby_enter(void) #else bfin_write_SIC_IWR(IWR_DISABLE_ALL); #endif + +#endif } int bf53x_suspend_l1_mem(unsigned char *memptr) @@ -83,10 +98,13 @@ int bf53x_resume_l1_mem(unsigned char *memptr) } #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK) +# ifdef CONFIG_BF60x +__attribute__((l1_text)) +# endif static void flushinv_all_dcache(void) { - u32 way, bank, subbank, set; - u32 status, addr; + register u32 way, bank, subbank, set; + register u32 status, addr; u32 dmem_ctl = bfin_read_DMEM_CONTROL(); for (bank = 0; bank < 2; ++bank) { @@ -133,6 +151,7 @@ int bfin_pm_suspend_mem_enter(void) return -ENOMEM; } +#ifndef CONFIG_BF60x wakeup = bfin_read_VR_CTL() & ~FREQ; wakeup |= SCKELOW; @@ -142,6 +161,7 @@ int bfin_pm_suspend_mem_enter(void) #ifdef CONFIG_PM_BFIN_WAKE_GP wakeup |= GPWE; #endif +#endif ret = blackfin_dma_suspend(); @@ -159,7 +179,11 @@ int bfin_pm_suspend_mem_enter(void) _disable_icplb(); bf53x_suspend_l1_mem(memptr); +#ifndef CONFIG_BF60x do_hibernate(wakeup | vr_wakeup); /* See you later! */ +#else + bfin_cpu_pm->enter(PM_SUSPEND_MEM); +#endif bf53x_resume_l1_mem(memptr); @@ -223,9 +247,39 @@ static int bfin_pm_enter(suspend_state_t state) return 0; } +#ifdef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH +void bfin_pm_end(void) +{ + u32 cycle, cycle2; + u64 usec64; + u32 usec; + + __asm__ __volatile__ ( + "1: %0 = CYCLES2\n" + "%1 = CYCLES\n" + "%2 = CYCLES2\n" + "CC = %2 == %0\n" + "if ! CC jump 1b\n" + : "=d,a" (cycle2), "=d,a" (cycle), "=d,a" (usec) : : "CC" + ); + + usec64 = ((u64)cycle2 << 32) + cycle; + do_div(usec64, get_cclk() / USEC_PER_SEC); + usec = usec64; + if (usec == 0) + usec = 1; + + pr_info("PM: resume of kernel completes after %ld msec %03ld usec\n", + usec / USEC_PER_MSEC, usec % USEC_PER_MSEC); +} +#endif + static const struct platform_suspend_ops bfin_pm_ops = { .enter = bfin_pm_enter, .valid = bfin_pm_valid, +#ifdef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH + .end = bfin_pm_end, +#endif }; static int __init bfin_pm_init(void) diff --git a/arch/blackfin/mm/init.c b/arch/blackfin/mm/init.c index 78daae084915..9cb85537bd2b 100644 --- a/arch/blackfin/mm/init.c +++ b/arch/blackfin/mm/init.c @@ -48,7 +48,7 @@ void __init paging_init(void) unsigned long zones_size[MAX_NR_ZONES] = { [0] = 0, - [ZONE_DMA] = (end_mem - PAGE_OFFSET) >> PAGE_SHIFT, + [ZONE_DMA] = (end_mem - CONFIG_PHY_RAM_BASE_ADDRESS) >> PAGE_SHIFT, [ZONE_NORMAL] = 0, #ifdef CONFIG_HIGHMEM [ZONE_HIGHMEM] = 0, @@ -60,7 +60,8 @@ void __init paging_init(void) pr_debug("free_area_init -> start_mem is %#lx virtual_end is %#lx\n", PAGE_ALIGN(memory_start), end_mem); - free_area_init(zones_size); + free_area_init_node(0, zones_size, + CONFIG_PHY_RAM_BASE_ADDRESS >> PAGE_SHIFT, NULL); } asmlinkage void __init init_pda(void) @@ -75,9 +76,6 @@ asmlinkage void __init init_pda(void) valid pointers to it. */ memset(&cpu_pda[cpu], 0, sizeof(cpu_pda[cpu])); - cpu_pda[0].next = &cpu_pda[1]; - cpu_pda[1].next = &cpu_pda[0]; - #ifdef CONFIG_EXCEPTION_L1_SCRATCH cpu_pda[cpu].ex_stack = (unsigned long *)(L1_SCRATCH_START + \ L1_SCRATCH_LENGTH); @@ -109,10 +107,10 @@ void __init mem_init(void) totalram_pages = free_all_bootmem(); reservedpages = 0; - for (tmp = 0; tmp < max_mapnr; tmp++) + for (tmp = ARCH_PFN_OFFSET; tmp < max_mapnr; tmp++) if (PageReserved(pfn_to_page(tmp))) reservedpages++; - freepages = max_mapnr - reservedpages; + freepages = max_mapnr - ARCH_PFN_OFFSET - reservedpages; /* do not count in kernel image between _rambase and _ramstart */ reservedpages -= (_ramstart - _rambase) >> PAGE_SHIFT; @@ -127,7 +125,7 @@ void __init mem_init(void) printk(KERN_INFO "Memory available: %luk/%luk RAM, " "(%uk init code, %uk kernel code, %uk data, %uk dma, %uk reserved)\n", - (unsigned long) freepages << (PAGE_SHIFT-10), _ramend >> 10, + (unsigned long) freepages << (PAGE_SHIFT-10), (_ramend - CONFIG_PHY_RAM_BASE_ADDRESS) >> 10, initk, codek, datak, DMA_UNCACHED_REGION >> 10, (reservedpages << (PAGE_SHIFT-10))); } diff --git a/arch/blackfin/mm/sram-alloc.c b/arch/blackfin/mm/sram-alloc.c index 29d98faa1efd..342e378da1ec 100644 --- a/arch/blackfin/mm/sram-alloc.c +++ b/arch/blackfin/mm/sram-alloc.c @@ -186,9 +186,45 @@ static void __init l1_inst_sram_init(void) #endif } +#ifdef __ADSPBF60x__ +static irqreturn_t l2_ecc_err(int irq, void *dev_id) +{ + int status; + + printk(KERN_ERR "L2 ecc error happend\n"); + status = bfin_read32(L2CTL0_STAT); + if (status & 0x1) + printk(KERN_ERR "Core channel error type:0x%x, addr:0x%x\n", + bfin_read32(L2CTL0_ET0), bfin_read32(L2CTL0_EADDR0)); + if (status & 0x2) + printk(KERN_ERR "System channel error type:0x%x, addr:0x%x\n", + bfin_read32(L2CTL0_ET1), bfin_read32(L2CTL0_EADDR1)); + + status = status >> 8; + if (status) + printk(KERN_ERR "L2 Bank%d error, addr:0x%x\n", + status, bfin_read32(L2CTL0_ERRADDR0 + status)); + + panic("L2 Ecc error"); + return IRQ_HANDLED; +} +#endif + static void __init l2_sram_init(void) { #if L2_LENGTH != 0 + +#ifdef __ADSPBF60x__ + int ret; + + ret = request_irq(IRQ_L2CTL0_ECC_ERR, l2_ecc_err, 0, "l2-ecc-err", + NULL); + if (unlikely(ret < 0)) { + printk(KERN_INFO "Fail to request l2 ecc error interrupt"); + return; + } +#endif + free_l2_sram_head.next = kmem_cache_alloc(sram_piece_cache, GFP_KERNEL); if (!free_l2_sram_head.next) { diff --git a/arch/c6x/Kconfig b/arch/c6x/Kconfig index 1c3ccd416d50..1f15b88b537f 100644 --- a/arch/c6x/Kconfig +++ b/arch/c6x/Kconfig @@ -3,7 +3,7 @@ # see Documentation/kbuild/kconfig-language.txt. # -config TMS320C6X +config C6X def_bool y select CLKDEV_LOOKUP select GENERIC_IRQ_SHOW @@ -19,24 +19,12 @@ config TMS320C6X config MMU def_bool n -config ZONE_DMA - def_bool y - config FPU def_bool n -config HIGHMEM - def_bool n - -config NUMA - def_bool n - config RWSEM_GENERIC_SPINLOCK def_bool y -config RWSEM_XCHGADD_ALGORITHM - def_bool n - config GENERIC_CALIBRATE_DELAY def_bool y diff --git a/arch/c6x/include/asm/elf.h b/arch/c6x/include/asm/elf.h index d57865ba2c44..f4552db20b4a 100644 --- a/arch/c6x/include/asm/elf.h +++ b/arch/c6x/include/asm/elf.h @@ -30,7 +30,19 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; */ #define elf_check_arch(x) ((x)->e_machine == EM_TI_C6000) -#define elf_check_const_displacement(x) (1) +#define elf_check_fdpic(x) (1) +#define elf_check_const_displacement(x) (0) + +#define ELF_FDPIC_PLAT_INIT(_regs, _exec_map, _interp_map, _dynamic_addr) \ +do { \ + _regs->b4 = (_exec_map); \ + _regs->a6 = (_interp_map); \ + _regs->b6 = (_dynamic_addr); \ +} while (0) + +#define ELF_FDPIC_CORE_EFLAGS 0 + +#define ELF_CORE_COPY_FPREGS(...) 0 /* No FPU regs to copy */ /* * These are used to set parameters in the core dumps. diff --git a/arch/c6x/include/asm/irq.h b/arch/c6x/include/asm/irq.h index f13b78d5e1ca..ab4577f93d96 100644 --- a/arch/c6x/include/asm/irq.h +++ b/arch/c6x/include/asm/irq.h @@ -42,10 +42,6 @@ /* This number is used when no interrupt has been assigned */ #define NO_IRQ 0 -struct irq_data; -extern irq_hw_number_t irqd_to_hwirq(struct irq_data *d); -extern irq_hw_number_t virq_to_hw(unsigned int virq); - extern void __init init_pic_c64xplus(void); extern void init_IRQ(void); diff --git a/arch/c6x/include/asm/mmu.h b/arch/c6x/include/asm/mmu.h index 41592bf16067..4467e770a1ce 100644 --- a/arch/c6x/include/asm/mmu.h +++ b/arch/c6x/include/asm/mmu.h @@ -13,6 +13,10 @@ typedef struct { unsigned long end_brk; +#ifdef CONFIG_BINFMT_ELF_FDPIC + unsigned long exec_fdpic_loadmap; + unsigned long interp_fdpic_loadmap; +#endif } mm_context_t; #endif /* _ASM_C6X_MMU_H */ diff --git a/arch/c6x/include/asm/ptrace.h b/arch/c6x/include/asm/ptrace.h index 21e8d7931fe7..b04ff5964258 100644 --- a/arch/c6x/include/asm/ptrace.h +++ b/arch/c6x/include/asm/ptrace.h @@ -97,6 +97,11 @@ #define PT_DP PT_B14 /* Data Segment Pointer (B14) */ #define PT_SP PT_B15 /* Stack Pointer (B15) */ +#define PTRACE_GETFDPIC 31 /* get the ELF fdpic loadmap address */ + +#define PTRACE_GETFDPIC_EXEC 0 /* [addr] request the executable loadmap */ +#define PTRACE_GETFDPIC_INTERP 1 /* [addr] request the interpreter loadmap */ + #ifndef __ASSEMBLY__ #ifdef _BIG_ENDIAN diff --git a/arch/c6x/kernel/irq.c b/arch/c6x/kernel/irq.c index 65b8ddf54b44..c90fb5e82ad7 100644 --- a/arch/c6x/kernel/irq.c +++ b/arch/c6x/kernel/irq.c @@ -130,16 +130,3 @@ int arch_show_interrupts(struct seq_file *p, int prec) seq_printf(p, "%*s: %10lu\n", prec, "Err", irq_err_count); return 0; } - -irq_hw_number_t irqd_to_hwirq(struct irq_data *d) -{ - return d->hwirq; -} -EXPORT_SYMBOL_GPL(irqd_to_hwirq); - -irq_hw_number_t virq_to_hw(unsigned int virq) -{ - struct irq_data *irq_data = irq_get_irq_data(virq); - return WARN_ON(!irq_data) ? 0 : irq_data->hwirq; -} -EXPORT_SYMBOL_GPL(virq_to_hw); diff --git a/arch/frv/include/asm/processor.h b/arch/frv/include/asm/processor.h index 81c2e271d620..9b1a92b73f60 100644 --- a/arch/frv/include/asm/processor.h +++ b/arch/frv/include/asm/processor.h @@ -135,10 +135,6 @@ unsigned long get_wchan(struct task_struct *p); #define KSTK_EIP(tsk) ((tsk)->thread.frame0->pc) #define KSTK_ESP(tsk) ((tsk)->thread.frame0->sp) -/* Allocation and freeing of basic task resources. */ -extern struct task_struct *alloc_task_struct_node(int node); -extern void free_task_struct(struct task_struct *p); - #define cpu_relax() barrier() /* data cache prefetch */ diff --git a/arch/hexagon/kernel/dma.c b/arch/hexagon/kernel/dma.c index 37302218ca4a..0f2367cc5493 100644 --- a/arch/hexagon/kernel/dma.c +++ b/arch/hexagon/kernel/dma.c @@ -22,6 +22,7 @@ #include <linux/bootmem.h> #include <linux/genalloc.h> #include <asm/dma-mapping.h> +#include <linux/module.h> struct dma_map_ops *dma_ops; EXPORT_SYMBOL(dma_ops); diff --git a/arch/hexagon/kernel/process.c b/arch/hexagon/kernel/process.c index 18c4f0b0f4ba..ff02821bfb7e 100644 --- a/arch/hexagon/kernel/process.c +++ b/arch/hexagon/kernel/process.c @@ -1,7 +1,7 @@ /* * Process creation support for Hexagon * - * Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved. + * Copyright (c) 2010-2012, Code Aurora Forum. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -88,7 +88,7 @@ void (*idle_sleep)(void) = default_idle; void cpu_idle(void) { while (1) { - tick_nohz_stop_sched_tick(1); + tick_nohz_idle_enter(); local_irq_disable(); while (!need_resched()) { idle_sleep(); @@ -97,7 +97,7 @@ void cpu_idle(void) local_irq_disable(); } local_irq_enable(); - tick_nohz_restart_sched_tick(); + tick_nohz_idle_exit(); schedule(); } } diff --git a/arch/hexagon/kernel/ptrace.c b/arch/hexagon/kernel/ptrace.c index 32342de1a79c..96c3b2c4dbad 100644 --- a/arch/hexagon/kernel/ptrace.c +++ b/arch/hexagon/kernel/ptrace.c @@ -28,6 +28,7 @@ #include <linux/ptrace.h> #include <linux/regset.h> #include <linux/user.h> +#include <linux/elf.h> #include <asm/user.h> diff --git a/arch/hexagon/kernel/smp.c b/arch/hexagon/kernel/smp.c index 9b44a9e2d05a..1298141874a3 100644 --- a/arch/hexagon/kernel/smp.c +++ b/arch/hexagon/kernel/smp.c @@ -1,7 +1,7 @@ /* * SMP support for Hexagon * - * Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved. + * Copyright (c) 2010-2012, Code Aurora Forum. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -28,6 +28,7 @@ #include <linux/sched.h> #include <linux/smp.h> #include <linux/spinlock.h> +#include <linux/cpu.h> #include <asm/time.h> /* timer_interrupt */ #include <asm/hexagon_vm.h> @@ -177,7 +178,12 @@ void __cpuinit start_secondary(void) printk(KERN_INFO "%s cpu %d\n", __func__, current_thread_info()->cpu); + notify_cpu_starting(cpu); + + ipi_call_lock(); set_cpu_online(cpu, true); + ipi_call_unlock(); + local_irq_enable(); cpu_idle(); diff --git a/arch/hexagon/kernel/time.c b/arch/hexagon/kernel/time.c index 6bee15c9c113..5d9b33b67935 100644 --- a/arch/hexagon/kernel/time.c +++ b/arch/hexagon/kernel/time.c @@ -28,6 +28,7 @@ #include <linux/of.h> #include <linux/of_address.h> #include <linux/of_irq.h> +#include <linux/module.h> #include <asm/timer-regs.h> #include <asm/hexagon_vm.h> diff --git a/arch/hexagon/kernel/vdso.c b/arch/hexagon/kernel/vdso.c index f212a453b527..5d39f42f7085 100644 --- a/arch/hexagon/kernel/vdso.c +++ b/arch/hexagon/kernel/vdso.c @@ -21,6 +21,7 @@ #include <linux/err.h> #include <linux/mm.h> #include <linux/vmalloc.h> +#include <linux/binfmts.h> #include <asm/vdso.h> diff --git a/arch/ia64/include/asm/cmpxchg.h b/arch/ia64/include/asm/cmpxchg.h index 4c96187e2049..4f37dbbb8640 100644 --- a/arch/ia64/include/asm/cmpxchg.h +++ b/arch/ia64/include/asm/cmpxchg.h @@ -1 +1,147 @@ -#include <asm/intrinsics.h> +#ifndef _ASM_IA64_CMPXCHG_H +#define _ASM_IA64_CMPXCHG_H + +/* + * Compare/Exchange, forked from asm/intrinsics.h + * which was: + * + * Copyright (C) 2002-2003 Hewlett-Packard Co + * David Mosberger-Tang <[email protected]> + */ + +#ifndef __ASSEMBLY__ + +#include <linux/types.h> +/* include compiler specific intrinsics */ +#include <asm/ia64regs.h> +#ifdef __INTEL_COMPILER +# include <asm/intel_intrin.h> +#else +# include <asm/gcc_intrin.h> +#endif + +/* + * This function doesn't exist, so you'll get a linker error if + * something tries to do an invalid xchg(). + */ +extern void ia64_xchg_called_with_bad_pointer(void); + +#define __xchg(x, ptr, size) \ +({ \ + unsigned long __xchg_result; \ + \ + switch (size) { \ + case 1: \ + __xchg_result = ia64_xchg1((__u8 *)ptr, x); \ + break; \ + \ + case 2: \ + __xchg_result = ia64_xchg2((__u16 *)ptr, x); \ + break; \ + \ + case 4: \ + __xchg_result = ia64_xchg4((__u32 *)ptr, x); \ + break; \ + \ + case 8: \ + __xchg_result = ia64_xchg8((__u64 *)ptr, x); \ + break; \ + default: \ + ia64_xchg_called_with_bad_pointer(); \ + } \ + __xchg_result; \ +}) + +#define xchg(ptr, x) \ +((__typeof__(*(ptr))) __xchg((unsigned long) (x), (ptr), sizeof(*(ptr)))) + +/* + * Atomic compare and exchange. Compare OLD with MEM, if identical, + * store NEW in MEM. Return the initial value in MEM. Success is + * indicated by comparing RETURN with OLD. + */ + +#define __HAVE_ARCH_CMPXCHG 1 + +/* + * This function doesn't exist, so you'll get a linker error + * if something tries to do an invalid cmpxchg(). + */ +extern long ia64_cmpxchg_called_with_bad_pointer(void); + +#define ia64_cmpxchg(sem, ptr, old, new, size) \ +({ \ + __u64 _o_, _r_; \ + \ + switch (size) { \ + case 1: \ + _o_ = (__u8) (long) (old); \ + break; \ + case 2: \ + _o_ = (__u16) (long) (old); \ + break; \ + case 4: \ + _o_ = (__u32) (long) (old); \ + break; \ + case 8: \ + _o_ = (__u64) (long) (old); \ + break; \ + default: \ + break; \ + } \ + switch (size) { \ + case 1: \ + _r_ = ia64_cmpxchg1_##sem((__u8 *) ptr, new, _o_); \ + break; \ + \ + case 2: \ + _r_ = ia64_cmpxchg2_##sem((__u16 *) ptr, new, _o_); \ + break; \ + \ + case 4: \ + _r_ = ia64_cmpxchg4_##sem((__u32 *) ptr, new, _o_); \ + break; \ + \ + case 8: \ + _r_ = ia64_cmpxchg8_##sem((__u64 *) ptr, new, _o_); \ + break; \ + \ + default: \ + _r_ = ia64_cmpxchg_called_with_bad_pointer(); \ + break; \ + } \ + (__typeof__(old)) _r_; \ +}) + +#define cmpxchg_acq(ptr, o, n) \ + ia64_cmpxchg(acq, (ptr), (o), (n), sizeof(*(ptr))) +#define cmpxchg_rel(ptr, o, n) \ + ia64_cmpxchg(rel, (ptr), (o), (n), sizeof(*(ptr))) + +/* for compatibility with other platforms: */ +#define cmpxchg(ptr, o, n) cmpxchg_acq((ptr), (o), (n)) +#define cmpxchg64(ptr, o, n) cmpxchg_acq((ptr), (o), (n)) + +#define cmpxchg_local cmpxchg +#define cmpxchg64_local cmpxchg64 + +#ifdef CONFIG_IA64_DEBUG_CMPXCHG +# define CMPXCHG_BUGCHECK_DECL int _cmpxchg_bugcheck_count = 128; +# define CMPXCHG_BUGCHECK(v) \ +do { \ + if (_cmpxchg_bugcheck_count-- <= 0) { \ + void *ip; \ + extern int printk(const char *fmt, ...); \ + ip = (void *) ia64_getreg(_IA64_REG_IP); \ + printk("CMPXCHG_BUGCHECK: stuck at %p on word %p\n", ip, (v));\ + break; \ + } \ +} while (0) +#else /* !CONFIG_IA64_DEBUG_CMPXCHG */ +# define CMPXCHG_BUGCHECK_DECL +# define CMPXCHG_BUGCHECK(v) +#endif /* !CONFIG_IA64_DEBUG_CMPXCHG */ + +#endif /* !__ASSEMBLY__ */ + +#endif /* _ASM_IA64_CMPXCHG_H */ diff --git a/arch/ia64/include/asm/futex.h b/arch/ia64/include/asm/futex.h index 0ab82cc2dc8f..d2bf1fd5e44f 100644 --- a/arch/ia64/include/asm/futex.h +++ b/arch/ia64/include/asm/futex.h @@ -106,15 +106,16 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, return -EFAULT; { - register unsigned long r8 __asm ("r8") = 0; + register unsigned long r8 __asm ("r8"); unsigned long prev; __asm__ __volatile__( " mf;; \n" - " mov ar.ccv=%3;; \n" - "[1:] cmpxchg4.acq %0=[%1],%2,ar.ccv \n" + " mov %0=r0 \n" + " mov ar.ccv=%4;; \n" + "[1:] cmpxchg4.acq %1=[%2],%3,ar.ccv \n" " .xdata4 \"__ex_table\", 1b-., 2f-. \n" "[2:]" - : "=r" (prev) + : "=r" (r8), "=r" (prev) : "r" (uaddr), "r" (newval), "rO" ((long) (unsigned) oldval) : "memory"); diff --git a/arch/ia64/include/asm/intrinsics.h b/arch/ia64/include/asm/intrinsics.h index e4076b511829..d129e367e764 100644 --- a/arch/ia64/include/asm/intrinsics.h +++ b/arch/ia64/include/asm/intrinsics.h @@ -18,6 +18,7 @@ #else # include <asm/gcc_intrin.h> #endif +#include <asm/cmpxchg.h> #define ia64_native_get_psr_i() (ia64_native_getreg(_IA64_REG_PSR) & IA64_PSR_I) @@ -81,119 +82,6 @@ extern unsigned long __bad_increment_for_ia64_fetch_and_add (void); #define ia64_fetch_and_add(i,v) (ia64_fetchadd(i, v, rel) + (i)) /* return new value */ -/* - * This function doesn't exist, so you'll get a linker error if - * something tries to do an invalid xchg(). - */ -extern void ia64_xchg_called_with_bad_pointer (void); - -#define __xchg(x,ptr,size) \ -({ \ - unsigned long __xchg_result; \ - \ - switch (size) { \ - case 1: \ - __xchg_result = ia64_xchg1((__u8 *)ptr, x); \ - break; \ - \ - case 2: \ - __xchg_result = ia64_xchg2((__u16 *)ptr, x); \ - break; \ - \ - case 4: \ - __xchg_result = ia64_xchg4((__u32 *)ptr, x); \ - break; \ - \ - case 8: \ - __xchg_result = ia64_xchg8((__u64 *)ptr, x); \ - break; \ - default: \ - ia64_xchg_called_with_bad_pointer(); \ - } \ - __xchg_result; \ -}) - -#define xchg(ptr,x) \ - ((__typeof__(*(ptr))) __xchg ((unsigned long) (x), (ptr), sizeof(*(ptr)))) - -/* - * Atomic compare and exchange. Compare OLD with MEM, if identical, - * store NEW in MEM. Return the initial value in MEM. Success is - * indicated by comparing RETURN with OLD. - */ - -#define __HAVE_ARCH_CMPXCHG 1 - -/* - * This function doesn't exist, so you'll get a linker error - * if something tries to do an invalid cmpxchg(). - */ -extern long ia64_cmpxchg_called_with_bad_pointer (void); - -#define ia64_cmpxchg(sem,ptr,old,new,size) \ -({ \ - __u64 _o_, _r_; \ - \ - switch (size) { \ - case 1: _o_ = (__u8 ) (long) (old); break; \ - case 2: _o_ = (__u16) (long) (old); break; \ - case 4: _o_ = (__u32) (long) (old); break; \ - case 8: _o_ = (__u64) (long) (old); break; \ - default: break; \ - } \ - switch (size) { \ - case 1: \ - _r_ = ia64_cmpxchg1_##sem((__u8 *) ptr, new, _o_); \ - break; \ - \ - case 2: \ - _r_ = ia64_cmpxchg2_##sem((__u16 *) ptr, new, _o_); \ - break; \ - \ - case 4: \ - _r_ = ia64_cmpxchg4_##sem((__u32 *) ptr, new, _o_); \ - break; \ - \ - case 8: \ - _r_ = ia64_cmpxchg8_##sem((__u64 *) ptr, new, _o_); \ - break; \ - \ - default: \ - _r_ = ia64_cmpxchg_called_with_bad_pointer(); \ - break; \ - } \ - (__typeof__(old)) _r_; \ -}) - -#define cmpxchg_acq(ptr, o, n) \ - ia64_cmpxchg(acq, (ptr), (o), (n), sizeof(*(ptr))) -#define cmpxchg_rel(ptr, o, n) \ - ia64_cmpxchg(rel, (ptr), (o), (n), sizeof(*(ptr))) - -/* for compatibility with other platforms: */ -#define cmpxchg(ptr, o, n) cmpxchg_acq((ptr), (o), (n)) -#define cmpxchg64(ptr, o, n) cmpxchg_acq((ptr), (o), (n)) - -#define cmpxchg_local cmpxchg -#define cmpxchg64_local cmpxchg64 - -#ifdef CONFIG_IA64_DEBUG_CMPXCHG -# define CMPXCHG_BUGCHECK_DECL int _cmpxchg_bugcheck_count = 128; -# define CMPXCHG_BUGCHECK(v) \ - do { \ - if (_cmpxchg_bugcheck_count-- <= 0) { \ - void *ip; \ - extern int printk(const char *fmt, ...); \ - ip = (void *) ia64_getreg(_IA64_REG_IP); \ - printk("CMPXCHG_BUGCHECK: stuck at %p on word %p\n", ip, (v)); \ - break; \ - } \ - } while (0) -#else /* !CONFIG_IA64_DEBUG_CMPXCHG */ -# define CMPXCHG_BUGCHECK_DECL -# define CMPXCHG_BUGCHECK(v) -#endif /* !CONFIG_IA64_DEBUG_CMPXCHG */ - #endif #ifdef __KERNEL__ diff --git a/arch/ia64/kernel/perfmon.c b/arch/ia64/kernel/perfmon.c index 9d0fd7d5bb82..f00ba025375d 100644 --- a/arch/ia64/kernel/perfmon.c +++ b/arch/ia64/kernel/perfmon.c @@ -604,12 +604,6 @@ pfm_unprotect_ctx_ctxsw(pfm_context_t *x, unsigned long f) spin_unlock(&(x)->ctx_lock); } -static inline unsigned int -pfm_do_munmap(struct mm_struct *mm, unsigned long addr, size_t len, int acct) -{ - return do_munmap(mm, addr, len); -} - static inline unsigned long pfm_get_unmapped_area(struct file *file, unsigned long addr, unsigned long len, unsigned long pgoff, unsigned long flags, unsigned long exec) { @@ -1458,8 +1452,9 @@ pfm_unreserve_session(pfm_context_t *ctx, int is_syswide, unsigned int cpu) * a PROTECT_CTX() section. */ static int -pfm_remove_smpl_mapping(struct task_struct *task, void *vaddr, unsigned long size) +pfm_remove_smpl_mapping(void *vaddr, unsigned long size) { + struct task_struct *task = current; int r; /* sanity checks */ @@ -1473,13 +1468,8 @@ pfm_remove_smpl_mapping(struct task_struct *task, void *vaddr, unsigned long siz /* * does the actual unmapping */ - down_write(&task->mm->mmap_sem); + r = vm_munmap((unsigned long)vaddr, size); - DPRINT(("down_write done smpl_vaddr=%p size=%lu\n", vaddr, size)); - - r = pfm_do_munmap(task->mm, (unsigned long)vaddr, size, 0); - - up_write(&task->mm->mmap_sem); if (r !=0) { printk(KERN_ERR "perfmon: [%d] unable to unmap sampling buffer @%p size=%lu\n", task_pid_nr(task), vaddr, size); } @@ -1945,7 +1935,7 @@ pfm_flush(struct file *filp, fl_owner_t id) * because some VM function reenables interrupts. * */ - if (smpl_buf_vaddr) pfm_remove_smpl_mapping(current, smpl_buf_vaddr, smpl_buf_size); + if (smpl_buf_vaddr) pfm_remove_smpl_mapping(smpl_buf_vaddr, smpl_buf_size); return 0; } diff --git a/arch/ia64/kvm/kvm-ia64.c b/arch/ia64/kvm/kvm-ia64.c index f5104b7c52cd..463fb3bbe11e 100644 --- a/arch/ia64/kvm/kvm-ia64.c +++ b/arch/ia64/kvm/kvm-ia64.c @@ -1174,7 +1174,7 @@ out: bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu) { - return irqchip_in_kernel(vcpu->kcm) == (vcpu->arch.apic != NULL); + return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL); } int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) diff --git a/arch/m68k/Makefile b/arch/m68k/Makefile index cf318f20c64d..b7f2e2d5cd2e 100644 --- a/arch/m68k/Makefile +++ b/arch/m68k/Makefile @@ -16,6 +16,13 @@ KBUILD_DEFCONFIG := multi_defconfig +ifneq ($(SUBARCH),$(ARCH)) + ifeq ($(CROSS_COMPILE),) + CROSS_COMPILE := $(call cc-cross-prefix, \ + m68k-linux-gnu- m68k-linux- m68k-unknown-linux-gnu-) + endif +endif + # # Enable processor type. Ordering of these is important - we want to # use the minimum processor type of the range we support. The logic @@ -62,12 +69,6 @@ endif LDFLAGS := -m m68kelf KBUILD_LDFLAGS_MODULE += -T $(srctree)/arch/m68k/kernel/module.lds -ifneq ($(SUBARCH),$(ARCH)) - ifeq ($(CROSS_COMPILE),) - CROSS_COMPILE := $(call cc-cross-prefix, \ - m68k-linux-gnu- m68k-linux- m68k-unknown-linux-gnu-) - endif -endif ifdef CONFIG_SUN3 LDFLAGS_vmlinux = -N @@ -115,18 +116,6 @@ core-$(CONFIG_M68000) += arch/m68k/platform/68328/ core-$(CONFIG_M68EZ328) += arch/m68k/platform/68EZ328/ core-$(CONFIG_M68VZ328) += arch/m68k/platform/68VZ328/ core-$(CONFIG_COLDFIRE) += arch/m68k/platform/coldfire/ -core-$(CONFIG_M5206) += arch/m68k/platform/5206/ -core-$(CONFIG_M5206e) += arch/m68k/platform/5206/ -core-$(CONFIG_M520x) += arch/m68k/platform/520x/ -core-$(CONFIG_M523x) += arch/m68k/platform/523x/ -core-$(CONFIG_M5249) += arch/m68k/platform/5249/ -core-$(CONFIG_M527x) += arch/m68k/platform/527x/ -core-$(CONFIG_M5272) += arch/m68k/platform/5272/ -core-$(CONFIG_M528x) += arch/m68k/platform/528x/ -core-$(CONFIG_M5307) += arch/m68k/platform/5307/ -core-$(CONFIG_M532x) += arch/m68k/platform/532x/ -core-$(CONFIG_M5407) += arch/m68k/platform/5407/ -core-$(CONFIG_M54xx) += arch/m68k/platform/54xx/ all: zImage diff --git a/arch/m68k/amiga/platform.c b/arch/m68k/amiga/platform.c index 7fd8b41723ea..80076d368b7e 100644 --- a/arch/m68k/amiga/platform.c +++ b/arch/m68k/amiga/platform.c @@ -6,6 +6,7 @@ * for more details. */ +#include <linux/err.h> #include <linux/init.h> #include <linux/platform_device.h> #include <linux/zorro.h> @@ -46,18 +47,25 @@ static const struct resource zorro_resources[] __initconst = { static int __init amiga_init_bus(void) { + struct platform_device *pdev; + unsigned int n; + if (!MACH_IS_AMIGA || !AMIGAHW_PRESENT(ZORRO)) return -ENODEV; - platform_device_register_simple("amiga-zorro", -1, zorro_resources, - AMIGAHW_PRESENT(ZORRO3) ? 4 : 2); + n = AMIGAHW_PRESENT(ZORRO3) ? 4 : 2; + pdev = platform_device_register_simple("amiga-zorro", -1, + zorro_resources, n); + if (IS_ERR(pdev)) + return PTR_ERR(pdev); + return 0; } subsys_initcall(amiga_init_bus); -static int z_dev_present(zorro_id id) +static int __init z_dev_present(zorro_id id) { unsigned int i; @@ -126,72 +134,122 @@ static const struct resource amiga_rtc_resource __initconst = { static int __init amiga_init_devices(void) { struct platform_device *pdev; + int error; if (!MACH_IS_AMIGA) return -ENODEV; /* video hardware */ - if (AMIGAHW_PRESENT(AMI_VIDEO)) - platform_device_register_simple("amiga-video", -1, NULL, 0); + if (AMIGAHW_PRESENT(AMI_VIDEO)) { + pdev = platform_device_register_simple("amiga-video", -1, NULL, + 0); + if (IS_ERR(pdev)) + return PTR_ERR(pdev); + } /* sound hardware */ - if (AMIGAHW_PRESENT(AMI_AUDIO)) - platform_device_register_simple("amiga-audio", -1, NULL, 0); + if (AMIGAHW_PRESENT(AMI_AUDIO)) { + pdev = platform_device_register_simple("amiga-audio", -1, NULL, + 0); + if (IS_ERR(pdev)) + return PTR_ERR(pdev); + } /* storage interfaces */ - if (AMIGAHW_PRESENT(AMI_FLOPPY)) - platform_device_register_simple("amiga-floppy", -1, NULL, 0); + if (AMIGAHW_PRESENT(AMI_FLOPPY)) { + pdev = platform_device_register_simple("amiga-floppy", -1, + NULL, 0); + if (IS_ERR(pdev)) + return PTR_ERR(pdev); + } - if (AMIGAHW_PRESENT(A3000_SCSI)) - platform_device_register_simple("amiga-a3000-scsi", -1, - &a3000_scsi_resource, 1); + if (AMIGAHW_PRESENT(A3000_SCSI)) { + pdev = platform_device_register_simple("amiga-a3000-scsi", -1, + &a3000_scsi_resource, 1); + if (IS_ERR(pdev)) + return PTR_ERR(pdev); + } - if (AMIGAHW_PRESENT(A4000_SCSI)) - platform_device_register_simple("amiga-a4000t-scsi", -1, - &a4000t_scsi_resource, 1); + if (AMIGAHW_PRESENT(A4000_SCSI)) { + pdev = platform_device_register_simple("amiga-a4000t-scsi", -1, + &a4000t_scsi_resource, + 1); + if (IS_ERR(pdev)) + return PTR_ERR(pdev); + } if (AMIGAHW_PRESENT(A1200_IDE) || z_dev_present(ZORRO_PROD_MTEC_VIPER_MK_V_E_MATRIX_530_SCSI_IDE)) { pdev = platform_device_register_simple("amiga-gayle-ide", -1, &a1200_ide_resource, 1); - platform_device_add_data(pdev, &a1200_ide_pdata, - sizeof(a1200_ide_pdata)); + if (IS_ERR(pdev)) + return PTR_ERR(pdev); + error = platform_device_add_data(pdev, &a1200_ide_pdata, + sizeof(a1200_ide_pdata)); + if (error) + return error; } if (AMIGAHW_PRESENT(A4000_IDE)) { pdev = platform_device_register_simple("amiga-gayle-ide", -1, &a4000_ide_resource, 1); - platform_device_add_data(pdev, &a4000_ide_pdata, - sizeof(a4000_ide_pdata)); + if (IS_ERR(pdev)) + return PTR_ERR(pdev); + error = platform_device_add_data(pdev, &a4000_ide_pdata, + sizeof(a4000_ide_pdata)); + if (error) + return error; } /* other I/O hardware */ - if (AMIGAHW_PRESENT(AMI_KEYBOARD)) - platform_device_register_simple("amiga-keyboard", -1, NULL, 0); + if (AMIGAHW_PRESENT(AMI_KEYBOARD)) { + pdev = platform_device_register_simple("amiga-keyboard", -1, + NULL, 0); + if (IS_ERR(pdev)) + return PTR_ERR(pdev); + } - if (AMIGAHW_PRESENT(AMI_MOUSE)) - platform_device_register_simple("amiga-mouse", -1, NULL, 0); + if (AMIGAHW_PRESENT(AMI_MOUSE)) { + pdev = platform_device_register_simple("amiga-mouse", -1, NULL, + 0); + if (IS_ERR(pdev)) + return PTR_ERR(pdev); + } - if (AMIGAHW_PRESENT(AMI_SERIAL)) - platform_device_register_simple("amiga-serial", -1, NULL, 0); + if (AMIGAHW_PRESENT(AMI_SERIAL)) { + pdev = platform_device_register_simple("amiga-serial", -1, + NULL, 0); + if (IS_ERR(pdev)) + return PTR_ERR(pdev); + } - if (AMIGAHW_PRESENT(AMI_PARALLEL)) - platform_device_register_simple("amiga-parallel", -1, NULL, 0); + if (AMIGAHW_PRESENT(AMI_PARALLEL)) { + pdev = platform_device_register_simple("amiga-parallel", -1, + NULL, 0); + if (IS_ERR(pdev)) + return PTR_ERR(pdev); + } /* real time clocks */ - if (AMIGAHW_PRESENT(A2000_CLK)) - platform_device_register_simple("rtc-msm6242", -1, - &amiga_rtc_resource, 1); + if (AMIGAHW_PRESENT(A2000_CLK)) { + pdev = platform_device_register_simple("rtc-msm6242", -1, + &amiga_rtc_resource, 1); + if (IS_ERR(pdev)) + return PTR_ERR(pdev); + } - if (AMIGAHW_PRESENT(A3000_CLK)) - platform_device_register_simple("rtc-rp5c01", -1, - &amiga_rtc_resource, 1); + if (AMIGAHW_PRESENT(A3000_CLK)) { + pdev = platform_device_register_simple("rtc-rp5c01", -1, + &amiga_rtc_resource, 1); + if (IS_ERR(pdev)) + return PTR_ERR(pdev); + } return 0; } -device_initcall(amiga_init_devices); +arch_initcall(amiga_init_devices); diff --git a/arch/m68k/atari/ataints.c b/arch/m68k/atari/ataints.c index 783d8f02360d..3f41092d1b70 100644 --- a/arch/m68k/atari/ataints.c +++ b/arch/m68k/atari/ataints.c @@ -206,7 +206,7 @@ void __init atari_init_IRQ(void) * hardware with a programmable int vector (probably a VME board). */ -unsigned long atari_register_vme_int(void) +unsigned int atari_register_vme_int(void) { int i; @@ -223,7 +223,7 @@ unsigned long atari_register_vme_int(void) EXPORT_SYMBOL(atari_register_vme_int); -void atari_unregister_vme_int(unsigned long irq) +void atari_unregister_vme_int(unsigned int irq) { if (irq >= VME_SOURCE_BASE && irq < VME_SOURCE_BASE + VME_MAX_SOURCES) { irq -= VME_SOURCE_BASE; diff --git a/arch/m68k/configs/m5275evb_defconfig b/arch/m68k/configs/m5275evb_defconfig index 33c32aeca12b..a1230e82bb1e 100644 --- a/arch/m68k/configs/m5275evb_defconfig +++ b/arch/m68k/configs/m5275evb_defconfig @@ -49,7 +49,6 @@ CONFIG_BLK_DEV_RAM=y CONFIG_NETDEVICES=y CONFIG_NET_ETHERNET=y CONFIG_FEC=y -CONFIG_FEC2=y # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set CONFIG_PPP=y diff --git a/arch/m68k/configs/m5475evb_defconfig b/arch/m68k/configs/m5475evb_defconfig new file mode 100644 index 000000000000..c5018a68819b --- /dev/null +++ b/arch/m68k/configs/m5475evb_defconfig @@ -0,0 +1,62 @@ +CONFIG_EXPERIMENTAL=y +# CONFIG_SWAP is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +CONFIG_SYSCTL_SYSCALL=y +# CONFIG_KALLSYMS is not set +# CONFIG_HOTPLUG is not set +# CONFIG_FUTEX is not set +# CONFIG_EPOLL is not set +# CONFIG_SIGNALFD is not set +# CONFIG_TIMERFD is not set +# CONFIG_EVENTFD is not set +# CONFIG_SHMEM is not set +# CONFIG_AIO is not set +CONFIG_EMBEDDED=y +CONFIG_MODULES=y +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_COLDFIRE=y +CONFIG_M547x=y +CONFIG_CLOCK_SET=y +CONFIG_CLOCK_FREQ=266000000 +# CONFIG_4KSTACKS is not set +CONFIG_RAMBASE=0x0 +CONFIG_RAMSIZE=0x2000000 +CONFIG_VECTORBASE=0x0 +CONFIG_MBAR=0xff000000 +CONFIG_KERNELBASE=0x20000 +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_FW_LOADER is not set +CONFIG_MTD=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_RAM=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_UCLINUX=y +CONFIG_BLK_DEV_RAM=y +# CONFIG_INPUT is not set +# CONFIG_VT is not set +# CONFIG_UNIX98_PTYS is not set +CONFIG_SERIAL_MCF=y +CONFIG_SERIAL_MCF_CONSOLE=y +# CONFIG_HW_RANDOM is not set +# CONFIG_HWMON is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_EXT2_FS=y +# CONFIG_FILE_LOCKING is not set +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY_USER is not set +# CONFIG_PROC_PAGE_MONITOR is not set +CONFIG_ROMFS_FS=y +CONFIG_ROMFS_BACKED_BY_MTD=y +# CONFIG_SCHED_DEBUG is not set +CONFIG_BOOTPARAM=y +CONFIG_BOOTPARAM_STRING="root=/dev/mtdblock0" diff --git a/arch/m68k/include/asm/atariints.h b/arch/m68k/include/asm/atariints.h index 656bbbf5a6ff..5fc13bdf9044 100644 --- a/arch/m68k/include/asm/atariints.h +++ b/arch/m68k/include/asm/atariints.h @@ -198,7 +198,7 @@ static inline int atari_irq_pending( unsigned irq ) return( get_mfp_bit( irq, MFP_PENDING ) ); } -unsigned long atari_register_vme_int( void ); -void atari_unregister_vme_int( unsigned long ); +unsigned int atari_register_vme_int(void); +void atari_unregister_vme_int(unsigned int); #endif /* linux/atariints.h */ diff --git a/arch/m68k/include/asm/cacheflush_no.h b/arch/m68k/include/asm/cacheflush_no.h index cb88aa96c4f1..7cafb537d03c 100644 --- a/arch/m68k/include/asm/cacheflush_no.h +++ b/arch/m68k/include/asm/cacheflush_no.h @@ -30,11 +30,8 @@ void mcf_cache_push(void); -static inline void __flush_cache_all(void) +static inline void __clear_cache_all(void) { -#ifdef CACHE_PUSH - mcf_cache_push(); -#endif #ifdef CACHE_INVALIDATE __asm__ __volatile__ ( "movel %0, %%d0\n\t" @@ -44,6 +41,14 @@ static inline void __flush_cache_all(void) #endif } +static inline void __flush_cache_all(void) +{ +#ifdef CACHE_PUSH + mcf_cache_push(); +#endif + __clear_cache_all(); +} + /* * Some ColdFire parts implement separate instruction and data caches, * on those we should just flush the appropriate cache. If we don't need @@ -76,4 +81,23 @@ static inline void __flush_dcache_all(void) __asm__ __volatile__ ( "nop" ); #endif } + +/* + * Push cache entries at supplied address. We want to write back any dirty + * data and the invalidate the cache lines associated with this address. + */ +static inline void cache_push(unsigned long paddr, int len) +{ + __flush_cache_all(); +} + +/* + * Clear cache entries at supplied address (that is don't write back any + * dirty data). + */ +static inline void cache_clear(unsigned long paddr, int len) +{ + __clear_cache_all(); +} + #endif /* _M68KNOMMU_CACHEFLUSH_H */ diff --git a/arch/m68k/include/asm/entry.h b/arch/m68k/include/asm/entry.h index 622138dc7288..d7de0f1a8957 100644 --- a/arch/m68k/include/asm/entry.h +++ b/arch/m68k/include/asm/entry.h @@ -33,13 +33,11 @@ /* the following macro is used when enabling interrupts */ #if defined(MACH_ATARI_ONLY) - /* block out HSYNC on the atari */ -#define ALLOWINT (~0x400) -#define MAX_NOINT_IPL 3 + /* block out HSYNC = ipl 2 on the atari */ +#define ALLOWINT (~0x500) #else /* portable version */ #define ALLOWINT (~0x700) -#define MAX_NOINT_IPL 0 #endif /* machine compilation types */ #ifdef __ASSEMBLY__ diff --git a/arch/m68k/include/asm/flat.h b/arch/m68k/include/asm/flat.h index a0e290793978..f9454b89a51b 100644 --- a/arch/m68k/include/asm/flat.h +++ b/arch/m68k/include/asm/flat.h @@ -11,6 +11,11 @@ #define flat_get_addr_from_rp(rp, relval, flags, p) get_unaligned(rp) #define flat_put_addr_at_rp(rp, val, relval) put_unaligned(val,rp) #define flat_get_relocate_addr(rel) (rel) -#define flat_set_persistent(relval, p) 0 + +static inline int flat_set_persistent(unsigned long relval, + unsigned long *persistent) +{ + return 0; +} #endif /* __M68KNOMMU_FLAT_H__ */ diff --git a/arch/m68k/include/asm/io_mm.h b/arch/m68k/include/asm/io_mm.h index 0fb3468000e7..fa4324bcf566 100644 --- a/arch/m68k/include/asm/io_mm.h +++ b/arch/m68k/include/asm/io_mm.h @@ -278,6 +278,13 @@ static inline void isa_delay(void) #define readl(addr) in_le32(addr) #define writel(val,addr) out_le32((addr),(val)) +#define readsb(port, buf, nr) raw_insb((port), (u8 *)(buf), (nr)) +#define readsw(port, buf, nr) raw_insw((port), (u16 *)(buf), (nr)) +#define readsl(port, buf, nr) raw_insl((port), (u32 *)(buf), (nr)) +#define writesb(port, buf, nr) raw_outsb((port), (u8 *)(buf), (nr)) +#define writesw(port, buf, nr) raw_outsw((port), (u16 *)(buf), (nr)) +#define writesl(port, buf, nr) raw_outsl((port), (u32 *)(buf), (nr)) + #define mmiowb() static inline void __iomem *ioremap(unsigned long physaddr, unsigned long size) diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h index 569476fba18c..d63b99ff7ff7 100644 --- a/arch/m68k/include/asm/m528xsim.h +++ b/arch/m68k/include/asm/m528xsim.h @@ -97,100 +97,81 @@ /* * GPIO registers */ -#define MCFGPIO_PORTA (MCF_IPSBAR + 0x00100000) -#define MCFGPIO_PORTB (MCF_IPSBAR + 0x00100001) -#define MCFGPIO_PORTC (MCF_IPSBAR + 0x00100002) -#define MCFGPIO_PORTD (MCF_IPSBAR + 0x00100003) -#define MCFGPIO_PORTE (MCF_IPSBAR + 0x00100004) -#define MCFGPIO_PORTF (MCF_IPSBAR + 0x00100005) -#define MCFGPIO_PORTG (MCF_IPSBAR + 0x00100006) -#define MCFGPIO_PORTH (MCF_IPSBAR + 0x00100007) -#define MCFGPIO_PORTJ (MCF_IPSBAR + 0x00100008) -#define MCFGPIO_PORTDD (MCF_IPSBAR + 0x00100009) -#define MCFGPIO_PORTEH (MCF_IPSBAR + 0x0010000A) -#define MCFGPIO_PORTEL (MCF_IPSBAR + 0x0010000B) -#define MCFGPIO_PORTAS (MCF_IPSBAR + 0x0010000C) -#define MCFGPIO_PORTQS (MCF_IPSBAR + 0x0010000D) -#define MCFGPIO_PORTSD (MCF_IPSBAR + 0x0010000E) -#define MCFGPIO_PORTTC (MCF_IPSBAR + 0x0010000F) -#define MCFGPIO_PORTTD (MCF_IPSBAR + 0x00100010) -#define MCFGPIO_PORTUA (MCF_IPSBAR + 0x00100011) - -#define MCFGPIO_DDRA (MCF_IPSBAR + 0x00100014) -#define MCFGPIO_DDRB (MCF_IPSBAR + 0x00100015) -#define MCFGPIO_DDRC (MCF_IPSBAR + 0x00100016) -#define MCFGPIO_DDRD (MCF_IPSBAR + 0x00100017) -#define MCFGPIO_DDRE (MCF_IPSBAR + 0x00100018) -#define MCFGPIO_DDRF (MCF_IPSBAR + 0x00100019) -#define MCFGPIO_DDRG (MCF_IPSBAR + 0x0010001A) -#define MCFGPIO_DDRH (MCF_IPSBAR + 0x0010001B) -#define MCFGPIO_DDRJ (MCF_IPSBAR + 0x0010001C) -#define MCFGPIO_DDRDD (MCF_IPSBAR + 0x0010001D) -#define MCFGPIO_DDREH (MCF_IPSBAR + 0x0010001E) -#define MCFGPIO_DDREL (MCF_IPSBAR + 0x0010001F) -#define MCFGPIO_DDRAS (MCF_IPSBAR + 0x00100020) -#define MCFGPIO_DDRQS (MCF_IPSBAR + 0x00100021) -#define MCFGPIO_DDRSD (MCF_IPSBAR + 0x00100022) -#define MCFGPIO_DDRTC (MCF_IPSBAR + 0x00100023) -#define MCFGPIO_DDRTD (MCF_IPSBAR + 0x00100024) -#define MCFGPIO_DDRUA (MCF_IPSBAR + 0x00100025) - -#define MCFGPIO_PORTAP (MCF_IPSBAR + 0x00100028) -#define MCFGPIO_PORTBP (MCF_IPSBAR + 0x00100029) -#define MCFGPIO_PORTCP (MCF_IPSBAR + 0x0010002A) -#define MCFGPIO_PORTDP (MCF_IPSBAR + 0x0010002B) -#define MCFGPIO_PORTEP (MCF_IPSBAR + 0x0010002C) -#define MCFGPIO_PORTFP (MCF_IPSBAR + 0x0010002D) -#define MCFGPIO_PORTGP (MCF_IPSBAR + 0x0010002E) -#define MCFGPIO_PORTHP (MCF_IPSBAR + 0x0010002F) -#define MCFGPIO_PORTJP (MCF_IPSBAR + 0x00100030) -#define MCFGPIO_PORTDDP (MCF_IPSBAR + 0x00100031) -#define MCFGPIO_PORTEHP (MCF_IPSBAR + 0x00100032) -#define MCFGPIO_PORTELP (MCF_IPSBAR + 0x00100033) -#define MCFGPIO_PORTASP (MCF_IPSBAR + 0x00100034) -#define MCFGPIO_PORTQSP (MCF_IPSBAR + 0x00100035) -#define MCFGPIO_PORTSDP (MCF_IPSBAR + 0x00100036) -#define MCFGPIO_PORTTCP (MCF_IPSBAR + 0x00100037) -#define MCFGPIO_PORTTDP (MCF_IPSBAR + 0x00100038) -#define MCFGPIO_PORTUAP (MCF_IPSBAR + 0x00100039) - -#define MCFGPIO_SETA (MCF_IPSBAR + 0x00100028) -#define MCFGPIO_SETB (MCF_IPSBAR + 0x00100029) -#define MCFGPIO_SETC (MCF_IPSBAR + 0x0010002A) -#define MCFGPIO_SETD (MCF_IPSBAR + 0x0010002B) -#define MCFGPIO_SETE (MCF_IPSBAR + 0x0010002C) -#define MCFGPIO_SETF (MCF_IPSBAR + 0x0010002D) -#define MCFGPIO_SETG (MCF_IPSBAR + 0x0010002E) -#define MCFGPIO_SETH (MCF_IPSBAR + 0x0010002F) -#define MCFGPIO_SETJ (MCF_IPSBAR + 0x00100030) -#define MCFGPIO_SETDD (MCF_IPSBAR + 0x00100031) -#define MCFGPIO_SETEH (MCF_IPSBAR + 0x00100032) -#define MCFGPIO_SETEL (MCF_IPSBAR + 0x00100033) -#define MCFGPIO_SETAS (MCF_IPSBAR + 0x00100034) -#define MCFGPIO_SETQS (MCF_IPSBAR + 0x00100035) -#define MCFGPIO_SETSD (MCF_IPSBAR + 0x00100036) -#define MCFGPIO_SETTC (MCF_IPSBAR + 0x00100037) -#define MCFGPIO_SETTD (MCF_IPSBAR + 0x00100038) -#define MCFGPIO_SETUA (MCF_IPSBAR + 0x00100039) - -#define MCFGPIO_CLRA (MCF_IPSBAR + 0x0010003C) -#define MCFGPIO_CLRB (MCF_IPSBAR + 0x0010003D) -#define MCFGPIO_CLRC (MCF_IPSBAR + 0x0010003E) -#define MCFGPIO_CLRD (MCF_IPSBAR + 0x0010003F) -#define MCFGPIO_CLRE (MCF_IPSBAR + 0x00100040) -#define MCFGPIO_CLRF (MCF_IPSBAR + 0x00100041) -#define MCFGPIO_CLRG (MCF_IPSBAR + 0x00100042) -#define MCFGPIO_CLRH (MCF_IPSBAR + 0x00100043) -#define MCFGPIO_CLRJ (MCF_IPSBAR + 0x00100044) -#define MCFGPIO_CLRDD (MCF_IPSBAR + 0x00100045) -#define MCFGPIO_CLREH (MCF_IPSBAR + 0x00100046) -#define MCFGPIO_CLREL (MCF_IPSBAR + 0x00100047) -#define MCFGPIO_CLRAS (MCF_IPSBAR + 0x00100048) -#define MCFGPIO_CLRQS (MCF_IPSBAR + 0x00100049) -#define MCFGPIO_CLRSD (MCF_IPSBAR + 0x0010004A) -#define MCFGPIO_CLRTC (MCF_IPSBAR + 0x0010004B) -#define MCFGPIO_CLRTD (MCF_IPSBAR + 0x0010004C) -#define MCFGPIO_CLRUA (MCF_IPSBAR + 0x0010004D) +#define MCFGPIO_PODR_A (MCF_IPSBAR + 0x00100000) +#define MCFGPIO_PODR_B (MCF_IPSBAR + 0x00100001) +#define MCFGPIO_PODR_C (MCF_IPSBAR + 0x00100002) +#define MCFGPIO_PODR_D (MCF_IPSBAR + 0x00100003) +#define MCFGPIO_PODR_E (MCF_IPSBAR + 0x00100004) +#define MCFGPIO_PODR_F (MCF_IPSBAR + 0x00100005) +#define MCFGPIO_PODR_G (MCF_IPSBAR + 0x00100006) +#define MCFGPIO_PODR_H (MCF_IPSBAR + 0x00100007) +#define MCFGPIO_PODR_J (MCF_IPSBAR + 0x00100008) +#define MCFGPIO_PODR_DD (MCF_IPSBAR + 0x00100009) +#define MCFGPIO_PODR_EH (MCF_IPSBAR + 0x0010000A) +#define MCFGPIO_PODR_EL (MCF_IPSBAR + 0x0010000B) +#define MCFGPIO_PODR_AS (MCF_IPSBAR + 0x0010000C) +#define MCFGPIO_PODR_QS (MCF_IPSBAR + 0x0010000D) +#define MCFGPIO_PODR_SD (MCF_IPSBAR + 0x0010000E) +#define MCFGPIO_PODR_TC (MCF_IPSBAR + 0x0010000F) +#define MCFGPIO_PODR_TD (MCF_IPSBAR + 0x00100010) +#define MCFGPIO_PODR_UA (MCF_IPSBAR + 0x00100011) + +#define MCFGPIO_PDDR_A (MCF_IPSBAR + 0x00100014) +#define MCFGPIO_PDDR_B (MCF_IPSBAR + 0x00100015) +#define MCFGPIO_PDDR_C (MCF_IPSBAR + 0x00100016) +#define MCFGPIO_PDDR_D (MCF_IPSBAR + 0x00100017) +#define MCFGPIO_PDDR_E (MCF_IPSBAR + 0x00100018) +#define MCFGPIO_PDDR_F (MCF_IPSBAR + 0x00100019) +#define MCFGPIO_PDDR_G (MCF_IPSBAR + 0x0010001A) +#define MCFGPIO_PDDR_H (MCF_IPSBAR + 0x0010001B) +#define MCFGPIO_PDDR_J (MCF_IPSBAR + 0x0010001C) +#define MCFGPIO_PDDR_DD (MCF_IPSBAR + 0x0010001D) +#define MCFGPIO_PDDR_EH (MCF_IPSBAR + 0x0010001E) +#define MCFGPIO_PDDR_EL (MCF_IPSBAR + 0x0010001F) +#define MCFGPIO_PDDR_AS (MCF_IPSBAR + 0x00100020) +#define MCFGPIO_PDDR_QS (MCF_IPSBAR + 0x00100021) +#define MCFGPIO_PDDR_SD (MCF_IPSBAR + 0x00100022) +#define MCFGPIO_PDDR_TC (MCF_IPSBAR + 0x00100023) +#define MCFGPIO_PDDR_TD (MCF_IPSBAR + 0x00100024) +#define MCFGPIO_PDDR_UA (MCF_IPSBAR + 0x00100025) + +#define MCFGPIO_PPDSDR_A (MCF_IPSBAR + 0x00100028) +#define MCFGPIO_PPDSDR_B (MCF_IPSBAR + 0x00100029) +#define MCFGPIO_PPDSDR_C (MCF_IPSBAR + 0x0010002A) +#define MCFGPIO_PPDSDR_D (MCF_IPSBAR + 0x0010002B) +#define MCFGPIO_PPDSDR_E (MCF_IPSBAR + 0x0010002C) +#define MCFGPIO_PPDSDR_F (MCF_IPSBAR + 0x0010002D) +#define MCFGPIO_PPDSDR_G (MCF_IPSBAR + 0x0010002E) +#define MCFGPIO_PPDSDR_H (MCF_IPSBAR + 0x0010002F) +#define MCFGPIO_PPDSDR_J (MCF_IPSBAR + 0x00100030) +#define MCFGPIO_PPDSDR_DD (MCF_IPSBAR + 0x00100031) +#define MCFGPIO_PPDSDR_EH (MCF_IPSBAR + 0x00100032) +#define MCFGPIO_PPDSDR_EL (MCF_IPSBAR + 0x00100033) +#define MCFGPIO_PPDSDR_AS (MCF_IPSBAR + 0x00100034) +#define MCFGPIO_PPDSDR_QS (MCF_IPSBAR + 0x00100035) +#define MCFGPIO_PPDSDR_SD (MCF_IPSBAR + 0x00100036) +#define MCFGPIO_PPDSDR_TC (MCF_IPSBAR + 0x00100037) +#define MCFGPIO_PPDSDR_TD (MCF_IPSBAR + 0x00100038) +#define MCFGPIO_PPDSDR_UA (MCF_IPSBAR + 0x00100039) + +#define MCFGPIO_PCLRR_A (MCF_IPSBAR + 0x0010003C) +#define MCFGPIO_PCLRR_B (MCF_IPSBAR + 0x0010003D) +#define MCFGPIO_PCLRR_C (MCF_IPSBAR + 0x0010003E) +#define MCFGPIO_PCLRR_D (MCF_IPSBAR + 0x0010003F) +#define MCFGPIO_PCLRR_E (MCF_IPSBAR + 0x00100040) +#define MCFGPIO_PCLRR_F (MCF_IPSBAR + 0x00100041) +#define MCFGPIO_PCLRR_G (MCF_IPSBAR + 0x00100042) +#define MCFGPIO_PCLRR_H (MCF_IPSBAR + 0x00100043) +#define MCFGPIO_PCLRR_J (MCF_IPSBAR + 0x00100044) +#define MCFGPIO_PCLRR_DD (MCF_IPSBAR + 0x00100045) +#define MCFGPIO_PCLRR_EH (MCF_IPSBAR + 0x00100046) +#define MCFGPIO_PCLRR_EL (MCF_IPSBAR + 0x00100047) +#define MCFGPIO_PCLRR_AS (MCF_IPSBAR + 0x00100048) +#define MCFGPIO_PCLRR_QS (MCF_IPSBAR + 0x00100049) +#define MCFGPIO_PCLRR_SD (MCF_IPSBAR + 0x0010004A) +#define MCFGPIO_PCLRR_TC (MCF_IPSBAR + 0x0010004B) +#define MCFGPIO_PCLRR_TD (MCF_IPSBAR + 0x0010004C) +#define MCFGPIO_PCLRR_UA (MCF_IPSBAR + 0x0010004D) #define MCFGPIO_PBCDPAR (MCF_IPSBAR + 0x00100050) #define MCFGPIO_PFPAR (MCF_IPSBAR + 0x00100051) @@ -242,11 +223,11 @@ * definitions for generic gpio support * */ -#define MCFGPIO_PODR MCFGPIO_PORTA /* port output data */ -#define MCFGPIO_PDDR MCFGPIO_DDRA /* port data direction */ -#define MCFGPIO_PPDR MCFGPIO_PORTAP /* port pin data */ -#define MCFGPIO_SETR MCFGPIO_SETA /* set output */ -#define MCFGPIO_CLRR MCFGPIO_CLRA /* clr output */ +#define MCFGPIO_PODR MCFGPIO_PODR_A /* port output data */ +#define MCFGPIO_PDDR MCFGPIO_PDDR_A /* port data direction */ +#define MCFGPIO_PPDR MCFGPIO_PPDSDR_A/* port pin data */ +#define MCFGPIO_SETR MCFGPIO_PPDSDR_A/* set output */ +#define MCFGPIO_CLRR MCFGPIO_PCLRR_A /* clr output */ #define MCFGPIO_IRQ_MAX 8 #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE diff --git a/arch/m68k/include/asm/mcfgpio.h b/arch/m68k/include/asm/mcfgpio.h index ee5e4ccce89e..fe468eaa51e0 100644 --- a/arch/m68k/include/asm/mcfgpio.h +++ b/arch/m68k/include/asm/mcfgpio.h @@ -29,6 +29,9 @@ struct mcf_gpio_chip { const u8 *gpio_to_pinmux; }; +extern struct mcf_gpio_chip mcf_gpio_chips[]; +extern unsigned int mcf_gpio_chips_size; + int mcf_gpio_direction_input(struct gpio_chip *, unsigned); int mcf_gpio_get_value(struct gpio_chip *, unsigned); int mcf_gpio_direction_output(struct gpio_chip *, unsigned, int); @@ -37,4 +40,58 @@ void mcf_gpio_set_value_fast(struct gpio_chip *, unsigned, int); int mcf_gpio_request(struct gpio_chip *, unsigned); void mcf_gpio_free(struct gpio_chip *, unsigned); +/* + * Define macros to ease the pain of setting up the GPIO tables. There + * are two cases we need to deal with here, they cover all currently + * available ColdFire GPIO hardware. There are of course minor differences + * in the layout and number of bits in each ColdFire part, but the macros + * take all that in. + * + * Firstly is the conventional GPIO registers where we toggle individual + * bits in a register, preserving the other bits in the register. For + * lack of a better term I have called this the slow method. + */ +#define MCFGPS(mlabel, mbase, mngpio, mpddr, mpodr, mppdr) \ + { \ + .gpio_chip = { \ + .label = #mlabel, \ + .request = mcf_gpio_request, \ + .free = mcf_gpio_free, \ + .direction_input = mcf_gpio_direction_input, \ + .direction_output = mcf_gpio_direction_output,\ + .get = mcf_gpio_get_value, \ + .set = mcf_gpio_set_value, \ + .base = mbase, \ + .ngpio = mngpio, \ + }, \ + .pddr = (void __iomem *) mpddr, \ + .podr = (void __iomem *) mpodr, \ + .ppdr = (void __iomem *) mppdr, \ + } + +/* + * Secondly is the faster case, where we have set and clear registers + * that allow us to set or clear a bit with a single write, not having + * to worry about preserving other bits. + */ +#define MCFGPF(mlabel, mbase, mngpio) \ + { \ + .gpio_chip = { \ + .label = #mlabel, \ + .request = mcf_gpio_request, \ + .free = mcf_gpio_free, \ + .direction_input = mcf_gpio_direction_input, \ + .direction_output = mcf_gpio_direction_output,\ + .get = mcf_gpio_get_value, \ + .set = mcf_gpio_set_value_fast, \ + .base = mbase, \ + .ngpio = mngpio, \ + }, \ + .pddr = (void __iomem *) MCFGPIO_PDDR_##mlabel, \ + .podr = (void __iomem *) MCFGPIO_PODR_##mlabel, \ + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_##mlabel, \ + .setr = (void __iomem *) MCFGPIO_PPDSDR_##mlabel, \ + .clrr = (void __iomem *) MCFGPIO_PCLRR_##mlabel, \ + } + #endif diff --git a/arch/m68k/include/asm/unaligned.h b/arch/m68k/include/asm/unaligned.h index 019caa740c21..f4043ae63db1 100644 --- a/arch/m68k/include/asm/unaligned.h +++ b/arch/m68k/include/asm/unaligned.h @@ -2,7 +2,7 @@ #define _ASM_M68K_UNALIGNED_H -#ifdef CONFIG_COLDFIRE +#if defined(CONFIG_COLDFIRE) || defined(CONFIG_M68000) #include <linux/unaligned/be_struct.h> #include <linux/unaligned/le_byteshift.h> #include <linux/unaligned/generic.h> diff --git a/arch/m68k/include/asm/vga.h b/arch/m68k/include/asm/vga.h new file mode 100644 index 000000000000..d3aa1401e7aa --- /dev/null +++ b/arch/m68k/include/asm/vga.h @@ -0,0 +1,27 @@ +#ifndef _ASM_M68K_VGA_H +#define _ASM_M68K_VGA_H + +#include <asm/raw_io.h> + +/* + * FIXME + * Ugh, we don't have PCI space, so map readb() and friends to use raw I/O + * accessors, which are identical to the z_*() Zorro bus accessors. + * This should make cirrusfb work again on Amiga + */ +#undef inb_p +#undef inw_p +#undef outb_p +#undef outw +#undef readb +#undef writeb +#undef writew +#define inb_p(port) 0 +#define inw_p(port) 0 +#define outb_p(port, val) do { } while (0) +#define outw(port, val) do { } while (0) +#define readb raw_inb +#define writeb raw_outb +#define writew raw_outw + +#endif /* _ASM_M68K_VGA_H */ diff --git a/arch/m68k/kernel/dma.c b/arch/m68k/kernel/dma.c index 90e8cb726c8c..f6daf6e15d2e 100644 --- a/arch/m68k/kernel/dma.c +++ b/arch/m68k/kernel/dma.c @@ -1,5 +1,164 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +#undef DEBUG + +#include <linux/dma-mapping.h> +#include <linux/device.h> +#include <linux/kernel.h> +#include <linux/scatterlist.h> +#include <linux/slab.h> +#include <linux/vmalloc.h> +#include <linux/export.h> + +#include <asm/pgalloc.h> + #ifdef CONFIG_MMU -#include "dma_mm.c" + +void *dma_alloc_coherent(struct device *dev, size_t size, + dma_addr_t *handle, gfp_t flag) +{ + struct page *page, **map; + pgprot_t pgprot; + void *addr; + int i, order; + + pr_debug("dma_alloc_coherent: %d,%x\n", size, flag); + + size = PAGE_ALIGN(size); + order = get_order(size); + + page = alloc_pages(flag, order); + if (!page) + return NULL; + + *handle = page_to_phys(page); + map = kmalloc(sizeof(struct page *) << order, flag & ~__GFP_DMA); + if (!map) { + __free_pages(page, order); + return NULL; + } + split_page(page, order); + + order = 1 << order; + size >>= PAGE_SHIFT; + map[0] = page; + for (i = 1; i < size; i++) + map[i] = page + i; + for (; i < order; i++) + __free_page(page + i); + pgprot = __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_DIRTY); + if (CPU_IS_040_OR_060) + pgprot_val(pgprot) |= _PAGE_GLOBAL040 | _PAGE_NOCACHE_S; + else + pgprot_val(pgprot) |= _PAGE_NOCACHE030; + addr = vmap(map, size, VM_MAP, pgprot); + kfree(map); + + return addr; +} + +void dma_free_coherent(struct device *dev, size_t size, + void *addr, dma_addr_t handle) +{ + pr_debug("dma_free_coherent: %p, %x\n", addr, handle); + vfree(addr); +} + #else -#include "dma_no.c" -#endif + +#include <asm/cacheflush.h> + +void *dma_alloc_coherent(struct device *dev, size_t size, + dma_addr_t *dma_handle, gfp_t gfp) +{ + void *ret; + /* ignore region specifiers */ + gfp &= ~(__GFP_DMA | __GFP_HIGHMEM); + + if (dev == NULL || (*dev->dma_mask < 0xffffffff)) + gfp |= GFP_DMA; + ret = (void *)__get_free_pages(gfp, get_order(size)); + + if (ret != NULL) { + memset(ret, 0, size); + *dma_handle = virt_to_phys(ret); + } + return ret; +} + +void dma_free_coherent(struct device *dev, size_t size, + void *vaddr, dma_addr_t dma_handle) +{ + free_pages((unsigned long)vaddr, get_order(size)); +} + +#endif /* CONFIG_MMU */ + +EXPORT_SYMBOL(dma_alloc_coherent); +EXPORT_SYMBOL(dma_free_coherent); + +void dma_sync_single_for_device(struct device *dev, dma_addr_t handle, + size_t size, enum dma_data_direction dir) +{ + switch (dir) { + case DMA_TO_DEVICE: + cache_push(handle, size); + break; + case DMA_FROM_DEVICE: + cache_clear(handle, size); + break; + default: + if (printk_ratelimit()) + printk("dma_sync_single_for_device: unsupported dir %u\n", dir); + break; + } +} +EXPORT_SYMBOL(dma_sync_single_for_device); + +void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nents, + enum dma_data_direction dir) +{ + int i; + + for (i = 0; i < nents; sg++, i++) + dma_sync_single_for_device(dev, sg->dma_address, sg->length, dir); +} +EXPORT_SYMBOL(dma_sync_sg_for_device); + +dma_addr_t dma_map_single(struct device *dev, void *addr, size_t size, + enum dma_data_direction dir) +{ + dma_addr_t handle = virt_to_bus(addr); + + dma_sync_single_for_device(dev, handle, size, dir); + return handle; +} +EXPORT_SYMBOL(dma_map_single); + +dma_addr_t dma_map_page(struct device *dev, struct page *page, + unsigned long offset, size_t size, + enum dma_data_direction dir) +{ + dma_addr_t handle = page_to_phys(page) + offset; + + dma_sync_single_for_device(dev, handle, size, dir); + return handle; +} +EXPORT_SYMBOL(dma_map_page); + +int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, + enum dma_data_direction dir) +{ + int i; + + for (i = 0; i < nents; sg++, i++) { + sg->dma_address = sg_phys(sg); + dma_sync_single_for_device(dev, sg->dma_address, sg->length, dir); + } + return nents; +} +EXPORT_SYMBOL(dma_map_sg); diff --git a/arch/m68k/kernel/dma_mm.c b/arch/m68k/kernel/dma_mm.c deleted file mode 100644 index a3c471b523f2..000000000000 --- a/arch/m68k/kernel/dma_mm.c +++ /dev/null @@ -1,131 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ - -#undef DEBUG - -#include <linux/dma-mapping.h> -#include <linux/device.h> -#include <linux/kernel.h> -#include <linux/scatterlist.h> -#include <linux/slab.h> -#include <linux/vmalloc.h> -#include <linux/export.h> - -#include <asm/pgalloc.h> - -void *dma_alloc_coherent(struct device *dev, size_t size, - dma_addr_t *handle, gfp_t flag) -{ - struct page *page, **map; - pgprot_t pgprot; - void *addr; - int i, order; - - pr_debug("dma_alloc_coherent: %d,%x\n", size, flag); - - size = PAGE_ALIGN(size); - order = get_order(size); - - page = alloc_pages(flag, order); - if (!page) - return NULL; - - *handle = page_to_phys(page); - map = kmalloc(sizeof(struct page *) << order, flag & ~__GFP_DMA); - if (!map) { - __free_pages(page, order); - return NULL; - } - split_page(page, order); - - order = 1 << order; - size >>= PAGE_SHIFT; - map[0] = page; - for (i = 1; i < size; i++) - map[i] = page + i; - for (; i < order; i++) - __free_page(page + i); - pgprot = __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_DIRTY); - if (CPU_IS_040_OR_060) - pgprot_val(pgprot) |= _PAGE_GLOBAL040 | _PAGE_NOCACHE_S; - else - pgprot_val(pgprot) |= _PAGE_NOCACHE030; - addr = vmap(map, size, VM_MAP, pgprot); - kfree(map); - - return addr; -} -EXPORT_SYMBOL(dma_alloc_coherent); - -void dma_free_coherent(struct device *dev, size_t size, - void *addr, dma_addr_t handle) -{ - pr_debug("dma_free_coherent: %p, %x\n", addr, handle); - vfree(addr); -} -EXPORT_SYMBOL(dma_free_coherent); - -void dma_sync_single_for_device(struct device *dev, dma_addr_t handle, - size_t size, enum dma_data_direction dir) -{ - switch (dir) { - case DMA_TO_DEVICE: - cache_push(handle, size); - break; - case DMA_FROM_DEVICE: - cache_clear(handle, size); - break; - default: - if (printk_ratelimit()) - printk("dma_sync_single_for_device: unsupported dir %u\n", dir); - break; - } -} -EXPORT_SYMBOL(dma_sync_single_for_device); - -void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nents, - enum dma_data_direction dir) -{ - int i; - - for (i = 0; i < nents; sg++, i++) - dma_sync_single_for_device(dev, sg->dma_address, sg->length, dir); -} -EXPORT_SYMBOL(dma_sync_sg_for_device); - -dma_addr_t dma_map_single(struct device *dev, void *addr, size_t size, - enum dma_data_direction dir) -{ - dma_addr_t handle = virt_to_bus(addr); - - dma_sync_single_for_device(dev, handle, size, dir); - return handle; -} -EXPORT_SYMBOL(dma_map_single); - -dma_addr_t dma_map_page(struct device *dev, struct page *page, - unsigned long offset, size_t size, - enum dma_data_direction dir) -{ - dma_addr_t handle = page_to_phys(page) + offset; - - dma_sync_single_for_device(dev, handle, size, dir); - return handle; -} -EXPORT_SYMBOL(dma_map_page); - -int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, - enum dma_data_direction dir) -{ - int i; - - for (i = 0; i < nents; sg++, i++) { - sg->dma_address = sg_phys(sg); - dma_sync_single_for_device(dev, sg->dma_address, sg->length, dir); - } - return nents; -} -EXPORT_SYMBOL(dma_map_sg); diff --git a/arch/m68k/kernel/dma_no.c b/arch/m68k/kernel/dma_no.c deleted file mode 100644 index f1dc3fc71bc2..000000000000 --- a/arch/m68k/kernel/dma_no.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Dynamic DMA mapping support. - * - * We never have any address translations to worry about, so this - * is just alloc/free. - */ - -#include <linux/types.h> -#include <linux/gfp.h> -#include <linux/mm.h> -#include <linux/device.h> -#include <linux/dma-mapping.h> -#include <linux/export.h> -#include <asm/cacheflush.h> - -void *dma_alloc_coherent(struct device *dev, size_t size, - dma_addr_t *dma_handle, gfp_t gfp) -{ - void *ret; - /* ignore region specifiers */ - gfp &= ~(__GFP_DMA | __GFP_HIGHMEM); - - if (dev == NULL || (*dev->dma_mask < 0xffffffff)) - gfp |= GFP_DMA; - ret = (void *)__get_free_pages(gfp, get_order(size)); - - if (ret != NULL) { - memset(ret, 0, size); - *dma_handle = virt_to_phys(ret); - } - return ret; -} - -void dma_free_coherent(struct device *dev, size_t size, - void *vaddr, dma_addr_t dma_handle) -{ - free_pages((unsigned long)vaddr, get_order(size)); -} - -void dma_sync_single_for_device(struct device *dev, dma_addr_t handle, - size_t size, enum dma_data_direction dir) -{ - switch (dir) { - case DMA_TO_DEVICE: - flush_dcache_range(handle, size); - break; - case DMA_FROM_DEVICE: - /* Should be clear already */ - break; - default: - if (printk_ratelimit()) - printk("dma_sync_single_for_device: unsupported dir %u\n", dir); - break; - } -} - -EXPORT_SYMBOL(dma_sync_single_for_device); -dma_addr_t dma_map_single(struct device *dev, void *addr, size_t size, - enum dma_data_direction dir) -{ - dma_addr_t handle = virt_to_phys(addr); - flush_dcache_range(handle, size); - return handle; -} -EXPORT_SYMBOL(dma_map_single); - -dma_addr_t dma_map_page(struct device *dev, struct page *page, - unsigned long offset, size_t size, - enum dma_data_direction dir) -{ - dma_addr_t handle = page_to_phys(page) + offset; - dma_sync_single_for_device(dev, handle, size, dir); - return handle; -} -EXPORT_SYMBOL(dma_map_page); diff --git a/arch/m68k/kernel/signal.c b/arch/m68k/kernel/signal.c index 2e25713e2ead..1747c7030a33 100644 --- a/arch/m68k/kernel/signal.c +++ b/arch/m68k/kernel/signal.c @@ -1,5 +1,1202 @@ +/* + * linux/arch/m68k/kernel/signal.c + * + * Copyright (C) 1991, 1992 Linus Torvalds + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +/* + * Linux/m68k support by Hamish Macdonald + * + * 68060 fixes by Jesper Skov + * + * 1997-12-01 Modified for POSIX.1b signals by Andreas Schwab + * + * mathemu support by Roman Zippel + * (Note: fpstate in the signal context is completely ignored for the emulator + * and the internal floating point format is put on stack) + */ + +/* + * ++roman (07/09/96): implemented signal stacks (specially for tosemu on + * Atari :-) Current limitation: Only one sigstack can be active at one time. + * If a second signal with SA_ONSTACK set arrives while working on a sigstack, + * SA_ONSTACK is ignored. This behaviour avoids lots of trouble with nested + * signal handlers! + */ + +#include <linux/sched.h> +#include <linux/mm.h> +#include <linux/kernel.h> +#include <linux/signal.h> +#include <linux/syscalls.h> +#include <linux/errno.h> +#include <linux/wait.h> +#include <linux/ptrace.h> +#include <linux/unistd.h> +#include <linux/stddef.h> +#include <linux/highuid.h> +#include <linux/personality.h> +#include <linux/tty.h> +#include <linux/binfmts.h> +#include <linux/module.h> + +#include <asm/setup.h> +#include <asm/uaccess.h> +#include <asm/pgtable.h> +#include <asm/traps.h> +#include <asm/ucontext.h> + +#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP))) + #ifdef CONFIG_MMU -#include "signal_mm.c" + +/* + * Handle the slight differences in classic 68k and ColdFire trap frames. + */ +#ifdef CONFIG_COLDFIRE +#define FORMAT 4 +#define FMT4SIZE 0 #else -#include "signal_no.c" +#define FORMAT 0 +#define FMT4SIZE sizeof(((struct frame *)0)->un.fmt4) #endif + +static const int frame_size_change[16] = { + [1] = -1, /* sizeof(((struct frame *)0)->un.fmt1), */ + [2] = sizeof(((struct frame *)0)->un.fmt2), + [3] = sizeof(((struct frame *)0)->un.fmt3), + [4] = FMT4SIZE, + [5] = -1, /* sizeof(((struct frame *)0)->un.fmt5), */ + [6] = -1, /* sizeof(((struct frame *)0)->un.fmt6), */ + [7] = sizeof(((struct frame *)0)->un.fmt7), + [8] = -1, /* sizeof(((struct frame *)0)->un.fmt8), */ + [9] = sizeof(((struct frame *)0)->un.fmt9), + [10] = sizeof(((struct frame *)0)->un.fmta), + [11] = sizeof(((struct frame *)0)->un.fmtb), + [12] = -1, /* sizeof(((struct frame *)0)->un.fmtc), */ + [13] = -1, /* sizeof(((struct frame *)0)->un.fmtd), */ + [14] = -1, /* sizeof(((struct frame *)0)->un.fmte), */ + [15] = -1, /* sizeof(((struct frame *)0)->un.fmtf), */ +}; + +static inline int frame_extra_sizes(int f) +{ + return frame_size_change[f]; +} + +int handle_kernel_fault(struct pt_regs *regs) +{ + const struct exception_table_entry *fixup; + struct pt_regs *tregs; + + /* Are we prepared to handle this kernel fault? */ + fixup = search_exception_tables(regs->pc); + if (!fixup) + return 0; + + /* Create a new four word stack frame, discarding the old one. */ + regs->stkadj = frame_extra_sizes(regs->format); + tregs = (struct pt_regs *)((long)regs + regs->stkadj); + tregs->vector = regs->vector; + tregs->format = FORMAT; + tregs->pc = fixup->fixup; + tregs->sr = regs->sr; + + return 1; +} + +void ptrace_signal_deliver(struct pt_regs *regs, void *cookie) +{ + if (regs->orig_d0 < 0) + return; + switch (regs->d0) { + case -ERESTARTNOHAND: + case -ERESTARTSYS: + case -ERESTARTNOINTR: + regs->d0 = regs->orig_d0; + regs->orig_d0 = -1; + regs->pc -= 2; + break; + } +} + +static inline void push_cache (unsigned long vaddr) +{ + /* + * Using the old cache_push_v() was really a big waste. + * + * What we are trying to do is to flush 8 bytes to ram. + * Flushing 2 cache lines of 16 bytes is much cheaper than + * flushing 1 or 2 pages, as previously done in + * cache_push_v(). + * Jes + */ + if (CPU_IS_040) { + unsigned long temp; + + __asm__ __volatile__ (".chip 68040\n\t" + "nop\n\t" + "ptestr (%1)\n\t" + "movec %%mmusr,%0\n\t" + ".chip 68k" + : "=r" (temp) + : "a" (vaddr)); + + temp &= PAGE_MASK; + temp |= vaddr & ~PAGE_MASK; + + __asm__ __volatile__ (".chip 68040\n\t" + "nop\n\t" + "cpushl %%bc,(%0)\n\t" + ".chip 68k" + : : "a" (temp)); + } + else if (CPU_IS_060) { + unsigned long temp; + __asm__ __volatile__ (".chip 68060\n\t" + "plpar (%0)\n\t" + ".chip 68k" + : "=a" (temp) + : "0" (vaddr)); + __asm__ __volatile__ (".chip 68060\n\t" + "cpushl %%bc,(%0)\n\t" + ".chip 68k" + : : "a" (temp)); + } else if (!CPU_IS_COLDFIRE) { + /* + * 68030/68020 have no writeback cache; + * still need to clear icache. + * Note that vaddr is guaranteed to be long word aligned. + */ + unsigned long temp; + asm volatile ("movec %%cacr,%0" : "=r" (temp)); + temp += 4; + asm volatile ("movec %0,%%caar\n\t" + "movec %1,%%cacr" + : : "r" (vaddr), "r" (temp)); + asm volatile ("movec %0,%%caar\n\t" + "movec %1,%%cacr" + : : "r" (vaddr + 4), "r" (temp)); + } +} + +static inline void adjustformat(struct pt_regs *regs) +{ +} + +static inline void save_a5_state(struct sigcontext *sc, struct pt_regs *regs) +{ +} + +#else /* CONFIG_MMU */ + +void ret_from_user_signal(void); +void ret_from_user_rt_signal(void); + +static inline int frame_extra_sizes(int f) +{ + /* No frame size adjustments required on non-MMU CPUs */ + return 0; +} + +static inline void adjustformat(struct pt_regs *regs) +{ + ((struct switch_stack *)regs - 1)->a5 = current->mm->start_data; + /* + * set format byte to make stack appear modulo 4, which it will + * be when doing the rte + */ + regs->format = 0x4; +} + +static inline void save_a5_state(struct sigcontext *sc, struct pt_regs *regs) +{ + sc->sc_a5 = ((struct switch_stack *)regs - 1)->a5; +} + +static inline void push_cache(unsigned long vaddr) +{ +} + +#endif /* CONFIG_MMU */ + +/* + * Atomically swap in the new signal mask, and wait for a signal. + */ +asmlinkage int +sys_sigsuspend(int unused0, int unused1, old_sigset_t mask) +{ + mask &= _BLOCKABLE; + spin_lock_irq(¤t->sighand->siglock); + current->saved_sigmask = current->blocked; + siginitset(¤t->blocked, mask); + recalc_sigpending(); + spin_unlock_irq(¤t->sighand->siglock); + + current->state = TASK_INTERRUPTIBLE; + schedule(); + set_restore_sigmask(); + + return -ERESTARTNOHAND; +} + +asmlinkage int +sys_sigaction(int sig, const struct old_sigaction __user *act, + struct old_sigaction __user *oact) +{ + struct k_sigaction new_ka, old_ka; + int ret; + + if (act) { + old_sigset_t mask; + if (!access_ok(VERIFY_READ, act, sizeof(*act)) || + __get_user(new_ka.sa.sa_handler, &act->sa_handler) || + __get_user(new_ka.sa.sa_restorer, &act->sa_restorer) || + __get_user(new_ka.sa.sa_flags, &act->sa_flags) || + __get_user(mask, &act->sa_mask)) + return -EFAULT; + siginitset(&new_ka.sa.sa_mask, mask); + } + + ret = do_sigaction(sig, act ? &new_ka : NULL, oact ? &old_ka : NULL); + + if (!ret && oact) { + if (!access_ok(VERIFY_WRITE, oact, sizeof(*oact)) || + __put_user(old_ka.sa.sa_handler, &oact->sa_handler) || + __put_user(old_ka.sa.sa_restorer, &oact->sa_restorer) || + __put_user(old_ka.sa.sa_flags, &oact->sa_flags) || + __put_user(old_ka.sa.sa_mask.sig[0], &oact->sa_mask)) + return -EFAULT; + } + + return ret; +} + +asmlinkage int +sys_sigaltstack(const stack_t __user *uss, stack_t __user *uoss) +{ + return do_sigaltstack(uss, uoss, rdusp()); +} + + +/* + * Do a signal return; undo the signal stack. + * + * Keep the return code on the stack quadword aligned! + * That makes the cache flush below easier. + */ + +struct sigframe +{ + char __user *pretcode; + int sig; + int code; + struct sigcontext __user *psc; + char retcode[8]; + unsigned long extramask[_NSIG_WORDS-1]; + struct sigcontext sc; +}; + +struct rt_sigframe +{ + char __user *pretcode; + int sig; + struct siginfo __user *pinfo; + void __user *puc; + char retcode[8]; + struct siginfo info; + struct ucontext uc; +}; + +#define FPCONTEXT_SIZE 216 +#define uc_fpstate uc_filler[0] +#define uc_formatvec uc_filler[FPCONTEXT_SIZE/4] +#define uc_extra uc_filler[FPCONTEXT_SIZE/4+1] + +#ifdef CONFIG_FPU + +static unsigned char fpu_version; /* version number of fpu, set by setup_frame */ + +static inline int restore_fpu_state(struct sigcontext *sc) +{ + int err = 1; + + if (FPU_IS_EMU) { + /* restore registers */ + memcpy(current->thread.fpcntl, sc->sc_fpcntl, 12); + memcpy(current->thread.fp, sc->sc_fpregs, 24); + return 0; + } + + if (CPU_IS_060 ? sc->sc_fpstate[2] : sc->sc_fpstate[0]) { + /* Verify the frame format. */ + if (!(CPU_IS_060 || CPU_IS_COLDFIRE) && + (sc->sc_fpstate[0] != fpu_version)) + goto out; + if (CPU_IS_020_OR_030) { + if (m68k_fputype & FPU_68881 && + !(sc->sc_fpstate[1] == 0x18 || sc->sc_fpstate[1] == 0xb4)) + goto out; + if (m68k_fputype & FPU_68882 && + !(sc->sc_fpstate[1] == 0x38 || sc->sc_fpstate[1] == 0xd4)) + goto out; + } else if (CPU_IS_040) { + if (!(sc->sc_fpstate[1] == 0x00 || + sc->sc_fpstate[1] == 0x28 || + sc->sc_fpstate[1] == 0x60)) + goto out; + } else if (CPU_IS_060) { + if (!(sc->sc_fpstate[3] == 0x00 || + sc->sc_fpstate[3] == 0x60 || + sc->sc_fpstate[3] == 0xe0)) + goto out; + } else if (CPU_IS_COLDFIRE) { + if (!(sc->sc_fpstate[0] == 0x00 || + sc->sc_fpstate[0] == 0x05 || + sc->sc_fpstate[0] == 0xe5)) + goto out; + } else + goto out; + + if (CPU_IS_COLDFIRE) { + __asm__ volatile ("fmovemd %0,%%fp0-%%fp1\n\t" + "fmovel %1,%%fpcr\n\t" + "fmovel %2,%%fpsr\n\t" + "fmovel %3,%%fpiar" + : /* no outputs */ + : "m" (sc->sc_fpregs[0]), + "m" (sc->sc_fpcntl[0]), + "m" (sc->sc_fpcntl[1]), + "m" (sc->sc_fpcntl[2])); + } else { + __asm__ volatile (".chip 68k/68881\n\t" + "fmovemx %0,%%fp0-%%fp1\n\t" + "fmoveml %1,%%fpcr/%%fpsr/%%fpiar\n\t" + ".chip 68k" + : /* no outputs */ + : "m" (*sc->sc_fpregs), + "m" (*sc->sc_fpcntl)); + } + } + + if (CPU_IS_COLDFIRE) { + __asm__ volatile ("frestore %0" : : "m" (*sc->sc_fpstate)); + } else { + __asm__ volatile (".chip 68k/68881\n\t" + "frestore %0\n\t" + ".chip 68k" + : : "m" (*sc->sc_fpstate)); + } + err = 0; + +out: + return err; +} + +static inline int rt_restore_fpu_state(struct ucontext __user *uc) +{ + unsigned char fpstate[FPCONTEXT_SIZE]; + int context_size = CPU_IS_060 ? 8 : (CPU_IS_COLDFIRE ? 12 : 0); + fpregset_t fpregs; + int err = 1; + + if (FPU_IS_EMU) { + /* restore fpu control register */ + if (__copy_from_user(current->thread.fpcntl, + uc->uc_mcontext.fpregs.f_fpcntl, 12)) + goto out; + /* restore all other fpu register */ + if (__copy_from_user(current->thread.fp, + uc->uc_mcontext.fpregs.f_fpregs, 96)) + goto out; + return 0; + } + + if (__get_user(*(long *)fpstate, (long __user *)&uc->uc_fpstate)) + goto out; + if (CPU_IS_060 ? fpstate[2] : fpstate[0]) { + if (!(CPU_IS_060 || CPU_IS_COLDFIRE)) + context_size = fpstate[1]; + /* Verify the frame format. */ + if (!(CPU_IS_060 || CPU_IS_COLDFIRE) && + (fpstate[0] != fpu_version)) + goto out; + if (CPU_IS_020_OR_030) { + if (m68k_fputype & FPU_68881 && + !(context_size == 0x18 || context_size == 0xb4)) + goto out; + if (m68k_fputype & FPU_68882 && + !(context_size == 0x38 || context_size == 0xd4)) + goto out; + } else if (CPU_IS_040) { + if (!(context_size == 0x00 || + context_size == 0x28 || + context_size == 0x60)) + goto out; + } else if (CPU_IS_060) { + if (!(fpstate[3] == 0x00 || + fpstate[3] == 0x60 || + fpstate[3] == 0xe0)) + goto out; + } else if (CPU_IS_COLDFIRE) { + if (!(fpstate[3] == 0x00 || + fpstate[3] == 0x05 || + fpstate[3] == 0xe5)) + goto out; + } else + goto out; + if (__copy_from_user(&fpregs, &uc->uc_mcontext.fpregs, + sizeof(fpregs))) + goto out; + + if (CPU_IS_COLDFIRE) { + __asm__ volatile ("fmovemd %0,%%fp0-%%fp7\n\t" + "fmovel %1,%%fpcr\n\t" + "fmovel %2,%%fpsr\n\t" + "fmovel %3,%%fpiar" + : /* no outputs */ + : "m" (fpregs.f_fpregs[0]), + "m" (fpregs.f_fpcntl[0]), + "m" (fpregs.f_fpcntl[1]), + "m" (fpregs.f_fpcntl[2])); + } else { + __asm__ volatile (".chip 68k/68881\n\t" + "fmovemx %0,%%fp0-%%fp7\n\t" + "fmoveml %1,%%fpcr/%%fpsr/%%fpiar\n\t" + ".chip 68k" + : /* no outputs */ + : "m" (*fpregs.f_fpregs), + "m" (*fpregs.f_fpcntl)); + } + } + if (context_size && + __copy_from_user(fpstate + 4, (long __user *)&uc->uc_fpstate + 1, + context_size)) + goto out; + + if (CPU_IS_COLDFIRE) { + __asm__ volatile ("frestore %0" : : "m" (*fpstate)); + } else { + __asm__ volatile (".chip 68k/68881\n\t" + "frestore %0\n\t" + ".chip 68k" + : : "m" (*fpstate)); + } + err = 0; + +out: + return err; +} + +/* + * Set up a signal frame. + */ +static inline void save_fpu_state(struct sigcontext *sc, struct pt_regs *regs) +{ + if (FPU_IS_EMU) { + /* save registers */ + memcpy(sc->sc_fpcntl, current->thread.fpcntl, 12); + memcpy(sc->sc_fpregs, current->thread.fp, 24); + return; + } + + if (CPU_IS_COLDFIRE) { + __asm__ volatile ("fsave %0" + : : "m" (*sc->sc_fpstate) : "memory"); + } else { + __asm__ volatile (".chip 68k/68881\n\t" + "fsave %0\n\t" + ".chip 68k" + : : "m" (*sc->sc_fpstate) : "memory"); + } + + if (CPU_IS_060 ? sc->sc_fpstate[2] : sc->sc_fpstate[0]) { + fpu_version = sc->sc_fpstate[0]; + if (CPU_IS_020_OR_030 && + regs->vector >= (VEC_FPBRUC * 4) && + regs->vector <= (VEC_FPNAN * 4)) { + /* Clear pending exception in 68882 idle frame */ + if (*(unsigned short *) sc->sc_fpstate == 0x1f38) + sc->sc_fpstate[0x38] |= 1 << 3; + } + + if (CPU_IS_COLDFIRE) { + __asm__ volatile ("fmovemd %%fp0-%%fp1,%0\n\t" + "fmovel %%fpcr,%1\n\t" + "fmovel %%fpsr,%2\n\t" + "fmovel %%fpiar,%3" + : "=m" (sc->sc_fpregs[0]), + "=m" (sc->sc_fpcntl[0]), + "=m" (sc->sc_fpcntl[1]), + "=m" (sc->sc_fpcntl[2]) + : /* no inputs */ + : "memory"); + } else { + __asm__ volatile (".chip 68k/68881\n\t" + "fmovemx %%fp0-%%fp1,%0\n\t" + "fmoveml %%fpcr/%%fpsr/%%fpiar,%1\n\t" + ".chip 68k" + : "=m" (*sc->sc_fpregs), + "=m" (*sc->sc_fpcntl) + : /* no inputs */ + : "memory"); + } + } +} + +static inline int rt_save_fpu_state(struct ucontext __user *uc, struct pt_regs *regs) +{ + unsigned char fpstate[FPCONTEXT_SIZE]; + int context_size = CPU_IS_060 ? 8 : (CPU_IS_COLDFIRE ? 12 : 0); + int err = 0; + + if (FPU_IS_EMU) { + /* save fpu control register */ + err |= copy_to_user(uc->uc_mcontext.fpregs.f_fpcntl, + current->thread.fpcntl, 12); + /* save all other fpu register */ + err |= copy_to_user(uc->uc_mcontext.fpregs.f_fpregs, + current->thread.fp, 96); + return err; + } + + if (CPU_IS_COLDFIRE) { + __asm__ volatile ("fsave %0" : : "m" (*fpstate) : "memory"); + } else { + __asm__ volatile (".chip 68k/68881\n\t" + "fsave %0\n\t" + ".chip 68k" + : : "m" (*fpstate) : "memory"); + } + + err |= __put_user(*(long *)fpstate, (long __user *)&uc->uc_fpstate); + if (CPU_IS_060 ? fpstate[2] : fpstate[0]) { + fpregset_t fpregs; + if (!(CPU_IS_060 || CPU_IS_COLDFIRE)) + context_size = fpstate[1]; + fpu_version = fpstate[0]; + if (CPU_IS_020_OR_030 && + regs->vector >= (VEC_FPBRUC * 4) && + regs->vector <= (VEC_FPNAN * 4)) { + /* Clear pending exception in 68882 idle frame */ + if (*(unsigned short *) fpstate == 0x1f38) + fpstate[0x38] |= 1 << 3; + } + if (CPU_IS_COLDFIRE) { + __asm__ volatile ("fmovemd %%fp0-%%fp7,%0\n\t" + "fmovel %%fpcr,%1\n\t" + "fmovel %%fpsr,%2\n\t" + "fmovel %%fpiar,%3" + : "=m" (fpregs.f_fpregs[0]), + "=m" (fpregs.f_fpcntl[0]), + "=m" (fpregs.f_fpcntl[1]), + "=m" (fpregs.f_fpcntl[2]) + : /* no inputs */ + : "memory"); + } else { + __asm__ volatile (".chip 68k/68881\n\t" + "fmovemx %%fp0-%%fp7,%0\n\t" + "fmoveml %%fpcr/%%fpsr/%%fpiar,%1\n\t" + ".chip 68k" + : "=m" (*fpregs.f_fpregs), + "=m" (*fpregs.f_fpcntl) + : /* no inputs */ + : "memory"); + } + err |= copy_to_user(&uc->uc_mcontext.fpregs, &fpregs, + sizeof(fpregs)); + } + if (context_size) + err |= copy_to_user((long __user *)&uc->uc_fpstate + 1, fpstate + 4, + context_size); + return err; +} + +#else /* CONFIG_FPU */ + +/* + * For the case with no FPU configured these all do nothing. + */ +static inline int restore_fpu_state(struct sigcontext *sc) +{ + return 0; +} + +static inline int rt_restore_fpu_state(struct ucontext __user *uc) +{ + return 0; +} + +static inline void save_fpu_state(struct sigcontext *sc, struct pt_regs *regs) +{ +} + +static inline int rt_save_fpu_state(struct ucontext __user *uc, struct pt_regs *regs) +{ + return 0; +} + +#endif /* CONFIG_FPU */ + +static int mangle_kernel_stack(struct pt_regs *regs, int formatvec, + void __user *fp) +{ + int fsize = frame_extra_sizes(formatvec >> 12); + if (fsize < 0) { + /* + * user process trying to return with weird frame format + */ +#ifdef DEBUG + printk("user process returning with weird frame format\n"); +#endif + return 1; + } + if (!fsize) { + regs->format = formatvec >> 12; + regs->vector = formatvec & 0xfff; + } else { + struct switch_stack *sw = (struct switch_stack *)regs - 1; + unsigned long buf[fsize / 2]; /* yes, twice as much */ + + /* that'll make sure that expansion won't crap over data */ + if (copy_from_user(buf + fsize / 4, fp, fsize)) + return 1; + + /* point of no return */ + regs->format = formatvec >> 12; + regs->vector = formatvec & 0xfff; +#define frame_offset (sizeof(struct pt_regs)+sizeof(struct switch_stack)) + __asm__ __volatile__ ( +#ifdef CONFIG_COLDFIRE + " movel %0,%/sp\n\t" + " bra ret_from_signal\n" +#else + " movel %0,%/a0\n\t" + " subl %1,%/a0\n\t" /* make room on stack */ + " movel %/a0,%/sp\n\t" /* set stack pointer */ + /* move switch_stack and pt_regs */ + "1: movel %0@+,%/a0@+\n\t" + " dbra %2,1b\n\t" + " lea %/sp@(%c3),%/a0\n\t" /* add offset of fmt */ + " lsrl #2,%1\n\t" + " subql #1,%1\n\t" + /* copy to the gap we'd made */ + "2: movel %4@+,%/a0@+\n\t" + " dbra %1,2b\n\t" + " bral ret_from_signal\n" +#endif + : /* no outputs, it doesn't ever return */ + : "a" (sw), "d" (fsize), "d" (frame_offset/4-1), + "n" (frame_offset), "a" (buf + fsize/4) + : "a0"); +#undef frame_offset + } + return 0; +} + +static inline int +restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *usc, void __user *fp) +{ + int formatvec; + struct sigcontext context; + int err = 0; + + /* Always make any pending restarted system calls return -EINTR */ + current_thread_info()->restart_block.fn = do_no_restart_syscall; + + /* get previous context */ + if (copy_from_user(&context, usc, sizeof(context))) + goto badframe; + + /* restore passed registers */ + regs->d0 = context.sc_d0; + regs->d1 = context.sc_d1; + regs->a0 = context.sc_a0; + regs->a1 = context.sc_a1; + regs->sr = (regs->sr & 0xff00) | (context.sc_sr & 0xff); + regs->pc = context.sc_pc; + regs->orig_d0 = -1; /* disable syscall checks */ + wrusp(context.sc_usp); + formatvec = context.sc_formatvec; + + err = restore_fpu_state(&context); + + if (err || mangle_kernel_stack(regs, formatvec, fp)) + goto badframe; + + return 0; + +badframe: + return 1; +} + +static inline int +rt_restore_ucontext(struct pt_regs *regs, struct switch_stack *sw, + struct ucontext __user *uc) +{ + int temp; + greg_t __user *gregs = uc->uc_mcontext.gregs; + unsigned long usp; + int err; + + /* Always make any pending restarted system calls return -EINTR */ + current_thread_info()->restart_block.fn = do_no_restart_syscall; + + err = __get_user(temp, &uc->uc_mcontext.version); + if (temp != MCONTEXT_VERSION) + goto badframe; + /* restore passed registers */ + err |= __get_user(regs->d0, &gregs[0]); + err |= __get_user(regs->d1, &gregs[1]); + err |= __get_user(regs->d2, &gregs[2]); + err |= __get_user(regs->d3, &gregs[3]); + err |= __get_user(regs->d4, &gregs[4]); + err |= __get_user(regs->d5, &gregs[5]); + err |= __get_user(sw->d6, &gregs[6]); + err |= __get_user(sw->d7, &gregs[7]); + err |= __get_user(regs->a0, &gregs[8]); + err |= __get_user(regs->a1, &gregs[9]); + err |= __get_user(regs->a2, &gregs[10]); + err |= __get_user(sw->a3, &gregs[11]); + err |= __get_user(sw->a4, &gregs[12]); + err |= __get_user(sw->a5, &gregs[13]); + err |= __get_user(sw->a6, &gregs[14]); + err |= __get_user(usp, &gregs[15]); + wrusp(usp); + err |= __get_user(regs->pc, &gregs[16]); + err |= __get_user(temp, &gregs[17]); + regs->sr = (regs->sr & 0xff00) | (temp & 0xff); + regs->orig_d0 = -1; /* disable syscall checks */ + err |= __get_user(temp, &uc->uc_formatvec); + + err |= rt_restore_fpu_state(uc); + + if (err || do_sigaltstack(&uc->uc_stack, NULL, usp) == -EFAULT) + goto badframe; + + if (mangle_kernel_stack(regs, temp, &uc->uc_extra)) + goto badframe; + + return 0; + +badframe: + return 1; +} + +asmlinkage int do_sigreturn(unsigned long __unused) +{ + struct switch_stack *sw = (struct switch_stack *) &__unused; + struct pt_regs *regs = (struct pt_regs *) (sw + 1); + unsigned long usp = rdusp(); + struct sigframe __user *frame = (struct sigframe __user *)(usp - 4); + sigset_t set; + + if (!access_ok(VERIFY_READ, frame, sizeof(*frame))) + goto badframe; + if (__get_user(set.sig[0], &frame->sc.sc_mask) || + (_NSIG_WORDS > 1 && + __copy_from_user(&set.sig[1], &frame->extramask, + sizeof(frame->extramask)))) + goto badframe; + + sigdelsetmask(&set, ~_BLOCKABLE); + current->blocked = set; + recalc_sigpending(); + + if (restore_sigcontext(regs, &frame->sc, frame + 1)) + goto badframe; + return regs->d0; + +badframe: + force_sig(SIGSEGV, current); + return 0; +} + +asmlinkage int do_rt_sigreturn(unsigned long __unused) +{ + struct switch_stack *sw = (struct switch_stack *) &__unused; + struct pt_regs *regs = (struct pt_regs *) (sw + 1); + unsigned long usp = rdusp(); + struct rt_sigframe __user *frame = (struct rt_sigframe __user *)(usp - 4); + sigset_t set; + + if (!access_ok(VERIFY_READ, frame, sizeof(*frame))) + goto badframe; + if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set))) + goto badframe; + + sigdelsetmask(&set, ~_BLOCKABLE); + current->blocked = set; + recalc_sigpending(); + + if (rt_restore_ucontext(regs, sw, &frame->uc)) + goto badframe; + return regs->d0; + +badframe: + force_sig(SIGSEGV, current); + return 0; +} + +static void setup_sigcontext(struct sigcontext *sc, struct pt_regs *regs, + unsigned long mask) +{ + sc->sc_mask = mask; + sc->sc_usp = rdusp(); + sc->sc_d0 = regs->d0; + sc->sc_d1 = regs->d1; + sc->sc_a0 = regs->a0; + sc->sc_a1 = regs->a1; + sc->sc_sr = regs->sr; + sc->sc_pc = regs->pc; + sc->sc_formatvec = regs->format << 12 | regs->vector; + save_a5_state(sc, regs); + save_fpu_state(sc, regs); +} + +static inline int rt_setup_ucontext(struct ucontext __user *uc, struct pt_regs *regs) +{ + struct switch_stack *sw = (struct switch_stack *)regs - 1; + greg_t __user *gregs = uc->uc_mcontext.gregs; + int err = 0; + + err |= __put_user(MCONTEXT_VERSION, &uc->uc_mcontext.version); + err |= __put_user(regs->d0, &gregs[0]); + err |= __put_user(regs->d1, &gregs[1]); + err |= __put_user(regs->d2, &gregs[2]); + err |= __put_user(regs->d3, &gregs[3]); + err |= __put_user(regs->d4, &gregs[4]); + err |= __put_user(regs->d5, &gregs[5]); + err |= __put_user(sw->d6, &gregs[6]); + err |= __put_user(sw->d7, &gregs[7]); + err |= __put_user(regs->a0, &gregs[8]); + err |= __put_user(regs->a1, &gregs[9]); + err |= __put_user(regs->a2, &gregs[10]); + err |= __put_user(sw->a3, &gregs[11]); + err |= __put_user(sw->a4, &gregs[12]); + err |= __put_user(sw->a5, &gregs[13]); + err |= __put_user(sw->a6, &gregs[14]); + err |= __put_user(rdusp(), &gregs[15]); + err |= __put_user(regs->pc, &gregs[16]); + err |= __put_user(regs->sr, &gregs[17]); + err |= __put_user((regs->format << 12) | regs->vector, &uc->uc_formatvec); + err |= rt_save_fpu_state(uc, regs); + return err; +} + +static inline void __user * +get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, size_t frame_size) +{ + unsigned long usp; + + /* Default to using normal stack. */ + usp = rdusp(); + + /* This is the X/Open sanctioned signal stack switching. */ + if (ka->sa.sa_flags & SA_ONSTACK) { + if (!sas_ss_flags(usp)) + usp = current->sas_ss_sp + current->sas_ss_size; + } + return (void __user *)((usp - frame_size) & -8UL); +} + +static int setup_frame (int sig, struct k_sigaction *ka, + sigset_t *set, struct pt_regs *regs) +{ + struct sigframe __user *frame; + int fsize = frame_extra_sizes(regs->format); + struct sigcontext context; + int err = 0; + + if (fsize < 0) { +#ifdef DEBUG + printk ("setup_frame: Unknown frame format %#x\n", + regs->format); +#endif + goto give_sigsegv; + } + + frame = get_sigframe(ka, regs, sizeof(*frame) + fsize); + + if (fsize) + err |= copy_to_user (frame + 1, regs + 1, fsize); + + err |= __put_user((current_thread_info()->exec_domain + && current_thread_info()->exec_domain->signal_invmap + && sig < 32 + ? current_thread_info()->exec_domain->signal_invmap[sig] + : sig), + &frame->sig); + + err |= __put_user(regs->vector, &frame->code); + err |= __put_user(&frame->sc, &frame->psc); + + if (_NSIG_WORDS > 1) + err |= copy_to_user(frame->extramask, &set->sig[1], + sizeof(frame->extramask)); + + setup_sigcontext(&context, regs, set->sig[0]); + err |= copy_to_user (&frame->sc, &context, sizeof(context)); + + /* Set up to return from userspace. */ +#ifdef CONFIG_MMU + err |= __put_user(frame->retcode, &frame->pretcode); + /* moveq #,d0; trap #0 */ + err |= __put_user(0x70004e40 + (__NR_sigreturn << 16), + (long __user *)(frame->retcode)); +#else + err |= __put_user((void *) ret_from_user_signal, &frame->pretcode); +#endif + + if (err) + goto give_sigsegv; + + push_cache ((unsigned long) &frame->retcode); + + /* + * Set up registers for signal handler. All the state we are about + * to destroy is successfully copied to sigframe. + */ + wrusp ((unsigned long) frame); + regs->pc = (unsigned long) ka->sa.sa_handler; + adjustformat(regs); + + /* + * This is subtle; if we build more than one sigframe, all but the + * first one will see frame format 0 and have fsize == 0, so we won't + * screw stkadj. + */ + if (fsize) + regs->stkadj = fsize; + + /* Prepare to skip over the extra stuff in the exception frame. */ + if (regs->stkadj) { + struct pt_regs *tregs = + (struct pt_regs *)((ulong)regs + regs->stkadj); +#ifdef DEBUG + printk("Performing stackadjust=%04x\n", regs->stkadj); +#endif + /* This must be copied with decreasing addresses to + handle overlaps. */ + tregs->vector = 0; + tregs->format = 0; + tregs->pc = regs->pc; + tregs->sr = regs->sr; + } + return 0; + +give_sigsegv: + force_sigsegv(sig, current); + return err; +} + +static int setup_rt_frame (int sig, struct k_sigaction *ka, siginfo_t *info, + sigset_t *set, struct pt_regs *regs) +{ + struct rt_sigframe __user *frame; + int fsize = frame_extra_sizes(regs->format); + int err = 0; + + if (fsize < 0) { +#ifdef DEBUG + printk ("setup_frame: Unknown frame format %#x\n", + regs->format); +#endif + goto give_sigsegv; + } + + frame = get_sigframe(ka, regs, sizeof(*frame)); + + if (fsize) + err |= copy_to_user (&frame->uc.uc_extra, regs + 1, fsize); + + err |= __put_user((current_thread_info()->exec_domain + && current_thread_info()->exec_domain->signal_invmap + && sig < 32 + ? current_thread_info()->exec_domain->signal_invmap[sig] + : sig), + &frame->sig); + err |= __put_user(&frame->info, &frame->pinfo); + err |= __put_user(&frame->uc, &frame->puc); + err |= copy_siginfo_to_user(&frame->info, info); + + /* Create the ucontext. */ + err |= __put_user(0, &frame->uc.uc_flags); + err |= __put_user(NULL, &frame->uc.uc_link); + err |= __put_user((void __user *)current->sas_ss_sp, + &frame->uc.uc_stack.ss_sp); + err |= __put_user(sas_ss_flags(rdusp()), + &frame->uc.uc_stack.ss_flags); + err |= __put_user(current->sas_ss_size, &frame->uc.uc_stack.ss_size); + err |= rt_setup_ucontext(&frame->uc, regs); + err |= copy_to_user (&frame->uc.uc_sigmask, set, sizeof(*set)); + + /* Set up to return from userspace. */ +#ifdef CONFIG_MMU + err |= __put_user(frame->retcode, &frame->pretcode); +#ifdef __mcoldfire__ + /* movel #__NR_rt_sigreturn,d0; trap #0 */ + err |= __put_user(0x203c0000, (long __user *)(frame->retcode + 0)); + err |= __put_user(0x00004e40 + (__NR_rt_sigreturn << 16), + (long __user *)(frame->retcode + 4)); +#else + /* moveq #,d0; notb d0; trap #0 */ + err |= __put_user(0x70004600 + ((__NR_rt_sigreturn ^ 0xff) << 16), + (long __user *)(frame->retcode + 0)); + err |= __put_user(0x4e40, (short __user *)(frame->retcode + 4)); +#endif +#else + err |= __put_user((void *) ret_from_user_rt_signal, &frame->pretcode); +#endif /* CONFIG_MMU */ + + if (err) + goto give_sigsegv; + + push_cache ((unsigned long) &frame->retcode); + + /* + * Set up registers for signal handler. All the state we are about + * to destroy is successfully copied to sigframe. + */ + wrusp ((unsigned long) frame); + regs->pc = (unsigned long) ka->sa.sa_handler; + adjustformat(regs); + + /* + * This is subtle; if we build more than one sigframe, all but the + * first one will see frame format 0 and have fsize == 0, so we won't + * screw stkadj. + */ + if (fsize) + regs->stkadj = fsize; + + /* Prepare to skip over the extra stuff in the exception frame. */ + if (regs->stkadj) { + struct pt_regs *tregs = + (struct pt_regs *)((ulong)regs + regs->stkadj); +#ifdef DEBUG + printk("Performing stackadjust=%04x\n", regs->stkadj); +#endif + /* This must be copied with decreasing addresses to + handle overlaps. */ + tregs->vector = 0; + tregs->format = 0; + tregs->pc = regs->pc; + tregs->sr = regs->sr; + } + return 0; + +give_sigsegv: + force_sigsegv(sig, current); + return err; +} + +static inline void +handle_restart(struct pt_regs *regs, struct k_sigaction *ka, int has_handler) +{ + switch (regs->d0) { + case -ERESTARTNOHAND: + if (!has_handler) + goto do_restart; + regs->d0 = -EINTR; + break; + + case -ERESTART_RESTARTBLOCK: + if (!has_handler) { + regs->d0 = __NR_restart_syscall; + regs->pc -= 2; + break; + } + regs->d0 = -EINTR; + break; + + case -ERESTARTSYS: + if (has_handler && !(ka->sa.sa_flags & SA_RESTART)) { + regs->d0 = -EINTR; + break; + } + /* fallthrough */ + case -ERESTARTNOINTR: + do_restart: + regs->d0 = regs->orig_d0; + regs->pc -= 2; + break; + } +} + +/* + * OK, we're invoking a handler + */ +static void +handle_signal(int sig, struct k_sigaction *ka, siginfo_t *info, + sigset_t *oldset, struct pt_regs *regs) +{ + int err; + /* are we from a system call? */ + if (regs->orig_d0 >= 0) + /* If so, check system call restarting.. */ + handle_restart(regs, ka, 1); + + /* set up the stack frame */ + if (ka->sa.sa_flags & SA_SIGINFO) + err = setup_rt_frame(sig, ka, info, oldset, regs); + else + err = setup_frame(sig, ka, oldset, regs); + + if (err) + return; + + sigorsets(¤t->blocked,¤t->blocked,&ka->sa.sa_mask); + if (!(ka->sa.sa_flags & SA_NODEFER)) + sigaddset(¤t->blocked,sig); + recalc_sigpending(); + + if (test_thread_flag(TIF_DELAYED_TRACE)) { + regs->sr &= ~0x8000; + send_sig(SIGTRAP, current, 1); + } + + clear_thread_flag(TIF_RESTORE_SIGMASK); +} + +/* + * Note that 'init' is a special process: it doesn't get signals it doesn't + * want to handle. Thus you cannot kill init even with a SIGKILL even by + * mistake. + */ +asmlinkage void do_signal(struct pt_regs *regs) +{ + siginfo_t info; + struct k_sigaction ka; + int signr; + sigset_t *oldset; + + current->thread.esp0 = (unsigned long) regs; + + if (test_thread_flag(TIF_RESTORE_SIGMASK)) + oldset = ¤t->saved_sigmask; + else + oldset = ¤t->blocked; + + signr = get_signal_to_deliver(&info, &ka, regs, NULL); + if (signr > 0) { + /* Whee! Actually deliver the signal. */ + handle_signal(signr, &ka, &info, oldset, regs); + return; + } + + /* Did we come from a system call? */ + if (regs->orig_d0 >= 0) + /* Restart the system call - no handlers present */ + handle_restart(regs, NULL, 0); + + /* If there's no signal to deliver, we just restore the saved mask. */ + if (test_thread_flag(TIF_RESTORE_SIGMASK)) { + clear_thread_flag(TIF_RESTORE_SIGMASK); + sigprocmask(SIG_SETMASK, ¤t->saved_sigmask, NULL); + } +} diff --git a/arch/m68k/kernel/signal_mm.c b/arch/m68k/kernel/signal_mm.c deleted file mode 100644 index cb856f9da655..000000000000 --- a/arch/m68k/kernel/signal_mm.c +++ /dev/null @@ -1,1115 +0,0 @@ -/* - * linux/arch/m68k/kernel/signal.c - * - * Copyright (C) 1991, 1992 Linus Torvalds - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ - -/* - * Linux/m68k support by Hamish Macdonald - * - * 68060 fixes by Jesper Skov - * - * 1997-12-01 Modified for POSIX.1b signals by Andreas Schwab - * - * mathemu support by Roman Zippel - * (Note: fpstate in the signal context is completely ignored for the emulator - * and the internal floating point format is put on stack) - */ - -/* - * ++roman (07/09/96): implemented signal stacks (specially for tosemu on - * Atari :-) Current limitation: Only one sigstack can be active at one time. - * If a second signal with SA_ONSTACK set arrives while working on a sigstack, - * SA_ONSTACK is ignored. This behaviour avoids lots of trouble with nested - * signal handlers! - */ - -#include <linux/sched.h> -#include <linux/mm.h> -#include <linux/kernel.h> -#include <linux/signal.h> -#include <linux/syscalls.h> -#include <linux/errno.h> -#include <linux/wait.h> -#include <linux/ptrace.h> -#include <linux/unistd.h> -#include <linux/stddef.h> -#include <linux/highuid.h> -#include <linux/personality.h> -#include <linux/tty.h> -#include <linux/binfmts.h> -#include <linux/module.h> - -#include <asm/setup.h> -#include <asm/uaccess.h> -#include <asm/pgtable.h> -#include <asm/traps.h> -#include <asm/ucontext.h> - -#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP))) - -static const int frame_extra_sizes[16] = { - [1] = -1, /* sizeof(((struct frame *)0)->un.fmt1), */ - [2] = sizeof(((struct frame *)0)->un.fmt2), - [3] = sizeof(((struct frame *)0)->un.fmt3), -#ifdef CONFIG_COLDFIRE - [4] = 0, -#else - [4] = sizeof(((struct frame *)0)->un.fmt4), -#endif - [5] = -1, /* sizeof(((struct frame *)0)->un.fmt5), */ - [6] = -1, /* sizeof(((struct frame *)0)->un.fmt6), */ - [7] = sizeof(((struct frame *)0)->un.fmt7), - [8] = -1, /* sizeof(((struct frame *)0)->un.fmt8), */ - [9] = sizeof(((struct frame *)0)->un.fmt9), - [10] = sizeof(((struct frame *)0)->un.fmta), - [11] = sizeof(((struct frame *)0)->un.fmtb), - [12] = -1, /* sizeof(((struct frame *)0)->un.fmtc), */ - [13] = -1, /* sizeof(((struct frame *)0)->un.fmtd), */ - [14] = -1, /* sizeof(((struct frame *)0)->un.fmte), */ - [15] = -1, /* sizeof(((struct frame *)0)->un.fmtf), */ -}; - -int handle_kernel_fault(struct pt_regs *regs) -{ - const struct exception_table_entry *fixup; - struct pt_regs *tregs; - - /* Are we prepared to handle this kernel fault? */ - fixup = search_exception_tables(regs->pc); - if (!fixup) - return 0; - - /* Create a new four word stack frame, discarding the old one. */ - regs->stkadj = frame_extra_sizes[regs->format]; - tregs = (struct pt_regs *)((long)regs + regs->stkadj); - tregs->vector = regs->vector; -#ifdef CONFIG_COLDFIRE - tregs->format = 4; -#else - tregs->format = 0; -#endif - tregs->pc = fixup->fixup; - tregs->sr = regs->sr; - - return 1; -} - -/* - * Atomically swap in the new signal mask, and wait for a signal. - */ -asmlinkage int -sys_sigsuspend(int unused0, int unused1, old_sigset_t mask) -{ - mask &= _BLOCKABLE; - spin_lock_irq(¤t->sighand->siglock); - current->saved_sigmask = current->blocked; - siginitset(¤t->blocked, mask); - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); - - current->state = TASK_INTERRUPTIBLE; - schedule(); - set_restore_sigmask(); - - return -ERESTARTNOHAND; -} - -asmlinkage int -sys_sigaction(int sig, const struct old_sigaction __user *act, - struct old_sigaction __user *oact) -{ - struct k_sigaction new_ka, old_ka; - int ret; - - if (act) { - old_sigset_t mask; - if (!access_ok(VERIFY_READ, act, sizeof(*act)) || - __get_user(new_ka.sa.sa_handler, &act->sa_handler) || - __get_user(new_ka.sa.sa_restorer, &act->sa_restorer) || - __get_user(new_ka.sa.sa_flags, &act->sa_flags) || - __get_user(mask, &act->sa_mask)) - return -EFAULT; - siginitset(&new_ka.sa.sa_mask, mask); - } - - ret = do_sigaction(sig, act ? &new_ka : NULL, oact ? &old_ka : NULL); - - if (!ret && oact) { - if (!access_ok(VERIFY_WRITE, oact, sizeof(*oact)) || - __put_user(old_ka.sa.sa_handler, &oact->sa_handler) || - __put_user(old_ka.sa.sa_restorer, &oact->sa_restorer) || - __put_user(old_ka.sa.sa_flags, &oact->sa_flags) || - __put_user(old_ka.sa.sa_mask.sig[0], &oact->sa_mask)) - return -EFAULT; - } - - return ret; -} - -asmlinkage int -sys_sigaltstack(const stack_t __user *uss, stack_t __user *uoss) -{ - return do_sigaltstack(uss, uoss, rdusp()); -} - - -/* - * Do a signal return; undo the signal stack. - * - * Keep the return code on the stack quadword aligned! - * That makes the cache flush below easier. - */ - -struct sigframe -{ - char __user *pretcode; - int sig; - int code; - struct sigcontext __user *psc; - char retcode[8]; - unsigned long extramask[_NSIG_WORDS-1]; - struct sigcontext sc; -}; - -struct rt_sigframe -{ - char __user *pretcode; - int sig; - struct siginfo __user *pinfo; - void __user *puc; - char retcode[8]; - struct siginfo info; - struct ucontext uc; -}; - - -static unsigned char fpu_version; /* version number of fpu, set by setup_frame */ - -static inline int restore_fpu_state(struct sigcontext *sc) -{ - int err = 1; - - if (FPU_IS_EMU) { - /* restore registers */ - memcpy(current->thread.fpcntl, sc->sc_fpcntl, 12); - memcpy(current->thread.fp, sc->sc_fpregs, 24); - return 0; - } - - if (CPU_IS_060 ? sc->sc_fpstate[2] : sc->sc_fpstate[0]) { - /* Verify the frame format. */ - if (!(CPU_IS_060 || CPU_IS_COLDFIRE) && - (sc->sc_fpstate[0] != fpu_version)) - goto out; - if (CPU_IS_020_OR_030) { - if (m68k_fputype & FPU_68881 && - !(sc->sc_fpstate[1] == 0x18 || sc->sc_fpstate[1] == 0xb4)) - goto out; - if (m68k_fputype & FPU_68882 && - !(sc->sc_fpstate[1] == 0x38 || sc->sc_fpstate[1] == 0xd4)) - goto out; - } else if (CPU_IS_040) { - if (!(sc->sc_fpstate[1] == 0x00 || - sc->sc_fpstate[1] == 0x28 || - sc->sc_fpstate[1] == 0x60)) - goto out; - } else if (CPU_IS_060) { - if (!(sc->sc_fpstate[3] == 0x00 || - sc->sc_fpstate[3] == 0x60 || - sc->sc_fpstate[3] == 0xe0)) - goto out; - } else if (CPU_IS_COLDFIRE) { - if (!(sc->sc_fpstate[0] == 0x00 || - sc->sc_fpstate[0] == 0x05 || - sc->sc_fpstate[0] == 0xe5)) - goto out; - } else - goto out; - - if (CPU_IS_COLDFIRE) { - __asm__ volatile ("fmovemd %0,%%fp0-%%fp1\n\t" - "fmovel %1,%%fpcr\n\t" - "fmovel %2,%%fpsr\n\t" - "fmovel %3,%%fpiar" - : /* no outputs */ - : "m" (sc->sc_fpregs[0]), - "m" (sc->sc_fpcntl[0]), - "m" (sc->sc_fpcntl[1]), - "m" (sc->sc_fpcntl[2])); - } else { - __asm__ volatile (".chip 68k/68881\n\t" - "fmovemx %0,%%fp0-%%fp1\n\t" - "fmoveml %1,%%fpcr/%%fpsr/%%fpiar\n\t" - ".chip 68k" - : /* no outputs */ - : "m" (*sc->sc_fpregs), - "m" (*sc->sc_fpcntl)); - } - } - - if (CPU_IS_COLDFIRE) { - __asm__ volatile ("frestore %0" : : "m" (*sc->sc_fpstate)); - } else { - __asm__ volatile (".chip 68k/68881\n\t" - "frestore %0\n\t" - ".chip 68k" - : : "m" (*sc->sc_fpstate)); - } - err = 0; - -out: - return err; -} - -#define FPCONTEXT_SIZE 216 -#define uc_fpstate uc_filler[0] -#define uc_formatvec uc_filler[FPCONTEXT_SIZE/4] -#define uc_extra uc_filler[FPCONTEXT_SIZE/4+1] - -static inline int rt_restore_fpu_state(struct ucontext __user *uc) -{ - unsigned char fpstate[FPCONTEXT_SIZE]; - int context_size = CPU_IS_060 ? 8 : (CPU_IS_COLDFIRE ? 12 : 0); - fpregset_t fpregs; - int err = 1; - - if (FPU_IS_EMU) { - /* restore fpu control register */ - if (__copy_from_user(current->thread.fpcntl, - uc->uc_mcontext.fpregs.f_fpcntl, 12)) - goto out; - /* restore all other fpu register */ - if (__copy_from_user(current->thread.fp, - uc->uc_mcontext.fpregs.f_fpregs, 96)) - goto out; - return 0; - } - - if (__get_user(*(long *)fpstate, (long __user *)&uc->uc_fpstate)) - goto out; - if (CPU_IS_060 ? fpstate[2] : fpstate[0]) { - if (!(CPU_IS_060 || CPU_IS_COLDFIRE)) - context_size = fpstate[1]; - /* Verify the frame format. */ - if (!(CPU_IS_060 || CPU_IS_COLDFIRE) && - (fpstate[0] != fpu_version)) - goto out; - if (CPU_IS_020_OR_030) { - if (m68k_fputype & FPU_68881 && - !(context_size == 0x18 || context_size == 0xb4)) - goto out; - if (m68k_fputype & FPU_68882 && - !(context_size == 0x38 || context_size == 0xd4)) - goto out; - } else if (CPU_IS_040) { - if (!(context_size == 0x00 || - context_size == 0x28 || - context_size == 0x60)) - goto out; - } else if (CPU_IS_060) { - if (!(fpstate[3] == 0x00 || - fpstate[3] == 0x60 || - fpstate[3] == 0xe0)) - goto out; - } else if (CPU_IS_COLDFIRE) { - if (!(fpstate[3] == 0x00 || - fpstate[3] == 0x05 || - fpstate[3] == 0xe5)) - goto out; - } else - goto out; - if (__copy_from_user(&fpregs, &uc->uc_mcontext.fpregs, - sizeof(fpregs))) - goto out; - - if (CPU_IS_COLDFIRE) { - __asm__ volatile ("fmovemd %0,%%fp0-%%fp7\n\t" - "fmovel %1,%%fpcr\n\t" - "fmovel %2,%%fpsr\n\t" - "fmovel %3,%%fpiar" - : /* no outputs */ - : "m" (fpregs.f_fpregs[0]), - "m" (fpregs.f_fpcntl[0]), - "m" (fpregs.f_fpcntl[1]), - "m" (fpregs.f_fpcntl[2])); - } else { - __asm__ volatile (".chip 68k/68881\n\t" - "fmovemx %0,%%fp0-%%fp7\n\t" - "fmoveml %1,%%fpcr/%%fpsr/%%fpiar\n\t" - ".chip 68k" - : /* no outputs */ - : "m" (*fpregs.f_fpregs), - "m" (*fpregs.f_fpcntl)); - } - } - if (context_size && - __copy_from_user(fpstate + 4, (long __user *)&uc->uc_fpstate + 1, - context_size)) - goto out; - - if (CPU_IS_COLDFIRE) { - __asm__ volatile ("frestore %0" : : "m" (*fpstate)); - } else { - __asm__ volatile (".chip 68k/68881\n\t" - "frestore %0\n\t" - ".chip 68k" - : : "m" (*fpstate)); - } - err = 0; - -out: - return err; -} - -static int mangle_kernel_stack(struct pt_regs *regs, int formatvec, - void __user *fp) -{ - int fsize = frame_extra_sizes[formatvec >> 12]; - if (fsize < 0) { - /* - * user process trying to return with weird frame format - */ -#ifdef DEBUG - printk("user process returning with weird frame format\n"); -#endif - return 1; - } - if (!fsize) { - regs->format = formatvec >> 12; - regs->vector = formatvec & 0xfff; - } else { - struct switch_stack *sw = (struct switch_stack *)regs - 1; - unsigned long buf[fsize / 2]; /* yes, twice as much */ - - /* that'll make sure that expansion won't crap over data */ - if (copy_from_user(buf + fsize / 4, fp, fsize)) - return 1; - - /* point of no return */ - regs->format = formatvec >> 12; - regs->vector = formatvec & 0xfff; -#define frame_offset (sizeof(struct pt_regs)+sizeof(struct switch_stack)) - __asm__ __volatile__ ( -#ifdef CONFIG_COLDFIRE - " movel %0,%/sp\n\t" - " bra ret_from_signal\n" -#else - " movel %0,%/a0\n\t" - " subl %1,%/a0\n\t" /* make room on stack */ - " movel %/a0,%/sp\n\t" /* set stack pointer */ - /* move switch_stack and pt_regs */ - "1: movel %0@+,%/a0@+\n\t" - " dbra %2,1b\n\t" - " lea %/sp@(%c3),%/a0\n\t" /* add offset of fmt */ - " lsrl #2,%1\n\t" - " subql #1,%1\n\t" - /* copy to the gap we'd made */ - "2: movel %4@+,%/a0@+\n\t" - " dbra %1,2b\n\t" - " bral ret_from_signal\n" -#endif - : /* no outputs, it doesn't ever return */ - : "a" (sw), "d" (fsize), "d" (frame_offset/4-1), - "n" (frame_offset), "a" (buf + fsize/4) - : "a0"); -#undef frame_offset - } - return 0; -} - -static inline int -restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *usc, void __user *fp) -{ - int formatvec; - struct sigcontext context; - int err; - - /* Always make any pending restarted system calls return -EINTR */ - current_thread_info()->restart_block.fn = do_no_restart_syscall; - - /* get previous context */ - if (copy_from_user(&context, usc, sizeof(context))) - goto badframe; - - /* restore passed registers */ - regs->d0 = context.sc_d0; - regs->d1 = context.sc_d1; - regs->a0 = context.sc_a0; - regs->a1 = context.sc_a1; - regs->sr = (regs->sr & 0xff00) | (context.sc_sr & 0xff); - regs->pc = context.sc_pc; - regs->orig_d0 = -1; /* disable syscall checks */ - wrusp(context.sc_usp); - formatvec = context.sc_formatvec; - - err = restore_fpu_state(&context); - - if (err || mangle_kernel_stack(regs, formatvec, fp)) - goto badframe; - - return 0; - -badframe: - return 1; -} - -static inline int -rt_restore_ucontext(struct pt_regs *regs, struct switch_stack *sw, - struct ucontext __user *uc) -{ - int temp; - greg_t __user *gregs = uc->uc_mcontext.gregs; - unsigned long usp; - int err; - - /* Always make any pending restarted system calls return -EINTR */ - current_thread_info()->restart_block.fn = do_no_restart_syscall; - - err = __get_user(temp, &uc->uc_mcontext.version); - if (temp != MCONTEXT_VERSION) - goto badframe; - /* restore passed registers */ - err |= __get_user(regs->d0, &gregs[0]); - err |= __get_user(regs->d1, &gregs[1]); - err |= __get_user(regs->d2, &gregs[2]); - err |= __get_user(regs->d3, &gregs[3]); - err |= __get_user(regs->d4, &gregs[4]); - err |= __get_user(regs->d5, &gregs[5]); - err |= __get_user(sw->d6, &gregs[6]); - err |= __get_user(sw->d7, &gregs[7]); - err |= __get_user(regs->a0, &gregs[8]); - err |= __get_user(regs->a1, &gregs[9]); - err |= __get_user(regs->a2, &gregs[10]); - err |= __get_user(sw->a3, &gregs[11]); - err |= __get_user(sw->a4, &gregs[12]); - err |= __get_user(sw->a5, &gregs[13]); - err |= __get_user(sw->a6, &gregs[14]); - err |= __get_user(usp, &gregs[15]); - wrusp(usp); - err |= __get_user(regs->pc, &gregs[16]); - err |= __get_user(temp, &gregs[17]); - regs->sr = (regs->sr & 0xff00) | (temp & 0xff); - regs->orig_d0 = -1; /* disable syscall checks */ - err |= __get_user(temp, &uc->uc_formatvec); - - err |= rt_restore_fpu_state(uc); - - if (err || do_sigaltstack(&uc->uc_stack, NULL, usp) == -EFAULT) - goto badframe; - - if (mangle_kernel_stack(regs, temp, &uc->uc_extra)) - goto badframe; - - return 0; - -badframe: - return 1; -} - -asmlinkage int do_sigreturn(unsigned long __unused) -{ - struct switch_stack *sw = (struct switch_stack *) &__unused; - struct pt_regs *regs = (struct pt_regs *) (sw + 1); - unsigned long usp = rdusp(); - struct sigframe __user *frame = (struct sigframe __user *)(usp - 4); - sigset_t set; - - if (!access_ok(VERIFY_READ, frame, sizeof(*frame))) - goto badframe; - if (__get_user(set.sig[0], &frame->sc.sc_mask) || - (_NSIG_WORDS > 1 && - __copy_from_user(&set.sig[1], &frame->extramask, - sizeof(frame->extramask)))) - goto badframe; - - sigdelsetmask(&set, ~_BLOCKABLE); - current->blocked = set; - recalc_sigpending(); - - if (restore_sigcontext(regs, &frame->sc, frame + 1)) - goto badframe; - return regs->d0; - -badframe: - force_sig(SIGSEGV, current); - return 0; -} - -asmlinkage int do_rt_sigreturn(unsigned long __unused) -{ - struct switch_stack *sw = (struct switch_stack *) &__unused; - struct pt_regs *regs = (struct pt_regs *) (sw + 1); - unsigned long usp = rdusp(); - struct rt_sigframe __user *frame = (struct rt_sigframe __user *)(usp - 4); - sigset_t set; - - if (!access_ok(VERIFY_READ, frame, sizeof(*frame))) - goto badframe; - if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set))) - goto badframe; - - sigdelsetmask(&set, ~_BLOCKABLE); - current->blocked = set; - recalc_sigpending(); - - if (rt_restore_ucontext(regs, sw, &frame->uc)) - goto badframe; - return regs->d0; - -badframe: - force_sig(SIGSEGV, current); - return 0; -} - -/* - * Set up a signal frame. - */ - -static inline void save_fpu_state(struct sigcontext *sc, struct pt_regs *regs) -{ - if (FPU_IS_EMU) { - /* save registers */ - memcpy(sc->sc_fpcntl, current->thread.fpcntl, 12); - memcpy(sc->sc_fpregs, current->thread.fp, 24); - return; - } - - if (CPU_IS_COLDFIRE) { - __asm__ volatile ("fsave %0" - : : "m" (*sc->sc_fpstate) : "memory"); - } else { - __asm__ volatile (".chip 68k/68881\n\t" - "fsave %0\n\t" - ".chip 68k" - : : "m" (*sc->sc_fpstate) : "memory"); - } - - if (CPU_IS_060 ? sc->sc_fpstate[2] : sc->sc_fpstate[0]) { - fpu_version = sc->sc_fpstate[0]; - if (CPU_IS_020_OR_030 && - regs->vector >= (VEC_FPBRUC * 4) && - regs->vector <= (VEC_FPNAN * 4)) { - /* Clear pending exception in 68882 idle frame */ - if (*(unsigned short *) sc->sc_fpstate == 0x1f38) - sc->sc_fpstate[0x38] |= 1 << 3; - } - - if (CPU_IS_COLDFIRE) { - __asm__ volatile ("fmovemd %%fp0-%%fp1,%0\n\t" - "fmovel %%fpcr,%1\n\t" - "fmovel %%fpsr,%2\n\t" - "fmovel %%fpiar,%3" - : "=m" (sc->sc_fpregs[0]), - "=m" (sc->sc_fpcntl[0]), - "=m" (sc->sc_fpcntl[1]), - "=m" (sc->sc_fpcntl[2]) - : /* no inputs */ - : "memory"); - } else { - __asm__ volatile (".chip 68k/68881\n\t" - "fmovemx %%fp0-%%fp1,%0\n\t" - "fmoveml %%fpcr/%%fpsr/%%fpiar,%1\n\t" - ".chip 68k" - : "=m" (*sc->sc_fpregs), - "=m" (*sc->sc_fpcntl) - : /* no inputs */ - : "memory"); - } - } -} - -static inline int rt_save_fpu_state(struct ucontext __user *uc, struct pt_regs *regs) -{ - unsigned char fpstate[FPCONTEXT_SIZE]; - int context_size = CPU_IS_060 ? 8 : (CPU_IS_COLDFIRE ? 12 : 0); - int err = 0; - - if (FPU_IS_EMU) { - /* save fpu control register */ - err |= copy_to_user(uc->uc_mcontext.fpregs.f_fpcntl, - current->thread.fpcntl, 12); - /* save all other fpu register */ - err |= copy_to_user(uc->uc_mcontext.fpregs.f_fpregs, - current->thread.fp, 96); - return err; - } - - if (CPU_IS_COLDFIRE) { - __asm__ volatile ("fsave %0" : : "m" (*fpstate) : "memory"); - } else { - __asm__ volatile (".chip 68k/68881\n\t" - "fsave %0\n\t" - ".chip 68k" - : : "m" (*fpstate) : "memory"); - } - - err |= __put_user(*(long *)fpstate, (long __user *)&uc->uc_fpstate); - if (CPU_IS_060 ? fpstate[2] : fpstate[0]) { - fpregset_t fpregs; - if (!(CPU_IS_060 || CPU_IS_COLDFIRE)) - context_size = fpstate[1]; - fpu_version = fpstate[0]; - if (CPU_IS_020_OR_030 && - regs->vector >= (VEC_FPBRUC * 4) && - regs->vector <= (VEC_FPNAN * 4)) { - /* Clear pending exception in 68882 idle frame */ - if (*(unsigned short *) fpstate == 0x1f38) - fpstate[0x38] |= 1 << 3; - } - if (CPU_IS_COLDFIRE) { - __asm__ volatile ("fmovemd %%fp0-%%fp7,%0\n\t" - "fmovel %%fpcr,%1\n\t" - "fmovel %%fpsr,%2\n\t" - "fmovel %%fpiar,%3" - : "=m" (fpregs.f_fpregs[0]), - "=m" (fpregs.f_fpcntl[0]), - "=m" (fpregs.f_fpcntl[1]), - "=m" (fpregs.f_fpcntl[2]) - : /* no inputs */ - : "memory"); - } else { - __asm__ volatile (".chip 68k/68881\n\t" - "fmovemx %%fp0-%%fp7,%0\n\t" - "fmoveml %%fpcr/%%fpsr/%%fpiar,%1\n\t" - ".chip 68k" - : "=m" (*fpregs.f_fpregs), - "=m" (*fpregs.f_fpcntl) - : /* no inputs */ - : "memory"); - } - err |= copy_to_user(&uc->uc_mcontext.fpregs, &fpregs, - sizeof(fpregs)); - } - if (context_size) - err |= copy_to_user((long __user *)&uc->uc_fpstate + 1, fpstate + 4, - context_size); - return err; -} - -static void setup_sigcontext(struct sigcontext *sc, struct pt_regs *regs, - unsigned long mask) -{ - sc->sc_mask = mask; - sc->sc_usp = rdusp(); - sc->sc_d0 = regs->d0; - sc->sc_d1 = regs->d1; - sc->sc_a0 = regs->a0; - sc->sc_a1 = regs->a1; - sc->sc_sr = regs->sr; - sc->sc_pc = regs->pc; - sc->sc_formatvec = regs->format << 12 | regs->vector; - save_fpu_state(sc, regs); -} - -static inline int rt_setup_ucontext(struct ucontext __user *uc, struct pt_regs *regs) -{ - struct switch_stack *sw = (struct switch_stack *)regs - 1; - greg_t __user *gregs = uc->uc_mcontext.gregs; - int err = 0; - - err |= __put_user(MCONTEXT_VERSION, &uc->uc_mcontext.version); - err |= __put_user(regs->d0, &gregs[0]); - err |= __put_user(regs->d1, &gregs[1]); - err |= __put_user(regs->d2, &gregs[2]); - err |= __put_user(regs->d3, &gregs[3]); - err |= __put_user(regs->d4, &gregs[4]); - err |= __put_user(regs->d5, &gregs[5]); - err |= __put_user(sw->d6, &gregs[6]); - err |= __put_user(sw->d7, &gregs[7]); - err |= __put_user(regs->a0, &gregs[8]); - err |= __put_user(regs->a1, &gregs[9]); - err |= __put_user(regs->a2, &gregs[10]); - err |= __put_user(sw->a3, &gregs[11]); - err |= __put_user(sw->a4, &gregs[12]); - err |= __put_user(sw->a5, &gregs[13]); - err |= __put_user(sw->a6, &gregs[14]); - err |= __put_user(rdusp(), &gregs[15]); - err |= __put_user(regs->pc, &gregs[16]); - err |= __put_user(regs->sr, &gregs[17]); - err |= __put_user((regs->format << 12) | regs->vector, &uc->uc_formatvec); - err |= rt_save_fpu_state(uc, regs); - return err; -} - -static inline void push_cache (unsigned long vaddr) -{ - /* - * Using the old cache_push_v() was really a big waste. - * - * What we are trying to do is to flush 8 bytes to ram. - * Flushing 2 cache lines of 16 bytes is much cheaper than - * flushing 1 or 2 pages, as previously done in - * cache_push_v(). - * Jes - */ - if (CPU_IS_040) { - unsigned long temp; - - __asm__ __volatile__ (".chip 68040\n\t" - "nop\n\t" - "ptestr (%1)\n\t" - "movec %%mmusr,%0\n\t" - ".chip 68k" - : "=r" (temp) - : "a" (vaddr)); - - temp &= PAGE_MASK; - temp |= vaddr & ~PAGE_MASK; - - __asm__ __volatile__ (".chip 68040\n\t" - "nop\n\t" - "cpushl %%bc,(%0)\n\t" - ".chip 68k" - : : "a" (temp)); - } - else if (CPU_IS_060) { - unsigned long temp; - __asm__ __volatile__ (".chip 68060\n\t" - "plpar (%0)\n\t" - ".chip 68k" - : "=a" (temp) - : "0" (vaddr)); - __asm__ __volatile__ (".chip 68060\n\t" - "cpushl %%bc,(%0)\n\t" - ".chip 68k" - : : "a" (temp)); - } else if (!CPU_IS_COLDFIRE) { - /* - * 68030/68020 have no writeback cache; - * still need to clear icache. - * Note that vaddr is guaranteed to be long word aligned. - */ - unsigned long temp; - asm volatile ("movec %%cacr,%0" : "=r" (temp)); - temp += 4; - asm volatile ("movec %0,%%caar\n\t" - "movec %1,%%cacr" - : : "r" (vaddr), "r" (temp)); - asm volatile ("movec %0,%%caar\n\t" - "movec %1,%%cacr" - : : "r" (vaddr + 4), "r" (temp)); - } -} - -static inline void __user * -get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, size_t frame_size) -{ - unsigned long usp; - - /* Default to using normal stack. */ - usp = rdusp(); - - /* This is the X/Open sanctioned signal stack switching. */ - if (ka->sa.sa_flags & SA_ONSTACK) { - if (!sas_ss_flags(usp)) - usp = current->sas_ss_sp + current->sas_ss_size; - } - return (void __user *)((usp - frame_size) & -8UL); -} - -static int setup_frame (int sig, struct k_sigaction *ka, - sigset_t *set, struct pt_regs *regs) -{ - struct sigframe __user *frame; - int fsize = frame_extra_sizes[regs->format]; - struct sigcontext context; - int err = 0; - - if (fsize < 0) { -#ifdef DEBUG - printk ("setup_frame: Unknown frame format %#x\n", - regs->format); -#endif - goto give_sigsegv; - } - - frame = get_sigframe(ka, regs, sizeof(*frame) + fsize); - - if (fsize) - err |= copy_to_user (frame + 1, regs + 1, fsize); - - err |= __put_user((current_thread_info()->exec_domain - && current_thread_info()->exec_domain->signal_invmap - && sig < 32 - ? current_thread_info()->exec_domain->signal_invmap[sig] - : sig), - &frame->sig); - - err |= __put_user(regs->vector, &frame->code); - err |= __put_user(&frame->sc, &frame->psc); - - if (_NSIG_WORDS > 1) - err |= copy_to_user(frame->extramask, &set->sig[1], - sizeof(frame->extramask)); - - setup_sigcontext(&context, regs, set->sig[0]); - err |= copy_to_user (&frame->sc, &context, sizeof(context)); - - /* Set up to return from userspace. */ - err |= __put_user(frame->retcode, &frame->pretcode); - /* moveq #,d0; trap #0 */ - err |= __put_user(0x70004e40 + (__NR_sigreturn << 16), - (long __user *)(frame->retcode)); - - if (err) - goto give_sigsegv; - - push_cache ((unsigned long) &frame->retcode); - - /* - * Set up registers for signal handler. All the state we are about - * to destroy is successfully copied to sigframe. - */ - wrusp ((unsigned long) frame); - regs->pc = (unsigned long) ka->sa.sa_handler; - - /* - * This is subtle; if we build more than one sigframe, all but the - * first one will see frame format 0 and have fsize == 0, so we won't - * screw stkadj. - */ - if (fsize) - regs->stkadj = fsize; - - /* Prepare to skip over the extra stuff in the exception frame. */ - if (regs->stkadj) { - struct pt_regs *tregs = - (struct pt_regs *)((ulong)regs + regs->stkadj); -#ifdef DEBUG - printk("Performing stackadjust=%04x\n", regs->stkadj); -#endif - /* This must be copied with decreasing addresses to - handle overlaps. */ - tregs->vector = 0; - tregs->format = 0; - tregs->pc = regs->pc; - tregs->sr = regs->sr; - } - return 0; - -give_sigsegv: - force_sigsegv(sig, current); - return err; -} - -static int setup_rt_frame (int sig, struct k_sigaction *ka, siginfo_t *info, - sigset_t *set, struct pt_regs *regs) -{ - struct rt_sigframe __user *frame; - int fsize = frame_extra_sizes[regs->format]; - int err = 0; - - if (fsize < 0) { -#ifdef DEBUG - printk ("setup_frame: Unknown frame format %#x\n", - regs->format); -#endif - goto give_sigsegv; - } - - frame = get_sigframe(ka, regs, sizeof(*frame)); - - if (fsize) - err |= copy_to_user (&frame->uc.uc_extra, regs + 1, fsize); - - err |= __put_user((current_thread_info()->exec_domain - && current_thread_info()->exec_domain->signal_invmap - && sig < 32 - ? current_thread_info()->exec_domain->signal_invmap[sig] - : sig), - &frame->sig); - err |= __put_user(&frame->info, &frame->pinfo); - err |= __put_user(&frame->uc, &frame->puc); - err |= copy_siginfo_to_user(&frame->info, info); - - /* Create the ucontext. */ - err |= __put_user(0, &frame->uc.uc_flags); - err |= __put_user(NULL, &frame->uc.uc_link); - err |= __put_user((void __user *)current->sas_ss_sp, - &frame->uc.uc_stack.ss_sp); - err |= __put_user(sas_ss_flags(rdusp()), - &frame->uc.uc_stack.ss_flags); - err |= __put_user(current->sas_ss_size, &frame->uc.uc_stack.ss_size); - err |= rt_setup_ucontext(&frame->uc, regs); - err |= copy_to_user (&frame->uc.uc_sigmask, set, sizeof(*set)); - - /* Set up to return from userspace. */ - err |= __put_user(frame->retcode, &frame->pretcode); -#ifdef __mcoldfire__ - /* movel #__NR_rt_sigreturn,d0; trap #0 */ - err |= __put_user(0x203c0000, (long __user *)(frame->retcode + 0)); - err |= __put_user(0x00004e40 + (__NR_rt_sigreturn << 16), - (long __user *)(frame->retcode + 4)); -#else - /* moveq #,d0; notb d0; trap #0 */ - err |= __put_user(0x70004600 + ((__NR_rt_sigreturn ^ 0xff) << 16), - (long __user *)(frame->retcode + 0)); - err |= __put_user(0x4e40, (short __user *)(frame->retcode + 4)); -#endif - - if (err) - goto give_sigsegv; - - push_cache ((unsigned long) &frame->retcode); - - /* - * Set up registers for signal handler. All the state we are about - * to destroy is successfully copied to sigframe. - */ - wrusp ((unsigned long) frame); - regs->pc = (unsigned long) ka->sa.sa_handler; - - /* - * This is subtle; if we build more than one sigframe, all but the - * first one will see frame format 0 and have fsize == 0, so we won't - * screw stkadj. - */ - if (fsize) - regs->stkadj = fsize; - - /* Prepare to skip over the extra stuff in the exception frame. */ - if (regs->stkadj) { - struct pt_regs *tregs = - (struct pt_regs *)((ulong)regs + regs->stkadj); -#ifdef DEBUG - printk("Performing stackadjust=%04x\n", regs->stkadj); -#endif - /* This must be copied with decreasing addresses to - handle overlaps. */ - tregs->vector = 0; - tregs->format = 0; - tregs->pc = regs->pc; - tregs->sr = regs->sr; - } - return 0; - -give_sigsegv: - force_sigsegv(sig, current); - return err; -} - -static inline void -handle_restart(struct pt_regs *regs, struct k_sigaction *ka, int has_handler) -{ - switch (regs->d0) { - case -ERESTARTNOHAND: - if (!has_handler) - goto do_restart; - regs->d0 = -EINTR; - break; - - case -ERESTART_RESTARTBLOCK: - if (!has_handler) { - regs->d0 = __NR_restart_syscall; - regs->pc -= 2; - break; - } - regs->d0 = -EINTR; - break; - - case -ERESTARTSYS: - if (has_handler && !(ka->sa.sa_flags & SA_RESTART)) { - regs->d0 = -EINTR; - break; - } - /* fallthrough */ - case -ERESTARTNOINTR: - do_restart: - regs->d0 = regs->orig_d0; - regs->pc -= 2; - break; - } -} - -void ptrace_signal_deliver(struct pt_regs *regs, void *cookie) -{ - if (regs->orig_d0 < 0) - return; - switch (regs->d0) { - case -ERESTARTNOHAND: - case -ERESTARTSYS: - case -ERESTARTNOINTR: - regs->d0 = regs->orig_d0; - regs->orig_d0 = -1; - regs->pc -= 2; - break; - } -} - -/* - * OK, we're invoking a handler - */ -static void -handle_signal(int sig, struct k_sigaction *ka, siginfo_t *info, - sigset_t *oldset, struct pt_regs *regs) -{ - int err; - /* are we from a system call? */ - if (regs->orig_d0 >= 0) - /* If so, check system call restarting.. */ - handle_restart(regs, ka, 1); - - /* set up the stack frame */ - if (ka->sa.sa_flags & SA_SIGINFO) - err = setup_rt_frame(sig, ka, info, oldset, regs); - else - err = setup_frame(sig, ka, oldset, regs); - - if (err) - return; - - sigorsets(¤t->blocked,¤t->blocked,&ka->sa.sa_mask); - if (!(ka->sa.sa_flags & SA_NODEFER)) - sigaddset(¤t->blocked,sig); - recalc_sigpending(); - - if (test_thread_flag(TIF_DELAYED_TRACE)) { - regs->sr &= ~0x8000; - send_sig(SIGTRAP, current, 1); - } - - clear_thread_flag(TIF_RESTORE_SIGMASK); -} - -/* - * Note that 'init' is a special process: it doesn't get signals it doesn't - * want to handle. Thus you cannot kill init even with a SIGKILL even by - * mistake. - */ -asmlinkage void do_signal(struct pt_regs *regs) -{ - siginfo_t info; - struct k_sigaction ka; - int signr; - sigset_t *oldset; - - current->thread.esp0 = (unsigned long) regs; - - if (test_thread_flag(TIF_RESTORE_SIGMASK)) - oldset = ¤t->saved_sigmask; - else - oldset = ¤t->blocked; - - signr = get_signal_to_deliver(&info, &ka, regs, NULL); - if (signr > 0) { - /* Whee! Actually deliver the signal. */ - handle_signal(signr, &ka, &info, oldset, regs); - return; - } - - /* Did we come from a system call? */ - if (regs->orig_d0 >= 0) - /* Restart the system call - no handlers present */ - handle_restart(regs, NULL, 0); - - /* If there's no signal to deliver, we just restore the saved mask. */ - if (test_thread_flag(TIF_RESTORE_SIGMASK)) { - clear_thread_flag(TIF_RESTORE_SIGMASK); - sigprocmask(SIG_SETMASK, ¤t->saved_sigmask, NULL); - } -} diff --git a/arch/m68k/kernel/signal_no.c b/arch/m68k/kernel/signal_no.c deleted file mode 100644 index 36a81bb6835a..000000000000 --- a/arch/m68k/kernel/signal_no.c +++ /dev/null @@ -1,765 +0,0 @@ -/* - * linux/arch/m68knommu/kernel/signal.c - * - * Copyright (C) 1991, 1992 Linus Torvalds - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ - -/* - * Linux/m68k support by Hamish Macdonald - * - * 68060 fixes by Jesper Skov - * - * 1997-12-01 Modified for POSIX.1b signals by Andreas Schwab - * - * mathemu support by Roman Zippel - * (Note: fpstate in the signal context is completely ignored for the emulator - * and the internal floating point format is put on stack) - */ - -/* - * ++roman (07/09/96): implemented signal stacks (specially for tosemu on - * Atari :-) Current limitation: Only one sigstack can be active at one time. - * If a second signal with SA_ONSTACK set arrives while working on a sigstack, - * SA_ONSTACK is ignored. This behaviour avoids lots of trouble with nested - * signal handlers! - */ - -#include <linux/sched.h> -#include <linux/mm.h> -#include <linux/kernel.h> -#include <linux/signal.h> -#include <linux/syscalls.h> -#include <linux/errno.h> -#include <linux/wait.h> -#include <linux/ptrace.h> -#include <linux/unistd.h> -#include <linux/stddef.h> -#include <linux/highuid.h> -#include <linux/tty.h> -#include <linux/personality.h> -#include <linux/binfmts.h> - -#include <asm/setup.h> -#include <asm/uaccess.h> -#include <asm/pgtable.h> -#include <asm/traps.h> -#include <asm/ucontext.h> - -#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP))) - -void ret_from_user_signal(void); -void ret_from_user_rt_signal(void); - -/* - * Atomically swap in the new signal mask, and wait for a signal. - */ -asmlinkage int -sys_sigsuspend(int unused0, int unused1, old_sigset_t mask) -{ - mask &= _BLOCKABLE; - spin_lock_irq(¤t->sighand->siglock); - current->saved_sigmask = current->blocked; - siginitset(¤t->blocked, mask); - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); - - current->state = TASK_INTERRUPTIBLE; - schedule(); - set_restore_sigmask(); - - return -ERESTARTNOHAND; -} - -asmlinkage int -sys_sigaction(int sig, const struct old_sigaction __user *act, - struct old_sigaction __user *oact) -{ - struct k_sigaction new_ka, old_ka; - int ret; - - if (act) { - old_sigset_t mask; - if (!access_ok(VERIFY_READ, act, sizeof(*act)) || - __get_user(new_ka.sa.sa_handler, &act->sa_handler) || - __get_user(new_ka.sa.sa_restorer, &act->sa_restorer) || - __get_user(new_ka.sa.sa_flags, &act->sa_flags) || - __get_user(mask, &act->sa_mask)) - return -EFAULT; - siginitset(&new_ka.sa.sa_mask, mask); - } - - ret = do_sigaction(sig, act ? &new_ka : NULL, oact ? &old_ka : NULL); - - if (!ret && oact) { - if (!access_ok(VERIFY_WRITE, oact, sizeof(*oact)) || - __put_user(old_ka.sa.sa_handler, &oact->sa_handler) || - __put_user(old_ka.sa.sa_restorer, &oact->sa_restorer) || - __put_user(old_ka.sa.sa_flags, &oact->sa_flags) || - __put_user(old_ka.sa.sa_mask.sig[0], &oact->sa_mask)) - return -EFAULT; - } - - return ret; -} - -asmlinkage int -sys_sigaltstack(const stack_t __user *uss, stack_t __user *uoss) -{ - return do_sigaltstack(uss, uoss, rdusp()); -} - - -/* - * Do a signal return; undo the signal stack. - * - * Keep the return code on the stack quadword aligned! - * That makes the cache flush below easier. - */ - -struct sigframe -{ - char __user *pretcode; - int sig; - int code; - struct sigcontext __user *psc; - char retcode[8]; - unsigned long extramask[_NSIG_WORDS-1]; - struct sigcontext sc; -}; - -struct rt_sigframe -{ - char __user *pretcode; - int sig; - struct siginfo __user *pinfo; - void __user *puc; - char retcode[8]; - struct siginfo info; - struct ucontext uc; -}; - -#ifdef CONFIG_FPU - -static unsigned char fpu_version = 0; /* version number of fpu, set by setup_frame */ - -static inline int restore_fpu_state(struct sigcontext *sc) -{ - int err = 1; - - if (FPU_IS_EMU) { - /* restore registers */ - memcpy(current->thread.fpcntl, sc->sc_fpcntl, 12); - memcpy(current->thread.fp, sc->sc_fpregs, 24); - return 0; - } - - if (sc->sc_fpstate[0]) { - /* Verify the frame format. */ - if (sc->sc_fpstate[0] != fpu_version) - goto out; - - __asm__ volatile (".chip 68k/68881\n\t" - "fmovemx %0,%%fp0-%%fp1\n\t" - "fmoveml %1,%%fpcr/%%fpsr/%%fpiar\n\t" - ".chip 68k" - : /* no outputs */ - : "m" (*sc->sc_fpregs), "m" (*sc->sc_fpcntl)); - } - __asm__ volatile (".chip 68k/68881\n\t" - "frestore %0\n\t" - ".chip 68k" : : "m" (*sc->sc_fpstate)); - err = 0; - -out: - return err; -} - -#define FPCONTEXT_SIZE 216 -#define uc_fpstate uc_filler[0] -#define uc_formatvec uc_filler[FPCONTEXT_SIZE/4] -#define uc_extra uc_filler[FPCONTEXT_SIZE/4+1] - -static inline int rt_restore_fpu_state(struct ucontext __user *uc) -{ - unsigned char fpstate[FPCONTEXT_SIZE]; - int context_size = 0; - fpregset_t fpregs; - int err = 1; - - if (FPU_IS_EMU) { - /* restore fpu control register */ - if (__copy_from_user(current->thread.fpcntl, - uc->uc_mcontext.fpregs.f_fpcntl, 12)) - goto out; - /* restore all other fpu register */ - if (__copy_from_user(current->thread.fp, - uc->uc_mcontext.fpregs.f_fpregs, 96)) - goto out; - return 0; - } - - if (__get_user(*(long *)fpstate, (long __user *)&uc->uc_fpstate)) - goto out; - if (fpstate[0]) { - context_size = fpstate[1]; - - /* Verify the frame format. */ - if (fpstate[0] != fpu_version) - goto out; - if (__copy_from_user(&fpregs, &uc->uc_mcontext.fpregs, - sizeof(fpregs))) - goto out; - __asm__ volatile (".chip 68k/68881\n\t" - "fmovemx %0,%%fp0-%%fp7\n\t" - "fmoveml %1,%%fpcr/%%fpsr/%%fpiar\n\t" - ".chip 68k" - : /* no outputs */ - : "m" (*fpregs.f_fpregs), - "m" (*fpregs.f_fpcntl)); - } - if (context_size && - __copy_from_user(fpstate + 4, (long __user *)&uc->uc_fpstate + 1, - context_size)) - goto out; - __asm__ volatile (".chip 68k/68881\n\t" - "frestore %0\n\t" - ".chip 68k" : : "m" (*fpstate)); - err = 0; - -out: - return err; -} - -#endif - -static inline int -restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *usc, void __user *fp, - int *pd0) -{ - int formatvec; - struct sigcontext context; - int err = 0; - - /* Always make any pending restarted system calls return -EINTR */ - current_thread_info()->restart_block.fn = do_no_restart_syscall; - - /* get previous context */ - if (copy_from_user(&context, usc, sizeof(context))) - goto badframe; - - /* restore passed registers */ - regs->d1 = context.sc_d1; - regs->a0 = context.sc_a0; - regs->a1 = context.sc_a1; - ((struct switch_stack *)regs - 1)->a5 = context.sc_a5; - regs->sr = (regs->sr & 0xff00) | (context.sc_sr & 0xff); - regs->pc = context.sc_pc; - regs->orig_d0 = -1; /* disable syscall checks */ - wrusp(context.sc_usp); - formatvec = context.sc_formatvec; - regs->format = formatvec >> 12; - regs->vector = formatvec & 0xfff; - -#ifdef CONFIG_FPU - err = restore_fpu_state(&context); -#endif - - *pd0 = context.sc_d0; - return err; - -badframe: - return 1; -} - -static inline int -rt_restore_ucontext(struct pt_regs *regs, struct switch_stack *sw, - struct ucontext __user *uc, int *pd0) -{ - int temp; - greg_t __user *gregs = uc->uc_mcontext.gregs; - unsigned long usp; - int err; - - /* Always make any pending restarted system calls return -EINTR */ - current_thread_info()->restart_block.fn = do_no_restart_syscall; - - err = __get_user(temp, &uc->uc_mcontext.version); - if (temp != MCONTEXT_VERSION) - goto badframe; - /* restore passed registers */ - err |= __get_user(regs->d0, &gregs[0]); - err |= __get_user(regs->d1, &gregs[1]); - err |= __get_user(regs->d2, &gregs[2]); - err |= __get_user(regs->d3, &gregs[3]); - err |= __get_user(regs->d4, &gregs[4]); - err |= __get_user(regs->d5, &gregs[5]); - err |= __get_user(sw->d6, &gregs[6]); - err |= __get_user(sw->d7, &gregs[7]); - err |= __get_user(regs->a0, &gregs[8]); - err |= __get_user(regs->a1, &gregs[9]); - err |= __get_user(regs->a2, &gregs[10]); - err |= __get_user(sw->a3, &gregs[11]); - err |= __get_user(sw->a4, &gregs[12]); - err |= __get_user(sw->a5, &gregs[13]); - err |= __get_user(sw->a6, &gregs[14]); - err |= __get_user(usp, &gregs[15]); - wrusp(usp); - err |= __get_user(regs->pc, &gregs[16]); - err |= __get_user(temp, &gregs[17]); - regs->sr = (regs->sr & 0xff00) | (temp & 0xff); - regs->orig_d0 = -1; /* disable syscall checks */ - regs->format = temp >> 12; - regs->vector = temp & 0xfff; - - if (do_sigaltstack(&uc->uc_stack, NULL, usp) == -EFAULT) - goto badframe; - - *pd0 = regs->d0; - return err; - -badframe: - return 1; -} - -asmlinkage int do_sigreturn(unsigned long __unused) -{ - struct switch_stack *sw = (struct switch_stack *) &__unused; - struct pt_regs *regs = (struct pt_regs *) (sw + 1); - unsigned long usp = rdusp(); - struct sigframe __user *frame = (struct sigframe __user *)(usp - 4); - sigset_t set; - int d0; - - if (!access_ok(VERIFY_READ, frame, sizeof(*frame))) - goto badframe; - if (__get_user(set.sig[0], &frame->sc.sc_mask) || - (_NSIG_WORDS > 1 && - __copy_from_user(&set.sig[1], &frame->extramask, - sizeof(frame->extramask)))) - goto badframe; - - sigdelsetmask(&set, ~_BLOCKABLE); - spin_lock_irq(¤t->sighand->siglock); - current->blocked = set; - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); - - if (restore_sigcontext(regs, &frame->sc, frame + 1, &d0)) - goto badframe; - return d0; - -badframe: - force_sig(SIGSEGV, current); - return 0; -} - -asmlinkage int do_rt_sigreturn(unsigned long __unused) -{ - struct switch_stack *sw = (struct switch_stack *) &__unused; - struct pt_regs *regs = (struct pt_regs *) (sw + 1); - unsigned long usp = rdusp(); - struct rt_sigframe __user *frame = (struct rt_sigframe __user *)(usp - 4); - sigset_t set; - int d0; - - if (!access_ok(VERIFY_READ, frame, sizeof(*frame))) - goto badframe; - if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set))) - goto badframe; - - sigdelsetmask(&set, ~_BLOCKABLE); - spin_lock_irq(¤t->sighand->siglock); - current->blocked = set; - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); - - if (rt_restore_ucontext(regs, sw, &frame->uc, &d0)) - goto badframe; - return d0; - -badframe: - force_sig(SIGSEGV, current); - return 0; -} - -#ifdef CONFIG_FPU -/* - * Set up a signal frame. - */ - -static inline void save_fpu_state(struct sigcontext *sc, struct pt_regs *regs) -{ - if (FPU_IS_EMU) { - /* save registers */ - memcpy(sc->sc_fpcntl, current->thread.fpcntl, 12); - memcpy(sc->sc_fpregs, current->thread.fp, 24); - return; - } - - __asm__ volatile (".chip 68k/68881\n\t" - "fsave %0\n\t" - ".chip 68k" - : : "m" (*sc->sc_fpstate) : "memory"); - - if (sc->sc_fpstate[0]) { - fpu_version = sc->sc_fpstate[0]; - __asm__ volatile (".chip 68k/68881\n\t" - "fmovemx %%fp0-%%fp1,%0\n\t" - "fmoveml %%fpcr/%%fpsr/%%fpiar,%1\n\t" - ".chip 68k" - : "=m" (*sc->sc_fpregs), - "=m" (*sc->sc_fpcntl) - : /* no inputs */ - : "memory"); - } -} - -static inline int rt_save_fpu_state(struct ucontext __user *uc, struct pt_regs *regs) -{ - unsigned char fpstate[FPCONTEXT_SIZE]; - int context_size = 0; - int err = 0; - - if (FPU_IS_EMU) { - /* save fpu control register */ - err |= copy_to_user(uc->uc_mcontext.fpregs.f_pcntl, - current->thread.fpcntl, 12); - /* save all other fpu register */ - err |= copy_to_user(uc->uc_mcontext.fpregs.f_fpregs, - current->thread.fp, 96); - return err; - } - - __asm__ volatile (".chip 68k/68881\n\t" - "fsave %0\n\t" - ".chip 68k" - : : "m" (*fpstate) : "memory"); - - err |= __put_user(*(long *)fpstate, (long __user *)&uc->uc_fpstate); - if (fpstate[0]) { - fpregset_t fpregs; - context_size = fpstate[1]; - fpu_version = fpstate[0]; - __asm__ volatile (".chip 68k/68881\n\t" - "fmovemx %%fp0-%%fp7,%0\n\t" - "fmoveml %%fpcr/%%fpsr/%%fpiar,%1\n\t" - ".chip 68k" - : "=m" (*fpregs.f_fpregs), - "=m" (*fpregs.f_fpcntl) - : /* no inputs */ - : "memory"); - err |= copy_to_user(&uc->uc_mcontext.fpregs, &fpregs, - sizeof(fpregs)); - } - if (context_size) - err |= copy_to_user((long __user *)&uc->uc_fpstate + 1, fpstate + 4, - context_size); - return err; -} - -#endif - -static void setup_sigcontext(struct sigcontext *sc, struct pt_regs *regs, - unsigned long mask) -{ - sc->sc_mask = mask; - sc->sc_usp = rdusp(); - sc->sc_d0 = regs->d0; - sc->sc_d1 = regs->d1; - sc->sc_a0 = regs->a0; - sc->sc_a1 = regs->a1; - sc->sc_a5 = ((struct switch_stack *)regs - 1)->a5; - sc->sc_sr = regs->sr; - sc->sc_pc = regs->pc; - sc->sc_formatvec = regs->format << 12 | regs->vector; -#ifdef CONFIG_FPU - save_fpu_state(sc, regs); -#endif -} - -static inline int rt_setup_ucontext(struct ucontext __user *uc, struct pt_regs *regs) -{ - struct switch_stack *sw = (struct switch_stack *)regs - 1; - greg_t __user *gregs = uc->uc_mcontext.gregs; - int err = 0; - - err |= __put_user(MCONTEXT_VERSION, &uc->uc_mcontext.version); - err |= __put_user(regs->d0, &gregs[0]); - err |= __put_user(regs->d1, &gregs[1]); - err |= __put_user(regs->d2, &gregs[2]); - err |= __put_user(regs->d3, &gregs[3]); - err |= __put_user(regs->d4, &gregs[4]); - err |= __put_user(regs->d5, &gregs[5]); - err |= __put_user(sw->d6, &gregs[6]); - err |= __put_user(sw->d7, &gregs[7]); - err |= __put_user(regs->a0, &gregs[8]); - err |= __put_user(regs->a1, &gregs[9]); - err |= __put_user(regs->a2, &gregs[10]); - err |= __put_user(sw->a3, &gregs[11]); - err |= __put_user(sw->a4, &gregs[12]); - err |= __put_user(sw->a5, &gregs[13]); - err |= __put_user(sw->a6, &gregs[14]); - err |= __put_user(rdusp(), &gregs[15]); - err |= __put_user(regs->pc, &gregs[16]); - err |= __put_user(regs->sr, &gregs[17]); -#ifdef CONFIG_FPU - err |= rt_save_fpu_state(uc, regs); -#endif - return err; -} - -static inline void __user * -get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, size_t frame_size) -{ - unsigned long usp; - - /* Default to using normal stack. */ - usp = rdusp(); - - /* This is the X/Open sanctioned signal stack switching. */ - if (ka->sa.sa_flags & SA_ONSTACK) { - if (!sas_ss_flags(usp)) - usp = current->sas_ss_sp + current->sas_ss_size; - } - return (void __user *)((usp - frame_size) & -8UL); -} - -static int setup_frame (int sig, struct k_sigaction *ka, - sigset_t *set, struct pt_regs *regs) -{ - struct sigframe __user *frame; - struct sigcontext context; - int err = 0; - - frame = get_sigframe(ka, regs, sizeof(*frame)); - - err |= __put_user((current_thread_info()->exec_domain - && current_thread_info()->exec_domain->signal_invmap - && sig < 32 - ? current_thread_info()->exec_domain->signal_invmap[sig] - : sig), - &frame->sig); - - err |= __put_user(regs->vector, &frame->code); - err |= __put_user(&frame->sc, &frame->psc); - - if (_NSIG_WORDS > 1) - err |= copy_to_user(frame->extramask, &set->sig[1], - sizeof(frame->extramask)); - - setup_sigcontext(&context, regs, set->sig[0]); - err |= copy_to_user (&frame->sc, &context, sizeof(context)); - - /* Set up to return from userspace. */ - err |= __put_user((void *) ret_from_user_signal, &frame->pretcode); - - if (err) - goto give_sigsegv; - - /* Set up registers for signal handler */ - wrusp ((unsigned long) frame); - regs->pc = (unsigned long) ka->sa.sa_handler; - ((struct switch_stack *)regs - 1)->a5 = current->mm->start_data; - regs->format = 0x4; /*set format byte to make stack appear modulo 4 - which it will be when doing the rte */ - -adjust_stack: - /* Prepare to skip over the extra stuff in the exception frame. */ - if (regs->stkadj) { - struct pt_regs *tregs = - (struct pt_regs *)((ulong)regs + regs->stkadj); -#if defined(DEBUG) - printk(KERN_DEBUG "Performing stackadjust=%04x\n", regs->stkadj); -#endif - /* This must be copied with decreasing addresses to - handle overlaps. */ - tregs->vector = 0; - tregs->format = 0; - tregs->pc = regs->pc; - tregs->sr = regs->sr; - } - return err; - -give_sigsegv: - force_sigsegv(sig, current); - goto adjust_stack; -} - -static int setup_rt_frame (int sig, struct k_sigaction *ka, siginfo_t *info, - sigset_t *set, struct pt_regs *regs) -{ - struct rt_sigframe __user *frame; - int err = 0; - - frame = get_sigframe(ka, regs, sizeof(*frame)); - - err |= __put_user((current_thread_info()->exec_domain - && current_thread_info()->exec_domain->signal_invmap - && sig < 32 - ? current_thread_info()->exec_domain->signal_invmap[sig] - : sig), - &frame->sig); - err |= __put_user(&frame->info, &frame->pinfo); - err |= __put_user(&frame->uc, &frame->puc); - err |= copy_siginfo_to_user(&frame->info, info); - - /* Create the ucontext. */ - err |= __put_user(0, &frame->uc.uc_flags); - err |= __put_user(NULL, &frame->uc.uc_link); - err |= __put_user((void __user *)current->sas_ss_sp, - &frame->uc.uc_stack.ss_sp); - err |= __put_user(sas_ss_flags(rdusp()), - &frame->uc.uc_stack.ss_flags); - err |= __put_user(current->sas_ss_size, &frame->uc.uc_stack.ss_size); - err |= rt_setup_ucontext(&frame->uc, regs); - err |= copy_to_user (&frame->uc.uc_sigmask, set, sizeof(*set)); - - /* Set up to return from userspace. */ - err |= __put_user((void *) ret_from_user_rt_signal, &frame->pretcode); - - if (err) - goto give_sigsegv; - - /* Set up registers for signal handler */ - wrusp ((unsigned long) frame); - regs->pc = (unsigned long) ka->sa.sa_handler; - ((struct switch_stack *)regs - 1)->a5 = current->mm->start_data; - regs->format = 0x4; /*set format byte to make stack appear modulo 4 - which it will be when doing the rte */ - -adjust_stack: - /* Prepare to skip over the extra stuff in the exception frame. */ - if (regs->stkadj) { - struct pt_regs *tregs = - (struct pt_regs *)((ulong)regs + regs->stkadj); -#if defined(DEBUG) - printk(KERN_DEBUG "Performing stackadjust=%04x\n", regs->stkadj); -#endif - /* This must be copied with decreasing addresses to - handle overlaps. */ - tregs->vector = 0; - tregs->format = 0; - tregs->pc = regs->pc; - tregs->sr = regs->sr; - } - return err; - -give_sigsegv: - force_sigsegv(sig, current); - goto adjust_stack; -} - -static inline void -handle_restart(struct pt_regs *regs, struct k_sigaction *ka, int has_handler) -{ - switch (regs->d0) { - case -ERESTARTNOHAND: - if (!has_handler) - goto do_restart; - regs->d0 = -EINTR; - break; - - case -ERESTART_RESTARTBLOCK: - if (!has_handler) { - regs->d0 = __NR_restart_syscall; - regs->pc -= 2; - break; - } - regs->d0 = -EINTR; - break; - - case -ERESTARTSYS: - if (has_handler && !(ka->sa.sa_flags & SA_RESTART)) { - regs->d0 = -EINTR; - break; - } - /* fallthrough */ - case -ERESTARTNOINTR: - do_restart: - regs->d0 = regs->orig_d0; - regs->pc -= 2; - break; - } -} - -/* - * OK, we're invoking a handler - */ -static void -handle_signal(int sig, struct k_sigaction *ka, siginfo_t *info, - sigset_t *oldset, struct pt_regs *regs) -{ - int err; - /* are we from a system call? */ - if (regs->orig_d0 >= 0) - /* If so, check system call restarting.. */ - handle_restart(regs, ka, 1); - - /* set up the stack frame */ - if (ka->sa.sa_flags & SA_SIGINFO) - err = setup_rt_frame(sig, ka, info, oldset, regs); - else - err = setup_frame(sig, ka, oldset, regs); - - if (err) - return; - - spin_lock_irq(¤t->sighand->siglock); - sigorsets(¤t->blocked,¤t->blocked,&ka->sa.sa_mask); - if (!(ka->sa.sa_flags & SA_NODEFER)) - sigaddset(¤t->blocked,sig); - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); - - clear_thread_flag(TIF_RESTORE_SIGMASK); -} - -/* - * Note that 'init' is a special process: it doesn't get signals it doesn't - * want to handle. Thus you cannot kill init even with a SIGKILL even by - * mistake. - */ -asmlinkage void do_signal(struct pt_regs *regs) -{ - struct k_sigaction ka; - siginfo_t info; - int signr; - sigset_t *oldset; - - /* - * We want the common case to go fast, which - * is why we may in certain cases get here from - * kernel mode. Just return without doing anything - * if so. - */ - if (!user_mode(regs)) - return; - - if (test_thread_flag(TIF_RESTORE_SIGMASK)) - oldset = ¤t->saved_sigmask; - else - oldset = ¤t->blocked; - - signr = get_signal_to_deliver(&info, &ka, regs, NULL); - if (signr > 0) { - /* Whee! Actually deliver the signal. */ - handle_signal(signr, &ka, &info, oldset, regs); - return; - } - - /* Did we come from a system call? */ - if (regs->orig_d0 >= 0) { - /* Restart the system call - no handlers present */ - handle_restart(regs, NULL, 0); - } - - /* If there's no signal to deliver, we just restore the saved mask. */ - if (test_thread_flag(TIF_RESTORE_SIGMASK)) { - clear_thread_flag(TIF_RESTORE_SIGMASK); - sigprocmask(SIG_SETMASK, ¤t->saved_sigmask, NULL); - } -} diff --git a/arch/m68k/mm/fault.c b/arch/m68k/mm/fault.c index 6b020a8461e7..aeebbb7b30f0 100644 --- a/arch/m68k/mm/fault.c +++ b/arch/m68k/mm/fault.c @@ -72,7 +72,8 @@ int do_page_fault(struct pt_regs *regs, unsigned long address, { struct mm_struct *mm = current->mm; struct vm_area_struct * vma; - int write, fault; + int fault; + unsigned int flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE; #ifdef DEBUG printk ("do page fault:\nregs->sr=%#x, regs->pc=%#lx, address=%#lx, %ld, %p\n", @@ -87,6 +88,7 @@ int do_page_fault(struct pt_regs *regs, unsigned long address, if (in_atomic() || !mm) goto no_context; +retry: down_read(&mm->mmap_sem); vma = find_vma(mm, address); @@ -117,14 +119,13 @@ good_area: #ifdef DEBUG printk("do_page_fault: good_area\n"); #endif - write = 0; switch (error_code & 3) { default: /* 3: write, present */ /* fall through */ case 2: /* write, not present */ if (!(vma->vm_flags & VM_WRITE)) goto acc_err; - write++; + flags |= FAULT_FLAG_WRITE; break; case 1: /* read, present */ goto acc_err; @@ -139,10 +140,14 @@ good_area: * the fault. */ - fault = handle_mm_fault(mm, vma, address, write ? FAULT_FLAG_WRITE : 0); + fault = handle_mm_fault(mm, vma, address, flags); #ifdef DEBUG printk("handle_mm_fault returns %d\n",fault); #endif + + if ((fault & VM_FAULT_RETRY) && fatal_signal_pending(current)) + return 0; + if (unlikely(fault & VM_FAULT_ERROR)) { if (fault & VM_FAULT_OOM) goto out_of_memory; @@ -150,10 +155,31 @@ good_area: goto bus_err; BUG(); } - if (fault & VM_FAULT_MAJOR) - current->maj_flt++; - else - current->min_flt++; + + /* + * Major/minor page fault accounting is only done on the + * initial attempt. If we go through a retry, it is extremely + * likely that the page will be found in page cache at that point. + */ + if (flags & FAULT_FLAG_ALLOW_RETRY) { + if (fault & VM_FAULT_MAJOR) + current->maj_flt++; + else + current->min_flt++; + if (fault & VM_FAULT_RETRY) { + /* Clear FAULT_FLAG_ALLOW_RETRY to avoid any risk + * of starvation. */ + flags &= ~FAULT_FLAG_ALLOW_RETRY; + + /* + * No need to up_read(&mm->mmap_sem) as we would + * have already released it in __lock_page_or_retry + * in mm/filemap.c. + */ + + goto retry; + } + } up_read(&mm->mmap_sem); return 0; diff --git a/arch/m68k/platform/5206/Makefile b/arch/m68k/platform/5206/Makefile deleted file mode 100644 index b5db05625cfa..000000000000 --- a/arch/m68k/platform/5206/Makefile +++ /dev/null @@ -1,18 +0,0 @@ -# -# Makefile for the m68knommu linux kernel. -# - -# -# If you want to play with the HW breakpoints then you will -# need to add define this, which will give you a stack backtrace -# on the console port whenever a DBG interrupt occurs. You have to -# set up you HW breakpoints to trigger a DBG interrupt: -# -# ccflags-y := -DTRAP_DBG_INTERRUPT -# asflags-y := -DTRAP_DBG_INTERRUPT -# - -asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 - -obj-y := config.o gpio.o - diff --git a/arch/m68k/platform/5206/gpio.c b/arch/m68k/platform/5206/gpio.c deleted file mode 100644 index b9ab4a120f28..000000000000 --- a/arch/m68k/platform/5206/gpio.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Coldfire generic GPIO support - * - * (C) Copyright 2009, Steven King <[email protected]> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. -*/ - -#include <linux/kernel.h> -#include <linux/init.h> - -#include <asm/coldfire.h> -#include <asm/mcfsim.h> -#include <asm/mcfgpio.h> - -static struct mcf_gpio_chip mcf_gpio_chips[] = { - { - .gpio_chip = { - .label = "PP", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFSIM_PADDR, - .podr = (void __iomem *) MCFSIM_PADAT, - .ppdr = (void __iomem *) MCFSIM_PADAT, - }, -}; - -static int __init mcf_gpio_init(void) -{ - unsigned i = 0; - while (i < ARRAY_SIZE(mcf_gpio_chips)) - (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]); - return 0; -} - -core_initcall(mcf_gpio_init); diff --git a/arch/m68k/platform/520x/Makefile b/arch/m68k/platform/520x/Makefile deleted file mode 100644 index ad3f4e5a57ce..000000000000 --- a/arch/m68k/platform/520x/Makefile +++ /dev/null @@ -1,17 +0,0 @@ -# -# Makefile for the M5208 specific file. -# - -# -# If you want to play with the HW breakpoints then you will -# need to add define this, which will give you a stack backtrace -# on the console port whenever a DBG interrupt occurs. You have to -# set up you HW breakpoints to trigger a DBG interrupt: -# -# ccflags-y := -DTRAP_DBG_INTERRUPT -# asflags-y := -DTRAP_DBG_INTERRUPT -# - -asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 - -obj-y := config.o gpio.o diff --git a/arch/m68k/platform/520x/gpio.c b/arch/m68k/platform/520x/gpio.c deleted file mode 100644 index 9bcc3e4b60c5..000000000000 --- a/arch/m68k/platform/520x/gpio.c +++ /dev/null @@ -1,175 +0,0 @@ -/* - * Coldfire generic GPIO support - * - * (C) Copyright 2009, Steven King <[email protected]> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. -*/ - -#include <linux/kernel.h> -#include <linux/init.h> - -#include <asm/coldfire.h> -#include <asm/mcfsim.h> -#include <asm/mcfgpio.h> - -static struct mcf_gpio_chip mcf_gpio_chips[] = { - { - .gpio_chip = { - .label = "PIRQ", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFEPORT_EPDDR, - .podr = (void __iomem *) MCFEPORT_EPDR, - .ppdr = (void __iomem *) MCFEPORT_EPPDR, - }, - { - .gpio_chip = { - .label = "CS", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 9, - .ngpio = 3, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_CS, - .podr = (void __iomem *) MCFGPIO_PODR_CS, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_CS, - .setr = (void __iomem *) MCFGPIO_PPDSDR_CS, - .clrr = (void __iomem *) MCFGPIO_PCLRR_CS, - }, - { - .gpio_chip = { - .label = "FECI2C", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 16, - .ngpio = 4, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_FECI2C, - .podr = (void __iomem *) MCFGPIO_PODR_FECI2C, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C, - .setr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C, - .clrr = (void __iomem *) MCFGPIO_PCLRR_FECI2C, - }, - { - .gpio_chip = { - .label = "QSPI", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 24, - .ngpio = 4, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_QSPI, - .podr = (void __iomem *) MCFGPIO_PODR_QSPI, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_QSPI, - .setr = (void __iomem *) MCFGPIO_PPDSDR_QSPI, - .clrr = (void __iomem *) MCFGPIO_PCLRR_QSPI, - }, - { - .gpio_chip = { - .label = "TIMER", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 32, - .ngpio = 4, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_TIMER, - .podr = (void __iomem *) MCFGPIO_PODR_TIMER, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_TIMER, - .setr = (void __iomem *) MCFGPIO_PPDSDR_TIMER, - .clrr = (void __iomem *) MCFGPIO_PCLRR_TIMER, - }, - { - .gpio_chip = { - .label = "UART", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 40, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_UART, - .podr = (void __iomem *) MCFGPIO_PODR_UART, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_UART, - .setr = (void __iomem *) MCFGPIO_PPDSDR_UART, - .clrr = (void __iomem *) MCFGPIO_PCLRR_UART, - }, - { - .gpio_chip = { - .label = "FECH", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 48, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_FECH, - .podr = (void __iomem *) MCFGPIO_PODR_FECH, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECH, - .setr = (void __iomem *) MCFGPIO_PPDSDR_FECH, - .clrr = (void __iomem *) MCFGPIO_PCLRR_FECH, - }, - { - .gpio_chip = { - .label = "FECL", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 56, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_FECL, - .podr = (void __iomem *) MCFGPIO_PODR_FECL, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECL, - .setr = (void __iomem *) MCFGPIO_PPDSDR_FECL, - .clrr = (void __iomem *) MCFGPIO_PCLRR_FECL, - }, -}; - -static int __init mcf_gpio_init(void) -{ - unsigned i = 0; - while (i < ARRAY_SIZE(mcf_gpio_chips)) - (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]); - return 0; -} - -core_initcall(mcf_gpio_init); diff --git a/arch/m68k/platform/523x/Makefile b/arch/m68k/platform/523x/Makefile deleted file mode 100644 index c04b8f71c88c..000000000000 --- a/arch/m68k/platform/523x/Makefile +++ /dev/null @@ -1,17 +0,0 @@ -# -# Makefile for the m68knommu linux kernel. -# - -# -# If you want to play with the HW breakpoints then you will -# need to add define this, which will give you a stack backtrace -# on the console port whenever a DBG interrupt occurs. You have to -# set up you HW breakpoints to trigger a DBG interrupt: -# -# ccflags-y := -DTRAP_DBG_INTERRUPT -# asflags-y := -DTRAP_DBG_INTERRUPT -# - -asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 - -obj-y := config.o gpio.o diff --git a/arch/m68k/platform/523x/gpio.c b/arch/m68k/platform/523x/gpio.c deleted file mode 100644 index 327ebf142c8e..000000000000 --- a/arch/m68k/platform/523x/gpio.c +++ /dev/null @@ -1,284 +0,0 @@ -/* - * Coldfire generic GPIO support - * - * (C) Copyright 2009, Steven King <[email protected]> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. -*/ - -#include <linux/kernel.h> -#include <linux/init.h> - -#include <asm/coldfire.h> -#include <asm/mcfsim.h> -#include <asm/mcfgpio.h> - -static struct mcf_gpio_chip mcf_gpio_chips[] = { - { - .gpio_chip = { - .label = "PIRQ", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value, - .base = 1, - .ngpio = 7, - }, - .pddr = (void __iomem *) MCFEPORT_EPDDR, - .podr = (void __iomem *) MCFEPORT_EPDR, - .ppdr = (void __iomem *) MCFEPORT_EPPDR, - }, - { - .gpio_chip = { - .label = "ADDR", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 13, - .ngpio = 3, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_ADDR, - .podr = (void __iomem *) MCFGPIO_PODR_ADDR, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_ADDR, - .setr = (void __iomem *) MCFGPIO_PPDSDR_ADDR, - .clrr = (void __iomem *) MCFGPIO_PCLRR_ADDR, - }, - { - .gpio_chip = { - .label = "DATAH", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 16, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_DATAH, - .podr = (void __iomem *) MCFGPIO_PODR_DATAH, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_DATAH, - .setr = (void __iomem *) MCFGPIO_PPDSDR_DATAH, - .clrr = (void __iomem *) MCFGPIO_PCLRR_DATAH, - }, - { - .gpio_chip = { - .label = "DATAL", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 24, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_DATAL, - .podr = (void __iomem *) MCFGPIO_PODR_DATAL, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_DATAL, - .setr = (void __iomem *) MCFGPIO_PPDSDR_DATAL, - .clrr = (void __iomem *) MCFGPIO_PCLRR_DATAL, - }, - { - .gpio_chip = { - .label = "BUSCTL", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 32, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_BUSCTL, - .podr = (void __iomem *) MCFGPIO_PODR_BUSCTL, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL, - .setr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL, - .clrr = (void __iomem *) MCFGPIO_PCLRR_BUSCTL, - }, - { - .gpio_chip = { - .label = "BS", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 40, - .ngpio = 4, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_BS, - .podr = (void __iomem *) MCFGPIO_PODR_BS, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BS, - .setr = (void __iomem *) MCFGPIO_PPDSDR_BS, - .clrr = (void __iomem *) MCFGPIO_PCLRR_BS, - }, - { - .gpio_chip = { - .label = "CS", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 49, - .ngpio = 7, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_CS, - .podr = (void __iomem *) MCFGPIO_PODR_CS, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_CS, - .setr = (void __iomem *) MCFGPIO_PPDSDR_CS, - .clrr = (void __iomem *) MCFGPIO_PCLRR_CS, - }, - { - .gpio_chip = { - .label = "SDRAM", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 56, - .ngpio = 6, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_SDRAM, - .podr = (void __iomem *) MCFGPIO_PODR_SDRAM, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_SDRAM, - .setr = (void __iomem *) MCFGPIO_PPDSDR_SDRAM, - .clrr = (void __iomem *) MCFGPIO_PCLRR_SDRAM, - }, - { - .gpio_chip = { - .label = "FECI2C", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 64, - .ngpio = 4, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_FECI2C, - .podr = (void __iomem *) MCFGPIO_PODR_FECI2C, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C, - .setr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C, - .clrr = (void __iomem *) MCFGPIO_PCLRR_FECI2C, - }, - { - .gpio_chip = { - .label = "UARTH", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 72, - .ngpio = 2, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_UARTH, - .podr = (void __iomem *) MCFGPIO_PODR_UARTH, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_UARTH, - .setr = (void __iomem *) MCFGPIO_PPDSDR_UARTH, - .clrr = (void __iomem *) MCFGPIO_PCLRR_UARTH, - }, - { - .gpio_chip = { - .label = "UARTL", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 80, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_UARTL, - .podr = (void __iomem *) MCFGPIO_PODR_UARTL, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_UARTL, - .setr = (void __iomem *) MCFGPIO_PPDSDR_UARTL, - .clrr = (void __iomem *) MCFGPIO_PCLRR_UARTL, - }, - { - .gpio_chip = { - .label = "QSPI", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 88, - .ngpio = 5, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_QSPI, - .podr = (void __iomem *) MCFGPIO_PODR_QSPI, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_QSPI, - .setr = (void __iomem *) MCFGPIO_PPDSDR_QSPI, - .clrr = (void __iomem *) MCFGPIO_PCLRR_QSPI, - }, - { - .gpio_chip = { - .label = "TIMER", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 96, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_TIMER, - .podr = (void __iomem *) MCFGPIO_PODR_TIMER, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_TIMER, - .setr = (void __iomem *) MCFGPIO_PPDSDR_TIMER, - .clrr = (void __iomem *) MCFGPIO_PCLRR_TIMER, - }, - { - .gpio_chip = { - .label = "ETPU", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 104, - .ngpio = 3, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_ETPU, - .podr = (void __iomem *) MCFGPIO_PODR_ETPU, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_ETPU, - .setr = (void __iomem *) MCFGPIO_PPDSDR_ETPU, - .clrr = (void __iomem *) MCFGPIO_PCLRR_ETPU, - }, -}; - -static int __init mcf_gpio_init(void) -{ - unsigned i = 0; - while (i < ARRAY_SIZE(mcf_gpio_chips)) - (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]); - return 0; -} - -core_initcall(mcf_gpio_init); diff --git a/arch/m68k/platform/5249/Makefile b/arch/m68k/platform/5249/Makefile deleted file mode 100644 index 4bed30fd0073..000000000000 --- a/arch/m68k/platform/5249/Makefile +++ /dev/null @@ -1,18 +0,0 @@ -# -# Makefile for the m68knommu linux kernel. -# - -# -# If you want to play with the HW breakpoints then you will -# need to add define this, which will give you a stack backtrace -# on the console port whenever a DBG interrupt occurs. You have to -# set up you HW breakpoints to trigger a DBG interrupt: -# -# ccflags-y := -DTRAP_DBG_INTERRUPT -# asflags-y := -DTRAP_DBG_INTERRUPT -# - -asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 - -obj-y := config.o gpio.o intc2.o - diff --git a/arch/m68k/platform/5249/gpio.c b/arch/m68k/platform/5249/gpio.c deleted file mode 100644 index 2b56c6ef65bf..000000000000 --- a/arch/m68k/platform/5249/gpio.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Coldfire generic GPIO support - * - * (C) Copyright 2009, Steven King <[email protected]> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. -*/ - -#include <linux/kernel.h> -#include <linux/init.h> - -#include <asm/coldfire.h> -#include <asm/mcfsim.h> -#include <asm/mcfgpio.h> - -static struct mcf_gpio_chip mcf_gpio_chips[] = { - { - .gpio_chip = { - .label = "GPIO0", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value, - .ngpio = 32, - }, - .pddr = (void __iomem *) MCFSIM2_GPIOENABLE, - .podr = (void __iomem *) MCFSIM2_GPIOWRITE, - .ppdr = (void __iomem *) MCFSIM2_GPIOREAD, - }, - { - .gpio_chip = { - .label = "GPIO1", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value, - .base = 32, - .ngpio = 32, - }, - .pddr = (void __iomem *) MCFSIM2_GPIO1ENABLE, - .podr = (void __iomem *) MCFSIM2_GPIO1WRITE, - .ppdr = (void __iomem *) MCFSIM2_GPIO1READ, - }, -}; - -static int __init mcf_gpio_init(void) -{ - unsigned i = 0; - while (i < ARRAY_SIZE(mcf_gpio_chips)) - (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]); - return 0; -} - -core_initcall(mcf_gpio_init); diff --git a/arch/m68k/platform/5272/Makefile b/arch/m68k/platform/5272/Makefile deleted file mode 100644 index 34110fc14301..000000000000 --- a/arch/m68k/platform/5272/Makefile +++ /dev/null @@ -1,18 +0,0 @@ -# -# Makefile for the linux kernel. -# - -# -# If you want to play with the HW breakpoints then you will -# need to add define this, which will give you a stack backtrace -# on the console port whenever a DBG interrupt occurs. You have to -# set up you HW breakpoints to trigger a DBG interrupt: -# -# ccflags-y := -DTRAP_DBG_INTERRUPT -# asflags-y := -DTRAP_DBG_INTERRUPT -# - -asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 - -obj-y := config.o gpio.o intc.o - diff --git a/arch/m68k/platform/5272/gpio.c b/arch/m68k/platform/5272/gpio.c deleted file mode 100644 index 57ac10a5d7f7..000000000000 --- a/arch/m68k/platform/5272/gpio.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Coldfire generic GPIO support - * - * (C) Copyright 2009, Steven King <[email protected]> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. -*/ - -#include <linux/kernel.h> -#include <linux/init.h> - -#include <asm/coldfire.h> -#include <asm/mcfsim.h> -#include <asm/mcfgpio.h> - -static struct mcf_gpio_chip mcf_gpio_chips[] = { - { - .gpio_chip = { - .label = "PA", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value, - .ngpio = 16, - }, - .pddr = (void __iomem *) MCFSIM_PADDR, - .podr = (void __iomem *) MCFSIM_PADAT, - .ppdr = (void __iomem *) MCFSIM_PADAT, - }, - { - .gpio_chip = { - .label = "PB", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value, - .base = 16, - .ngpio = 16, - }, - .pddr = (void __iomem *) MCFSIM_PBDDR, - .podr = (void __iomem *) MCFSIM_PBDAT, - .ppdr = (void __iomem *) MCFSIM_PBDAT, - }, - { - .gpio_chip = { - .label = "PC", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value, - .base = 32, - .ngpio = 16, - }, - .pddr = (void __iomem *) MCFSIM_PCDDR, - .podr = (void __iomem *) MCFSIM_PCDAT, - .ppdr = (void __iomem *) MCFSIM_PCDAT, - }, -}; - -static int __init mcf_gpio_init(void) -{ - unsigned i = 0; - while (i < ARRAY_SIZE(mcf_gpio_chips)) - (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]); - return 0; -} - -core_initcall(mcf_gpio_init); diff --git a/arch/m68k/platform/527x/Makefile b/arch/m68k/platform/527x/Makefile deleted file mode 100644 index 6ac4b57370ea..000000000000 --- a/arch/m68k/platform/527x/Makefile +++ /dev/null @@ -1,18 +0,0 @@ -# -# Makefile for the linux kernel. -# - -# -# If you want to play with the HW breakpoints then you will -# need to add define this, which will give you a stack backtrace -# on the console port whenever a DBG interrupt occurs. You have to -# set up you HW breakpoints to trigger a DBG interrupt: -# -# ccflags-y := -DTRAP_DBG_INTERRUPT -# asflags-y := -DTRAP_DBG_INTERRUPT -# - -asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 - -obj-y := config.o gpio.o - diff --git a/arch/m68k/platform/527x/gpio.c b/arch/m68k/platform/527x/gpio.c deleted file mode 100644 index 205da0aa0f2d..000000000000 --- a/arch/m68k/platform/527x/gpio.c +++ /dev/null @@ -1,609 +0,0 @@ -/* - * Coldfire generic GPIO support - * - * (C) Copyright 2009, Steven King <[email protected]> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. -*/ - -#include <linux/kernel.h> -#include <linux/init.h> - -#include <asm/coldfire.h> -#include <asm/mcfsim.h> -#include <asm/mcfgpio.h> - -static struct mcf_gpio_chip mcf_gpio_chips[] = { -#if defined(CONFIG_M5271) - { - .gpio_chip = { - .label = "PIRQ", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value, - .base = 1, - .ngpio = 7, - }, - .pddr = (void __iomem *) MCFEPORT_EPDDR, - .podr = (void __iomem *) MCFEPORT_EPDR, - .ppdr = (void __iomem *) MCFEPORT_EPPDR, - }, - { - .gpio_chip = { - .label = "ADDR", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 13, - .ngpio = 3, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_ADDR, - .podr = (void __iomem *) MCFGPIO_PODR_ADDR, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_ADDR, - .setr = (void __iomem *) MCFGPIO_PPDSDR_ADDR, - .clrr = (void __iomem *) MCFGPIO_PCLRR_ADDR, - }, - { - .gpio_chip = { - .label = "DATAH", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 16, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_DATAH, - .podr = (void __iomem *) MCFGPIO_PODR_DATAH, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_DATAH, - .setr = (void __iomem *) MCFGPIO_PPDSDR_DATAH, - .clrr = (void __iomem *) MCFGPIO_PCLRR_DATAH, - }, - { - .gpio_chip = { - .label = "DATAL", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 24, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_DATAL, - .podr = (void __iomem *) MCFGPIO_PODR_DATAL, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_DATAL, - .setr = (void __iomem *) MCFGPIO_PPDSDR_DATAL, - .clrr = (void __iomem *) MCFGPIO_PCLRR_DATAL, - }, - { - .gpio_chip = { - .label = "BUSCTL", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 32, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_BUSCTL, - .podr = (void __iomem *) MCFGPIO_PODR_BUSCTL, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL, - .setr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL, - .clrr = (void __iomem *) MCFGPIO_PCLRR_BUSCTL, - }, - { - .gpio_chip = { - .label = "BS", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 40, - .ngpio = 4, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_BS, - .podr = (void __iomem *) MCFGPIO_PODR_BS, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BS, - .setr = (void __iomem *) MCFGPIO_PPDSDR_BS, - .clrr = (void __iomem *) MCFGPIO_PCLRR_BS, - }, - { - .gpio_chip = { - .label = "CS", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 49, - .ngpio = 7, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_CS, - .podr = (void __iomem *) MCFGPIO_PODR_CS, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_CS, - .setr = (void __iomem *) MCFGPIO_PPDSDR_CS, - .clrr = (void __iomem *) MCFGPIO_PCLRR_CS, - }, - { - .gpio_chip = { - .label = "SDRAM", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 56, - .ngpio = 6, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_SDRAM, - .podr = (void __iomem *) MCFGPIO_PODR_SDRAM, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_SDRAM, - .setr = (void __iomem *) MCFGPIO_PPDSDR_SDRAM, - .clrr = (void __iomem *) MCFGPIO_PCLRR_SDRAM, - }, - { - .gpio_chip = { - .label = "FECI2C", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 64, - .ngpio = 4, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_FECI2C, - .podr = (void __iomem *) MCFGPIO_PODR_FECI2C, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C, - .setr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C, - .clrr = (void __iomem *) MCFGPIO_PCLRR_FECI2C, - }, - { - .gpio_chip = { - .label = "UARTH", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 72, - .ngpio = 2, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_UARTH, - .podr = (void __iomem *) MCFGPIO_PODR_UARTH, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_UARTH, - .setr = (void __iomem *) MCFGPIO_PPDSDR_UARTH, - .clrr = (void __iomem *) MCFGPIO_PCLRR_UARTH, - }, - { - .gpio_chip = { - .label = "UARTL", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 80, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_UARTL, - .podr = (void __iomem *) MCFGPIO_PODR_UARTL, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_UARTL, - .setr = (void __iomem *) MCFGPIO_PPDSDR_UARTL, - .clrr = (void __iomem *) MCFGPIO_PCLRR_UARTL, - }, - { - .gpio_chip = { - .label = "QSPI", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 88, - .ngpio = 5, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_QSPI, - .podr = (void __iomem *) MCFGPIO_PODR_QSPI, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_QSPI, - .setr = (void __iomem *) MCFGPIO_PPDSDR_QSPI, - .clrr = (void __iomem *) MCFGPIO_PCLRR_QSPI, - }, - { - .gpio_chip = { - .label = "TIMER", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 96, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_TIMER, - .podr = (void __iomem *) MCFGPIO_PODR_TIMER, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_TIMER, - .setr = (void __iomem *) MCFGPIO_PPDSDR_TIMER, - .clrr = (void __iomem *) MCFGPIO_PCLRR_TIMER, - }, -#elif defined(CONFIG_M5275) - { - .gpio_chip = { - .label = "PIRQ", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value, - .base = 1, - .ngpio = 7, - }, - .pddr = (void __iomem *) MCFEPORT_EPDDR, - .podr = (void __iomem *) MCFEPORT_EPDR, - .ppdr = (void __iomem *) MCFEPORT_EPPDR, - }, - { - .gpio_chip = { - .label = "BUSCTL", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 8, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_BUSCTL, - .podr = (void __iomem *) MCFGPIO_PODR_BUSCTL, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL, - .setr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL, - .clrr = (void __iomem *) MCFGPIO_PCLRR_BUSCTL, - }, - { - .gpio_chip = { - .label = "ADDR", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 21, - .ngpio = 3, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_ADDR, - .podr = (void __iomem *) MCFGPIO_PODR_ADDR, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_ADDR, - .setr = (void __iomem *) MCFGPIO_PPDSDR_ADDR, - .clrr = (void __iomem *) MCFGPIO_PCLRR_ADDR, - }, - { - .gpio_chip = { - .label = "CS", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 25, - .ngpio = 7, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_CS, - .podr = (void __iomem *) MCFGPIO_PODR_CS, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_CS, - .setr = (void __iomem *) MCFGPIO_PPDSDR_CS, - .clrr = (void __iomem *) MCFGPIO_PCLRR_CS, - }, - { - .gpio_chip = { - .label = "FEC0H", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 32, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_FEC0H, - .podr = (void __iomem *) MCFGPIO_PODR_FEC0H, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FEC0H, - .setr = (void __iomem *) MCFGPIO_PPDSDR_FEC0H, - .clrr = (void __iomem *) MCFGPIO_PCLRR_FEC0H, - }, - { - .gpio_chip = { - .label = "FEC0L", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 40, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_FEC0L, - .podr = (void __iomem *) MCFGPIO_PODR_FEC0L, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FEC0L, - .setr = (void __iomem *) MCFGPIO_PPDSDR_FEC0L, - .clrr = (void __iomem *) MCFGPIO_PCLRR_FEC0L, - }, - { - .gpio_chip = { - .label = "FECI2C", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 48, - .ngpio = 6, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_FECI2C, - .podr = (void __iomem *) MCFGPIO_PODR_FECI2C, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C, - .setr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C, - .clrr = (void __iomem *) MCFGPIO_PCLRR_FECI2C, - }, - { - .gpio_chip = { - .label = "QSPI", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 56, - .ngpio = 7, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_QSPI, - .podr = (void __iomem *) MCFGPIO_PODR_QSPI, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_QSPI, - .setr = (void __iomem *) MCFGPIO_PPDSDR_QSPI, - .clrr = (void __iomem *) MCFGPIO_PCLRR_QSPI, - }, - { - .gpio_chip = { - .label = "SDRAM", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 64, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_SDRAM, - .podr = (void __iomem *) MCFGPIO_PODR_SDRAM, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_SDRAM, - .setr = (void __iomem *) MCFGPIO_PPDSDR_SDRAM, - .clrr = (void __iomem *) MCFGPIO_PCLRR_SDRAM, - }, - { - .gpio_chip = { - .label = "TIMERH", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 72, - .ngpio = 4, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_TIMERH, - .podr = (void __iomem *) MCFGPIO_PODR_TIMERH, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_TIMERH, - .setr = (void __iomem *) MCFGPIO_PPDSDR_TIMERH, - .clrr = (void __iomem *) MCFGPIO_PCLRR_TIMERH, - }, - { - .gpio_chip = { - .label = "TIMERL", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 80, - .ngpio = 4, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_TIMERL, - .podr = (void __iomem *) MCFGPIO_PODR_TIMERL, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_TIMERL, - .setr = (void __iomem *) MCFGPIO_PPDSDR_TIMERL, - .clrr = (void __iomem *) MCFGPIO_PCLRR_TIMERL, - }, - { - .gpio_chip = { - .label = "UARTL", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 88, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_UARTL, - .podr = (void __iomem *) MCFGPIO_PODR_UARTL, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_UARTL, - .setr = (void __iomem *) MCFGPIO_PPDSDR_UARTL, - .clrr = (void __iomem *) MCFGPIO_PCLRR_UARTL, - }, - { - .gpio_chip = { - .label = "FEC1H", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 96, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_FEC1H, - .podr = (void __iomem *) MCFGPIO_PODR_FEC1H, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FEC1H, - .setr = (void __iomem *) MCFGPIO_PPDSDR_FEC1H, - .clrr = (void __iomem *) MCFGPIO_PCLRR_FEC1H, - }, - { - .gpio_chip = { - .label = "FEC1L", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 104, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_FEC1L, - .podr = (void __iomem *) MCFGPIO_PODR_FEC1L, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FEC1L, - .setr = (void __iomem *) MCFGPIO_PPDSDR_FEC1L, - .clrr = (void __iomem *) MCFGPIO_PCLRR_FEC1L, - }, - { - .gpio_chip = { - .label = "BS", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 114, - .ngpio = 2, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_BS, - .podr = (void __iomem *) MCFGPIO_PODR_BS, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BS, - .setr = (void __iomem *) MCFGPIO_PPDSDR_BS, - .clrr = (void __iomem *) MCFGPIO_PCLRR_BS, - }, - { - .gpio_chip = { - .label = "IRQ", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 121, - .ngpio = 7, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_IRQ, - .podr = (void __iomem *) MCFGPIO_PODR_IRQ, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_IRQ, - .setr = (void __iomem *) MCFGPIO_PPDSDR_IRQ, - .clrr = (void __iomem *) MCFGPIO_PCLRR_IRQ, - }, - { - .gpio_chip = { - .label = "USBH", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 128, - .ngpio = 1, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_USBH, - .podr = (void __iomem *) MCFGPIO_PODR_USBH, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_USBH, - .setr = (void __iomem *) MCFGPIO_PPDSDR_USBH, - .clrr = (void __iomem *) MCFGPIO_PCLRR_USBH, - }, - { - .gpio_chip = { - .label = "USBL", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 136, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_USBL, - .podr = (void __iomem *) MCFGPIO_PODR_USBL, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_USBL, - .setr = (void __iomem *) MCFGPIO_PPDSDR_USBL, - .clrr = (void __iomem *) MCFGPIO_PCLRR_USBL, - }, - { - .gpio_chip = { - .label = "UARTH", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 144, - .ngpio = 4, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_UARTH, - .podr = (void __iomem *) MCFGPIO_PODR_UARTH, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_UARTH, - .setr = (void __iomem *) MCFGPIO_PPDSDR_UARTH, - .clrr = (void __iomem *) MCFGPIO_PCLRR_UARTH, - }, -#endif -}; - -static int __init mcf_gpio_init(void) -{ - unsigned i = 0; - while (i < ARRAY_SIZE(mcf_gpio_chips)) - (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]); - return 0; -} - -core_initcall(mcf_gpio_init); diff --git a/arch/m68k/platform/528x/Makefile b/arch/m68k/platform/528x/Makefile deleted file mode 100644 index 6ac4b57370ea..000000000000 --- a/arch/m68k/platform/528x/Makefile +++ /dev/null @@ -1,18 +0,0 @@ -# -# Makefile for the linux kernel. -# - -# -# If you want to play with the HW breakpoints then you will -# need to add define this, which will give you a stack backtrace -# on the console port whenever a DBG interrupt occurs. You have to -# set up you HW breakpoints to trigger a DBG interrupt: -# -# ccflags-y := -DTRAP_DBG_INTERRUPT -# asflags-y := -DTRAP_DBG_INTERRUPT -# - -asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 - -obj-y := config.o gpio.o - diff --git a/arch/m68k/platform/528x/gpio.c b/arch/m68k/platform/528x/gpio.c deleted file mode 100644 index 526db665d87e..000000000000 --- a/arch/m68k/platform/528x/gpio.c +++ /dev/null @@ -1,438 +0,0 @@ -/* - * Coldfire generic GPIO support - * - * (C) Copyright 2009, Steven King <[email protected]> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. -*/ - -#include <linux/kernel.h> -#include <linux/init.h> - -#include <asm/coldfire.h> -#include <asm/mcfsim.h> -#include <asm/mcfgpio.h> - -static struct mcf_gpio_chip mcf_gpio_chips[] = { - { - .gpio_chip = { - .label = "NQ", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value, - .base = 1, - .ngpio = 7, - }, - .pddr = (void __iomem *)MCFEPORT_EPDDR, - .podr = (void __iomem *)MCFEPORT_EPDR, - .ppdr = (void __iomem *)MCFEPORT_EPPDR, - }, - { - .gpio_chip = { - .label = "TA", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 8, - .ngpio = 4, - }, - .pddr = (void __iomem *)MCFGPTA_GPTDDR, - .podr = (void __iomem *)MCFGPTA_GPTPORT, - .ppdr = (void __iomem *)MCFGPTB_GPTPORT, - }, - { - .gpio_chip = { - .label = "TB", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 16, - .ngpio = 4, - }, - .pddr = (void __iomem *)MCFGPTB_GPTDDR, - .podr = (void __iomem *)MCFGPTB_GPTPORT, - .ppdr = (void __iomem *)MCFGPTB_GPTPORT, - }, - { - .gpio_chip = { - .label = "QA", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 24, - .ngpio = 4, - }, - .pddr = (void __iomem *)MCFQADC_DDRQA, - .podr = (void __iomem *)MCFQADC_PORTQA, - .ppdr = (void __iomem *)MCFQADC_PORTQA, - }, - { - .gpio_chip = { - .label = "QB", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 32, - .ngpio = 4, - }, - .pddr = (void __iomem *)MCFQADC_DDRQB, - .podr = (void __iomem *)MCFQADC_PORTQB, - .ppdr = (void __iomem *)MCFQADC_PORTQB, - }, - { - .gpio_chip = { - .label = "A", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 40, - .ngpio = 8, - }, - .pddr = (void __iomem *)MCFGPIO_DDRA, - .podr = (void __iomem *)MCFGPIO_PORTA, - .ppdr = (void __iomem *)MCFGPIO_PORTAP, - .setr = (void __iomem *)MCFGPIO_SETA, - .clrr = (void __iomem *)MCFGPIO_CLRA, - }, - { - .gpio_chip = { - .label = "B", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 48, - .ngpio = 8, - }, - .pddr = (void __iomem *)MCFGPIO_DDRB, - .podr = (void __iomem *)MCFGPIO_PORTB, - .ppdr = (void __iomem *)MCFGPIO_PORTBP, - .setr = (void __iomem *)MCFGPIO_SETB, - .clrr = (void __iomem *)MCFGPIO_CLRB, - }, - { - .gpio_chip = { - .label = "C", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 56, - .ngpio = 8, - }, - .pddr = (void __iomem *)MCFGPIO_DDRC, - .podr = (void __iomem *)MCFGPIO_PORTC, - .ppdr = (void __iomem *)MCFGPIO_PORTCP, - .setr = (void __iomem *)MCFGPIO_SETC, - .clrr = (void __iomem *)MCFGPIO_CLRC, - }, - { - .gpio_chip = { - .label = "D", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 64, - .ngpio = 8, - }, - .pddr = (void __iomem *)MCFGPIO_DDRD, - .podr = (void __iomem *)MCFGPIO_PORTD, - .ppdr = (void __iomem *)MCFGPIO_PORTDP, - .setr = (void __iomem *)MCFGPIO_SETD, - .clrr = (void __iomem *)MCFGPIO_CLRD, - }, - { - .gpio_chip = { - .label = "E", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 72, - .ngpio = 8, - }, - .pddr = (void __iomem *)MCFGPIO_DDRE, - .podr = (void __iomem *)MCFGPIO_PORTE, - .ppdr = (void __iomem *)MCFGPIO_PORTEP, - .setr = (void __iomem *)MCFGPIO_SETE, - .clrr = (void __iomem *)MCFGPIO_CLRE, - }, - { - .gpio_chip = { - .label = "F", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 80, - .ngpio = 8, - }, - .pddr = (void __iomem *)MCFGPIO_DDRF, - .podr = (void __iomem *)MCFGPIO_PORTF, - .ppdr = (void __iomem *)MCFGPIO_PORTFP, - .setr = (void __iomem *)MCFGPIO_SETF, - .clrr = (void __iomem *)MCFGPIO_CLRF, - }, - { - .gpio_chip = { - .label = "G", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 88, - .ngpio = 8, - }, - .pddr = (void __iomem *)MCFGPIO_DDRG, - .podr = (void __iomem *)MCFGPIO_PORTG, - .ppdr = (void __iomem *)MCFGPIO_PORTGP, - .setr = (void __iomem *)MCFGPIO_SETG, - .clrr = (void __iomem *)MCFGPIO_CLRG, - }, - { - .gpio_chip = { - .label = "H", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 96, - .ngpio = 8, - }, - .pddr = (void __iomem *)MCFGPIO_DDRH, - .podr = (void __iomem *)MCFGPIO_PORTH, - .ppdr = (void __iomem *)MCFGPIO_PORTHP, - .setr = (void __iomem *)MCFGPIO_SETH, - .clrr = (void __iomem *)MCFGPIO_CLRH, - }, - { - .gpio_chip = { - .label = "J", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 104, - .ngpio = 8, - }, - .pddr = (void __iomem *)MCFGPIO_DDRJ, - .podr = (void __iomem *)MCFGPIO_PORTJ, - .ppdr = (void __iomem *)MCFGPIO_PORTJP, - .setr = (void __iomem *)MCFGPIO_SETJ, - .clrr = (void __iomem *)MCFGPIO_CLRJ, - }, - { - .gpio_chip = { - .label = "DD", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 112, - .ngpio = 8, - }, - .pddr = (void __iomem *)MCFGPIO_DDRDD, - .podr = (void __iomem *)MCFGPIO_PORTDD, - .ppdr = (void __iomem *)MCFGPIO_PORTDDP, - .setr = (void __iomem *)MCFGPIO_SETDD, - .clrr = (void __iomem *)MCFGPIO_CLRDD, - }, - { - .gpio_chip = { - .label = "EH", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 120, - .ngpio = 8, - }, - .pddr = (void __iomem *)MCFGPIO_DDREH, - .podr = (void __iomem *)MCFGPIO_PORTEH, - .ppdr = (void __iomem *)MCFGPIO_PORTEHP, - .setr = (void __iomem *)MCFGPIO_SETEH, - .clrr = (void __iomem *)MCFGPIO_CLREH, - }, - { - .gpio_chip = { - .label = "EL", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 128, - .ngpio = 8, - }, - .pddr = (void __iomem *)MCFGPIO_DDREL, - .podr = (void __iomem *)MCFGPIO_PORTEL, - .ppdr = (void __iomem *)MCFGPIO_PORTELP, - .setr = (void __iomem *)MCFGPIO_SETEL, - .clrr = (void __iomem *)MCFGPIO_CLREL, - }, - { - .gpio_chip = { - .label = "AS", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 136, - .ngpio = 6, - }, - .pddr = (void __iomem *)MCFGPIO_DDRAS, - .podr = (void __iomem *)MCFGPIO_PORTAS, - .ppdr = (void __iomem *)MCFGPIO_PORTASP, - .setr = (void __iomem *)MCFGPIO_SETAS, - .clrr = (void __iomem *)MCFGPIO_CLRAS, - }, - { - .gpio_chip = { - .label = "QS", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 144, - .ngpio = 7, - }, - .pddr = (void __iomem *)MCFGPIO_DDRQS, - .podr = (void __iomem *)MCFGPIO_PORTQS, - .ppdr = (void __iomem *)MCFGPIO_PORTQSP, - .setr = (void __iomem *)MCFGPIO_SETQS, - .clrr = (void __iomem *)MCFGPIO_CLRQS, - }, - { - .gpio_chip = { - .label = "SD", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 152, - .ngpio = 6, - }, - .pddr = (void __iomem *)MCFGPIO_DDRSD, - .podr = (void __iomem *)MCFGPIO_PORTSD, - .ppdr = (void __iomem *)MCFGPIO_PORTSDP, - .setr = (void __iomem *)MCFGPIO_SETSD, - .clrr = (void __iomem *)MCFGPIO_CLRSD, - }, - { - .gpio_chip = { - .label = "TC", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 160, - .ngpio = 4, - }, - .pddr = (void __iomem *)MCFGPIO_DDRTC, - .podr = (void __iomem *)MCFGPIO_PORTTC, - .ppdr = (void __iomem *)MCFGPIO_PORTTCP, - .setr = (void __iomem *)MCFGPIO_SETTC, - .clrr = (void __iomem *)MCFGPIO_CLRTC, - }, - { - .gpio_chip = { - .label = "TD", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 168, - .ngpio = 4, - }, - .pddr = (void __iomem *)MCFGPIO_DDRTD, - .podr = (void __iomem *)MCFGPIO_PORTTD, - .ppdr = (void __iomem *)MCFGPIO_PORTTDP, - .setr = (void __iomem *)MCFGPIO_SETTD, - .clrr = (void __iomem *)MCFGPIO_CLRTD, - }, - { - .gpio_chip = { - .label = "UA", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 176, - .ngpio = 4, - }, - .pddr = (void __iomem *)MCFGPIO_DDRUA, - .podr = (void __iomem *)MCFGPIO_PORTUA, - .ppdr = (void __iomem *)MCFGPIO_PORTUAP, - .setr = (void __iomem *)MCFGPIO_SETUA, - .clrr = (void __iomem *)MCFGPIO_CLRUA, - }, -}; - -static int __init mcf_gpio_init(void) -{ - unsigned i = 0; - while (i < ARRAY_SIZE(mcf_gpio_chips)) - (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]); - return 0; -} - -core_initcall(mcf_gpio_init); diff --git a/arch/m68k/platform/5307/Makefile b/arch/m68k/platform/5307/Makefile deleted file mode 100644 index d4293b791f2e..000000000000 --- a/arch/m68k/platform/5307/Makefile +++ /dev/null @@ -1,20 +0,0 @@ -# -# Makefile for the m68knommu kernel. -# - -# -# If you want to play with the HW breakpoints then you will -# need to add define this, which will give you a stack backtrace -# on the console port whenever a DBG interrupt occurs. You have to -# set up you HW breakpoints to trigger a DBG interrupt: -# -# ccflags-y := -DTRAP_DBG_INTERRUPT -# asflags-y := -DTRAP_DBG_INTERRUPT -# - -asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 - -obj-y += config.o gpio.o -obj-$(CONFIG_NETtel) += nettel.o -obj-$(CONFIG_CLEOPATRA) += nettel.o - diff --git a/arch/m68k/platform/5307/gpio.c b/arch/m68k/platform/5307/gpio.c deleted file mode 100644 index 5850612b4a38..000000000000 --- a/arch/m68k/platform/5307/gpio.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Coldfire generic GPIO support - * - * (C) Copyright 2009, Steven King <[email protected]> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. -*/ - -#include <linux/kernel.h> -#include <linux/init.h> - -#include <asm/coldfire.h> -#include <asm/mcfsim.h> -#include <asm/mcfgpio.h> - -static struct mcf_gpio_chip mcf_gpio_chips[] = { - { - .gpio_chip = { - .label = "PP", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value, - .ngpio = 16, - }, - .pddr = (void __iomem *) MCFSIM_PADDR, - .podr = (void __iomem *) MCFSIM_PADAT, - .ppdr = (void __iomem *) MCFSIM_PADAT, - }, -}; - -static int __init mcf_gpio_init(void) -{ - unsigned i = 0; - while (i < ARRAY_SIZE(mcf_gpio_chips)) - (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]); - return 0; -} - -core_initcall(mcf_gpio_init); diff --git a/arch/m68k/platform/532x/Makefile b/arch/m68k/platform/532x/Makefile deleted file mode 100644 index ce01669399c6..000000000000 --- a/arch/m68k/platform/532x/Makefile +++ /dev/null @@ -1,18 +0,0 @@ -# -# Makefile for the m68knommu linux kernel. -# - -# -# If you want to play with the HW breakpoints then you will -# need to add define this, which will give you a stack backtrace -# on the console port whenever a DBG interrupt occurs. You have to -# set up you HW breakpoints to trigger a DBG interrupt: -# -# ccflags-y := -DTRAP_DBG_INTERRUPT -# asflags-y := -DTRAP_DBG_INTERRUPT -# - -asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 - -#obj-y := config.o usb-mcf532x.o spi-mcf532x.o -obj-y := config.o gpio.o diff --git a/arch/m68k/platform/532x/gpio.c b/arch/m68k/platform/532x/gpio.c deleted file mode 100644 index 212a85deac90..000000000000 --- a/arch/m68k/platform/532x/gpio.c +++ /dev/null @@ -1,337 +0,0 @@ -/* - * Coldfire generic GPIO support - * - * (C) Copyright 2009, Steven King <[email protected]> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. -*/ - -#include <linux/kernel.h> -#include <linux/init.h> - -#include <asm/coldfire.h> -#include <asm/mcfsim.h> -#include <asm/mcfgpio.h> - -static struct mcf_gpio_chip mcf_gpio_chips[] = { - { - .gpio_chip = { - .label = "PIRQ", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFEPORT_EPDDR, - .podr = (void __iomem *) MCFEPORT_EPDR, - .ppdr = (void __iomem *) MCFEPORT_EPPDR, - }, - { - .gpio_chip = { - .label = "FECH", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 8, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_FECH, - .podr = (void __iomem *) MCFGPIO_PODR_FECH, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECH, - .setr = (void __iomem *) MCFGPIO_PPDSDR_FECH, - .clrr = (void __iomem *) MCFGPIO_PCLRR_FECH, - }, - { - .gpio_chip = { - .label = "FECL", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 16, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_FECL, - .podr = (void __iomem *) MCFGPIO_PODR_FECL, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECL, - .setr = (void __iomem *) MCFGPIO_PPDSDR_FECL, - .clrr = (void __iomem *) MCFGPIO_PCLRR_FECL, - }, - { - .gpio_chip = { - .label = "SSI", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 24, - .ngpio = 5, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_SSI, - .podr = (void __iomem *) MCFGPIO_PODR_SSI, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_SSI, - .setr = (void __iomem *) MCFGPIO_PPDSDR_SSI, - .clrr = (void __iomem *) MCFGPIO_PCLRR_SSI, - }, - { - .gpio_chip = { - .label = "BUSCTL", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 32, - .ngpio = 4, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_BUSCTL, - .podr = (void __iomem *) MCFGPIO_PODR_BUSCTL, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL, - .setr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL, - .clrr = (void __iomem *) MCFGPIO_PCLRR_BUSCTL, - }, - { - .gpio_chip = { - .label = "BE", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 40, - .ngpio = 4, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_BE, - .podr = (void __iomem *) MCFGPIO_PODR_BE, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BE, - .setr = (void __iomem *) MCFGPIO_PPDSDR_BE, - .clrr = (void __iomem *) MCFGPIO_PCLRR_BE, - }, - { - .gpio_chip = { - .label = "CS", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 49, - .ngpio = 5, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_CS, - .podr = (void __iomem *) MCFGPIO_PODR_CS, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_CS, - .setr = (void __iomem *) MCFGPIO_PPDSDR_CS, - .clrr = (void __iomem *) MCFGPIO_PCLRR_CS, - }, - { - .gpio_chip = { - .label = "PWM", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 58, - .ngpio = 4, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_PWM, - .podr = (void __iomem *) MCFGPIO_PODR_PWM, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_PWM, - .setr = (void __iomem *) MCFGPIO_PPDSDR_PWM, - .clrr = (void __iomem *) MCFGPIO_PCLRR_PWM, - }, - { - .gpio_chip = { - .label = "FECI2C", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 64, - .ngpio = 4, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_FECI2C, - .podr = (void __iomem *) MCFGPIO_PODR_FECI2C, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C, - .setr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C, - .clrr = (void __iomem *) MCFGPIO_PCLRR_FECI2C, - }, - { - .gpio_chip = { - .label = "UART", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 72, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_UART, - .podr = (void __iomem *) MCFGPIO_PODR_UART, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_UART, - .setr = (void __iomem *) MCFGPIO_PPDSDR_UART, - .clrr = (void __iomem *) MCFGPIO_PCLRR_UART, - }, - { - .gpio_chip = { - .label = "QSPI", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 80, - .ngpio = 6, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_QSPI, - .podr = (void __iomem *) MCFGPIO_PODR_QSPI, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_QSPI, - .setr = (void __iomem *) MCFGPIO_PPDSDR_QSPI, - .clrr = (void __iomem *) MCFGPIO_PCLRR_QSPI, - }, - { - .gpio_chip = { - .label = "TIMER", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 88, - .ngpio = 4, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_TIMER, - .podr = (void __iomem *) MCFGPIO_PODR_TIMER, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_TIMER, - .setr = (void __iomem *) MCFGPIO_PPDSDR_TIMER, - .clrr = (void __iomem *) MCFGPIO_PCLRR_TIMER, - }, - { - .gpio_chip = { - .label = "LCDDATAH", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 96, - .ngpio = 2, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_LCDDATAH, - .podr = (void __iomem *) MCFGPIO_PODR_LCDDATAH, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_LCDDATAH, - .setr = (void __iomem *) MCFGPIO_PPDSDR_LCDDATAH, - .clrr = (void __iomem *) MCFGPIO_PCLRR_LCDDATAH, - }, - { - .gpio_chip = { - .label = "LCDDATAM", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 104, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_LCDDATAM, - .podr = (void __iomem *) MCFGPIO_PODR_LCDDATAM, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_LCDDATAM, - .setr = (void __iomem *) MCFGPIO_PPDSDR_LCDDATAM, - .clrr = (void __iomem *) MCFGPIO_PCLRR_LCDDATAM, - }, - { - .gpio_chip = { - .label = "LCDDATAL", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 112, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_LCDDATAL, - .podr = (void __iomem *) MCFGPIO_PODR_LCDDATAL, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_LCDDATAL, - .setr = (void __iomem *) MCFGPIO_PPDSDR_LCDDATAL, - .clrr = (void __iomem *) MCFGPIO_PCLRR_LCDDATAL, - }, - { - .gpio_chip = { - .label = "LCDCTLH", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 120, - .ngpio = 1, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_LCDCTLH, - .podr = (void __iomem *) MCFGPIO_PODR_LCDCTLH, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_LCDCTLH, - .setr = (void __iomem *) MCFGPIO_PPDSDR_LCDCTLH, - .clrr = (void __iomem *) MCFGPIO_PCLRR_LCDCTLH, - }, - { - .gpio_chip = { - .label = "LCDCTLL", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 128, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_LCDCTLL, - .podr = (void __iomem *) MCFGPIO_PODR_LCDCTLL, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_LCDCTLL, - .setr = (void __iomem *) MCFGPIO_PPDSDR_LCDCTLL, - .clrr = (void __iomem *) MCFGPIO_PCLRR_LCDCTLL, - }, -}; - -static int __init mcf_gpio_init(void) -{ - unsigned i = 0; - while (i < ARRAY_SIZE(mcf_gpio_chips)) - (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]); - return 0; -} - -core_initcall(mcf_gpio_init); diff --git a/arch/m68k/platform/5407/Makefile b/arch/m68k/platform/5407/Makefile deleted file mode 100644 index e83fe148eddc..000000000000 --- a/arch/m68k/platform/5407/Makefile +++ /dev/null @@ -1,18 +0,0 @@ -# -# Makefile for the m68knommu linux kernel. -# - -# -# If you want to play with the HW breakpoints then you will -# need to add define this, which will give you a stack backtrace -# on the console port whenever a DBG interrupt occurs. You have to -# set up you HW breakpoints to trigger a DBG interrupt: -# -# ccflags-y := -DTRAP_DBG_INTERRUPT -# asflags-y := -DTRAP_DBG_INTERRUPT -# - -asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 - -obj-y := config.o gpio.o - diff --git a/arch/m68k/platform/5407/gpio.c b/arch/m68k/platform/5407/gpio.c deleted file mode 100644 index 5850612b4a38..000000000000 --- a/arch/m68k/platform/5407/gpio.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Coldfire generic GPIO support - * - * (C) Copyright 2009, Steven King <[email protected]> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. -*/ - -#include <linux/kernel.h> -#include <linux/init.h> - -#include <asm/coldfire.h> -#include <asm/mcfsim.h> -#include <asm/mcfgpio.h> - -static struct mcf_gpio_chip mcf_gpio_chips[] = { - { - .gpio_chip = { - .label = "PP", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value, - .ngpio = 16, - }, - .pddr = (void __iomem *) MCFSIM_PADDR, - .podr = (void __iomem *) MCFSIM_PADAT, - .ppdr = (void __iomem *) MCFSIM_PADAT, - }, -}; - -static int __init mcf_gpio_init(void) -{ - unsigned i = 0; - while (i < ARRAY_SIZE(mcf_gpio_chips)) - (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]); - return 0; -} - -core_initcall(mcf_gpio_init); diff --git a/arch/m68k/platform/54xx/Makefile b/arch/m68k/platform/54xx/Makefile deleted file mode 100644 index 6cfd090ec3cd..000000000000 --- a/arch/m68k/platform/54xx/Makefile +++ /dev/null @@ -1,19 +0,0 @@ -# -# Makefile for the m68knommu linux kernel. -# - -# -# If you want to play with the HW breakpoints then you will -# need to add define this, which will give you a stack backtrace -# on the console port whenever a DBG interrupt occurs. You have to -# set up you HW breakpoints to trigger a DBG interrupt: -# -# EXTRA_CFLAGS += -DTRAP_DBG_INTERRUPT -# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT -# - -asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 - -obj-y := config.o -obj-$(CONFIG_FIREBEE) += firebee.o - diff --git a/arch/m68k/platform/68EZ328/Makefile b/arch/m68k/platform/68EZ328/Makefile index ee97735a242c..b44d799b1115 100644 --- a/arch/m68k/platform/68EZ328/Makefile +++ b/arch/m68k/platform/68EZ328/Makefile @@ -3,9 +3,3 @@ # obj-y := config.o - -extra-y := bootlogo.rh - -$(obj)/bootlogo.rh: $(src)/bootlogo.h - perl $(src)/../68328/bootlogo.pl < $(src)/bootlogo.h \ - > $(obj)/bootlogo.rh diff --git a/arch/m68k/platform/68VZ328/Makefile b/arch/m68k/platform/68VZ328/Makefile index 447ffa0fd7c7..a49d75e65489 100644 --- a/arch/m68k/platform/68VZ328/Makefile +++ b/arch/m68k/platform/68VZ328/Makefile @@ -3,14 +3,9 @@ # obj-y := config.o -logo-$(UCDIMM) := bootlogo.rh -logo-$(DRAGEN2) := screen.h -extra-y := $(logo-y) - -$(obj)/bootlogo.rh: $(src)/../68EZ328/bootlogo.h - perl $(src)/bootlogo.pl < $(src)/../68328/bootlogo.h > $(obj)/bootlogo.rh +extra-$(DRAGEN2):= screen.h $(obj)/screen.h: $(src)/screen.xbm $(src)/xbm2lcd.pl perl $(src)/xbm2lcd.pl < $(src)/screen.xbm > $(obj)/screen.h -clean-files := $(obj)/screen.h $(obj)/bootlogo.rh +clean-files := $(obj)/screen.h diff --git a/arch/m68k/platform/68EZ328/bootlogo.h b/arch/m68k/platform/68VZ328/bootlogo.h index e842bdae5839..b38e2b255142 100644 --- a/arch/m68k/platform/68EZ328/bootlogo.h +++ b/arch/m68k/platform/68VZ328/bootlogo.h @@ -1,6 +1,6 @@ #define splash_width 640 #define splash_height 480 -static unsigned char splash_bits[] = { +unsigned char __attribute__ ((aligned(16))) bootlogo_bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, diff --git a/arch/m68k/platform/coldfire/Makefile b/arch/m68k/platform/coldfire/Makefile index a0815c61dec1..76d389d9a84e 100644 --- a/arch/m68k/platform/coldfire/Makefile +++ b/arch/m68k/platform/coldfire/Makefile @@ -15,18 +15,22 @@ asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 obj-$(CONFIG_COLDFIRE) += cache.o clk.o device.o dma.o entry.o vectors.o -obj-$(CONFIG_M5206) += timers.o intc.o reset.o -obj-$(CONFIG_M5206e) += timers.o intc.o reset.o -obj-$(CONFIG_M520x) += pit.o intc-simr.o reset.o -obj-$(CONFIG_M523x) += pit.o dma_timer.o intc-2.o reset.o -obj-$(CONFIG_M5249) += timers.o intc.o reset.o -obj-$(CONFIG_M527x) += pit.o intc-2.o reset.o -obj-$(CONFIG_M5272) += timers.o -obj-$(CONFIG_M528x) += pit.o intc-2.o reset.o -obj-$(CONFIG_M5307) += timers.o intc.o reset.o -obj-$(CONFIG_M532x) += timers.o intc-simr.o reset.o -obj-$(CONFIG_M5407) += timers.o intc.o reset.o -obj-$(CONFIG_M54xx) += sltimers.o intc-2.o +obj-$(CONFIG_M5206) += m5206.o timers.o intc.o reset.o +obj-$(CONFIG_M5206e) += m5206.o timers.o intc.o reset.o +obj-$(CONFIG_M520x) += m520x.o pit.o intc-simr.o reset.o +obj-$(CONFIG_M523x) += m523x.o pit.o dma_timer.o intc-2.o reset.o +obj-$(CONFIG_M5249) += m5249.o timers.o intc.o intc-5249.o reset.o +obj-$(CONFIG_M527x) += m527x.o pit.o intc-2.o reset.o +obj-$(CONFIG_M5272) += m5272.o intc-5272.o timers.o +obj-$(CONFIG_M528x) += m528x.o pit.o intc-2.o reset.o +obj-$(CONFIG_M5307) += m5307.o timers.o intc.o reset.o +obj-$(CONFIG_M532x) += m532x.o timers.o intc-simr.o reset.o +obj-$(CONFIG_M5407) += m5407.o timers.o intc.o reset.o +obj-$(CONFIG_M54xx) += m54xx.o sltimers.o intc-2.o + +obj-$(CONFIG_NETtel) += nettel.o +obj-$(CONFIG_CLEOPATRA) += nettel.o +obj-$(CONFIG_FIREBEE) += firebee.o obj-y += pinmux.o gpio.o extra-y := head.o diff --git a/arch/m68k/platform/coldfire/device.c b/arch/m68k/platform/coldfire/device.c index fa50c48292ff..3aa77ddea89d 100644 --- a/arch/m68k/platform/coldfire/device.c +++ b/arch/m68k/platform/coldfire/device.c @@ -114,14 +114,14 @@ static struct resource mcf_fec1_resources[] = { static struct platform_device mcf_fec1 = { .name = "fec", - .id = 0, + .id = 1, .num_resources = ARRAY_SIZE(mcf_fec1_resources), .resource = mcf_fec1_resources, }; #endif /* MCFFEC_BASE1 */ #endif /* CONFIG_FEC */ -#ifdef CONFIG_SPI_COLDFIRE_QSPI +#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) /* * The ColdFire QSPI module is an SPI protocol hardware block used * on a number of different ColdFire CPUs. @@ -274,7 +274,7 @@ static struct platform_device mcf_qspi = { .resource = mcf_qspi_resources, .dev.platform_data = &mcf_qspi_data, }; -#endif /* CONFIG_SPI_COLDFIRE_QSPI */ +#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */ static struct platform_device *mcf_devices[] __initdata = { &mcf_uart, @@ -284,7 +284,7 @@ static struct platform_device *mcf_devices[] __initdata = { &mcf_fec1, #endif #endif -#ifdef CONFIG_SPI_COLDFIRE_QSPI +#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) &mcf_qspi, #endif }; diff --git a/arch/m68k/platform/54xx/firebee.c b/arch/m68k/platform/coldfire/firebee.c index 46d50534f981..46d50534f981 100644 --- a/arch/m68k/platform/54xx/firebee.c +++ b/arch/m68k/platform/coldfire/firebee.c diff --git a/arch/m68k/platform/coldfire/gpio.c b/arch/m68k/platform/coldfire/gpio.c index 292a1a5a2d7c..4c8c42450a4e 100644 --- a/arch/m68k/platform/coldfire/gpio.c +++ b/arch/m68k/platform/coldfire/gpio.c @@ -122,6 +122,10 @@ struct bus_type mcf_gpio_subsys = { static int __init mcf_gpio_sysinit(void) { + unsigned int i = 0; + + while (i < mcf_gpio_chips_size) + gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]); return subsys_system_register(&mcf_gpio_subsys, NULL); } diff --git a/arch/m68k/platform/5249/intc2.c b/arch/m68k/platform/coldfire/intc-5249.c index f343bf7bf5b0..f343bf7bf5b0 100644 --- a/arch/m68k/platform/5249/intc2.c +++ b/arch/m68k/platform/coldfire/intc-5249.c diff --git a/arch/m68k/platform/5272/intc.c b/arch/m68k/platform/coldfire/intc-5272.c index 7160e618b0a9..7160e618b0a9 100644 --- a/arch/m68k/platform/5272/intc.c +++ b/arch/m68k/platform/coldfire/intc-5272.c diff --git a/arch/m68k/platform/5206/config.c b/arch/m68k/platform/coldfire/m5206.c index 6bfbeebd231b..a8b81df653f0 100644 --- a/arch/m68k/platform/5206/config.c +++ b/arch/m68k/platform/coldfire/m5206.c @@ -16,6 +16,15 @@ #include <asm/machdep.h> #include <asm/coldfire.h> #include <asm/mcfsim.h> +#include <asm/mcfgpio.h> + +/***************************************************************************/ + +struct mcf_gpio_chip mcf_gpio_chips[] = { + MCFGPS(PP, 0, 8, MCFSIM_PADDR, MCFSIM_PADAT, MCFSIM_PADAT), +}; + +unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips); /***************************************************************************/ diff --git a/arch/m68k/platform/520x/config.c b/arch/m68k/platform/coldfire/m520x.c index 235947844f27..3264b8883d5f 100644 --- a/arch/m68k/platform/520x/config.c +++ b/arch/m68k/platform/coldfire/m520x.c @@ -19,10 +19,26 @@ #include <asm/coldfire.h> #include <asm/mcfsim.h> #include <asm/mcfuart.h> +#include <asm/mcfgpio.h> /***************************************************************************/ -#ifdef CONFIG_SPI_COLDFIRE_QSPI +struct mcf_gpio_chip mcf_gpio_chips[] = { + MCFGPS(PIRQ, 0, 8, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR), + MCFGPF(CS, 9, 3), + MCFGPF(FECI2C, 16, 4), + MCFGPF(QSPI, 24, 4), + MCFGPF(TIMER, 32, 4), + MCFGPF(UART, 40, 8), + MCFGPF(FECH, 48, 8), + MCFGPF(FECL, 56, 8), +}; + +unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips); + +/***************************************************************************/ + +#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) static void __init m520x_qspi_init(void) { @@ -35,7 +51,7 @@ static void __init m520x_qspi_init(void) writew(par, MCF_GPIO_PAR_UART); } -#endif /* CONFIG_SPI_COLDFIRE_QSPI */ +#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */ /***************************************************************************/ @@ -79,7 +95,7 @@ void __init config_BSP(char *commandp, int size) mach_sched_init = hw_timer_init; m520x_uarts_init(); m520x_fec_init(); -#ifdef CONFIG_SPI_COLDFIRE_QSPI +#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) m520x_qspi_init(); #endif } diff --git a/arch/m68k/platform/523x/config.c b/arch/m68k/platform/coldfire/m523x.c index c8b405d5a961..5d57a4249412 100644 --- a/arch/m68k/platform/523x/config.c +++ b/arch/m68k/platform/coldfire/m523x.c @@ -19,10 +19,32 @@ #include <asm/machdep.h> #include <asm/coldfire.h> #include <asm/mcfsim.h> +#include <asm/mcfgpio.h> /***************************************************************************/ -#ifdef CONFIG_SPI_COLDFIRE_QSPI +struct mcf_gpio_chip mcf_gpio_chips[] = { + MCFGPS(PIRQ, 1, 7, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR), + MCFGPF(ADDR, 13, 3), + MCFGPF(DATAH, 16, 8), + MCFGPF(DATAL, 24, 8), + MCFGPF(BUSCTL, 32, 8), + MCFGPF(BS, 40, 4), + MCFGPF(CS, 49, 7), + MCFGPF(SDRAM, 56, 6), + MCFGPF(FECI2C, 64, 4), + MCFGPF(UARTH, 72, 2), + MCFGPF(UARTL, 80, 8), + MCFGPF(QSPI, 88, 5), + MCFGPF(TIMER, 96, 8), + MCFGPF(ETPU, 104, 3), +}; + +unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips); + +/***************************************************************************/ + +#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) static void __init m523x_qspi_init(void) { @@ -36,7 +58,7 @@ static void __init m523x_qspi_init(void) writew(par, MCFGPIO_PAR_TIMER); } -#endif /* CONFIG_SPI_COLDFIRE_QSPI */ +#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */ /***************************************************************************/ @@ -58,7 +80,7 @@ void __init config_BSP(char *commandp, int size) { mach_sched_init = hw_timer_init; m523x_fec_init(); -#ifdef CONFIG_SPI_COLDFIRE_QSPI +#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) m523x_qspi_init(); #endif } diff --git a/arch/m68k/platform/5249/config.c b/arch/m68k/platform/coldfire/m5249.c index bbf05135bb98..fdfa1edfd1ac 100644 --- a/arch/m68k/platform/5249/config.c +++ b/arch/m68k/platform/coldfire/m5249.c @@ -16,6 +16,16 @@ #include <asm/machdep.h> #include <asm/coldfire.h> #include <asm/mcfsim.h> +#include <asm/mcfgpio.h> + +/***************************************************************************/ + +struct mcf_gpio_chip mcf_gpio_chips[] = { + MCFGPS(GPIO0, 0, 32, MCFSIM2_GPIOENABLE, MCFSIM2_GPIOWRITE, MCFSIM2_GPIOREAD), + MCFGPS(GPIO1, 32, 32, MCFSIM2_GPIO1ENABLE, MCFSIM2_GPIO1WRITE, MCFSIM2_GPIO1READ), +}; + +unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips); /***************************************************************************/ @@ -51,7 +61,7 @@ static struct platform_device *m5249_devices[] __initdata = { /***************************************************************************/ -#ifdef CONFIG_SPI_COLDFIRE_QSPI +#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) static void __init m5249_qspi_init(void) { @@ -61,7 +71,7 @@ static void __init m5249_qspi_init(void) mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI); } -#endif /* CONFIG_SPI_COLDFIRE_QSPI */ +#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */ /***************************************************************************/ @@ -90,7 +100,7 @@ void __init config_BSP(char *commandp, int size) #ifdef CONFIG_M5249C3 m5249_smc91x_init(); #endif -#ifdef CONFIG_SPI_COLDFIRE_QSPI +#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) m5249_qspi_init(); #endif } diff --git a/arch/m68k/platform/5272/config.c b/arch/m68k/platform/coldfire/m5272.c index e68bc7a148eb..43e36060da18 100644 --- a/arch/m68k/platform/5272/config.c +++ b/arch/m68k/platform/coldfire/m5272.c @@ -19,6 +19,7 @@ #include <asm/coldfire.h> #include <asm/mcfsim.h> #include <asm/mcfuart.h> +#include <asm/mcfgpio.h> /***************************************************************************/ @@ -30,6 +31,16 @@ unsigned char ledbank = 0xff; /***************************************************************************/ +struct mcf_gpio_chip mcf_gpio_chips[] = { + MCFGPS(PA, 0, 16, MCFSIM_PADDR, MCFSIM_PADAT, MCFSIM_PADAT), + MCFGPS(PB, 16, 16, MCFSIM_PBDDR, MCFSIM_PBDAT, MCFSIM_PBDAT), + MCFGPS(Pc, 32, 16, MCFSIM_PCDDR, MCFSIM_PCDAT, MCFSIM_PCDAT), +}; + +unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips); + +/***************************************************************************/ + static void __init m5272_uarts_init(void) { u32 v; diff --git a/arch/m68k/platform/527x/config.c b/arch/m68k/platform/coldfire/m527x.c index 7ed848c3b848..9b0b66aabd1b 100644 --- a/arch/m68k/platform/527x/config.c +++ b/arch/m68k/platform/coldfire/m527x.c @@ -20,10 +20,53 @@ #include <asm/coldfire.h> #include <asm/mcfsim.h> #include <asm/mcfuart.h> +#include <asm/mcfgpio.h> /***************************************************************************/ -#ifdef CONFIG_SPI_COLDFIRE_QSPI +struct mcf_gpio_chip mcf_gpio_chips[] = { +#if defined(CONFIG_M5271) + MCFGPS(PIRQ, 1, 7, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR), + MCFGPF(ADDR, 13, 3), + MCFGPF(DATAH, 16, 8), + MCFGPF(DATAL, 24, 8), + MCFGPF(BUSCTL, 32, 8), + MCFGPF(BS, 40, 4), + MCFGPF(CS, 49, 7), + MCFGPF(SDRAM, 56, 6), + MCFGPF(FECI2C, 64, 4), + MCFGPF(UARTH, 72, 2), + MCFGPF(UARTL, 80, 8), + MCFGPF(QSPI, 88, 5), + MCFGPF(TIMER, 96, 8), +#elif defined(CONFIG_M5275) + MCFGPS(PIRQ, 1, 7, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR), + MCFGPF(BUSCTL, 8, 8), + MCFGPF(ADDR, 21, 3), + MCFGPF(CS, 25, 7), + MCFGPF(FEC0H, 32, 8), + MCFGPF(FEC0L, 40, 8), + MCFGPF(FECI2C, 48, 6), + MCFGPF(QSPI, 56, 7), + MCFGPF(SDRAM, 64, 8), + MCFGPF(TIMERH, 72, 4), + MCFGPF(TIMERL, 80, 4), + MCFGPF(UARTL, 88, 8), + MCFGPF(FEC1H, 96, 8), + MCFGPF(FEC1L, 104, 8), + MCFGPF(BS, 114, 2), + MCFGPF(IRQ, 121, 7), + MCFGPF(USBH, 128, 1), + MCFGPF(USBL, 136, 8), + MCFGPF(UARTH, 144, 4), +#endif +}; + +unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips); + +/***************************************************************************/ + +#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) static void __init m527x_qspi_init(void) { @@ -42,7 +85,7 @@ static void __init m527x_qspi_init(void) #endif } -#endif /* CONFIG_SPI_COLDFIRE_QSPI */ +#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */ /***************************************************************************/ @@ -74,9 +117,7 @@ static void __init m527x_fec_init(void) writew(par | 0xf00, MCF_IPSBAR + 0x100082); v = readb(MCF_IPSBAR + 0x100078); writeb(v | 0xc0, MCF_IPSBAR + 0x100078); -#endif -#ifdef CONFIG_FEC2 /* Set multi-function pins to ethernet mode for fec1 */ par = readw(MCF_IPSBAR + 0x100082); writew(par | 0xa0, MCF_IPSBAR + 0x100082); @@ -92,7 +133,7 @@ void __init config_BSP(char *commandp, int size) mach_sched_init = hw_timer_init; m527x_uarts_init(); m527x_fec_init(); -#ifdef CONFIG_SPI_COLDFIRE_QSPI +#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) m527x_qspi_init(); #endif } diff --git a/arch/m68k/platform/528x/config.c b/arch/m68k/platform/coldfire/m528x.c index d4492926614c..7ed1276b29dc 100644 --- a/arch/m68k/platform/528x/config.c +++ b/arch/m68k/platform/coldfire/m528x.c @@ -21,10 +21,41 @@ #include <asm/coldfire.h> #include <asm/mcfsim.h> #include <asm/mcfuart.h> +#include <asm/mcfgpio.h> /***************************************************************************/ -#ifdef CONFIG_SPI_COLDFIRE_QSPI +struct mcf_gpio_chip mcf_gpio_chips[] = { + MCFGPS(NQ, 1, 7, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR), + MCFGPS(TA, 8, 4, MCFGPTA_GPTDDR, MCFGPTA_GPTPORT, MCFGPTB_GPTPORT), + MCFGPS(TB, 16, 4, MCFGPTB_GPTDDR, MCFGPTB_GPTPORT, MCFGPTB_GPTPORT), + MCFGPS(QA, 24, 4, MCFQADC_DDRQA, MCFQADC_PORTQA, MCFQADC_PORTQA), + MCFGPS(QB, 32, 4, MCFQADC_DDRQB, MCFQADC_PORTQB, MCFQADC_PORTQB), + MCFGPF(A, 40, 8), + MCFGPF(B, 48, 8), + MCFGPF(C, 56, 8), + MCFGPF(D, 64, 8), + MCFGPF(E, 72, 8), + MCFGPF(F, 80, 8), + MCFGPF(G, 88, 8), + MCFGPF(H, 96, 8), + MCFGPF(J, 104, 8), + MCFGPF(DD, 112, 8), + MCFGPF(EH, 120, 8), + MCFGPF(EL, 128, 8), + MCFGPF(AS, 136, 6), + MCFGPF(QS, 144, 7), + MCFGPF(SD, 152, 6), + MCFGPF(TC, 160, 4), + MCFGPF(TD, 168, 4), + MCFGPF(UA, 176, 4), +}; + +unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips); + +/***************************************************************************/ + +#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) static void __init m528x_qspi_init(void) { @@ -32,7 +63,7 @@ static void __init m528x_qspi_init(void) __raw_writeb(0x07, MCFGPIO_PQSPAR); } -#endif /* CONFIG_SPI_COLDFIRE_QSPI */ +#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */ /***************************************************************************/ @@ -98,7 +129,7 @@ void __init config_BSP(char *commandp, int size) mach_sched_init = hw_timer_init; m528x_uarts_init(); m528x_fec_init(); -#ifdef CONFIG_SPI_COLDFIRE_QSPI +#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) m528x_qspi_init(); #endif } diff --git a/arch/m68k/platform/5307/config.c b/arch/m68k/platform/coldfire/m5307.c index a568d2870d15..93b484976ab3 100644 --- a/arch/m68k/platform/5307/config.c +++ b/arch/m68k/platform/coldfire/m5307.c @@ -16,6 +16,7 @@ #include <asm/machdep.h> #include <asm/coldfire.h> #include <asm/mcfsim.h> +#include <asm/mcfgpio.h> #include <asm/mcfwdebug.h> /***************************************************************************/ @@ -28,6 +29,14 @@ unsigned char ledbank = 0xff; /***************************************************************************/ +struct mcf_gpio_chip mcf_gpio_chips[] = { + MCFGPS(PP, 0, 16, MCFSIM_PADDR, MCFSIM_PADAT, MCFSIM_PADAT), +}; + +unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips); + +/***************************************************************************/ + void __init config_BSP(char *commandp, int size) { #if defined(CONFIG_NETtel) || \ diff --git a/arch/m68k/platform/532x/config.c b/arch/m68k/platform/coldfire/m532x.c index 2bec3477b739..8e9476d59a65 100644 --- a/arch/m68k/platform/532x/config.c +++ b/arch/m68k/platform/coldfire/m532x.c @@ -26,11 +26,36 @@ #include <asm/mcfsim.h> #include <asm/mcfuart.h> #include <asm/mcfdma.h> +#include <asm/mcfgpio.h> #include <asm/mcfwdebug.h> /***************************************************************************/ -#ifdef CONFIG_SPI_COLDFIRE_QSPI +struct mcf_gpio_chip mcf_gpio_chips[] = { + MCFGPS(PIRQ, 0, 8, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR), + MCFGPF(FECH, 8, 8), + MCFGPF(FECL, 16, 8), + MCFGPF(SSI, 24, 5), + MCFGPF(BUSCTL, 32, 4), + MCFGPF(BE, 40, 4), + MCFGPF(CS, 49, 5), + MCFGPF(PWM, 58, 4), + MCFGPF(FECI2C, 64, 4), + MCFGPF(UART, 72, 8), + MCFGPF(QSPI, 80, 6), + MCFGPF(TIMER, 88, 4), + MCFGPF(LCDDATAH, 96, 2), + MCFGPF(LCDDATAM, 104, 8), + MCFGPF(LCDDATAL, 112, 8), + MCFGPF(LCDCTLH, 120, 1), + MCFGPF(LCDCTLL, 128, 8), +}; + +unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips); + +/***************************************************************************/ + +#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) static void __init m532x_qspi_init(void) { @@ -38,7 +63,7 @@ static void __init m532x_qspi_init(void) writew(0x01f0, MCF_GPIO_PAR_QSPI); } -#endif /* CONFIG_SPI_COLDFIRE_QSPI */ +#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */ /***************************************************************************/ @@ -77,7 +102,7 @@ void __init config_BSP(char *commandp, int size) mach_sched_init = hw_timer_init; m532x_uarts_init(); m532x_fec_init(); -#ifdef CONFIG_SPI_COLDFIRE_QSPI +#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) m532x_qspi_init(); #endif diff --git a/arch/m68k/platform/5407/config.c b/arch/m68k/platform/coldfire/m5407.c index bb6c746ae819..faa6680b3404 100644 --- a/arch/m68k/platform/5407/config.c +++ b/arch/m68k/platform/coldfire/m5407.c @@ -16,6 +16,15 @@ #include <asm/machdep.h> #include <asm/coldfire.h> #include <asm/mcfsim.h> +#include <asm/mcfgpio.h> + +/***************************************************************************/ + +struct mcf_gpio_chip mcf_gpio_chips[] = { + MCFGPS(PP, 0, 16, MCFSIM_PADDR, MCFSIM_PADAT, MCFSIM_PADAT), +}; + +unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips); /***************************************************************************/ diff --git a/arch/m68k/platform/54xx/config.c b/arch/m68k/platform/coldfire/m54xx.c index 2081c6cbb3de..20672dadb252 100644 --- a/arch/m68k/platform/54xx/config.c +++ b/arch/m68k/platform/coldfire/m54xx.c @@ -21,12 +21,19 @@ #include <asm/m54xxsim.h> #include <asm/mcfuart.h> #include <asm/m54xxgpt.h> +#include <asm/mcfgpio.h> #ifdef CONFIG_MMU #include <asm/mmu_context.h> #endif /***************************************************************************/ +struct mcf_gpio_chip mcf_gpio_chips[] = { }; + +unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips); + +/***************************************************************************/ + static void __init m54xx_uarts_init(void) { /* enable io pins */ diff --git a/arch/m68k/platform/5307/nettel.c b/arch/m68k/platform/coldfire/nettel.c index e925ea4602f8..e925ea4602f8 100644 --- a/arch/m68k/platform/5307/nettel.c +++ b/arch/m68k/platform/coldfire/nettel.c diff --git a/arch/microblaze/pci/pci-common.c b/arch/microblaze/pci/pci-common.c index d10403dadd2b..ed22bfc5db14 100644 --- a/arch/microblaze/pci/pci-common.c +++ b/arch/microblaze/pci/pci-common.c @@ -1422,6 +1422,7 @@ int pcibios_enable_device(struct pci_dev *dev, int mask) static void __devinit pcibios_setup_phb_resources(struct pci_controller *hose, struct list_head *resources) { + unsigned long io_offset; struct resource *res; int i; diff --git a/arch/mips/ath79/dev-wmac.c b/arch/mips/ath79/dev-wmac.c index e21507052066..9c717bf98ffe 100644 --- a/arch/mips/ath79/dev-wmac.c +++ b/arch/mips/ath79/dev-wmac.c @@ -58,8 +58,8 @@ static void __init ar913x_wmac_setup(void) static int ar933x_wmac_reset(void) { - ath79_device_reset_clear(AR933X_RESET_WMAC); ath79_device_reset_set(AR933X_RESET_WMAC); + ath79_device_reset_clear(AR933X_RESET_WMAC); return 0; } diff --git a/arch/mips/configs/mtx1_defconfig b/arch/mips/configs/mtx1_defconfig index 807c97eed8a8..46c61edcdf7b 100644 --- a/arch/mips/configs/mtx1_defconfig +++ b/arch/mips/configs/mtx1_defconfig @@ -346,11 +346,8 @@ CONFIG_CHELSIO_T1=m CONFIG_IXGB=m CONFIG_S2IO=m CONFIG_MYRI10GE=m -CONFIG_TR=y CONFIG_IBMOL=m CONFIG_IBMLS=m -CONFIG_3C359=m -CONFIG_TMS380TR=m CONFIG_TMSPCI=m CONFIG_ABYSS=m CONFIG_USB_CATC=m @@ -376,7 +373,6 @@ CONFIG_PCMCIA_SMC91C92=m CONFIG_PCMCIA_XIRC2PS=m CONFIG_PCMCIA_AXNET=m CONFIG_ARCNET_COM20020_CS=m -CONFIG_PCMCIA_IBMTR=m CONFIG_WAN=y CONFIG_LANMEDIA=m CONFIG_HDLC=m diff --git a/arch/mips/include/asm/mach-jz4740/irq.h b/arch/mips/include/asm/mach-jz4740/irq.h index a865c983c70a..5ad1a9c113c6 100644 --- a/arch/mips/include/asm/mach-jz4740/irq.h +++ b/arch/mips/include/asm/mach-jz4740/irq.h @@ -45,7 +45,7 @@ #define JZ4740_IRQ_LCD JZ4740_IRQ(30) /* 2nd-level interrupts */ -#define JZ4740_IRQ_DMA(x) (JZ4740_IRQ(32) + (X)) +#define JZ4740_IRQ_DMA(x) (JZ4740_IRQ(32) + (x)) #define JZ4740_IRQ_INTC_GPIO(x) (JZ4740_IRQ_GPIO0 - (x)) #define JZ4740_IRQ_GPIO(x) (JZ4740_IRQ(48) + (x)) diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h index 73c0d45798de..9b02cfba7449 100644 --- a/arch/mips/include/asm/mmu_context.h +++ b/arch/mips/include/asm/mmu_context.h @@ -37,12 +37,6 @@ extern void tlbmiss_handler_setup_pgd(unsigned long pgd); write_c0_xcontext((unsigned long) smp_processor_id() << 51); \ } while (0) - -static inline unsigned long get_current_pgd(void) -{ - return PHYS_TO_XKSEG_CACHED((read_c0_context() >> 11) & ~0xfffUL); -} - #else /* CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/ /* diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c index 185ca00c4c84..d5a338a1739c 100644 --- a/arch/mips/kernel/signal.c +++ b/arch/mips/kernel/signal.c @@ -257,11 +257,8 @@ asmlinkage int sys_sigsuspend(nabi_no_regargs struct pt_regs regs) return -EFAULT; sigdelsetmask(&newset, ~_BLOCKABLE); - spin_lock_irq(¤t->sighand->siglock); current->saved_sigmask = current->blocked; - current->blocked = newset; - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); + set_current_blocked(&newset); current->state = TASK_INTERRUPTIBLE; schedule(); @@ -286,11 +283,8 @@ asmlinkage int sys_rt_sigsuspend(nabi_no_regargs struct pt_regs regs) return -EFAULT; sigdelsetmask(&newset, ~_BLOCKABLE); - spin_lock_irq(¤t->sighand->siglock); current->saved_sigmask = current->blocked; - current->blocked = newset; - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); + set_current_blocked(&newset); current->state = TASK_INTERRUPTIBLE; schedule(); @@ -362,10 +356,7 @@ asmlinkage void sys_sigreturn(nabi_no_regargs struct pt_regs regs) goto badframe; sigdelsetmask(&blocked, ~_BLOCKABLE); - spin_lock_irq(¤t->sighand->siglock); - current->blocked = blocked; - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); + set_current_blocked(&blocked); sig = restore_sigcontext(®s, &frame->sf_sc); if (sig < 0) @@ -401,10 +392,7 @@ asmlinkage void sys_rt_sigreturn(nabi_no_regargs struct pt_regs regs) goto badframe; sigdelsetmask(&set, ~_BLOCKABLE); - spin_lock_irq(¤t->sighand->siglock); - current->blocked = set; - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); + set_current_blocked(&set); sig = restore_sigcontext(®s, &frame->rs_uc.uc_mcontext); if (sig < 0) @@ -580,12 +568,7 @@ static int handle_signal(unsigned long sig, siginfo_t *info, if (ret) return ret; - spin_lock_irq(¤t->sighand->siglock); - sigorsets(¤t->blocked, ¤t->blocked, &ka->sa.sa_mask); - if (!(ka->sa.sa_flags & SA_NODEFER)) - sigaddset(¤t->blocked, sig); - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); + block_sigmask(ka, sig); return ret; } diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c index 06b5da392e24..ac3b8d89aae5 100644 --- a/arch/mips/kernel/signal32.c +++ b/arch/mips/kernel/signal32.c @@ -290,11 +290,8 @@ asmlinkage int sys32_sigsuspend(nabi_no_regargs struct pt_regs regs) return -EFAULT; sigdelsetmask(&newset, ~_BLOCKABLE); - spin_lock_irq(¤t->sighand->siglock); current->saved_sigmask = current->blocked; - current->blocked = newset; - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); + set_current_blocked(&newset); current->state = TASK_INTERRUPTIBLE; schedule(); @@ -318,11 +315,8 @@ asmlinkage int sys32_rt_sigsuspend(nabi_no_regargs struct pt_regs regs) return -EFAULT; sigdelsetmask(&newset, ~_BLOCKABLE); - spin_lock_irq(¤t->sighand->siglock); current->saved_sigmask = current->blocked; - current->blocked = newset; - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); + set_current_blocked(&newset); current->state = TASK_INTERRUPTIBLE; schedule(); @@ -488,10 +482,7 @@ asmlinkage void sys32_sigreturn(nabi_no_regargs struct pt_regs regs) goto badframe; sigdelsetmask(&blocked, ~_BLOCKABLE); - spin_lock_irq(¤t->sighand->siglock); - current->blocked = blocked; - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); + set_current_blocked(&blocked); sig = restore_sigcontext32(®s, &frame->sf_sc); if (sig < 0) @@ -529,10 +520,7 @@ asmlinkage void sys32_rt_sigreturn(nabi_no_regargs struct pt_regs regs) goto badframe; sigdelsetmask(&set, ~_BLOCKABLE); - spin_lock_irq(¤t->sighand->siglock); - current->blocked = set; - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); + set_current_blocked(&set); sig = restore_sigcontext32(®s, &frame->rs_uc.uc_mcontext); if (sig < 0) diff --git a/arch/mips/kernel/signal_n32.c b/arch/mips/kernel/signal_n32.c index ae29e894ab8d..86eb4b04631c 100644 --- a/arch/mips/kernel/signal_n32.c +++ b/arch/mips/kernel/signal_n32.c @@ -93,11 +93,8 @@ asmlinkage int sysn32_rt_sigsuspend(nabi_no_regargs struct pt_regs regs) sigset_from_compat(&newset, &uset); sigdelsetmask(&newset, ~_BLOCKABLE); - spin_lock_irq(¤t->sighand->siglock); current->saved_sigmask = current->blocked; - current->blocked = newset; - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); + set_current_blocked(&newset); current->state = TASK_INTERRUPTIBLE; schedule(); @@ -121,10 +118,7 @@ asmlinkage void sysn32_rt_sigreturn(nabi_no_regargs struct pt_regs regs) goto badframe; sigdelsetmask(&set, ~_BLOCKABLE); - spin_lock_irq(¤t->sighand->siglock); - current->blocked = set; - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); + set_current_blocked(&set); sig = restore_sigcontext(®s, &frame->rs_uc.uc_mcontext); if (sig < 0) diff --git a/arch/mn10300/kernel/smp.c b/arch/mn10300/kernel/smp.c index 910dddf65e44..9cd69ad6aa02 100644 --- a/arch/mn10300/kernel/smp.c +++ b/arch/mn10300/kernel/smp.c @@ -24,6 +24,7 @@ #include <linux/sched.h> #include <linux/profile.h> #include <linux/smp.h> +#include <linux/cpu.h> #include <asm/tlbflush.h> #include <asm/bitops.h> #include <asm/processor.h> @@ -38,7 +39,6 @@ #include "internal.h" #ifdef CONFIG_HOTPLUG_CPU -#include <linux/cpu.h> #include <asm/cacheflush.h> static unsigned long sleep_mode[NR_CPUS]; @@ -874,10 +874,13 @@ static void __init smp_online(void) cpu = smp_processor_id(); - local_irq_enable(); + notify_cpu_starting(cpu); + ipi_call_lock(); set_cpu_online(cpu, true); - smp_wmb(); + ipi_call_unlock(); + + local_irq_enable(); } /** diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig index a4787197d8fe..7589051e79e0 100644 --- a/arch/openrisc/Kconfig +++ b/arch/openrisc/Kconfig @@ -7,6 +7,7 @@ config OPENRISC def_bool y select OF select OF_EARLY_FLATTREE + select IRQ_DOMAIN select HAVE_MEMBLOCK select ARCH_WANT_OPTIONAL_GPIOLIB select HAVE_ARCH_TRACEHOOK diff --git a/arch/openrisc/include/asm/Kbuild b/arch/openrisc/include/asm/Kbuild index dcea5a0308ae..c936483bc8e2 100644 --- a/arch/openrisc/include/asm/Kbuild +++ b/arch/openrisc/include/asm/Kbuild @@ -1,6 +1,7 @@ include include/asm-generic/Kbuild.asm -header-y += spr_defs.h +header-y += elf.h +header-y += ucontext.h generic-y += atomic.h generic-y += auxvec.h diff --git a/arch/openrisc/include/asm/dma-mapping.h b/arch/openrisc/include/asm/dma-mapping.h index b206ba4608b2..fab8628e1b6e 100644 --- a/arch/openrisc/include/asm/dma-mapping.h +++ b/arch/openrisc/include/asm/dma-mapping.h @@ -20,150 +20,71 @@ /* * See Documentation/DMA-API-HOWTO.txt and * Documentation/DMA-API.txt for documentation. - * - * This file is written with the intention of eventually moving over - * to largely using asm-generic/dma-mapping-common.h in its place. */ #include <linux/dma-debug.h> #include <asm-generic/dma-coherent.h> #include <linux/kmemcheck.h> +#include <linux/dma-mapping.h> #define DMA_ERROR_CODE (~(dma_addr_t)0x0) +extern struct dma_map_ops or1k_dma_map_ops; -#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f) -#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h) - -void *or1k_dma_alloc_coherent(struct device *dev, size_t size, - dma_addr_t *dma_handle, gfp_t flag); -void or1k_dma_free_coherent(struct device *dev, size_t size, void *vaddr, - dma_addr_t dma_handle); -dma_addr_t or1k_map_page(struct device *dev, struct page *page, - unsigned long offset, size_t size, - enum dma_data_direction dir, - struct dma_attrs *attrs); -void or1k_unmap_page(struct device *dev, dma_addr_t dma_handle, - size_t size, enum dma_data_direction dir, - struct dma_attrs *attrs); -int or1k_map_sg(struct device *dev, struct scatterlist *sg, - int nents, enum dma_data_direction dir, - struct dma_attrs *attrs); -void or1k_unmap_sg(struct device *dev, struct scatterlist *sg, - int nents, enum dma_data_direction dir, - struct dma_attrs *attrs); -void or1k_sync_single_for_cpu(struct device *dev, - dma_addr_t dma_handle, size_t size, - enum dma_data_direction dir); -void or1k_sync_single_for_device(struct device *dev, - dma_addr_t dma_handle, size_t size, - enum dma_data_direction dir); - -static inline void *dma_alloc_coherent(struct device *dev, size_t size, - dma_addr_t *dma_handle, gfp_t flag) +static inline struct dma_map_ops *get_dma_ops(struct device *dev) { - void *memory; - - memory = or1k_dma_alloc_coherent(dev, size, dma_handle, flag); - - debug_dma_alloc_coherent(dev, size, *dma_handle, memory); - return memory; + return &or1k_dma_map_ops; } -static inline void dma_free_coherent(struct device *dev, size_t size, - void *cpu_addr, dma_addr_t dma_handle) -{ - debug_dma_free_coherent(dev, size, cpu_addr, dma_handle); - or1k_dma_free_coherent(dev, size, cpu_addr, dma_handle); -} +#include <asm-generic/dma-mapping-common.h> -static inline dma_addr_t dma_map_single(struct device *dev, void *ptr, - size_t size, - enum dma_data_direction dir) -{ - dma_addr_t addr; - - kmemcheck_mark_initialized(ptr, size); - BUG_ON(!valid_dma_direction(dir)); - addr = or1k_map_page(dev, virt_to_page(ptr), - (unsigned long)ptr & ~PAGE_MASK, size, - dir, NULL); - debug_dma_map_page(dev, virt_to_page(ptr), - (unsigned long)ptr & ~PAGE_MASK, size, - dir, addr, true); - return addr; -} +#define dma_alloc_coherent(d,s,h,f) dma_alloc_attrs(d,s,h,f,NULL) -static inline void dma_unmap_single(struct device *dev, dma_addr_t addr, - size_t size, - enum dma_data_direction dir) +static inline void *dma_alloc_attrs(struct device *dev, size_t size, + dma_addr_t *dma_handle, gfp_t gfp, + struct dma_attrs *attrs) { - BUG_ON(!valid_dma_direction(dir)); - or1k_unmap_page(dev, addr, size, dir, NULL); - debug_dma_unmap_page(dev, addr, size, dir, true); -} + struct dma_map_ops *ops = get_dma_ops(dev); + void *memory; -static inline int dma_map_sg(struct device *dev, struct scatterlist *sg, - int nents, enum dma_data_direction dir) -{ - int i, ents; - struct scatterlist *s; + memory = ops->alloc(dev, size, dma_handle, gfp, attrs); - for_each_sg(sg, s, nents, i) - kmemcheck_mark_initialized(sg_virt(s), s->length); - BUG_ON(!valid_dma_direction(dir)); - ents = or1k_map_sg(dev, sg, nents, dir, NULL); - debug_dma_map_sg(dev, sg, nents, ents, dir); + debug_dma_alloc_coherent(dev, size, *dma_handle, memory); - return ents; + return memory; } -static inline void dma_unmap_sg(struct device *dev, struct scatterlist *sg, - int nents, enum dma_data_direction dir) -{ - BUG_ON(!valid_dma_direction(dir)); - debug_dma_unmap_sg(dev, sg, nents, dir); - or1k_unmap_sg(dev, sg, nents, dir, NULL); -} +#define dma_free_coherent(d,s,c,h) dma_free_attrs(d,s,c,h,NULL) -static inline dma_addr_t dma_map_page(struct device *dev, struct page *page, - size_t offset, size_t size, - enum dma_data_direction dir) +static inline void dma_free_attrs(struct device *dev, size_t size, + void *cpu_addr, dma_addr_t dma_handle, + struct dma_attrs *attrs) { - dma_addr_t addr; + struct dma_map_ops *ops = get_dma_ops(dev); - kmemcheck_mark_initialized(page_address(page) + offset, size); - BUG_ON(!valid_dma_direction(dir)); - addr = or1k_map_page(dev, page, offset, size, dir, NULL); - debug_dma_map_page(dev, page, offset, size, dir, addr, false); + debug_dma_free_coherent(dev, size, cpu_addr, dma_handle); - return addr; + ops->free(dev, size, cpu_addr, dma_handle, attrs); } -static inline void dma_unmap_page(struct device *dev, dma_addr_t addr, - size_t size, enum dma_data_direction dir) +static inline void *dma_alloc_noncoherent(struct device *dev, size_t size, + dma_addr_t *dma_handle, gfp_t gfp) { - BUG_ON(!valid_dma_direction(dir)); - or1k_unmap_page(dev, addr, size, dir, NULL); - debug_dma_unmap_page(dev, addr, size, dir, true); -} + struct dma_attrs attrs; -static inline void dma_sync_single_for_cpu(struct device *dev, dma_addr_t addr, - size_t size, - enum dma_data_direction dir) -{ - BUG_ON(!valid_dma_direction(dir)); - or1k_sync_single_for_cpu(dev, addr, size, dir); - debug_dma_sync_single_for_cpu(dev, addr, size, dir); + dma_set_attr(DMA_ATTR_NON_CONSISTENT, &attrs); + + return dma_alloc_attrs(dev, size, dma_handle, gfp, &attrs); } -static inline void dma_sync_single_for_device(struct device *dev, - dma_addr_t addr, size_t size, - enum dma_data_direction dir) +static inline void dma_free_noncoherent(struct device *dev, size_t size, + void *cpu_addr, dma_addr_t dma_handle) { - BUG_ON(!valid_dma_direction(dir)); - or1k_sync_single_for_device(dev, addr, size, dir); - debug_dma_sync_single_for_device(dev, addr, size, dir); + struct dma_attrs attrs; + + dma_set_attr(DMA_ATTR_NON_CONSISTENT, &attrs); + + dma_free_attrs(dev, size, cpu_addr, dma_handle, &attrs); } static inline int dma_supported(struct device *dev, u64 dma_mask) diff --git a/arch/openrisc/include/asm/elf.h b/arch/openrisc/include/asm/elf.h index 2ce603bbfdd3..a8fe2c513070 100644 --- a/arch/openrisc/include/asm/elf.h +++ b/arch/openrisc/include/asm/elf.h @@ -20,11 +20,17 @@ #define __ASM_OPENRISC_ELF_H /* + * This files is partially exported to userspace. This allows us to keep + * the ELF bits in one place which should assist in keeping the kernel and + * userspace in sync. + */ + +/* * ELF register definitions.. */ -#include <linux/types.h> -#include <linux/ptrace.h> +/* for struct user_regs_struct definition */ +#include <asm/ptrace.h> /* The OR1K relocation types... not all relevant for module loader */ #define R_OR32_NONE 0 @@ -62,6 +68,8 @@ typedef unsigned long elf_fpregset_t; #ifdef __KERNEL__ +#include <linux/types.h> + /* * This is used to ensure we don't load something for the wrong architecture. */ diff --git a/arch/openrisc/include/asm/ptrace.h b/arch/openrisc/include/asm/ptrace.h index 4651a737591d..8555c0c3d4d7 100644 --- a/arch/openrisc/include/asm/ptrace.h +++ b/arch/openrisc/include/asm/ptrace.h @@ -19,8 +19,6 @@ #ifndef __ASM_OPENRISC_PTRACE_H #define __ASM_OPENRISC_PTRACE_H -#include <asm/spr_defs.h> - #ifndef __ASSEMBLY__ /* * This is the layout of the regset returned by the GETREGSET ptrace call @@ -30,13 +28,13 @@ struct user_regs_struct { unsigned long gpr[32]; unsigned long pc; unsigned long sr; - unsigned long pad1; - unsigned long pad2; }; #endif #ifdef __KERNEL__ +#include <asm/spr_defs.h> + /* * Make kernel PTrace/register structures opaque to userspace... userspace can * access thread state via the regset mechanism. This allows us a bit of diff --git a/arch/openrisc/kernel/dma.c b/arch/openrisc/kernel/dma.c index f1c8ee2895d0..0b77ddb1ee07 100644 --- a/arch/openrisc/kernel/dma.c +++ b/arch/openrisc/kernel/dma.c @@ -21,13 +21,16 @@ #include <linux/dma-mapping.h> #include <linux/dma-debug.h> +#include <linux/export.h> +#include <linux/dma-attrs.h> #include <asm/cpuinfo.h> #include <asm/spr_defs.h> #include <asm/tlbflush.h> -static int page_set_nocache(pte_t *pte, unsigned long addr, - unsigned long next, struct mm_walk *walk) +static int +page_set_nocache(pte_t *pte, unsigned long addr, + unsigned long next, struct mm_walk *walk) { unsigned long cl; @@ -46,8 +49,9 @@ static int page_set_nocache(pte_t *pte, unsigned long addr, return 0; } -static int page_clear_nocache(pte_t *pte, unsigned long addr, - unsigned long next, struct mm_walk *walk) +static int +page_clear_nocache(pte_t *pte, unsigned long addr, + unsigned long next, struct mm_walk *walk) { pte_val(*pte) &= ~_PAGE_CI; @@ -67,9 +71,19 @@ static int page_clear_nocache(pte_t *pte, unsigned long addr, * cache-inhibit bit on those pages, and makes sure that the pages are * flushed out of the cache before they are used. * + * If the NON_CONSISTENT attribute is set, then this function just + * returns "normal", cachable memory. + * + * There are additional flags WEAK_ORDERING and WRITE_COMBINE to take + * into consideration here, too. All current known implementations of + * the OR1K support only strongly ordered memory accesses, so that flag + * is being ignored for now; uncached but write-combined memory is a + * missing feature of the OR1K. */ -void *or1k_dma_alloc_coherent(struct device *dev, size_t size, - dma_addr_t *dma_handle, gfp_t gfp) +static void * +or1k_dma_alloc(struct device *dev, size_t size, + dma_addr_t *dma_handle, gfp_t gfp, + struct dma_attrs *attrs) { unsigned long va; void *page; @@ -87,20 +101,23 @@ void *or1k_dma_alloc_coherent(struct device *dev, size_t size, va = (unsigned long)page; - /* - * We need to iterate through the pages, clearing the dcache for - * them and setting the cache-inhibit bit. - */ - if (walk_page_range(va, va + size, &walk)) { - free_pages_exact(page, size); - return NULL; + if (!dma_get_attr(DMA_ATTR_NON_CONSISTENT, attrs)) { + /* + * We need to iterate through the pages, clearing the dcache for + * them and setting the cache-inhibit bit. + */ + if (walk_page_range(va, va + size, &walk)) { + free_pages_exact(page, size); + return NULL; + } } return (void *)va; } -void or1k_dma_free_coherent(struct device *dev, size_t size, void *vaddr, - dma_addr_t dma_handle) +static void +or1k_dma_free(struct device *dev, size_t size, void *vaddr, + dma_addr_t dma_handle, struct dma_attrs *attrs) { unsigned long va = (unsigned long)vaddr; struct mm_walk walk = { @@ -108,16 +125,19 @@ void or1k_dma_free_coherent(struct device *dev, size_t size, void *vaddr, .mm = &init_mm }; - /* walk_page_range shouldn't be able to fail here */ - WARN_ON(walk_page_range(va, va + size, &walk)); + if (!dma_get_attr(DMA_ATTR_NON_CONSISTENT, attrs)) { + /* walk_page_range shouldn't be able to fail here */ + WARN_ON(walk_page_range(va, va + size, &walk)); + } free_pages_exact(vaddr, size); } -dma_addr_t or1k_map_page(struct device *dev, struct page *page, - unsigned long offset, size_t size, - enum dma_data_direction dir, - struct dma_attrs *attrs) +static dma_addr_t +or1k_map_page(struct device *dev, struct page *page, + unsigned long offset, size_t size, + enum dma_data_direction dir, + struct dma_attrs *attrs) { unsigned long cl; dma_addr_t addr = page_to_phys(page) + offset; @@ -147,16 +167,18 @@ dma_addr_t or1k_map_page(struct device *dev, struct page *page, return addr; } -void or1k_unmap_page(struct device *dev, dma_addr_t dma_handle, - size_t size, enum dma_data_direction dir, - struct dma_attrs *attrs) +static void +or1k_unmap_page(struct device *dev, dma_addr_t dma_handle, + size_t size, enum dma_data_direction dir, + struct dma_attrs *attrs) { /* Nothing special to do here... */ } -int or1k_map_sg(struct device *dev, struct scatterlist *sg, - int nents, enum dma_data_direction dir, - struct dma_attrs *attrs) +static int +or1k_map_sg(struct device *dev, struct scatterlist *sg, + int nents, enum dma_data_direction dir, + struct dma_attrs *attrs) { struct scatterlist *s; int i; @@ -169,9 +191,10 @@ int or1k_map_sg(struct device *dev, struct scatterlist *sg, return nents; } -void or1k_unmap_sg(struct device *dev, struct scatterlist *sg, - int nents, enum dma_data_direction dir, - struct dma_attrs *attrs) +static void +or1k_unmap_sg(struct device *dev, struct scatterlist *sg, + int nents, enum dma_data_direction dir, + struct dma_attrs *attrs) { struct scatterlist *s; int i; @@ -181,9 +204,10 @@ void or1k_unmap_sg(struct device *dev, struct scatterlist *sg, } } -void or1k_sync_single_for_cpu(struct device *dev, - dma_addr_t dma_handle, size_t size, - enum dma_data_direction dir) +static void +or1k_sync_single_for_cpu(struct device *dev, + dma_addr_t dma_handle, size_t size, + enum dma_data_direction dir) { unsigned long cl; dma_addr_t addr = dma_handle; @@ -193,9 +217,10 @@ void or1k_sync_single_for_cpu(struct device *dev, mtspr(SPR_DCBIR, cl); } -void or1k_sync_single_for_device(struct device *dev, - dma_addr_t dma_handle, size_t size, - enum dma_data_direction dir) +static void +or1k_sync_single_for_device(struct device *dev, + dma_addr_t dma_handle, size_t size, + enum dma_data_direction dir) { unsigned long cl; dma_addr_t addr = dma_handle; @@ -205,6 +230,18 @@ void or1k_sync_single_for_device(struct device *dev, mtspr(SPR_DCBFR, cl); } +struct dma_map_ops or1k_dma_map_ops = { + .alloc = or1k_dma_alloc, + .free = or1k_dma_free, + .map_page = or1k_map_page, + .unmap_page = or1k_unmap_page, + .map_sg = or1k_map_sg, + .unmap_sg = or1k_unmap_sg, + .sync_single_for_cpu = or1k_sync_single_for_cpu, + .sync_single_for_device = or1k_sync_single_for_device, +}; +EXPORT_SYMBOL(or1k_dma_map_ops); + /* Number of entries preallocated for DMA-API debugging */ #define PREALLOC_DMA_DEBUG_ENTRIES (1 << 16) diff --git a/arch/openrisc/kernel/entry.S b/arch/openrisc/kernel/entry.S index 6e61af8682b8..ddfcaa828b0e 100644 --- a/arch/openrisc/kernel/entry.S +++ b/arch/openrisc/kernel/entry.S @@ -1117,10 +1117,10 @@ ENTRY(sys_rt_sigreturn) ENTRY(sys_or1k_atomic) /* FIXME: This ignores r3 and always does an XCHG */ DISABLE_INTERRUPTS(r17,r19) - l.lwz r30,0(r4) - l.lwz r28,0(r5) - l.sw 0(r4),r28 - l.sw 0(r5),r30 + l.lwz r29,0(r4) + l.lwz r27,0(r5) + l.sw 0(r4),r27 + l.sw 0(r5),r29 ENABLE_INTERRUPTS(r17) l.jr r9 l.or r11,r0,r0 diff --git a/arch/openrisc/kernel/irq.c b/arch/openrisc/kernel/irq.c index 4bfead220956..e935b9d8eee1 100644 --- a/arch/openrisc/kernel/irq.c +++ b/arch/openrisc/kernel/irq.c @@ -14,17 +14,13 @@ * 2 of the License, or (at your option) any later version. */ -#include <linux/ptrace.h> -#include <linux/errno.h> #include <linux/interrupt.h> #include <linux/init.h> #include <linux/of.h> #include <linux/ftrace.h> #include <linux/irq.h> -#include <linux/seq_file.h> -#include <linux/kernel_stat.h> #include <linux/export.h> - +#include <linux/irqdomain.h> #include <linux/irqflags.h> /* read interrupt enabled status */ @@ -98,6 +94,7 @@ static void or1k_pic_mask_ack(struct irq_data *data) #endif } +#if 0 static int or1k_pic_set_type(struct irq_data *data, unsigned int flow_type) { /* There's nothing to do in the PIC configuration when changing @@ -107,43 +104,64 @@ static int or1k_pic_set_type(struct irq_data *data, unsigned int flow_type) return irq_setup_alt_chip(data, flow_type); } +#endif + +static struct irq_chip or1k_dev = { + .name = "or1k-PIC", + .irq_unmask = or1k_pic_unmask, + .irq_mask = or1k_pic_mask, + .irq_ack = or1k_pic_ack, + .irq_mask_ack = or1k_pic_mask_ack, +}; + +static struct irq_domain *root_domain; static inline int pic_get_irq(int first) { - int irq; + int hwirq; - irq = ffs(mfspr(SPR_PICSR) >> first); + hwirq = ffs(mfspr(SPR_PICSR) >> first); + if (!hwirq) + return NO_IRQ; + else + hwirq = hwirq + first -1; - return irq ? irq + first - 1 : NO_IRQ; + return irq_find_mapping(root_domain, hwirq); } -static void __init or1k_irq_init(void) + +static int or1k_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) { - struct irq_chip_generic *gc; - struct irq_chip_type *ct; + irq_set_chip_and_handler_name(irq, &or1k_dev, + handle_level_irq, "level"); + irq_set_status_flags(irq, IRQ_LEVEL | IRQ_NOPROBE); - /* Disable all interrupts until explicitly requested */ - mtspr(SPR_PICMR, (0UL)); + return 0; +} - gc = irq_alloc_generic_chip("or1k-PIC", 1, 0, 0, handle_level_irq); - ct = gc->chip_types; +static const struct irq_domain_ops or1k_irq_domain_ops = { + .xlate = irq_domain_xlate_onecell, + .map = or1k_map, +}; - ct->chip.irq_unmask = or1k_pic_unmask; - ct->chip.irq_mask = or1k_pic_mask; - ct->chip.irq_ack = or1k_pic_ack; - ct->chip.irq_mask_ack = or1k_pic_mask_ack; - ct->chip.irq_set_type = or1k_pic_set_type; +/* + * This sets up the IRQ domain for the PIC built in to the OpenRISC + * 1000 CPU. This is the "root" domain as these are the interrupts + * that directly trigger an exception in the CPU. + */ +static void __init or1k_irq_init(void) +{ + struct device_node *intc = NULL; - /* The OR1K PIC can handle both level and edge trigged - * interrupts in roughly the same manner - */ -#if 0 - /* FIXME: chip.type??? */ - ct->chip.type = IRQ_TYPE_EDGE_BOTH | IRQ_TYPE_LEVEL_MASK; -#endif + /* The interrupt controller device node is mandatory */ + intc = of_find_compatible_node(NULL, NULL, "opencores,or1k-pic"); + BUG_ON(!intc); - irq_setup_generic_chip(gc, IRQ_MSK(NR_IRQS), 0, - IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE); + /* Disable all interrupts until explicitly requested */ + mtspr(SPR_PICMR, (0UL)); + + root_domain = irq_domain_add_linear(intc, 32, + &or1k_irq_domain_ops, NULL); } void __init init_IRQ(void) @@ -164,10 +182,3 @@ void __irq_entry do_IRQ(struct pt_regs *regs) irq_exit(); set_irq_regs(old_regs); } - -unsigned int irq_create_of_mapping(struct device_node *controller, - const u32 *intspec, unsigned int intsize) -{ - return intspec[0]; -} -EXPORT_SYMBOL_GPL(irq_create_of_mapping); diff --git a/arch/openrisc/mm/fault.c b/arch/openrisc/mm/fault.c index a5dce82f864b..40f850e9766c 100644 --- a/arch/openrisc/mm/fault.c +++ b/arch/openrisc/mm/fault.c @@ -54,6 +54,7 @@ asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long address, struct vm_area_struct *vma; siginfo_t info; int fault; + unsigned int flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE; tsk = current; @@ -105,6 +106,7 @@ asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long address, if (in_interrupt() || !mm) goto no_context; +retry: down_read(&mm->mmap_sem); vma = find_vma(mm, address); @@ -143,6 +145,7 @@ good_area: if (write_acc) { if (!(vma->vm_flags & VM_WRITE)) goto bad_area; + flags |= FAULT_FLAG_WRITE; } else { /* not present */ if (!(vma->vm_flags & (VM_READ | VM_EXEC))) @@ -159,7 +162,11 @@ good_area: * the fault. */ - fault = handle_mm_fault(mm, vma, address, write_acc); + fault = handle_mm_fault(mm, vma, address, flags); + + if ((fault & VM_FAULT_RETRY) && fatal_signal_pending(current)) + return; + if (unlikely(fault & VM_FAULT_ERROR)) { if (fault & VM_FAULT_OOM) goto out_of_memory; @@ -167,11 +174,24 @@ good_area: goto do_sigbus; BUG(); } - /*RGD modeled on Cris */ - if (fault & VM_FAULT_MAJOR) - tsk->maj_flt++; - else - tsk->min_flt++; + + if (flags & FAULT_FLAG_ALLOW_RETRY) { + /*RGD modeled on Cris */ + if (fault & VM_FAULT_MAJOR) + tsk->maj_flt++; + else + tsk->min_flt++; + if (fault & VM_FAULT_RETRY) { + flags &= ~FAULT_FLAG_ALLOW_RETRY; + + /* No need to up_read(&mm->mmap_sem) as we would + * have already released it in __lock_page_or_retry + * in mm/filemap.c. + */ + + goto retry; + } + } up_read(&mm->mmap_sem); return; diff --git a/arch/parisc/include/asm/hardware.h b/arch/parisc/include/asm/hardware.h index 4e9626836bab..d1d864b81bae 100644 --- a/arch/parisc/include/asm/hardware.h +++ b/arch/parisc/include/asm/hardware.h @@ -2,7 +2,6 @@ #define _PARISC_HARDWARE_H #include <linux/mod_devicetable.h> -#include <asm/pdc.h> #define HWTYPE_ANY_ID PA_HWTYPE_ANY_ID #define HVERSION_ANY_ID PA_HVERSION_ANY_ID @@ -95,12 +94,14 @@ struct bc_module { #define HPHW_MC 15 #define HPHW_FAULTY 31 +struct parisc_device_id; /* hardware.c: */ extern const char *parisc_hardware_description(struct parisc_device_id *id); extern enum cpu_type parisc_get_cpu_type(unsigned long hversion); struct pci_dev; +struct hardware_path; /* drivers.c: */ extern struct parisc_device *alloc_pa_dev(unsigned long hpa, diff --git a/arch/parisc/include/asm/page.h b/arch/parisc/include/asm/page.h index a84cc1f925f6..4e0e7dbf0f3f 100644 --- a/arch/parisc/include/asm/page.h +++ b/arch/parisc/include/asm/page.h @@ -160,5 +160,11 @@ extern int npmem_ranges; #include <asm-generic/memory_model.h> #include <asm-generic/getorder.h> +#include <asm/pdc.h> + +#define PAGE0 ((struct zeropage *)__PAGE_OFFSET) + +/* DEFINITION OF THE ZERO-PAGE (PAG0) */ +/* based on work by Jason Eckhardt ([email protected]) */ #endif /* _PARISC_PAGE_H */ diff --git a/arch/parisc/include/asm/pdc.h b/arch/parisc/include/asm/pdc.h index 4ca510b3c6f8..7f0f2d23059d 100644 --- a/arch/parisc/include/asm/pdc.h +++ b/arch/parisc/include/asm/pdc.h @@ -343,8 +343,6 @@ #ifdef __KERNEL__ -#include <asm/page.h> /* for __PAGE_OFFSET */ - extern int pdc_type; /* Values for pdc_type */ @@ -677,11 +675,6 @@ static inline char * os_id_to_string(u16 os_id) { #endif /* __KERNEL__ */ -#define PAGE0 ((struct zeropage *)__PAGE_OFFSET) - -/* DEFINITION OF THE ZERO-PAGE (PAG0) */ -/* based on work by Jason Eckhardt ([email protected]) */ - /* flags of the device_path */ #define PF_AUTOBOOT 0x80 #define PF_AUTOSEARCH 0x40 diff --git a/arch/parisc/include/asm/pgtable.h b/arch/parisc/include/asm/pgtable.h index 22dadeb58695..ee99f2339356 100644 --- a/arch/parisc/include/asm/pgtable.h +++ b/arch/parisc/include/asm/pgtable.h @@ -44,6 +44,8 @@ struct vm_area_struct; #endif /* !__ASSEMBLY__ */ +#include <asm/page.h> + #define pte_ERROR(e) \ printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) #define pmd_ERROR(e) \ diff --git a/arch/parisc/include/asm/prefetch.h b/arch/parisc/include/asm/prefetch.h index c5edc60c059f..1ee7c82672c1 100644 --- a/arch/parisc/include/asm/prefetch.h +++ b/arch/parisc/include/asm/prefetch.h @@ -21,7 +21,12 @@ #define ARCH_HAS_PREFETCH static inline void prefetch(const void *addr) { - __asm__("ldw 0(%0), %%r0" : : "r" (addr)); + __asm__( +#ifndef CONFIG_PA20 + /* Need to avoid prefetch of NULL on PA7300LC */ + " extrw,u,= %0,31,32,%%r0\n" +#endif + " ldw 0(%0), %%r0" : : "r" (addr)); } /* LDD is a PA2.0 addition. */ diff --git a/arch/parisc/include/asm/spinlock.h b/arch/parisc/include/asm/spinlock.h index 804aa28ab1d6..3516e0b27044 100644 --- a/arch/parisc/include/asm/spinlock.h +++ b/arch/parisc/include/asm/spinlock.h @@ -1,6 +1,8 @@ #ifndef __ASM_SPINLOCK_H #define __ASM_SPINLOCK_H +#include <asm/barrier.h> +#include <asm/ldcw.h> #include <asm/processor.h> #include <asm/spinlock_types.h> diff --git a/arch/parisc/kernel/entry.S b/arch/parisc/kernel/entry.S index 6f0594439143..535034217021 100644 --- a/arch/parisc/kernel/entry.S +++ b/arch/parisc/kernel/entry.S @@ -581,7 +581,11 @@ */ cmpiclr,= 0x01,\tmp,%r0 ldi (_PAGE_DIRTY|_PAGE_READ|_PAGE_WRITE),\prot +#ifdef CONFIG_64BIT depd,z \prot,8,7,\prot +#else + depw,z \prot,8,7,\prot +#endif /* * OK, it is in the temp alias region, check whether "from" or "to". * Check "subtle" note in pacache.S re: r23/r26. diff --git a/arch/parisc/kernel/pacache.S b/arch/parisc/kernel/pacache.S index 93ff3d90edd1..5d7218ad885c 100644 --- a/arch/parisc/kernel/pacache.S +++ b/arch/parisc/kernel/pacache.S @@ -692,7 +692,7 @@ ENTRY(flush_icache_page_asm) /* Purge any old translation */ - pitlb (%sr0,%r28) + pitlb (%sr4,%r28) ldil L%icache_stride, %r1 ldw R%icache_stride(%r1), %r1 @@ -706,27 +706,29 @@ ENTRY(flush_icache_page_asm) sub %r25, %r1, %r25 -1: fic,m %r1(%r28) - fic,m %r1(%r28) - fic,m %r1(%r28) - fic,m %r1(%r28) - fic,m %r1(%r28) - fic,m %r1(%r28) - fic,m %r1(%r28) - fic,m %r1(%r28) - fic,m %r1(%r28) - fic,m %r1(%r28) - fic,m %r1(%r28) - fic,m %r1(%r28) - fic,m %r1(%r28) - fic,m %r1(%r28) - fic,m %r1(%r28) + /* fic only has the type 26 form on PA1.1, requiring an + * explicit space specification, so use %sr4 */ +1: fic,m %r1(%sr4,%r28) + fic,m %r1(%sr4,%r28) + fic,m %r1(%sr4,%r28) + fic,m %r1(%sr4,%r28) + fic,m %r1(%sr4,%r28) + fic,m %r1(%sr4,%r28) + fic,m %r1(%sr4,%r28) + fic,m %r1(%sr4,%r28) + fic,m %r1(%sr4,%r28) + fic,m %r1(%sr4,%r28) + fic,m %r1(%sr4,%r28) + fic,m %r1(%sr4,%r28) + fic,m %r1(%sr4,%r28) + fic,m %r1(%sr4,%r28) + fic,m %r1(%sr4,%r28) cmpb,COND(<<) %r28, %r25,1b - fic,m %r1(%r28) + fic,m %r1(%sr4,%r28) sync bv %r0(%r2) - pitlb (%sr0,%r25) + pitlb (%sr4,%r25) .exit .procend diff --git a/arch/parisc/kernel/pdc_cons.c b/arch/parisc/kernel/pdc_cons.c index 4f004596a6e7..47341aa208f2 100644 --- a/arch/parisc/kernel/pdc_cons.c +++ b/arch/parisc/kernel/pdc_cons.c @@ -50,6 +50,7 @@ #include <linux/init.h> #include <linux/major.h> #include <linux/tty.h> +#include <asm/page.h> /* for PAGE0 */ #include <asm/pdc.h> /* for iodc_call() proto and friends */ static DEFINE_SPINLOCK(pdc_console_lock); @@ -104,7 +105,7 @@ static int pdc_console_tty_open(struct tty_struct *tty, struct file *filp) static void pdc_console_tty_close(struct tty_struct *tty, struct file *filp) { - if (!tty->count) { + if (tty->count == 1) { del_timer_sync(&pdc_console_timer); tty_port_tty_set(&tty_port, NULL); } diff --git a/arch/parisc/kernel/smp.c b/arch/parisc/kernel/smp.c index 0bb1d63907f8..4dc7b7942b4c 100644 --- a/arch/parisc/kernel/smp.c +++ b/arch/parisc/kernel/smp.c @@ -31,6 +31,7 @@ #include <linux/delay.h> #include <linux/bitops.h> #include <linux/ftrace.h> +#include <linux/cpu.h> #include <linux/atomic.h> #include <asm/current.h> @@ -295,8 +296,13 @@ smp_cpu_init(int cpunum) printk(KERN_CRIT "CPU#%d already initialized!\n", cpunum); machine_halt(); - } + } + + notify_cpu_starting(cpunum); + + ipi_call_lock(); set_cpu_online(cpunum, true); + ipi_call_unlock(); /* Initialise the idle task for this CPU */ atomic_inc(&init_mm.mm_count); diff --git a/arch/parisc/kernel/time.c b/arch/parisc/kernel/time.c index 7c0774397b89..70e105d62423 100644 --- a/arch/parisc/kernel/time.c +++ b/arch/parisc/kernel/time.c @@ -29,6 +29,7 @@ #include <asm/uaccess.h> #include <asm/io.h> #include <asm/irq.h> +#include <asm/page.h> #include <asm/param.h> #include <asm/pdc.h> #include <asm/led.h> diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index feab3bad6d0f..73ec03945717 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -141,7 +141,7 @@ config PPC select IRQ_FORCED_THREADING select HAVE_RCU_TABLE_FREE if SMP select HAVE_SYSCALL_TRACEPOINTS - select HAVE_BPF_JIT if (PPC64 && NET) + select HAVE_BPF_JIT if PPC64 select HAVE_ARCH_JUMP_LABEL select ARCH_HAVE_NMI_SAFE_CMPXCHG diff --git a/arch/powerpc/boot/dts/fsl/pq3-mpic-message-B.dtsi b/arch/powerpc/boot/dts/fsl/pq3-mpic-message-B.dtsi new file mode 100644 index 000000000000..1cf0b77b1efe --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/pq3-mpic-message-B.dtsi @@ -0,0 +1,43 @@ +/* + * PQ3 MPIC Message (Group B) device tree stub [ controller @ offset 0x42400 ] + * + * Copyright 2012 Freescale Semiconductor Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +message@42400 { + compatible = "fsl,mpic-v3.1-msgr"; + reg = <0x42400 0x200>; + interrupts = < + 0xb4 2 0 0 + 0xb5 2 0 0 + 0xb6 2 0 0 + 0xb7 2 0 0>; +}; diff --git a/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi b/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi index fdedf7b1fe0f..71c30eb10056 100644 --- a/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi +++ b/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi @@ -53,6 +53,16 @@ timer@41100 { 3 0 3 0>; }; +message@41400 { + compatible = "fsl,mpic-v3.1-msgr"; + reg = <0x41400 0x200>; + interrupts = < + 0xb0 2 0 0 + 0xb1 2 0 0 + 0xb2 2 0 0 + 0xb3 2 0 0>; +}; + msi@41600 { compatible = "fsl,mpic-msi"; reg = <0x41600 0x80>; diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h index 548da3aa0a30..d58fc4e4149c 100644 --- a/arch/powerpc/include/asm/exception-64s.h +++ b/arch/powerpc/include/asm/exception-64s.h @@ -288,13 +288,6 @@ label##_hv: \ /* Exception addition: Hard disable interrupts */ #define DISABLE_INTS SOFT_DISABLE_INTS(r10,r11) -/* Exception addition: Keep interrupt state */ -#define ENABLE_INTS \ - ld r11,PACAKMSR(r13); \ - ld r12,_MSR(r1); \ - rlwimi r11,r12,0,MSR_EE; \ - mtmsrd r11,1 - #define ADD_NVGPRS \ bl .save_nvgprs diff --git a/arch/powerpc/include/asm/irq.h b/arch/powerpc/include/asm/irq.h index cf417e510736..0e40843a1c6e 100644 --- a/arch/powerpc/include/asm/irq.h +++ b/arch/powerpc/include/asm/irq.h @@ -18,10 +18,6 @@ #include <linux/atomic.h> -/* Define a way to iterate across irqs. */ -#define for_each_irq(i) \ - for ((i) = 0; (i) < NR_IRQS; ++(i)) - extern atomic_t ppc_n_lost_interrupts; /* This number is used when no interrupt has been assigned */ @@ -33,8 +29,6 @@ extern atomic_t ppc_n_lost_interrupts; /* Same thing, used by the generic IRQ code */ #define NR_IRQS_LEGACY NUM_ISA_INTERRUPTS -struct irq_data; -extern irq_hw_number_t irqd_to_hwirq(struct irq_data *d); extern irq_hw_number_t virq_to_hw(unsigned int virq); /** diff --git a/arch/powerpc/include/asm/kvm_book3s.h b/arch/powerpc/include/asm/kvm_book3s.h index aa795ccef294..fd07f43d6622 100644 --- a/arch/powerpc/include/asm/kvm_book3s.h +++ b/arch/powerpc/include/asm/kvm_book3s.h @@ -81,12 +81,13 @@ struct kvmppc_vcpu_book3s { u64 sdr1; u64 hior; u64 msr_mask; - u64 vsid_next; #ifdef CONFIG_PPC_BOOK3S_32 u32 vsid_pool[VSID_POOL_SIZE]; + u32 vsid_next; #else - u64 vsid_first; - u64 vsid_max; + u64 proto_vsid_first; + u64 proto_vsid_max; + u64 proto_vsid_next; #endif int context_id[SID_CONTEXTS]; diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h index c65b9294376e..c9f698a994be 100644 --- a/arch/powerpc/include/asm/mpic.h +++ b/arch/powerpc/include/asm/mpic.h @@ -275,9 +275,6 @@ struct mpic unsigned int isu_mask; /* Number of sources */ unsigned int num_sources; - /* default senses array */ - unsigned char *senses; - unsigned int senses_count; /* vector numbers used for internal sources (ipi/timers) */ unsigned int ipi_vecs[4]; @@ -415,21 +412,6 @@ extern struct mpic *mpic_alloc(struct device_node *node, extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num, phys_addr_t phys_addr); -/* Set default sense codes - * - * @mpic: controller - * @senses: array of sense codes - * @count: size of above array - * - * Optionally provide an array (indexed on hardware interrupt numbers - * for this MPIC) of default sense codes for the chip. Those are linux - * sense codes IRQ_TYPE_* - * - * The driver gets ownership of the pointer, don't dispose of it or - * anything like that. __init only. - */ -extern void mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count); - /* Initialize the controller. After this has been called, none of the above * should be called again for this mpic diff --git a/arch/powerpc/include/asm/mpic_msgr.h b/arch/powerpc/include/asm/mpic_msgr.h index 3ec37dc9003e..326d33ca55cd 100644 --- a/arch/powerpc/include/asm/mpic_msgr.h +++ b/arch/powerpc/include/asm/mpic_msgr.h @@ -13,6 +13,7 @@ #include <linux/types.h> #include <linux/spinlock.h> +#include <asm/smp.h> struct mpic_msgr { u32 __iomem *base; diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h index b86faa9107da..8a97aa7289d3 100644 --- a/arch/powerpc/include/asm/reg_booke.h +++ b/arch/powerpc/include/asm/reg_booke.h @@ -15,11 +15,6 @@ #ifndef __ASM_POWERPC_REG_BOOKE_H__ #define __ASM_POWERPC_REG_BOOKE_H__ -#ifdef CONFIG_BOOKE_WDT -extern u32 booke_wdt_enabled; -extern u32 booke_wdt_period; -#endif /* CONFIG_BOOKE_WDT */ - /* Machine State Register (MSR) Fields */ #define MSR_GS (1<<28) /* Guest state */ #define MSR_UCLE (1<<26) /* User-mode cache lock enable */ diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S index 3e57a00b8cba..ba3aeb4bc06a 100644 --- a/arch/powerpc/kernel/entry_32.S +++ b/arch/powerpc/kernel/entry_32.S @@ -206,40 +206,43 @@ reenable_mmu: /* re-enable mmu so we can */ andi. r10,r10,MSR_EE /* Did EE change? */ beq 1f - /* Save handler and return address into the 2 unused words - * of the STACK_FRAME_OVERHEAD (sneak sneak sneak). Everything - * else can be recovered from the pt_regs except r3 which for - * normal interrupts has been set to pt_regs and for syscalls - * is an argument, so we temporarily use ORIG_GPR3 to save it - */ - stw r9,8(r1) - stw r11,12(r1) - stw r3,ORIG_GPR3(r1) /* * The trace_hardirqs_off will use CALLER_ADDR0 and CALLER_ADDR1. * If from user mode there is only one stack frame on the stack, and * accessing CALLER_ADDR1 will cause oops. So we need create a dummy * stack frame to make trace_hardirqs_off happy. + * + * This is handy because we also need to save a bunch of GPRs, + * r3 can be different from GPR3(r1) at this point, r9 and r11 + * contains the old MSR and handler address respectively, + * r4 & r5 can contain page fault arguments that need to be passed + * along as well. r12, CCR, CTR, XER etc... are left clobbered as + * they aren't useful past this point (aren't syscall arguments), + * the rest is restored from the exception frame. */ + stwu r1,-32(r1) + stw r9,8(r1) + stw r11,12(r1) + stw r3,16(r1) + stw r4,20(r1) + stw r5,24(r1) andi. r12,r12,MSR_PR - beq 11f - stwu r1,-16(r1) + b 11f bl trace_hardirqs_off - addi r1,r1,16 b 12f - 11: bl trace_hardirqs_off 12: + lwz r5,24(r1) + lwz r4,20(r1) + lwz r3,16(r1) + lwz r11,12(r1) + lwz r9,8(r1) + addi r1,r1,32 lwz r0,GPR0(r1) - lwz r3,ORIG_GPR3(r1) - lwz r4,GPR4(r1) - lwz r5,GPR5(r1) lwz r6,GPR6(r1) lwz r7,GPR7(r1) lwz r8,GPR8(r1) - lwz r9,8(r1) - lwz r11,12(r1) 1: mtctr r11 mtlr r9 bctr /* jump to handler */ diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S index f8a7a1a1a9f4..ef2074c3e906 100644 --- a/arch/powerpc/kernel/entry_64.S +++ b/arch/powerpc/kernel/entry_64.S @@ -588,23 +588,19 @@ _GLOBAL(ret_from_except_lite) fast_exc_return_irq: restore: /* - * This is the main kernel exit path, we first check if we - * have to change our interrupt state. + * This is the main kernel exit path. First we check if we + * are about to re-enable interrupts */ ld r5,SOFTE(r1) lbz r6,PACASOFTIRQEN(r13) - cmpwi cr1,r5,0 - cmpw cr0,r5,r6 - beq cr0,4f + cmpwi cr0,r5,0 + beq restore_irq_off - /* We do, handle disable first, which is easy */ - bne cr1,3f; - li r0,0 - stb r0,PACASOFTIRQEN(r13); - TRACE_DISABLE_INTS - b 4f + /* We are enabling, were we already enabled ? Yes, just return */ + cmpwi cr0,r6,1 + beq cr0,do_restore -3: /* + /* * We are about to soft-enable interrupts (we are hard disabled * at this point). We check if there's anything that needs to * be replayed first. @@ -626,7 +622,7 @@ restore_no_replay: /* * Final return path. BookE is handled in a different file */ -4: +do_restore: #ifdef CONFIG_PPC_BOOK3E b .exception_return_book3e #else @@ -700,6 +696,25 @@ fast_exception_return: #endif /* CONFIG_PPC_BOOK3E */ /* + * We are returning to a context with interrupts soft disabled. + * + * However, we may also about to hard enable, so we need to + * make sure that in this case, we also clear PACA_IRQ_HARD_DIS + * or that bit can get out of sync and bad things will happen + */ +restore_irq_off: + ld r3,_MSR(r1) + lbz r7,PACAIRQHAPPENED(r13) + andi. r0,r3,MSR_EE + beq 1f + rlwinm r7,r7,0,~PACA_IRQ_HARD_DIS + stb r7,PACAIRQHAPPENED(r13) +1: li r0,0 + stb r0,PACASOFTIRQEN(r13); + TRACE_DISABLE_INTS + b do_restore + + /* * Something did happen, check if a re-emit is needed * (this also clears paca->irq_happened) */ @@ -748,6 +763,9 @@ restore_check_irq_replay: #endif /* CONFIG_PPC_BOOK3E */ 1: b .ret_from_except /* What else to do here ? */ + + +3: do_work: #ifdef CONFIG_PREEMPT andi. r0,r3,MSR_PR /* Returning to user mode? */ @@ -767,16 +785,6 @@ do_work: SOFT_DISABLE_INTS(r3,r4) 1: bl .preempt_schedule_irq - /* Hard-disable interrupts again (and update PACA) */ -#ifdef CONFIG_PPC_BOOK3E - wrteei 0 -#else - ld r10,PACAKMSR(r13) /* Get kernel MSR without EE */ - mtmsrd r10,1 -#endif /* CONFIG_PPC_BOOK3E */ - li r0,PACA_IRQ_HARD_DIS - stb r0,PACAIRQHAPPENED(r13) - /* Re-test flags and eventually loop */ clrrdi r9,r1,THREAD_SHIFT ld r4,TI_FLAGS(r9) @@ -787,14 +795,6 @@ do_work: user_work: #endif /* CONFIG_PREEMPT */ - /* Enable interrupts */ -#ifdef CONFIG_PPC_BOOK3E - wrteei 1 -#else - ori r10,r10,MSR_EE - mtmsrd r10,1 -#endif /* CONFIG_PPC_BOOK3E */ - andi. r0,r4,_TIF_NEED_RESCHED beq 1f bl .restore_interrupts diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S index cb705fdbb458..8f880bc77c56 100644 --- a/arch/powerpc/kernel/exceptions-64s.S +++ b/arch/powerpc/kernel/exceptions-64s.S @@ -768,8 +768,8 @@ alignment_common: std r3,_DAR(r1) std r4,_DSISR(r1) bl .save_nvgprs + DISABLE_INTS addi r3,r1,STACK_FRAME_OVERHEAD - ENABLE_INTS bl .alignment_exception b .ret_from_except diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c index 243dbabfe74d..641da9e868ce 100644 --- a/arch/powerpc/kernel/irq.c +++ b/arch/powerpc/kernel/irq.c @@ -229,6 +229,19 @@ notrace void arch_local_irq_restore(unsigned long en) */ if (unlikely(irq_happened != PACA_IRQ_HARD_DIS)) __hard_irq_disable(); +#ifdef CONFIG_TRACE_IRQFLAG + else { + /* + * We should already be hard disabled here. We had bugs + * where that wasn't the case so let's dbl check it and + * warn if we are wrong. Only do that when IRQ tracing + * is enabled as mfmsr() can be costly. + */ + if (WARN_ON(mfmsr() & MSR_EE)) + __hard_irq_disable(); + } +#endif /* CONFIG_TRACE_IRQFLAG */ + set_soft_enabled(0); /* @@ -260,11 +273,17 @@ EXPORT_SYMBOL(arch_local_irq_restore); * if they are currently disabled. This is typically called before * schedule() or do_signal() when returning to userspace. We do it * in C to avoid the burden of dealing with lockdep etc... + * + * NOTE: This is called with interrupts hard disabled but not marked + * as such in paca->irq_happened, so we need to resync this. */ void restore_interrupts(void) { - if (irqs_disabled()) + if (irqs_disabled()) { + local_paca->irq_happened |= PACA_IRQ_HARD_DIS; local_irq_enable(); + } else + __hard_irq_enable(); } #endif /* CONFIG_PPC64 */ @@ -330,14 +349,10 @@ void migrate_irqs(void) alloc_cpumask_var(&mask, GFP_KERNEL); - for_each_irq(irq) { + for_each_irq_desc(irq, desc) { struct irq_data *data; struct irq_chip *chip; - desc = irq_to_desc(irq); - if (!desc) - continue; - data = irq_desc_get_irq_data(desc); if (irqd_is_per_cpu(data)) continue; @@ -560,12 +575,6 @@ void do_softirq(void) local_irq_restore(flags); } -irq_hw_number_t irqd_to_hwirq(struct irq_data *d) -{ - return d->hwirq; -} -EXPORT_SYMBOL_GPL(irqd_to_hwirq); - irq_hw_number_t virq_to_hw(unsigned int virq) { struct irq_data *irq_data = irq_get_irq_data(virq); diff --git a/arch/powerpc/kernel/machine_kexec.c b/arch/powerpc/kernel/machine_kexec.c index c957b1202bdc..5df777794403 100644 --- a/arch/powerpc/kernel/machine_kexec.c +++ b/arch/powerpc/kernel/machine_kexec.c @@ -23,14 +23,11 @@ void machine_kexec_mask_interrupts(void) { unsigned int i; + struct irq_desc *desc; - for_each_irq(i) { - struct irq_desc *desc = irq_to_desc(i); + for_each_irq_desc(i, desc) { struct irq_chip *chip; - if (!desc) - continue; - chip = irq_desc_get_chip(desc); if (!chip) continue; diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c index f88698c0f332..4937c9690090 100644 --- a/arch/powerpc/kernel/process.c +++ b/arch/powerpc/kernel/process.c @@ -1235,7 +1235,7 @@ void __ppc64_runlatch_on(void) ctrl |= CTRL_RUNLATCH; mtspr(SPRN_CTRLT, ctrl); - ti->local_flags |= TLF_RUNLATCH; + ti->local_flags |= _TLF_RUNLATCH; } /* Called with hard IRQs off */ @@ -1244,7 +1244,7 @@ void __ppc64_runlatch_off(void) struct thread_info *ti = current_thread_info(); unsigned long ctrl; - ti->local_flags &= ~TLF_RUNLATCH; + ti->local_flags &= ~_TLF_RUNLATCH; ctrl = mfspr(SPRN_CTRLF); ctrl &= ~CTRL_RUNLATCH; diff --git a/arch/powerpc/kernel/setup_32.c b/arch/powerpc/kernel/setup_32.c index 9825f29d1faf..ec8a53fa9e8f 100644 --- a/arch/powerpc/kernel/setup_32.c +++ b/arch/powerpc/kernel/setup_32.c @@ -150,6 +150,9 @@ notrace void __init machine_init(u64 dt_ptr) } #ifdef CONFIG_BOOKE_WDT +extern u32 booke_wdt_enabled; +extern u32 booke_wdt_period; + /* Checks wdt=x and wdt_period=xx command-line option */ notrace int __init early_parse_wdt(char *p) { diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c index 6aa0c663e247..158972341a2d 100644 --- a/arch/powerpc/kernel/traps.c +++ b/arch/powerpc/kernel/traps.c @@ -248,7 +248,7 @@ void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr) addr, regs->nip, regs->link, code); } - if (!arch_irq_disabled_regs(regs)) + if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs)) local_irq_enable(); memset(&info, 0, sizeof(info)); @@ -1019,7 +1019,9 @@ void __kprobes program_check_exception(struct pt_regs *regs) return; } - local_irq_enable(); + /* We restore the interrupt state now */ + if (!arch_irq_disabled_regs(regs)) + local_irq_enable(); #ifdef CONFIG_MATH_EMULATION /* (reason & REASON_ILLEGAL) would be the obvious thing here, @@ -1069,6 +1071,10 @@ void alignment_exception(struct pt_regs *regs) { int sig, code, fixed = 0; + /* We restore the interrupt state now */ + if (!arch_irq_disabled_regs(regs)) + local_irq_enable(); + /* we don't implement logging of alignment exceptions */ if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS)) fixed = fix_alignment(regs); diff --git a/arch/powerpc/kvm/book3s_64_mmu_host.c b/arch/powerpc/kvm/book3s_64_mmu_host.c index 6f87f39a1ac2..10fc8ec9d2a8 100644 --- a/arch/powerpc/kvm/book3s_64_mmu_host.c +++ b/arch/powerpc/kvm/book3s_64_mmu_host.c @@ -194,14 +194,14 @@ static struct kvmppc_sid_map *create_sid_map(struct kvm_vcpu *vcpu, u64 gvsid) backwards_map = !backwards_map; /* Uh-oh ... out of mappings. Let's flush! */ - if (vcpu_book3s->vsid_next == vcpu_book3s->vsid_max) { - vcpu_book3s->vsid_next = vcpu_book3s->vsid_first; + if (vcpu_book3s->proto_vsid_next == vcpu_book3s->proto_vsid_max) { + vcpu_book3s->proto_vsid_next = vcpu_book3s->proto_vsid_first; memset(vcpu_book3s->sid_map, 0, sizeof(struct kvmppc_sid_map) * SID_MAP_NUM); kvmppc_mmu_pte_flush(vcpu, 0, 0); kvmppc_mmu_flush_segments(vcpu); } - map->host_vsid = vcpu_book3s->vsid_next++; + map->host_vsid = vsid_scramble(vcpu_book3s->proto_vsid_next++, 256M); map->guest_vsid = gvsid; map->valid = true; @@ -319,9 +319,10 @@ int kvmppc_mmu_init(struct kvm_vcpu *vcpu) return -1; vcpu3s->context_id[0] = err; - vcpu3s->vsid_max = ((vcpu3s->context_id[0] + 1) << USER_ESID_BITS) - 1; - vcpu3s->vsid_first = vcpu3s->context_id[0] << USER_ESID_BITS; - vcpu3s->vsid_next = vcpu3s->vsid_first; + vcpu3s->proto_vsid_max = ((vcpu3s->context_id[0] + 1) + << USER_ESID_BITS) - 1; + vcpu3s->proto_vsid_first = vcpu3s->context_id[0] << USER_ESID_BITS; + vcpu3s->proto_vsid_next = vcpu3s->proto_vsid_first; kvmppc_mmu_hpte_init(vcpu); diff --git a/arch/powerpc/kvm/book3s_64_mmu_hv.c b/arch/powerpc/kvm/book3s_64_mmu_hv.c index ddc485a529f2..c3beaeef3f60 100644 --- a/arch/powerpc/kvm/book3s_64_mmu_hv.c +++ b/arch/powerpc/kvm/book3s_64_mmu_hv.c @@ -258,6 +258,8 @@ static long kvmppc_get_guest_page(struct kvm *kvm, unsigned long gfn, !(memslot->userspace_addr & (s - 1))) { start &= ~(s - 1); pgsize = s; + get_page(hpage); + put_page(page); page = hpage; } } @@ -281,11 +283,8 @@ static long kvmppc_get_guest_page(struct kvm *kvm, unsigned long gfn, err = 0; out: - if (got) { - if (PageHuge(page)) - page = compound_head(page); + if (got) put_page(page); - } return err; up_err: @@ -678,8 +677,15 @@ int kvmppc_book3s_hv_page_fault(struct kvm_run *run, struct kvm_vcpu *vcpu, SetPageDirty(page); out_put: - if (page) - put_page(page); + if (page) { + /* + * We drop pages[0] here, not page because page might + * have been set to the head page of a compound, but + * we have to drop the reference on the correct tail + * page to match the get inside gup() + */ + put_page(pages[0]); + } return ret; out_unlock: @@ -979,6 +985,7 @@ void *kvmppc_pin_guest_page(struct kvm *kvm, unsigned long gpa, pa = *physp; } page = pfn_to_page(pa >> PAGE_SHIFT); + get_page(page); } else { hva = gfn_to_hva_memslot(memslot, gfn); npages = get_user_pages_fast(hva, 1, 1, pages); @@ -991,8 +998,6 @@ void *kvmppc_pin_guest_page(struct kvm *kvm, unsigned long gpa, page = compound_head(page); psize <<= compound_order(page); } - if (!kvm->arch.using_mmu_notifiers) - get_page(page); offset = gpa & (psize - 1); if (nb_ret) *nb_ret = psize - offset; @@ -1003,7 +1008,6 @@ void kvmppc_unpin_guest_page(struct kvm *kvm, void *va) { struct page *page = virt_to_page(va); - page = compound_head(page); put_page(page); } diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c index 01294a5099dd..108d1f580177 100644 --- a/arch/powerpc/kvm/book3s_hv.c +++ b/arch/powerpc/kvm/book3s_hv.c @@ -1192,8 +1192,6 @@ static void unpin_slot(struct kvm *kvm, int slot_id) continue; pfn = physp[j] >> PAGE_SHIFT; page = pfn_to_page(pfn); - if (PageHuge(page)) - page = compound_head(page); SetPageDirty(page); put_page(page); } diff --git a/arch/powerpc/kvm/book3s_hv_rm_mmu.c b/arch/powerpc/kvm/book3s_hv_rm_mmu.c index def880aea63a..cec4daddbf31 100644 --- a/arch/powerpc/kvm/book3s_hv_rm_mmu.c +++ b/arch/powerpc/kvm/book3s_hv_rm_mmu.c @@ -463,6 +463,7 @@ long kvmppc_h_bulk_remove(struct kvm_vcpu *vcpu) /* insert R and C bits from PTE */ rcbits = rev->guest_rpte & (HPTE_R_R|HPTE_R_C); args[j] |= rcbits << (56 - 5); + hp[0] = 0; continue; } diff --git a/arch/powerpc/kvm/book3s_segment.S b/arch/powerpc/kvm/book3s_segment.S index 0676ae249b9f..6e6e9cef34a8 100644 --- a/arch/powerpc/kvm/book3s_segment.S +++ b/arch/powerpc/kvm/book3s_segment.S @@ -197,7 +197,8 @@ kvmppc_interrupt: /* Save guest PC and MSR */ #ifdef CONFIG_PPC64 BEGIN_FTR_SECTION - andi. r0,r12,0x2 + andi. r0, r12, 0x2 + cmpwi cr1, r0, 0 beq 1f mfspr r3,SPRN_HSRR0 mfspr r4,SPRN_HSRR1 @@ -250,6 +251,12 @@ END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) beq ld_last_prev_inst cmpwi r12, BOOK3S_INTERRUPT_ALIGNMENT beq- ld_last_inst +#ifdef CONFIG_PPC64 +BEGIN_FTR_SECTION + cmpwi r12, BOOK3S_INTERRUPT_H_EMUL_ASSIST + beq- ld_last_inst +END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) +#endif b no_ld_last_inst @@ -316,23 +323,17 @@ no_dcbz32_off: * Having set up SRR0/1 with the address where we want * to continue with relocation on (potentially in module * space), we either just go straight there with rfi[d], - * or we jump to an interrupt handler with bctr if there - * is an interrupt to be handled first. In the latter - * case, the rfi[d] at the end of the interrupt handler - * will get us back to where we want to continue. + * or we jump to an interrupt handler if there is an + * interrupt to be handled first. In the latter case, + * the rfi[d] at the end of the interrupt handler will + * get us back to where we want to continue. */ - cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL - beq 1f - cmpwi r12, BOOK3S_INTERRUPT_DECREMENTER - beq 1f - cmpwi r12, BOOK3S_INTERRUPT_PERFMON -1: mtctr r12 - /* Register usage at this point: * * R1 = host R1 * R2 = host R2 + * R10 = raw exit handler id * R12 = exit handler id * R13 = shadow vcpu (32-bit) or PACA (64-bit) * SVCPU.* = guest * @@ -342,12 +343,25 @@ no_dcbz32_off: PPC_LL r6, HSTATE_HOST_MSR(r13) PPC_LL r8, HSTATE_VMHANDLER(r13) - /* Restore host msr -> SRR1 */ +#ifdef CONFIG_PPC64 +BEGIN_FTR_SECTION + beq cr1, 1f + mtspr SPRN_HSRR1, r6 + mtspr SPRN_HSRR0, r8 +END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) +#endif +1: /* Restore host msr -> SRR1 */ mtsrr1 r6 /* Load highmem handler address */ mtsrr0 r8 /* RFI into the highmem handler, or jump to interrupt handler */ - beqctr + cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL + beqa BOOK3S_INTERRUPT_EXTERNAL + cmpwi r12, BOOK3S_INTERRUPT_DECREMENTER + beqa BOOK3S_INTERRUPT_DECREMENTER + cmpwi r12, BOOK3S_INTERRUPT_PERFMON + beqa BOOK3S_INTERRUPT_PERFMON + RFI kvmppc_handler_trampoline_exit_end: diff --git a/arch/powerpc/net/bpf_jit.h b/arch/powerpc/net/bpf_jit.h index af1ab5e9a691..5c3cf2d04e41 100644 --- a/arch/powerpc/net/bpf_jit.h +++ b/arch/powerpc/net/bpf_jit.h @@ -48,7 +48,13 @@ /* * Assembly helpers from arch/powerpc/net/bpf_jit.S: */ -extern u8 sk_load_word[], sk_load_half[], sk_load_byte[], sk_load_byte_msh[]; +#define DECLARE_LOAD_FUNC(func) \ + extern u8 func[], func##_negative_offset[], func##_positive_offset[] + +DECLARE_LOAD_FUNC(sk_load_word); +DECLARE_LOAD_FUNC(sk_load_half); +DECLARE_LOAD_FUNC(sk_load_byte); +DECLARE_LOAD_FUNC(sk_load_byte_msh); #define FUNCTION_DESCR_SIZE 24 diff --git a/arch/powerpc/net/bpf_jit_64.S b/arch/powerpc/net/bpf_jit_64.S index ff4506e85cce..55ba3855a97f 100644 --- a/arch/powerpc/net/bpf_jit_64.S +++ b/arch/powerpc/net/bpf_jit_64.S @@ -31,14 +31,13 @@ * then branch directly to slow_path_XXX if required. (In fact, could * load a spare GPR with the address of slow_path_generic and pass size * as an argument, making the call site a mtlr, li and bllr.) - * - * Technically, the "is addr < 0" check is unnecessary & slowing down - * the ABS path, as it's statically checked on generation. */ .globl sk_load_word sk_load_word: cmpdi r_addr, 0 - blt bpf_error + blt bpf_slow_path_word_neg + .globl sk_load_word_positive_offset +sk_load_word_positive_offset: /* Are we accessing past headlen? */ subi r_scratch1, r_HL, 4 cmpd r_scratch1, r_addr @@ -51,7 +50,9 @@ sk_load_word: .globl sk_load_half sk_load_half: cmpdi r_addr, 0 - blt bpf_error + blt bpf_slow_path_half_neg + .globl sk_load_half_positive_offset +sk_load_half_positive_offset: subi r_scratch1, r_HL, 2 cmpd r_scratch1, r_addr blt bpf_slow_path_half @@ -61,7 +62,9 @@ sk_load_half: .globl sk_load_byte sk_load_byte: cmpdi r_addr, 0 - blt bpf_error + blt bpf_slow_path_byte_neg + .globl sk_load_byte_positive_offset +sk_load_byte_positive_offset: cmpd r_HL, r_addr ble bpf_slow_path_byte lbzx r_A, r_D, r_addr @@ -69,22 +72,20 @@ sk_load_byte: /* * BPF_S_LDX_B_MSH: ldxb 4*([offset]&0xf) - * r_addr is the offset value, already known positive + * r_addr is the offset value */ .globl sk_load_byte_msh sk_load_byte_msh: + cmpdi r_addr, 0 + blt bpf_slow_path_byte_msh_neg + .globl sk_load_byte_msh_positive_offset +sk_load_byte_msh_positive_offset: cmpd r_HL, r_addr ble bpf_slow_path_byte_msh lbzx r_X, r_D, r_addr rlwinm r_X, r_X, 2, 32-4-2, 31-2 blr -bpf_error: - /* Entered with cr0 = lt */ - li r3, 0 - /* Generated code will 'blt epilogue', returning 0. */ - blr - /* Call out to skb_copy_bits: * We'll need to back up our volatile regs first; we have * local variable space at r1+(BPF_PPC_STACK_BASIC). @@ -136,3 +137,84 @@ bpf_slow_path_byte_msh: lbz r_X, BPF_PPC_STACK_BASIC+(2*8)(r1) rlwinm r_X, r_X, 2, 32-4-2, 31-2 blr + +/* Call out to bpf_internal_load_pointer_neg_helper: + * We'll need to back up our volatile regs first; we have + * local variable space at r1+(BPF_PPC_STACK_BASIC). + * Allocate a new stack frame here to remain ABI-compliant in + * stashing LR. + */ +#define sk_negative_common(SIZE) \ + mflr r0; \ + std r0, 16(r1); \ + /* R3 goes in parameter space of caller's frame */ \ + std r_skb, (BPF_PPC_STACKFRAME+48)(r1); \ + std r_A, (BPF_PPC_STACK_BASIC+(0*8))(r1); \ + std r_X, (BPF_PPC_STACK_BASIC+(1*8))(r1); \ + stdu r1, -BPF_PPC_SLOWPATH_FRAME(r1); \ + /* R3 = r_skb, as passed */ \ + mr r4, r_addr; \ + li r5, SIZE; \ + bl bpf_internal_load_pointer_neg_helper; \ + /* R3 != 0 on success */ \ + addi r1, r1, BPF_PPC_SLOWPATH_FRAME; \ + ld r0, 16(r1); \ + ld r_A, (BPF_PPC_STACK_BASIC+(0*8))(r1); \ + ld r_X, (BPF_PPC_STACK_BASIC+(1*8))(r1); \ + mtlr r0; \ + cmpldi r3, 0; \ + beq bpf_error_slow; /* cr0 = EQ */ \ + mr r_addr, r3; \ + ld r_skb, (BPF_PPC_STACKFRAME+48)(r1); \ + /* Great success! */ + +bpf_slow_path_word_neg: + lis r_scratch1,-32 /* SKF_LL_OFF */ + cmpd r_addr, r_scratch1 /* addr < SKF_* */ + blt bpf_error /* cr0 = LT */ + .globl sk_load_word_negative_offset +sk_load_word_negative_offset: + sk_negative_common(4) + lwz r_A, 0(r_addr) + blr + +bpf_slow_path_half_neg: + lis r_scratch1,-32 /* SKF_LL_OFF */ + cmpd r_addr, r_scratch1 /* addr < SKF_* */ + blt bpf_error /* cr0 = LT */ + .globl sk_load_half_negative_offset +sk_load_half_negative_offset: + sk_negative_common(2) + lhz r_A, 0(r_addr) + blr + +bpf_slow_path_byte_neg: + lis r_scratch1,-32 /* SKF_LL_OFF */ + cmpd r_addr, r_scratch1 /* addr < SKF_* */ + blt bpf_error /* cr0 = LT */ + .globl sk_load_byte_negative_offset +sk_load_byte_negative_offset: + sk_negative_common(1) + lbz r_A, 0(r_addr) + blr + +bpf_slow_path_byte_msh_neg: + lis r_scratch1,-32 /* SKF_LL_OFF */ + cmpd r_addr, r_scratch1 /* addr < SKF_* */ + blt bpf_error /* cr0 = LT */ + .globl sk_load_byte_msh_negative_offset +sk_load_byte_msh_negative_offset: + sk_negative_common(1) + lbz r_X, 0(r_addr) + rlwinm r_X, r_X, 2, 32-4-2, 31-2 + blr + +bpf_error_slow: + /* fabricate a cr0 = lt */ + li r_scratch1, -1 + cmpdi r_scratch1, 0 +bpf_error: + /* Entered with cr0 = lt */ + li r3, 0 + /* Generated code will 'blt epilogue', returning 0. */ + blr diff --git a/arch/powerpc/net/bpf_jit_comp.c b/arch/powerpc/net/bpf_jit_comp.c index 73619d3aeb6c..2dc8b1484845 100644 --- a/arch/powerpc/net/bpf_jit_comp.c +++ b/arch/powerpc/net/bpf_jit_comp.c @@ -127,6 +127,9 @@ static void bpf_jit_build_epilogue(u32 *image, struct codegen_context *ctx) PPC_BLR(); } +#define CHOOSE_LOAD_FUNC(K, func) \ + ((int)K < 0 ? ((int)K >= SKF_LL_OFF ? func##_negative_offset : func) : func##_positive_offset) + /* Assemble the body code between the prologue & epilogue. */ static int bpf_jit_build_body(struct sk_filter *fp, u32 *image, struct codegen_context *ctx, @@ -391,21 +394,16 @@ static int bpf_jit_build_body(struct sk_filter *fp, u32 *image, /*** Absolute loads from packet header/data ***/ case BPF_S_LD_W_ABS: - func = sk_load_word; + func = CHOOSE_LOAD_FUNC(K, sk_load_word); goto common_load; case BPF_S_LD_H_ABS: - func = sk_load_half; + func = CHOOSE_LOAD_FUNC(K, sk_load_half); goto common_load; case BPF_S_LD_B_ABS: - func = sk_load_byte; + func = CHOOSE_LOAD_FUNC(K, sk_load_byte); common_load: - /* - * Load from [K]. Reference with the (negative) - * SKF_NET_OFF/SKF_LL_OFF offsets is unsupported. - */ + /* Load from [K]. */ ctx->seen |= SEEN_DATAREF; - if ((int)K < 0) - return -ENOTSUPP; PPC_LI64(r_scratch1, func); PPC_MTLR(r_scratch1); PPC_LI32(r_addr, K); @@ -429,7 +427,7 @@ static int bpf_jit_build_body(struct sk_filter *fp, u32 *image, common_load_ind: /* * Load from [X + K]. Negative offsets are tested for - * in the helper functions, and result in a 'ret 0'. + * in the helper functions. */ ctx->seen |= SEEN_DATAREF | SEEN_XREG; PPC_LI64(r_scratch1, func); @@ -443,13 +441,7 @@ static int bpf_jit_build_body(struct sk_filter *fp, u32 *image, break; case BPF_S_LDX_B_MSH: - /* - * x86 version drops packet (RET 0) when K<0, whereas - * interpreter does allow K<0 (__load_pointer, special - * ancillary data). common_load returns ENOTSUPP if K<0, - * so we fall back to interpreter & filter works. - */ - func = sk_load_byte_msh; + func = CHOOSE_LOAD_FUNC(K, sk_load_byte_msh); goto common_load; break; diff --git a/arch/powerpc/platforms/85xx/common.c b/arch/powerpc/platforms/85xx/common.c index 9fef5302adc1..67dac22b4363 100644 --- a/arch/powerpc/platforms/85xx/common.c +++ b/arch/powerpc/platforms/85xx/common.c @@ -21,6 +21,12 @@ static struct of_device_id __initdata mpc85xx_common_ids[] = { { .compatible = "fsl,qe", }, { .compatible = "fsl,cpm2", }, { .compatible = "fsl,srio", }, + /* So that the DMA channel nodes can be probed individually: */ + { .compatible = "fsl,eloplus-dma", }, + /* For the PMC driver */ + { .compatible = "fsl,mpc8548-guts", }, + /* Probably unnecessary? */ + { .compatible = "gpio-leds", }, {}, }; diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c index 9a6f04406e0d..d208ebccb91c 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c @@ -399,12 +399,6 @@ static int __init board_fixups(void) machine_arch_initcall(mpc8568_mds, board_fixups); machine_arch_initcall(mpc8569_mds, board_fixups); -static struct of_device_id mpc85xx_ids[] = { - { .compatible = "fsl,mpc8548-guts", }, - { .compatible = "gpio-leds", }, - {}, -}; - static int __init mpc85xx_publish_devices(void) { if (machine_is(mpc8568_mds)) @@ -412,10 +406,7 @@ static int __init mpc85xx_publish_devices(void) if (machine_is(mpc8569_mds)) simple_gpiochip_init("fsl,mpc8569mds-bcsr-gpio"); - mpc85xx_common_publish_devices(); - of_platform_bus_probe(NULL, mpc85xx_ids, NULL); - - return 0; + return mpc85xx_common_publish_devices(); } machine_device_initcall(mpc8568_mds, mpc85xx_publish_devices); diff --git a/arch/powerpc/platforms/85xx/p1022_ds.c b/arch/powerpc/platforms/85xx/p1022_ds.c index e74b7cde9aee..f700c81a1321 100644 --- a/arch/powerpc/platforms/85xx/p1022_ds.c +++ b/arch/powerpc/platforms/85xx/p1022_ds.c @@ -460,18 +460,7 @@ static void __init p1022_ds_setup_arch(void) pr_info("Freescale P1022 DS reference board\n"); } -static struct of_device_id __initdata p1022_ds_ids[] = { - /* So that the DMA channel nodes can be probed individually: */ - { .compatible = "fsl,eloplus-dma", }, - {}, -}; - -static int __init p1022_ds_publish_devices(void) -{ - mpc85xx_common_publish_devices(); - return of_platform_bus_probe(NULL, p1022_ds_ids, NULL); -} -machine_device_initcall(p1022_ds, p1022_ds_publish_devices); +machine_device_initcall(p1022_ds, mpc85xx_common_publish_devices); machine_arch_initcall(p1022_ds, swiotlb_setup_bus_notifier); diff --git a/arch/powerpc/platforms/cell/axon_msi.c b/arch/powerpc/platforms/cell/axon_msi.c index db360fc4cf0e..85825b5401e5 100644 --- a/arch/powerpc/platforms/cell/axon_msi.c +++ b/arch/powerpc/platforms/cell/axon_msi.c @@ -114,7 +114,7 @@ static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc) pr_devel("axon_msi: woff %x roff %x msi %x\n", write_offset, msic->read_offset, msi); - if (msi < NR_IRQS && irq_get_chip_data(msi) == msic) { + if (msi < nr_irqs && irq_get_chip_data(msi) == msic) { generic_handle_irq(msi); msic->fifo_virt[idx] = cpu_to_le32(0xffffffff); } else { @@ -276,9 +276,6 @@ static int axon_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) if (rc) return rc; - /* We rely on being able to stash a virq in a u16 */ - BUILD_BUG_ON(NR_IRQS > 65536); - list_for_each_entry(entry, &dev->msi_list, list) { virq = irq_create_direct_mapping(msic->irq_domain); if (virq == NO_IRQ) { @@ -392,7 +389,8 @@ static int axon_msi_probe(struct platform_device *device) } memset(msic->fifo_virt, 0xff, MSIC_FIFO_SIZE_BYTES); - msic->irq_domain = irq_domain_add_nomap(dn, &msic_host_ops, msic); + /* We rely on being able to stash a virq in a u16, so limit irqs to < 65536 */ + msic->irq_domain = irq_domain_add_nomap(dn, 65536, &msic_host_ops, msic); if (!msic->irq_domain) { printk(KERN_ERR "axon_msi: couldn't allocate irq_domain for %s\n", dn->full_name); diff --git a/arch/powerpc/platforms/cell/beat_interrupt.c b/arch/powerpc/platforms/cell/beat_interrupt.c index e5c3a2c6090d..8c6dc42ecf65 100644 --- a/arch/powerpc/platforms/cell/beat_interrupt.c +++ b/arch/powerpc/platforms/cell/beat_interrupt.c @@ -239,7 +239,7 @@ void __init beatic_init_IRQ(void) ppc_md.get_irq = beatic_get_irq; /* Allocate an irq host */ - beatic_host = irq_domain_add_nomap(NULL, &beatic_pic_host_ops, NULL); + beatic_host = irq_domain_add_nomap(NULL, 0, &beatic_pic_host_ops, NULL); BUG_ON(beatic_host == NULL); irq_set_default_host(beatic_host); } @@ -248,6 +248,6 @@ void beatic_deinit_IRQ(void) { int i; - for (i = 1; i < NR_IRQS; i++) + for (i = 1; i < nr_irqs; i++) beat_destruct_irq_plug(i); } diff --git a/arch/powerpc/platforms/powermac/low_i2c.c b/arch/powerpc/platforms/powermac/low_i2c.c index 996c5ff7824b..03685a329d7d 100644 --- a/arch/powerpc/platforms/powermac/low_i2c.c +++ b/arch/powerpc/platforms/powermac/low_i2c.c @@ -366,11 +366,20 @@ static void kw_i2c_timeout(unsigned long data) unsigned long flags; spin_lock_irqsave(&host->lock, flags); + + /* + * If the timer is pending, that means we raced with the + * irq, in which case we just return + */ + if (timer_pending(&host->timeout_timer)) + goto skip; + kw_i2c_handle_interrupt(host, kw_read_reg(reg_isr)); if (host->state != state_idle) { host->timeout_timer.expires = jiffies + KW_POLL_TIMEOUT; add_timer(&host->timeout_timer); } + skip: spin_unlock_irqrestore(&host->lock, flags); } diff --git a/arch/powerpc/platforms/powermac/pic.c b/arch/powerpc/platforms/powermac/pic.c index 66ad93de1d55..c4e630576ff2 100644 --- a/arch/powerpc/platforms/powermac/pic.c +++ b/arch/powerpc/platforms/powermac/pic.c @@ -57,9 +57,9 @@ static int max_real_irqs; static DEFINE_RAW_SPINLOCK(pmac_pic_lock); -#define NR_MASK_WORDS ((NR_IRQS + 31) / 32) -static unsigned long ppc_lost_interrupts[NR_MASK_WORDS]; -static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS]; +/* The max irq number this driver deals with is 128; see max_irqs */ +static DECLARE_BITMAP(ppc_lost_interrupts, 128); +static DECLARE_BITMAP(ppc_cached_irq_mask, 128); static int pmac_irq_cascade = -1; static struct irq_domain *pmac_pic_host; diff --git a/arch/powerpc/platforms/powermac/smp.c b/arch/powerpc/platforms/powermac/smp.c index a81e5a88fbdf..b4ddaa3fbb29 100644 --- a/arch/powerpc/platforms/powermac/smp.c +++ b/arch/powerpc/platforms/powermac/smp.c @@ -192,7 +192,7 @@ static int psurge_secondary_ipi_init(void) { int rc = -ENOMEM; - psurge_host = irq_domain_add_nomap(NULL, &psurge_host_ops, NULL); + psurge_host = irq_domain_add_nomap(NULL, 0, &psurge_host_ops, NULL); if (psurge_host) psurge_secondary_virq = irq_create_direct_mapping(psurge_host); diff --git a/arch/powerpc/platforms/ps3/interrupt.c b/arch/powerpc/platforms/ps3/interrupt.c index 2a4ff86cc21f..5f3b23220b8e 100644 --- a/arch/powerpc/platforms/ps3/interrupt.c +++ b/arch/powerpc/platforms/ps3/interrupt.c @@ -753,9 +753,8 @@ void __init ps3_init_IRQ(void) unsigned cpu; struct irq_domain *host; - host = irq_domain_add_nomap(NULL, &ps3_host_ops, NULL); + host = irq_domain_add_nomap(NULL, PS3_PLUG_MAX + 1, &ps3_host_ops, NULL); irq_set_default_host(host); - irq_set_virq_count(PS3_PLUG_MAX + 1); for_each_possible_cpu(cpu) { struct ps3_private *pd = &per_cpu(ps3_private, cpu); diff --git a/arch/powerpc/platforms/pseries/Kconfig b/arch/powerpc/platforms/pseries/Kconfig index aadbe4f6d537..178a5f300bc9 100644 --- a/arch/powerpc/platforms/pseries/Kconfig +++ b/arch/powerpc/platforms/pseries/Kconfig @@ -30,9 +30,9 @@ config PPC_SPLPAR two or more partitions. config EEH - bool "PCI Extended Error Handling (EEH)" if EXPERT + bool depends on PPC_PSERIES && PCI - default y if !EXPERT + default y config PSERIES_MSI bool diff --git a/arch/powerpc/platforms/pseries/eeh.c b/arch/powerpc/platforms/pseries/eeh.c index 309d38ef7322..a75e37dc41aa 100644 --- a/arch/powerpc/platforms/pseries/eeh.c +++ b/arch/powerpc/platforms/pseries/eeh.c @@ -1076,7 +1076,7 @@ static void eeh_add_device_late(struct pci_dev *dev) pr_debug("EEH: Adding device %s\n", pci_name(dev)); dn = pci_device_to_OF_node(dev); - edev = pci_dev_to_eeh_dev(dev); + edev = of_node_to_eeh_dev(dn); if (edev->pdev == dev) { pr_debug("EEH: Already referenced !\n"); return; diff --git a/arch/powerpc/sysdev/cpm2_pic.c b/arch/powerpc/sysdev/cpm2_pic.c index d3be961e2ae7..10386b676d87 100644 --- a/arch/powerpc/sysdev/cpm2_pic.c +++ b/arch/powerpc/sysdev/cpm2_pic.c @@ -51,8 +51,7 @@ static intctl_cpm2_t __iomem *cpm2_intctl; static struct irq_domain *cpm2_pic_host; -#define NR_MASK_WORDS ((NR_IRQS + 31) / 32) -static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS]; +static unsigned long ppc_cached_irq_mask[2]; /* 2 32-bit registers */ static const u_char irq_to_siureg[] = { 1, 1, 1, 1, 1, 1, 1, 1, diff --git a/arch/powerpc/sysdev/mpc8xx_pic.c b/arch/powerpc/sysdev/mpc8xx_pic.c index d5f5416be310..b724622c3a0b 100644 --- a/arch/powerpc/sysdev/mpc8xx_pic.c +++ b/arch/powerpc/sysdev/mpc8xx_pic.c @@ -18,69 +18,45 @@ extern int cpm_get_irq(struct pt_regs *regs); static struct irq_domain *mpc8xx_pic_host; -#define NR_MASK_WORDS ((NR_IRQS + 31) / 32) -static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS]; +static unsigned long mpc8xx_cached_irq_mask; static sysconf8xx_t __iomem *siu_reg; -int cpm_get_irq(struct pt_regs *regs); +static inline unsigned long mpc8xx_irqd_to_bit(struct irq_data *d) +{ + return 0x80000000 >> irqd_to_hwirq(d); +} static void mpc8xx_unmask_irq(struct irq_data *d) { - int bit, word; - unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d); - - bit = irq_nr & 0x1f; - word = irq_nr >> 5; - - ppc_cached_irq_mask[word] |= (1 << (31-bit)); - out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]); + mpc8xx_cached_irq_mask |= mpc8xx_irqd_to_bit(d); + out_be32(&siu_reg->sc_simask, mpc8xx_cached_irq_mask); } static void mpc8xx_mask_irq(struct irq_data *d) { - int bit, word; - unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d); - - bit = irq_nr & 0x1f; - word = irq_nr >> 5; - - ppc_cached_irq_mask[word] &= ~(1 << (31-bit)); - out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]); + mpc8xx_cached_irq_mask &= ~mpc8xx_irqd_to_bit(d); + out_be32(&siu_reg->sc_simask, mpc8xx_cached_irq_mask); } static void mpc8xx_ack(struct irq_data *d) { - int bit; - unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d); - - bit = irq_nr & 0x1f; - out_be32(&siu_reg->sc_sipend, 1 << (31-bit)); + out_be32(&siu_reg->sc_sipend, mpc8xx_irqd_to_bit(d)); } static void mpc8xx_end_irq(struct irq_data *d) { - int bit, word; - unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d); - - bit = irq_nr & 0x1f; - word = irq_nr >> 5; - - ppc_cached_irq_mask[word] |= (1 << (31-bit)); - out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]); + mpc8xx_cached_irq_mask |= mpc8xx_irqd_to_bit(d); + out_be32(&siu_reg->sc_simask, mpc8xx_cached_irq_mask); } static int mpc8xx_set_irq_type(struct irq_data *d, unsigned int flow_type) { - if (flow_type & IRQ_TYPE_EDGE_FALLING) { - irq_hw_number_t hw = (unsigned int)irqd_to_hwirq(d); + /* only external IRQ senses are programmable */ + if ((flow_type & IRQ_TYPE_EDGE_FALLING) && !(irqd_to_hwirq(d) & 1)) { unsigned int siel = in_be32(&siu_reg->sc_siel); - - /* only external IRQ senses are programmable */ - if ((hw & 1) == 0) { - siel |= (0x80000000 >> hw); - out_be32(&siu_reg->sc_siel, siel); - __irq_set_handler_locked(d->irq, handle_edge_irq); - } + siel |= mpc8xx_irqd_to_bit(d); + out_be32(&siu_reg->sc_siel, siel); + __irq_set_handler_locked(d->irq, handle_edge_irq); } return 0; } @@ -132,6 +108,9 @@ static int mpc8xx_pic_host_xlate(struct irq_domain *h, struct device_node *ct, IRQ_TYPE_EDGE_FALLING, }; + if (intspec[0] > 0x1f) + return 0; + *out_hwirq = intspec[0]; if (intsize > 1 && intspec[1] < 4) *out_flags = map_pic_senses[intspec[1]]; diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c index 9ac71ebd2c40..395af1347749 100644 --- a/arch/powerpc/sysdev/mpic.c +++ b/arch/powerpc/sysdev/mpic.c @@ -604,18 +604,14 @@ static struct mpic *mpic_find(unsigned int irq) } /* Determine if the linux irq is an IPI */ -static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int irq) +static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int src) { - unsigned int src = virq_to_hw(irq); - return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]); } /* Determine if the linux irq is a timer */ -static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int irq) +static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int src) { - unsigned int src = virq_to_hw(irq); - return (src >= mpic->timer_vecs[0] && src <= mpic->timer_vecs[7]); } @@ -876,21 +872,45 @@ int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type) if (src >= mpic->num_sources) return -EINVAL; + vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)); + + /* We don't support "none" type */ if (flow_type == IRQ_TYPE_NONE) - if (mpic->senses && src < mpic->senses_count) - flow_type = mpic->senses[src]; - if (flow_type == IRQ_TYPE_NONE) - flow_type = IRQ_TYPE_LEVEL_LOW; + flow_type = IRQ_TYPE_DEFAULT; + + /* Default: read HW settings */ + if (flow_type == IRQ_TYPE_DEFAULT) { + switch(vold & (MPIC_INFO(VECPRI_POLARITY_MASK) | + MPIC_INFO(VECPRI_SENSE_MASK))) { + case MPIC_INFO(VECPRI_SENSE_EDGE) | + MPIC_INFO(VECPRI_POLARITY_POSITIVE): + flow_type = IRQ_TYPE_EDGE_RISING; + break; + case MPIC_INFO(VECPRI_SENSE_EDGE) | + MPIC_INFO(VECPRI_POLARITY_NEGATIVE): + flow_type = IRQ_TYPE_EDGE_FALLING; + break; + case MPIC_INFO(VECPRI_SENSE_LEVEL) | + MPIC_INFO(VECPRI_POLARITY_POSITIVE): + flow_type = IRQ_TYPE_LEVEL_HIGH; + break; + case MPIC_INFO(VECPRI_SENSE_LEVEL) | + MPIC_INFO(VECPRI_POLARITY_NEGATIVE): + flow_type = IRQ_TYPE_LEVEL_LOW; + break; + } + } + /* Apply to irq desc */ irqd_set_trigger_type(d, flow_type); + /* Apply to HW */ if (mpic_is_ht_interrupt(mpic, src)) vecpri = MPIC_VECPRI_POLARITY_POSITIVE | MPIC_VECPRI_SENSE_EDGE; else vecpri = mpic_type_to_vecpri(mpic, flow_type); - vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)); vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) | MPIC_INFO(VECPRI_SENSE_MASK)); vnew |= vecpri; @@ -1026,7 +1046,7 @@ static int mpic_host_map(struct irq_domain *h, unsigned int virq, irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq); /* Set default irq type */ - irq_set_irq_type(virq, IRQ_TYPE_NONE); + irq_set_irq_type(virq, IRQ_TYPE_DEFAULT); /* If the MPIC was reset, then all vectors have already been * initialized. Otherwise, a per source lazy initialization @@ -1417,12 +1437,6 @@ void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num, mpic->num_sources = isu_first + mpic->isu_size; } -void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count) -{ - mpic->senses = senses; - mpic->senses_count = count; -} - void __init mpic_init(struct mpic *mpic) { int i, cpu; @@ -1555,12 +1569,12 @@ void mpic_irq_set_priority(unsigned int irq, unsigned int pri) return; raw_spin_lock_irqsave(&mpic_lock, flags); - if (mpic_is_ipi(mpic, irq)) { + if (mpic_is_ipi(mpic, src)) { reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) & ~MPIC_VECPRI_PRIORITY_MASK; mpic_ipi_write(src - mpic->ipi_vecs[0], reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); - } else if (mpic_is_tm(mpic, irq)) { + } else if (mpic_is_tm(mpic, src)) { reg = mpic_tm_read(src - mpic->timer_vecs[0]) & ~MPIC_VECPRI_PRIORITY_MASK; mpic_tm_write(src - mpic->timer_vecs[0], diff --git a/arch/powerpc/sysdev/mpic_msgr.c b/arch/powerpc/sysdev/mpic_msgr.c index 6e7fa386e76a..483d8fa72e8b 100644 --- a/arch/powerpc/sysdev/mpic_msgr.c +++ b/arch/powerpc/sysdev/mpic_msgr.c @@ -27,6 +27,7 @@ static struct mpic_msgr **mpic_msgrs; static unsigned int mpic_msgr_count; +static DEFINE_RAW_SPINLOCK(msgrs_lock); static inline void _mpic_msgr_mer_write(struct mpic_msgr *msgr, u32 value) { @@ -56,12 +57,11 @@ struct mpic_msgr *mpic_msgr_get(unsigned int reg_num) if (reg_num >= mpic_msgr_count) return ERR_PTR(-ENODEV); - raw_spin_lock_irqsave(&msgr->lock, flags); - if (mpic_msgrs[reg_num]->in_use == MSGR_FREE) { - msgr = mpic_msgrs[reg_num]; + raw_spin_lock_irqsave(&msgrs_lock, flags); + msgr = mpic_msgrs[reg_num]; + if (msgr->in_use == MSGR_FREE) msgr->in_use = MSGR_INUSE; - } - raw_spin_unlock_irqrestore(&msgr->lock, flags); + raw_spin_unlock_irqrestore(&msgrs_lock, flags); return msgr; } @@ -228,7 +228,7 @@ static __devinit int mpic_msgr_probe(struct platform_device *dev) reg_number = block_number * MPIC_MSGR_REGISTERS_PER_BLOCK + i; msgr->base = msgr_block_addr + i * MPIC_MSGR_STRIDE; - msgr->mer = msgr->base + MPIC_MSGR_MER_OFFSET; + msgr->mer = (u32 *)((u8 *)msgr->base + MPIC_MSGR_MER_OFFSET); msgr->in_use = MSGR_FREE; msgr->num = i; raw_spin_lock_init(&msgr->lock); diff --git a/arch/powerpc/sysdev/scom.c b/arch/powerpc/sysdev/scom.c index 49a3ece1c6b3..702256a1ca11 100644 --- a/arch/powerpc/sysdev/scom.c +++ b/arch/powerpc/sysdev/scom.c @@ -22,6 +22,7 @@ #include <linux/debugfs.h> #include <linux/slab.h> #include <linux/export.h> +#include <asm/debug.h> #include <asm/prom.h> #include <asm/scom.h> diff --git a/arch/powerpc/sysdev/xics/xics-common.c b/arch/powerpc/sysdev/xics/xics-common.c index ea5e204e3450..cd1d18db92c6 100644 --- a/arch/powerpc/sysdev/xics/xics-common.c +++ b/arch/powerpc/sysdev/xics/xics-common.c @@ -188,6 +188,7 @@ void xics_migrate_irqs_away(void) { int cpu = smp_processor_id(), hw_cpu = hard_smp_processor_id(); unsigned int irq, virq; + struct irq_desc *desc; /* If we used to be the default server, move to the new "boot_cpuid" */ if (hw_cpu == xics_default_server) @@ -202,8 +203,7 @@ void xics_migrate_irqs_away(void) /* Allow IPIs again... */ icp_ops->set_priority(DEFAULT_PRIORITY); - for_each_irq(virq) { - struct irq_desc *desc; + for_each_irq_desc(virq, desc) { struct irq_chip *chip; long server; unsigned long flags; @@ -212,9 +212,8 @@ void xics_migrate_irqs_away(void) /* We can't set affinity on ISA interrupts */ if (virq < NUM_ISA_INTERRUPTS) continue; - desc = irq_to_desc(virq); /* We only need to migrate enabled IRQS */ - if (!desc || !desc->action) + if (!desc->action) continue; if (desc->irq_data.domain != xics_host) continue; diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig index 2b7c0fbe578e..b42f2866594b 100644 --- a/arch/s390/Kconfig +++ b/arch/s390/Kconfig @@ -90,7 +90,6 @@ config S390 select HAVE_KERNEL_XZ select HAVE_ARCH_MUTEX_CPU_RELAX select HAVE_ARCH_JUMP_LABEL if !MARCH_G5 - select HAVE_RCU_TABLE_FREE if SMP select ARCH_SAVE_PAGE_KEYS if HIBERNATION select HAVE_MEMBLOCK select HAVE_MEMBLOCK_NODE_MAP @@ -218,7 +217,7 @@ config COMPAT def_bool y prompt "Kernel support for 31 bit emulation" depends on 64BIT - select COMPAT_BINFMT_ELF + select COMPAT_BINFMT_ELF if BINFMT_ELF select ARCH_WANT_OLD_COMPAT_IPC help Select this option if you want to enable your system kernel to @@ -235,6 +234,25 @@ config KEYS_COMPAT config AUDIT_ARCH def_bool y +config HAVE_MARCH_Z900_FEATURES + def_bool n + +config HAVE_MARCH_Z990_FEATURES + def_bool n + select HAVE_MARCH_Z900_FEATURES + +config HAVE_MARCH_Z9_109_FEATURES + def_bool n + select HAVE_MARCH_Z990_FEATURES + +config HAVE_MARCH_Z10_FEATURES + def_bool n + select HAVE_MARCH_Z9_109_FEATURES + +config HAVE_MARCH_Z196_FEATURES + def_bool n + select HAVE_MARCH_Z10_FEATURES + comment "Code generation options" choice @@ -250,6 +268,7 @@ config MARCH_G5 config MARCH_Z900 bool "IBM zSeries model z800 and z900" + select HAVE_MARCH_Z900_FEATURES if 64BIT help Select this to enable optimizations for model z800/z900 (2064 and 2066 series). This will enable some optimizations that are not @@ -257,6 +276,7 @@ config MARCH_Z900 config MARCH_Z990 bool "IBM zSeries model z890 and z990" + select HAVE_MARCH_Z990_FEATURES if 64BIT help Select this to enable optimizations for model z890/z990 (2084 and 2086 series). The kernel will be slightly faster but will not work @@ -264,6 +284,7 @@ config MARCH_Z990 config MARCH_Z9_109 bool "IBM System z9" + select HAVE_MARCH_Z9_109_FEATURES if 64BIT help Select this to enable optimizations for IBM System z9 (2094 and 2096 series). The kernel will be slightly faster but will not work @@ -271,6 +292,7 @@ config MARCH_Z9_109 config MARCH_Z10 bool "IBM System z10" + select HAVE_MARCH_Z10_FEATURES if 64BIT help Select this to enable optimizations for IBM System z10 (2097 and 2098 series). The kernel will be slightly faster but will not work @@ -278,6 +300,7 @@ config MARCH_Z10 config MARCH_Z196 bool "IBM zEnterprise 114 and 196" + select HAVE_MARCH_Z196_FEATURES if 64BIT help Select this to enable optimizations for IBM zEnterprise 114 and 196 (2818 and 2817 series). The kernel will be slightly faster but will @@ -407,33 +430,6 @@ config CHSC_SCH comment "Misc" -config IPL - def_bool y - prompt "Builtin IPL record support" - help - If you want to use the produced kernel to IPL directly from a - device, you have to merge a bootsector specific to the device - into the first bytes of the kernel. You will have to select the - IPL device. - -choice - prompt "IPL method generated into head.S" - depends on IPL - default IPL_VM - help - Select "tape" if you want to IPL the image from a Tape. - - Select "vm_reader" if you are running under VM/ESA and want - to IPL the image from the emulated card reader. - -config IPL_TAPE - bool "tape" - -config IPL_VM - bool "vm_reader" - -endchoice - source "fs/Kconfig.binfmt" config FORCE_MAX_ZONEORDER @@ -570,7 +566,7 @@ config KEXEC config CRASH_DUMP bool "kernel crash dumps" - depends on 64BIT + depends on 64BIT && SMP select KEXEC help Generate crash dump after being started by kexec. diff --git a/arch/s390/boot/.gitignore b/arch/s390/boot/.gitignore new file mode 100644 index 000000000000..017d5912ad2d --- /dev/null +++ b/arch/s390/boot/.gitignore @@ -0,0 +1,2 @@ +image +bzImage diff --git a/arch/s390/boot/compressed/.gitignore b/arch/s390/boot/compressed/.gitignore new file mode 100644 index 000000000000..ae06b9b4c02f --- /dev/null +++ b/arch/s390/boot/compressed/.gitignore @@ -0,0 +1,3 @@ +sizes.h +vmlinux +vmlinux.lds diff --git a/arch/s390/defconfig b/arch/s390/defconfig index 6cf8e26b3137..37d2bf267964 100644 --- a/arch/s390/defconfig +++ b/arch/s390/defconfig @@ -1,8 +1,12 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y +CONFIG_FHANDLE=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y CONFIG_AUDIT=y -CONFIG_RCU_TRACE=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_CGROUPS=y @@ -14,16 +18,22 @@ CONFIG_CGROUP_MEM_RES_CTLR_SWAP=y CONFIG_CGROUP_SCHED=y CONFIG_RT_GROUP_SCHED=y CONFIG_BLK_CGROUP=y +CONFIG_NAMESPACES=y CONFIG_BLK_DEV_INITRD=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_RD_XZ=y +CONFIG_RD_LZO=y +CONFIG_EXPERT=y # CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y CONFIG_PROFILING=y CONFIG_OPROFILE=y CONFIG_KPROBES=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODVERSIONS=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_IBM_PARTITION=y CONFIG_DEFAULT_DEADLINE=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y @@ -34,18 +44,15 @@ CONFIG_KSM=y CONFIG_BINFMT_MISC=m CONFIG_CMM=m CONFIG_HZ_100=y -CONFIG_KEXEC=y -CONFIG_PM=y +CONFIG_CRASH_DUMP=y CONFIG_HIBERNATION=y CONFIG_PACKET=y CONFIG_UNIX=y CONFIG_NET_KEY=y -CONFIG_AFIUCV=m CONFIG_INET=y CONFIG_IP_MULTICAST=y # CONFIG_INET_LRO is not set CONFIG_IPV6=y -CONFIG_NET_SCTPPROBE=m CONFIG_L2TP=m CONFIG_L2TP_DEBUGFS=m CONFIG_VLAN_8021Q=y @@ -84,15 +91,14 @@ CONFIG_SCSI_CONSTANTS=y CONFIG_SCSI_LOGGING=y CONFIG_SCSI_SCAN_ASYNC=y CONFIG_ZFCP=y -CONFIG_ZFCP_DIF=y CONFIG_NETDEVICES=y -CONFIG_DUMMY=m CONFIG_BONDING=m +CONFIG_DUMMY=m CONFIG_EQUALIZER=m CONFIG_TUN=m -CONFIG_NET_ETHERNET=y CONFIG_VIRTIO_NET=y CONFIG_RAW_DRIVER=m +CONFIG_VIRTIO_BALLOON=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set @@ -103,27 +109,21 @@ CONFIG_PROC_KCORE=y CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y # CONFIG_NETWORK_FILESYSTEMS is not set -CONFIG_PARTITION_ADVANCED=y -CONFIG_IBM_PARTITION=y -CONFIG_DLM=m CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_KERNEL=y CONFIG_TIMER_STATS=y CONFIG_PROVE_LOCKING=y CONFIG_PROVE_RCU=y CONFIG_LOCK_STAT=y CONFIG_DEBUG_LOCKDEP=y -CONFIG_DEBUG_SPINLOCK_SLEEP=y CONFIG_DEBUG_LIST=y CONFIG_DEBUG_NOTIFIERS=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set +CONFIG_RCU_TRACE=y CONFIG_KPROBES_SANITY_TEST=y CONFIG_DEBUG_FORCE_WEAK_PER_CPU=y CONFIG_CPU_NOTIFIER_ERROR_INJECT=m CONFIG_LATENCYTOP=y -CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_DEBUG_PAGEALLOC=y -# CONFIG_FTRACE is not set +CONFIG_BLK_DEV_IO_TRACE=y # CONFIG_STRICT_DEVMEM is not set CONFIG_CRYPTO_NULL=m CONFIG_CRYPTO_CRYPTD=m @@ -155,7 +155,6 @@ CONFIG_CRYPTO_BLOWFISH=m CONFIG_CRYPTO_CAMELLIA=m CONFIG_CRYPTO_CAST5=m CONFIG_CRYPTO_CAST6=m -CONFIG_CRYPTO_DES=m CONFIG_CRYPTO_FCRYPT=m CONFIG_CRYPTO_KHAZAD=m CONFIG_CRYPTO_SALSA20=m @@ -173,4 +172,3 @@ CONFIG_CRYPTO_SHA512_S390=m CONFIG_CRYPTO_DES_S390=m CONFIG_CRYPTO_AES_S390=m CONFIG_CRC7=m -CONFIG_VIRTIO_BALLOON=y diff --git a/arch/s390/include/asm/barrier.h b/arch/s390/include/asm/barrier.h index 451273ad4d34..10a508802940 100644 --- a/arch/s390/include/asm/barrier.h +++ b/arch/s390/include/asm/barrier.h @@ -11,25 +11,28 @@ * Force strict CPU ordering. * And yes, this is required on UP too when we're talking * to devices. - * - * This is very similar to the ppc eieio/sync instruction in that is - * does a checkpoint syncronisation & makes sure that - * all memory ops have completed wrt other CPU's ( see 7-15 POP DJB ). */ -#define eieio() asm volatile("bcr 15,0" : : : "memory") -#define SYNC_OTHER_CORES(x) eieio() -#define mb() eieio() -#define rmb() eieio() -#define wmb() eieio() -#define read_barrier_depends() do { } while(0) -#define smp_mb() mb() -#define smp_rmb() rmb() -#define smp_wmb() wmb() -#define smp_read_barrier_depends() read_barrier_depends() -#define smp_mb__before_clear_bit() smp_mb() -#define smp_mb__after_clear_bit() smp_mb() +static inline void mb(void) +{ +#ifdef CONFIG_HAVE_MARCH_Z196_FEATURES + /* Fast-BCR without checkpoint synchronization */ + asm volatile("bcr 14,0" : : : "memory"); +#else + asm volatile("bcr 15,0" : : : "memory"); +#endif +} + +#define rmb() mb() +#define wmb() mb() +#define read_barrier_depends() do { } while(0) +#define smp_mb() mb() +#define smp_rmb() rmb() +#define smp_wmb() wmb() +#define smp_read_barrier_depends() read_barrier_depends() +#define smp_mb__before_clear_bit() smp_mb() +#define smp_mb__after_clear_bit() smp_mb() -#define set_mb(var, value) do { var = value; mb(); } while (0) +#define set_mb(var, value) do { var = value; mb(); } while (0) #endif /* __ASM_BARRIER_H */ diff --git a/arch/s390/include/asm/ccwgroup.h b/arch/s390/include/asm/ccwgroup.h index f2ea2c56a7e1..f2ef34f6d6e5 100644 --- a/arch/s390/include/asm/ccwgroup.h +++ b/arch/s390/include/asm/ccwgroup.h @@ -29,9 +29,7 @@ struct ccwgroup_device { /** * struct ccwgroup_driver - driver for ccw group devices - * @max_slaves: maximum number of slave devices - * @driver_id: unique id - * @probe: function called on probe + * @setup: function called during device creation to setup the device * @remove: function called on remove * @set_online: function called when device is set online * @set_offline: function called when device is set offline @@ -44,10 +42,7 @@ struct ccwgroup_device { * @driver: embedded driver structure */ struct ccwgroup_driver { - int max_slaves; - unsigned long driver_id; - - int (*probe) (struct ccwgroup_device *); + int (*setup) (struct ccwgroup_device *); void (*remove) (struct ccwgroup_device *); int (*set_online) (struct ccwgroup_device *); int (*set_offline) (struct ccwgroup_device *); @@ -63,9 +58,8 @@ struct ccwgroup_driver { extern int ccwgroup_driver_register (struct ccwgroup_driver *cdriver); extern void ccwgroup_driver_unregister (struct ccwgroup_driver *cdriver); -int ccwgroup_create_from_string(struct device *root, unsigned int creator_id, - struct ccw_driver *cdrv, int num_devices, - const char *buf); +int ccwgroup_create_dev(struct device *root, struct ccwgroup_driver *gdrv, + int num_devices, const char *buf); extern int ccwgroup_probe_ccwdev(struct ccw_device *cdev); extern void ccwgroup_remove_ccwdev(struct ccw_device *cdev); diff --git a/arch/s390/include/asm/facility.h b/arch/s390/include/asm/facility.h index 1e5b27edc0c9..2ee66a65f2d4 100644 --- a/arch/s390/include/asm/facility.h +++ b/arch/s390/include/asm/facility.h @@ -38,12 +38,11 @@ static inline void stfle(u64 *stfle_fac_list, int size) unsigned long nr; preempt_disable(); - S390_lowcore.stfl_fac_list = 0; asm volatile( " .insn s,0xb2b10000,0(0)\n" /* stfl */ "0:\n" EX_TABLE(0b, 0b) - : "=m" (S390_lowcore.stfl_fac_list)); + : "+m" (S390_lowcore.stfl_fac_list)); nr = 4; /* bytes stored by stfl */ memcpy(stfle_fac_list, &S390_lowcore.stfl_fac_list, 4); if (S390_lowcore.stfl_fac_list & 0x01000000) { diff --git a/arch/s390/include/asm/io.h b/arch/s390/include/asm/io.h index b7ff6afc3caa..27216d317991 100644 --- a/arch/s390/include/asm/io.h +++ b/arch/s390/include/asm/io.h @@ -38,11 +38,8 @@ static inline void * phys_to_virt(unsigned long address) return (void *) address; } -/* - * Convert a physical pointer to a virtual kernel pointer for /dev/mem - * access - */ -#define xlate_dev_mem_ptr(p) __va(p) +void *xlate_dev_mem_ptr(unsigned long phys); +void unxlate_dev_mem_ptr(unsigned long phys, void *addr); /* * Convert a virtual cached pointer to an uncached pointer diff --git a/arch/s390/include/asm/pgalloc.h b/arch/s390/include/asm/pgalloc.h index 8eef9b5b3cf4..78e3041919de 100644 --- a/arch/s390/include/asm/pgalloc.h +++ b/arch/s390/include/asm/pgalloc.h @@ -22,10 +22,7 @@ void crst_table_free(struct mm_struct *, unsigned long *); unsigned long *page_table_alloc(struct mm_struct *, unsigned long); void page_table_free(struct mm_struct *, unsigned long *); -#ifdef CONFIG_HAVE_RCU_TABLE_FREE void page_table_free_rcu(struct mmu_gather *, unsigned long *); -void __tlb_remove_table(void *_table); -#endif static inline void clear_table(unsigned long *s, unsigned long val, size_t n) { diff --git a/arch/s390/include/asm/qdio.h b/arch/s390/include/asm/qdio.h index d75c8e78f7e3..f039d86adf67 100644 --- a/arch/s390/include/asm/qdio.h +++ b/arch/s390/include/asm/qdio.h @@ -258,11 +258,6 @@ struct slsb { u8 val[QDIO_MAX_BUFFERS_PER_Q]; } __attribute__ ((packed, aligned(256))); -#define CHSC_AC2_MULTI_BUFFER_AVAILABLE 0x0080 -#define CHSC_AC2_MULTI_BUFFER_ENABLED 0x0040 -#define CHSC_AC2_DATA_DIV_AVAILABLE 0x0010 -#define CHSC_AC2_DATA_DIV_ENABLED 0x0002 - /** * struct qdio_outbuf_state - SBAL related asynchronous operation information * (for communication with upper layer programs) @@ -293,6 +288,8 @@ struct qdio_outbuf_state { #define AC1_SC_QEBSM_AVAILABLE 0x02 /* available for subchannel */ #define AC1_SC_QEBSM_ENABLED 0x01 /* enabled for subchannel */ +#define CHSC_AC2_MULTI_BUFFER_AVAILABLE 0x0080 +#define CHSC_AC2_MULTI_BUFFER_ENABLED 0x0040 #define CHSC_AC2_DATA_DIV_AVAILABLE 0x0010 #define CHSC_AC2_DATA_DIV_ENABLED 0x0002 @@ -328,11 +325,13 @@ typedef void qdio_handler_t(struct ccw_device *, unsigned int, int, int, int, unsigned long); /* qdio errors reported to the upper-layer program */ -#define QDIO_ERROR_SIGA_TARGET 0x02 -#define QDIO_ERROR_SIGA_ACCESS_EXCEPTION 0x10 -#define QDIO_ERROR_SIGA_BUSY 0x20 -#define QDIO_ERROR_ACTIVATE_CHECK_CONDITION 0x40 -#define QDIO_ERROR_SLSB_STATE 0x80 +#define QDIO_ERROR_ACTIVATE 0x0001 +#define QDIO_ERROR_GET_BUF_STATE 0x0002 +#define QDIO_ERROR_SET_BUF_STATE 0x0004 +#define QDIO_ERROR_SLSB_STATE 0x0100 + +#define QDIO_ERROR_FATAL 0x00ff +#define QDIO_ERROR_TEMPORARY 0xff00 /* for qdio_cleanup */ #define QDIO_FLAG_CLEANUP_USING_CLEAR 0x01 diff --git a/arch/s390/include/asm/setup.h b/arch/s390/include/asm/setup.h index b21e46e5d4b8..7244e1f64126 100644 --- a/arch/s390/include/asm/setup.h +++ b/arch/s390/include/asm/setup.h @@ -82,7 +82,6 @@ extern unsigned int user_mode; #define MACHINE_FLAG_LPAR (1UL << 12) #define MACHINE_FLAG_SPP (1UL << 13) #define MACHINE_FLAG_TOPOLOGY (1UL << 14) -#define MACHINE_FLAG_STCKF (1UL << 15) #define MACHINE_IS_VM (S390_lowcore.machine_flags & MACHINE_FLAG_VM) #define MACHINE_IS_KVM (S390_lowcore.machine_flags & MACHINE_FLAG_KVM) @@ -101,7 +100,6 @@ extern unsigned int user_mode; #define MACHINE_HAS_PFMF (0) #define MACHINE_HAS_SPP (0) #define MACHINE_HAS_TOPOLOGY (0) -#define MACHINE_HAS_STCKF (0) #else /* __s390x__ */ #define MACHINE_HAS_IEEE (1) #define MACHINE_HAS_CSP (1) @@ -113,7 +111,6 @@ extern unsigned int user_mode; #define MACHINE_HAS_PFMF (S390_lowcore.machine_flags & MACHINE_FLAG_PFMF) #define MACHINE_HAS_SPP (S390_lowcore.machine_flags & MACHINE_FLAG_SPP) #define MACHINE_HAS_TOPOLOGY (S390_lowcore.machine_flags & MACHINE_FLAG_TOPOLOGY) -#define MACHINE_HAS_STCKF (S390_lowcore.machine_flags & MACHINE_FLAG_STCKF) #endif /* __s390x__ */ #define ZFCPDUMP_HSA_SIZE (32UL<<20) diff --git a/arch/s390/include/asm/swab.h b/arch/s390/include/asm/swab.h index 6bdee21c077e..a3e4ebb32090 100644 --- a/arch/s390/include/asm/swab.h +++ b/arch/s390/include/asm/swab.h @@ -77,7 +77,7 @@ static inline __u16 __arch_swab16p(const __u16 *x) asm volatile( #ifndef __s390x__ - " icm %0,2,%O+1(%R1)\n" + " icm %0,2,%O1+1(%R1)\n" " ic %0,%1\n" : "=&d" (result) : "Q" (*x) : "cc"); #else /* __s390x__ */ diff --git a/arch/s390/include/asm/thread_info.h b/arch/s390/include/asm/thread_info.h index a73038155e0d..003b04edcff6 100644 --- a/arch/s390/include/asm/thread_info.h +++ b/arch/s390/include/asm/thread_info.h @@ -95,7 +95,6 @@ static inline struct thread_info *current_thread_info(void) #define TIF_SYSCALL_AUDIT 9 /* syscall auditing active */ #define TIF_SECCOMP 10 /* secure computing */ #define TIF_SYSCALL_TRACEPOINT 11 /* syscall tracepoint instrumentation */ -#define TIF_SIE 12 /* guest execution active */ #define TIF_POLLING_NRFLAG 16 /* true if poll_idle() is polling TIF_NEED_RESCHED */ #define TIF_31BIT 17 /* 32bit process */ @@ -114,7 +113,6 @@ static inline struct thread_info *current_thread_info(void) #define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT) #define _TIF_SECCOMP (1<<TIF_SECCOMP) #define _TIF_SYSCALL_TRACEPOINT (1<<TIF_SYSCALL_TRACEPOINT) -#define _TIF_SIE (1<<TIF_SIE) #define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG) #define _TIF_31BIT (1<<TIF_31BIT) #define _TIF_SINGLE_STEP (1<<TIF_SINGLE_STEP) diff --git a/arch/s390/include/asm/timex.h b/arch/s390/include/asm/timex.h index c447a27a7fdb..239ece9e53c1 100644 --- a/arch/s390/include/asm/timex.h +++ b/arch/s390/include/asm/timex.h @@ -73,11 +73,15 @@ static inline void local_tick_enable(unsigned long long comp) typedef unsigned long long cycles_t; -static inline unsigned long long get_clock (void) +static inline unsigned long long get_clock(void) { unsigned long long clk; +#ifdef CONFIG_HAVE_MARCH_Z9_109_FEATURES + asm volatile(".insn s,0xb27c0000,%0" : "=Q" (clk) : : "cc"); +#else asm volatile("stck %0" : "=Q" (clk) : : "cc"); +#endif return clk; } @@ -86,17 +90,6 @@ static inline void get_clock_ext(char *clk) asm volatile("stcke %0" : "=Q" (*clk) : : "cc"); } -static inline unsigned long long get_clock_fast(void) -{ - unsigned long long clk; - - if (MACHINE_HAS_STCKF) - asm volatile(".insn s,0xb27c0000,%0" : "=Q" (clk) : : "cc"); - else - clk = get_clock(); - return clk; -} - static inline unsigned long long get_clock_xt(void) { unsigned char clk[16]; diff --git a/arch/s390/include/asm/tlb.h b/arch/s390/include/asm/tlb.h index c687a2c83462..775a5eea8f9e 100644 --- a/arch/s390/include/asm/tlb.h +++ b/arch/s390/include/asm/tlb.h @@ -30,14 +30,10 @@ struct mmu_gather { struct mm_struct *mm; -#ifdef CONFIG_HAVE_RCU_TABLE_FREE struct mmu_table_batch *batch; -#endif unsigned int fullmm; - unsigned int need_flush; }; -#ifdef CONFIG_HAVE_RCU_TABLE_FREE struct mmu_table_batch { struct rcu_head rcu; unsigned int nr; @@ -49,7 +45,6 @@ struct mmu_table_batch { extern void tlb_table_flush(struct mmu_gather *tlb); extern void tlb_remove_table(struct mmu_gather *tlb, void *table); -#endif static inline void tlb_gather_mmu(struct mmu_gather *tlb, struct mm_struct *mm, @@ -57,29 +52,20 @@ static inline void tlb_gather_mmu(struct mmu_gather *tlb, { tlb->mm = mm; tlb->fullmm = full_mm_flush; - tlb->need_flush = 0; -#ifdef CONFIG_HAVE_RCU_TABLE_FREE tlb->batch = NULL; -#endif if (tlb->fullmm) __tlb_flush_mm(mm); } static inline void tlb_flush_mmu(struct mmu_gather *tlb) { - if (!tlb->need_flush) - return; - tlb->need_flush = 0; - __tlb_flush_mm(tlb->mm); -#ifdef CONFIG_HAVE_RCU_TABLE_FREE tlb_table_flush(tlb); -#endif } static inline void tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end) { - tlb_flush_mmu(tlb); + tlb_table_flush(tlb); } /* @@ -105,10 +91,8 @@ static inline void tlb_remove_page(struct mmu_gather *tlb, struct page *page) static inline void pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte, unsigned long address) { -#ifdef CONFIG_HAVE_RCU_TABLE_FREE if (!tlb->fullmm) return page_table_free_rcu(tlb, (unsigned long *) pte); -#endif page_table_free(tlb->mm, (unsigned long *) pte); } @@ -125,10 +109,8 @@ static inline void pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmd, #ifdef __s390x__ if (tlb->mm->context.asce_limit <= (1UL << 31)) return; -#ifdef CONFIG_HAVE_RCU_TABLE_FREE if (!tlb->fullmm) return tlb_remove_table(tlb, pmd); -#endif crst_table_free(tlb->mm, (unsigned long *) pmd); #endif } @@ -146,10 +128,8 @@ static inline void pud_free_tlb(struct mmu_gather *tlb, pud_t *pud, #ifdef __s390x__ if (tlb->mm->context.asce_limit <= (1UL << 42)) return; -#ifdef CONFIG_HAVE_RCU_TABLE_FREE if (!tlb->fullmm) return tlb_remove_table(tlb, pud); -#endif crst_table_free(tlb->mm, (unsigned long *) pud); #endif } diff --git a/arch/s390/kernel/.gitignore b/arch/s390/kernel/.gitignore new file mode 100644 index 000000000000..c5f676c3c224 --- /dev/null +++ b/arch/s390/kernel/.gitignore @@ -0,0 +1 @@ +vmlinux.lds diff --git a/arch/s390/kernel/compat_signal.c b/arch/s390/kernel/compat_signal.c index 28040fd5e8a2..377c096ca4a7 100644 --- a/arch/s390/kernel/compat_signal.c +++ b/arch/s390/kernel/compat_signal.c @@ -437,13 +437,6 @@ get_sigframe(struct k_sigaction *ka, struct pt_regs * regs, size_t frame_size) sp = current->sas_ss_sp + current->sas_ss_size; } - /* This is the legacy signal stack switching. */ - else if (!user_mode(regs) && - !(ka->sa.sa_flags & SA_RESTORER) && - ka->sa.sa_restorer) { - sp = (unsigned long) ka->sa.sa_restorer; - } - return (void __user *)((sp - frame_size) & -8ul); } diff --git a/arch/s390/kernel/early.c b/arch/s390/kernel/early.c index 9475e682727f..d84181f1f5e8 100644 --- a/arch/s390/kernel/early.c +++ b/arch/s390/kernel/early.c @@ -374,8 +374,6 @@ static __init void detect_machine_facilities(void) S390_lowcore.machine_flags |= MACHINE_FLAG_MVCOS; if (test_facility(40)) S390_lowcore.machine_flags |= MACHINE_FLAG_SPP; - if (test_facility(25)) - S390_lowcore.machine_flags |= MACHINE_FLAG_STCKF; #endif } diff --git a/arch/s390/kernel/entry.S b/arch/s390/kernel/entry.S index 74ee563fe62b..1ae93b573d7d 100644 --- a/arch/s390/kernel/entry.S +++ b/arch/s390/kernel/entry.S @@ -145,22 +145,23 @@ STACK_SIZE = 1 << STACK_SHIFT * gpr2 = prev */ ENTRY(__switch_to) + stm %r6,%r15,__SF_GPRS(%r15) # store gprs of prev task + st %r15,__THREAD_ksp(%r2) # store kernel stack of prev l %r4,__THREAD_info(%r2) # get thread_info of prev l %r5,__THREAD_info(%r3) # get thread_info of next + lr %r15,%r5 + ahi %r15,STACK_SIZE # end of kernel stack of next + st %r3,__LC_CURRENT # store task struct of next + st %r5,__LC_THREAD_INFO # store thread info of next + st %r15,__LC_KERNEL_STACK # store end of kernel stack + lctl %c4,%c4,__TASK_pid(%r3) # load pid to control reg. 4 + mvc __LC_CURRENT_PID(4,%r0),__TASK_pid(%r3) # store pid of next + l %r15,__THREAD_ksp(%r3) # load kernel stack of next tm __TI_flags+3(%r4),_TIF_MCCK_PENDING # machine check pending? jz 0f ni __TI_flags+3(%r4),255-_TIF_MCCK_PENDING # clear flag in prev oi __TI_flags+3(%r5),_TIF_MCCK_PENDING # set it in next -0: stm %r6,%r15,__SF_GPRS(%r15) # store gprs of prev task - st %r15,__THREAD_ksp(%r2) # store kernel stack of prev - l %r15,__THREAD_ksp(%r3) # load kernel stack of next - lctl %c4,%c4,__TASK_pid(%r3) # load pid to control reg. 4 - lm %r6,%r15,__SF_GPRS(%r15) # load gprs of next task - st %r3,__LC_CURRENT # store task struct of next - mvc __LC_CURRENT_PID(4,%r0),__TASK_pid(%r3) # store pid of next - st %r5,__LC_THREAD_INFO # store thread info of next - ahi %r5,STACK_SIZE # end of kernel stack of next - st %r5,__LC_KERNEL_STACK # store end of kernel stack +0: lm %r6,%r15,__SF_GPRS(%r15) # load gprs of next task br %r14 __critical_start: diff --git a/arch/s390/kernel/entry64.S b/arch/s390/kernel/entry64.S index 4e1c292fa7e3..229fe1d07749 100644 --- a/arch/s390/kernel/entry64.S +++ b/arch/s390/kernel/entry64.S @@ -81,16 +81,14 @@ _TIF_EXIT_SIE = (_TIF_SIGPENDING | _TIF_NEED_RESCHED | _TIF_MCCK_PENDING) .macro HANDLE_SIE_INTERCEPT scratch #if defined(CONFIG_KVM) || defined(CONFIG_KVM_MODULE) - tm __TI_flags+6(%r12),_TIF_SIE>>8 - jz .+42 - tm __LC_MACHINE_FLAGS+6,0x20 # MACHINE_FLAG_SPP - jz .+8 - .insn s,0xb2800000,BASED(.Lhost_id) # set host id + tmhh %r8,0x0001 # interrupting from user ? + jnz .+42 lgr \scratch,%r9 slg \scratch,BASED(.Lsie_loop) clg \scratch,BASED(.Lsie_length) - jhe .+10 + jhe .+22 lg %r9,BASED(.Lsie_loop) + SPP BASED(.Lhost_id) # set host id #endif .endm @@ -148,6 +146,14 @@ _TIF_EXIT_SIE = (_TIF_SIGPENDING | _TIF_NEED_RESCHED | _TIF_MCCK_PENDING) ssm __LC_RETURN_PSW .endm + .macro STCK savearea +#ifdef CONFIG_HAVE_MARCH_Z9_109_FEATURES + .insn s,0xb27c0000,\savearea # store clock fast +#else + .insn s,0xb2050000,\savearea # store clock +#endif + .endm + .section .kprobes.text, "ax" /* @@ -158,22 +164,23 @@ _TIF_EXIT_SIE = (_TIF_SIGPENDING | _TIF_NEED_RESCHED | _TIF_MCCK_PENDING) * gpr2 = prev */ ENTRY(__switch_to) + stmg %r6,%r15,__SF_GPRS(%r15) # store gprs of prev task + stg %r15,__THREAD_ksp(%r2) # store kernel stack of prev lg %r4,__THREAD_info(%r2) # get thread_info of prev lg %r5,__THREAD_info(%r3) # get thread_info of next + lgr %r15,%r5 + aghi %r15,STACK_SIZE # end of kernel stack of next + stg %r3,__LC_CURRENT # store task struct of next + stg %r5,__LC_THREAD_INFO # store thread info of next + stg %r15,__LC_KERNEL_STACK # store end of kernel stack + lctl %c4,%c4,__TASK_pid(%r3) # load pid to control reg. 4 + mvc __LC_CURRENT_PID+4(4,%r0),__TASK_pid(%r3) # store pid of next + lg %r15,__THREAD_ksp(%r3) # load kernel stack of next tm __TI_flags+7(%r4),_TIF_MCCK_PENDING # machine check pending? jz 0f ni __TI_flags+7(%r4),255-_TIF_MCCK_PENDING # clear flag in prev oi __TI_flags+7(%r5),_TIF_MCCK_PENDING # set it in next -0: stmg %r6,%r15,__SF_GPRS(%r15) # store gprs of prev task - stg %r15,__THREAD_ksp(%r2) # store kernel stack of prev - lg %r15,__THREAD_ksp(%r3) # load kernel stack of next - lctl %c4,%c4,__TASK_pid(%r3) # load pid to control reg. 4 - lmg %r6,%r15,__SF_GPRS(%r15) # load gprs of next task - stg %r3,__LC_CURRENT # store task struct of next - mvc __LC_CURRENT_PID+4(4,%r0),__TASK_pid(%r3) # store pid of next - stg %r5,__LC_THREAD_INFO # store thread info of next - aghi %r5,STACK_SIZE # end of kernel stack of next - stg %r5,__LC_KERNEL_STACK # store end of kernel stack +0: lmg %r6,%r15,__SF_GPRS(%r15) # load gprs of next task br %r14 __critical_start: @@ -458,7 +465,7 @@ pgm_svcper: * IO interrupt handler routine */ ENTRY(io_int_handler) - stck __LC_INT_CLOCK + STCK __LC_INT_CLOCK stpt __LC_ASYNC_ENTER_TIMER stmg %r8,%r15,__LC_SAVE_AREA_ASYNC lg %r10,__LC_LAST_BREAK @@ -604,7 +611,7 @@ io_notify_resume: * External interrupt handler routine */ ENTRY(ext_int_handler) - stck __LC_INT_CLOCK + STCK __LC_INT_CLOCK stpt __LC_ASYNC_ENTER_TIMER stmg %r8,%r15,__LC_SAVE_AREA_ASYNC lg %r10,__LC_LAST_BREAK @@ -622,6 +629,7 @@ ext_skip: mvc __PT_R8(64,%r11),__LC_SAVE_AREA_ASYNC stmg %r8,%r9,__PT_PSW(%r11) TRACE_IRQS_OFF + xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15) lghi %r1,4096 lgr %r2,%r11 # pass pointer to pt_regs llgf %r3,__LC_EXT_CPU_ADDR # get cpu address + interruption code @@ -638,7 +646,7 @@ ENTRY(psw_idle) larl %r1,psw_idle_lpsw+4 stg %r1,__SF_EMPTY+8(%r15) larl %r1,.Lvtimer_max - stck __IDLE_ENTER(%r2) + STCK __IDLE_ENTER(%r2) ltr %r5,%r5 stpt __VQ_IDLE_ENTER(%r3) jz psw_idle_lpsw @@ -654,7 +662,7 @@ __critical_end: * Machine check handler routines */ ENTRY(mcck_int_handler) - stck __LC_MCCK_CLOCK + STCK __LC_MCCK_CLOCK la %r1,4095 # revalidate r1 spt __LC_CPU_TIMER_SAVE_AREA-4095(%r1) # revalidate cpu timer lmg %r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r1)# revalidate gprs @@ -967,7 +975,6 @@ ENTRY(sie64a) xc __SF_EMPTY+16(8,%r15),__SF_EMPTY+16(%r15) # host id == 0 lmg %r0,%r13,0(%r3) # load guest gprs 0-13 lg %r14,__LC_THREAD_INFO # pointer thread_info struct - oi __TI_flags+6(%r14),_TIF_SIE>>8 sie_loop: lg %r14,__LC_THREAD_INFO # pointer thread_info struct tm __TI_flags+7(%r14),_TIF_EXIT_SIE @@ -985,7 +992,6 @@ sie_done: lg %r14,__LC_THREAD_INFO # pointer thread_info struct sie_exit: lctlg %c1,%c1,__LC_USER_ASCE # load primary asce - ni __TI_flags+6(%r14),255-(_TIF_SIE>>8) lg %r14,__SF_EMPTY+8(%r15) # load guest register save area stmg %r0,%r13,0(%r14) # save guest gprs 0-13 lmg %r6,%r14,__SF_GPRS(%r15) # restore kernel registers @@ -994,7 +1000,6 @@ sie_exit: sie_fault: lctlg %c1,%c1,__LC_USER_ASCE # load primary asce lg %r14,__LC_THREAD_INFO # pointer thread_info struct - ni __TI_flags+6(%r14),255-(_TIF_SIE>>8) lg %r14,__SF_EMPTY+8(%r15) # load guest register save area stmg %r0,%r13,0(%r14) # save guest gprs 0-13 lmg %r6,%r14,__SF_GPRS(%r15) # restore kernel registers diff --git a/arch/s390/kernel/head.S b/arch/s390/kernel/head.S index c27a0727f930..4939d15375aa 100644 --- a/arch/s390/kernel/head.S +++ b/arch/s390/kernel/head.S @@ -34,125 +34,7 @@ #endif __HEAD -#ifndef CONFIG_IPL - .org 0 - .long 0x00080000,0x80000000+startup # Just a restart PSW -#else -#ifdef CONFIG_IPL_TAPE -#define IPL_BS 1024 - .org 0 - .long 0x00080000,0x80000000+iplstart # The first 24 bytes are loaded - .long 0x27000000,0x60000001 # by ipl to addresses 0-23. - .long 0x02000000,0x20000000+IPL_BS # (a PSW and two CCWs). - .long 0x00000000,0x00000000 # external old psw - .long 0x00000000,0x00000000 # svc old psw - .long 0x00000000,0x00000000 # program check old psw - .long 0x00000000,0x00000000 # machine check old psw - .long 0x00000000,0x00000000 # io old psw - .long 0x00000000,0x00000000 - .long 0x00000000,0x00000000 - .long 0x00000000,0x00000000 - .long 0x000a0000,0x00000058 # external new psw - .long 0x000a0000,0x00000060 # svc new psw - .long 0x000a0000,0x00000068 # program check new psw - .long 0x000a0000,0x00000070 # machine check new psw - .long 0x00080000,0x80000000+.Lioint # io new psw - .org 0x100 -# -# subroutine for loading from tape -# Parameters: -# R1 = device number -# R2 = load address -.Lloader: - st %r14,.Lldret - la %r3,.Lorbread # r3 = address of orb - la %r5,.Lirb # r5 = address of irb - st %r2,.Lccwread+4 # initialize CCW data addresses - lctl %c6,%c6,.Lcr6 - slr %r2,%r2 -.Lldlp: - la %r6,3 # 3 retries -.Lssch: - ssch 0(%r3) # load chunk of IPL_BS bytes - bnz .Llderr -.Lw4end: - bas %r14,.Lwait4io - tm 8(%r5),0x82 # do we have a problem ? - bnz .Lrecov - slr %r7,%r7 - icm %r7,3,10(%r5) # get residual count - lcr %r7,%r7 - la %r7,IPL_BS(%r7) # IPL_BS-residual=#bytes read - ar %r2,%r7 # add to total size - tm 8(%r5),0x01 # found a tape mark ? - bnz .Ldone - l %r0,.Lccwread+4 # update CCW data addresses - ar %r0,%r7 - st %r0,.Lccwread+4 - b .Lldlp -.Ldone: - l %r14,.Lldret - br %r14 # r2 contains the total size -.Lrecov: - bas %r14,.Lsense # do the sensing - bct %r6,.Lssch # dec. retry count & branch - b .Llderr -# -# Sense subroutine -# -.Lsense: - st %r14,.Lsnsret - la %r7,.Lorbsense - ssch 0(%r7) # start sense command - bnz .Llderr - bas %r14,.Lwait4io - l %r14,.Lsnsret - tm 8(%r5),0x82 # do we have a problem ? - bnz .Llderr - br %r14 -# -# Wait for interrupt subroutine -# -.Lwait4io: - lpsw .Lwaitpsw -.Lioint: - c %r1,0xb8 # compare subchannel number - bne .Lwait4io - tsch 0(%r5) - slr %r0,%r0 - tm 8(%r5),0x82 # do we have a problem ? - bnz .Lwtexit - tm 8(%r5),0x04 # got device end ? - bz .Lwait4io -.Lwtexit: - br %r14 -.Llderr: - lpsw .Lcrash - - .align 8 -.Lorbread: - .long 0x00000000,0x0080ff00,.Lccwread - .align 8 -.Lorbsense: - .long 0x00000000,0x0080ff00,.Lccwsense - .align 8 -.Lccwread: - .long 0x02200000+IPL_BS,0x00000000 -.Lccwsense: - .long 0x04200001,0x00000000 -.Lwaitpsw: - .long 0x020a0000,0x80000000+.Lioint - -.Lirb: .long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 -.Lcr6: .long 0xff000000 - .align 8 -.Lcrash:.long 0x000a0000,0x00000000 -.Lldret:.long 0 -.Lsnsret: .long 0 -#endif /* CONFIG_IPL_TAPE */ - -#ifdef CONFIG_IPL_VM #define IPL_BS 0x730 .org 0 .long 0x00080000,0x80000000+iplstart # The first 24 bytes are loaded @@ -256,7 +138,6 @@ __HEAD .long 0x02600050,0x00000000 .endr .long 0x02200050,0x00000000 -#endif /* CONFIG_IPL_VM */ iplstart: lh %r1,0xb8 # test if subchannel number @@ -325,7 +206,6 @@ iplstart: clc 0(3,%r2),.L_eof bz .Lagain2 -#ifdef CONFIG_IPL_VM # # reset files in VM reader # @@ -358,7 +238,6 @@ iplstart: .long 0x00080000,0x80000000+.Lrdrint .Lrdrwaitpsw: .long 0x020a0000,0x80000000+.Lrdrint -#endif # # everything loaded, go for it @@ -376,8 +255,6 @@ iplstart: .L_eof: .long 0xc5d6c600 /* C'EOF' */ .L_hdr: .long 0xc8c4d900 /* C'HDR' */ -#endif /* CONFIG_IPL */ - # # SALIPL loader support. Based on a patch by Rob van der Heij. # This entry point is called directly from the SALIPL loader and @@ -474,9 +351,9 @@ ENTRY(startup_kdump) stck __LC_LAST_UPDATE_CLOCK spt 5f-.LPG0(%r13) mvc __LC_LAST_UPDATE_TIMER(8),5f-.LPG0(%r13) + xc __LC_STFL_FAC_LIST(8),__LC_STFL_FAC_LIST #ifndef CONFIG_MARCH_G5 # check capabilities against MARCH_{G5,Z900,Z990,Z9_109,Z10} - xc __LC_STFL_FAC_LIST(8),__LC_STFL_FAC_LIST .insn s,0xb2b10000,__LC_STFL_FAC_LIST # store facility list tm __LC_STFL_FAC_LIST,0x01 # stfle available ? jz 0f diff --git a/arch/s390/kernel/irq.c b/arch/s390/kernel/irq.c index 1c2cdd59ccd0..8a22c27219dd 100644 --- a/arch/s390/kernel/irq.c +++ b/arch/s390/kernel/irq.c @@ -118,9 +118,10 @@ asmlinkage void do_softirq(void) "a" (__do_softirq) : "0", "1", "2", "3", "4", "5", "14", "cc", "memory" ); - } else + } else { /* We are already on the async stack. */ __do_softirq(); + } } local_irq_restore(flags); @@ -192,11 +193,12 @@ int unregister_external_interrupt(u16 code, ext_int_handler_t handler) int index = ext_hash(code); spin_lock_irqsave(&ext_int_hash_lock, flags); - list_for_each_entry_rcu(p, &ext_int_hash[index], entry) + list_for_each_entry_rcu(p, &ext_int_hash[index], entry) { if (p->code == code && p->handler == handler) { list_del_rcu(&p->entry); kfree_rcu(p, rcu); } + } spin_unlock_irqrestore(&ext_int_hash_lock, flags); return 0; } @@ -211,9 +213,10 @@ void __irq_entry do_extint(struct pt_regs *regs, struct ext_code ext_code, old_regs = set_irq_regs(regs); irq_enter(); - if (S390_lowcore.int_clock >= S390_lowcore.clock_comparator) + if (S390_lowcore.int_clock >= S390_lowcore.clock_comparator) { /* Serve timer interrupts first. */ clock_comparator_work(); + } kstat_cpu(smp_processor_id()).irqs[EXTERNAL_INTERRUPT]++; if (ext_code.code != 0x1004) __get_cpu_var(s390_idle).nohz_delay = 1; diff --git a/arch/s390/kernel/perf_cpum_cf.c b/arch/s390/kernel/perf_cpum_cf.c index 46405086479c..cb019f429e88 100644 --- a/arch/s390/kernel/perf_cpum_cf.c +++ b/arch/s390/kernel/perf_cpum_cf.c @@ -178,7 +178,7 @@ static void cpumf_pmu_enable(struct pmu *pmu) err = lcctl(cpuhw->state); if (err) { pr_err("Enabling the performance measuring unit " - "failed with rc=%lx\n", err); + "failed with rc=%x\n", err); return; } @@ -203,7 +203,7 @@ static void cpumf_pmu_disable(struct pmu *pmu) err = lcctl(inactive); if (err) { pr_err("Disabling the performance measuring unit " - "failed with rc=%lx\n", err); + "failed with rc=%x\n", err); return; } diff --git a/arch/s390/kernel/signal.c b/arch/s390/kernel/signal.c index f7582b27f600..8a4e2b760d56 100644 --- a/arch/s390/kernel/signal.c +++ b/arch/s390/kernel/signal.c @@ -235,13 +235,6 @@ get_sigframe(struct k_sigaction *ka, struct pt_regs * regs, size_t frame_size) sp = current->sas_ss_sp + current->sas_ss_size; } - /* This is the legacy signal stack switching. */ - else if (!user_mode(regs) && - !(ka->sa.sa_flags & SA_RESTORER) && - ka->sa.sa_restorer) { - sp = (unsigned long) ka->sa.sa_restorer; - } - return (void __user *)((sp - frame_size) & -8ul); } @@ -414,15 +407,6 @@ void do_signal(struct pt_regs *regs) struct k_sigaction ka; sigset_t *oldset; - /* - * We want the common case to go fast, which - * is why we may in certain cases get here from - * kernel mode. Just return without doing anything - * if so. - */ - if (!user_mode(regs)) - return; - if (test_thread_flag(TIF_RESTORE_SIGMASK)) oldset = ¤t->saved_sigmask; else diff --git a/arch/s390/kernel/smp.c b/arch/s390/kernel/smp.c index 1f77227669e8..e505458c6899 100644 --- a/arch/s390/kernel/smp.c +++ b/arch/s390/kernel/smp.c @@ -226,6 +226,8 @@ out: return -ENOMEM; } +#ifdef CONFIG_HOTPLUG_CPU + static void pcpu_free_lowcore(struct pcpu *pcpu) { pcpu_sigp_retry(pcpu, sigp_set_prefix, 0); @@ -247,6 +249,8 @@ static void pcpu_free_lowcore(struct pcpu *pcpu) } } +#endif /* CONFIG_HOTPLUG_CPU */ + static void pcpu_prepare_secondary(struct pcpu *pcpu, int cpu) { struct _lowcore *lc = pcpu->lowcore; diff --git a/arch/s390/kernel/vdso32/.gitignore b/arch/s390/kernel/vdso32/.gitignore new file mode 100644 index 000000000000..e45fba9d0ced --- /dev/null +++ b/arch/s390/kernel/vdso32/.gitignore @@ -0,0 +1 @@ +vdso32.lds diff --git a/arch/s390/kernel/vdso64/.gitignore b/arch/s390/kernel/vdso64/.gitignore new file mode 100644 index 000000000000..3fd18cf9fec2 --- /dev/null +++ b/arch/s390/kernel/vdso64/.gitignore @@ -0,0 +1 @@ +vdso64.lds diff --git a/arch/s390/mm/fault.c b/arch/s390/mm/fault.c index 46ef3fd0663b..72cec9ecd96c 100644 --- a/arch/s390/mm/fault.c +++ b/arch/s390/mm/fault.c @@ -294,7 +294,7 @@ static inline int do_exception(struct pt_regs *regs, int access) down_read(&mm->mmap_sem); #ifdef CONFIG_PGSTE - if (test_tsk_thread_flag(current, TIF_SIE) && S390_lowcore.gmap) { + if ((current->flags & PF_VCPU) && S390_lowcore.gmap) { address = __gmap_fault(address, (struct gmap *) S390_lowcore.gmap); if (address == -EFAULT) { @@ -549,19 +549,15 @@ static void pfault_interrupt(struct ext_code ext_code, if ((subcode & 0xff00) != __SUBCODE_MASK) return; kstat_cpu(smp_processor_id()).irqs[EXTINT_PFL]++; - if (subcode & 0x0080) { - /* Get the token (= pid of the affected task). */ - pid = sizeof(void *) == 4 ? param32 : param64; - rcu_read_lock(); - tsk = find_task_by_pid_ns(pid, &init_pid_ns); - if (tsk) - get_task_struct(tsk); - rcu_read_unlock(); - if (!tsk) - return; - } else { - tsk = current; - } + /* Get the token (= pid of the affected task). */ + pid = sizeof(void *) == 4 ? param32 : param64; + rcu_read_lock(); + tsk = find_task_by_pid_ns(pid, &init_pid_ns); + if (tsk) + get_task_struct(tsk); + rcu_read_unlock(); + if (!tsk) + return; spin_lock(&pfault_lock); if (subcode & 0x0080) { /* signal bit is set -> a page has been swapped in by VM */ @@ -574,6 +570,7 @@ static void pfault_interrupt(struct ext_code ext_code, tsk->thread.pfault_wait = 0; list_del(&tsk->thread.list); wake_up_process(tsk); + put_task_struct(tsk); } else { /* Completion interrupt was faster than initial * interrupt. Set pfault_wait to -1 so the initial @@ -585,24 +582,35 @@ static void pfault_interrupt(struct ext_code ext_code, if (tsk->state == TASK_RUNNING) tsk->thread.pfault_wait = -1; } - put_task_struct(tsk); } else { /* signal bit not set -> a real page is missing. */ - if (tsk->thread.pfault_wait == -1) { + if (WARN_ON_ONCE(tsk != current)) + goto out; + if (tsk->thread.pfault_wait == 1) { + /* Already on the list with a reference: put to sleep */ + __set_task_state(tsk, TASK_UNINTERRUPTIBLE); + set_tsk_need_resched(tsk); + } else if (tsk->thread.pfault_wait == -1) { /* Completion interrupt was faster than the initial * interrupt (pfault_wait == -1). Set pfault_wait * back to zero and exit. */ tsk->thread.pfault_wait = 0; } else { /* Initial interrupt arrived before completion - * interrupt. Let the task sleep. */ + * interrupt. Let the task sleep. + * An extra task reference is needed since a different + * cpu may set the task state to TASK_RUNNING again + * before the scheduler is reached. */ + get_task_struct(tsk); tsk->thread.pfault_wait = 1; list_add(&tsk->thread.list, &pfault_list); - set_task_state(tsk, TASK_UNINTERRUPTIBLE); + __set_task_state(tsk, TASK_UNINTERRUPTIBLE); set_tsk_need_resched(tsk); } } +out: spin_unlock(&pfault_lock); + put_task_struct(tsk); } static int __cpuinit pfault_cpu_notify(struct notifier_block *self, @@ -620,6 +628,7 @@ static int __cpuinit pfault_cpu_notify(struct notifier_block *self, list_del(&thread->list); tsk = container_of(thread, struct task_struct, thread); wake_up_process(tsk); + put_task_struct(tsk); } spin_unlock_irq(&pfault_lock); break; diff --git a/arch/s390/mm/hugetlbpage.c b/arch/s390/mm/hugetlbpage.c index 597bb2d27c3c..900de2b3cf28 100644 --- a/arch/s390/mm/hugetlbpage.c +++ b/arch/s390/mm/hugetlbpage.c @@ -58,6 +58,8 @@ void arch_release_hugepage(struct page *page) ptep = (pte_t *) page[1].index; if (!ptep) return; + clear_table((unsigned long *) ptep, _PAGE_TYPE_EMPTY, + PTRS_PER_PTE * sizeof(pte_t)); page_table_free(&init_mm, (unsigned long *) ptep); page[1].index = 0; } diff --git a/arch/s390/mm/maccess.c b/arch/s390/mm/maccess.c index 7bb15fcca75e..795a0a9bb2eb 100644 --- a/arch/s390/mm/maccess.c +++ b/arch/s390/mm/maccess.c @@ -12,6 +12,7 @@ #include <linux/types.h> #include <linux/errno.h> #include <linux/gfp.h> +#include <linux/cpu.h> #include <asm/ctl_reg.h> /* @@ -61,21 +62,14 @@ long probe_kernel_write(void *dst, const void *src, size_t size) return copied < 0 ? -EFAULT : 0; } -/* - * Copy memory in real mode (kernel to kernel) - */ -int memcpy_real(void *dest, void *src, size_t count) +static int __memcpy_real(void *dest, void *src, size_t count) { register unsigned long _dest asm("2") = (unsigned long) dest; register unsigned long _len1 asm("3") = (unsigned long) count; register unsigned long _src asm("4") = (unsigned long) src; register unsigned long _len2 asm("5") = (unsigned long) count; - unsigned long flags; int rc = -EFAULT; - if (!count) - return 0; - flags = __arch_local_irq_stnsm(0xf8UL); asm volatile ( "0: mvcle %1,%2,0x0\n" "1: jo 0b\n" @@ -86,7 +80,23 @@ int memcpy_real(void *dest, void *src, size_t count) "+d" (_len2), "=m" (*((long *) dest)) : "m" (*((long *) src)) : "cc", "memory"); - arch_local_irq_restore(flags); + return rc; +} + +/* + * Copy memory in real mode (kernel to kernel) + */ +int memcpy_real(void *dest, void *src, size_t count) +{ + unsigned long flags; + int rc; + + if (!count) + return 0; + local_irq_save(flags); + __arch_local_irq_stnsm(0xfbUL); + rc = __memcpy_real(dest, src, count); + local_irq_restore(flags); return rc; } @@ -157,3 +167,69 @@ out: free_page((unsigned long) buf); return rc; } + +/* + * Check if physical address is within prefix or zero page + */ +static int is_swapped(unsigned long addr) +{ + unsigned long lc; + int cpu; + + if (addr < sizeof(struct _lowcore)) + return 1; + for_each_online_cpu(cpu) { + lc = (unsigned long) lowcore_ptr[cpu]; + if (addr > lc + sizeof(struct _lowcore) - 1 || addr < lc) + continue; + return 1; + } + return 0; +} + +/* + * Return swapped prefix or zero page address + */ +static unsigned long get_swapped(unsigned long addr) +{ + unsigned long prefix = store_prefix(); + + if (addr < sizeof(struct _lowcore)) + return addr + prefix; + if (addr >= prefix && addr < prefix + sizeof(struct _lowcore)) + return addr - prefix; + return addr; +} + +/* + * Convert a physical pointer for /dev/mem access + * + * For swapped prefix pages a new buffer is returned that contains a copy of + * the absolute memory. The buffer size is maximum one page large. + */ +void *xlate_dev_mem_ptr(unsigned long addr) +{ + void *bounce = (void *) addr; + unsigned long size; + + get_online_cpus(); + preempt_disable(); + if (is_swapped(addr)) { + size = PAGE_SIZE - (addr & ~PAGE_MASK); + bounce = (void *) __get_free_page(GFP_ATOMIC); + if (bounce) + memcpy_real(bounce, (void *) get_swapped(addr), size); + } + preempt_enable(); + put_online_cpus(); + return bounce; +} + +/* + * Free converted buffer for /dev/mem access (if necessary) + */ +void unxlate_dev_mem_ptr(unsigned long addr, void *buf) +{ + if ((void *) addr != buf) + free_page((unsigned long) buf); +} diff --git a/arch/s390/mm/pgtable.c b/arch/s390/mm/pgtable.c index 373adf69b01c..a3db5a3ea083 100644 --- a/arch/s390/mm/pgtable.c +++ b/arch/s390/mm/pgtable.c @@ -678,8 +678,6 @@ void page_table_free(struct mm_struct *mm, unsigned long *table) } } -#ifdef CONFIG_HAVE_RCU_TABLE_FREE - static void __page_table_free_rcu(void *table, unsigned bit) { struct page *page; @@ -733,7 +731,66 @@ void __tlb_remove_table(void *_table) free_pages((unsigned long) table, ALLOC_ORDER); } -#endif +static void tlb_remove_table_smp_sync(void *arg) +{ + /* Simply deliver the interrupt */ +} + +static void tlb_remove_table_one(void *table) +{ + /* + * This isn't an RCU grace period and hence the page-tables cannot be + * assumed to be actually RCU-freed. + * + * It is however sufficient for software page-table walkers that rely + * on IRQ disabling. See the comment near struct mmu_table_batch. + */ + smp_call_function(tlb_remove_table_smp_sync, NULL, 1); + __tlb_remove_table(table); +} + +static void tlb_remove_table_rcu(struct rcu_head *head) +{ + struct mmu_table_batch *batch; + int i; + + batch = container_of(head, struct mmu_table_batch, rcu); + + for (i = 0; i < batch->nr; i++) + __tlb_remove_table(batch->tables[i]); + + free_page((unsigned long)batch); +} + +void tlb_table_flush(struct mmu_gather *tlb) +{ + struct mmu_table_batch **batch = &tlb->batch; + + if (*batch) { + __tlb_flush_mm(tlb->mm); + call_rcu_sched(&(*batch)->rcu, tlb_remove_table_rcu); + *batch = NULL; + } +} + +void tlb_remove_table(struct mmu_gather *tlb, void *table) +{ + struct mmu_table_batch **batch = &tlb->batch; + + if (*batch == NULL) { + *batch = (struct mmu_table_batch *) + __get_free_page(GFP_NOWAIT | __GFP_NOWARN); + if (*batch == NULL) { + __tlb_flush_mm(tlb->mm); + tlb_remove_table_one(table); + return; + } + (*batch)->nr = 0; + } + (*batch)->tables[(*batch)->nr++] = table; + if ((*batch)->nr == MAX_TABLE_BATCH) + tlb_table_flush(tlb); +} /* * switch on pgstes for its userspace process (for kvm) @@ -765,6 +822,8 @@ int s390_enable_sie(void) /* we copy the mm and let dup_mm create the page tables with_pgstes */ tsk->mm->context.alloc_pgste = 1; + /* make sure that both mms have a correct rss state */ + sync_mm_rss(tsk->mm); mm = dup_mm(tsk); tsk->mm->context.alloc_pgste = 0; if (!mm) diff --git a/arch/sh/include/asm/atomic.h b/arch/sh/include/asm/atomic.h index 37f2f4a55231..f4c1c20bcdf6 100644 --- a/arch/sh/include/asm/atomic.h +++ b/arch/sh/include/asm/atomic.h @@ -11,7 +11,7 @@ #include <linux/types.h> #include <asm/cmpxchg.h> -#define ATOMIC_INIT(i) ( (atomic_t) { (i) } ) +#define ATOMIC_INIT(i) { (i) } #define atomic_read(v) (*(volatile int *)&(v)->counter) #define atomic_set(v,i) ((v)->counter = (i)) diff --git a/arch/sh/mm/fault_32.c b/arch/sh/mm/fault_32.c index 324eef93c900..e99b104d967a 100644 --- a/arch/sh/mm/fault_32.c +++ b/arch/sh/mm/fault_32.c @@ -86,7 +86,7 @@ static noinline int vmalloc_fault(unsigned long address) pte_t *pte_k; /* Make sure we are in vmalloc/module/P3 area: */ - if (!(address >= VMALLOC_START && address < P3_ADDR_MAX)) + if (!(address >= P3SEG && address < P3_ADDR_MAX)) return -1; /* diff --git a/arch/sparc/Kbuild b/arch/sparc/Kbuild new file mode 100644 index 000000000000..5cd01161fd00 --- /dev/null +++ b/arch/sparc/Kbuild @@ -0,0 +1,8 @@ +# +# core part of the sparc kernel +# + +obj-y += kernel/ +obj-y += mm/ +obj-y += math-emu/ +obj-y += net/ diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig index 6c0683d3fcba..d176c03274c5 100644 --- a/arch/sparc/Kconfig +++ b/arch/sparc/Kconfig @@ -30,6 +30,7 @@ config SPARC select USE_GENERIC_SMP_HELPERS if SMP select GENERIC_PCI_IOMAP select HAVE_NMI_WATCHDOG if SPARC64 + select HAVE_BPF_JIT config SPARC32 def_bool !64BIT @@ -61,6 +62,7 @@ config SPARC64 select IRQ_PREFLOW_FASTEOI select ARCH_HAVE_NMI_SAFE_CMPXCHG select HAVE_C_RECORDMCOUNT + select NO_BOOTMEM config ARCH_DEFCONFIG string @@ -73,17 +75,12 @@ config BITS default 32 if SPARC32 default 64 if SPARC64 -config ARCH_USES_GETTIMEOFFSET - bool - default y if SPARC32 - config GENERIC_CMOS_UPDATE bool default y config GENERIC_CLOCKEVENTS - bool - default y if SPARC64 + def_bool y config IOMMU_HELPER bool @@ -154,7 +151,7 @@ source "kernel/Kconfig.freezer" menu "Processor type and features" config SMP - bool "Symmetric multi-processing support (does not work on sun4/sun4c)" + bool "Symmetric multi-processing support" ---help--- This enables support for systems with more than one CPU. If you have a system with only one CPU, say N. If you have a system with more diff --git a/arch/sparc/Makefile b/arch/sparc/Makefile index eddcfb36aafb..b9a72e2b8acc 100644 --- a/arch/sparc/Makefile +++ b/arch/sparc/Makefile @@ -19,39 +19,27 @@ ifeq ($(CONFIG_SPARC32),y) # sparc32 # -# -# Uncomment the first KBUILD_CFLAGS if you are doing kgdb source level -# debugging of the kernel to get the proper debugging information. - -AS := $(AS) -32 -LDFLAGS := -m elf32_sparc CHECKFLAGS += -D__sparc__ +LDFLAGS := -m elf32_sparc export BITS := 32 UTS_MACHINE := sparc -#KBUILD_CFLAGS += -g -pipe -fcall-used-g5 -fcall-used-g7 -KBUILD_CFLAGS += -m32 -pipe -mno-fpu -fcall-used-g5 -fcall-used-g7 -KBUILD_AFLAGS += -m32 -Wa,-Av8 - -#LDFLAGS_vmlinux = -N -Ttext 0xf0004000 -# Since 2.5.40, the first stage is left not btfix-ed. -# Actual linking is done with "make image". -LDFLAGS_vmlinux = -r +KBUILD_CFLAGS += -m32 -mcpu=v8 -pipe -mno-fpu -fcall-used-g5 -fcall-used-g7 +KBUILD_AFLAGS += -m32 -Wa,-Av8 else ##### # sparc64 # -CHECKFLAGS += -D__sparc__ -D__sparc_v9__ -D__arch64__ -m64 +CHECKFLAGS += -D__sparc__ -D__sparc_v9__ -D__arch64__ -m64 +LDFLAGS := -m elf64_sparc +export BITS := 64 +UTS_MACHINE := sparc64 -LDFLAGS := -m elf64_sparc -export BITS := 64 -UTS_MACHINE := sparc64 - -KBUILD_CFLAGS += -m64 -pipe -mno-fpu -mcpu=ultrasparc -mcmodel=medlow \ - -ffixed-g4 -ffixed-g5 -fcall-used-g7 -Wno-sign-compare \ - -Wa,--undeclared-regs +KBUILD_CFLAGS += -m64 -pipe -mno-fpu -mcpu=ultrasparc -mcmodel=medlow +KBUILD_CFLAGS += -ffixed-g4 -ffixed-g5 -fcall-used-g7 -Wno-sign-compare +KBUILD_CFLAGS += -Wa,--undeclared-regs KBUILD_CFLAGS += $(call cc-option,-mtune=ultrasparc3) KBUILD_AFLAGS += -m64 -mcpu=ultrasparc -Wa,--undeclared-regs @@ -64,25 +52,14 @@ endif head-y := arch/sparc/kernel/head_$(BITS).o head-y += arch/sparc/kernel/init_task.o -core-y += arch/sparc/kernel/ -core-y += arch/sparc/mm/ arch/sparc/math-emu/ +# See arch/sparc/Kbuild for the core part of the kernel +core-y += arch/sparc/ libs-y += arch/sparc/prom/ libs-y += arch/sparc/lib/ drivers-$(CONFIG_OPROFILE) += arch/sparc/oprofile/ -# Export what is needed by arch/sparc/boot/Makefile -export VMLINUX_INIT VMLINUX_MAIN -VMLINUX_INIT := $(head-y) $(init-y) -VMLINUX_MAIN := $(core-y) kernel/ mm/ fs/ ipc/ security/ crypto/ block/ -VMLINUX_MAIN += $(patsubst %/, %/lib.a, $(libs-y)) $(libs-y) -VMLINUX_MAIN += $(drivers-y) $(net-y) - -ifdef CONFIG_KALLSYMS -export kallsyms.o := .tmp_kallsyms2.o -endif - boot := arch/sparc/boot # Default target diff --git a/arch/sparc/boot/Makefile b/arch/sparc/boot/Makefile index d56d199c1aa8..6e63afb128d9 100644 --- a/arch/sparc/boot/Makefile +++ b/arch/sparc/boot/Makefile @@ -6,8 +6,8 @@ ROOT_IMG := /usr/src/root.img ELFTOAOUT := elftoaout -hostprogs-y := piggyback btfixupprep -targets := tftpboot.img btfix.o btfix.S image zImage vmlinux.aout +hostprogs-y := piggyback +targets := tftpboot.img image zImage vmlinux.aout clean-files := System.map quiet_cmd_elftoaout = ELFTOAOUT $@ @@ -17,58 +17,9 @@ quiet_cmd_piggy = PIGGY $@ quiet_cmd_strip = STRIP $@ cmd_strip = $(STRIP) -R .comment -R .note -K sun4u_init -K _end -K _start $< -o $@ -ifeq ($(CONFIG_SPARC32),y) -quiet_cmd_btfix = BTFIX $@ - cmd_btfix = $(OBJDUMP) -x vmlinux | $(obj)/btfixupprep > $@ -quiet_cmd_sysmap = SYSMAP $(obj)/System.map - cmd_sysmap = $(CONFIG_SHELL) $(srctree)/scripts/mksysmap -quiet_cmd_image = LD $@ - cmd_image = $(LD) $(LDFLAGS) $(EXTRA_LDFLAGS) $(LDFLAGS_$(@F)) -o $@ - -define rule_image - $(if $($(quiet)cmd_image), \ - echo ' $($(quiet)cmd_image)' &&) \ - $(cmd_image); \ - $(if $($(quiet)cmd_sysmap), \ - echo ' $($(quiet)cmd_sysmap)' &&) \ - $(cmd_sysmap) $@ $(obj)/System.map; \ - if [ $$? -ne 0 ]; then \ - rm -f $@; \ - /bin/false; \ - fi; \ - echo 'cmd_$@ := $(cmd_image)' > $(@D)/.$(@F).cmd -endef - -BTOBJS := $(patsubst %/, %/built-in.o, $(VMLINUX_INIT)) -BTLIBS := $(patsubst %/, %/built-in.o, $(VMLINUX_MAIN)) -LDFLAGS_image := -T arch/sparc/kernel/vmlinux.lds $(BTOBJS) \ - --start-group $(BTLIBS) --end-group \ - $(kallsyms.o) $(obj)/btfix.o - -# Link the final image including btfixup'ed symbols. -# This is a replacement for the link done in the top-level Makefile. -# Note: No dependency on the prerequisite files since that would require -# make to try check if they are updated - and due to changes -# in gcc options (path for example) this would result in -# these files being recompiled for each build. -$(obj)/image: $(obj)/btfix.o FORCE - $(call if_changed_rule,image) - -$(obj)/zImage: $(obj)/image - $(call if_changed,strip) - @echo ' kernel: $@ is ready' - -$(obj)/btfix.S: $(obj)/btfixupprep vmlinux FORCE - $(call if_changed,btfix) - -endif - ifeq ($(CONFIG_SPARC64),y) # Actual linking -$(obj)/image: vmlinux FORCE - $(call if_changed,strip) - @echo ' kernel: $@ is ready' $(obj)/zImage: $(obj)/image $(call if_changed,gzip) @@ -79,6 +30,10 @@ $(obj)/vmlinux.aout: vmlinux FORCE @echo ' kernel: $@ is ready' else +$(obj)/zImage: $(obj)/image + $(call if_changed,strip) + @echo ' kernel: $@ is ready' + # The following lines make a readable image for U-Boot. # uImage - Binary file read by U-boot # uImage.o - object file of uImage for loading with a @@ -107,6 +62,10 @@ $(obj)/uImage: $(obj)/image.gz endif +$(obj)/image: vmlinux FORCE + $(call if_changed,strip) + @echo ' kernel: $@ is ready' + $(obj)/tftpboot.img: $(obj)/image $(obj)/piggyback System.map $(ROOT_IMG) FORCE $(call if_changed,elftoaout) $(call if_changed,piggy) diff --git a/arch/sparc/boot/btfixupprep.c b/arch/sparc/boot/btfixupprep.c deleted file mode 100644 index da031159e2b7..000000000000 --- a/arch/sparc/boot/btfixupprep.c +++ /dev/null @@ -1,386 +0,0 @@ -/* - Simple utility to prepare vmlinux image for sparc. - Resolves all BTFIXUP uses and settings and creates - a special .s object to link to the image. - - Copyright (C) 1998 Jakub Jelinek ([email protected]) - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ - -#include <stdio.h> -#include <string.h> -#include <ctype.h> -#include <errno.h> -#include <unistd.h> -#include <stdlib.h> -#include <malloc.h> - -#define MAXSYMS 1024 - -static char *symtab = "SYMBOL TABLE:"; -static char *relrec = "RELOCATION RECORDS FOR ["; -static int rellen; -static int symlen; -int mode; - -struct _btfixup; - -typedef struct _btfixuprel { - char *sect; - unsigned long offset; - struct _btfixup *f; - int frel; - struct _btfixuprel *next; -} btfixuprel; - -typedef struct _btfixup { - int type; - int setinitval; - unsigned int initval; - char *initvalstr; - char *name; - btfixuprel *rel; -} btfixup; - -btfixup array[MAXSYMS]; -int last = 0; -char buffer[1024]; -unsigned long lastfoffset = -1; -unsigned long lastfrelno; -btfixup *lastf; - -static void fatal(void) __attribute__((noreturn)); -static void fatal(void) -{ - fprintf(stderr, "Malformed output from objdump\n%s\n", buffer); - exit(1); -} - -static btfixup *find(int type, char *name) -{ - int i; - for (i = 0; i < last; i++) { - if (array[i].type == type && !strcmp(array[i].name, name)) - return array + i; - } - array[last].type = type; - array[last].name = strdup(name); - array[last].setinitval = 0; - if (!array[last].name) fatal(); - array[last].rel = NULL; - last++; - if (last >= MAXSYMS) { - fprintf(stderr, "Ugh. Something strange. More than %d different BTFIXUP symbols\n", MAXSYMS); - exit(1); - } - return array + last - 1; -} - -static void set_mode (char *buffer) -{ - for (mode = 0;; mode++) - if (buffer[mode] < '0' || buffer[mode] > '9') - break; - if (mode != 8 && mode != 16) - fatal(); -} - - -int main(int argc,char **argv) -{ - char *p, *q; - char *sect; - int i, j, k; - unsigned int initval; - int shift; - btfixup *f; - btfixuprel *r, **rr; - unsigned long offset; - char *initvalstr; - - symlen = strlen(symtab); - while (fgets (buffer, 1024, stdin) != NULL) - if (!strncmp (buffer, symtab, symlen)) - goto main0; - fatal(); -main0: - rellen = strlen(relrec); - while (fgets (buffer, 1024, stdin) != NULL) - if (!strncmp (buffer, relrec, rellen)) - goto main1; - fatal(); -main1: - sect = malloc(strlen (buffer + rellen) + 1); - if (!sect) fatal(); - strcpy (sect, buffer + rellen); - p = strchr (sect, ']'); - if (!p) fatal(); - *p = 0; - if (fgets (buffer, 1024, stdin) == NULL) - fatal(); - while (fgets (buffer, 1024, stdin) != NULL) { - int nbase; - if (!strncmp (buffer, relrec, rellen)) - goto main1; - if (mode == 0) - set_mode (buffer); - p = strchr (buffer, '\n'); - if (p) *p = 0; - if (strlen (buffer) < 22+mode) - continue; - if (strncmp (buffer + mode, " R_SPARC_", 9)) - continue; - nbase = 27 - 8 + mode; - if (buffer[nbase] != '_' || buffer[nbase+1] != '_' || buffer[nbase+2] != '_') - continue; - switch (buffer[nbase+3]) { - case 'f': /* CALL */ - case 'b': /* BLACKBOX */ - case 's': /* SIMM13 */ - case 'a': /* HALF */ - case 'h': /* SETHI */ - case 'i': /* INT */ - break; - default: - continue; - } - p = strchr (buffer + nbase+5, '+'); - if (p) *p = 0; - shift = nbase + 5; - if (buffer[nbase+4] == 's' && buffer[nbase+5] == '_') { - shift = nbase + 6; - if (strcmp (sect, ".init.text")) { - fprintf(stderr, - "Wrong use of '%s' BTFIXUPSET in '%s' section.\n" - "BTFIXUPSET_CALL can be used only in" - " __init sections\n", - buffer + shift, sect); - exit(1); - } - } else if (buffer[nbase+4] != '_') - continue; - if (!strcmp (sect, ".text.exit")) - continue; - if (strcmp (sect, ".text") && - strcmp (sect, ".init.text") && - strcmp (sect, ".fixup") && - (strcmp (sect, "__ksymtab") || buffer[nbase+3] != 'f')) { - if (buffer[nbase+3] == 'f') - fprintf(stderr, - "Wrong use of '%s' in '%s' section.\n" - " It can be used only in .text, .init.text," - " .fixup and __ksymtab\n", - buffer + shift, sect); - else - fprintf(stderr, - "Wrong use of '%s' in '%s' section.\n" - " It can be only used in .text, .init.text," - " and .fixup\n", buffer + shift, sect); - exit(1); - } - p = strstr (buffer + shift, "__btset_"); - if (p && buffer[nbase+4] == 's') { - fprintf(stderr, "__btset_ in BTFIXUP name can only be used when defining the variable, not for setting\n%s\n", buffer); - exit(1); - } - initval = 0; - initvalstr = NULL; - if (p) { - if (p[8] != '0' || p[9] != 'x') { - fprintf(stderr, "Pre-initialized values can be only initialized with hexadecimal constants starting 0x\n%s\n", buffer); - exit(1); - } - initval = strtoul(p + 10, &q, 16); - if (*q || !initval) { - fprintf(stderr, "Pre-initialized values can be only in the form name__btset_0xXXXXXXXX where X are hex digits.\nThey cannot be name__btset_0x00000000 though. Use BTFIXUPDEF_XX instead of BTFIXUPDEF_XX_INIT then.\n%s\n", buffer); - exit(1); - } - initvalstr = p + 10; - *p = 0; - } - f = find(buffer[nbase+3], buffer + shift); - if (buffer[nbase+4] == 's') - continue; - switch (buffer[nbase+3]) { - case 'f': - if (initval) { - fprintf(stderr, "Cannot use pre-initialized fixups for calls\n%s\n", buffer); - exit(1); - } - if (!strcmp (sect, "__ksymtab")) { - if (strncmp (buffer + mode+9, "32 ", 10)) { - fprintf(stderr, "BTFIXUP_CALL in EXPORT_SYMBOL results in relocation other than R_SPARC_32\n\%s\n", buffer); - exit(1); - } - } else if (strncmp (buffer + mode+9, "WDISP30 ", 10) && - strncmp (buffer + mode+9, "HI22 ", 10) && - strncmp (buffer + mode+9, "LO10 ", 10)) { - fprintf(stderr, "BTFIXUP_CALL results in relocation other than R_SPARC_WDISP30, R_SPARC_HI22 or R_SPARC_LO10\n%s\n", buffer); - exit(1); - } - break; - case 'b': - if (initval) { - fprintf(stderr, "Cannot use pre-initialized fixups for blackboxes\n%s\n", buffer); - exit(1); - } - if (strncmp (buffer + mode+9, "HI22 ", 10)) { - fprintf(stderr, "BTFIXUP_BLACKBOX results in relocation other than R_SPARC_HI22\n%s\n", buffer); - exit(1); - } - break; - case 's': - if (initval + 0x1000 >= 0x2000) { - fprintf(stderr, "Wrong initializer for SIMM13. Has to be from $fffff000 to $00000fff\n%s\n", buffer); - exit(1); - } - if (strncmp (buffer + mode+9, "13 ", 10)) { - fprintf(stderr, "BTFIXUP_SIMM13 results in relocation other than R_SPARC_13\n%s\n", buffer); - exit(1); - } - break; - case 'a': - if (initval + 0x1000 >= 0x2000 && (initval & 0x3ff)) { - fprintf(stderr, "Wrong initializer for HALF.\n%s\n", buffer); - exit(1); - } - if (strncmp (buffer + mode+9, "13 ", 10)) { - fprintf(stderr, "BTFIXUP_HALF results in relocation other than R_SPARC_13\n%s\n", buffer); - exit(1); - } - break; - case 'h': - if (initval & 0x3ff) { - fprintf(stderr, "Wrong initializer for SETHI. Cannot have set low 10 bits\n%s\n", buffer); - exit(1); - } - if (strncmp (buffer + mode+9, "HI22 ", 10)) { - fprintf(stderr, "BTFIXUP_SETHI results in relocation other than R_SPARC_HI22\n%s\n", buffer); - exit(1); - } - break; - case 'i': - if (initval) { - fprintf(stderr, "Cannot use pre-initialized fixups for INT\n%s\n", buffer); - exit(1); - } - if (strncmp (buffer + mode+9, "HI22 ", 10) && strncmp (buffer + mode+9, "LO10 ", 10)) { - fprintf(stderr, "BTFIXUP_INT results in relocation other than R_SPARC_HI22 and R_SPARC_LO10\n%s\n", buffer); - exit(1); - } - break; - } - if (!f->setinitval) { - f->initval = initval; - if (initvalstr) { - f->initvalstr = strdup(initvalstr); - if (!f->initvalstr) fatal(); - } - f->setinitval = 1; - } else if (f->initval != initval) { - fprintf(stderr, "Btfixup %s previously used with initializer %s which doesn't match with current initializer\n%s\n", - f->name, f->initvalstr ? : "0x00000000", buffer); - exit(1); - } else if (initval && strcmp(f->initvalstr, initvalstr)) { - fprintf(stderr, "Btfixup %s previously used with initializer %s which doesn't match with current initializer.\n" - "Initializers have to match literally as well.\n%s\n", - f->name, f->initvalstr, buffer); - exit(1); - } - offset = strtoul(buffer, &q, 16); - if (q != buffer + mode || (!offset && (mode == 8 ? strncmp (buffer, "00000000 ", 9) : strncmp (buffer, "0000000000000000 ", 17)))) { - fprintf(stderr, "Malformed relocation address in\n%s\n", buffer); - exit(1); - } - for (k = 0, r = f->rel, rr = &f->rel; r; rr = &r->next, r = r->next, k++) - if (r->offset == offset && !strcmp(r->sect, sect)) { - fprintf(stderr, "Ugh. One address has two relocation records\n"); - exit(1); - } - *rr = malloc(sizeof(btfixuprel)); - if (!*rr) fatal(); - (*rr)->offset = offset; - (*rr)->f = NULL; - if (buffer[nbase+3] == 'f') { - lastf = f; - lastfoffset = offset; - lastfrelno = k; - } else if (lastfoffset + 4 == offset) { - (*rr)->f = lastf; - (*rr)->frel = lastfrelno; - } - (*rr)->sect = sect; - (*rr)->next = NULL; - } - printf("! Generated by btfixupprep. Do not edit.\n\n"); - printf("\t.section\t\".data..init\",#alloc,#write\n\t.align\t4\n\n"); - printf("\t.global\t___btfixup_start\n___btfixup_start:\n\n"); - for (i = 0; i < last; i++) { - f = array + i; - printf("\t.global\t___%cs_%s\n", f->type, f->name); - if (f->type == 'f') - printf("___%cs_%s:\n\t.word 0x%08x,0,0,", f->type, f->name, f->type << 24); - else - printf("___%cs_%s:\n\t.word 0x%08x,0,", f->type, f->name, f->type << 24); - for (j = 0, r = f->rel; r != NULL; j++, r = r->next); - if (j) - printf("%d\n\t.word\t", j * 2); - else - printf("0\n"); - for (r = f->rel, j--; r != NULL; j--, r = r->next) { - if (!strcmp (r->sect, ".text")) - printf ("_stext+0x%08lx", r->offset); - else if (!strcmp (r->sect, ".init.text")) - printf ("__init_begin+0x%08lx", r->offset); - else if (!strcmp (r->sect, "__ksymtab")) - printf ("__start___ksymtab+0x%08lx", r->offset); - else if (!strcmp (r->sect, ".fixup")) - printf ("__start___fixup+0x%08lx", r->offset); - else - fatal(); - if (f->type == 'f' || !r->f) - printf (",0"); - else - printf (",___fs_%s+0x%08x", r->f->name, (4 + r->frel*2)*4 + 4); - if (j) printf (","); - else printf ("\n"); - } - printf("\n"); - } - printf("\n\t.global\t___btfixup_end\n___btfixup_end:\n"); - printf("\n\n! Define undefined references\n\n"); - for (i = 0; i < last; i++) { - f = array + i; - if (f->type == 'f') { - printf("\t.global\t___f_%s\n", f->name); - printf("___f_%s:\n", f->name); - } - } - printf("\tretl\n\t nop\n\n"); - for (i = 0; i < last; i++) { - f = array + i; - if (f->type != 'f') { - if (!f->initval) { - printf("\t.global\t___%c_%s\n", f->type, f->name); - printf("___%c_%s = 0\n", f->type, f->name); - } else { - printf("\t.global\t___%c_%s__btset_0x%s\n", f->type, f->name, f->initvalstr); - printf("___%c_%s__btset_0x%s = 0x%08x\n", f->type, f->name, f->initvalstr, f->initval); - } - } - } - printf("\n\n"); - exit(0); -} diff --git a/arch/sparc/include/asm/asi.h b/arch/sparc/include/asm/asi.h index b2e3db63a64b..cbb93e5141de 100644 --- a/arch/sparc/include/asm/asi.h +++ b/arch/sparc/include/asm/asi.h @@ -112,6 +112,20 @@ #define ASI_M_ACTION 0x4c /* Breakpoint Action Register (GNU/Viking) */ +/* LEON ASI */ +#define ASI_LEON_NOCACHE 0x01 + +#define ASI_LEON_DCACHE_MISS 0x01 + +#define ASI_LEON_CACHEREGS 0x02 +#define ASI_LEON_IFLUSH 0x10 +#define ASI_LEON_DFLUSH 0x11 + +#define ASI_LEON_MMUFLUSH 0x18 +#define ASI_LEON_MMUREGS 0x19 +#define ASI_LEON_BYPASS 0x1c +#define ASI_LEON_FLUSH_PAGE 0x10 + /* V9 Architecture mandary ASIs. */ #define ASI_N 0x04 /* Nucleus */ #define ASI_NL 0x0c /* Nucleus, little endian */ diff --git a/arch/sparc/include/asm/asmmacro.h b/arch/sparc/include/asm/asmmacro.h index a995bf8aba3f..02a172fb193a 100644 --- a/arch/sparc/include/asm/asmmacro.h +++ b/arch/sparc/include/asm/asmmacro.h @@ -6,17 +6,6 @@ #ifndef _SPARC_ASMMACRO_H #define _SPARC_ASMMACRO_H -#include <asm/btfixup.h> -#include <asm/asi.h> - -#define GET_PROCESSOR4M_ID(reg) \ - rd %tbr, %reg; \ - srl %reg, 12, %reg; \ - and %reg, 3, %reg; - -#define GET_PROCESSOR4D_ID(reg) \ - lda [%g0] ASI_M_VIKING_TMP1, %reg; - /* All trap entry points _must_ begin with this macro or else you * lose. It makes sure the kernel has a proper window so that * c-code can be called. @@ -31,10 +20,4 @@ /* All traps low-level code here must end with this macro. */ #define RESTORE_ALL b ret_trap_entry; clr %l6; -/* sun4 probably wants half word accesses to ASI_SEGMAP, while sun4c+ - likes byte accesses. These are to avoid ifdef mania. */ - -#define lduXa lduba -#define stXa stba - #endif /* !(_SPARC_ASMMACRO_H) */ diff --git a/arch/sparc/include/asm/btfixup.h b/arch/sparc/include/asm/btfixup.h deleted file mode 100644 index 797722cf69f2..000000000000 --- a/arch/sparc/include/asm/btfixup.h +++ /dev/null @@ -1,208 +0,0 @@ -/* - * asm/btfixup.h: Macros for boot time linking. - * - * Copyright (C) 1998 Jakub Jelinek ([email protected]) - */ - -#ifndef _SPARC_BTFIXUP_H -#define _SPARC_BTFIXUP_H - -#include <linux/init.h> - -#ifndef __ASSEMBLY__ - -#ifdef MODULE -extern unsigned int ___illegal_use_of_BTFIXUP_SIMM13_in_module(void); -extern unsigned int ___illegal_use_of_BTFIXUP_SETHI_in_module(void); -extern unsigned int ___illegal_use_of_BTFIXUP_HALF_in_module(void); -extern unsigned int ___illegal_use_of_BTFIXUP_INT_in_module(void); - -#define BTFIXUP_SIMM13(__name) ___illegal_use_of_BTFIXUP_SIMM13_in_module() -#define BTFIXUP_HALF(__name) ___illegal_use_of_BTFIXUP_HALF_in_module() -#define BTFIXUP_SETHI(__name) ___illegal_use_of_BTFIXUP_SETHI_in_module() -#define BTFIXUP_INT(__name) ___illegal_use_of_BTFIXUP_INT_in_module() -#define BTFIXUP_BLACKBOX(__name) ___illegal_use_of_BTFIXUP_BLACKBOX_in_module - -#else - -#define BTFIXUP_SIMM13(__name) ___sf_##__name() -#define BTFIXUP_HALF(__name) ___af_##__name() -#define BTFIXUP_SETHI(__name) ___hf_##__name() -#define BTFIXUP_INT(__name) ((unsigned int)&___i_##__name) -/* This must be written in assembly and present in a sethi */ -#define BTFIXUP_BLACKBOX(__name) ___b_##__name -#endif /* MODULE */ - -/* Fixup call xx */ - -#define BTFIXUPDEF_CALL(__type, __name, __args...) \ - extern __type ___f_##__name(__args); \ - extern unsigned ___fs_##__name[3]; -#define BTFIXUPDEF_CALL_CONST(__type, __name, __args...) \ - extern __type ___f_##__name(__args) __attribute_const__; \ - extern unsigned ___fs_##__name[3]; -#define BTFIXUP_CALL(__name) ___f_##__name - -#define BTFIXUPDEF_BLACKBOX(__name) \ - extern unsigned ___bs_##__name[2]; - -/* Put bottom 13bits into some register variable */ - -#define BTFIXUPDEF_SIMM13(__name) \ - static inline unsigned int ___sf_##__name(void) __attribute_const__; \ - extern unsigned ___ss_##__name[2]; \ - static inline unsigned int ___sf_##__name(void) { \ - unsigned int ret; \ - __asm__ ("or %%g0, ___s_" #__name ", %0" : "=r"(ret)); \ - return ret; \ - } -#define BTFIXUPDEF_SIMM13_INIT(__name,__val) \ - static inline unsigned int ___sf_##__name(void) __attribute_const__; \ - extern unsigned ___ss_##__name[2]; \ - static inline unsigned int ___sf_##__name(void) { \ - unsigned int ret; \ - __asm__ ("or %%g0, ___s_" #__name "__btset_" #__val ", %0" : "=r"(ret));\ - return ret; \ - } - -/* Put either bottom 13 bits, or upper 22 bits into some register variable - * (depending on the value, this will lead into sethi FIX, reg; or - * mov FIX, reg; ) - */ - -#define BTFIXUPDEF_HALF(__name) \ - static inline unsigned int ___af_##__name(void) __attribute_const__; \ - extern unsigned ___as_##__name[2]; \ - static inline unsigned int ___af_##__name(void) { \ - unsigned int ret; \ - __asm__ ("or %%g0, ___a_" #__name ", %0" : "=r"(ret)); \ - return ret; \ - } -#define BTFIXUPDEF_HALF_INIT(__name,__val) \ - static inline unsigned int ___af_##__name(void) __attribute_const__; \ - extern unsigned ___as_##__name[2]; \ - static inline unsigned int ___af_##__name(void) { \ - unsigned int ret; \ - __asm__ ("or %%g0, ___a_" #__name "__btset_" #__val ", %0" : "=r"(ret));\ - return ret; \ - } - -/* Put upper 22 bits into some register variable */ - -#define BTFIXUPDEF_SETHI(__name) \ - static inline unsigned int ___hf_##__name(void) __attribute_const__; \ - extern unsigned ___hs_##__name[2]; \ - static inline unsigned int ___hf_##__name(void) { \ - unsigned int ret; \ - __asm__ ("sethi %%hi(___h_" #__name "), %0" : "=r"(ret)); \ - return ret; \ - } -#define BTFIXUPDEF_SETHI_INIT(__name,__val) \ - static inline unsigned int ___hf_##__name(void) __attribute_const__; \ - extern unsigned ___hs_##__name[2]; \ - static inline unsigned int ___hf_##__name(void) { \ - unsigned int ret; \ - __asm__ ("sethi %%hi(___h_" #__name "__btset_" #__val "), %0" : \ - "=r"(ret)); \ - return ret; \ - } - -/* Put a full 32bit integer into some register variable */ - -#define BTFIXUPDEF_INT(__name) \ - extern unsigned char ___i_##__name; \ - extern unsigned ___is_##__name[2]; - -#define BTFIXUPCALL_NORM 0x00000000 /* Always call */ -#define BTFIXUPCALL_NOP 0x01000000 /* Possibly optimize to nop */ -#define BTFIXUPCALL_RETINT(i) (0x90102000|((i) & 0x1fff)) /* Possibly optimize to mov i, %o0 */ -#define BTFIXUPCALL_ORINT(i) (0x90122000|((i) & 0x1fff)) /* Possibly optimize to or %o0, i, %o0 */ -#define BTFIXUPCALL_RETO0 0x01000000 /* Return first parameter, actually a nop */ -#define BTFIXUPCALL_ANDNINT(i) (0x902a2000|((i) & 0x1fff)) /* Possibly optimize to andn %o0, i, %o0 */ -#define BTFIXUPCALL_SWAPO0O1 0xd27a0000 /* Possibly optimize to swap [%o0],%o1 */ -#define BTFIXUPCALL_SWAPO0G0 0xc07a0000 /* Possibly optimize to swap [%o0],%g0 */ -#define BTFIXUPCALL_SWAPG1G2 0xc4784000 /* Possibly optimize to swap [%g1],%g2 */ -#define BTFIXUPCALL_STG0O0 0xc0220000 /* Possibly optimize to st %g0,[%o0] */ -#define BTFIXUPCALL_STO1O0 0xd2220000 /* Possibly optimize to st %o1,[%o0] */ - -#define BTFIXUPSET_CALL(__name, __addr, __insn) \ - do { \ - ___fs_##__name[0] |= 1; \ - ___fs_##__name[1] = (unsigned long)__addr; \ - ___fs_##__name[2] = __insn; \ - } while (0) - -#define BTFIXUPSET_BLACKBOX(__name, __func) \ - do { \ - ___bs_##__name[0] |= 1; \ - ___bs_##__name[1] = (unsigned long)__func; \ - } while (0) - -#define BTFIXUPCOPY_CALL(__name, __from) \ - do { \ - ___fs_##__name[0] |= 1; \ - ___fs_##__name[1] = ___fs_##__from[1]; \ - ___fs_##__name[2] = ___fs_##__from[2]; \ - } while (0) - -#define BTFIXUPSET_SIMM13(__name, __val) \ - do { \ - ___ss_##__name[0] |= 1; \ - ___ss_##__name[1] = (unsigned)__val; \ - } while (0) - -#define BTFIXUPCOPY_SIMM13(__name, __from) \ - do { \ - ___ss_##__name[0] |= 1; \ - ___ss_##__name[1] = ___ss_##__from[1]; \ - } while (0) - -#define BTFIXUPSET_HALF(__name, __val) \ - do { \ - ___as_##__name[0] |= 1; \ - ___as_##__name[1] = (unsigned)__val; \ - } while (0) - -#define BTFIXUPCOPY_HALF(__name, __from) \ - do { \ - ___as_##__name[0] |= 1; \ - ___as_##__name[1] = ___as_##__from[1]; \ - } while (0) - -#define BTFIXUPSET_SETHI(__name, __val) \ - do { \ - ___hs_##__name[0] |= 1; \ - ___hs_##__name[1] = (unsigned)__val; \ - } while (0) - -#define BTFIXUPCOPY_SETHI(__name, __from) \ - do { \ - ___hs_##__name[0] |= 1; \ - ___hs_##__name[1] = ___hs_##__from[1]; \ - } while (0) - -#define BTFIXUPSET_INT(__name, __val) \ - do { \ - ___is_##__name[0] |= 1; \ - ___is_##__name[1] = (unsigned)__val; \ - } while (0) - -#define BTFIXUPCOPY_INT(__name, __from) \ - do { \ - ___is_##__name[0] |= 1; \ - ___is_##__name[1] = ___is_##__from[1]; \ - } while (0) - -#define BTFIXUPVAL_CALL(__name) \ - ((unsigned long)___fs_##__name[1]) - -extern void btfixup(void); - -#else /* __ASSEMBLY__ */ - -#define BTFIXUP_SETHI(__name) %hi(___h_ ## __name) -#define BTFIXUP_SETHI_INIT(__name,__val) %hi(___h_ ## __name ## __btset_ ## __val) - -#endif /* __ASSEMBLY__ */ - -#endif /* !(_SPARC_BTFIXUP_H) */ diff --git a/arch/sparc/include/asm/cache.h b/arch/sparc/include/asm/cache.h index 69358b590c91..5bb6991b4857 100644 --- a/arch/sparc/include/asm/cache.h +++ b/arch/sparc/include/asm/cache.h @@ -22,118 +22,4 @@ #define __read_mostly __attribute__((__section__(".data..read_mostly"))) -#ifdef CONFIG_SPARC32 -#include <asm/asi.h> - -/* Direct access to the instruction cache is provided through and - * alternate address space. The IDC bit must be off in the ICCR on - * HyperSparcs for these accesses to work. The code below does not do - * any checking, the caller must do so. These routines are for - * diagnostics only, but could end up being useful. Use with care. - * Also, you are asking for trouble if you execute these in one of the - * three instructions following a %asr/%psr access or modification. - */ - -/* First, cache-tag access. */ -static inline unsigned int get_icache_tag(int setnum, int tagnum) -{ - unsigned int vaddr, retval; - - vaddr = ((setnum&1) << 12) | ((tagnum&0x7f) << 5); - __asm__ __volatile__("lda [%1] %2, %0\n\t" : - "=r" (retval) : - "r" (vaddr), "i" (ASI_M_TXTC_TAG)); - return retval; -} - -static inline void put_icache_tag(int setnum, int tagnum, unsigned int entry) -{ - unsigned int vaddr; - - vaddr = ((setnum&1) << 12) | ((tagnum&0x7f) << 5); - __asm__ __volatile__("sta %0, [%1] %2\n\t" : : - "r" (entry), "r" (vaddr), "i" (ASI_M_TXTC_TAG) : - "memory"); -} - -/* Second cache-data access. The data is returned two-32bit quantities - * at a time. - */ -static inline void get_icache_data(int setnum, int tagnum, int subblock, - unsigned int *data) -{ - unsigned int value1, value2, vaddr; - - vaddr = ((setnum&0x1) << 12) | ((tagnum&0x7f) << 5) | - ((subblock&0x3) << 3); - __asm__ __volatile__("ldda [%2] %3, %%g2\n\t" - "or %%g0, %%g2, %0\n\t" - "or %%g0, %%g3, %1\n\t" : - "=r" (value1), "=r" (value2) : - "r" (vaddr), "i" (ASI_M_TXTC_DATA) : - "g2", "g3"); - data[0] = value1; data[1] = value2; -} - -static inline void put_icache_data(int setnum, int tagnum, int subblock, - unsigned int *data) -{ - unsigned int value1, value2, vaddr; - - vaddr = ((setnum&0x1) << 12) | ((tagnum&0x7f) << 5) | - ((subblock&0x3) << 3); - value1 = data[0]; value2 = data[1]; - __asm__ __volatile__("or %%g0, %0, %%g2\n\t" - "or %%g0, %1, %%g3\n\t" - "stda %%g2, [%2] %3\n\t" : : - "r" (value1), "r" (value2), - "r" (vaddr), "i" (ASI_M_TXTC_DATA) : - "g2", "g3", "memory" /* no joke */); -} - -/* Different types of flushes with the ICACHE. Some of the flushes - * affect both the ICACHE and the external cache. Others only clear - * the ICACHE entries on the cpu itself. V8's (most) allow - * granularity of flushes on the packet (element in line), whole line, - * and entire cache (ie. all lines) level. The ICACHE only flushes are - * ROSS HyperSparc specific and are in ross.h - */ - -/* Flushes which clear out both the on-chip and external caches */ -static inline void flush_ei_page(unsigned int addr) -{ - __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : : - "r" (addr), "i" (ASI_M_FLUSH_PAGE) : - "memory"); -} - -static inline void flush_ei_seg(unsigned int addr) -{ - __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : : - "r" (addr), "i" (ASI_M_FLUSH_SEG) : - "memory"); -} - -static inline void flush_ei_region(unsigned int addr) -{ - __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : : - "r" (addr), "i" (ASI_M_FLUSH_REGION) : - "memory"); -} - -static inline void flush_ei_ctx(unsigned int addr) -{ - __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : : - "r" (addr), "i" (ASI_M_FLUSH_CTX) : - "memory"); -} - -static inline void flush_ei_user(unsigned int addr) -{ - __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : : - "r" (addr), "i" (ASI_M_FLUSH_USER) : - "memory"); -} -#endif /* CONFIG_SPARC32 */ - #endif /* !(_SPARC_CACHE_H) */ diff --git a/arch/sparc/include/asm/cacheflush.h b/arch/sparc/include/asm/cacheflush.h index 049168087b19..f6c4839b8388 100644 --- a/arch/sparc/include/asm/cacheflush.h +++ b/arch/sparc/include/asm/cacheflush.h @@ -1,5 +1,9 @@ #ifndef ___ASM_SPARC_CACHEFLUSH_H #define ___ASM_SPARC_CACHEFLUSH_H + +/* flush addr - to allow use of self-modifying code */ +#define flushi(addr) __asm__ __volatile__ ("flush %0" : : "r" (addr) : "memory") + #if defined(__sparc__) && defined(__arch64__) #include <asm/cacheflush_64.h> #else diff --git a/arch/sparc/include/asm/cacheflush_32.h b/arch/sparc/include/asm/cacheflush_32.h index 68431b47a22a..bb014c24f318 100644 --- a/arch/sparc/include/asm/cacheflush_32.h +++ b/arch/sparc/include/asm/cacheflush_32.h @@ -1,56 +1,18 @@ #ifndef _SPARC_CACHEFLUSH_H #define _SPARC_CACHEFLUSH_H -#include <linux/mm.h> /* Common for other includes */ -// #include <linux/kernel.h> from pgalloc.h -// #include <linux/sched.h> from pgalloc.h - -// #include <asm/page.h> -#include <asm/btfixup.h> - -/* - * Fine grained cache flushing. - */ -#ifdef CONFIG_SMP - -BTFIXUPDEF_CALL(void, local_flush_cache_all, void) -BTFIXUPDEF_CALL(void, local_flush_cache_mm, struct mm_struct *) -BTFIXUPDEF_CALL(void, local_flush_cache_range, struct vm_area_struct *, unsigned long, unsigned long) -BTFIXUPDEF_CALL(void, local_flush_cache_page, struct vm_area_struct *, unsigned long) - -#define local_flush_cache_all() BTFIXUP_CALL(local_flush_cache_all)() -#define local_flush_cache_mm(mm) BTFIXUP_CALL(local_flush_cache_mm)(mm) -#define local_flush_cache_range(vma,start,end) BTFIXUP_CALL(local_flush_cache_range)(vma,start,end) -#define local_flush_cache_page(vma,addr) BTFIXUP_CALL(local_flush_cache_page)(vma,addr) - -BTFIXUPDEF_CALL(void, local_flush_page_to_ram, unsigned long) -BTFIXUPDEF_CALL(void, local_flush_sig_insns, struct mm_struct *, unsigned long) - -#define local_flush_page_to_ram(addr) BTFIXUP_CALL(local_flush_page_to_ram)(addr) -#define local_flush_sig_insns(mm,insn_addr) BTFIXUP_CALL(local_flush_sig_insns)(mm,insn_addr) - -extern void smp_flush_cache_all(void); -extern void smp_flush_cache_mm(struct mm_struct *mm); -extern void smp_flush_cache_range(struct vm_area_struct *vma, - unsigned long start, - unsigned long end); -extern void smp_flush_cache_page(struct vm_area_struct *vma, unsigned long page); - -extern void smp_flush_page_to_ram(unsigned long page); -extern void smp_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr); - -#endif /* CONFIG_SMP */ - -BTFIXUPDEF_CALL(void, flush_cache_all, void) -BTFIXUPDEF_CALL(void, flush_cache_mm, struct mm_struct *) -BTFIXUPDEF_CALL(void, flush_cache_range, struct vm_area_struct *, unsigned long, unsigned long) -BTFIXUPDEF_CALL(void, flush_cache_page, struct vm_area_struct *, unsigned long) - -#define flush_cache_all() BTFIXUP_CALL(flush_cache_all)() -#define flush_cache_mm(mm) BTFIXUP_CALL(flush_cache_mm)(mm) -#define flush_cache_dup_mm(mm) BTFIXUP_CALL(flush_cache_mm)(mm) -#define flush_cache_range(vma,start,end) BTFIXUP_CALL(flush_cache_range)(vma,start,end) -#define flush_cache_page(vma,addr,pfn) BTFIXUP_CALL(flush_cache_page)(vma,addr) +#include <asm/cachetlb_32.h> + +#define flush_cache_all() \ + sparc32_cachetlb_ops->cache_all() +#define flush_cache_mm(mm) \ + sparc32_cachetlb_ops->cache_mm(mm) +#define flush_cache_dup_mm(mm) \ + sparc32_cachetlb_ops->cache_mm(mm) +#define flush_cache_range(vma,start,end) \ + sparc32_cachetlb_ops->cache_range(vma, start, end) +#define flush_cache_page(vma,addr,pfn) \ + sparc32_cachetlb_ops->cache_page(vma, addr) #define flush_icache_range(start, end) do { } while (0) #define flush_icache_page(vma, pg) do { } while (0) @@ -67,11 +29,12 @@ BTFIXUPDEF_CALL(void, flush_cache_page, struct vm_area_struct *, unsigned long) memcpy(dst, src, len); \ } while (0) -BTFIXUPDEF_CALL(void, __flush_page_to_ram, unsigned long) -BTFIXUPDEF_CALL(void, flush_sig_insns, struct mm_struct *, unsigned long) - -#define __flush_page_to_ram(addr) BTFIXUP_CALL(__flush_page_to_ram)(addr) -#define flush_sig_insns(mm,insn_addr) BTFIXUP_CALL(flush_sig_insns)(mm,insn_addr) +#define __flush_page_to_ram(addr) \ + sparc32_cachetlb_ops->page_to_ram(addr) +#define flush_sig_insns(mm,insn_addr) \ + sparc32_cachetlb_ops->sig_insns(mm, insn_addr) +#define flush_page_for_dma(addr) \ + sparc32_cachetlb_ops->page_for_dma(addr) extern void sparc_flush_page_to_ram(struct page *page); diff --git a/arch/sparc/include/asm/cacheflush_64.h b/arch/sparc/include/asm/cacheflush_64.h index 2efea2ff88b7..301736d9e7a1 100644 --- a/arch/sparc/include/asm/cacheflush_64.h +++ b/arch/sparc/include/asm/cacheflush_64.h @@ -8,9 +8,6 @@ #include <linux/mm.h> /* Cache flush operations. */ - - -#define flushi(addr) __asm__ __volatile__ ("flush %0" : : "r" (addr) : "memory") #define flushw_all() __asm__ __volatile__("flushw") extern void __flushw_user(void); diff --git a/arch/sparc/include/asm/cachetlb_32.h b/arch/sparc/include/asm/cachetlb_32.h new file mode 100644 index 000000000000..efb19889a083 --- /dev/null +++ b/arch/sparc/include/asm/cachetlb_32.h @@ -0,0 +1,29 @@ +#ifndef _SPARC_CACHETLB_H +#define _SPARC_CACHETLB_H + +struct mm_struct; +struct vm_area_struct; + +struct sparc32_cachetlb_ops { + void (*cache_all)(void); + void (*cache_mm)(struct mm_struct *); + void (*cache_range)(struct vm_area_struct *, unsigned long, + unsigned long); + void (*cache_page)(struct vm_area_struct *, unsigned long); + + void (*tlb_all)(void); + void (*tlb_mm)(struct mm_struct *); + void (*tlb_range)(struct vm_area_struct *, unsigned long, + unsigned long); + void (*tlb_page)(struct vm_area_struct *, unsigned long); + + void (*page_to_ram)(unsigned long); + void (*sig_insns)(struct mm_struct *, unsigned long); + void (*page_for_dma)(unsigned long); +}; +extern const struct sparc32_cachetlb_ops *sparc32_cachetlb_ops; +#ifdef CONFIG_SMP +extern const struct sparc32_cachetlb_ops *local_ops; +#endif + +#endif /* SPARC_CACHETLB_H */ diff --git a/arch/sparc/include/asm/cmpxchg_32.h b/arch/sparc/include/asm/cmpxchg_32.h index c786b0a92b51..1fae1a02e3c2 100644 --- a/arch/sparc/include/asm/cmpxchg_32.h +++ b/arch/sparc/include/asm/cmpxchg_32.h @@ -11,40 +11,13 @@ #ifndef __ARCH_SPARC_CMPXCHG__ #define __ARCH_SPARC_CMPXCHG__ -#include <asm/btfixup.h> - -/* This has special calling conventions */ -#ifndef CONFIG_SMP -BTFIXUPDEF_CALL(void, ___xchg32, void) -#endif - static inline unsigned long xchg_u32(__volatile__ unsigned long *m, unsigned long val) { -#ifdef CONFIG_SMP __asm__ __volatile__("swap [%2], %0" : "=&r" (val) : "0" (val), "r" (m) : "memory"); return val; -#else - register unsigned long *ptr asm("g1"); - register unsigned long ret asm("g2"); - - ptr = (unsigned long *) m; - ret = val; - - /* Note: this is magic and the nop there is - really needed. */ - __asm__ __volatile__( - "mov %%o7, %%g4\n\t" - "call ___f____xchg32\n\t" - " nop\n\t" - : "=&r" (ret) - : "0" (ret), "r" (ptr) - : "g3", "g4", "g7", "memory", "cc"); - - return ret; -#endif } extern void __xchg_called_with_bad_pointer(void); diff --git a/arch/sparc/include/asm/contregs.h b/arch/sparc/include/asm/contregs.h index 48fa8a4ef357..b8abdfcf5555 100644 --- a/arch/sparc/include/asm/contregs.h +++ b/arch/sparc/include/asm/contregs.h @@ -7,28 +7,6 @@ * Copyright (C) 1995 David S. Miller ([email protected]) */ -/* 3=sun3 - 4=sun4 (as in sun4 sysmaint student book) - c=sun4c (according to davem) */ - -#define AC_IDPROM 0x00000000 /* 34 ID PROM, R/O, byte, 32 bytes */ -#define AC_PAGEMAP 0x10000000 /* 3 Pagemap R/W, long */ -#define AC_SEGMAP 0x20000000 /* 3 Segment map, byte */ -#define AC_CONTEXT 0x30000000 /* 34c current mmu-context */ -#define AC_SENABLE 0x40000000 /* 34c system dvma/cache/reset enable reg*/ -#define AC_UDVMA_ENB 0x50000000 /* 34 Not used on Sun boards, byte */ -#define AC_BUS_ERROR 0x60000000 /* 34 Not cleared on read, byte. */ -#define AC_SYNC_ERR 0x60000000 /* c fault type */ -#define AC_SYNC_VA 0x60000004 /* c fault virtual address */ -#define AC_ASYNC_ERR 0x60000008 /* c asynchronous fault type */ -#define AC_ASYNC_VA 0x6000000c /* c async fault virtual address */ -#define AC_LEDS 0x70000000 /* 34 Zero turns on LEDs, byte */ -#define AC_CACHETAGS 0x80000000 /* 34c direct access to the VAC tags */ -#define AC_CACHEDDATA 0x90000000 /* 3 c direct access to the VAC data */ -#define AC_UDVMA_MAP 0xD0000000 /* 4 Not used on Sun boards, byte */ -#define AC_VME_VECTOR 0xE0000000 /* 4 For non-Autovector VME, byte */ -#define AC_BOOT_SCC 0xF0000000 /* 34 bypass to access Zilog 8530. byte.*/ - /* s=Swift, h=Ross_HyperSPARC, v=TI_Viking, t=Tsunami, r=Ross_Cypress */ #define AC_M_PCR 0x0000 /* shv Processor Control Reg */ #define AC_M_CTPR 0x0100 /* shv Context Table Pointer Reg */ diff --git a/arch/sparc/include/asm/cpu_type.h b/arch/sparc/include/asm/cpu_type.h index 4ca184d95d82..84d7d83b8084 100644 --- a/arch/sparc/include/asm/cpu_type.h +++ b/arch/sparc/include/asm/cpu_type.h @@ -5,30 +5,24 @@ * Sparc (general) CPU types */ enum sparc_cpu { - sun4 = 0x00, - sun4c = 0x01, - sun4m = 0x02, - sun4d = 0x03, - sun4e = 0x04, - sun4u = 0x05, /* V8 ploos ploos */ - sun_unknown = 0x06, - ap1000 = 0x07, /* almost a sun4m */ - sparc_leon = 0x08, /* Leon SoC */ + sun4m = 0x00, + sun4d = 0x01, + sun4e = 0x02, + sun4u = 0x03, /* V8 ploos ploos */ + sun_unknown = 0x04, + ap1000 = 0x05, /* almost a sun4m */ + sparc_leon = 0x06, /* Leon SoC */ }; #ifdef CONFIG_SPARC32 extern enum sparc_cpu sparc_cpu_model; -#define ARCH_SUN4C (sparc_cpu_model==sun4c) - #define SUN4M_NCPUS 4 /* Architectural limit of sun4m. */ #else #define sparc_cpu_model sun4u -/* This cannot ever be a sun4c :) That's just history. */ -#define ARCH_SUN4C 0 #endif #endif /* __ASM_CPU_TYPE_H */ diff --git a/arch/sparc/include/asm/cpudata_32.h b/arch/sparc/include/asm/cpudata_32.h index a4c5a938b936..0300d94c25b3 100644 --- a/arch/sparc/include/asm/cpudata_32.h +++ b/arch/sparc/include/asm/cpudata_32.h @@ -14,7 +14,6 @@ typedef struct { unsigned long udelay_val; unsigned long clock_tick; - unsigned int multiplier; unsigned int counter; #ifdef CONFIG_SMP unsigned int irq_resched_count; diff --git a/arch/sparc/include/asm/cypress.h b/arch/sparc/include/asm/cypress.h deleted file mode 100644 index 95e9772ea394..000000000000 --- a/arch/sparc/include/asm/cypress.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * cypress.h: Cypress module specific definitions and defines. - * - * Copyright (C) 1995 David S. Miller ([email protected]) - */ - -#ifndef _SPARC_CYPRESS_H -#define _SPARC_CYPRESS_H - -/* Cypress chips have %psr 'impl' of '0001' and 'vers' of '0001'. */ - -/* The MMU control register fields on the Sparc Cypress 604/605 MMU's. - * - * --------------------------------------------------------------- - * |implvers| MCA | MCM |MV| MID |BM| C|RSV|MR|CM|CL|CE|RSV|NF|ME| - * --------------------------------------------------------------- - * 31 24 23-22 21-20 19 18-15 14 13 12 11 10 9 8 7-2 1 0 - * - * MCA: MultiChip Access -- Used for configuration of multiple - * CY7C604/605 cache units. - * MCM: MultiChip Mask -- Again, for multiple cache unit config. - * MV: MultiChip Valid -- Indicates MCM and MCA have valid settings. - * MID: ModuleID -- Unique processor ID for MBus transactions. (605 only) - * BM: Boot Mode -- 0 = not in boot mode, 1 = in boot mode - * C: Cacheable -- Indicates whether accesses are cacheable while - * the MMU is off. 0=no 1=yes - * MR: MemoryReflection -- Indicates whether the bus attached to the - * MBus supports memory reflection. 0=no 1=yes (605 only) - * CM: CacheMode -- Indicates whether the cache is operating in write - * through or copy-back mode. 0=write-through 1=copy-back - * CL: CacheLock -- Indicates if the entire cache is locked or not. - * 0=not-locked 1=locked (604 only) - * CE: CacheEnable -- Is the virtual cache on? 0=no 1=yes - * NF: NoFault -- Do faults generate traps? 0=yes 1=no - * ME: MmuEnable -- Is the MMU doing translations? 0=no 1=yes - */ - -#define CYPRESS_MCA 0x00c00000 -#define CYPRESS_MCM 0x00300000 -#define CYPRESS_MVALID 0x00080000 -#define CYPRESS_MIDMASK 0x00078000 /* Only on 605 */ -#define CYPRESS_BMODE 0x00004000 -#define CYPRESS_ACENABLE 0x00002000 -#define CYPRESS_MRFLCT 0x00000800 /* Only on 605 */ -#define CYPRESS_CMODE 0x00000400 -#define CYPRESS_CLOCK 0x00000200 /* Only on 604 */ -#define CYPRESS_CENABLE 0x00000100 -#define CYPRESS_NFAULT 0x00000002 -#define CYPRESS_MENABLE 0x00000001 - -static inline void cypress_flush_page(unsigned long page) -{ - __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : : - "r" (page), "i" (ASI_M_FLUSH_PAGE)); -} - -static inline void cypress_flush_segment(unsigned long addr) -{ - __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : : - "r" (addr), "i" (ASI_M_FLUSH_SEG)); -} - -static inline void cypress_flush_region(unsigned long addr) -{ - __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : : - "r" (addr), "i" (ASI_M_FLUSH_REGION)); -} - -static inline void cypress_flush_context(void) -{ - __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t" : : - "i" (ASI_M_FLUSH_CTX)); -} - -/* XXX Displacement flushes for buggy chips and initial testing - * XXX go here. - */ - -#endif /* !(_SPARC_CYPRESS_H) */ diff --git a/arch/sparc/include/asm/dma.h b/arch/sparc/include/asm/dma.h index b554927bbaf6..3d434ef5eae3 100644 --- a/arch/sparc/include/asm/dma.h +++ b/arch/sparc/include/asm/dma.h @@ -92,27 +92,31 @@ extern int isa_dma_bridge_buggy; #ifdef CONFIG_SPARC32 /* Routines for data transfer buffers. */ -BTFIXUPDEF_CALL(char *, mmu_lockarea, char *, unsigned long) -BTFIXUPDEF_CALL(void, mmu_unlockarea, char *, unsigned long) - -#define mmu_lockarea(vaddr,len) BTFIXUP_CALL(mmu_lockarea)(vaddr,len) -#define mmu_unlockarea(vaddr,len) BTFIXUP_CALL(mmu_unlockarea)(vaddr,len) - -struct page; struct device; struct scatterlist; -/* These are implementations for sbus_map_sg/sbus_unmap_sg... collapse later */ -BTFIXUPDEF_CALL(__u32, mmu_get_scsi_one, struct device *, char *, unsigned long) -BTFIXUPDEF_CALL(void, mmu_get_scsi_sgl, struct device *, struct scatterlist *, int) -BTFIXUPDEF_CALL(void, mmu_release_scsi_one, struct device *, __u32, unsigned long) -BTFIXUPDEF_CALL(void, mmu_release_scsi_sgl, struct device *, struct scatterlist *, int) - -#define mmu_get_scsi_one(dev,vaddr,len) BTFIXUP_CALL(mmu_get_scsi_one)(dev,vaddr,len) -#define mmu_get_scsi_sgl(dev,sg,sz) BTFIXUP_CALL(mmu_get_scsi_sgl)(dev,sg,sz) -#define mmu_release_scsi_one(dev,vaddr,len) BTFIXUP_CALL(mmu_release_scsi_one)(dev,vaddr,len) -#define mmu_release_scsi_sgl(dev,sg,sz) BTFIXUP_CALL(mmu_release_scsi_sgl)(dev,sg,sz) - +struct sparc32_dma_ops { + __u32 (*get_scsi_one)(struct device *, char *, unsigned long); + void (*get_scsi_sgl)(struct device *, struct scatterlist *, int); + void (*release_scsi_one)(struct device *, __u32, unsigned long); + void (*release_scsi_sgl)(struct device *, struct scatterlist *,int); +#ifdef CONFIG_SBUS + int (*map_dma_area)(struct device *, dma_addr_t *, unsigned long, unsigned long, int); + void (*unmap_dma_area)(struct device *, unsigned long, int); +#endif +}; +extern const struct sparc32_dma_ops *sparc32_dma_ops; + +#define mmu_get_scsi_one(dev,vaddr,len) \ + sparc32_dma_ops->get_scsi_one(dev, vaddr, len) +#define mmu_get_scsi_sgl(dev,sg,sz) \ + sparc32_dma_ops->get_scsi_sgl(dev, sg, sz) +#define mmu_release_scsi_one(dev,vaddr,len) \ + sparc32_dma_ops->release_scsi_one(dev, vaddr,len) +#define mmu_release_scsi_sgl(dev,sg,sz) \ + sparc32_dma_ops->release_scsi_sgl(dev, sg, sz) + +#ifdef CONFIG_SBUS /* * mmu_map/unmap are provided by iommu/iounit; Invalid to call on IIep. * @@ -123,17 +127,17 @@ BTFIXUPDEF_CALL(void, mmu_release_scsi_sgl, struct device *, struct scatterlist * Second mapping is for device visible address, or "bus" address. * The bus address is returned at '*pba'. * - * These functions seem distinct, but are hard to split. On sun4c, - * at least for now, 'a' is equal to bus address, and retured in *pba. + * These functions seem distinct, but are hard to split. * On sun4m, page attributes depend on the CPU type, so we have to * know if we are mapping RAM or I/O, so it has to be an additional argument * to a separate mapping function for CPU visible mappings. */ -BTFIXUPDEF_CALL(int, mmu_map_dma_area, struct device *, dma_addr_t *, unsigned long, unsigned long, int len) -BTFIXUPDEF_CALL(void, mmu_unmap_dma_area, struct device *, unsigned long busa, int len) +#define sbus_map_dma_area(dev,pba,va,a,len) \ + sparc32_dma_ops->map_dma_area(dev, pba, va, a, len) +#define sbus_unmap_dma_area(dev,ba,len) \ + sparc32_dma_ops->unmap_dma_area(dev, ba, len) +#endif /* CONFIG_SBUS */ -#define mmu_map_dma_area(dev,pba,va,a,len) BTFIXUP_CALL(mmu_map_dma_area)(dev,pba,va,a,len) -#define mmu_unmap_dma_area(dev,ba,len) BTFIXUP_CALL(mmu_unmap_dma_area)(dev,ba,len) #endif #endif /* !(_ASM_SPARC_DMA_H) */ diff --git a/arch/sparc/include/asm/elf_32.h b/arch/sparc/include/asm/elf_32.h index 4269ca6ad18a..2d4d755cba9e 100644 --- a/arch/sparc/include/asm/elf_32.h +++ b/arch/sparc/include/asm/elf_32.h @@ -118,16 +118,9 @@ typedef struct { instruction set this cpu supports. This can NOT be done in userspace on Sparc. */ -/* Sun4c has none of the capabilities, most sun4m's have them all. - * XXX This is gross, set some global variable at boot time. -DaveM - */ -#define ELF_HWCAP ((ARCH_SUN4C) ? 0 : \ - (HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR | \ - HWCAP_SPARC_SWAP | \ - ((srmmu_modtype != Cypress && \ - srmmu_modtype != Cypress_vE && \ - srmmu_modtype != Cypress_vD) ? \ - HWCAP_SPARC_MULDIV : 0))) +/* Most sun4m's have them all. */ +#define ELF_HWCAP (HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR | \ + HWCAP_SPARC_SWAP | HWCAP_SPARC_MULDIV) /* This yields a string that ld.so will use to load implementation specific libraries for optimization. This is more specific in diff --git a/arch/sparc/include/asm/floppy_32.h b/arch/sparc/include/asm/floppy_32.h index 698d9559fead..fb3f16954c69 100644 --- a/arch/sparc/include/asm/floppy_32.h +++ b/arch/sparc/include/asm/floppy_32.h @@ -12,7 +12,6 @@ #include <asm/page.h> #include <asm/pgtable.h> #include <asm/idprom.h> -#include <asm/machines.h> #include <asm/oplib.h> #include <asm/auxio.h> #include <asm/irq.h> @@ -103,25 +102,13 @@ static struct sun_floppy_ops sun_fdops; /* Routines unique to each controller type on a Sun. */ static void sun_set_dor(unsigned char value, int fdc_82077) { - if (sparc_cpu_model == sun4c) { - unsigned int bits = 0; - if (value & 0x10) - bits |= AUXIO_FLPY_DSEL; - if ((value & 0x80) == 0) - bits |= AUXIO_FLPY_EJCT; - set_auxio(bits, (~bits) & (AUXIO_FLPY_DSEL|AUXIO_FLPY_EJCT)); - } - if (fdc_82077) { + if (fdc_82077) sun_fdc->dor_82077 = value; - } } static unsigned char sun_read_dir(void) { - if (sparc_cpu_model == sun4c) - return (get_auxio() & AUXIO_FLPY_DCHG) ? 0x80 : 0; - else - return sun_fdc->dir_82077; + return sun_fdc->dir_82077; } static unsigned char sun_82072_fd_inb(int port) @@ -242,10 +229,7 @@ static inline void virtual_dma_init(void) static inline void sun_fd_disable_dma(void) { doing_pdma = 0; - if (pdma_base) { - mmu_unlockarea(pdma_base, pdma_areasize); - pdma_base = NULL; - } + pdma_base = NULL; } static inline void sun_fd_set_dma_mode(int mode) @@ -275,7 +259,6 @@ static inline void sun_fd_set_dma_count(int length) static inline void sun_fd_enable_dma(void) { - pdma_vaddr = mmu_lockarea(pdma_vaddr, pdma_size); pdma_base = pdma_vaddr; pdma_areasize = pdma_size; } @@ -301,38 +284,36 @@ static int sun_floppy_init(void) { struct platform_device *op; struct device_node *dp; + struct resource r; char state[128]; - phandle tnode, fd_node; + phandle fd_node; + phandle tnode; int num_regs; - struct resource r; use_virtual_dma = 1; /* Forget it if we aren't on a machine that could possibly * ever have a floppy drive. */ - if((sparc_cpu_model != sun4c && sparc_cpu_model != sun4m) || - ((idprom->id_machtype == (SM_SUN4C | SM_4C_SLC)) || - (idprom->id_machtype == (SM_SUN4C | SM_4C_ELC)))) { + if (sparc_cpu_model != sun4m) { /* We certainly don't have a floppy controller. */ goto no_sun_fdc; } /* Well, try to find one. */ tnode = prom_getchild(prom_root_node); fd_node = prom_searchsiblings(tnode, "obio"); - if(fd_node != 0) { + if (fd_node != 0) { tnode = prom_getchild(fd_node); fd_node = prom_searchsiblings(tnode, "SUNW,fdtwo"); } else { fd_node = prom_searchsiblings(tnode, "fd"); } - if(fd_node == 0) { + if (fd_node == 0) { goto no_sun_fdc; } /* The sun4m lets us know if the controller is actually usable. */ - if(sparc_cpu_model == sun4m && - prom_getproperty(fd_node, "status", state, sizeof(state)) != -1) { + if (prom_getproperty(fd_node, "status", state, sizeof(state)) != -1) { if(!strcmp(state, "disabled")) { goto no_sun_fdc; } @@ -343,12 +324,12 @@ static int sun_floppy_init(void) memset(&r, 0, sizeof(r)); r.flags = fd_regs[0].which_io; r.start = fd_regs[0].phys_addr; - sun_fdc = (struct sun_flpy_controller *) - of_ioremap(&r, 0, fd_regs[0].reg_size, "floppy"); + sun_fdc = of_ioremap(&r, 0, fd_regs[0].reg_size, "floppy"); /* Look up irq in platform_device. * We try "SUNW,fdtwo" and "fd" */ + op = NULL; for_each_node_by_name(dp, "SUNW,fdtwo") { op = of_find_device_by_node(dp); if (op) @@ -367,7 +348,7 @@ static int sun_floppy_init(void) FLOPPY_IRQ = op->archdata.irqs[0]; /* Last minute sanity check... */ - if(sun_fdc->status_82072 == 0xff) { + if (sun_fdc->status_82072 == 0xff) { sun_fdc = NULL; goto no_sun_fdc; } diff --git a/arch/sparc/include/asm/floppy_64.h b/arch/sparc/include/asm/floppy_64.h index bcef1f5a2a6d..e204f902e6c9 100644 --- a/arch/sparc/include/asm/floppy_64.h +++ b/arch/sparc/include/asm/floppy_64.h @@ -161,10 +161,7 @@ unsigned long pdma_areasize; static void sun_fd_disable_dma(void) { doing_pdma = 0; - if (pdma_base) { - mmu_unlockarea(pdma_base, pdma_areasize); - pdma_base = NULL; - } + pdma_base = NULL; } static void sun_fd_set_dma_mode(int mode) @@ -194,7 +191,6 @@ static void sun_fd_set_dma_count(int length) static void sun_fd_enable_dma(void) { - pdma_vaddr = mmu_lockarea(pdma_vaddr, pdma_size); pdma_base = pdma_vaddr; pdma_areasize = pdma_size; } diff --git a/arch/sparc/include/asm/head_32.h b/arch/sparc/include/asm/head_32.h index 7c35491a8b53..a76874838f61 100644 --- a/arch/sparc/include/asm/head_32.h +++ b/arch/sparc/include/asm/head_32.h @@ -2,15 +2,8 @@ #define __SPARC_HEAD_H #define KERNBASE 0xf0000000 /* First address the kernel will eventually be */ -#define LOAD_ADDR 0x4000 /* prom jumps to us here unless this is elf /boot */ -#define SUN4C_SEGSZ (1 << 18) -#define SRMMU_L1_KBASE_OFFSET ((KERNBASE>>24)<<2) /* Used in boot remapping. */ -#define INTS_ENAB 0x01 /* entry.S uses this. */ - -#define SUN4_PROM_VECTOR 0xFFE81000 /* SUN4 PROM needs to be hardwired */ #define WRITE_PAUSE nop; nop; nop; /* Have to do this after %wim/%psr chg */ -#define NOP_INSN 0x01000000 /* Used to patch sparc_save_state */ /* Here are some trap goodies */ @@ -18,9 +11,7 @@ #define TRAP_ENTRY(type, label) \ rd %psr, %l0; b label; rd %wim, %l3; nop; -/* Data/text faults. Defaults to sun4c version at boot time. */ -#define SPARC_TFAULT rd %psr, %l0; rd %wim, %l3; b sun4c_fault; mov 1, %l7; -#define SPARC_DFAULT rd %psr, %l0; rd %wim, %l3; b sun4c_fault; mov 0, %l7; +/* Data/text faults */ #define SRMMU_TFAULT rd %psr, %l0; rd %wim, %l3; b srmmu_fault; mov 1, %l7; #define SRMMU_DFAULT rd %psr, %l0; rd %wim, %l3; b srmmu_fault; mov 0, %l7; @@ -80,16 +71,6 @@ #define TRAP_ENTRY_INTERRUPT(int_level) \ mov int_level, %l7; rd %psr, %l0; b real_irq_entry; rd %wim, %l3; -/* NMI's (Non Maskable Interrupts) are special, you can't keep them - * from coming in, and basically if you get one, the shows over. ;( - * On the sun4c they are usually asynchronous memory errors, on the - * the sun4m they could be either due to mem errors or a software - * initiated interrupt from the prom/kern on an SMP box saying "I - * command you to do CPU tricks, read your mailbox for more info." - */ -#define NMI_TRAP \ - rd %wim, %l3; b linux_trap_nmi_sun4c; mov %psr, %l0; nop; - /* Window overflows/underflows are special and we need to try to be as * efficient as possible here.... */ diff --git a/arch/sparc/include/asm/leon.h b/arch/sparc/include/asm/leon.h index a4e457f003ed..24f802beffb9 100644 --- a/arch/sparc/include/asm/leon.h +++ b/arch/sparc/include/asm/leon.h @@ -10,19 +10,6 @@ #ifdef CONFIG_SPARC_LEON -#define ASI_LEON_NOCACHE 0x01 - -#define ASI_LEON_DCACHE_MISS 0x1 - -#define ASI_LEON_CACHEREGS 0x02 -#define ASI_LEON_IFLUSH 0x10 -#define ASI_LEON_DFLUSH 0x11 - -#define ASI_LEON_MMUFLUSH 0x18 -#define ASI_LEON_MMUREGS 0x19 -#define ASI_LEON_BYPASS 0x1c -#define ASI_LEON_FLUSH_PAGE 0x10 - /* mmu register access, ASI_LEON_MMUREGS */ #define LEON_CNR_CTRL 0x000 #define LEON_CNR_CTXP 0x100 @@ -57,29 +44,6 @@ #define LEON_IRQMASK_R 0x0000fffe /* bit 15- 1 of lregs.irqmask */ #define LEON_IRQPRIO_R 0xfffe0000 /* bit 31-17 of lregs.irqmask */ -/* leon uart register definitions */ -#define LEON_OFF_UDATA 0x0 -#define LEON_OFF_USTAT 0x4 -#define LEON_OFF_UCTRL 0x8 -#define LEON_OFF_USCAL 0xc - -#define LEON_UCTRL_RE 0x01 -#define LEON_UCTRL_TE 0x02 -#define LEON_UCTRL_RI 0x04 -#define LEON_UCTRL_TI 0x08 -#define LEON_UCTRL_PS 0x10 -#define LEON_UCTRL_PE 0x20 -#define LEON_UCTRL_FL 0x40 -#define LEON_UCTRL_LB 0x80 - -#define LEON_USTAT_DR 0x01 -#define LEON_USTAT_TS 0x02 -#define LEON_USTAT_TH 0x04 -#define LEON_USTAT_BR 0x08 -#define LEON_USTAT_OV 0x10 -#define LEON_USTAT_PE 0x20 -#define LEON_USTAT_FE 0x40 - #define LEON_MCFG2_SRAMDIS 0x00002000 #define LEON_MCFG2_SDRAMEN 0x00004000 #define LEON_MCFG2_SRAMBANKSZ 0x00001e00 /* [12-9] */ @@ -89,8 +53,6 @@ #define LEON_TCNT0_MASK 0x7fffff -#define LEON_USTAT_ERROR (LEON_USTAT_OV | LEON_USTAT_PE | LEON_USTAT_FE) -/* no break yet */ #define ASI_LEON3_SYSCTRL 0x02 #define ASI_LEON3_SYSCTRL_ICFG 0x08 @@ -278,18 +240,11 @@ static inline int sparc_leon3_cpuid(void) #define LEON2_CFG_SSIZE_MASK 0x00007000UL #ifndef __ASSEMBLY__ -extern unsigned long srmmu_swprobe(unsigned long vaddr, unsigned long *paddr); -extern void leon_flush_icache_all(void); -extern void leon_flush_dcache_all(void); -extern void leon_flush_cache_all(void); -extern void leon_flush_tlb_all(void); -extern int leon_flush_during_switch; -extern int leon_flush_needed(void); - struct vm_area_struct; + +extern unsigned long srmmu_swprobe(unsigned long vaddr, unsigned long *paddr); extern void leon_flush_icache_all(void); extern void leon_flush_dcache_all(void); -extern void leon_flush_pcache_all(struct vm_area_struct *vma, unsigned long page); extern void leon_flush_cache_all(void); extern void leon_flush_tlb_all(void); extern int leon_flush_during_switch; @@ -321,22 +276,12 @@ extern unsigned int leon_build_device_irq(unsigned int real_irq, extern void leon_update_virq_handling(unsigned int virq, irq_flow_handler_t flow_handler, const char *name, int do_ack); -extern void leon_clear_clock_irq(void); -extern void leon_load_profile_irq(int cpu, unsigned int limit); -extern void leon_init_timers(irq_handler_t counter_fn); -extern void leon_clear_clock_irq(void); -extern void leon_load_profile_irq(int cpu, unsigned int limit); +extern void leon_init_timers(void); extern void leon_trans_init(struct device_node *dp); extern void leon_node_init(struct device_node *dp, struct device_node ***nextp); -extern void leon_init_IRQ(void); -extern void leon_init(void); -extern unsigned long srmmu_swprobe(unsigned long vaddr, unsigned long *paddr); extern void init_leon(void); extern void poke_leonsparc(void); extern void leon3_getCacheRegs(struct leon3_cacheregs *regs); -extern int leon_flush_needed(void); -extern void leon_switch_mm(void); -extern int srmmu_swprobe_trace; extern int leon3_ticker_irq; #ifdef CONFIG_SMP diff --git a/arch/sparc/include/asm/machines.h b/arch/sparc/include/asm/machines.h index cd9c099567e4..fd6ddb05d1b7 100644 --- a/arch/sparc/include/asm/machines.h +++ b/arch/sparc/include/asm/machines.h @@ -12,11 +12,6 @@ struct Sun_Machine_Models { unsigned char id_machtype; }; -/* Current number of machines we know about that has an IDPROM - * machtype entry including one entry for the 0x80 OBP machines. - */ -#define NUM_SUN_MACHINES 16 - /* The machine type in the idprom area looks like this: * * --------------- @@ -24,36 +19,20 @@ struct Sun_Machine_Models { * --------------- * 7 4 3 0 * - * The ARCH field determines the architecture line (sun4, sun4c, etc). + * The ARCH field determines the architecture line (sun4m, etc). * The MACH field determines the machine make within that architecture. */ #define SM_ARCH_MASK 0xf0 -#define SM_SUN4 0x20 #define M_LEON 0x30 -#define SM_SUN4C 0x50 #define SM_SUN4M 0x70 #define SM_SUN4M_OBP 0x80 #define SM_TYP_MASK 0x0f -/* Sun4 machines */ -#define SM_4_260 0x01 /* Sun 4/200 series */ -#define SM_4_110 0x02 /* Sun 4/100 series */ -#define SM_4_330 0x03 /* Sun 4/300 series */ -#define SM_4_470 0x04 /* Sun 4/400 series */ /* Leon machines */ #define M_LEON3_SOC 0x02 /* Leon3 SoC */ -/* Sun4c machines Full Name - PROM NAME */ -#define SM_4C_SS1 0x01 /* Sun4c SparcStation 1 - Sun 4/60 */ -#define SM_4C_IPC 0x02 /* Sun4c SparcStation IPC - Sun 4/40 */ -#define SM_4C_SS1PLUS 0x03 /* Sun4c SparcStation 1+ - Sun 4/65 */ -#define SM_4C_SLC 0x04 /* Sun4c SparcStation SLC - Sun 4/20 */ -#define SM_4C_SS2 0x05 /* Sun4c SparcStation 2 - Sun 4/75 */ -#define SM_4C_ELC 0x06 /* Sun4c SparcStation ELC - Sun 4/25 */ -#define SM_4C_IPX 0x07 /* Sun4c SparcStation IPX - Sun 4/50 */ - /* Sun4m machines, these predate the OpenBoot. These values only mean * something if the value in the ARCH field is SM_SUN4M, if it is * SM_SUN4M_OBP then you have the following situation: diff --git a/arch/sparc/include/asm/mbus.h b/arch/sparc/include/asm/mbus.h index 69f07a022ee6..14128bcc5821 100644 --- a/arch/sparc/include/asm/mbus.h +++ b/arch/sparc/include/asm/mbus.h @@ -8,14 +8,10 @@ #define _SPARC_MBUS_H #include <asm/ross.h> /* HyperSparc stuff */ -#include <asm/cypress.h> /* Cypress Chips */ #include <asm/viking.h> /* Ugh, bug city... */ enum mbus_module { HyperSparc = 0, - Cypress = 1, - Cypress_vE = 2, - Cypress_vD = 3, Swift_ok = 4, Swift_bad_c = 5, Swift_lots_o_bugs = 6, diff --git a/arch/sparc/include/asm/memreg.h b/arch/sparc/include/asm/memreg.h deleted file mode 100644 index 845ad2b39183..000000000000 --- a/arch/sparc/include/asm/memreg.h +++ /dev/null @@ -1,51 +0,0 @@ -#ifndef _SPARC_MEMREG_H -#define _SPARC_MEMREG_H -/* memreg.h: Definitions of the values found in the synchronous - * and asynchronous memory error registers when a fault - * occurs on the sun4c. - * - * Copyright (C) 1995 David S. Miller ([email protected]) - */ - -/* First the synchronous error codes, these are usually just - * normal page faults. - */ - -#define SUN4C_SYNC_WDRESET 0x0001 /* watchdog reset */ -#define SUN4C_SYNC_SIZE 0x0002 /* bad access size? whuz this? */ -#define SUN4C_SYNC_PARITY 0x0008 /* bad ram chips caused a parity error */ -#define SUN4C_SYNC_SBUS 0x0010 /* the SBUS had some problems... */ -#define SUN4C_SYNC_NOMEM 0x0020 /* translation to non-existent ram */ -#define SUN4C_SYNC_PROT 0x0040 /* access violated pte protections */ -#define SUN4C_SYNC_NPRESENT 0x0080 /* pte said that page was not present */ -#define SUN4C_SYNC_BADWRITE 0x8000 /* while writing something went bogus */ - -#define SUN4C_SYNC_BOLIXED \ - (SUN4C_SYNC_WDRESET | SUN4C_SYNC_SIZE | SUN4C_SYNC_SBUS | \ - SUN4C_SYNC_NOMEM | SUN4C_SYNC_PARITY) - -/* Now the asynchronous error codes, these are almost always produced - * by the cache writing things back to memory and getting a bad translation. - * Bad DVMA transactions can cause these faults too. - */ - -#define SUN4C_ASYNC_BADDVMA 0x0010 /* error during DVMA access */ -#define SUN4C_ASYNC_NOMEM 0x0020 /* write back pointed to bad phys addr */ -#define SUN4C_ASYNC_BADWB 0x0080 /* write back points to non-present page */ - -/* Memory parity error register with associated bit constants. */ -#ifndef __ASSEMBLY__ -extern __volatile__ unsigned long __iomem *sun4c_memerr_reg; -#endif - -#define SUN4C_MPE_ERROR 0x80 /* Parity error detected. (ro) */ -#define SUN4C_MPE_MULTI 0x40 /* Multiple parity errors detected. (ro) */ -#define SUN4C_MPE_TEST 0x20 /* Write inverse parity. (rw) */ -#define SUN4C_MPE_CHECK 0x10 /* Enable parity checking. (rw) */ -#define SUN4C_MPE_ERR00 0x08 /* Parity error in bits 0-7. (ro) */ -#define SUN4C_MPE_ERR08 0x04 /* Parity error in bits 8-15. (ro) */ -#define SUN4C_MPE_ERR16 0x02 /* Parity error in bits 16-23. (ro) */ -#define SUN4C_MPE_ERR24 0x01 /* Parity error in bits 24-31. (ro) */ -#define SUN4C_MPE_ERRS 0x0F /* Bit mask for the error bits. (ro) */ - -#endif /* !(_SPARC_MEMREG_H) */ diff --git a/arch/sparc/include/asm/mmu_context_32.h b/arch/sparc/include/asm/mmu_context_32.h index 671a997b9e69..01456c900720 100644 --- a/arch/sparc/include/asm/mmu_context_32.h +++ b/arch/sparc/include/asm/mmu_context_32.h @@ -1,8 +1,6 @@ #ifndef __SPARC_MMU_CONTEXT_H #define __SPARC_MMU_CONTEXT_H -#include <asm/btfixup.h> - #ifndef __ASSEMBLY__ #include <asm-generic/mm_hooks.h> @@ -23,14 +21,11 @@ static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) * all the page tables have been flushed. Our job is to destroy * any remaining processor-specific state. */ -BTFIXUPDEF_CALL(void, destroy_context, struct mm_struct *) - -#define destroy_context(mm) BTFIXUP_CALL(destroy_context)(mm) +void destroy_context(struct mm_struct *mm); /* Switch the current MM context. */ -BTFIXUPDEF_CALL(void, switch_mm, struct mm_struct *, struct mm_struct *, struct task_struct *) - -#define switch_mm(old_mm, mm, tsk) BTFIXUP_CALL(switch_mm)(old_mm, mm, tsk) +void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm, + struct task_struct *tsk); #define deactivate_mm(tsk,mm) do { } while (0) diff --git a/arch/sparc/include/asm/obio.h b/arch/sparc/include/asm/obio.h index 4ade0c8a2c79..910c1d9af1f8 100644 --- a/arch/sparc/include/asm/obio.h +++ b/arch/sparc/include/asm/obio.h @@ -220,19 +220,6 @@ static inline void cc_set_igen(unsigned gen) "i" (ASI_M_MXCC)); } -/* +-------+-------------+-----------+------------------------------------+ - * | bcast | devid | sid | levels mask | - * +-------+-------------+-----------+------------------------------------+ - * 31 30 23 22 15 14 0 - */ -#define IGEN_MESSAGE(bcast, devid, sid, levels) \ - (((bcast) << 31) | ((devid) << 23) | ((sid) << 15) | (levels)) - -static inline void sun4d_send_ipi(int cpu, int level) -{ - cc_set_igen(IGEN_MESSAGE(0, cpu << 3, 6 + ((level >> 1) & 7), 1 << (level - 1))); -} - #endif /* !__ASSEMBLY__ */ #endif /* !(_SPARC_OBIO_H) */ diff --git a/arch/sparc/include/asm/oplib_32.h b/arch/sparc/include/asm/oplib_32.h index 71e5e9aeb67e..27517879a6c2 100644 --- a/arch/sparc/include/asm/oplib_32.h +++ b/arch/sparc/include/asm/oplib_32.h @@ -105,14 +105,6 @@ extern void prom_write(const char *buf, unsigned int len); extern int prom_startcpu(int cpunode, struct linux_prom_registers *context_table, int context, char *program_counter); -/* Sun4/sun4c specific memory-management startup hook. */ - -/* Map the passed segment in the given context at the passed - * virtual address. - */ -extern void prom_putsegment(int context, unsigned long virt_addr, - int physical_segment); - /* Initialize the memory lists based upon the prom version. */ void prom_meminit(void); diff --git a/arch/sparc/include/asm/page_32.h b/arch/sparc/include/asm/page_32.h index bb5c2ac4055d..fab78a308ebf 100644 --- a/arch/sparc/include/asm/page_32.h +++ b/arch/sparc/include/asm/page_32.h @@ -14,8 +14,6 @@ #define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT) #define PAGE_MASK (~(PAGE_SIZE-1)) -#include <asm/btfixup.h> - #ifndef __ASSEMBLY__ #define clear_page(page) memset((void *)(page), 0, PAGE_SIZE) @@ -45,12 +43,6 @@ struct sparc_phys_banks { extern struct sparc_phys_banks sp_banks[SPARC_PHYS_BANKS+1]; -/* Cache alias structure. Entry is valid if context != -1. */ -struct cache_palias { - unsigned long vaddr; - int context; -}; - /* passing structs on the Sparc slow us down tremendously... */ /* #define STRICT_MM_TYPECHECKS */ @@ -116,10 +108,7 @@ typedef unsigned long iopgprot_t; typedef struct page *pgtable_t; extern unsigned long sparc_unmapped_base; - -BTFIXUPDEF_SETHI(sparc_unmapped_base) - -#define TASK_UNMAPPED_BASE BTFIXUP_SETHI(sparc_unmapped_base) +#define TASK_UNMAPPED_BASE sparc_unmapped_base #else /* !(__ASSEMBLY__) */ diff --git a/arch/sparc/include/asm/pgalloc_32.h b/arch/sparc/include/asm/pgalloc_32.h index ca2b34456c4b..e5b169b46d21 100644 --- a/arch/sparc/include/asm/pgalloc_32.h +++ b/arch/sparc/include/asm/pgalloc_32.h @@ -4,8 +4,10 @@ #include <linux/kernel.h> #include <linux/sched.h> +#include <asm/pgtsrmmu.h> +#include <asm/pgtable.h> +#include <asm/vaddrs.h> #include <asm/page.h> -#include <asm/btfixup.h> struct page; @@ -15,54 +17,74 @@ extern struct pgtable_cache_struct { unsigned long pgtable_cache_sz; unsigned long pgd_cache_sz; } pgt_quicklists; + +unsigned long srmmu_get_nocache(int size, int align); +void srmmu_free_nocache(unsigned long vaddr, int size); + #define pgd_quicklist (pgt_quicklists.pgd_cache) #define pmd_quicklist ((unsigned long *)0) #define pte_quicklist (pgt_quicklists.pte_cache) #define pgtable_cache_size (pgt_quicklists.pgtable_cache_sz) #define pgd_cache_size (pgt_quicklists.pgd_cache_sz) -extern void check_pgt_cache(void); -BTFIXUPDEF_CALL(void, do_check_pgt_cache, int, int) -#define do_check_pgt_cache(low,high) BTFIXUP_CALL(do_check_pgt_cache)(low,high) - -BTFIXUPDEF_CALL(pgd_t *, get_pgd_fast, void) -#define get_pgd_fast() BTFIXUP_CALL(get_pgd_fast)() +#define check_pgt_cache() do { } while (0) -BTFIXUPDEF_CALL(void, free_pgd_fast, pgd_t *) -#define free_pgd_fast(pgd) BTFIXUP_CALL(free_pgd_fast)(pgd) +pgd_t *get_pgd_fast(void); +static inline void free_pgd_fast(pgd_t *pgd) +{ + srmmu_free_nocache((unsigned long)pgd, SRMMU_PGD_TABLE_SIZE); +} #define pgd_free(mm, pgd) free_pgd_fast(pgd) #define pgd_alloc(mm) get_pgd_fast() -BTFIXUPDEF_CALL(void, pgd_set, pgd_t *, pmd_t *) -#define pgd_set(pgdp,pmdp) BTFIXUP_CALL(pgd_set)(pgdp,pmdp) +static inline void pgd_set(pgd_t * pgdp, pmd_t * pmdp) +{ + unsigned long pa = __nocache_pa((unsigned long)pmdp); + + set_pte((pte_t *)pgdp, (SRMMU_ET_PTD | (pa >> 4))); +} + #define pgd_populate(MM, PGD, PMD) pgd_set(PGD, PMD) -BTFIXUPDEF_CALL(pmd_t *, pmd_alloc_one, struct mm_struct *, unsigned long) -#define pmd_alloc_one(mm, address) BTFIXUP_CALL(pmd_alloc_one)(mm, address) +static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, + unsigned long address) +{ + return (pmd_t *)srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, + SRMMU_PMD_TABLE_SIZE); +} -BTFIXUPDEF_CALL(void, free_pmd_fast, pmd_t *) -#define free_pmd_fast(pmd) BTFIXUP_CALL(free_pmd_fast)(pmd) +static inline void free_pmd_fast(pmd_t * pmd) +{ + srmmu_free_nocache((unsigned long)pmd, SRMMU_PMD_TABLE_SIZE); +} #define pmd_free(mm, pmd) free_pmd_fast(pmd) #define __pmd_free_tlb(tlb, pmd, addr) pmd_free((tlb)->mm, pmd) -BTFIXUPDEF_CALL(void, pmd_populate, pmd_t *, struct page *) -#define pmd_populate(MM, PMD, PTE) BTFIXUP_CALL(pmd_populate)(PMD, PTE) +void pmd_populate(struct mm_struct *mm, pmd_t *pmdp, struct page *ptep); #define pmd_pgtable(pmd) pmd_page(pmd) -BTFIXUPDEF_CALL(void, pmd_set, pmd_t *, pte_t *) -#define pmd_populate_kernel(MM, PMD, PTE) BTFIXUP_CALL(pmd_set)(PMD, PTE) -BTFIXUPDEF_CALL(pgtable_t , pte_alloc_one, struct mm_struct *, unsigned long) -#define pte_alloc_one(mm, address) BTFIXUP_CALL(pte_alloc_one)(mm, address) -BTFIXUPDEF_CALL(pte_t *, pte_alloc_one_kernel, struct mm_struct *, unsigned long) -#define pte_alloc_one_kernel(mm, addr) BTFIXUP_CALL(pte_alloc_one_kernel)(mm, addr) +void pmd_set(pmd_t *pmdp, pte_t *ptep); +#define pmd_populate_kernel(MM, PMD, PTE) pmd_set(PMD, PTE) + +pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address); + +static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, + unsigned long address) +{ + return (pte_t *)srmmu_get_nocache(PTE_SIZE, PTE_SIZE); +} + + +static inline void free_pte_fast(pte_t *pte) +{ + srmmu_free_nocache((unsigned long)pte, PTE_SIZE); +} -BTFIXUPDEF_CALL(void, free_pte_fast, pte_t *) -#define pte_free_kernel(mm, pte) BTFIXUP_CALL(free_pte_fast)(pte) +#define pte_free_kernel(mm, pte) free_pte_fast(pte) -BTFIXUPDEF_CALL(void, pte_free, pgtable_t ) -#define pte_free(mm, pte) BTFIXUP_CALL(pte_free)(pte) +void pte_free(struct mm_struct * mm, pgtable_t pte); #define __pte_free_tlb(tlb, pte, addr) pte_free((tlb)->mm, pte) #endif /* _SPARC_PGALLOC_H */ diff --git a/arch/sparc/include/asm/pgtable_32.h b/arch/sparc/include/asm/pgtable_32.h index 3d7101860e68..cbbbed5cb3aa 100644 --- a/arch/sparc/include/asm/pgtable_32.h +++ b/arch/sparc/include/asm/pgtable_32.h @@ -16,11 +16,9 @@ #include <linux/spinlock.h> #include <linux/swap.h> #include <asm/types.h> -#include <asm/pgtsun4c.h> #include <asm/pgtsrmmu.h> -#include <asm/vac-ops.h> +#include <asm/vaddrs.h> #include <asm/oplib.h> -#include <asm/btfixup.h> #include <asm/cpu_type.h> @@ -30,87 +28,55 @@ struct page; extern void load_mmu(void); extern unsigned long calc_highpages(void); -BTFIXUPDEF_SIMM13(pgdir_shift) -BTFIXUPDEF_SETHI(pgdir_size) -BTFIXUPDEF_SETHI(pgdir_mask) - -BTFIXUPDEF_SIMM13(ptrs_per_pmd) -BTFIXUPDEF_SIMM13(ptrs_per_pgd) -BTFIXUPDEF_SIMM13(user_ptrs_per_pgd) - #define pte_ERROR(e) __builtin_trap() #define pmd_ERROR(e) __builtin_trap() #define pgd_ERROR(e) __builtin_trap() -BTFIXUPDEF_INT(page_none) -BTFIXUPDEF_INT(page_copy) -BTFIXUPDEF_INT(page_readonly) -BTFIXUPDEF_INT(page_kernel) - -#define PMD_SHIFT SUN4C_PMD_SHIFT +#define PMD_SHIFT 22 #define PMD_SIZE (1UL << PMD_SHIFT) #define PMD_MASK (~(PMD_SIZE-1)) #define PMD_ALIGN(__addr) (((__addr) + ~PMD_MASK) & PMD_MASK) -#define PGDIR_SHIFT BTFIXUP_SIMM13(pgdir_shift) -#define PGDIR_SIZE BTFIXUP_SETHI(pgdir_size) -#define PGDIR_MASK BTFIXUP_SETHI(pgdir_mask) +#define PGDIR_SHIFT SRMMU_PGDIR_SHIFT +#define PGDIR_SIZE SRMMU_PGDIR_SIZE +#define PGDIR_MASK SRMMU_PGDIR_MASK #define PTRS_PER_PTE 1024 -#define PTRS_PER_PMD BTFIXUP_SIMM13(ptrs_per_pmd) -#define PTRS_PER_PGD BTFIXUP_SIMM13(ptrs_per_pgd) -#define USER_PTRS_PER_PGD BTFIXUP_SIMM13(user_ptrs_per_pgd) +#define PTRS_PER_PMD SRMMU_PTRS_PER_PMD +#define PTRS_PER_PGD SRMMU_PTRS_PER_PGD +#define USER_PTRS_PER_PGD PAGE_OFFSET / SRMMU_PGDIR_SIZE #define FIRST_USER_ADDRESS 0 #define PTE_SIZE (PTRS_PER_PTE*4) -#define PAGE_NONE __pgprot(BTFIXUP_INT(page_none)) -extern pgprot_t PAGE_SHARED; -#define PAGE_COPY __pgprot(BTFIXUP_INT(page_copy)) -#define PAGE_READONLY __pgprot(BTFIXUP_INT(page_readonly)) - -extern unsigned long page_kernel; - -#ifdef MODULE -#define PAGE_KERNEL page_kernel -#else -#define PAGE_KERNEL __pgprot(BTFIXUP_INT(page_kernel)) -#endif +#define PAGE_NONE SRMMU_PAGE_NONE +#define PAGE_SHARED SRMMU_PAGE_SHARED +#define PAGE_COPY SRMMU_PAGE_COPY +#define PAGE_READONLY SRMMU_PAGE_RDONLY +#define PAGE_KERNEL SRMMU_PAGE_KERNEL /* Top-level page directory */ extern pgd_t swapper_pg_dir[1024]; extern void paging_init(void); -/* Page table for 0-4MB for everybody, on the Sparc this - * holds the same as on the i386. - */ -extern pte_t pg0[1024]; -extern pte_t pg1[1024]; -extern pte_t pg2[1024]; -extern pte_t pg3[1024]; - extern unsigned long ptr_in_current_pgd; -/* Here is a trick, since mmap.c need the initializer elements for - * protection_map[] to be constant at compile time, I set the following - * to all zeros. I set it to the real values after I link in the - * appropriate MMU page table routines at boot time. - */ -#define __P000 __pgprot(0) -#define __P001 __pgprot(0) -#define __P010 __pgprot(0) -#define __P011 __pgprot(0) -#define __P100 __pgprot(0) -#define __P101 __pgprot(0) -#define __P110 __pgprot(0) -#define __P111 __pgprot(0) - -#define __S000 __pgprot(0) -#define __S001 __pgprot(0) -#define __S010 __pgprot(0) -#define __S011 __pgprot(0) -#define __S100 __pgprot(0) -#define __S101 __pgprot(0) -#define __S110 __pgprot(0) -#define __S111 __pgprot(0) +/* xwr */ +#define __P000 PAGE_NONE +#define __P001 PAGE_READONLY +#define __P010 PAGE_COPY +#define __P011 PAGE_COPY +#define __P100 PAGE_READONLY +#define __P101 PAGE_READONLY +#define __P110 PAGE_COPY +#define __P111 PAGE_COPY + +#define __S000 PAGE_NONE +#define __S001 PAGE_READONLY +#define __S010 PAGE_SHARED +#define __S011 PAGE_SHARED +#define __S100 PAGE_READONLY +#define __S101 PAGE_READONLY +#define __S110 PAGE_SHARED +#define __S111 PAGE_SHARED extern int num_contexts; @@ -137,82 +103,137 @@ extern unsigned long empty_zero_page; #define ZERO_PAGE(vaddr) (virt_to_page(&empty_zero_page)) /* + * In general all page table modifications should use the V8 atomic + * swap instruction. This insures the mmu and the cpu are in sync + * with respect to ref/mod bits in the page tables. + */ +static inline unsigned long srmmu_swap(unsigned long *addr, unsigned long value) +{ + __asm__ __volatile__("swap [%2], %0" : "=&r" (value) : "0" (value), "r" (addr)); + return value; +} + +/* Certain architectures need to do special things when pte's + * within a page table are directly modified. Thus, the following + * hook is made available. */ -BTFIXUPDEF_CALL_CONST(struct page *, pmd_page, pmd_t) -BTFIXUPDEF_CALL_CONST(unsigned long, pgd_page_vaddr, pgd_t) -#define pmd_page(pmd) BTFIXUP_CALL(pmd_page)(pmd) -#define pgd_page_vaddr(pgd) BTFIXUP_CALL(pgd_page_vaddr)(pgd) +static inline void set_pte(pte_t *ptep, pte_t pteval) +{ + srmmu_swap((unsigned long *)ptep, pte_val(pteval)); +} + +#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) + +static inline int srmmu_device_memory(unsigned long x) +{ + return ((x & 0xF0000000) != 0); +} + +static inline struct page *pmd_page(pmd_t pmd) +{ + if (srmmu_device_memory(pmd_val(pmd))) + BUG(); + return pfn_to_page((pmd_val(pmd) & SRMMU_PTD_PMASK) >> (PAGE_SHIFT-4)); +} + +static inline unsigned long pgd_page_vaddr(pgd_t pgd) +{ + if (srmmu_device_memory(pgd_val(pgd))) { + return ~0; + } else { + unsigned long v = pgd_val(pgd) & SRMMU_PTD_PMASK; + return (unsigned long)__nocache_va(v << 4); + } +} -BTFIXUPDEF_CALL_CONST(int, pte_present, pte_t) -BTFIXUPDEF_CALL(void, pte_clear, pte_t *) +static inline int pte_present(pte_t pte) +{ + return ((pte_val(pte) & SRMMU_ET_MASK) == SRMMU_ET_PTE); +} static inline int pte_none(pte_t pte) { return !pte_val(pte); } -#define pte_present(pte) BTFIXUP_CALL(pte_present)(pte) -#define pte_clear(mm,addr,pte) BTFIXUP_CALL(pte_clear)(pte) +static inline void __pte_clear(pte_t *ptep) +{ + set_pte(ptep, __pte(0)); +} + +static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) +{ + __pte_clear(ptep); +} + +static inline int pmd_bad(pmd_t pmd) +{ + return (pmd_val(pmd) & SRMMU_ET_MASK) != SRMMU_ET_PTD; +} -BTFIXUPDEF_CALL_CONST(int, pmd_bad, pmd_t) -BTFIXUPDEF_CALL_CONST(int, pmd_present, pmd_t) -BTFIXUPDEF_CALL(void, pmd_clear, pmd_t *) +static inline int pmd_present(pmd_t pmd) +{ + return ((pmd_val(pmd) & SRMMU_ET_MASK) == SRMMU_ET_PTD); +} static inline int pmd_none(pmd_t pmd) { return !pmd_val(pmd); } -#define pmd_bad(pmd) BTFIXUP_CALL(pmd_bad)(pmd) -#define pmd_present(pmd) BTFIXUP_CALL(pmd_present)(pmd) -#define pmd_clear(pmd) BTFIXUP_CALL(pmd_clear)(pmd) +static inline void pmd_clear(pmd_t *pmdp) +{ + int i; + for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++) + set_pte((pte_t *)&pmdp->pmdv[i], __pte(0)); +} -BTFIXUPDEF_CALL_CONST(int, pgd_none, pgd_t) -BTFIXUPDEF_CALL_CONST(int, pgd_bad, pgd_t) -BTFIXUPDEF_CALL_CONST(int, pgd_present, pgd_t) -BTFIXUPDEF_CALL(void, pgd_clear, pgd_t *) +static inline int pgd_none(pgd_t pgd) +{ + return !(pgd_val(pgd) & 0xFFFFFFF); +} -#define pgd_none(pgd) BTFIXUP_CALL(pgd_none)(pgd) -#define pgd_bad(pgd) BTFIXUP_CALL(pgd_bad)(pgd) -#define pgd_present(pgd) BTFIXUP_CALL(pgd_present)(pgd) -#define pgd_clear(pgd) BTFIXUP_CALL(pgd_clear)(pgd) +static inline int pgd_bad(pgd_t pgd) +{ + return (pgd_val(pgd) & SRMMU_ET_MASK) != SRMMU_ET_PTD; +} + +static inline int pgd_present(pgd_t pgd) +{ + return ((pgd_val(pgd) & SRMMU_ET_MASK) == SRMMU_ET_PTD); +} + +static inline void pgd_clear(pgd_t *pgdp) +{ + set_pte((pte_t *)pgdp, __pte(0)); +} /* * The following only work if pte_present() is true. * Undefined behaviour if not.. */ -BTFIXUPDEF_HALF(pte_writei) -BTFIXUPDEF_HALF(pte_dirtyi) -BTFIXUPDEF_HALF(pte_youngi) - -static int pte_write(pte_t pte) __attribute_const__; static inline int pte_write(pte_t pte) { - return pte_val(pte) & BTFIXUP_HALF(pte_writei); + return pte_val(pte) & SRMMU_WRITE; } -static int pte_dirty(pte_t pte) __attribute_const__; static inline int pte_dirty(pte_t pte) { - return pte_val(pte) & BTFIXUP_HALF(pte_dirtyi); + return pte_val(pte) & SRMMU_DIRTY; } -static int pte_young(pte_t pte) __attribute_const__; static inline int pte_young(pte_t pte) { - return pte_val(pte) & BTFIXUP_HALF(pte_youngi); + return pte_val(pte) & SRMMU_REF; } /* * The following only work if pte_present() is not true. */ -BTFIXUPDEF_HALF(pte_filei) - -static int pte_file(pte_t pte) __attribute_const__; static inline int pte_file(pte_t pte) { - return pte_val(pte) & BTFIXUP_HALF(pte_filei); + return pte_val(pte) & SRMMU_FILE; } static inline int pte_special(pte_t pte) @@ -220,68 +241,85 @@ static inline int pte_special(pte_t pte) return 0; } -/* - */ -BTFIXUPDEF_HALF(pte_wrprotecti) -BTFIXUPDEF_HALF(pte_mkcleani) -BTFIXUPDEF_HALF(pte_mkoldi) - -static pte_t pte_wrprotect(pte_t pte) __attribute_const__; static inline pte_t pte_wrprotect(pte_t pte) { - return __pte(pte_val(pte) & ~BTFIXUP_HALF(pte_wrprotecti)); + return __pte(pte_val(pte) & ~SRMMU_WRITE); } -static pte_t pte_mkclean(pte_t pte) __attribute_const__; static inline pte_t pte_mkclean(pte_t pte) { - return __pte(pte_val(pte) & ~BTFIXUP_HALF(pte_mkcleani)); + return __pte(pte_val(pte) & ~SRMMU_DIRTY); } -static pte_t pte_mkold(pte_t pte) __attribute_const__; static inline pte_t pte_mkold(pte_t pte) { - return __pte(pte_val(pte) & ~BTFIXUP_HALF(pte_mkoldi)); + return __pte(pte_val(pte) & ~SRMMU_REF); } -BTFIXUPDEF_CALL_CONST(pte_t, pte_mkwrite, pte_t) -BTFIXUPDEF_CALL_CONST(pte_t, pte_mkdirty, pte_t) -BTFIXUPDEF_CALL_CONST(pte_t, pte_mkyoung, pte_t) +static inline pte_t pte_mkwrite(pte_t pte) +{ + return __pte(pte_val(pte) | SRMMU_WRITE); +} + +static inline pte_t pte_mkdirty(pte_t pte) +{ + return __pte(pte_val(pte) | SRMMU_DIRTY); +} -#define pte_mkwrite(pte) BTFIXUP_CALL(pte_mkwrite)(pte) -#define pte_mkdirty(pte) BTFIXUP_CALL(pte_mkdirty)(pte) -#define pte_mkyoung(pte) BTFIXUP_CALL(pte_mkyoung)(pte) +static inline pte_t pte_mkyoung(pte_t pte) +{ + return __pte(pte_val(pte) | SRMMU_REF); +} #define pte_mkspecial(pte) (pte) #define pfn_pte(pfn, prot) mk_pte(pfn_to_page(pfn), prot) -BTFIXUPDEF_CALL(unsigned long, pte_pfn, pte_t) -#define pte_pfn(pte) BTFIXUP_CALL(pte_pfn)(pte) +static inline unsigned long pte_pfn(pte_t pte) +{ + if (srmmu_device_memory(pte_val(pte))) { + /* Just return something that will cause + * pfn_valid() to return false. This makes + * copy_one_pte() to just directly copy to + * PTE over. + */ + return ~0UL; + } + return (pte_val(pte) & SRMMU_PTE_PMASK) >> (PAGE_SHIFT-4); +} + #define pte_page(pte) pfn_to_page(pte_pfn(pte)) /* * Conversion functions: convert a page and protection to a page entry, * and a page entry and page directory to the page they refer to. */ -BTFIXUPDEF_CALL_CONST(pte_t, mk_pte, struct page *, pgprot_t) - -BTFIXUPDEF_CALL_CONST(pte_t, mk_pte_phys, unsigned long, pgprot_t) -BTFIXUPDEF_CALL_CONST(pte_t, mk_pte_io, unsigned long, pgprot_t, int) -BTFIXUPDEF_CALL_CONST(pgprot_t, pgprot_noncached, pgprot_t) +static inline pte_t mk_pte(struct page *page, pgprot_t pgprot) +{ + return __pte((page_to_pfn(page) << (PAGE_SHIFT-4)) | pgprot_val(pgprot)); +} -#define mk_pte(page,pgprot) BTFIXUP_CALL(mk_pte)(page,pgprot) -#define mk_pte_phys(page,pgprot) BTFIXUP_CALL(mk_pte_phys)(page,pgprot) -#define mk_pte_io(page,pgprot,space) BTFIXUP_CALL(mk_pte_io)(page,pgprot,space) +static inline pte_t mk_pte_phys(unsigned long page, pgprot_t pgprot) +{ + return __pte(((page) >> 4) | pgprot_val(pgprot)); +} -#define pgprot_noncached(pgprot) BTFIXUP_CALL(pgprot_noncached)(pgprot) +static inline pte_t mk_pte_io(unsigned long page, pgprot_t pgprot, int space) +{ + return __pte(((page) >> 4) | (space << 28) | pgprot_val(pgprot)); +} -BTFIXUPDEF_INT(pte_modify_mask) +#define pgprot_noncached pgprot_noncached +static inline pgprot_t pgprot_noncached(pgprot_t prot) +{ + prot &= ~__pgprot(SRMMU_CACHE); + return prot; +} static pte_t pte_modify(pte_t pte, pgprot_t newprot) __attribute_const__; static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) { - return __pte((pte_val(pte) & BTFIXUP_INT(pte_modify_mask)) | + return __pte((pte_val(pte) & SRMMU_CHG_MASK) | pgprot_val(newprot)); } @@ -294,74 +332,69 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) #define pgd_offset_k(address) pgd_offset(&init_mm, address) /* Find an entry in the second-level page table.. */ -BTFIXUPDEF_CALL(pmd_t *, pmd_offset, pgd_t *, unsigned long) -#define pmd_offset(dir,addr) BTFIXUP_CALL(pmd_offset)(dir,addr) +static inline pmd_t *pmd_offset(pgd_t * dir, unsigned long address) +{ + return (pmd_t *) pgd_page_vaddr(*dir) + + ((address >> PMD_SHIFT) & (PTRS_PER_PMD - 1)); +} /* Find an entry in the third-level page table.. */ -BTFIXUPDEF_CALL(pte_t *, pte_offset_kernel, pmd_t *, unsigned long) -#define pte_offset_kernel(dir,addr) BTFIXUP_CALL(pte_offset_kernel)(dir,addr) +pte_t *pte_offset_kernel(pmd_t * dir, unsigned long address); /* - * This shortcut works on sun4m (and sun4d) because the nocache area is static, - * and sun4c is guaranteed to have no highmem anyway. + * This shortcut works on sun4m (and sun4d) because the nocache area is static. */ #define pte_offset_map(d, a) pte_offset_kernel(d,a) #define pte_unmap(pte) do{}while(0) -/* Certain architectures need to do special things when pte's - * within a page table are directly modified. Thus, the following - * hook is made available. - */ - -BTFIXUPDEF_CALL(void, set_pte, pte_t *, pte_t) - -#define set_pte(ptep,pteval) BTFIXUP_CALL(set_pte)(ptep,pteval) -#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) - struct seq_file; -BTFIXUPDEF_CALL(void, mmu_info, struct seq_file *) - -#define mmu_info(p) BTFIXUP_CALL(mmu_info)(p) +void mmu_info(struct seq_file *m); /* Fault handler stuff... */ #define FAULT_CODE_PROT 0x1 #define FAULT_CODE_WRITE 0x2 #define FAULT_CODE_USER 0x4 -BTFIXUPDEF_CALL(void, update_mmu_cache, struct vm_area_struct *, unsigned long, pte_t *) - -#define update_mmu_cache(vma,addr,ptep) BTFIXUP_CALL(update_mmu_cache)(vma,addr,ptep) - -BTFIXUPDEF_CALL(void, sparc_mapiorange, unsigned int, unsigned long, - unsigned long, unsigned int) -BTFIXUPDEF_CALL(void, sparc_unmapiorange, unsigned long, unsigned int) -#define sparc_mapiorange(bus,pa,va,len) BTFIXUP_CALL(sparc_mapiorange)(bus,pa,va,len) -#define sparc_unmapiorange(va,len) BTFIXUP_CALL(sparc_unmapiorange)(va,len) +#define update_mmu_cache(vma, address, ptep) do { } while (0) -extern int invalid_segment; +void srmmu_mapiorange(unsigned int bus, unsigned long xpa, + unsigned long xva, unsigned int len); +void srmmu_unmapiorange(unsigned long virt_addr, unsigned int len); /* Encode and de-code a swap entry */ -BTFIXUPDEF_CALL(unsigned long, __swp_type, swp_entry_t) -BTFIXUPDEF_CALL(unsigned long, __swp_offset, swp_entry_t) -BTFIXUPDEF_CALL(swp_entry_t, __swp_entry, unsigned long, unsigned long) +static inline unsigned long __swp_type(swp_entry_t entry) +{ + return (entry.val >> SRMMU_SWP_TYPE_SHIFT) & SRMMU_SWP_TYPE_MASK; +} + +static inline unsigned long __swp_offset(swp_entry_t entry) +{ + return (entry.val >> SRMMU_SWP_OFF_SHIFT) & SRMMU_SWP_OFF_MASK; +} -#define __swp_type(__x) BTFIXUP_CALL(__swp_type)(__x) -#define __swp_offset(__x) BTFIXUP_CALL(__swp_offset)(__x) -#define __swp_entry(__type,__off) BTFIXUP_CALL(__swp_entry)(__type,__off) +static inline swp_entry_t __swp_entry(unsigned long type, unsigned long offset) +{ + return (swp_entry_t) { + (type & SRMMU_SWP_TYPE_MASK) << SRMMU_SWP_TYPE_SHIFT + | (offset & SRMMU_SWP_OFF_MASK) << SRMMU_SWP_OFF_SHIFT }; +} #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) /* file-offset-in-pte helpers */ -BTFIXUPDEF_CALL(unsigned long, pte_to_pgoff, pte_t pte); -BTFIXUPDEF_CALL(pte_t, pgoff_to_pte, unsigned long pgoff); +static inline unsigned long pte_to_pgoff(pte_t pte) +{ + return pte_val(pte) >> SRMMU_PTE_FILE_SHIFT; +} -#define pte_to_pgoff(pte) BTFIXUP_CALL(pte_to_pgoff)(pte) -#define pgoff_to_pte(off) BTFIXUP_CALL(pgoff_to_pte)(off) +static inline pte_t pgoff_to_pte(unsigned long pgoff) +{ + return __pte((pgoff << SRMMU_PTE_FILE_SHIFT) | SRMMU_FILE); +} /* * This is made a constant because mm/fremap.c required a constant. - * Note that layout of these bits is different between sun4c.c and srmmu.c. */ #define PTE_FILE_MAX_BITS 24 @@ -399,9 +432,6 @@ static inline unsigned long __get_phys (unsigned long addr) { switch (sparc_cpu_model){ - case sun4: - case sun4c: - return sun4c_get_pte (addr) << PAGE_SHIFT; case sun4m: case sun4d: return ((srmmu_get_pte (addr) & 0xffffff00) << 4); @@ -414,9 +444,6 @@ static inline int __get_iospace (unsigned long addr) { switch (sparc_cpu_model){ - case sun4: - case sun4c: - return -1; /* Don't check iospace on sun4c */ case sun4m: case sun4d: return (srmmu_get_pte (addr) >> 28); @@ -463,7 +490,7 @@ static inline int io_remap_pfn_range(struct vm_area_struct *vma, set_pte_at((__vma)->vm_mm, (__address), __ptep, __entry); \ flush_tlb_page(__vma, __address); \ } \ - (sparc_cpu_model == sun4c) || __changed; \ + __changed; \ }) #include <asm-generic/pgtable.h> @@ -471,10 +498,8 @@ static inline int io_remap_pfn_range(struct vm_area_struct *vma, #endif /* !(__ASSEMBLY__) */ #define VMALLOC_START _AC(0xfe600000,UL) -/* XXX Alter this when I get around to fixing sun4c - Anton */ #define VMALLOC_END _AC(0xffc00000,UL) - /* We provide our own get_unmapped_area to cope with VA holes for userland */ #define HAVE_ARCH_UNMAPPED_AREA diff --git a/arch/sparc/include/asm/pgtable_64.h b/arch/sparc/include/asm/pgtable_64.h index 76e4a52aa85e..61210db139fb 100644 --- a/arch/sparc/include/asm/pgtable_64.h +++ b/arch/sparc/include/asm/pgtable_64.h @@ -717,10 +717,6 @@ extern unsigned long find_ecache_flush_span(unsigned long size); struct seq_file; extern void mmu_info(struct seq_file *); -/* These do nothing with the way I have things setup. */ -#define mmu_lockarea(vaddr, len) (vaddr) -#define mmu_unlockarea(vaddr, len) do { } while(0) - struct vm_area_struct; extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *); diff --git a/arch/sparc/include/asm/pgtsrmmu.h b/arch/sparc/include/asm/pgtsrmmu.h index f6ae2b2b6870..cb828703a63a 100644 --- a/arch/sparc/include/asm/pgtsrmmu.h +++ b/arch/sparc/include/asm/pgtsrmmu.h @@ -173,17 +173,6 @@ static inline void srmmu_set_ctable_ptr(unsigned long paddr) "memory"); } -static inline unsigned long srmmu_get_ctable_ptr(void) -{ - unsigned int retval; - - __asm__ __volatile__("lda [%1] %2, %0\n\t" : - "=r" (retval) : - "r" (SRMMU_CTXTBL_PTR), - "i" (ASI_M_MMUREGS)); - return (retval & SRMMU_CTX_PMASK) << 4; -} - static inline void srmmu_set_context(int context) { __asm__ __volatile__("sta %0, [%1] %2\n\t" : : @@ -231,42 +220,6 @@ static inline void srmmu_flush_whole_tlb(void) } /* These flush types are not available on all chips... */ -static inline void srmmu_flush_tlb_ctx(void) -{ - __asm__ __volatile__("sta %%g0, [%0] %1\n\t": : - "r" (0x300), /* Flush TLB ctx.. */ - "i" (ASI_M_FLUSH_PROBE) : "memory"); - -} - -static inline void srmmu_flush_tlb_region(unsigned long addr) -{ - addr &= SRMMU_PGDIR_MASK; - __asm__ __volatile__("sta %%g0, [%0] %1\n\t": : - "r" (addr | 0x200), /* Flush TLB region.. */ - "i" (ASI_M_FLUSH_PROBE) : "memory"); - -} - - -static inline void srmmu_flush_tlb_segment(unsigned long addr) -{ - addr &= SRMMU_REAL_PMD_MASK; - __asm__ __volatile__("sta %%g0, [%0] %1\n\t": : - "r" (addr | 0x100), /* Flush TLB segment.. */ - "i" (ASI_M_FLUSH_PROBE) : "memory"); - -} - -static inline void srmmu_flush_tlb_page(unsigned long page) -{ - page &= PAGE_MASK; - __asm__ __volatile__("sta %%g0, [%0] %1\n\t": : - "r" (page), /* Flush TLB page.. */ - "i" (ASI_M_FLUSH_PROBE) : "memory"); - -} - #ifndef CONFIG_SPARC_LEON static inline unsigned long srmmu_hwprobe(unsigned long vaddr) { @@ -294,9 +247,6 @@ srmmu_get_pte (unsigned long addr) return entry; } -extern unsigned long (*srmmu_read_physical)(unsigned long paddr); -extern void (*srmmu_write_physical)(unsigned long paddr, unsigned long word); - #endif /* !(__ASSEMBLY__) */ #endif /* !(_SPARC_PGTSRMMU_H) */ diff --git a/arch/sparc/include/asm/pgtsun4c.h b/arch/sparc/include/asm/pgtsun4c.h deleted file mode 100644 index aeb25e912179..000000000000 --- a/arch/sparc/include/asm/pgtsun4c.h +++ /dev/null @@ -1,172 +0,0 @@ -/* - * pgtsun4c.h: Sun4c specific pgtable.h defines and code. - * - * Copyright (C) 1995 David S. Miller ([email protected]) - */ -#ifndef _SPARC_PGTSUN4C_H -#define _SPARC_PGTSUN4C_H - -#include <asm/contregs.h> - -/* PMD_SHIFT determines the size of the area a second-level page table can map */ -#define SUN4C_PMD_SHIFT 22 - -/* PGDIR_SHIFT determines what a third-level page table entry can map */ -#define SUN4C_PGDIR_SHIFT 22 -#define SUN4C_PGDIR_SIZE (1UL << SUN4C_PGDIR_SHIFT) -#define SUN4C_PGDIR_MASK (~(SUN4C_PGDIR_SIZE-1)) -#define SUN4C_PGDIR_ALIGN(addr) (((addr)+SUN4C_PGDIR_SIZE-1)&SUN4C_PGDIR_MASK) - -/* To represent how the sun4c mmu really lays things out. */ -#define SUN4C_REAL_PGDIR_SHIFT 18 -#define SUN4C_REAL_PGDIR_SIZE (1UL << SUN4C_REAL_PGDIR_SHIFT) -#define SUN4C_REAL_PGDIR_MASK (~(SUN4C_REAL_PGDIR_SIZE-1)) -#define SUN4C_REAL_PGDIR_ALIGN(addr) (((addr)+SUN4C_REAL_PGDIR_SIZE-1)&SUN4C_REAL_PGDIR_MASK) - -/* 16 bit PFN on sun4c */ -#define SUN4C_PFN_MASK 0xffff - -/* Don't increase these unless the structures in sun4c.c are fixed */ -#define SUN4C_MAX_SEGMAPS 256 -#define SUN4C_MAX_CONTEXTS 16 - -/* - * To be efficient, and not have to worry about allocating such - * a huge pgd, we make the kernel sun4c tables each hold 1024 - * entries and the pgd similarly just like the i386 tables. - */ -#define SUN4C_PTRS_PER_PTE 1024 -#define SUN4C_PTRS_PER_PMD 1 -#define SUN4C_PTRS_PER_PGD 1024 - -/* - * Sparc SUN4C pte fields. - */ -#define _SUN4C_PAGE_VALID 0x80000000 -#define _SUN4C_PAGE_SILENT_READ 0x80000000 /* synonym */ -#define _SUN4C_PAGE_DIRTY 0x40000000 -#define _SUN4C_PAGE_SILENT_WRITE 0x40000000 /* synonym */ -#define _SUN4C_PAGE_PRIV 0x20000000 /* privileged page */ -#define _SUN4C_PAGE_NOCACHE 0x10000000 /* non-cacheable page */ -#define _SUN4C_PAGE_PRESENT 0x08000000 /* implemented in software */ -#define _SUN4C_PAGE_IO 0x04000000 /* I/O page */ -#define _SUN4C_PAGE_FILE 0x02000000 /* implemented in software */ -#define _SUN4C_PAGE_READ 0x00800000 /* implemented in software */ -#define _SUN4C_PAGE_WRITE 0x00400000 /* implemented in software */ -#define _SUN4C_PAGE_ACCESSED 0x00200000 /* implemented in software */ -#define _SUN4C_PAGE_MODIFIED 0x00100000 /* implemented in software */ - -#define _SUN4C_READABLE (_SUN4C_PAGE_READ|_SUN4C_PAGE_SILENT_READ|\ - _SUN4C_PAGE_ACCESSED) -#define _SUN4C_WRITEABLE (_SUN4C_PAGE_WRITE|_SUN4C_PAGE_SILENT_WRITE|\ - _SUN4C_PAGE_MODIFIED) - -#define _SUN4C_PAGE_CHG_MASK (0xffff|_SUN4C_PAGE_ACCESSED|_SUN4C_PAGE_MODIFIED) - -#define SUN4C_PAGE_NONE __pgprot(_SUN4C_PAGE_PRESENT) -#define SUN4C_PAGE_SHARED __pgprot(_SUN4C_PAGE_PRESENT|_SUN4C_READABLE|\ - _SUN4C_PAGE_WRITE) -#define SUN4C_PAGE_COPY __pgprot(_SUN4C_PAGE_PRESENT|_SUN4C_READABLE) -#define SUN4C_PAGE_READONLY __pgprot(_SUN4C_PAGE_PRESENT|_SUN4C_READABLE) -#define SUN4C_PAGE_KERNEL __pgprot(_SUN4C_READABLE|_SUN4C_WRITEABLE|\ - _SUN4C_PAGE_DIRTY|_SUN4C_PAGE_PRIV) - -/* SUN4C swap entry encoding - * - * We use 5 bits for the type and 19 for the offset. This gives us - * 32 swapfiles of 4GB each. Encoding looks like: - * - * RRRRRRRRooooooooooooooooooottttt - * fedcba9876543210fedcba9876543210 - * - * The top 8 bits are reserved for protection and status bits, especially - * FILE and PRESENT. - */ -#define SUN4C_SWP_TYPE_MASK 0x1f -#define SUN4C_SWP_OFF_MASK 0x7ffff -#define SUN4C_SWP_OFF_SHIFT 5 - -#ifndef __ASSEMBLY__ - -static inline unsigned long sun4c_get_synchronous_error(void) -{ - unsigned long sync_err; - - __asm__ __volatile__("lda [%1] %2, %0\n\t" : - "=r" (sync_err) : - "r" (AC_SYNC_ERR), "i" (ASI_CONTROL)); - return sync_err; -} - -static inline unsigned long sun4c_get_synchronous_address(void) -{ - unsigned long sync_addr; - - __asm__ __volatile__("lda [%1] %2, %0\n\t" : - "=r" (sync_addr) : - "r" (AC_SYNC_VA), "i" (ASI_CONTROL)); - return sync_addr; -} - -/* SUN4C pte, segmap, and context manipulation */ -static inline unsigned long sun4c_get_segmap(unsigned long addr) -{ - register unsigned long entry; - - __asm__ __volatile__("\n\tlduba [%1] %2, %0\n\t" : - "=r" (entry) : - "r" (addr), "i" (ASI_SEGMAP)); - - return entry; -} - -static inline void sun4c_put_segmap(unsigned long addr, unsigned long entry) -{ - - __asm__ __volatile__("\n\tstba %1, [%0] %2; nop; nop; nop;\n\t" : : - "r" (addr), "r" (entry), - "i" (ASI_SEGMAP) - : "memory"); -} - -static inline unsigned long sun4c_get_pte(unsigned long addr) -{ - register unsigned long entry; - - __asm__ __volatile__("\n\tlda [%1] %2, %0\n\t" : - "=r" (entry) : - "r" (addr), "i" (ASI_PTE)); - return entry; -} - -static inline void sun4c_put_pte(unsigned long addr, unsigned long entry) -{ - __asm__ __volatile__("\n\tsta %1, [%0] %2; nop; nop; nop;\n\t" : : - "r" (addr), - "r" ((entry & ~(_SUN4C_PAGE_PRESENT))), "i" (ASI_PTE) - : "memory"); -} - -static inline int sun4c_get_context(void) -{ - register int ctx; - - __asm__ __volatile__("\n\tlduba [%1] %2, %0\n\t" : - "=r" (ctx) : - "r" (AC_CONTEXT), "i" (ASI_CONTROL)); - - return ctx; -} - -static inline int sun4c_set_context(int ctx) -{ - __asm__ __volatile__("\n\tstba %0, [%1] %2; nop; nop; nop;\n\t" : : - "r" (ctx), "r" (AC_CONTEXT), "i" (ASI_CONTROL) - : "memory"); - - return ctx; -} - -#endif /* !(__ASSEMBLY__) */ - -#endif /* !(_SPARC_PGTSUN4C_H) */ diff --git a/arch/sparc/include/asm/processor_32.h b/arch/sparc/include/asm/processor_32.h index 09521c6a5edb..9cbd854fdfdd 100644 --- a/arch/sparc/include/asm/processor_32.h +++ b/arch/sparc/include/asm/processor_32.h @@ -16,7 +16,6 @@ #include <asm/ptrace.h> #include <asm/head.h> #include <asm/signal.h> -#include <asm/btfixup.h> #include <asm/page.h> /* diff --git a/arch/sparc/include/asm/setup.h b/arch/sparc/include/asm/setup.h index 00497abec996..8a83699a5507 100644 --- a/arch/sparc/include/asm/setup.h +++ b/arch/sparc/include/asm/setup.h @@ -20,10 +20,7 @@ extern char reboot_command[]; * Only sun4d + leon may have boot_cpu_id != 0 */ extern unsigned char boot_cpu_id; -extern unsigned char boot_cpu_id4; -extern unsigned long empty_bad_page; -extern unsigned long empty_bad_page_table; extern unsigned long empty_zero_page; extern int serial_console; diff --git a/arch/sparc/include/asm/shmparam_32.h b/arch/sparc/include/asm/shmparam_32.h index 59a1243c12f3..142825c8d3ac 100644 --- a/arch/sparc/include/asm/shmparam_32.h +++ b/arch/sparc/include/asm/shmparam_32.h @@ -4,8 +4,6 @@ #define __ARCH_FORCE_SHMLBA 1 extern int vac_cache_size; -#define SHMLBA (vac_cache_size ? vac_cache_size : \ - (sparc_cpu_model == sun4c ? (64 * 1024) : \ - (sparc_cpu_model == sun4 ? (128 * 1024) : PAGE_SIZE))) +#define SHMLBA (vac_cache_size ? vac_cache_size : PAGE_SIZE) #endif /* _ASMSPARC_SHMPARAM_H */ diff --git a/arch/sparc/include/asm/smp_32.h b/arch/sparc/include/asm/smp_32.h index 01c51c704341..b73da3c5f10a 100644 --- a/arch/sparc/include/asm/smp_32.h +++ b/arch/sparc/include/asm/smp_32.h @@ -8,7 +8,6 @@ #include <linux/threads.h> #include <asm/head.h> -#include <asm/btfixup.h> #ifndef __ASSEMBLY__ @@ -58,104 +57,53 @@ struct seq_file; void smp_bogo(struct seq_file *); void smp_info(struct seq_file *); -BTFIXUPDEF_CALL(void, smp_cross_call, smpfunc_t, cpumask_t, unsigned long, unsigned long, unsigned long, unsigned long) -BTFIXUPDEF_CALL(int, __hard_smp_processor_id, void) -BTFIXUPDEF_CALL(void, smp_ipi_resched, int); -BTFIXUPDEF_CALL(void, smp_ipi_single, int); -BTFIXUPDEF_CALL(void, smp_ipi_mask_one, int); -BTFIXUPDEF_BLACKBOX(hard_smp_processor_id) -BTFIXUPDEF_BLACKBOX(load_current) - -#define smp_cross_call(func,mask,arg1,arg2,arg3,arg4) BTFIXUP_CALL(smp_cross_call)(func,mask,arg1,arg2,arg3,arg4) +struct sparc32_ipi_ops { + void (*cross_call)(smpfunc_t func, cpumask_t mask, unsigned long arg1, + unsigned long arg2, unsigned long arg3, + unsigned long arg4); + void (*resched)(int cpu); + void (*single)(int cpu); + void (*mask_one)(int cpu); +}; +extern const struct sparc32_ipi_ops *sparc32_ipi_ops; + +static inline void xc0(smpfunc_t func) +{ + sparc32_ipi_ops->cross_call(func, *cpu_online_mask, 0, 0, 0, 0); +} -static inline void xc0(smpfunc_t func) { smp_cross_call(func, *cpu_online_mask, 0, 0, 0, 0); } static inline void xc1(smpfunc_t func, unsigned long arg1) -{ smp_cross_call(func, *cpu_online_mask, arg1, 0, 0, 0); } -static inline void xc2(smpfunc_t func, unsigned long arg1, unsigned long arg2) -{ smp_cross_call(func, *cpu_online_mask, arg1, arg2, 0, 0); } -static inline void xc3(smpfunc_t func, unsigned long arg1, unsigned long arg2, - unsigned long arg3) -{ smp_cross_call(func, *cpu_online_mask, arg1, arg2, arg3, 0); } -static inline void xc4(smpfunc_t func, unsigned long arg1, unsigned long arg2, - unsigned long arg3, unsigned long arg4) -{ smp_cross_call(func, *cpu_online_mask, arg1, arg2, arg3, arg4); } - -extern void arch_send_call_function_single_ipi(int cpu); -extern void arch_send_call_function_ipi_mask(const struct cpumask *mask); - -static inline int cpu_logical_map(int cpu) { - return cpu; + sparc32_ipi_ops->cross_call(func, *cpu_online_mask, arg1, 0, 0, 0); } - -static inline int hard_smp4m_processor_id(void) +static inline void xc2(smpfunc_t func, unsigned long arg1, unsigned long arg2) { - int cpuid; - - __asm__ __volatile__("rd %%tbr, %0\n\t" - "srl %0, 12, %0\n\t" - "and %0, 3, %0\n\t" : - "=&r" (cpuid)); - return cpuid; + sparc32_ipi_ops->cross_call(func, *cpu_online_mask, arg1, arg2, 0, 0); } -static inline int hard_smp4d_processor_id(void) +static inline void xc3(smpfunc_t func, unsigned long arg1, unsigned long arg2, + unsigned long arg3) { - int cpuid; - - __asm__ __volatile__("lda [%%g0] %1, %0\n\t" : - "=&r" (cpuid) : "i" (ASI_M_VIKING_TMP1)); - return cpuid; + sparc32_ipi_ops->cross_call(func, *cpu_online_mask, + arg1, arg2, arg3, 0); } -extern inline int hard_smpleon_processor_id(void) +static inline void xc4(smpfunc_t func, unsigned long arg1, unsigned long arg2, + unsigned long arg3, unsigned long arg4) { - int cpuid; - __asm__ __volatile__("rd %%asr17,%0\n\t" - "srl %0,28,%0" : - "=&r" (cpuid) : ); - return cpuid; + sparc32_ipi_ops->cross_call(func, *cpu_online_mask, + arg1, arg2, arg3, arg4); } -#ifndef MODULE -static inline int hard_smp_processor_id(void) +extern void arch_send_call_function_single_ipi(int cpu); +extern void arch_send_call_function_ipi_mask(const struct cpumask *mask); + +static inline int cpu_logical_map(int cpu) { - int cpuid; - - /* Black box - sun4m - __asm__ __volatile__("rd %%tbr, %0\n\t" - "srl %0, 12, %0\n\t" - "and %0, 3, %0\n\t" : - "=&r" (cpuid)); - - sun4d - __asm__ __volatile__("lda [%g0] ASI_M_VIKING_TMP1, %0\n\t" - "nop; nop" : - "=&r" (cpuid)); - - leon - __asm__ __volatile__( "rd %asr17, %0\n\t" - "srl %0, 0x1c, %0\n\t" - "nop\n\t" : - "=&r" (cpuid)); - See btfixup.h and btfixupprep.c to understand how a blackbox works. - */ - __asm__ __volatile__("sethi %%hi(___b_hard_smp_processor_id), %0\n\t" - "sethi %%hi(boot_cpu_id), %0\n\t" - "ldub [%0 + %%lo(boot_cpu_id)], %0\n\t" : - "=&r" (cpuid)); - return cpuid; + return cpu; } -#else -static inline int hard_smp_processor_id(void) -{ - int cpuid; - __asm__ __volatile__("mov %%o7, %%g1\n\t" - "call ___f___hard_smp_processor_id\n\t" - " nop\n\t" - "mov %%g2, %0\n\t" : "=r"(cpuid) : : "g1", "g2"); - return cpuid; -} -#endif +extern int hard_smp_processor_id(void); #define raw_smp_processor_id() (current_thread_info()->cpu) diff --git a/arch/sparc/include/asm/smpprim.h b/arch/sparc/include/asm/smpprim.h deleted file mode 100644 index eb849d862c64..000000000000 --- a/arch/sparc/include/asm/smpprim.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * smpprim.h: SMP locking primitives on the Sparc - * - * God knows we won't be actually using this code for some time - * but I thought I'd write it since I knew how. - * - * Copyright (C) 1995 David S. Miller ([email protected]) - */ - -#ifndef __SPARC_SMPPRIM_H -#define __SPARC_SMPPRIM_H - -/* Test and set the unsigned byte at ADDR to 1. Returns the previous - * value. On the Sparc we use the ldstub instruction since it is - * atomic. - */ - -static inline __volatile__ char test_and_set(void *addr) -{ - char state = 0; - - __asm__ __volatile__("ldstub [%0], %1 ! test_and_set\n\t" - "=r" (addr), "=r" (state) : - "0" (addr), "1" (state) : "memory"); - - return state; -} - -/* Initialize a spin-lock. */ -static inline __volatile__ smp_initlock(void *spinlock) -{ - /* Unset the lock. */ - *((unsigned char *) spinlock) = 0; - - return; -} - -/* This routine spins until it acquires the lock at ADDR. */ -static inline __volatile__ smp_lock(void *addr) -{ - while(test_and_set(addr) == 0xff) - ; - - /* We now have the lock */ - return; -} - -/* This routine releases the lock at ADDR. */ -static inline __volatile__ smp_unlock(void *addr) -{ - *((unsigned char *) addr) = 0; -} - -#endif /* !(__SPARC_SMPPRIM_H) */ diff --git a/arch/sparc/include/asm/string_32.h b/arch/sparc/include/asm/string_32.h index edf196ee4ef8..12f67857152e 100644 --- a/arch/sparc/include/asm/string_32.h +++ b/arch/sparc/include/asm/string_32.h @@ -61,68 +61,7 @@ extern int memcmp(const void *,const void *,__kernel_size_t); extern __kernel_size_t strlen(const char *); #define __HAVE_ARCH_STRNCMP - -extern int __strncmp(const char *, const char *, __kernel_size_t); - -static inline int __constant_strncmp(const char *src, const char *dest, __kernel_size_t count) -{ - register int retval; - switch(count) { - case 0: return 0; - case 1: return (src[0] - dest[0]); - case 2: retval = (src[0] - dest[0]); - if(!retval && src[0]) - retval = (src[1] - dest[1]); - return retval; - case 3: retval = (src[0] - dest[0]); - if(!retval && src[0]) { - retval = (src[1] - dest[1]); - if(!retval && src[1]) - retval = (src[2] - dest[2]); - } - return retval; - case 4: retval = (src[0] - dest[0]); - if(!retval && src[0]) { - retval = (src[1] - dest[1]); - if(!retval && src[1]) { - retval = (src[2] - dest[2]); - if (!retval && src[2]) - retval = (src[3] - dest[3]); - } - } - return retval; - case 5: retval = (src[0] - dest[0]); - if(!retval && src[0]) { - retval = (src[1] - dest[1]); - if(!retval && src[1]) { - retval = (src[2] - dest[2]); - if (!retval && src[2]) { - retval = (src[3] - dest[3]); - if (!retval && src[3]) - retval = (src[4] - dest[4]); - } - } - } - return retval; - default: - retval = (src[0] - dest[0]); - if(!retval && src[0]) { - retval = (src[1] - dest[1]); - if(!retval && src[1]) { - retval = (src[2] - dest[2]); - if(!retval && src[2]) - retval = __strncmp(src+3,dest+3,count-3); - } - } - return retval; - } -} - -#undef strncmp -#define strncmp(__arg0, __arg1, __arg2) \ -(__builtin_constant_p(__arg2) ? \ - __constant_strncmp(__arg0, __arg1, __arg2) : \ - __strncmp(__arg0, __arg1, __arg2)) +extern int strncmp(const char *, const char *, __kernel_size_t); #endif /* !EXPORT_SYMTAB_STROPS */ diff --git a/arch/sparc/include/asm/sysen.h b/arch/sparc/include/asm/sysen.h deleted file mode 100644 index 6af34abde6e7..000000000000 --- a/arch/sparc/include/asm/sysen.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * sysen.h: Bit fields within the "System Enable" register accessed via - * the ASI_CONTROL address space at address AC_SYSENABLE. - * - * Copyright (C) 1994 David S. Miller ([email protected]) - */ - -#ifndef _SPARC_SYSEN_H -#define _SPARC_SYSEN_H - -#define SENABLE_DVMA 0x20 /* enable dvma transfers */ -#define SENABLE_CACHE 0x10 /* enable VAC cache */ -#define SENABLE_RESET 0x04 /* reset whole machine, danger Will Robinson */ - -#endif /* _SPARC_SYSEN_H */ diff --git a/arch/sparc/include/asm/thread_info_32.h b/arch/sparc/include/asm/thread_info_32.h index c2a1080cdd3b..cd0b2dc8fab9 100644 --- a/arch/sparc/include/asm/thread_info_32.h +++ b/arch/sparc/include/asm/thread_info_32.h @@ -15,7 +15,6 @@ #ifndef __ASSEMBLY__ -#include <asm/btfixup.h> #include <asm/ptrace.h> #include <asm/page.h> @@ -82,11 +81,8 @@ register struct thread_info *current_thread_info_reg asm("g6"); #define __HAVE_ARCH_THREAD_INFO_ALLOCATOR -BTFIXUPDEF_CALL(struct thread_info *, alloc_thread_info_node, int) -#define alloc_thread_info_node(tsk, node) BTFIXUP_CALL(alloc_thread_info_node)(node) - -BTFIXUPDEF_CALL(void, free_thread_info, struct thread_info *) -#define free_thread_info(ti) BTFIXUP_CALL(free_thread_info)(ti) +struct thread_info * alloc_thread_info_node(struct task_struct *tsk, int node); +void free_thread_info(struct thread_info *); #endif /* __ASSEMBLY__ */ diff --git a/arch/sparc/include/asm/timer_32.h b/arch/sparc/include/asm/timer_32.h index 1a91e11dd104..72f40a546de3 100644 --- a/arch/sparc/include/asm/timer_32.h +++ b/arch/sparc/include/asm/timer_32.h @@ -8,14 +8,37 @@ #ifndef _SPARC_TIMER_H #define _SPARC_TIMER_H +#include <linux/clocksource.h> +#include <linux/irqreturn.h> + +#include <asm-generic/percpu.h> + #include <asm/cpu_type.h> /* For SUN4M_NCPUS */ -#include <asm/btfixup.h> + +#define SBUS_CLOCK_RATE 2000000 /* 2MHz */ +#define TIMER_VALUE_SHIFT 9 +#define TIMER_VALUE_MASK 0x3fffff +#define TIMER_LIMIT_BIT (1 << 31) /* Bit 31 in Counter-Timer register */ + +/* The counter timer register has the value offset by 9 bits. + * From sun4m manual: + * When a counter reaches the value in the corresponding limit register, + * the Limit bit is set and the counter is set to 500 nS (i.e. 0x00000200). + * + * To compensate for this add one to the value. + */ +static inline unsigned int timer_value(unsigned int value) +{ + return (value + 1) << TIMER_VALUE_SHIFT; +} extern __volatile__ unsigned int *master_l10_counter; -/* FIXME: Make do_[gs]ettimeofday btfixup calls */ -struct timespec; -BTFIXUPDEF_CALL(int, bus_do_settimeofday, struct timespec *tv) -#define bus_do_settimeofday(tv) BTFIXUP_CALL(bus_do_settimeofday)(tv) +extern irqreturn_t notrace timer_interrupt(int dummy, void *dev_id); + +#ifdef CONFIG_SMP +DECLARE_PER_CPU(struct clock_event_device, sparc32_clockevent); +extern void register_percpu_ce(int cpu); +#endif #endif /* !(_SPARC_TIMER_H) */ diff --git a/arch/sparc/include/asm/timex_32.h b/arch/sparc/include/asm/timex_32.h index a254750e4c03..b6ccdb0d6f7d 100644 --- a/arch/sparc/include/asm/timex_32.h +++ b/arch/sparc/include/asm/timex_32.h @@ -12,5 +12,4 @@ typedef unsigned long cycles_t; #define get_cycles() (0) -extern u32 (*do_arch_gettimeoffset)(void); #endif diff --git a/arch/sparc/include/asm/tlbflush_32.h b/arch/sparc/include/asm/tlbflush_32.h index fe0a71abc9bb..a5c4142130f5 100644 --- a/arch/sparc/include/asm/tlbflush_32.h +++ b/arch/sparc/include/asm/tlbflush_32.h @@ -1,52 +1,16 @@ #ifndef _SPARC_TLBFLUSH_H #define _SPARC_TLBFLUSH_H -#include <linux/mm.h> -// #include <asm/processor.h> - -/* - * TLB flushing: - * - * - flush_tlb() flushes the current mm struct TLBs XXX Exists? - * - flush_tlb_all() flushes all processes TLBs - * - flush_tlb_mm(mm) flushes the specified mm context TLB's - * - flush_tlb_page(vma, vmaddr) flushes one page - * - flush_tlb_range(vma, start, end) flushes a range of pages - * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages - */ - -#ifdef CONFIG_SMP - -BTFIXUPDEF_CALL(void, local_flush_tlb_all, void) -BTFIXUPDEF_CALL(void, local_flush_tlb_mm, struct mm_struct *) -BTFIXUPDEF_CALL(void, local_flush_tlb_range, struct vm_area_struct *, unsigned long, unsigned long) -BTFIXUPDEF_CALL(void, local_flush_tlb_page, struct vm_area_struct *, unsigned long) - -#define local_flush_tlb_all() BTFIXUP_CALL(local_flush_tlb_all)() -#define local_flush_tlb_mm(mm) BTFIXUP_CALL(local_flush_tlb_mm)(mm) -#define local_flush_tlb_range(vma,start,end) BTFIXUP_CALL(local_flush_tlb_range)(vma,start,end) -#define local_flush_tlb_page(vma,addr) BTFIXUP_CALL(local_flush_tlb_page)(vma,addr) - -extern void smp_flush_tlb_all(void); -extern void smp_flush_tlb_mm(struct mm_struct *mm); -extern void smp_flush_tlb_range(struct vm_area_struct *vma, - unsigned long start, - unsigned long end); -extern void smp_flush_tlb_page(struct vm_area_struct *mm, unsigned long page); - -#endif /* CONFIG_SMP */ - -BTFIXUPDEF_CALL(void, flush_tlb_all, void) -BTFIXUPDEF_CALL(void, flush_tlb_mm, struct mm_struct *) -BTFIXUPDEF_CALL(void, flush_tlb_range, struct vm_area_struct *, unsigned long, unsigned long) -BTFIXUPDEF_CALL(void, flush_tlb_page, struct vm_area_struct *, unsigned long) - -#define flush_tlb_all() BTFIXUP_CALL(flush_tlb_all)() -#define flush_tlb_mm(mm) BTFIXUP_CALL(flush_tlb_mm)(mm) -#define flush_tlb_range(vma,start,end) BTFIXUP_CALL(flush_tlb_range)(vma,start,end) -#define flush_tlb_page(vma,addr) BTFIXUP_CALL(flush_tlb_page)(vma,addr) - -// #define flush_tlb() flush_tlb_mm(current->active_mm) /* XXX Sure? */ +#include <asm/cachetlb_32.h> + +#define flush_tlb_all() \ + sparc32_cachetlb_ops->tlb_all() +#define flush_tlb_mm(mm) \ + sparc32_cachetlb_ops->tlb_mm(mm) +#define flush_tlb_range(vma, start, end) \ + sparc32_cachetlb_ops->tlb_range(vma, start, end) +#define flush_tlb_page(vma, addr) \ + sparc32_cachetlb_ops->tlb_page(vma, addr) /* * This is a kludge, until I know better. --zaitcev XXX diff --git a/arch/sparc/include/asm/uaccess_32.h b/arch/sparc/include/asm/uaccess_32.h index 8303ac481034..d50c310f5d38 100644 --- a/arch/sparc/include/asm/uaccess_32.h +++ b/arch/sparc/include/asm/uaccess_32.h @@ -12,7 +12,6 @@ #include <linux/sched.h> #include <linux/string.h> #include <linux/errno.h> -#include <asm/vac-ops.h> #endif #ifndef __ASSEMBLY__ diff --git a/arch/sparc/include/asm/vac-ops.h b/arch/sparc/include/asm/vac-ops.h deleted file mode 100644 index a63e88ef0426..000000000000 --- a/arch/sparc/include/asm/vac-ops.h +++ /dev/null @@ -1,127 +0,0 @@ -#ifndef _SPARC_VAC_OPS_H -#define _SPARC_VAC_OPS_H - -/* vac-ops.h: Inline assembly routines to do operations on the Sparc - * VAC (virtual address cache) for the sun4c. - * - * Copyright (C) 1994, David S. Miller ([email protected]) - */ - -#include <asm/sysen.h> -#include <asm/contregs.h> -#include <asm/asi.h> - -/* The SUN4C models have a virtually addressed write-through - * cache. - * - * The cache tags are directly accessible through an ASI and - * each have the form: - * - * ------------------------------------------------------------ - * | MBZ | CONTEXT | WRITE | PRIV | VALID | MBZ | TagID | MBZ | - * ------------------------------------------------------------ - * 31 25 24 22 21 20 19 18 16 15 2 1 0 - * - * MBZ: These bits are either unused and/or reserved and should - * be written as zeroes. - * - * CONTEXT: Records the context to which this cache line belongs. - * - * WRITE: A copy of the writable bit from the mmu pte access bits. - * - * PRIV: A copy of the privileged bit from the pte access bits. - * - * VALID: If set, this line is valid, else invalid. - * - * TagID: Fourteen bits of tag ID. - * - * Every virtual address is seen by the cache like this: - * - * ---------------------------------------- - * | RESV | TagID | LINE | BYTE-in-LINE | - * ---------------------------------------- - * 31 30 29 16 15 4 3 0 - * - * RESV: Unused/reserved. - * - * TagID: Used to match the Tag-ID in that vac tags. - * - * LINE: Which line within the cache - * - * BYTE-in-LINE: Which byte within the cache line. - */ - -/* Sun4c VAC Tags */ -#define S4CVACTAG_CID 0x01c00000 -#define S4CVACTAG_W 0x00200000 -#define S4CVACTAG_P 0x00100000 -#define S4CVACTAG_V 0x00080000 -#define S4CVACTAG_TID 0x0000fffc - -/* Sun4c VAC Virtual Address */ -/* These aren't used, why bother? (Anton) */ -#if 0 -#define S4CVACVA_TID 0x3fff0000 -#define S4CVACVA_LINE 0x0000fff0 -#define S4CVACVA_BIL 0x0000000f -#endif - -/* The indexing of cache lines creates a problem. Because the line - * field of a virtual address extends past the page offset within - * the virtual address it is possible to have what are called - * 'bad aliases' which will create inconsistencies. So we must make - * sure that within a context that if a physical page is mapped - * more than once, that 'extra' line bits are the same. If this is - * not the case, and thus is a 'bad alias' we must turn off the - * cacheable bit in the pte's of all such pages. - */ - -#define S4CVAC_BADBITS 0x0000f000 - -/* The following is true if vaddr1 and vaddr2 would cause - * a 'bad alias'. - */ -#define S4CVAC_BADALIAS(vaddr1, vaddr2) \ - ((((unsigned long) (vaddr1)) ^ ((unsigned long) (vaddr2))) & \ - (S4CVAC_BADBITS)) - -/* The following structure describes the characteristics of a sun4c - * VAC as probed from the prom during boot time. - */ -struct sun4c_vac_props { - unsigned int num_bytes; /* Size of the cache */ - unsigned int do_hwflushes; /* Hardware flushing available? */ - unsigned int linesize; /* Size of each line in bytes */ - unsigned int log2lsize; /* log2(linesize) */ - unsigned int on; /* VAC is enabled */ -}; - -extern struct sun4c_vac_props sun4c_vacinfo; - -/* sun4c_enable_vac() enables the sun4c virtual address cache. */ -static inline void sun4c_enable_vac(void) -{ - __asm__ __volatile__("lduba [%0] %1, %%g1\n\t" - "or %%g1, %2, %%g1\n\t" - "stba %%g1, [%0] %1\n\t" - : /* no outputs */ - : "r" ((unsigned int) AC_SENABLE), - "i" (ASI_CONTROL), "i" (SENABLE_CACHE) - : "g1", "memory"); - sun4c_vacinfo.on = 1; -} - -/* sun4c_disable_vac() disables the virtual address cache. */ -static inline void sun4c_disable_vac(void) -{ - __asm__ __volatile__("lduba [%0] %1, %%g1\n\t" - "andn %%g1, %2, %%g1\n\t" - "stba %%g1, [%0] %1\n\t" - : /* no outputs */ - : "r" ((unsigned int) AC_SENABLE), - "i" (ASI_CONTROL), "i" (SENABLE_CACHE) - : "g1", "memory"); - sun4c_vacinfo.on = 0; -} - -#endif /* !(_SPARC_VAC_OPS_H) */ diff --git a/arch/sparc/include/asm/vaddrs.h b/arch/sparc/include/asm/vaddrs.h index 541e13755cec..da6535d88a72 100644 --- a/arch/sparc/include/asm/vaddrs.h +++ b/arch/sparc/include/asm/vaddrs.h @@ -34,22 +34,6 @@ #define IOBASE_VADDR 0xfe000000 #define IOBASE_END 0xfe600000 -/* - * On the sun4/4c we need a place - * to reliably map locked down kernel data. This includes the - * task_struct and kernel stack pages of each process plus the - * scsi buffers during dvma IO transfers, also the floppy buffers - * during pseudo dma which runs with traps off (no faults allowed). - * Some quick calculations yield: - * NR_TASKS <512> * (3 * PAGE_SIZE) == 0x600000 - * Subtract this from 0xc00000 and you get 0x927C0 of vm left - * over to map SCSI dvma + floppy pseudo-dma buffers. So be - * careful if you change NR_TASKS or else there won't be enough - * room for it all. - */ -#define SUN4C_LOCK_VADDR 0xff000000 -#define SUN4C_LOCK_END 0xffc00000 - #define KADB_DEBUGGER_BEGVM 0xffc00000 /* Where kern debugger is in virt-mem */ #define KADB_DEBUGGER_ENDVM 0xffd00000 #define DEBUG_FIRSTVADDR KADB_DEBUGGER_BEGVM diff --git a/arch/sparc/include/asm/winmacro.h b/arch/sparc/include/asm/winmacro.h index a9be04b0d049..9b7b21764cde 100644 --- a/arch/sparc/include/asm/winmacro.h +++ b/arch/sparc/include/asm/winmacro.h @@ -103,37 +103,24 @@ st %scratch, [%cur_reg + TI_W_SAVED]; #ifdef CONFIG_SMP -/* Results of LOAD_CURRENT() after BTFIXUP for SUN4M, SUN4D & LEON (comments) */ -#define LOAD_CURRENT4M(dest_reg, idreg) \ - rd %tbr, %idreg; \ - sethi %hi(current_set), %dest_reg; \ - srl %idreg, 10, %idreg; \ - or %dest_reg, %lo(current_set), %dest_reg; \ - and %idreg, 0xc, %idreg; \ - ld [%idreg + %dest_reg], %dest_reg; - -#define LOAD_CURRENT4D(dest_reg, idreg) \ - lda [%g0] ASI_M_VIKING_TMP1, %idreg; \ - sethi %hi(C_LABEL(current_set)), %dest_reg; \ - sll %idreg, 2, %idreg; \ - or %dest_reg, %lo(C_LABEL(current_set)), %dest_reg; \ - ld [%idreg + %dest_reg], %dest_reg; - -#define LOAD_CURRENT_LEON(dest_reg, idreg) \ - rd %asr17, %idreg; \ - sethi %hi(current_set), %dest_reg; \ - srl %idreg, 0x1c, %idreg; \ - or %dest_reg, %lo(current_set), %dest_reg; \ - sll %idreg, 0x2, %idreg; \ - ld [%idreg + %dest_reg], %dest_reg; - -/* Blackbox - take care with this... - check smp4m and smp4d before changing this. */ -#define LOAD_CURRENT(dest_reg, idreg) \ - sethi %hi(___b_load_current), %idreg; \ - sethi %hi(current_set), %dest_reg; \ - sethi %hi(boot_cpu_id4), %idreg; \ - or %dest_reg, %lo(current_set), %dest_reg; \ - ldub [%idreg + %lo(boot_cpu_id4)], %idreg; \ +#define LOAD_CURRENT(dest_reg, idreg) \ +661: rd %tbr, %idreg; \ + srl %idreg, 10, %idreg; \ + and %idreg, 0xc, %idreg; \ + .section .cpuid_patch, "ax"; \ + /* Instruction location. */ \ + .word 661b; \ + /* SUN4D implementation. */ \ + lda [%g0] ASI_M_VIKING_TMP1, %idreg; \ + sll %idreg, 2, %idreg; \ + nop; \ + /* LEON implementation. */ \ + rd %asr17, %idreg; \ + srl %idreg, 0x1c, %idreg; \ + sll %idreg, 0x02, %idreg; \ + .previous; \ + sethi %hi(current_set), %dest_reg; \ + or %dest_reg, %lo(current_set), %dest_reg;\ ld [%idreg + %dest_reg], %dest_reg; #else #define LOAD_CURRENT(dest_reg, idreg) \ diff --git a/arch/sparc/kernel/Makefile b/arch/sparc/kernel/Makefile index cb85458f89d2..c19dd022b9cb 100644 --- a/arch/sparc/kernel/Makefile +++ b/arch/sparc/kernel/Makefile @@ -28,7 +28,7 @@ obj-y += traps_$(BITS).o # IRQ obj-y += irq_$(BITS).o -obj-$(CONFIG_SPARC32) += sun4m_irq.o sun4c_irq.o sun4d_irq.o +obj-$(CONFIG_SPARC32) += sun4m_irq.o sun4d_irq.o obj-y += process_$(BITS).o obj-y += signal_$(BITS).o @@ -46,7 +46,6 @@ obj-$(CONFIG_SPARC32) += tadpole.o obj-y += ptrace_$(BITS).o obj-y += unaligned_$(BITS).o obj-y += una_asm_$(BITS).o -obj-$(CONFIG_SPARC32) += muldiv.o obj-y += prom_common.o obj-y += prom_$(BITS).o obj-y += of_device_common.o diff --git a/arch/sparc/kernel/auxio_32.c b/arch/sparc/kernel/auxio_32.c index 56d0f52c3e62..e20cc55fb768 100644 --- a/arch/sparc/kernel/auxio_32.c +++ b/arch/sparc/kernel/auxio_32.c @@ -32,7 +32,6 @@ void __init auxio_probe(void) switch (sparc_cpu_model) { case sparc_leon: case sun4d: - case sun4: return; default: break; @@ -65,9 +64,8 @@ void __init auxio_probe(void) r.start = auxregs[0].phys_addr; r.end = auxregs[0].phys_addr + auxregs[0].reg_size - 1; auxio_register = of_ioremap(&r, 0, auxregs[0].reg_size, "auxio"); - /* Fix the address on sun4m and sun4c. */ - if((((unsigned long) auxregs[0].phys_addr) & 3) == 3 || - sparc_cpu_model == sun4c) + /* Fix the address on sun4m. */ + if ((((unsigned long) auxregs[0].phys_addr) & 3) == 3) auxio_register += (3 - ((unsigned long)auxio_register & 3)); set_auxio(AUXIO_LED, 0); @@ -86,12 +84,7 @@ void set_auxio(unsigned char bits_on, unsigned char bits_off) unsigned char regval; unsigned long flags; spin_lock_irqsave(&auxio_lock, flags); - switch(sparc_cpu_model) { - case sun4c: - regval = sbus_readb(auxio_register); - sbus_writeb(((regval | bits_on) & ~bits_off) | AUXIO_ORMEIN, - auxio_register); - break; + switch (sparc_cpu_model) { case sun4m: if(!auxio_register) break; /* VME chassis sun4m, no auxio. */ diff --git a/arch/sparc/kernel/central.c b/arch/sparc/kernel/central.c index 38d48a59879c..9708851a8b9f 100644 --- a/arch/sparc/kernel/central.c +++ b/arch/sparc/kernel/central.c @@ -269,4 +269,4 @@ static int __init sunfire_init(void) return 0; } -subsys_initcall(sunfire_init); +fs_initcall(sunfire_init); diff --git a/arch/sparc/kernel/devices.c b/arch/sparc/kernel/devices.c index 6b2f56a6f8af..3d465e87f7e2 100644 --- a/arch/sparc/kernel/devices.c +++ b/arch/sparc/kernel/devices.c @@ -21,7 +21,6 @@ #include <asm/cpu_type.h> extern void clock_stop_probe(void); /* tadpole.c */ -extern void sun4c_probe_memerr_reg(void); static char *cpu_mid_prop(void) { @@ -139,7 +138,4 @@ void __init device_scan(void) auxio_power_probe(); } clock_stop_probe(); - - if (ARCH_SUN4C) - sun4c_probe_memerr_reg(); } diff --git a/arch/sparc/kernel/ds.c b/arch/sparc/kernel/ds.c index fea13c7b1aee..f09257c86107 100644 --- a/arch/sparc/kernel/ds.c +++ b/arch/sparc/kernel/ds.c @@ -868,7 +868,7 @@ void ldom_power_off(void) static void ds_conn_reset(struct ds_info *dp) { - printk(KERN_ERR "ds-%llu: ds_conn_reset() from %p\n", + printk(KERN_ERR "ds-%llu: ds_conn_reset() from %pf\n", dp->id, __builtin_return_address(0)); } @@ -1264,4 +1264,4 @@ static int __init ds_init(void) return vio_register_driver(&ds_driver); } -subsys_initcall(ds_init); +fs_initcall(ds_init); diff --git a/arch/sparc/kernel/entry.S b/arch/sparc/kernel/entry.S index f445e98463e6..2dbe1806e530 100644 --- a/arch/sparc/kernel/entry.S +++ b/arch/sparc/kernel/entry.S @@ -7,6 +7,7 @@ * Copyright (C) 1997 Anton Blanchard ([email protected]) */ +#include <linux/linkage.h> #include <linux/errno.h> #include <asm/head.h> @@ -17,10 +18,8 @@ #include <asm/asm-offsets.h> #include <asm/psr.h> #include <asm/vaddrs.h> -#include <asm/memreg.h> #include <asm/page.h> #include <asm/pgtable.h> -#include <asm/pgtsun4c.h> #include <asm/winmacro.h> #include <asm/signal.h> #include <asm/obio.h> @@ -125,22 +124,11 @@ floppy_tdone: set auxio_register, %l7 ld [%l7], %l7 - set sparc_cpu_model, %l5 - ld [%l5], %l5 - subcc %l5, 1, %g0 /* enum { sun4c = 1 }; */ - be 1f - ldub [%l7], %l5 + ldub [%l7], %l5 or %l5, 0xc2, %l5 stb %l5, [%l7] andn %l5, 0x02, %l5 - b 2f - nop - -1: - or %l5, 0xf4, %l5 - stb %l5, [%l7] - andn %l5, 0x04, %l5 2: /* Kill some time so the bits set */ @@ -266,6 +254,11 @@ smp4m_ticker: WRITE_PAUSE RESTORE_ALL +#define GET_PROCESSOR4M_ID(reg) \ + rd %tbr, %reg; \ + srl %reg, 12, %reg; \ + and %reg, 3, %reg; + /* Here is where we check for possible SMP IPI passed to us * on some level other than 15 which is the NMI and only used * for cross calls. That has a separate entry point below. @@ -328,7 +321,7 @@ linux_trap_ipi15_sun4m: ld [%o5 + %o0], %o5 ld [%o5 + 0x00], %o3 ! sun4m_irq_percpu[cpu]->pending andcc %o3, %o2, %g0 - be 1f ! Must be an NMI async memory error + be sun4m_nmi_error ! Must be an NMI async memory error st %o2, [%o5 + 0x04] ! sun4m_irq_percpu[cpu]->clear=0x80000000 WRITE_PAUSE ld [%o5 + 0x00], %g0 ! sun4m_irq_percpu[cpu]->pending @@ -342,27 +335,6 @@ linux_trap_ipi15_sun4m: nop b ret_trap_lockless_ipi clr %l6 -1: - /* NMI async memory error handling. */ - sethi %hi(0x80000000), %l4 - sethi %hi(sun4m_irq_global), %o5 - ld [%o5 + %lo(sun4m_irq_global)], %l5 - st %l4, [%l5 + 0x0c] ! sun4m_irq_global->mask_set=0x80000000 - WRITE_PAUSE - ld [%l5 + 0x00], %g0 ! sun4m_irq_global->pending - WRITE_PAUSE - or %l0, PSR_PIL, %l4 - wr %l4, 0x0, %psr - WRITE_PAUSE - wr %l4, PSR_ET, %psr - WRITE_PAUSE - call sun4m_nmi - nop - st %l4, [%l5 + 0x08] ! sun4m_irq_global->mask_clear=0x80000000 - WRITE_PAUSE - ld [%l5 + 0x00], %g0 ! sun4m_irq_global->pending - WRITE_PAUSE - RESTORE_ALL .globl smp4d_ticker /* SMP per-cpu ticker interrupts are handled specially. */ @@ -760,326 +732,37 @@ setcc_trap_handler: jmp %l2 ! advance over trap instruction rett %l2 + 0x4 ! like this... - .align 4 - .globl linux_trap_nmi_sun4c -linux_trap_nmi_sun4c: - SAVE_ALL - - /* Ugh, we need to clear the IRQ line. This is now - * a very sun4c specific trap handler... - */ - sethi %hi(interrupt_enable), %l5 - ld [%l5 + %lo(interrupt_enable)], %l5 - ldub [%l5], %l6 - andn %l6, INTS_ENAB, %l6 - stb %l6, [%l5] - - /* Now it is safe to re-enable traps without recursion. */ - or %l0, PSR_PIL, %l0 - wr %l0, PSR_ET, %psr +sun4m_nmi_error: + /* NMI async memory error handling. */ + sethi %hi(0x80000000), %l4 + sethi %hi(sun4m_irq_global), %o5 + ld [%o5 + %lo(sun4m_irq_global)], %l5 + st %l4, [%l5 + 0x0c] ! sun4m_irq_global->mask_set=0x80000000 WRITE_PAUSE - - /* Now call the c-code with the pt_regs frame ptr and the - * memory error registers as arguments. The ordering chosen - * here is due to unlatching semantics. - */ - sethi %hi(AC_SYNC_ERR), %o0 - add %o0, 0x4, %o0 - lda [%o0] ASI_CONTROL, %o2 ! sync vaddr - sub %o0, 0x4, %o0 - lda [%o0] ASI_CONTROL, %o1 ! sync error - add %o0, 0xc, %o0 - lda [%o0] ASI_CONTROL, %o4 ! async vaddr - sub %o0, 0x4, %o0 - lda [%o0] ASI_CONTROL, %o3 ! async error - call sparc_lvl15_nmi - add %sp, STACKFRAME_SZ, %o0 - - RESTORE_ALL - - .align 4 - .globl invalid_segment_patch1_ff - .globl invalid_segment_patch2_ff -invalid_segment_patch1_ff: cmp %l4, 0xff -invalid_segment_patch2_ff: mov 0xff, %l3 - - .align 4 - .globl invalid_segment_patch1_1ff - .globl invalid_segment_patch2_1ff -invalid_segment_patch1_1ff: cmp %l4, 0x1ff -invalid_segment_patch2_1ff: mov 0x1ff, %l3 - - .align 4 - .globl num_context_patch1_16, num_context_patch2_16 -num_context_patch1_16: mov 0x10, %l7 -num_context_patch2_16: mov 0x10, %l7 - - .align 4 - .globl vac_linesize_patch_32 -vac_linesize_patch_32: subcc %l7, 32, %l7 - - .align 4 - .globl vac_hwflush_patch1_on, vac_hwflush_patch2_on - -/* - * Ugly, but we can't use hardware flushing on the sun4 and we'd require - * two instructions (Anton) - */ -vac_hwflush_patch1_on: addcc %l7, -PAGE_SIZE, %l7 - -vac_hwflush_patch2_on: sta %g0, [%l3 + %l7] ASI_HWFLUSHSEG - - .globl invalid_segment_patch1, invalid_segment_patch2 - .globl num_context_patch1 - .globl vac_linesize_patch, vac_hwflush_patch1 - .globl vac_hwflush_patch2 - - .align 4 - .globl sun4c_fault - -! %l0 = %psr -! %l1 = %pc -! %l2 = %npc -! %l3 = %wim -! %l7 = 1 for textfault -! We want error in %l5, vaddr in %l6 -sun4c_fault: - sethi %hi(AC_SYNC_ERR), %l4 - add %l4, 0x4, %l6 ! AC_SYNC_VA in %l6 - lda [%l6] ASI_CONTROL, %l5 ! Address - lda [%l4] ASI_CONTROL, %l6 ! Error, retained for a bit - - andn %l5, 0xfff, %l5 ! Encode all info into l7 - srl %l6, 14, %l4 - - and %l4, 2, %l4 - or %l5, %l4, %l4 - - or %l4, %l7, %l7 ! l7 = [addr,write,txtfault] - - andcc %l0, PSR_PS, %g0 - be sun4c_fault_fromuser - andcc %l7, 1, %g0 ! Text fault? - - be 1f - sethi %hi(KERNBASE), %l4 - - mov %l1, %l5 ! PC - -1: - cmp %l5, %l4 - blu sun4c_fault_fromuser - sethi %hi(~((1 << SUN4C_REAL_PGDIR_SHIFT) - 1)), %l4 - - /* If the kernel references a bum kernel pointer, or a pte which - * points to a non existent page in ram, we will run this code - * _forever_ and lock up the machine!!!!! So we must check for - * this condition, the AC_SYNC_ERR bits are what we must examine. - * Also a parity error would make this happen as well. So we just - * check that we are in fact servicing a tlb miss and not some - * other type of fault for the kernel. - */ - andcc %l6, 0x80, %g0 - be sun4c_fault_fromuser - and %l5, %l4, %l5 - - /* Test for NULL pte_t * in vmalloc area. */ - sethi %hi(VMALLOC_START), %l4 - cmp %l5, %l4 - blu,a invalid_segment_patch1 - lduXa [%l5] ASI_SEGMAP, %l4 - - sethi %hi(swapper_pg_dir), %l4 - srl %l5, SUN4C_PGDIR_SHIFT, %l6 - or %l4, %lo(swapper_pg_dir), %l4 - sll %l6, 2, %l6 - ld [%l4 + %l6], %l4 - andcc %l4, PAGE_MASK, %g0 - be sun4c_fault_fromuser - lduXa [%l5] ASI_SEGMAP, %l4 - -invalid_segment_patch1: - cmp %l4, 0x7f - bne 1f - sethi %hi(sun4c_kfree_ring), %l4 - or %l4, %lo(sun4c_kfree_ring), %l4 - ld [%l4 + 0x18], %l3 - deccc %l3 ! do we have a free entry? - bcs,a 2f ! no, unmap one. - sethi %hi(sun4c_kernel_ring), %l4 - - st %l3, [%l4 + 0x18] ! sun4c_kfree_ring.num_entries-- - - ld [%l4 + 0x00], %l6 ! entry = sun4c_kfree_ring.ringhd.next - st %l5, [%l6 + 0x08] ! entry->vaddr = address - - ld [%l6 + 0x00], %l3 ! next = entry->next - ld [%l6 + 0x04], %l7 ! entry->prev - - st %l7, [%l3 + 0x04] ! next->prev = entry->prev - st %l3, [%l7 + 0x00] ! entry->prev->next = next - - sethi %hi(sun4c_kernel_ring), %l4 - or %l4, %lo(sun4c_kernel_ring), %l4 - ! head = &sun4c_kernel_ring.ringhd - - ld [%l4 + 0x00], %l7 ! head->next - - st %l4, [%l6 + 0x04] ! entry->prev = head - st %l7, [%l6 + 0x00] ! entry->next = head->next - st %l6, [%l7 + 0x04] ! head->next->prev = entry - - st %l6, [%l4 + 0x00] ! head->next = entry - - ld [%l4 + 0x18], %l3 - inc %l3 ! sun4c_kernel_ring.num_entries++ - st %l3, [%l4 + 0x18] - b 4f - ld [%l6 + 0x08], %l5 - -2: - or %l4, %lo(sun4c_kernel_ring), %l4 - ! head = &sun4c_kernel_ring.ringhd - - ld [%l4 + 0x04], %l6 ! entry = head->prev - - ld [%l6 + 0x08], %l3 ! tmp = entry->vaddr - - ! Flush segment from the cache. - sethi %hi((64 * 1024)), %l7 -9: -vac_hwflush_patch1: -vac_linesize_patch: - subcc %l7, 16, %l7 - bne 9b -vac_hwflush_patch2: - sta %g0, [%l3 + %l7] ASI_FLUSHSEG - - st %l5, [%l6 + 0x08] ! entry->vaddr = address - - ld [%l6 + 0x00], %l5 ! next = entry->next - ld [%l6 + 0x04], %l7 ! entry->prev - - st %l7, [%l5 + 0x04] ! next->prev = entry->prev - st %l5, [%l7 + 0x00] ! entry->prev->next = next - st %l4, [%l6 + 0x04] ! entry->prev = head - - ld [%l4 + 0x00], %l7 ! head->next - - st %l7, [%l6 + 0x00] ! entry->next = head->next - st %l6, [%l7 + 0x04] ! head->next->prev = entry - st %l6, [%l4 + 0x00] ! head->next = entry - - mov %l3, %l5 ! address = tmp - -4: -num_context_patch1: - mov 0x08, %l7 - - ld [%l6 + 0x08], %l4 - ldub [%l6 + 0x0c], %l3 - or %l4, %l3, %l4 ! encode new vaddr/pseg into l4 - - sethi %hi(AC_CONTEXT), %l3 - lduba [%l3] ASI_CONTROL, %l6 - - /* Invalidate old mapping, instantiate new mapping, - * for each context. Registers l6/l7 are live across - * this loop. - */ -3: deccc %l7 - sethi %hi(AC_CONTEXT), %l3 - stba %l7, [%l3] ASI_CONTROL -invalid_segment_patch2: - mov 0x7f, %l3 - stXa %l3, [%l5] ASI_SEGMAP - andn %l4, 0x1ff, %l3 - bne 3b - stXa %l4, [%l3] ASI_SEGMAP - - sethi %hi(AC_CONTEXT), %l3 - stba %l6, [%l3] ASI_CONTROL - - andn %l4, 0x1ff, %l5 - -1: - sethi %hi(VMALLOC_START), %l4 - cmp %l5, %l4 - - bgeu 1f - mov 1 << (SUN4C_REAL_PGDIR_SHIFT - PAGE_SHIFT), %l7 - - sethi %hi(KERNBASE), %l6 - - sub %l5, %l6, %l4 - srl %l4, PAGE_SHIFT, %l4 - sethi %hi((SUN4C_PAGE_KERNEL & 0xf4000000)), %l3 - or %l3, %l4, %l3 - - sethi %hi(PAGE_SIZE), %l4 - -2: - sta %l3, [%l5] ASI_PTE - deccc %l7 - inc %l3 - bne 2b - add %l5, %l4, %l5 - - b 7f - sethi %hi(sun4c_kernel_faults), %l4 - -1: - srl %l5, SUN4C_PGDIR_SHIFT, %l3 - sethi %hi(swapper_pg_dir), %l4 - or %l4, %lo(swapper_pg_dir), %l4 - sll %l3, 2, %l3 - ld [%l4 + %l3], %l4 - and %l4, PAGE_MASK, %l4 - - srl %l5, (PAGE_SHIFT - 2), %l6 - and %l6, ((SUN4C_PTRS_PER_PTE - 1) << 2), %l6 - add %l6, %l4, %l6 - - sethi %hi(PAGE_SIZE), %l4 - -2: - ld [%l6], %l3 - deccc %l7 - sta %l3, [%l5] ASI_PTE - add %l6, 0x4, %l6 - bne 2b - add %l5, %l4, %l5 - - sethi %hi(sun4c_kernel_faults), %l4 -7: - ld [%l4 + %lo(sun4c_kernel_faults)], %l3 - inc %l3 - st %l3, [%l4 + %lo(sun4c_kernel_faults)] - - /* Restore condition codes */ - wr %l0, 0x0, %psr + ld [%l5 + 0x00], %g0 ! sun4m_irq_global->pending WRITE_PAUSE - jmp %l1 - rett %l2 - -sun4c_fault_fromuser: - SAVE_ALL + or %l0, PSR_PIL, %l4 + wr %l4, 0x0, %psr + WRITE_PAUSE + wr %l4, PSR_ET, %psr + WRITE_PAUSE + call sun4m_nmi nop - - mov %l7, %o1 ! Decode the info from %l7 - mov %l7, %o2 - and %o1, 1, %o1 ! arg2 = text_faultp - mov %l7, %o3 - and %o2, 2, %o2 ! arg3 = writep - andn %o3, 0xfff, %o3 ! arg4 = faulting address - - wr %l0, PSR_ET, %psr + st %l4, [%l5 + 0x08] ! sun4m_irq_global->mask_clear=0x80000000 WRITE_PAUSE + ld [%l5 + 0x00], %g0 ! sun4m_irq_global->pending + WRITE_PAUSE + RESTORE_ALL - call do_sun4c_fault - add %sp, STACKFRAME_SZ, %o0 ! arg1 = pt_regs ptr +#ifndef CONFIG_SMP + .align 4 + .globl linux_trap_ipi15_sun4m +linux_trap_ipi15_sun4m: + SAVE_ALL - RESTORE_ALL + ba sun4m_nmi_error + nop +#endif /* CONFIG_SMP */ .align 4 .globl srmmu_fault @@ -1483,11 +1166,13 @@ fpload: .globl __ndelay __ndelay: save %sp, -STACKFRAME_SZ, %sp - mov %i0, %o0 - call .umul ! round multiplier up so large ns ok - mov 0x1ae, %o1 ! 2**32 / (1 000 000 000 / HZ) - call .umul - mov %i1, %o1 ! udelay_val + mov %i0, %o0 ! round multiplier up so large ns ok + mov 0x1ae, %o1 ! 2**32 / (1 000 000 000 / HZ) + umul %o0, %o1, %o0 + rd %y, %o1 + mov %i1, %o1 ! udelay_val + umul %o0, %o1, %o0 + rd %y, %o1 ba delay_continue mov %o1, %o0 ! >>32 later for better resolution @@ -1496,18 +1181,21 @@ __udelay: save %sp, -STACKFRAME_SZ, %sp mov %i0, %o0 sethi %hi(0x10c7), %o1 ! round multiplier up so large us ok - call .umul - or %o1, %lo(0x10c7), %o1 ! 2**32 / 1 000 000 - call .umul - mov %i1, %o1 ! udelay_val + or %o1, %lo(0x10c7), %o1 ! 2**32 / 1 000 000 + umul %o0, %o1, %o0 + rd %y, %o1 + mov %i1, %o1 ! udelay_val + umul %o0, %o1, %o0 + rd %y, %o1 sethi %hi(0x028f4b62), %l0 ! Add in rounding constant * 2**32, or %g0, %lo(0x028f4b62), %l0 addcc %o0, %l0, %o0 ! 2**32 * 0.009 999 bcs,a 3f add %o1, 0x01, %o1 3: - call .umul - mov HZ, %o0 ! >>32 earlier for wider range + mov HZ, %o0 ! >>32 earlier for wider range + umul %o0, %o1, %o0 + rd %y, %o1 delay_continue: cmp %o0, 0x0 @@ -1670,4 +1358,26 @@ flushw_all: ret restore +#ifdef CONFIG_SMP +ENTRY(hard_smp_processor_id) +661: rd %tbr, %g1 + srl %g1, 12, %o0 + and %o0, 3, %o0 + .section .cpuid_patch, "ax" + /* Instruction location. */ + .word 661b + /* SUN4D implementation. */ + lda [%g0] ASI_M_VIKING_TMP1, %o0 + nop + nop + /* LEON implementation. */ + rd %asr17, %o0 + srl %o0, 0x1c, %o0 + nop + .previous + retl + nop +ENDPROC(hard_smp_processor_id) +#endif + /* End of entry.S */ diff --git a/arch/sparc/kernel/etrap_32.S b/arch/sparc/kernel/etrap_32.S index e806fcdc46db..84b5f0d2afde 100644 --- a/arch/sparc/kernel/etrap_32.S +++ b/arch/sparc/kernel/etrap_32.S @@ -216,9 +216,7 @@ tsetup_patch6: /* Call MMU-architecture dependent stack checking * routine. */ - .globl tsetup_mmu_patchme -tsetup_mmu_patchme: - b tsetup_sun4c_stackchk + b tsetup_srmmu_stackchk andcc %sp, 0x7, %g0 /* Architecture specific stack checking routines. When either @@ -228,52 +226,6 @@ tsetup_mmu_patchme: */ #define glob_tmp g1 -tsetup_sun4c_stackchk: - /* Done by caller: andcc %sp, 0x7, %g0 */ - bne trap_setup_user_stack_is_bolixed - sra %sp, 29, %glob_tmp - - add %glob_tmp, 0x1, %glob_tmp - andncc %glob_tmp, 0x1, %g0 - bne trap_setup_user_stack_is_bolixed - and %sp, 0xfff, %glob_tmp ! delay slot - - /* See if our dump area will be on more than one - * page. - */ - add %glob_tmp, 0x38, %glob_tmp - andncc %glob_tmp, 0xff8, %g0 - be tsetup_sun4c_onepage ! only one page to check - lda [%sp] ASI_PTE, %glob_tmp ! have to check first page anyways - -tsetup_sun4c_twopages: - /* Is first page ok permission wise? */ - srl %glob_tmp, 29, %glob_tmp - cmp %glob_tmp, 0x6 - bne trap_setup_user_stack_is_bolixed - add %sp, 0x38, %glob_tmp /* Is second page in vma hole? */ - - sra %glob_tmp, 29, %glob_tmp - add %glob_tmp, 0x1, %glob_tmp - andncc %glob_tmp, 0x1, %g0 - bne trap_setup_user_stack_is_bolixed - add %sp, 0x38, %glob_tmp - - lda [%glob_tmp] ASI_PTE, %glob_tmp - -tsetup_sun4c_onepage: - srl %glob_tmp, 29, %glob_tmp - cmp %glob_tmp, 0x6 ! can user write to it? - bne trap_setup_user_stack_is_bolixed ! failure - nop - - STORE_WINDOW(sp) - - restore %g0, %g0, %g0 - - jmpl %t_retpc + 0x8, %g0 - mov %t_kstack, %sp - .globl tsetup_srmmu_stackchk tsetup_srmmu_stackchk: /* Check results of callers andcc %sp, 0x7, %g0 */ diff --git a/arch/sparc/kernel/head_32.S b/arch/sparc/kernel/head_32.S index 587785759838..a0f5c20e4b9c 100644 --- a/arch/sparc/kernel/head_32.S +++ b/arch/sparc/kernel/head_32.S @@ -26,11 +26,9 @@ #include <asm/pgtsrmmu.h> /* SRMMU_PGDIR_SHIFT */ .data -/* - * The following are used with the prom_vector node-ops to figure out - * the cpu-type +/* The following are used with the prom_vector node-ops to figure out + * the cpu-type */ - .align 4 cputyp: .word 1 @@ -38,384 +36,35 @@ cputyp: .align 4 .globl cputypval cputypval: - .asciz "sun4c" + .asciz "sun4m" .ascii " " -cputypvalend: -cputypvallen = cputypvar - cputypval - +/* Tested on SS-5, SS-10 */ .align 4 -/* - * Sun people can't spell worth damn. "compatability" indeed. - * At least we *know* we can't spell, and use a spell-checker. - */ - -/* Uh, actually Linus it is I who cannot spell. Too much murky - * Sparc assembly will do this to ya. - */ cputypvar: - .asciz "compatability" - -/* Tested on SS-5, SS-10. Probably someone at Sun applied a spell-checker. */ - .align 4 -cputypvar_sun4m: .asciz "compatible" .align 4 -sun4_notsup: - .asciz "Sparc-Linux sun4 support does no longer exist.\n\n" +sun4c_notsup: + .asciz "Sparc-Linux sun4/sun4c support does no longer exist.\n\n" .align 4 sun4e_notsup: .asciz "Sparc-Linux sun4e support does not exist\n\n" .align 4 - /* The Sparc trap table, bootloader gives us control at _start. */ - __HEAD - .globl _stext, _start, __stext - .globl trapbase -_start: /* danger danger */ -__stext: -_stext: -trapbase: -#ifdef CONFIG_SMP -trapbase_cpu0: -#endif -/* We get control passed to us here at t_zero. */ -t_zero: b gokernel; nop; nop; nop; -t_tflt: SPARC_TFAULT /* Inst. Access Exception */ -t_bins: TRAP_ENTRY(0x2, bad_instruction) /* Illegal Instruction */ -t_pins: TRAP_ENTRY(0x3, priv_instruction) /* Privileged Instruction */ -t_fpd: TRAP_ENTRY(0x4, fpd_trap_handler) /* Floating Point Disabled */ -t_wovf: WINDOW_SPILL /* Window Overflow */ -t_wunf: WINDOW_FILL /* Window Underflow */ -t_mna: TRAP_ENTRY(0x7, mna_handler) /* Memory Address Not Aligned */ -t_fpe: TRAP_ENTRY(0x8, fpe_trap_handler) /* Floating Point Exception */ -t_dflt: SPARC_DFAULT /* Data Miss Exception */ -t_tio: TRAP_ENTRY(0xa, do_tag_overflow) /* Tagged Instruction Ovrflw */ -t_wpt: TRAP_ENTRY(0xb, do_watchpoint) /* Watchpoint Detected */ -t_badc: BAD_TRAP(0xc) BAD_TRAP(0xd) BAD_TRAP(0xe) BAD_TRAP(0xf) BAD_TRAP(0x10) -t_irq1: TRAP_ENTRY_INTERRUPT(1) /* IRQ Software/SBUS Level 1 */ -t_irq2: TRAP_ENTRY_INTERRUPT(2) /* IRQ SBUS Level 2 */ -t_irq3: TRAP_ENTRY_INTERRUPT(3) /* IRQ SCSI/DMA/SBUS Level 3 */ -t_irq4: TRAP_ENTRY_INTERRUPT(4) /* IRQ Software Level 4 */ -t_irq5: TRAP_ENTRY_INTERRUPT(5) /* IRQ SBUS/Ethernet Level 5 */ -t_irq6: TRAP_ENTRY_INTERRUPT(6) /* IRQ Software Level 6 */ -t_irq7: TRAP_ENTRY_INTERRUPT(7) /* IRQ Video/SBUS Level 5 */ -t_irq8: TRAP_ENTRY_INTERRUPT(8) /* IRQ SBUS Level 6 */ -t_irq9: TRAP_ENTRY_INTERRUPT(9) /* IRQ SBUS Level 7 */ -t_irq10:TRAP_ENTRY_INTERRUPT(10) /* IRQ Timer #1 (one we use) */ -t_irq11:TRAP_ENTRY_INTERRUPT(11) /* IRQ Floppy Intr. */ -t_irq12:TRAP_ENTRY_INTERRUPT(12) /* IRQ Zilog serial chip */ -t_irq13:TRAP_ENTRY_INTERRUPT(13) /* IRQ Audio Intr. */ -t_irq14:TRAP_ENTRY_INTERRUPT(14) /* IRQ Timer #2 */ - .globl t_nmi -#ifndef CONFIG_SMP -t_nmi: NMI_TRAP /* Level 15 (NMI) */ -#else -t_nmi: TRAP_ENTRY(0x1f, linux_trap_ipi15_sun4m) -#endif -t_racc: TRAP_ENTRY(0x20, do_reg_access) /* General Register Access Error */ -t_iacce:BAD_TRAP(0x21) /* Instr Access Error */ -t_bad22:BAD_TRAP(0x22) BAD_TRAP(0x23) -t_cpdis:TRAP_ENTRY(0x24, do_cp_disabled) /* Co-Processor Disabled */ -t_uflsh:SKIP_TRAP(0x25, unimp_flush) /* Unimplemented FLUSH inst. */ -t_bad26:BAD_TRAP(0x26) BAD_TRAP(0x27) -t_cpexc:TRAP_ENTRY(0x28, do_cp_exception) /* Co-Processor Exception */ -t_dacce:SPARC_DFAULT /* Data Access Error */ -t_hwdz: TRAP_ENTRY(0x2a, do_hw_divzero) /* Division by zero, you lose... */ -t_dserr:BAD_TRAP(0x2b) /* Data Store Error */ -t_daccm:BAD_TRAP(0x2c) /* Data Access MMU-Miss */ -t_bad2d:BAD_TRAP(0x2d) BAD_TRAP(0x2e) BAD_TRAP(0x2f) BAD_TRAP(0x30) BAD_TRAP(0x31) -t_bad32:BAD_TRAP(0x32) BAD_TRAP(0x33) BAD_TRAP(0x34) BAD_TRAP(0x35) BAD_TRAP(0x36) -t_bad37:BAD_TRAP(0x37) BAD_TRAP(0x38) BAD_TRAP(0x39) BAD_TRAP(0x3a) BAD_TRAP(0x3b) -t_iaccm:BAD_TRAP(0x3c) /* Instr Access MMU-Miss */ -t_bad3d:BAD_TRAP(0x3d) BAD_TRAP(0x3e) BAD_TRAP(0x3f) BAD_TRAP(0x40) BAD_TRAP(0x41) -t_bad42:BAD_TRAP(0x42) BAD_TRAP(0x43) BAD_TRAP(0x44) BAD_TRAP(0x45) BAD_TRAP(0x46) -t_bad47:BAD_TRAP(0x47) BAD_TRAP(0x48) BAD_TRAP(0x49) BAD_TRAP(0x4a) BAD_TRAP(0x4b) -t_bad4c:BAD_TRAP(0x4c) BAD_TRAP(0x4d) BAD_TRAP(0x4e) BAD_TRAP(0x4f) BAD_TRAP(0x50) -t_bad51:BAD_TRAP(0x51) BAD_TRAP(0x52) BAD_TRAP(0x53) BAD_TRAP(0x54) BAD_TRAP(0x55) -t_bad56:BAD_TRAP(0x56) BAD_TRAP(0x57) BAD_TRAP(0x58) BAD_TRAP(0x59) BAD_TRAP(0x5a) -t_bad5b:BAD_TRAP(0x5b) BAD_TRAP(0x5c) BAD_TRAP(0x5d) BAD_TRAP(0x5e) BAD_TRAP(0x5f) -t_bad60:BAD_TRAP(0x60) BAD_TRAP(0x61) BAD_TRAP(0x62) BAD_TRAP(0x63) BAD_TRAP(0x64) -t_bad65:BAD_TRAP(0x65) BAD_TRAP(0x66) BAD_TRAP(0x67) BAD_TRAP(0x68) BAD_TRAP(0x69) -t_bad6a:BAD_TRAP(0x6a) BAD_TRAP(0x6b) BAD_TRAP(0x6c) BAD_TRAP(0x6d) BAD_TRAP(0x6e) -t_bad6f:BAD_TRAP(0x6f) BAD_TRAP(0x70) BAD_TRAP(0x71) BAD_TRAP(0x72) BAD_TRAP(0x73) -t_bad74:BAD_TRAP(0x74) BAD_TRAP(0x75) BAD_TRAP(0x76) BAD_TRAP(0x77) BAD_TRAP(0x78) -t_bad79:BAD_TRAP(0x79) BAD_TRAP(0x7a) BAD_TRAP(0x7b) BAD_TRAP(0x7c) BAD_TRAP(0x7d) -t_bad7e:BAD_TRAP(0x7e) BAD_TRAP(0x7f) -t_bad80:BAD_TRAP(0x80) /* SunOS System Call */ -t_sbkpt:BREAKPOINT_TRAP /* Software Breakpoint/KGDB */ -t_divz: TRAP_ENTRY(0x82, do_hw_divzero) /* Divide by zero trap */ -t_flwin:TRAP_ENTRY(0x83, do_flush_windows) /* Flush Windows Trap */ -t_clwin:BAD_TRAP(0x84) /* Clean Windows Trap */ -t_rchk: BAD_TRAP(0x85) /* Range Check */ -t_funal:BAD_TRAP(0x86) /* Fix Unaligned Access Trap */ -t_iovf: BAD_TRAP(0x87) /* Integer Overflow Trap */ -t_bad88:BAD_TRAP(0x88) /* Slowaris System Call */ -t_bad89:BAD_TRAP(0x89) /* Net-B.S. System Call */ -t_bad8a:BAD_TRAP(0x8a) BAD_TRAP(0x8b) BAD_TRAP(0x8c) BAD_TRAP(0x8d) BAD_TRAP(0x8e) -t_bad8f:BAD_TRAP(0x8f) -t_linux:LINUX_SYSCALL_TRAP /* Linux System Call */ -t_bad91:BAD_TRAP(0x91) BAD_TRAP(0x92) BAD_TRAP(0x93) BAD_TRAP(0x94) BAD_TRAP(0x95) -t_bad96:BAD_TRAP(0x96) BAD_TRAP(0x97) BAD_TRAP(0x98) BAD_TRAP(0x99) BAD_TRAP(0x9a) -t_bad9b:BAD_TRAP(0x9b) BAD_TRAP(0x9c) BAD_TRAP(0x9d) BAD_TRAP(0x9e) BAD_TRAP(0x9f) -t_getcc:GETCC_TRAP /* Get Condition Codes */ -t_setcc:SETCC_TRAP /* Set Condition Codes */ -t_getpsr:GETPSR_TRAP /* Get PSR Register */ -t_bada3:BAD_TRAP(0xa3) BAD_TRAP(0xa4) BAD_TRAP(0xa5) BAD_TRAP(0xa6) -t_bada7:BAD_TRAP(0xa7) -t_bada8:BAD_TRAP(0xa8) BAD_TRAP(0xa9) BAD_TRAP(0xaa) BAD_TRAP(0xab) -t_badac:BAD_TRAP(0xac) BAD_TRAP(0xad) BAD_TRAP(0xae) BAD_TRAP(0xaf) BAD_TRAP(0xb0) -t_badb1:BAD_TRAP(0xb1) BAD_TRAP(0xb2) BAD_TRAP(0xb3) BAD_TRAP(0xb4) BAD_TRAP(0xb5) -t_badb6:BAD_TRAP(0xb6) BAD_TRAP(0xb7) BAD_TRAP(0xb8) BAD_TRAP(0xb9) BAD_TRAP(0xba) -t_badbb:BAD_TRAP(0xbb) BAD_TRAP(0xbc) BAD_TRAP(0xbd) BAD_TRAP(0xbe) BAD_TRAP(0xbf) -t_badc0:BAD_TRAP(0xc0) BAD_TRAP(0xc1) BAD_TRAP(0xc2) BAD_TRAP(0xc3) BAD_TRAP(0xc4) -t_badc5:BAD_TRAP(0xc5) BAD_TRAP(0xc6) BAD_TRAP(0xc7) BAD_TRAP(0xc8) BAD_TRAP(0xc9) -t_badca:BAD_TRAP(0xca) BAD_TRAP(0xcb) BAD_TRAP(0xcc) BAD_TRAP(0xcd) BAD_TRAP(0xce) -t_badcf:BAD_TRAP(0xcf) BAD_TRAP(0xd0) BAD_TRAP(0xd1) BAD_TRAP(0xd2) BAD_TRAP(0xd3) -t_badd4:BAD_TRAP(0xd4) BAD_TRAP(0xd5) BAD_TRAP(0xd6) BAD_TRAP(0xd7) BAD_TRAP(0xd8) -t_badd9:BAD_TRAP(0xd9) BAD_TRAP(0xda) BAD_TRAP(0xdb) BAD_TRAP(0xdc) BAD_TRAP(0xdd) -t_badde:BAD_TRAP(0xde) BAD_TRAP(0xdf) BAD_TRAP(0xe0) BAD_TRAP(0xe1) BAD_TRAP(0xe2) -t_bade3:BAD_TRAP(0xe3) BAD_TRAP(0xe4) BAD_TRAP(0xe5) BAD_TRAP(0xe6) BAD_TRAP(0xe7) -t_bade8:BAD_TRAP(0xe8) BAD_TRAP(0xe9) BAD_TRAP(0xea) BAD_TRAP(0xeb) BAD_TRAP(0xec) -t_baded:BAD_TRAP(0xed) BAD_TRAP(0xee) BAD_TRAP(0xef) BAD_TRAP(0xf0) BAD_TRAP(0xf1) -t_badf2:BAD_TRAP(0xf2) BAD_TRAP(0xf3) BAD_TRAP(0xf4) BAD_TRAP(0xf5) BAD_TRAP(0xf6) -t_badf7:BAD_TRAP(0xf7) BAD_TRAP(0xf8) BAD_TRAP(0xf9) BAD_TRAP(0xfa) BAD_TRAP(0xfb) -t_badfc:BAD_TRAP(0xfc) -t_kgdb: KGDB_TRAP(0xfd) -dbtrap: BAD_TRAP(0xfe) /* Debugger/PROM breakpoint #1 */ -dbtrap2:BAD_TRAP(0xff) /* Debugger/PROM breakpoint #2 */ - - .globl end_traptable -end_traptable: - -#ifdef CONFIG_SMP - /* Trap tables for the other cpus. */ - .globl trapbase_cpu1, trapbase_cpu2, trapbase_cpu3 -trapbase_cpu1: - BAD_TRAP(0x0) SRMMU_TFAULT TRAP_ENTRY(0x2, bad_instruction) - TRAP_ENTRY(0x3, priv_instruction) TRAP_ENTRY(0x4, fpd_trap_handler) - WINDOW_SPILL WINDOW_FILL TRAP_ENTRY(0x7, mna_handler) - TRAP_ENTRY(0x8, fpe_trap_handler) SRMMU_DFAULT - TRAP_ENTRY(0xa, do_tag_overflow) TRAP_ENTRY(0xb, do_watchpoint) - BAD_TRAP(0xc) BAD_TRAP(0xd) BAD_TRAP(0xe) BAD_TRAP(0xf) BAD_TRAP(0x10) - TRAP_ENTRY_INTERRUPT(1) TRAP_ENTRY_INTERRUPT(2) - TRAP_ENTRY_INTERRUPT(3) TRAP_ENTRY_INTERRUPT(4) - TRAP_ENTRY_INTERRUPT(5) TRAP_ENTRY_INTERRUPT(6) - TRAP_ENTRY_INTERRUPT(7) TRAP_ENTRY_INTERRUPT(8) - TRAP_ENTRY_INTERRUPT(9) TRAP_ENTRY_INTERRUPT(10) - TRAP_ENTRY_INTERRUPT(11) TRAP_ENTRY_INTERRUPT(12) - TRAP_ENTRY_INTERRUPT(13) TRAP_ENTRY_INTERRUPT(14) - TRAP_ENTRY(0x1f, linux_trap_ipi15_sun4m) - TRAP_ENTRY(0x20, do_reg_access) BAD_TRAP(0x21) BAD_TRAP(0x22) - BAD_TRAP(0x23) TRAP_ENTRY(0x24, do_cp_disabled) SKIP_TRAP(0x25, unimp_flush) - BAD_TRAP(0x26) BAD_TRAP(0x27) TRAP_ENTRY(0x28, do_cp_exception) - SRMMU_DFAULT TRAP_ENTRY(0x2a, do_hw_divzero) BAD_TRAP(0x2b) BAD_TRAP(0x2c) - BAD_TRAP(0x2d) BAD_TRAP(0x2e) BAD_TRAP(0x2f) BAD_TRAP(0x30) BAD_TRAP(0x31) - BAD_TRAP(0x32) BAD_TRAP(0x33) BAD_TRAP(0x34) BAD_TRAP(0x35) BAD_TRAP(0x36) - BAD_TRAP(0x37) BAD_TRAP(0x38) BAD_TRAP(0x39) BAD_TRAP(0x3a) BAD_TRAP(0x3b) - BAD_TRAP(0x3c) BAD_TRAP(0x3d) BAD_TRAP(0x3e) BAD_TRAP(0x3f) BAD_TRAP(0x40) - BAD_TRAP(0x41) BAD_TRAP(0x42) BAD_TRAP(0x43) BAD_TRAP(0x44) BAD_TRAP(0x45) - BAD_TRAP(0x46) BAD_TRAP(0x47) BAD_TRAP(0x48) BAD_TRAP(0x49) BAD_TRAP(0x4a) - BAD_TRAP(0x4b) BAD_TRAP(0x4c) BAD_TRAP(0x4d) BAD_TRAP(0x4e) BAD_TRAP(0x4f) - BAD_TRAP(0x50) - BAD_TRAP(0x51) BAD_TRAP(0x52) BAD_TRAP(0x53) BAD_TRAP(0x54) BAD_TRAP(0x55) - BAD_TRAP(0x56) BAD_TRAP(0x57) BAD_TRAP(0x58) BAD_TRAP(0x59) BAD_TRAP(0x5a) - BAD_TRAP(0x5b) BAD_TRAP(0x5c) BAD_TRAP(0x5d) BAD_TRAP(0x5e) BAD_TRAP(0x5f) - BAD_TRAP(0x60) BAD_TRAP(0x61) BAD_TRAP(0x62) BAD_TRAP(0x63) BAD_TRAP(0x64) - BAD_TRAP(0x65) BAD_TRAP(0x66) BAD_TRAP(0x67) BAD_TRAP(0x68) BAD_TRAP(0x69) - BAD_TRAP(0x6a) BAD_TRAP(0x6b) BAD_TRAP(0x6c) BAD_TRAP(0x6d) BAD_TRAP(0x6e) - BAD_TRAP(0x6f) BAD_TRAP(0x70) BAD_TRAP(0x71) BAD_TRAP(0x72) BAD_TRAP(0x73) - BAD_TRAP(0x74) BAD_TRAP(0x75) BAD_TRAP(0x76) BAD_TRAP(0x77) BAD_TRAP(0x78) - BAD_TRAP(0x79) BAD_TRAP(0x7a) BAD_TRAP(0x7b) BAD_TRAP(0x7c) BAD_TRAP(0x7d) - BAD_TRAP(0x7e) BAD_TRAP(0x7f) - BAD_TRAP(0x80) - BREAKPOINT_TRAP - TRAP_ENTRY(0x82, do_hw_divzero) - TRAP_ENTRY(0x83, do_flush_windows) BAD_TRAP(0x84) BAD_TRAP(0x85) - BAD_TRAP(0x86) BAD_TRAP(0x87) BAD_TRAP(0x88) - BAD_TRAP(0x89) BAD_TRAP(0x8a) BAD_TRAP(0x8b) BAD_TRAP(0x8c) - BAD_TRAP(0x8d) BAD_TRAP(0x8e) BAD_TRAP(0x8f) - LINUX_SYSCALL_TRAP BAD_TRAP(0x91) BAD_TRAP(0x92) BAD_TRAP(0x93) BAD_TRAP(0x94) - BAD_TRAP(0x95) BAD_TRAP(0x96) BAD_TRAP(0x97) BAD_TRAP(0x98) BAD_TRAP(0x99) - BAD_TRAP(0x9a) BAD_TRAP(0x9b) BAD_TRAP(0x9c) BAD_TRAP(0x9d) BAD_TRAP(0x9e) - BAD_TRAP(0x9f) GETCC_TRAP SETCC_TRAP GETPSR_TRAP - BAD_TRAP(0xa3) BAD_TRAP(0xa4) BAD_TRAP(0xa5) BAD_TRAP(0xa6) - BAD_TRAP(0xa7) BAD_TRAP(0xa8) BAD_TRAP(0xa9) BAD_TRAP(0xaa) BAD_TRAP(0xab) - BAD_TRAP(0xac) BAD_TRAP(0xad) BAD_TRAP(0xae) BAD_TRAP(0xaf) BAD_TRAP(0xb0) - BAD_TRAP(0xb1) BAD_TRAP(0xb2) BAD_TRAP(0xb3) BAD_TRAP(0xb4) BAD_TRAP(0xb5) - BAD_TRAP(0xb6) BAD_TRAP(0xb7) BAD_TRAP(0xb8) BAD_TRAP(0xb9) BAD_TRAP(0xba) - BAD_TRAP(0xbb) BAD_TRAP(0xbc) BAD_TRAP(0xbd) BAD_TRAP(0xbe) BAD_TRAP(0xbf) - BAD_TRAP(0xc0) BAD_TRAP(0xc1) BAD_TRAP(0xc2) BAD_TRAP(0xc3) BAD_TRAP(0xc4) - BAD_TRAP(0xc5) BAD_TRAP(0xc6) BAD_TRAP(0xc7) BAD_TRAP(0xc8) BAD_TRAP(0xc9) - BAD_TRAP(0xca) BAD_TRAP(0xcb) BAD_TRAP(0xcc) BAD_TRAP(0xcd) BAD_TRAP(0xce) - BAD_TRAP(0xcf) BAD_TRAP(0xd0) BAD_TRAP(0xd1) BAD_TRAP(0xd2) BAD_TRAP(0xd3) - BAD_TRAP(0xd4) BAD_TRAP(0xd5) BAD_TRAP(0xd6) BAD_TRAP(0xd7) BAD_TRAP(0xd8) - BAD_TRAP(0xd9) BAD_TRAP(0xda) BAD_TRAP(0xdb) BAD_TRAP(0xdc) BAD_TRAP(0xdd) - BAD_TRAP(0xde) BAD_TRAP(0xdf) BAD_TRAP(0xe0) BAD_TRAP(0xe1) BAD_TRAP(0xe2) - BAD_TRAP(0xe3) BAD_TRAP(0xe4) BAD_TRAP(0xe5) BAD_TRAP(0xe6) BAD_TRAP(0xe7) - BAD_TRAP(0xe8) BAD_TRAP(0xe9) BAD_TRAP(0xea) BAD_TRAP(0xeb) BAD_TRAP(0xec) - BAD_TRAP(0xed) BAD_TRAP(0xee) BAD_TRAP(0xef) BAD_TRAP(0xf0) BAD_TRAP(0xf1) - BAD_TRAP(0xf2) BAD_TRAP(0xf3) BAD_TRAP(0xf4) BAD_TRAP(0xf5) BAD_TRAP(0xf6) - BAD_TRAP(0xf7) BAD_TRAP(0xf8) BAD_TRAP(0xf9) BAD_TRAP(0xfa) BAD_TRAP(0xfb) - BAD_TRAP(0xfc) KGDB_TRAP(0xfd) BAD_TRAP(0xfe) BAD_TRAP(0xff) - -trapbase_cpu2: - BAD_TRAP(0x0) SRMMU_TFAULT TRAP_ENTRY(0x2, bad_instruction) - TRAP_ENTRY(0x3, priv_instruction) TRAP_ENTRY(0x4, fpd_trap_handler) - WINDOW_SPILL WINDOW_FILL TRAP_ENTRY(0x7, mna_handler) - TRAP_ENTRY(0x8, fpe_trap_handler) SRMMU_DFAULT - TRAP_ENTRY(0xa, do_tag_overflow) TRAP_ENTRY(0xb, do_watchpoint) - BAD_TRAP(0xc) BAD_TRAP(0xd) BAD_TRAP(0xe) BAD_TRAP(0xf) BAD_TRAP(0x10) - TRAP_ENTRY_INTERRUPT(1) TRAP_ENTRY_INTERRUPT(2) - TRAP_ENTRY_INTERRUPT(3) TRAP_ENTRY_INTERRUPT(4) - TRAP_ENTRY_INTERRUPT(5) TRAP_ENTRY_INTERRUPT(6) - TRAP_ENTRY_INTERRUPT(7) TRAP_ENTRY_INTERRUPT(8) - TRAP_ENTRY_INTERRUPT(9) TRAP_ENTRY_INTERRUPT(10) - TRAP_ENTRY_INTERRUPT(11) TRAP_ENTRY_INTERRUPT(12) - TRAP_ENTRY_INTERRUPT(13) TRAP_ENTRY_INTERRUPT(14) - TRAP_ENTRY(0x1f, linux_trap_ipi15_sun4m) - TRAP_ENTRY(0x20, do_reg_access) BAD_TRAP(0x21) BAD_TRAP(0x22) - BAD_TRAP(0x23) TRAP_ENTRY(0x24, do_cp_disabled) SKIP_TRAP(0x25, unimp_flush) - BAD_TRAP(0x26) BAD_TRAP(0x27) TRAP_ENTRY(0x28, do_cp_exception) - SRMMU_DFAULT TRAP_ENTRY(0x2a, do_hw_divzero) BAD_TRAP(0x2b) BAD_TRAP(0x2c) - BAD_TRAP(0x2d) BAD_TRAP(0x2e) BAD_TRAP(0x2f) BAD_TRAP(0x30) BAD_TRAP(0x31) - BAD_TRAP(0x32) BAD_TRAP(0x33) BAD_TRAP(0x34) BAD_TRAP(0x35) BAD_TRAP(0x36) - BAD_TRAP(0x37) BAD_TRAP(0x38) BAD_TRAP(0x39) BAD_TRAP(0x3a) BAD_TRAP(0x3b) - BAD_TRAP(0x3c) BAD_TRAP(0x3d) BAD_TRAP(0x3e) BAD_TRAP(0x3f) BAD_TRAP(0x40) - BAD_TRAP(0x41) BAD_TRAP(0x42) BAD_TRAP(0x43) BAD_TRAP(0x44) BAD_TRAP(0x45) - BAD_TRAP(0x46) BAD_TRAP(0x47) BAD_TRAP(0x48) BAD_TRAP(0x49) BAD_TRAP(0x4a) - BAD_TRAP(0x4b) BAD_TRAP(0x4c) BAD_TRAP(0x4d) BAD_TRAP(0x4e) BAD_TRAP(0x4f) - BAD_TRAP(0x50) - BAD_TRAP(0x51) BAD_TRAP(0x52) BAD_TRAP(0x53) BAD_TRAP(0x54) BAD_TRAP(0x55) - BAD_TRAP(0x56) BAD_TRAP(0x57) BAD_TRAP(0x58) BAD_TRAP(0x59) BAD_TRAP(0x5a) - BAD_TRAP(0x5b) BAD_TRAP(0x5c) BAD_TRAP(0x5d) BAD_TRAP(0x5e) BAD_TRAP(0x5f) - BAD_TRAP(0x60) BAD_TRAP(0x61) BAD_TRAP(0x62) BAD_TRAP(0x63) BAD_TRAP(0x64) - BAD_TRAP(0x65) BAD_TRAP(0x66) BAD_TRAP(0x67) BAD_TRAP(0x68) BAD_TRAP(0x69) - BAD_TRAP(0x6a) BAD_TRAP(0x6b) BAD_TRAP(0x6c) BAD_TRAP(0x6d) BAD_TRAP(0x6e) - BAD_TRAP(0x6f) BAD_TRAP(0x70) BAD_TRAP(0x71) BAD_TRAP(0x72) BAD_TRAP(0x73) - BAD_TRAP(0x74) BAD_TRAP(0x75) BAD_TRAP(0x76) BAD_TRAP(0x77) BAD_TRAP(0x78) - BAD_TRAP(0x79) BAD_TRAP(0x7a) BAD_TRAP(0x7b) BAD_TRAP(0x7c) BAD_TRAP(0x7d) - BAD_TRAP(0x7e) BAD_TRAP(0x7f) - BAD_TRAP(0x80) - BREAKPOINT_TRAP - TRAP_ENTRY(0x82, do_hw_divzero) - TRAP_ENTRY(0x83, do_flush_windows) BAD_TRAP(0x84) BAD_TRAP(0x85) - BAD_TRAP(0x86) BAD_TRAP(0x87) BAD_TRAP(0x88) - BAD_TRAP(0x89) BAD_TRAP(0x8a) BAD_TRAP(0x8b) BAD_TRAP(0x8c) - BAD_TRAP(0x8d) BAD_TRAP(0x8e) BAD_TRAP(0x8f) - LINUX_SYSCALL_TRAP BAD_TRAP(0x91) BAD_TRAP(0x92) BAD_TRAP(0x93) BAD_TRAP(0x94) - BAD_TRAP(0x95) BAD_TRAP(0x96) BAD_TRAP(0x97) BAD_TRAP(0x98) BAD_TRAP(0x99) - BAD_TRAP(0x9a) BAD_TRAP(0x9b) BAD_TRAP(0x9c) BAD_TRAP(0x9d) BAD_TRAP(0x9e) - BAD_TRAP(0x9f) GETCC_TRAP SETCC_TRAP GETPSR_TRAP - BAD_TRAP(0xa3) BAD_TRAP(0xa4) BAD_TRAP(0xa5) BAD_TRAP(0xa6) - BAD_TRAP(0xa7) BAD_TRAP(0xa8) BAD_TRAP(0xa9) BAD_TRAP(0xaa) BAD_TRAP(0xab) - BAD_TRAP(0xac) BAD_TRAP(0xad) BAD_TRAP(0xae) BAD_TRAP(0xaf) BAD_TRAP(0xb0) - BAD_TRAP(0xb1) BAD_TRAP(0xb2) BAD_TRAP(0xb3) BAD_TRAP(0xb4) BAD_TRAP(0xb5) - BAD_TRAP(0xb6) BAD_TRAP(0xb7) BAD_TRAP(0xb8) BAD_TRAP(0xb9) BAD_TRAP(0xba) - BAD_TRAP(0xbb) BAD_TRAP(0xbc) BAD_TRAP(0xbd) BAD_TRAP(0xbe) BAD_TRAP(0xbf) - BAD_TRAP(0xc0) BAD_TRAP(0xc1) BAD_TRAP(0xc2) BAD_TRAP(0xc3) BAD_TRAP(0xc4) - BAD_TRAP(0xc5) BAD_TRAP(0xc6) BAD_TRAP(0xc7) BAD_TRAP(0xc8) BAD_TRAP(0xc9) - BAD_TRAP(0xca) BAD_TRAP(0xcb) BAD_TRAP(0xcc) BAD_TRAP(0xcd) BAD_TRAP(0xce) - BAD_TRAP(0xcf) BAD_TRAP(0xd0) BAD_TRAP(0xd1) BAD_TRAP(0xd2) BAD_TRAP(0xd3) - BAD_TRAP(0xd4) BAD_TRAP(0xd5) BAD_TRAP(0xd6) BAD_TRAP(0xd7) BAD_TRAP(0xd8) - BAD_TRAP(0xd9) BAD_TRAP(0xda) BAD_TRAP(0xdb) BAD_TRAP(0xdc) BAD_TRAP(0xdd) - BAD_TRAP(0xde) BAD_TRAP(0xdf) BAD_TRAP(0xe0) BAD_TRAP(0xe1) BAD_TRAP(0xe2) - BAD_TRAP(0xe3) BAD_TRAP(0xe4) BAD_TRAP(0xe5) BAD_TRAP(0xe6) BAD_TRAP(0xe7) - BAD_TRAP(0xe8) BAD_TRAP(0xe9) BAD_TRAP(0xea) BAD_TRAP(0xeb) BAD_TRAP(0xec) - BAD_TRAP(0xed) BAD_TRAP(0xee) BAD_TRAP(0xef) BAD_TRAP(0xf0) BAD_TRAP(0xf1) - BAD_TRAP(0xf2) BAD_TRAP(0xf3) BAD_TRAP(0xf4) BAD_TRAP(0xf5) BAD_TRAP(0xf6) - BAD_TRAP(0xf7) BAD_TRAP(0xf8) BAD_TRAP(0xf9) BAD_TRAP(0xfa) BAD_TRAP(0xfb) - BAD_TRAP(0xfc) KGDB_TRAP(0xfd) BAD_TRAP(0xfe) BAD_TRAP(0xff) - -trapbase_cpu3: - BAD_TRAP(0x0) SRMMU_TFAULT TRAP_ENTRY(0x2, bad_instruction) - TRAP_ENTRY(0x3, priv_instruction) TRAP_ENTRY(0x4, fpd_trap_handler) - WINDOW_SPILL WINDOW_FILL TRAP_ENTRY(0x7, mna_handler) - TRAP_ENTRY(0x8, fpe_trap_handler) SRMMU_DFAULT - TRAP_ENTRY(0xa, do_tag_overflow) TRAP_ENTRY(0xb, do_watchpoint) - BAD_TRAP(0xc) BAD_TRAP(0xd) BAD_TRAP(0xe) BAD_TRAP(0xf) BAD_TRAP(0x10) - TRAP_ENTRY_INTERRUPT(1) TRAP_ENTRY_INTERRUPT(2) - TRAP_ENTRY_INTERRUPT(3) TRAP_ENTRY_INTERRUPT(4) - TRAP_ENTRY_INTERRUPT(5) TRAP_ENTRY_INTERRUPT(6) - TRAP_ENTRY_INTERRUPT(7) TRAP_ENTRY_INTERRUPT(8) - TRAP_ENTRY_INTERRUPT(9) TRAP_ENTRY_INTERRUPT(10) - TRAP_ENTRY_INTERRUPT(11) TRAP_ENTRY_INTERRUPT(12) - TRAP_ENTRY_INTERRUPT(13) TRAP_ENTRY_INTERRUPT(14) - TRAP_ENTRY(0x1f, linux_trap_ipi15_sun4m) - TRAP_ENTRY(0x20, do_reg_access) BAD_TRAP(0x21) BAD_TRAP(0x22) - BAD_TRAP(0x23) TRAP_ENTRY(0x24, do_cp_disabled) SKIP_TRAP(0x25, unimp_flush) - BAD_TRAP(0x26) BAD_TRAP(0x27) TRAP_ENTRY(0x28, do_cp_exception) - SRMMU_DFAULT TRAP_ENTRY(0x2a, do_hw_divzero) BAD_TRAP(0x2b) BAD_TRAP(0x2c) - BAD_TRAP(0x2d) BAD_TRAP(0x2e) BAD_TRAP(0x2f) BAD_TRAP(0x30) BAD_TRAP(0x31) - BAD_TRAP(0x32) BAD_TRAP(0x33) BAD_TRAP(0x34) BAD_TRAP(0x35) BAD_TRAP(0x36) - BAD_TRAP(0x37) BAD_TRAP(0x38) BAD_TRAP(0x39) BAD_TRAP(0x3a) BAD_TRAP(0x3b) - BAD_TRAP(0x3c) BAD_TRAP(0x3d) BAD_TRAP(0x3e) BAD_TRAP(0x3f) BAD_TRAP(0x40) - BAD_TRAP(0x41) BAD_TRAP(0x42) BAD_TRAP(0x43) BAD_TRAP(0x44) BAD_TRAP(0x45) - BAD_TRAP(0x46) BAD_TRAP(0x47) BAD_TRAP(0x48) BAD_TRAP(0x49) BAD_TRAP(0x4a) - BAD_TRAP(0x4b) BAD_TRAP(0x4c) BAD_TRAP(0x4d) BAD_TRAP(0x4e) BAD_TRAP(0x4f) - BAD_TRAP(0x50) - BAD_TRAP(0x51) BAD_TRAP(0x52) BAD_TRAP(0x53) BAD_TRAP(0x54) BAD_TRAP(0x55) - BAD_TRAP(0x56) BAD_TRAP(0x57) BAD_TRAP(0x58) BAD_TRAP(0x59) BAD_TRAP(0x5a) - BAD_TRAP(0x5b) BAD_TRAP(0x5c) BAD_TRAP(0x5d) BAD_TRAP(0x5e) BAD_TRAP(0x5f) - BAD_TRAP(0x60) BAD_TRAP(0x61) BAD_TRAP(0x62) BAD_TRAP(0x63) BAD_TRAP(0x64) - BAD_TRAP(0x65) BAD_TRAP(0x66) BAD_TRAP(0x67) BAD_TRAP(0x68) BAD_TRAP(0x69) - BAD_TRAP(0x6a) BAD_TRAP(0x6b) BAD_TRAP(0x6c) BAD_TRAP(0x6d) BAD_TRAP(0x6e) - BAD_TRAP(0x6f) BAD_TRAP(0x70) BAD_TRAP(0x71) BAD_TRAP(0x72) BAD_TRAP(0x73) - BAD_TRAP(0x74) BAD_TRAP(0x75) BAD_TRAP(0x76) BAD_TRAP(0x77) BAD_TRAP(0x78) - BAD_TRAP(0x79) BAD_TRAP(0x7a) BAD_TRAP(0x7b) BAD_TRAP(0x7c) BAD_TRAP(0x7d) - BAD_TRAP(0x7e) BAD_TRAP(0x7f) - BAD_TRAP(0x80) - BREAKPOINT_TRAP - TRAP_ENTRY(0x82, do_hw_divzero) - TRAP_ENTRY(0x83, do_flush_windows) BAD_TRAP(0x84) BAD_TRAP(0x85) - BAD_TRAP(0x86) BAD_TRAP(0x87) BAD_TRAP(0x88) - BAD_TRAP(0x89) BAD_TRAP(0x8a) BAD_TRAP(0x8b) BAD_TRAP(0x8c) - BAD_TRAP(0x8d) BAD_TRAP(0x8e) BAD_TRAP(0x8f) - LINUX_SYSCALL_TRAP BAD_TRAP(0x91) BAD_TRAP(0x92) BAD_TRAP(0x93) BAD_TRAP(0x94) - BAD_TRAP(0x95) BAD_TRAP(0x96) BAD_TRAP(0x97) BAD_TRAP(0x98) BAD_TRAP(0x99) - BAD_TRAP(0x9a) BAD_TRAP(0x9b) BAD_TRAP(0x9c) BAD_TRAP(0x9d) BAD_TRAP(0x9e) - BAD_TRAP(0x9f) GETCC_TRAP SETCC_TRAP GETPSR_TRAP - BAD_TRAP(0xa3) BAD_TRAP(0xa4) BAD_TRAP(0xa5) BAD_TRAP(0xa6) - BAD_TRAP(0xa7) BAD_TRAP(0xa8) BAD_TRAP(0xa9) BAD_TRAP(0xaa) BAD_TRAP(0xab) - BAD_TRAP(0xac) BAD_TRAP(0xad) BAD_TRAP(0xae) BAD_TRAP(0xaf) BAD_TRAP(0xb0) - BAD_TRAP(0xb1) BAD_TRAP(0xb2) BAD_TRAP(0xb3) BAD_TRAP(0xb4) BAD_TRAP(0xb5) - BAD_TRAP(0xb6) BAD_TRAP(0xb7) BAD_TRAP(0xb8) BAD_TRAP(0xb9) BAD_TRAP(0xba) - BAD_TRAP(0xbb) BAD_TRAP(0xbc) BAD_TRAP(0xbd) BAD_TRAP(0xbe) BAD_TRAP(0xbf) - BAD_TRAP(0xc0) BAD_TRAP(0xc1) BAD_TRAP(0xc2) BAD_TRAP(0xc3) BAD_TRAP(0xc4) - BAD_TRAP(0xc5) BAD_TRAP(0xc6) BAD_TRAP(0xc7) BAD_TRAP(0xc8) BAD_TRAP(0xc9) - BAD_TRAP(0xca) BAD_TRAP(0xcb) BAD_TRAP(0xcc) BAD_TRAP(0xcd) BAD_TRAP(0xce) - BAD_TRAP(0xcf) BAD_TRAP(0xd0) BAD_TRAP(0xd1) BAD_TRAP(0xd2) BAD_TRAP(0xd3) - BAD_TRAP(0xd4) BAD_TRAP(0xd5) BAD_TRAP(0xd6) BAD_TRAP(0xd7) BAD_TRAP(0xd8) - BAD_TRAP(0xd9) BAD_TRAP(0xda) BAD_TRAP(0xdb) BAD_TRAP(0xdc) BAD_TRAP(0xdd) - BAD_TRAP(0xde) BAD_TRAP(0xdf) BAD_TRAP(0xe0) BAD_TRAP(0xe1) BAD_TRAP(0xe2) - BAD_TRAP(0xe3) BAD_TRAP(0xe4) BAD_TRAP(0xe5) BAD_TRAP(0xe6) BAD_TRAP(0xe7) - BAD_TRAP(0xe8) BAD_TRAP(0xe9) BAD_TRAP(0xea) BAD_TRAP(0xeb) BAD_TRAP(0xec) - BAD_TRAP(0xed) BAD_TRAP(0xee) BAD_TRAP(0xef) BAD_TRAP(0xf0) BAD_TRAP(0xf1) - BAD_TRAP(0xf2) BAD_TRAP(0xf3) BAD_TRAP(0xf4) BAD_TRAP(0xf5) BAD_TRAP(0xf6) - BAD_TRAP(0xf7) BAD_TRAP(0xf8) BAD_TRAP(0xf9) BAD_TRAP(0xfa) BAD_TRAP(0xfb) - BAD_TRAP(0xfc) KGDB_TRAP(0xfd) BAD_TRAP(0xfe) BAD_TRAP(0xff) +/* The trap-table - located in the __HEAD section */ +#include "ttable_32.S" -#endif .align PAGE_SIZE /* This was the only reasonable way I could think of to properly align * these page-table data structures. */ - .globl pg0, pg1, pg2, pg3 - .globl empty_bad_page - .globl empty_bad_page_table - .globl empty_zero_page .globl swapper_pg_dir swapper_pg_dir: .skip PAGE_SIZE -pg0: .skip PAGE_SIZE -pg1: .skip PAGE_SIZE -pg2: .skip PAGE_SIZE -pg3: .skip PAGE_SIZE -empty_bad_page: .skip PAGE_SIZE -empty_bad_page_table: .skip PAGE_SIZE + .globl empty_zero_page empty_zero_page: .skip PAGE_SIZE .global root_flags @@ -523,10 +172,10 @@ copy_prom_lvl14: ldd [%g2 + 0x8], %g4 std %g4, [%g3 + 0x8] ! Copy proms handler -/* Must determine whether we are on a sun4c MMU, SRMMU, or SUN4/400 MUTANT - * MMU so we can remap ourselves properly. DON'T TOUCH %l0 thru %l5 in these - * remapping routines, we need their values afterwards! +/* DON'T TOUCH %l0 thru %l5 in these remapping routines, + * we need their values afterwards! */ + /* Now check whether we are already mapped, if we * are we can skip all this garbage coming up. */ @@ -535,26 +184,29 @@ copy_prom_done: be go_to_highmem ! this will be a nop then nop - set LOAD_ADDR, %g6 + /* Validate that we are in fact running on an + * SRMMU based cpu. + */ + set 0x4000, %g6 cmp %g7, %g6 - bne remap_not_a_sun4 ! This is not a Sun4 + bne not_a_sun4 nop - or %g0, 0x1, %g1 - lduba [%g1] ASI_CONTROL, %g1 ! Only safe to try on Sun4. - subcc %g1, 0x24, %g0 ! Is this a mutant Sun4/400??? - be sun4_mutant_remap ! Ugh, it is... +halt_sun4_or_sun4c: + ld [%g7 + 0x68], %o1 + set sun4c_notsup, %o0 + sub %o0, %l6, %o0 + call %o1 nop - - b sun4_normal_remap ! regular sun4, 2 level mmu + ba halt_me nop -remap_not_a_sun4: - lda [%g0] ASI_M_MMUREGS, %g1 ! same as ASI_PTE on sun4c - and %g1, 0x1, %g1 ! Test SRMMU Enable bit ;-) - cmp %g1, 0x0 - be sun4c_remap ! A sun4c MMU or normal Sun4 +not_a_sun4: + lda [%g0] ASI_M_MMUREGS, %g1 + andcc %g1, 1, %g0 + be halt_sun4_or_sun4c nop + srmmu_remap: /* First, check for a viking (TI) module. */ set 0x40000000, %g2 @@ -660,72 +312,6 @@ srmmu_nviking: b go_to_highmem nop ! wheee.... - /* This remaps the kernel on Sun4/4xx machines - * that have the Sun Mutant Three Level MMU. - * It's like a platypus, Sun didn't have the - * SRMMU in conception so they kludged the three - * level logic in the regular Sun4 MMU probably. - * - * Basically, you take each entry in the top level - * directory that maps the low 3MB starting at - * address zero and put the mapping in the KERNBASE - * slots. These top level pgd's are called regmaps. - */ -sun4_mutant_remap: - or %g0, %g0, %g3 ! source base - sethi %hi(KERNBASE), %g4 ! destination base - or %g4, %lo(KERNBASE), %g4 - sethi %hi(0x300000), %g5 - or %g5, %lo(0x300000), %g5 ! upper bound 3MB - or %g0, 0x1, %l6 - sll %l6, 24, %l6 ! Regmap mapping size - add %g3, 0x2, %g3 ! Base magic - add %g4, 0x2, %g4 ! Base magic - - /* Main remapping loop on Sun4-Mutant-MMU. - * "I am not an animal..." -Famous Mutant Person - */ -sun4_mutant_loop: - lduha [%g3] ASI_REGMAP, %g2 ! Get lower entry - stha %g2, [%g4] ASI_REGMAP ! Store in high entry - add %g4, %l6, %g4 ! Move up high memory ptr - subcc %g3, %g5, %g0 ! Reached our limit? - blu sun4_mutant_loop ! Nope, loop again - add %g3, %l6, %g3 ! delay, Move up low ptr - b go_to_highmem ! Jump to high memory. - nop - - /* The following is for non-4/4xx sun4 MMU's. */ -sun4_normal_remap: - mov 0, %g3 ! source base - set KERNBASE, %g4 ! destination base - set 0x300000, %g5 ! upper bound 3MB - mov 1, %l6 - sll %l6, 18, %l6 ! sun4 mmu segmap size -sun4_normal_loop: - lduha [%g3] ASI_SEGMAP, %g6 ! load phys_seg - stha %g6, [%g4] ASI_SEGMAP ! stort new virt mapping - add %g3, %l6, %g3 ! increment source pointer - subcc %g3, %g5, %g0 ! reached limit? - blu sun4_normal_loop ! nope, loop again - add %g4, %l6, %g4 ! delay, increment dest ptr - b go_to_highmem - nop - - /* The following works for Sun4c MMU's */ -sun4c_remap: - mov 0, %g3 ! source base - set KERNBASE, %g4 ! destination base - set 0x300000, %g5 ! upper bound 3MB - mov 1, %l6 - sll %l6, 18, %l6 ! sun4c mmu segmap size -sun4c_remap_loop: - lda [%g3] ASI_SEGMAP, %g6 ! load phys_seg - sta %g6, [%g4] ASI_SEGMAP ! store new virt mapping - add %g3, %l6, %g3 ! Increment source ptr - subcc %g3, %g5, %g0 ! Reached limit? - bl sun4c_remap_loop ! Nope, loop again - add %g4, %l6, %g4 ! delay, Increment dest ptr /* Now do a non-relative jump so that PC is in high-memory */ go_to_highmem: @@ -750,35 +336,12 @@ execute_in_high_mem: sethi %hi(linux_dbvec), %g1 st %o1, [%g1 + %lo(linux_dbvec)] - ld [%o0 + 0x4], %o3 - and %o3, 0x3, %o5 ! get the version - - cmp %o3, 0x2 ! a v2 prom? - be found_version - nop - - /* [email protected] */ - cmp %o3, 0x3 ! a v3 prom? - be found_version - nop - -/* Old sun4's pass our load address into %o0 instead of the prom - * pointer. On sun4's you have to hard code the romvec pointer into - * your code. Sun probably still does that because they don't even - * trust their own "OpenBoot" specifications. - */ - set LOAD_ADDR, %g6 - cmp %o0, %g6 ! an old sun4? - be sun4_init - nop - -found_version: /* Get the machine type via the mysterious romvec node operations. */ - add %g7, 0x1c, %l1 + add %g7, 0x1c, %l1 ld [%l1], %l0 ld [%l0], %l0 - call %l0 + call %l0 or %g0, %g0, %o0 ! next_node(0) = first_node or %o0, %g0, %g6 @@ -786,28 +349,13 @@ found_version: or %o1, %lo(cputypvar), %o1 sethi %hi(cputypval), %o2 ! information, the string or %o2, %lo(cputypval), %o2 - ld [%l1], %l0 ! 'compatibility' tells + ld [%l1], %l0 ! 'compatible' tells ld [%l0 + 0xc], %l0 ! that we want 'sun4x' where - call %l0 ! x is one of '', 'c', 'm', - nop ! 'd' or 'e'. %o2 holds pointer + call %l0 ! x is one of 'm', 'd' or 'e'. + nop ! %o2 holds pointer ! to a buf where above string ! will get stored by the prom. - subcc %o0, %g0, %g0 - bpos got_prop ! Got the property - nop - - or %g6, %g0, %o0 - sethi %hi(cputypvar_sun4m), %o1 - or %o1, %lo(cputypvar_sun4m), %o1 - sethi %hi(cputypval), %o2 - or %o2, %lo(cputypval), %o2 - ld [%l1], %l0 - ld [%l0 + 0xc], %l0 - call %l0 - nop - -got_prop: #ifdef CONFIG_SPARC_LEON /* no cpu-type check is needed, it is a SPARC-LEON */ @@ -826,45 +374,29 @@ got_prop: /* Update boot_cpu_id only on boot cpu */ stub %g1, [%g2 + %lo(boot_cpu_id)] - ba sun4c_continue_boot + ba continue_boot nop #endif + +/* Check to cputype. We may be booted on a sun4u (64 bit box), + * and sun4d needs special treatment. + */ + set cputypval, %o2 ldub [%o2 + 0x4], %l1 - cmp %l1, ' ' - be 1f - cmp %l1, 'c' - be 1f - cmp %l1, 'm' - be 1f + cmp %l1, 'm' + be sun4m_init cmp %l1, 's' - be 1f + be sun4m_init cmp %l1, 'd' - be 1f + be sun4d_init cmp %l1, 'e' be no_sun4e_here ! Could be a sun4e. nop b no_sun4u_here ! AIEEE, a V9 sun4u... Get our BIG BROTHER kernel :)) nop -1: set cputypval, %l1 - ldub [%l1 + 0x4], %l1 - cmp %l1, 'm' ! Test for sun4d, sun4e ? - be sun4m_init - cmp %l1, 's' ! Treat sun4s as sun4m - be sun4m_init - cmp %l1, 'd' ! Let us see how the beast will die - be sun4d_init - nop - - /* Jump into mmu context zero. */ - set AC_CONTEXT, %g1 - stba %g0, [%g1] ASI_CONTROL - - b sun4c_continue_boot - nop - /* CPUID in bootbus can be found at PA 0xff0140000 */ #define SUN4D_BOOTBUS_CPUID 0xf0140000 @@ -892,66 +424,6 @@ sun4d_init: /* Fall through to sun4m_init */ sun4m_init: - /* XXX Fucking Cypress... */ - lda [%g0] ASI_M_MMUREGS, %g5 - srl %g5, 28, %g4 - - cmp %g4, 1 - bne 1f - srl %g5, 24, %g4 - - and %g4, 0xf, %g4 - cmp %g4, 7 /* This would be a HyperSparc. */ - - bne 2f - nop - -1: - -#define PATCH_IT(dst, src) \ - set (dst), %g5; \ - set (src), %g4; \ - ld [%g4], %g3; \ - st %g3, [%g5]; \ - ld [%g4+0x4], %g3; \ - st %g3, [%g5+0x4]; - - /* Signed multiply. */ - PATCH_IT(.mul, .mul_patch) - PATCH_IT(.mul+0x08, .mul_patch+0x08) - - /* Signed remainder. */ - PATCH_IT(.rem, .rem_patch) - PATCH_IT(.rem+0x08, .rem_patch+0x08) - PATCH_IT(.rem+0x10, .rem_patch+0x10) - PATCH_IT(.rem+0x18, .rem_patch+0x18) - PATCH_IT(.rem+0x20, .rem_patch+0x20) - PATCH_IT(.rem+0x28, .rem_patch+0x28) - - /* Signed division. */ - PATCH_IT(.div, .div_patch) - PATCH_IT(.div+0x08, .div_patch+0x08) - PATCH_IT(.div+0x10, .div_patch+0x10) - PATCH_IT(.div+0x18, .div_patch+0x18) - PATCH_IT(.div+0x20, .div_patch+0x20) - - /* Unsigned multiply. */ - PATCH_IT(.umul, .umul_patch) - PATCH_IT(.umul+0x08, .umul_patch+0x08) - - /* Unsigned remainder. */ - PATCH_IT(.urem, .urem_patch) - PATCH_IT(.urem+0x08, .urem_patch+0x08) - PATCH_IT(.urem+0x10, .urem_patch+0x10) - PATCH_IT(.urem+0x18, .urem_patch+0x18) - - /* Unsigned division. */ - PATCH_IT(.udiv, .udiv_patch) - PATCH_IT(.udiv+0x08, .udiv_patch+0x08) - PATCH_IT(.udiv+0x10, .udiv_patch+0x10) - -#undef PATCH_IT - /* Ok, the PROM could have done funny things and apple cider could still * be sitting in the fault status/address registers. Read them all to * clear them so we don't get magic faults later on. @@ -962,7 +434,7 @@ sun4m_init: srl %o1, 28, %o1 ! Get a type of the CPU subcc %o1, 4, %g0 ! TI: Viking or MicroSPARC - be sun4c_continue_boot + be continue_boot nop set AC_M_SFSR, %o0 @@ -972,7 +444,7 @@ sun4m_init: /* Fujitsu MicroSPARC-II has no asynchronous flavors of FARs */ subcc %o1, 0, %g0 - be sun4c_continue_boot + be continue_boot nop set AC_M_AFSR, %o0 @@ -982,8 +454,7 @@ sun4m_init: nop -sun4c_continue_boot: - +continue_boot: /* Aieee, now set PC and nPC, enable traps, give ourselves a stack and it's * show-time! @@ -1026,10 +497,7 @@ sun4c_continue_boot: mov %g0, %g3 stub %g3, [%g2 + %lo(boot_cpu_id)] -1: /* boot_cpu_id set. calculate boot_cpu_id4 = boot_cpu_id*4 */ - sll %g3, 2, %g3 - sethi %hi(boot_cpu_id4), %g2 - stub %g3, [%g2 + %lo(boot_cpu_id4)] +1: sll %g3, 2, %g3 /* Initialize the uwinmask value for init task just in case. * But first make current_set[boot_cpu_id] point to something useful. @@ -1165,19 +633,6 @@ sun4c_continue_boot: call halt_me nop -sun4_init: - sethi %hi(SUN4_PROM_VECTOR+0x84), %o1 - ld [%o1 + %lo(SUN4_PROM_VECTOR+0x84)], %o1 - set sun4_notsup, %o0 - call %o1 /* printf */ - nop - sethi %hi(SUN4_PROM_VECTOR+0xc4), %o1 - ld [%o1 + %lo(SUN4_PROM_VECTOR+0xc4)], %o1 - call %o1 /* exittomon */ - nop -1: ba 1b ! Cannot exit into KMON - nop - no_sun4e_here: ld [%g7 + 0x68], %o1 set sun4e_notsup, %o0 diff --git a/arch/sparc/kernel/head_64.S b/arch/sparc/kernel/head_64.S index 0d810c2f1d00..b42ddbf9651e 100644 --- a/arch/sparc/kernel/head_64.S +++ b/arch/sparc/kernel/head_64.S @@ -906,7 +906,7 @@ swapper_4m_tsb: * error and will instead write junk into the relocation and * you'll have an unbootable kernel. */ -#include "ttable.S" +#include "ttable_64.S" ! 0x0000000000428000 diff --git a/arch/sparc/kernel/idprom.c b/arch/sparc/kernel/idprom.c index 9167db40720e..6bd75012109d 100644 --- a/arch/sparc/kernel/idprom.c +++ b/arch/sparc/kernel/idprom.c @@ -25,22 +25,9 @@ static struct idprom idprom_buffer; * of the Sparc CPU and have a meaningful IDPROM machtype value that we * know about. See asm-sparc/machines.h for empirical constants. */ -static struct Sun_Machine_Models Sun_Machines[NUM_SUN_MACHINES] = { -/* First, Sun4's */ -{ .name = "Sun 4/100 Series", .id_machtype = (SM_SUN4 | SM_4_110) }, -{ .name = "Sun 4/200 Series", .id_machtype = (SM_SUN4 | SM_4_260) }, -{ .name = "Sun 4/300 Series", .id_machtype = (SM_SUN4 | SM_4_330) }, -{ .name = "Sun 4/400 Series", .id_machtype = (SM_SUN4 | SM_4_470) }, -/* Now Leon */ +static struct Sun_Machine_Models Sun_Machines[] = { +/* First, Leon */ { .name = "Leon3 System-on-a-Chip", .id_machtype = (M_LEON | M_LEON3_SOC) }, -/* Now, Sun4c's */ -{ .name = "Sun4c SparcStation 1", .id_machtype = (SM_SUN4C | SM_4C_SS1) }, -{ .name = "Sun4c SparcStation IPC", .id_machtype = (SM_SUN4C | SM_4C_IPC) }, -{ .name = "Sun4c SparcStation 1+", .id_machtype = (SM_SUN4C | SM_4C_SS1PLUS) }, -{ .name = "Sun4c SparcStation SLC", .id_machtype = (SM_SUN4C | SM_4C_SLC) }, -{ .name = "Sun4c SparcStation 2", .id_machtype = (SM_SUN4C | SM_4C_SS2) }, -{ .name = "Sun4c SparcStation ELC", .id_machtype = (SM_SUN4C | SM_4C_ELC) }, -{ .name = "Sun4c SparcStation IPX", .id_machtype = (SM_SUN4C | SM_4C_IPX) }, /* Finally, early Sun4m's */ { .name = "Sun4m SparcSystem600", .id_machtype = (SM_SUN4M | SM_4M_SS60) }, { .name = "Sun4m SparcStation10/20", .id_machtype = (SM_SUN4M | SM_4M_SS50) }, @@ -53,7 +40,7 @@ static void __init display_system_type(unsigned char machtype) char sysname[128]; register int i; - for (i = 0; i < NUM_SUN_MACHINES; i++) { + for (i = 0; i < ARRAY_SIZE(Sun_Machines); i++) { if (Sun_Machines[i].id_machtype == machtype) { if (machtype != (SM_SUN4M_OBP | 0x00) || prom_getproperty(prom_root_node, "banner-name", diff --git a/arch/sparc/kernel/ioport.c b/arch/sparc/kernel/ioport.c index 21bd73943f7f..a2846f5e32d8 100644 --- a/arch/sparc/kernel/ioport.c +++ b/arch/sparc/kernel/ioport.c @@ -50,6 +50,8 @@ #include <asm/io-unit.h> #include <asm/leon.h> +const struct sparc32_dma_ops *sparc32_dma_ops; + /* This function must make sure that caches and memory are coherent after DMA * On LEON systems without cache snooping it flushes the entire D-CACHE. */ @@ -229,7 +231,7 @@ _sparc_ioremap(struct resource *res, u32 bus, u32 pa, int sz) } pa &= PAGE_MASK; - sparc_mapiorange(bus, pa, res->start, resource_size(res)); + srmmu_mapiorange(bus, pa, res->start, resource_size(res)); return (void __iomem *)(unsigned long)(res->start + offset); } @@ -243,7 +245,7 @@ static void _sparc_free_io(struct resource *res) plen = resource_size(res); BUG_ON((plen & (PAGE_SIZE-1)) != 0); - sparc_unmapiorange(res->start, plen); + srmmu_unmapiorange(res->start, plen); release_resource(res); } @@ -292,13 +294,13 @@ static void *sbus_alloc_coherent(struct device *dev, size_t len, goto err_nova; } - // XXX The mmu_map_dma_area does this for us below, see comments. - // sparc_mapiorange(0, virt_to_phys(va), res->start, len_total); + // XXX The sbus_map_dma_area does this for us below, see comments. + // srmmu_mapiorange(0, virt_to_phys(va), res->start, len_total); /* * XXX That's where sdev would be used. Currently we load * all iommu tables with the same translations. */ - if (mmu_map_dma_area(dev, dma_addrp, va, res->start, len_total) != 0) + if (sbus_map_dma_area(dev, dma_addrp, va, res->start, len_total) != 0) goto err_noiommu; res->name = op->dev.of_node->name; @@ -343,7 +345,7 @@ static void sbus_free_coherent(struct device *dev, size_t n, void *p, kfree(res); pgv = virt_to_page(p); - mmu_unmap_dma_area(dev, ba, n); + sbus_unmap_dma_area(dev, ba, n); __free_pages(pgv, get_order(n)); } @@ -381,11 +383,6 @@ static int sbus_map_sg(struct device *dev, struct scatterlist *sg, int n, enum dma_data_direction dir, struct dma_attrs *attrs) { mmu_get_scsi_sgl(dev, sg, n); - - /* - * XXX sparc64 can return a partial length here. sun4c should do this - * but it currently panics if it can't fulfill the request - Anton - */ return n; } @@ -469,7 +466,7 @@ static void *pci32_alloc_coherent(struct device *dev, size_t len, printk("pci_alloc_consistent: cannot occupy 0x%lx", len_total); goto err_nova; } - sparc_mapiorange(0, virt_to_phys(va), res->start, len_total); + srmmu_mapiorange(0, virt_to_phys(va), res->start, len_total); *pba = virt_to_phys(va); /* equals virt_to_bus (R.I.P.) for us. */ return (void *) res->start; @@ -514,7 +511,7 @@ static void pci32_free_coherent(struct device *dev, size_t n, void *p, } dma_make_coherent(ba, n); - sparc_unmapiorange((unsigned long)p, n); + srmmu_unmapiorange((unsigned long)p, n); release_resource(res); kfree(res); diff --git a/arch/sparc/kernel/irq.h b/arch/sparc/kernel/irq.h index 5a021dd2f854..b66b6aad1d6d 100644 --- a/arch/sparc/kernel/irq.h +++ b/arch/sparc/kernel/irq.h @@ -1,6 +1,5 @@ #include <linux/platform_device.h> -#include <asm/btfixup.h> #include <asm/cpu_type.h> struct irq_bucket { @@ -10,6 +9,9 @@ struct irq_bucket { unsigned int pil; }; +#define SUN4M_HARD_INT(x) (0x000000001 << (x)) +#define SUN4M_SOFT_INT(x) (0x000010000 << (x)) + #define SUN4D_MAX_BOARD 10 #define SUN4D_MAX_IRQ ((SUN4D_MAX_BOARD + 2) << 5) @@ -41,52 +43,46 @@ struct sun4m_irq_global { extern struct sun4m_irq_percpu __iomem *sun4m_irq_percpu[SUN4M_NCPUS]; extern struct sun4m_irq_global __iomem *sun4m_irq_global; +/* The following definitions describe the individual platform features: */ +#define FEAT_L10_CLOCKSOURCE (1 << 0) /* L10 timer is used as a clocksource */ +#define FEAT_L10_CLOCKEVENT (1 << 1) /* L10 timer is used as a clockevent */ +#define FEAT_L14_ONESHOT (1 << 2) /* L14 timer clockevent can oneshot */ + /* - * Platform specific irq configuration + * Platform specific configuration * The individual platforms assign their platform * specifics in their init functions. */ -struct sparc_irq_config { - void (*init_timers)(irq_handler_t); +struct sparc_config { + void (*init_timers)(void); unsigned int (*build_device_irq)(struct platform_device *op, unsigned int real_irq); + + /* generic clockevent features - see FEAT_* above */ + int features; + + /* clock rate used for clock event timer */ + int clock_rate; + + /* one period for clock source timer */ + unsigned int cs_period; + + /* function to obtain offsett for cs period */ + unsigned int (*get_cycles_offset)(void); + + void (*clear_clock_irq)(void); + void (*load_profile_irq)(int cpu, unsigned int limit); }; -extern struct sparc_irq_config sparc_irq_config; +extern struct sparc_config sparc_config; unsigned int irq_alloc(unsigned int real_irq, unsigned int pil); void irq_link(unsigned int irq); void irq_unlink(unsigned int irq); void handler_irq(unsigned int pil, struct pt_regs *regs); -/* Dave Redman ([email protected]) - * changed these to function pointers.. it saves cycles and will allow - * the irq dependencies to be split into different files at a later date - * sun4c_irq.c, sun4m_irq.c etc so we could reduce the kernel size. - * Jakub Jelinek ([email protected]) - * Changed these to btfixup entities... It saves cycles :) - */ - -BTFIXUPDEF_CALL(void, clear_clock_irq, void) -BTFIXUPDEF_CALL(void, load_profile_irq, int, unsigned int) - -static inline void clear_clock_irq(void) -{ - BTFIXUP_CALL(clear_clock_irq)(); -} - -static inline void load_profile_irq(int cpu, int limit) -{ - BTFIXUP_CALL(load_profile_irq)(cpu, limit); -} +unsigned long leon_get_irqmask(unsigned int irq); #ifdef CONFIG_SMP -BTFIXUPDEF_CALL(void, set_cpu_int, int, int) -BTFIXUPDEF_CALL(void, clear_cpu_int, int, int) -BTFIXUPDEF_CALL(void, set_irq_udt, int) - -#define set_cpu_int(cpu,level) BTFIXUP_CALL(set_cpu_int)(cpu,level) -#define clear_cpu_int(cpu,level) BTFIXUP_CALL(clear_cpu_int)(cpu,level) -#define set_irq_udt(cpu) BTFIXUP_CALL(set_irq_udt)(cpu) /* All SUN4D IPIs are sent on this IRQ, may be shared with hard IRQs */ #define SUN4D_IPI_IRQ 13 diff --git a/arch/sparc/kernel/irq_32.c b/arch/sparc/kernel/irq_32.c index b2668afd1c34..ae04914f7774 100644 --- a/arch/sparc/kernel/irq_32.c +++ b/arch/sparc/kernel/irq_32.c @@ -23,16 +23,8 @@ #include "kernel.h" #include "irq.h" -#ifdef CONFIG_SMP -#define SMP_NOP2 "nop; nop;\n\t" -#define SMP_NOP3 "nop; nop; nop;\n\t" -#else -#define SMP_NOP2 -#define SMP_NOP3 -#endif /* SMP */ - /* platform specific irq setup */ -struct sparc_irq_config sparc_irq_config; +struct sparc_config sparc_config; unsigned long arch_local_irq_save(void) { @@ -41,7 +33,6 @@ unsigned long arch_local_irq_save(void) __asm__ __volatile__( "rd %%psr, %0\n\t" - SMP_NOP3 /* Sun4m + Cypress + SMP bug */ "or %0, %2, %1\n\t" "wr %1, 0, %%psr\n\t" "nop; nop; nop\n" @@ -59,7 +50,6 @@ void arch_local_irq_enable(void) __asm__ __volatile__( "rd %%psr, %0\n\t" - SMP_NOP3 /* Sun4m + Cypress + SMP bug */ "andn %0, %1, %0\n\t" "wr %0, 0, %%psr\n\t" "nop; nop; nop\n" @@ -76,7 +66,6 @@ void arch_local_irq_restore(unsigned long old_psr) __asm__ __volatile__( "rd %%psr, %0\n\t" "and %2, %1, %2\n\t" - SMP_NOP2 /* Sun4m + Cypress + SMP bug */ "andn %0, %1, %0\n\t" "wr %0, %2, %%psr\n\t" "nop; nop; nop\n" @@ -346,11 +335,6 @@ void sparc_floppy_irq(int irq, void *dev_id, struct pt_regs *regs) void __init init_IRQ(void) { switch (sparc_cpu_model) { - case sun4c: - case sun4: - sun4c_init_IRQ(); - break; - case sun4m: pcic_probe(); if (pcic_present()) @@ -371,6 +355,5 @@ void __init init_IRQ(void) prom_printf("Cannot initialize IRQs on this Sun machine..."); break; } - btfixup(); } diff --git a/arch/sparc/kernel/irq_64.c b/arch/sparc/kernel/irq_64.c index dff2c3d7d370..9bcbbe2c4e7e 100644 --- a/arch/sparc/kernel/irq_64.c +++ b/arch/sparc/kernel/irq_64.c @@ -799,7 +799,7 @@ static void kill_prom_timer(void) prom_limit0 = prom_timers->limit0; prom_limit1 = prom_timers->limit1; - /* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14. + /* Just as in sun4c PROM uses timer which ticks at IRQ 14. * We turn both off here just to be paranoid. */ prom_timers->limit0 = 0; diff --git a/arch/sparc/kernel/kernel.h b/arch/sparc/kernel/kernel.h index fd6c36b1df74..a86372d34587 100644 --- a/arch/sparc/kernel/kernel.h +++ b/arch/sparc/kernel/kernel.h @@ -32,9 +32,6 @@ extern void cpu_probe(void); /* traps_32.c */ extern void handle_hw_divzero(struct pt_regs *regs, unsigned long pc, unsigned long npc, unsigned long psr); -/* muldiv.c */ -extern int do_user_muldiv (struct pt_regs *, unsigned long); - /* irq_32.c */ extern struct irqaction static_irqaction[]; extern int static_irq_count; @@ -43,12 +40,7 @@ extern spinlock_t irq_action_lock; extern void unexpected_irq(int irq, void *dev_id, struct pt_regs * regs); extern void init_IRQ(void); -/* sun4c_irq.c */ -extern void sun4c_init_IRQ(void); - /* sun4m_irq.c */ -extern unsigned int lvl14_resolution; - extern void sun4m_init_IRQ(void); extern void sun4m_unmask_profile_irq(void); extern void sun4m_clear_profile_irq(int cpu); @@ -85,8 +77,6 @@ extern unsigned int patchme_maybe_smp_msg[]; extern void floppy_hardint(void); /* trampoline_32.S */ -extern int __smp4m_processor_id(void); -extern int __smp4d_processor_id(void); extern unsigned long sun4m_cpu_startup; extern unsigned long sun4d_cpu_startup; diff --git a/arch/sparc/kernel/leon_kernel.c b/arch/sparc/kernel/leon_kernel.c index 35e43673c453..77c1b916e4dd 100644 --- a/arch/sparc/kernel/leon_kernel.c +++ b/arch/sparc/kernel/leon_kernel.c @@ -10,6 +10,8 @@ #include <linux/of_platform.h> #include <linux/interrupt.h> #include <linux/of_device.h> +#include <linux/clocksource.h> +#include <linux/clockchips.h> #include <asm/oplib.h> #include <asm/timer.h> @@ -84,7 +86,7 @@ void leon_eirq_setup(unsigned int eirq) sparc_leon_eirq = eirq; } -static inline unsigned long get_irqmask(unsigned int irq) +unsigned long leon_get_irqmask(unsigned int irq) { unsigned long mask; @@ -210,7 +212,7 @@ unsigned int leon_build_device_irq(unsigned int real_irq, unsigned long mask; irq = 0; - mask = get_irqmask(real_irq); + mask = leon_get_irqmask(real_irq); if (mask == 0) goto out; @@ -250,7 +252,38 @@ void leon_update_virq_handling(unsigned int virq, irq_set_chip_data(virq, (void *)mask); } -void __init leon_init_timers(irq_handler_t counter_fn) +static u32 leon_cycles_offset(void) +{ + u32 rld, val, off; + rld = LEON3_BYPASS_LOAD_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx].rld); + val = LEON3_BYPASS_LOAD_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx].val); + off = rld - val; + return rld - val; +} + +#ifdef CONFIG_SMP + +/* smp clockevent irq */ +irqreturn_t leon_percpu_timer_ce_interrupt(int irq, void *unused) +{ + struct clock_event_device *ce; + int cpu = smp_processor_id(); + + leon_clear_profile_irq(cpu); + + ce = &per_cpu(sparc32_clockevent, cpu); + + irq_enter(); + if (ce->event_handler) + ce->event_handler(ce); + irq_exit(); + + return IRQ_HANDLED; +} + +#endif /* CONFIG_SMP */ + +void __init leon_init_timers(void) { int irq, eirq; struct device_node *rootnp, *np, *nnp; @@ -260,6 +293,14 @@ void __init leon_init_timers(irq_handler_t counter_fn) int ampopts; int err; + sparc_config.get_cycles_offset = leon_cycles_offset; + sparc_config.cs_period = 1000000 / HZ; + sparc_config.features |= FEAT_L10_CLOCKSOURCE; + +#ifndef CONFIG_SMP + sparc_config.features |= FEAT_L10_CLOCKEVENT; +#endif + leondebug_irq_disable = 0; leon_debug_irqout = 0; master_l10_counter = (unsigned int *)&dummy_master_l10_counter; @@ -369,7 +410,7 @@ void __init leon_init_timers(irq_handler_t counter_fn) leon_eirq_setup(eirq); irq = _leon_build_device_irq(NULL, leon3_gptimer_irq+leon3_gptimer_idx); - err = request_irq(irq, counter_fn, IRQF_TIMER, "timer", NULL); + err = request_irq(irq, timer_interrupt, IRQF_TIMER, "timer", NULL); if (err) { printk(KERN_ERR "unable to attach timer IRQ%d\n", irq); prom_halt(); @@ -386,7 +427,7 @@ void __init leon_init_timers(irq_handler_t counter_fn) */ local_irq_save(flags); patchme_maybe_smp_msg[0] = 0x01000000; /* NOP out the branch */ - local_flush_cache_all(); + local_ops->cache_all(); local_irq_restore(flags); } #endif @@ -401,7 +442,7 @@ void __init leon_init_timers(irq_handler_t counter_fn) /* Install per-cpu IRQ handler for broadcasted ticker */ irq = leon_build_device_irq(leon3_ticker_irq, handle_percpu_irq, "per-cpu", 0); - err = request_irq(irq, leon_percpu_timer_interrupt, + err = request_irq(irq, leon_percpu_timer_ce_interrupt, IRQF_PERCPU | IRQF_TIMER, "ticker", NULL); if (err) { @@ -422,13 +463,12 @@ bad: return; } -void leon_clear_clock_irq(void) +static void leon_clear_clock_irq(void) { } -void leon_load_profile_irq(int cpu, unsigned int limit) +static void leon_load_profile_irq(int cpu, unsigned int limit) { - BUG(); } void __init leon_trans_init(struct device_node *dp) @@ -457,25 +497,6 @@ void __init leon_node_init(struct device_node *dp, struct device_node ***nextp) } #ifdef CONFIG_SMP - -void leon_set_cpu_int(int cpu, int level) -{ - unsigned long mask; - mask = get_irqmask(level); - LEON3_BYPASS_STORE_PA(&leon3_irqctrl_regs->force[cpu], mask); -} - -static void leon_clear_ipi(int cpu, int level) -{ - unsigned long mask; - mask = get_irqmask(level); - LEON3_BYPASS_STORE_PA(&leon3_irqctrl_regs->force[cpu], mask<<16); -} - -static void leon_set_udt(int cpu) -{ -} - void leon_clear_profile_irq(int cpu) { } @@ -483,7 +504,7 @@ void leon_clear_profile_irq(int cpu) void leon_enable_irq_cpu(unsigned int irq_nr, unsigned int cpu) { unsigned long mask, flags, *addr; - mask = get_irqmask(irq_nr); + mask = leon_get_irqmask(irq_nr); spin_lock_irqsave(&leon_irq_lock, flags); addr = (unsigned long *)LEON_IMASK(cpu); LEON3_BYPASS_STORE_PA(addr, (LEON3_BYPASS_LOAD_PA(addr) | mask)); @@ -494,20 +515,11 @@ void leon_enable_irq_cpu(unsigned int irq_nr, unsigned int cpu) void __init leon_init_IRQ(void) { - sparc_irq_config.init_timers = leon_init_timers; - sparc_irq_config.build_device_irq = _leon_build_device_irq; - - BTFIXUPSET_CALL(clear_clock_irq, leon_clear_clock_irq, - BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(load_profile_irq, leon_load_profile_irq, - BTFIXUPCALL_NOP); - -#ifdef CONFIG_SMP - BTFIXUPSET_CALL(set_cpu_int, leon_set_cpu_int, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(clear_cpu_int, leon_clear_ipi, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(set_irq_udt, leon_set_udt, BTFIXUPCALL_NORM); -#endif - + sparc_config.init_timers = leon_init_timers; + sparc_config.build_device_irq = _leon_build_device_irq; + sparc_config.clock_rate = 1000000; + sparc_config.clear_clock_irq = leon_clear_clock_irq; + sparc_config.load_profile_irq = leon_load_profile_irq; } void __init leon_init(void) diff --git a/arch/sparc/kernel/leon_smp.c b/arch/sparc/kernel/leon_smp.c index 1210fde18740..29325bacba6f 100644 --- a/arch/sparc/kernel/leon_smp.c +++ b/arch/sparc/kernel/leon_smp.c @@ -23,6 +23,8 @@ #include <linux/pm.h> #include <linux/delay.h> #include <linux/gfp.h> +#include <linux/cpu.h> +#include <linux/clockchips.h> #include <asm/cacheflush.h> #include <asm/tlbflush.h> @@ -42,6 +44,7 @@ #include <asm/asi.h> #include <asm/leon.h> #include <asm/leon_amba.h> +#include <asm/timer.h> #include "kernel.h" @@ -68,24 +71,24 @@ static inline unsigned long do_swap(volatile unsigned long *ptr, return val; } -static void smp_setup_percpu_timer(void); - void __cpuinit leon_callin(void) { - int cpuid = hard_smpleon_processor_id(); + int cpuid = hard_smp_processor_id(); - local_flush_cache_all(); - local_flush_tlb_all(); + local_ops->cache_all(); + local_ops->tlb_all(); leon_configure_cache_smp(); + notify_cpu_starting(cpuid); + /* Get our local ticker going. */ - smp_setup_percpu_timer(); + register_percpu_ce(cpuid); calibrate_delay(); smp_store_cpu_info(cpuid); - local_flush_cache_all(); - local_flush_tlb_all(); + local_ops->cache_all(); + local_ops->tlb_all(); /* * Unblock the master CPU _only_ when the scheduler state @@ -96,8 +99,8 @@ void __cpuinit leon_callin(void) */ do_swap(&cpu_callin_map[cpuid], 1); - local_flush_cache_all(); - local_flush_tlb_all(); + local_ops->cache_all(); + local_ops->tlb_all(); /* Fix idle thread fields. */ __asm__ __volatile__("ld [%0], %%g6\n\t" : : "r"(¤t_set[cpuid]) @@ -140,8 +143,8 @@ void __init leon_configure_cache_smp(void) } } - local_flush_cache_all(); - local_flush_tlb_all(); + local_ops->cache_all(); + local_ops->tlb_all(); } void leon_smp_setbroadcast(unsigned int mask) @@ -196,8 +199,7 @@ void __init leon_boot_cpus(void) leon_smp_setbroadcast(1 << LEON3_IRQ_TICKER); leon_configure_cache_smp(); - smp_setup_percpu_timer(); - local_flush_cache_all(); + local_ops->cache_all(); } @@ -224,7 +226,7 @@ int __cpuinit leon_boot_one_cpu(int i) /* whirrr, whirrr, whirrrrrrrrr... */ printk(KERN_INFO "Starting CPU %d : (irqmp: 0x%x)\n", (unsigned int)i, (unsigned int)&leon3_irqctrl_regs->mpstatus); - local_flush_cache_all(); + local_ops->cache_all(); /* Make sure all IRQs are of from the start for this new CPU */ LEON_BYPASS_STORE_PA(&leon3_irqctrl_regs->mask[i], 0); @@ -249,7 +251,7 @@ int __cpuinit leon_boot_one_cpu(int i) leon_enable_irq_cpu(leon_ipi_irq, i); } - local_flush_cache_all(); + local_ops->cache_all(); return 0; } @@ -269,7 +271,7 @@ void __init leon_smp_done(void) } } *prev = first; - local_flush_cache_all(); + local_ops->cache_all(); /* Free unneeded trap tables */ if (!cpu_present(1)) { @@ -335,7 +337,7 @@ static void __init leon_ipi_init(void) local_irq_save(flags); trap_table = &sparc_ttable[SP_TRAP_IRQ1 + (leon_ipi_irq - 1)]; trap_table->inst_three += smpleon_ipi - real_irq_entry; - local_flush_cache_all(); + local_ops->cache_all(); local_irq_restore(flags); for_each_possible_cpu(cpu) { @@ -344,6 +346,13 @@ static void __init leon_ipi_init(void) } } +static void leon_send_ipi(int cpu, int level) +{ + unsigned long mask; + mask = leon_get_irqmask(level); + LEON3_BYPASS_STORE_PA(&leon3_irqctrl_regs->force[cpu], mask); +} + static void leon_ipi_single(int cpu) { struct leon_ipi_work *work = &per_cpu(leon_ipi_work, cpu); @@ -352,7 +361,7 @@ static void leon_ipi_single(int cpu) work->single = 1; /* Generate IRQ on the CPU */ - set_cpu_int(cpu, leon_ipi_irq); + leon_send_ipi(cpu, leon_ipi_irq); } static void leon_ipi_mask_one(int cpu) @@ -363,7 +372,7 @@ static void leon_ipi_mask_one(int cpu) work->msk = 1; /* Generate IRQ on the CPU */ - set_cpu_int(cpu, leon_ipi_irq); + leon_send_ipi(cpu, leon_ipi_irq); } static void leon_ipi_resched(int cpu) @@ -374,7 +383,7 @@ static void leon_ipi_resched(int cpu) work->resched = 1; /* Generate IRQ on the CPU (any IRQ will cause resched) */ - set_cpu_int(cpu, leon_ipi_irq); + leon_send_ipi(cpu, leon_ipi_irq); } void leonsmp_ipi_interrupt(void) @@ -446,7 +455,7 @@ static void leon_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1, if (cpumask_test_cpu(i, &mask)) { ccall_info.processors_in[i] = 0; ccall_info.processors_out[i] = 0; - set_cpu_int(i, LEON3_IRQ_CROSS_CALL); + leon_send_ipi(i, LEON3_IRQ_CROSS_CALL); } } @@ -489,68 +498,19 @@ void leon_cross_call_irq(void) ccall_info.processors_out[i] = 1; } -irqreturn_t leon_percpu_timer_interrupt(int irq, void *unused) -{ - int cpu = smp_processor_id(); - - leon_clear_profile_irq(cpu); - - profile_tick(CPU_PROFILING); - - if (!--prof_counter(cpu)) { - int user = user_mode(get_irq_regs()); - - update_process_times(user); - - prof_counter(cpu) = prof_multiplier(cpu); - } - - return IRQ_HANDLED; -} - -static void __init smp_setup_percpu_timer(void) -{ - int cpu = smp_processor_id(); - - prof_counter(cpu) = prof_multiplier(cpu) = 1; -} - -void __init leon_blackbox_id(unsigned *addr) -{ - int rd = *addr & 0x3e000000; - int rs1 = rd >> 11; - - /* patch places where ___b_hard_smp_processor_id appears */ - addr[0] = 0x81444000 | rd; /* rd %asr17, reg */ - addr[1] = 0x8130201c | rd | rs1; /* srl reg, 0x1c, reg */ - addr[2] = 0x01000000; /* nop */ -} - -void __init leon_blackbox_current(unsigned *addr) -{ - int rd = *addr & 0x3e000000; - int rs1 = rd >> 11; - - /* patch LOAD_CURRENT macro where ___b_load_current appears */ - addr[0] = 0x81444000 | rd; /* rd %asr17, reg */ - addr[2] = 0x8130201c | rd | rs1; /* srl reg, 0x1c, reg */ - addr[4] = 0x81282002 | rd | rs1; /* sll reg, 0x2, reg */ - -} +static const struct sparc32_ipi_ops leon_ipi_ops = { + .cross_call = leon_cross_call, + .resched = leon_ipi_resched, + .single = leon_ipi_single, + .mask_one = leon_ipi_mask_one, +}; void __init leon_init_smp(void) { /* Patch ipi15 trap table */ t_nmi[1] = t_nmi[1] + (linux_trap_ipi15_leon - linux_trap_ipi15_sun4m); - BTFIXUPSET_BLACKBOX(hard_smp_processor_id, leon_blackbox_id); - BTFIXUPSET_BLACKBOX(load_current, leon_blackbox_current); - BTFIXUPSET_CALL(smp_cross_call, leon_cross_call, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(__hard_smp_processor_id, __leon_processor_id, - BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(smp_ipi_resched, leon_ipi_resched, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(smp_ipi_single, leon_ipi_single, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(smp_ipi_mask_one, leon_ipi_mask_one, BTFIXUPCALL_NORM); + sparc32_ipi_ops = &leon_ipi_ops; } #endif /* CONFIG_SPARC_LEON */ diff --git a/arch/sparc/kernel/module.c b/arch/sparc/kernel/module.c index 276359e1ff56..15e0a1693976 100644 --- a/arch/sparc/kernel/module.c +++ b/arch/sparc/kernel/module.c @@ -32,26 +32,11 @@ static void *module_map(unsigned long size) GFP_KERNEL, PAGE_KERNEL, -1, __builtin_return_address(0)); } - -static char *dot2underscore(char *name) -{ - return name; -} #else static void *module_map(unsigned long size) { return vmalloc(size); } - -/* Replace references to .func with _Func */ -static char *dot2underscore(char *name) -{ - if (name[0] == '.') { - name[0] = '_'; - name[1] = toupper(name[1]); - } - return name; -} #endif /* CONFIG_SPARC64 */ void *module_alloc(unsigned long size) @@ -93,12 +78,8 @@ int module_frob_arch_sections(Elf_Ehdr *hdr, for (i = 1; i < sechdrs[symidx].sh_size / sizeof(Elf_Sym); i++) { if (sym[i].st_shndx == SHN_UNDEF) { - if (ELF_ST_TYPE(sym[i].st_info) == STT_REGISTER) { + if (ELF_ST_TYPE(sym[i].st_info) == STT_REGISTER) sym[i].st_shndx = SHN_ABS; - } else { - char *name = strtab + sym[i].st_name; - dot2underscore(name); - } } } return 0; diff --git a/arch/sparc/kernel/muldiv.c b/arch/sparc/kernel/muldiv.c deleted file mode 100644 index f7db516b07d8..000000000000 --- a/arch/sparc/kernel/muldiv.c +++ /dev/null @@ -1,238 +0,0 @@ -/* - * muldiv.c: Hardware multiply/division illegal instruction trap - * for sun4c/sun4 (which do not have those instructions) - * - * Copyright (C) 1996 Jakub Jelinek ([email protected]) - * Copyright (C) 1996 David S. Miller ([email protected]) - * - * 2004-12-25 Krzysztof Helt ([email protected]) - * - fixed registers constrains in inline assembly declarations - */ - -#include <linux/kernel.h> -#include <linux/sched.h> -#include <linux/mm.h> -#include <asm/ptrace.h> -#include <asm/processor.h> -#include <asm/uaccess.h> - -#include "kernel.h" - -/* #define DEBUG_MULDIV */ - -static inline int has_imm13(int insn) -{ - return (insn & 0x2000); -} - -static inline int is_foocc(int insn) -{ - return (insn & 0x800000); -} - -static inline int sign_extend_imm13(int imm) -{ - return imm << 19 >> 19; -} - -static inline void advance(struct pt_regs *regs) -{ - regs->pc = regs->npc; - regs->npc += 4; -} - -static inline void maybe_flush_windows(unsigned int rs1, unsigned int rs2, - unsigned int rd) -{ - if(rs2 >= 16 || rs1 >= 16 || rd >= 16) { - /* Wheee... */ - __asm__ __volatile__("save %sp, -0x40, %sp\n\t" - "save %sp, -0x40, %sp\n\t" - "save %sp, -0x40, %sp\n\t" - "save %sp, -0x40, %sp\n\t" - "save %sp, -0x40, %sp\n\t" - "save %sp, -0x40, %sp\n\t" - "save %sp, -0x40, %sp\n\t" - "restore; restore; restore; restore;\n\t" - "restore; restore; restore;\n\t"); - } -} - -#define fetch_reg(reg, regs) ({ \ - struct reg_window32 __user *win; \ - register unsigned long ret; \ - \ - if (!(reg)) ret = 0; \ - else if ((reg) < 16) { \ - ret = regs->u_regs[(reg)]; \ - } else { \ - /* Ho hum, the slightly complicated case. */ \ - win = (struct reg_window32 __user *)regs->u_regs[UREG_FP];\ - if (get_user (ret, &win->locals[(reg) - 16])) return -1;\ - } \ - ret; \ -}) - -static inline int -store_reg(unsigned int result, unsigned int reg, struct pt_regs *regs) -{ - struct reg_window32 __user *win; - - if (!reg) - return 0; - if (reg < 16) { - regs->u_regs[reg] = result; - return 0; - } else { - /* need to use put_user() in this case: */ - win = (struct reg_window32 __user *) regs->u_regs[UREG_FP]; - return (put_user(result, &win->locals[reg - 16])); - } -} - -/* Should return 0 if mul/div emulation succeeded and SIGILL should - * not be issued. - */ -int do_user_muldiv(struct pt_regs *regs, unsigned long pc) -{ - unsigned int insn; - int inst; - unsigned int rs1, rs2, rdv; - - if (!pc) - return -1; /* This happens to often, I think */ - if (get_user (insn, (unsigned int __user *)pc)) - return -1; - if ((insn & 0xc1400000) != 0x80400000) - return -1; - inst = ((insn >> 19) & 0xf); - if ((inst & 0xe) != 10 && (inst & 0xe) != 14) - return -1; - - /* Now we know we have to do something with umul, smul, udiv or sdiv */ - rs1 = (insn >> 14) & 0x1f; - rs2 = insn & 0x1f; - rdv = (insn >> 25) & 0x1f; - if (has_imm13(insn)) { - maybe_flush_windows(rs1, 0, rdv); - rs2 = sign_extend_imm13(insn); - } else { - maybe_flush_windows(rs1, rs2, rdv); - rs2 = fetch_reg(rs2, regs); - } - rs1 = fetch_reg(rs1, regs); - switch (inst) { - case 10: /* umul */ -#ifdef DEBUG_MULDIV - printk ("unsigned muldiv: 0x%x * 0x%x = ", rs1, rs2); -#endif - __asm__ __volatile__ ("\n\t" - "mov %0, %%o0\n\t" - "call .umul\n\t" - " mov %1, %%o1\n\t" - "mov %%o0, %0\n\t" - "mov %%o1, %1\n\t" - : "=r" (rs1), "=r" (rs2) - : "0" (rs1), "1" (rs2) - : "o0", "o1", "o2", "o3", "o4", "o5", "o7", "cc"); -#ifdef DEBUG_MULDIV - printk ("0x%x%08x\n", rs2, rs1); -#endif - if (store_reg(rs1, rdv, regs)) - return -1; - regs->y = rs2; - break; - case 11: /* smul */ -#ifdef DEBUG_MULDIV - printk ("signed muldiv: 0x%x * 0x%x = ", rs1, rs2); -#endif - __asm__ __volatile__ ("\n\t" - "mov %0, %%o0\n\t" - "call .mul\n\t" - " mov %1, %%o1\n\t" - "mov %%o0, %0\n\t" - "mov %%o1, %1\n\t" - : "=r" (rs1), "=r" (rs2) - : "0" (rs1), "1" (rs2) - : "o0", "o1", "o2", "o3", "o4", "o5", "o7", "cc"); -#ifdef DEBUG_MULDIV - printk ("0x%x%08x\n", rs2, rs1); -#endif - if (store_reg(rs1, rdv, regs)) - return -1; - regs->y = rs2; - break; - case 14: /* udiv */ -#ifdef DEBUG_MULDIV - printk ("unsigned muldiv: 0x%x%08x / 0x%x = ", regs->y, rs1, rs2); -#endif - if (!rs2) { -#ifdef DEBUG_MULDIV - printk ("DIVISION BY ZERO\n"); -#endif - handle_hw_divzero (regs, pc, regs->npc, regs->psr); - return 0; - } - __asm__ __volatile__ ("\n\t" - "mov %2, %%o0\n\t" - "mov %0, %%o1\n\t" - "mov %%g0, %%o2\n\t" - "call __udivdi3\n\t" - " mov %1, %%o3\n\t" - "mov %%o1, %0\n\t" - "mov %%o0, %1\n\t" - : "=r" (rs1), "=r" (rs2) - : "r" (regs->y), "0" (rs1), "1" (rs2) - : "o0", "o1", "o2", "o3", "o4", "o5", "o7", - "g1", "g2", "g3", "cc"); -#ifdef DEBUG_MULDIV - printk ("0x%x\n", rs1); -#endif - if (store_reg(rs1, rdv, regs)) - return -1; - break; - case 15: /* sdiv */ -#ifdef DEBUG_MULDIV - printk ("signed muldiv: 0x%x%08x / 0x%x = ", regs->y, rs1, rs2); -#endif - if (!rs2) { -#ifdef DEBUG_MULDIV - printk ("DIVISION BY ZERO\n"); -#endif - handle_hw_divzero (regs, pc, regs->npc, regs->psr); - return 0; - } - __asm__ __volatile__ ("\n\t" - "mov %2, %%o0\n\t" - "mov %0, %%o1\n\t" - "mov %%g0, %%o2\n\t" - "call __divdi3\n\t" - " mov %1, %%o3\n\t" - "mov %%o1, %0\n\t" - "mov %%o0, %1\n\t" - : "=r" (rs1), "=r" (rs2) - : "r" (regs->y), "0" (rs1), "1" (rs2) - : "o0", "o1", "o2", "o3", "o4", "o5", "o7", - "g1", "g2", "g3", "cc"); -#ifdef DEBUG_MULDIV - printk ("0x%x\n", rs1); -#endif - if (store_reg(rs1, rdv, regs)) - return -1; - break; - } - if (is_foocc (insn)) { - regs->psr &= ~PSR_ICC; - if ((inst & 0xe) == 14) { - /* ?div */ - if (rs2) regs->psr |= PSR_V; - } - if (!rs1) regs->psr |= PSR_Z; - if (((int)rs1) < 0) regs->psr |= PSR_N; -#ifdef DEBUG_MULDIV - printk ("psr muldiv: %08x\n", regs->psr); -#endif - } - advance(regs); - return 0; -} diff --git a/arch/sparc/kernel/of_device_32.c b/arch/sparc/kernel/of_device_32.c index 4ee8ce0d5d8d..185aa96fa5be 100644 --- a/arch/sparc/kernel/of_device_32.c +++ b/arch/sparc/kernel/of_device_32.c @@ -356,7 +356,7 @@ static struct platform_device * __init scan_one_device(struct device_node *dp, op->archdata.num_irqs = len / sizeof(struct linux_prom_irqs); for (i = 0; i < op->archdata.num_irqs; i++) op->archdata.irqs[i] = - sparc_irq_config.build_device_irq(op, intr[i].pri); + sparc_config.build_device_irq(op, intr[i].pri); } else { const unsigned int *irq = of_get_property(dp, "interrupts", &len); @@ -365,7 +365,7 @@ static struct platform_device * __init scan_one_device(struct device_node *dp, op->archdata.num_irqs = len / sizeof(unsigned int); for (i = 0; i < op->archdata.num_irqs; i++) op->archdata.irqs[i] = - sparc_irq_config.build_device_irq(op, irq[i]); + sparc_config.build_device_irq(op, irq[i]); } else { op->archdata.num_irqs = 0; } diff --git a/arch/sparc/kernel/pcic.c b/arch/sparc/kernel/pcic.c index fcc148effaac..ded3f6090c3f 100644 --- a/arch/sparc/kernel/pcic.c +++ b/arch/sparc/kernel/pcic.c @@ -703,31 +703,28 @@ static void pcic_clear_clock_irq(void) pcic_timer_dummy = readl(pcic0.pcic_regs+PCI_SYS_LIMIT); } -static irqreturn_t pcic_timer_handler (int irq, void *h) +/* CPU frequency is 100 MHz, timer increments every 4 CPU clocks */ +#define USECS_PER_JIFFY (1000000 / HZ) +#define TICK_TIMER_LIMIT ((100 * 1000000 / 4) / HZ) + +static unsigned int pcic_cycles_offset(void) { - pcic_clear_clock_irq(); - xtime_update(1); -#ifndef CONFIG_SMP - update_process_times(user_mode(get_irq_regs())); -#endif - return IRQ_HANDLED; -} + u32 value, count; -#define USECS_PER_JIFFY 10000 /* We have 100HZ "standard" timer for sparc */ -#define TICK_TIMER_LIMIT ((100*1000000/4)/100) + value = readl(pcic0.pcic_regs + PCI_SYS_COUNTER); + count = value & ~PCI_SYS_COUNTER_OVERFLOW; -u32 pci_gettimeoffset(void) -{ + if (value & PCI_SYS_COUNTER_OVERFLOW) + count += TICK_TIMER_LIMIT; /* - * We divide all by 100 + * We divide all by HZ * to have microsecond resolution and to avoid overflow */ - unsigned long count = - readl(pcic0.pcic_regs+PCI_SYS_COUNTER) & ~PCI_SYS_COUNTER_OVERFLOW; - count = ((count/100)*USECS_PER_JIFFY) / (TICK_TIMER_LIMIT/100); - return count * 1000; -} + count = ((count / HZ) * USECS_PER_JIFFY) / (TICK_TIMER_LIMIT / HZ); + /* Coordinate with the sparc_config.clock_rate setting */ + return count * 2; +} void __init pci_time_init(void) { @@ -736,9 +733,16 @@ void __init pci_time_init(void) int timer_irq, irq; int err; - do_arch_gettimeoffset = pci_gettimeoffset; - - btfixup(); +#ifndef CONFIG_SMP + /* + * The clock_rate is in SBUS dimension. + * We take into account this in pcic_cycles_offset() + */ + sparc_config.clock_rate = SBUS_CLOCK_RATE / HZ; + sparc_config.features |= FEAT_L10_CLOCKEVENT; +#endif + sparc_config.features |= FEAT_L10_CLOCKSOURCE; + sparc_config.get_cycles_offset = pcic_cycles_offset; writel (TICK_TIMER_LIMIT, pcic->pcic_regs+PCI_SYS_LIMIT); /* PROM should set appropriate irq */ @@ -747,7 +751,7 @@ void __init pci_time_init(void) writel (PCI_COUNTER_IRQ_SET(timer_irq, 0), pcic->pcic_regs+PCI_COUNTER_IRQ); irq = pcic_build_device_irq(NULL, timer_irq); - err = request_irq(irq, pcic_timer_handler, + err = request_irq(irq, timer_interrupt, IRQF_TIMER, "timer", NULL); if (err) { prom_printf("time_init: unable to attach IRQ%d\n", timer_irq); @@ -875,10 +879,9 @@ static void pcic_load_profile_irq(int cpu, unsigned int limit) void __init sun4m_pci_init_IRQ(void) { - sparc_irq_config.build_device_irq = pcic_build_device_irq; - - BTFIXUPSET_CALL(clear_clock_irq, pcic_clear_clock_irq, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(load_profile_irq, pcic_load_profile_irq, BTFIXUPCALL_NORM); + sparc_config.build_device_irq = pcic_build_device_irq; + sparc_config.clear_clock_irq = pcic_clear_clock_irq; + sparc_config.load_profile_irq = pcic_load_profile_irq; } int pcibios_assign_resource(struct pci_dev *pdev, int resource) diff --git a/arch/sparc/kernel/process_32.c b/arch/sparc/kernel/process_32.c index efa07542e85f..fe6787cc62fc 100644 --- a/arch/sparc/kernel/process_32.c +++ b/arch/sparc/kernel/process_32.c @@ -67,8 +67,6 @@ struct thread_info *current_set[NR_CPUS]; #ifndef CONFIG_SMP -#define SUN4C_FAULT_HIGH 100 - /* * the idle loop on a Sparc... ;) */ @@ -76,36 +74,6 @@ void cpu_idle(void) { /* endless idle loop with no priority at all */ for (;;) { - if (ARCH_SUN4C) { - static int count = HZ; - static unsigned long last_jiffies; - static unsigned long last_faults; - static unsigned long fps; - unsigned long now; - unsigned long faults; - - extern unsigned long sun4c_kernel_faults; - extern void sun4c_grow_kernel_ring(void); - - local_irq_disable(); - now = jiffies; - count -= (now - last_jiffies); - last_jiffies = now; - if (count < 0) { - count += HZ; - faults = sun4c_kernel_faults; - fps = (fps + (faults - last_faults)) >> 1; - last_faults = faults; -#if 0 - printk("kernel faults / second = %ld\n", fps); -#endif - if (fps >= SUN4C_FAULT_HIGH) { - sun4c_grow_kernel_ring(); - } - } - local_irq_enable(); - } - if (pm_idle) { while (!need_resched()) (*pm_idle)(); @@ -114,7 +82,6 @@ void cpu_idle(void) cpu_relax(); } schedule_preempt_disabled(); - check_pgt_cache(); } } @@ -137,7 +104,6 @@ void cpu_idle(void) cpu_relax(); } schedule_preempt_disabled(); - check_pgt_cache(); } } @@ -179,88 +145,6 @@ void machine_power_off(void) machine_halt(); } -#if 0 - -static DEFINE_SPINLOCK(sparc_backtrace_lock); - -void __show_backtrace(unsigned long fp) -{ - struct reg_window32 *rw; - unsigned long flags; - int cpu = smp_processor_id(); - - spin_lock_irqsave(&sparc_backtrace_lock, flags); - - rw = (struct reg_window32 *)fp; - while(rw && (((unsigned long) rw) >= PAGE_OFFSET) && - !(((unsigned long) rw) & 0x7)) { - printk("CPU[%d]: ARGS[%08lx,%08lx,%08lx,%08lx,%08lx,%08lx] " - "FP[%08lx] CALLER[%08lx]: ", cpu, - rw->ins[0], rw->ins[1], rw->ins[2], rw->ins[3], - rw->ins[4], rw->ins[5], - rw->ins[6], - rw->ins[7]); - printk("%pS\n", (void *) rw->ins[7]); - rw = (struct reg_window32 *) rw->ins[6]; - } - spin_unlock_irqrestore(&sparc_backtrace_lock, flags); -} - -#define __SAVE __asm__ __volatile__("save %sp, -0x40, %sp\n\t") -#define __RESTORE __asm__ __volatile__("restore %g0, %g0, %g0\n\t") -#define __GET_FP(fp) __asm__ __volatile__("mov %%i6, %0" : "=r" (fp)) - -void show_backtrace(void) -{ - unsigned long fp; - - __SAVE; __SAVE; __SAVE; __SAVE; - __SAVE; __SAVE; __SAVE; __SAVE; - __RESTORE; __RESTORE; __RESTORE; __RESTORE; - __RESTORE; __RESTORE; __RESTORE; __RESTORE; - - __GET_FP(fp); - - __show_backtrace(fp); -} - -#ifdef CONFIG_SMP -void smp_show_backtrace_all_cpus(void) -{ - xc0((smpfunc_t) show_backtrace); - show_backtrace(); -} -#endif - -void show_stackframe(struct sparc_stackf *sf) -{ - unsigned long size; - unsigned long *stk; - int i; - - printk("l0: %08lx l1: %08lx l2: %08lx l3: %08lx " - "l4: %08lx l5: %08lx l6: %08lx l7: %08lx\n", - sf->locals[0], sf->locals[1], sf->locals[2], sf->locals[3], - sf->locals[4], sf->locals[5], sf->locals[6], sf->locals[7]); - printk("i0: %08lx i1: %08lx i2: %08lx i3: %08lx " - "i4: %08lx i5: %08lx fp: %08lx i7: %08lx\n", - sf->ins[0], sf->ins[1], sf->ins[2], sf->ins[3], - sf->ins[4], sf->ins[5], (unsigned long)sf->fp, sf->callers_pc); - printk("sp: %08lx x0: %08lx x1: %08lx x2: %08lx " - "x3: %08lx x4: %08lx x5: %08lx xx: %08lx\n", - (unsigned long)sf->structptr, sf->xargs[0], sf->xargs[1], - sf->xargs[2], sf->xargs[3], sf->xargs[4], sf->xargs[5], - sf->xxargs[0]); - size = ((unsigned long)sf->fp) - ((unsigned long)sf); - size -= STACKFRAME_SZ; - stk = (unsigned long *)((unsigned long)sf + STACKFRAME_SZ); - i = 0; - do { - printk("s%d: %08lx\n", i++, *stk++); - } while ((size -= sizeof(unsigned long))); -} -#endif - void show_regs(struct pt_regs *r) { struct reg_window32 *rw = (struct reg_window32 *) r->u_regs[14]; diff --git a/arch/sparc/kernel/rtrap_32.S b/arch/sparc/kernel/rtrap_32.S index 5f5f74c2c2ca..7abc24e2bf1a 100644 --- a/arch/sparc/kernel/rtrap_32.S +++ b/arch/sparc/kernel/rtrap_32.S @@ -128,13 +128,12 @@ rtrap_patch2: and %glob_tmp, 0xff, %glob_tmp wr %glob_tmp, 0x0, %wim - /* Here comes the architecture specific - * branch to the user stack checking routine - * for return from traps. - */ - .globl rtrap_mmu_patchme -rtrap_mmu_patchme: b sun4c_rett_stackchk - andcc %fp, 0x7, %g0 + /* Here comes the architecture specific + * branch to the user stack checking routine + * for return from traps. + */ + b srmmu_rett_stackchk + andcc %fp, 0x7, %g0 ret_trap_userwins_ok: LOAD_PT_PRIV(sp, t_psr, t_pc, t_npc) @@ -225,69 +224,6 @@ ret_trap_user_stack_is_bolixed: b signal_p ld [%curptr + TI_FLAGS], %g2 -sun4c_rett_stackchk: - be 1f - and %fp, 0xfff, %g1 ! delay slot - - b ret_trap_user_stack_is_bolixed + 0x4 - wr %t_wim, 0x0, %wim - - /* See if we have to check the sanity of one page or two */ -1: - add %g1, 0x38, %g1 - sra %fp, 29, %g2 - add %g2, 0x1, %g2 - andncc %g2, 0x1, %g0 - be 1f - andncc %g1, 0xff8, %g0 - - /* %sp is in vma hole, yuck */ - b ret_trap_user_stack_is_bolixed + 0x4 - wr %t_wim, 0x0, %wim - -1: - be sun4c_rett_onepage /* Only one page to check */ - lda [%fp] ASI_PTE, %g2 - -sun4c_rett_twopages: - add %fp, 0x38, %g1 - sra %g1, 29, %g2 - add %g2, 0x1, %g2 - andncc %g2, 0x1, %g0 - be 1f - lda [%g1] ASI_PTE, %g2 - - /* Second page is in vma hole */ - b ret_trap_user_stack_is_bolixed + 0x4 - wr %t_wim, 0x0, %wim - -1: - srl %g2, 29, %g2 - andcc %g2, 0x4, %g0 - bne sun4c_rett_onepage - lda [%fp] ASI_PTE, %g2 - - /* Second page has bad perms */ - b ret_trap_user_stack_is_bolixed + 0x4 - wr %t_wim, 0x0, %wim - -sun4c_rett_onepage: - srl %g2, 29, %g2 - andcc %g2, 0x4, %g0 - bne,a 1f - restore %g0, %g0, %g0 - - /* A page had bad page permissions, losing... */ - b ret_trap_user_stack_is_bolixed + 0x4 - wr %t_wim, 0x0, %wim - - /* Whee, things are ok, load the window and continue. */ -1: - LOAD_WINDOW(sp) - - b ret_trap_userwins_ok - save %g0, %g0, %g0 - .globl srmmu_rett_stackchk srmmu_rett_stackchk: bne ret_trap_user_stack_is_bolixed diff --git a/arch/sparc/kernel/rtrap_64.S b/arch/sparc/kernel/rtrap_64.S index 77f1b95e0806..afa2a9e3d0a0 100644 --- a/arch/sparc/kernel/rtrap_64.S +++ b/arch/sparc/kernel/rtrap_64.S @@ -20,11 +20,6 @@ .text .align 32 -__handle_softirq: - call do_softirq - nop - ba,a,pt %xcc, __handle_softirq_continue - nop __handle_preemption: call schedule wrpr %g0, RTRAP_PSTATE, %pstate @@ -78,20 +73,8 @@ rtrap_nmi: ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1 .globl rtrap_irq, rtrap, irqsz_patchme, rtrap_xcall rtrap_irq: rtrap: -#ifndef CONFIG_SMP - sethi %hi(__cpu_data), %l0 - lduw [%l0 + %lo(__cpu_data)], %l1 -#else - sethi %hi(__cpu_data), %l0 - or %l0, %lo(__cpu_data), %l0 - lduw [%l0 + %g5], %l1 -#endif - cmp %l1, 0 - /* mm/ultra.S:xcall_report_regs KNOWS about this load. */ - bne,pn %icc, __handle_softirq - ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1 -__handle_softirq_continue: + ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1 rtrap_xcall: sethi %hi(0xf << 20), %l4 and %l1, %l4, %l4 diff --git a/arch/sparc/kernel/setup_32.c b/arch/sparc/kernel/setup_32.c index d444468b27f6..c052313f4dc5 100644 --- a/arch/sparc/kernel/setup_32.c +++ b/arch/sparc/kernel/setup_32.c @@ -42,7 +42,6 @@ #include <asm/vaddrs.h> #include <asm/mbus.h> #include <asm/idprom.h> -#include <asm/machines.h> #include <asm/cpudata.h> #include <asm/setup.h> #include <asm/cacheflush.h> @@ -106,7 +105,6 @@ unsigned long cmdline_memory_size __initdata = 0; /* which CPU booted us (0xff = not set) */ unsigned char boot_cpu_id = 0xff; /* 0xff will make it into DATA section... */ -unsigned char boot_cpu_id4; /* boot_cpu_id << 2 */ static void prom_console_write(struct console *con, const char *s, unsigned n) @@ -182,13 +180,6 @@ static void __init boot_flags_init(char *commands) } } -/* This routine will in the future do all the nasty prom stuff - * to probe for the mmu type and its parameters, etc. This will - * also be where SMP things happen. - */ - -extern void sun4c_probe_vac(void); - extern unsigned short root_flags; extern unsigned short root_dev; extern unsigned short ram_flags; @@ -200,6 +191,52 @@ extern int root_mountflags; char reboot_command[COMMAND_LINE_SIZE]; +struct cpuid_patch_entry { + unsigned int addr; + unsigned int sun4d[3]; + unsigned int leon[3]; +}; +extern struct cpuid_patch_entry __cpuid_patch, __cpuid_patch_end; + +static void __init per_cpu_patch(void) +{ + struct cpuid_patch_entry *p; + + if (sparc_cpu_model == sun4m) { + /* Nothing to do, this is what the unpatched code + * targets. + */ + return; + } + + p = &__cpuid_patch; + while (p < &__cpuid_patch_end) { + unsigned long addr = p->addr; + unsigned int *insns; + + switch (sparc_cpu_model) { + case sun4d: + insns = &p->sun4d[0]; + break; + + case sparc_leon: + insns = &p->leon[0]; + break; + default: + prom_printf("Unknown cpu type, halting.\n"); + prom_halt(); + } + *(unsigned int *) (addr + 0) = insns[0]; + flushi(addr + 0); + *(unsigned int *) (addr + 4) = insns[1]; + flushi(addr + 4); + *(unsigned int *) (addr + 8) = insns[2]; + flushi(addr + 8); + + p++; + } +} + enum sparc_cpu sparc_cpu_model; EXPORT_SYMBOL(sparc_cpu_model); @@ -225,10 +262,6 @@ void __init setup_arch(char **cmdline_p) /* Set sparc_cpu_model */ sparc_cpu_model = sun_unknown; - if (!strcmp(&cputypval[0], "sun4 ")) - sparc_cpu_model = sun4; - if (!strcmp(&cputypval[0], "sun4c")) - sparc_cpu_model = sun4c; if (!strcmp(&cputypval[0], "sun4m")) sparc_cpu_model = sun4m; if (!strcmp(&cputypval[0], "sun4s")) @@ -244,12 +277,6 @@ void __init setup_arch(char **cmdline_p) printk("ARCH: "); switch(sparc_cpu_model) { - case sun4: - printk("SUN4\n"); - break; - case sun4c: - printk("SUN4C\n"); - break; case sun4m: printk("SUN4M\n"); break; @@ -275,8 +302,6 @@ void __init setup_arch(char **cmdline_p) #endif idprom_init(); - if (ARCH_SUN4C) - sun4c_probe_vac(); load_mmu(); phys_base = 0xffffffffUL; @@ -313,6 +338,9 @@ void __init setup_arch(char **cmdline_p) init_mm.context = (unsigned long) NO_CONTEXT; init_task.thread.kregs = &fake_swapper_regs; + /* Run-time patch instructions to match the cpu model */ + per_cpu_patch(); + paging_init(); smp_setup_cpu_possible_map(); diff --git a/arch/sparc/kernel/signal_32.c b/arch/sparc/kernel/signal_32.c index 1e750e415d7a..ac8e66b50f07 100644 --- a/arch/sparc/kernel/signal_32.c +++ b/arch/sparc/kernel/signal_32.c @@ -217,12 +217,9 @@ segv: /* Checks if the fp is valid */ static inline int invalid_frame_pointer(void __user *fp, int fplen) { - if ((((unsigned long) fp) & 7) || - !__access_ok((unsigned long)fp, fplen) || - ((sparc_cpu_model == sun4 || sparc_cpu_model == sun4c) && - ((unsigned long) fp < 0xe0000000 && (unsigned long) fp >= 0x20000000))) + if ((((unsigned long) fp) & 7) || !__access_ok((unsigned long)fp, fplen)) return 1; - + return 0; } diff --git a/arch/sparc/kernel/smp_32.c b/arch/sparc/kernel/smp_32.c index f671e7fd6ddc..57713758079e 100644 --- a/arch/sparc/kernel/smp_32.c +++ b/arch/sparc/kernel/smp_32.c @@ -40,6 +40,8 @@ volatile unsigned long cpu_callin_map[NR_CPUS] __cpuinitdata = {0,}; cpumask_t smp_commenced_mask = CPU_MASK_NONE; +const struct sparc32_ipi_ops *sparc32_ipi_ops; + /* The only guaranteed locking primitive available on all Sparc * processors is 'ldstub [%reg + immediate], %dest_reg' which atomically * places the current byte at the effective address into dest_reg and @@ -85,14 +87,6 @@ void __init smp_cpus_done(unsigned int max_cpus) (bogosum/(5000/HZ))%100); switch(sparc_cpu_model) { - case sun4: - printk("SUN4\n"); - BUG(); - break; - case sun4c: - printk("SUN4C\n"); - BUG(); - break; case sun4m: smp4m_smp_done(); break; @@ -132,7 +126,7 @@ void smp_send_reschedule(int cpu) * a single CPU. The trap handler needs only to do trap entry/return * to call schedule. */ - BTFIXUP_CALL(smp_ipi_resched)(cpu); + sparc32_ipi_ops->resched(cpu); } void smp_send_stop(void) @@ -142,7 +136,7 @@ void smp_send_stop(void) void arch_send_call_function_single_ipi(int cpu) { /* trigger one IPI single call on one CPU */ - BTFIXUP_CALL(smp_ipi_single)(cpu); + sparc32_ipi_ops->single(cpu); } void arch_send_call_function_ipi_mask(const struct cpumask *mask) @@ -151,7 +145,7 @@ void arch_send_call_function_ipi_mask(const struct cpumask *mask) /* trigger IPI mask call on each CPU */ for_each_cpu(cpu, mask) - BTFIXUP_CALL(smp_ipi_mask_one)(cpu); + sparc32_ipi_ops->mask_one(cpu); } void smp_resched_interrupt(void) @@ -179,150 +173,9 @@ void smp_call_function_interrupt(void) irq_exit(); } -void smp_flush_cache_all(void) -{ - xc0((smpfunc_t) BTFIXUP_CALL(local_flush_cache_all)); - local_flush_cache_all(); -} - -void smp_flush_tlb_all(void) -{ - xc0((smpfunc_t) BTFIXUP_CALL(local_flush_tlb_all)); - local_flush_tlb_all(); -} - -void smp_flush_cache_mm(struct mm_struct *mm) -{ - if(mm->context != NO_CONTEXT) { - cpumask_t cpu_mask; - cpumask_copy(&cpu_mask, mm_cpumask(mm)); - cpumask_clear_cpu(smp_processor_id(), &cpu_mask); - if (!cpumask_empty(&cpu_mask)) - xc1((smpfunc_t) BTFIXUP_CALL(local_flush_cache_mm), (unsigned long) mm); - local_flush_cache_mm(mm); - } -} - -void smp_flush_tlb_mm(struct mm_struct *mm) -{ - if(mm->context != NO_CONTEXT) { - cpumask_t cpu_mask; - cpumask_copy(&cpu_mask, mm_cpumask(mm)); - cpumask_clear_cpu(smp_processor_id(), &cpu_mask); - if (!cpumask_empty(&cpu_mask)) { - xc1((smpfunc_t) BTFIXUP_CALL(local_flush_tlb_mm), (unsigned long) mm); - if(atomic_read(&mm->mm_users) == 1 && current->active_mm == mm) - cpumask_copy(mm_cpumask(mm), - cpumask_of(smp_processor_id())); - } - local_flush_tlb_mm(mm); - } -} - -void smp_flush_cache_range(struct vm_area_struct *vma, unsigned long start, - unsigned long end) -{ - struct mm_struct *mm = vma->vm_mm; - - if (mm->context != NO_CONTEXT) { - cpumask_t cpu_mask; - cpumask_copy(&cpu_mask, mm_cpumask(mm)); - cpumask_clear_cpu(smp_processor_id(), &cpu_mask); - if (!cpumask_empty(&cpu_mask)) - xc3((smpfunc_t) BTFIXUP_CALL(local_flush_cache_range), (unsigned long) vma, start, end); - local_flush_cache_range(vma, start, end); - } -} - -void smp_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, - unsigned long end) -{ - struct mm_struct *mm = vma->vm_mm; - - if (mm->context != NO_CONTEXT) { - cpumask_t cpu_mask; - cpumask_copy(&cpu_mask, mm_cpumask(mm)); - cpumask_clear_cpu(smp_processor_id(), &cpu_mask); - if (!cpumask_empty(&cpu_mask)) - xc3((smpfunc_t) BTFIXUP_CALL(local_flush_tlb_range), (unsigned long) vma, start, end); - local_flush_tlb_range(vma, start, end); - } -} - -void smp_flush_cache_page(struct vm_area_struct *vma, unsigned long page) -{ - struct mm_struct *mm = vma->vm_mm; - - if(mm->context != NO_CONTEXT) { - cpumask_t cpu_mask; - cpumask_copy(&cpu_mask, mm_cpumask(mm)); - cpumask_clear_cpu(smp_processor_id(), &cpu_mask); - if (!cpumask_empty(&cpu_mask)) - xc2((smpfunc_t) BTFIXUP_CALL(local_flush_cache_page), (unsigned long) vma, page); - local_flush_cache_page(vma, page); - } -} - -void smp_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) -{ - struct mm_struct *mm = vma->vm_mm; - - if(mm->context != NO_CONTEXT) { - cpumask_t cpu_mask; - cpumask_copy(&cpu_mask, mm_cpumask(mm)); - cpumask_clear_cpu(smp_processor_id(), &cpu_mask); - if (!cpumask_empty(&cpu_mask)) - xc2((smpfunc_t) BTFIXUP_CALL(local_flush_tlb_page), (unsigned long) vma, page); - local_flush_tlb_page(vma, page); - } -} - -void smp_flush_page_to_ram(unsigned long page) -{ - /* Current theory is that those who call this are the one's - * who have just dirtied their cache with the pages contents - * in kernel space, therefore we only run this on local cpu. - * - * XXX This experiment failed, research further... -DaveM - */ -#if 1 - xc1((smpfunc_t) BTFIXUP_CALL(local_flush_page_to_ram), page); -#endif - local_flush_page_to_ram(page); -} - -void smp_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr) -{ - cpumask_t cpu_mask; - cpumask_copy(&cpu_mask, mm_cpumask(mm)); - cpumask_clear_cpu(smp_processor_id(), &cpu_mask); - if (!cpumask_empty(&cpu_mask)) - xc2((smpfunc_t) BTFIXUP_CALL(local_flush_sig_insns), (unsigned long) mm, insn_addr); - local_flush_sig_insns(mm, insn_addr); -} - -extern unsigned int lvl14_resolution; - -/* /proc/profile writes can call this, don't __init it please. */ -static DEFINE_SPINLOCK(prof_setup_lock); - int setup_profiling_timer(unsigned int multiplier) { - int i; - unsigned long flags; - - /* Prevent level14 ticker IRQ flooding. */ - if((!multiplier) || (lvl14_resolution / multiplier) < 500) - return -EINVAL; - - spin_lock_irqsave(&prof_setup_lock, flags); - for_each_possible_cpu(i) { - load_profile_irq(i, lvl14_resolution / multiplier); - prof_multiplier(i) = multiplier; - } - spin_unlock_irqrestore(&prof_setup_lock, flags); - - return 0; + return -EINVAL; } void __init smp_prepare_cpus(unsigned int max_cpus) @@ -345,14 +198,6 @@ void __init smp_prepare_cpus(unsigned int max_cpus) smp_store_cpu_info(boot_cpu_id); switch(sparc_cpu_model) { - case sun4: - printk("SUN4\n"); - BUG(); - break; - case sun4c: - printk("SUN4C\n"); - BUG(); - break; case sun4m: smp4m_boot_cpus(); break; @@ -418,14 +263,6 @@ int __cpuinit __cpu_up(unsigned int cpu) int ret=0; switch(sparc_cpu_model) { - case sun4: - printk("SUN4\n"); - BUG(); - break; - case sun4c: - printk("SUN4C\n"); - BUG(); - break; case sun4m: ret = smp4m_boot_one_cpu(cpu); break; diff --git a/arch/sparc/kernel/sparc_ksyms_32.c b/arch/sparc/kernel/sparc_ksyms_32.c index baeab8720237..e521c54560f9 100644 --- a/arch/sparc/kernel/sparc_ksyms_32.c +++ b/arch/sparc/kernel/sparc_ksyms_32.c @@ -28,19 +28,5 @@ EXPORT_SYMBOL(__ndelay); EXPORT_SYMBOL(__ret_efault); EXPORT_SYMBOL(empty_zero_page); -/* Defined using magic */ -#ifndef CONFIG_SMP -EXPORT_SYMBOL(BTFIXUP_CALL(___xchg32)); -#else -EXPORT_SYMBOL(BTFIXUP_CALL(__hard_smp_processor_id)); -#endif -EXPORT_SYMBOL(BTFIXUP_CALL(mmu_unlockarea)); -EXPORT_SYMBOL(BTFIXUP_CALL(mmu_lockarea)); -EXPORT_SYMBOL(BTFIXUP_CALL(mmu_get_scsi_sgl)); -EXPORT_SYMBOL(BTFIXUP_CALL(mmu_get_scsi_one)); -EXPORT_SYMBOL(BTFIXUP_CALL(mmu_release_scsi_sgl)); -EXPORT_SYMBOL(BTFIXUP_CALL(mmu_release_scsi_one)); -EXPORT_SYMBOL(BTFIXUP_CALL(pgprot_noncached)); - /* Exporting a symbol from /init/main.c */ EXPORT_SYMBOL(saved_command_line); diff --git a/arch/sparc/kernel/sun4c_irq.c b/arch/sparc/kernel/sun4c_irq.c deleted file mode 100644 index f6bf25a2ff80..000000000000 --- a/arch/sparc/kernel/sun4c_irq.c +++ /dev/null @@ -1,264 +0,0 @@ -/* - * sun4c irq support - * - * djhr: Hacked out of irq.c into a CPU dependent version. - * - * Copyright (C) 1995 David S. Miller ([email protected]) - * Copyright (C) 1995 Miguel de Icaza ([email protected]) - * Copyright (C) 1995 Pete A. Zaitcev ([email protected]) - * Copyright (C) 1996 Dave Redman ([email protected]) - */ - -#include <linux/init.h> - -#include <asm/oplib.h> -#include <asm/timer.h> -#include <asm/irq.h> -#include <asm/io.h> - -#include "irq.h" - -/* Sun4c interrupts are typically laid out as follows: - * - * 1 - Software interrupt, SBUS level 1 - * 2 - SBUS level 2 - * 3 - ESP SCSI, SBUS level 3 - * 4 - Software interrupt - * 5 - Lance ethernet, SBUS level 4 - * 6 - Software interrupt - * 7 - Graphics card, SBUS level 5 - * 8 - SBUS level 6 - * 9 - SBUS level 7 - * 10 - Counter timer - * 11 - Floppy - * 12 - Zilog uart - * 13 - CS4231 audio - * 14 - Profiling timer - * 15 - NMI - * - * The interrupt enable bits in the interrupt mask register are - * really only used to enable/disable the timer interrupts, and - * for signalling software interrupts. There is also a master - * interrupt enable bit in this register. - * - * Interrupts are enabled by setting the SUN4C_INT_* bits, they - * are disabled by clearing those bits. - */ - -/* - * Bit field defines for the interrupt registers on various - * Sparc machines. - */ - -/* The sun4c interrupt register. */ -#define SUN4C_INT_ENABLE 0x01 /* Allow interrupts. */ -#define SUN4C_INT_E14 0x80 /* Enable level 14 IRQ. */ -#define SUN4C_INT_E10 0x20 /* Enable level 10 IRQ. */ -#define SUN4C_INT_E8 0x10 /* Enable level 8 IRQ. */ -#define SUN4C_INT_E6 0x08 /* Enable level 6 IRQ. */ -#define SUN4C_INT_E4 0x04 /* Enable level 4 IRQ. */ -#define SUN4C_INT_E1 0x02 /* Enable level 1 IRQ. */ - -/* - * Pointer to the interrupt enable byte - * Used by entry.S - */ -unsigned char __iomem *interrupt_enable; - -static void sun4c_mask_irq(struct irq_data *data) -{ - unsigned long mask = (unsigned long)data->chip_data; - - if (mask) { - unsigned long flags; - - local_irq_save(flags); - mask = sbus_readb(interrupt_enable) & ~mask; - sbus_writeb(mask, interrupt_enable); - local_irq_restore(flags); - } -} - -static void sun4c_unmask_irq(struct irq_data *data) -{ - unsigned long mask = (unsigned long)data->chip_data; - - if (mask) { - unsigned long flags; - - local_irq_save(flags); - mask = sbus_readb(interrupt_enable) | mask; - sbus_writeb(mask, interrupt_enable); - local_irq_restore(flags); - } -} - -static unsigned int sun4c_startup_irq(struct irq_data *data) -{ - irq_link(data->irq); - sun4c_unmask_irq(data); - - return 0; -} - -static void sun4c_shutdown_irq(struct irq_data *data) -{ - sun4c_mask_irq(data); - irq_unlink(data->irq); -} - -static struct irq_chip sun4c_irq = { - .name = "sun4c", - .irq_startup = sun4c_startup_irq, - .irq_shutdown = sun4c_shutdown_irq, - .irq_mask = sun4c_mask_irq, - .irq_unmask = sun4c_unmask_irq, -}; - -static unsigned int sun4c_build_device_irq(struct platform_device *op, - unsigned int real_irq) -{ - unsigned int irq; - - if (real_irq >= 16) { - prom_printf("Bogus sun4c IRQ %u\n", real_irq); - prom_halt(); - } - - irq = irq_alloc(real_irq, real_irq); - if (irq) { - unsigned long mask = 0UL; - - switch (real_irq) { - case 1: - mask = SUN4C_INT_E1; - break; - case 8: - mask = SUN4C_INT_E8; - break; - case 10: - mask = SUN4C_INT_E10; - break; - case 14: - mask = SUN4C_INT_E14; - break; - default: - /* All the rest are either always enabled, - * or are for signalling software interrupts. - */ - break; - } - irq_set_chip_and_handler_name(irq, &sun4c_irq, - handle_level_irq, "level"); - irq_set_chip_data(irq, (void *)mask); - } - return irq; -} - -struct sun4c_timer_info { - u32 l10_count; - u32 l10_limit; - u32 l14_count; - u32 l14_limit; -}; - -static struct sun4c_timer_info __iomem *sun4c_timers; - -static void sun4c_clear_clock_irq(void) -{ - sbus_readl(&sun4c_timers->l10_limit); -} - -static void sun4c_load_profile_irq(int cpu, unsigned int limit) -{ - /* Errm.. not sure how to do this.. */ -} - -static void __init sun4c_init_timers(irq_handler_t counter_fn) -{ - const struct linux_prom_irqs *prom_irqs; - struct device_node *dp; - unsigned int irq; - const u32 *addr; - int err; - - dp = of_find_node_by_name(NULL, "counter-timer"); - if (!dp) { - prom_printf("sun4c_init_timers: Unable to find counter-timer\n"); - prom_halt(); - } - - addr = of_get_property(dp, "address", NULL); - if (!addr) { - prom_printf("sun4c_init_timers: No address property\n"); - prom_halt(); - } - - sun4c_timers = (void __iomem *) (unsigned long) addr[0]; - - prom_irqs = of_get_property(dp, "intr", NULL); - of_node_put(dp); - if (!prom_irqs) { - prom_printf("sun4c_init_timers: No intr property\n"); - prom_halt(); - } - - /* Have the level 10 timer tick at 100HZ. We don't touch the - * level 14 timer limit since we are letting the prom handle - * them until we have a real console driver so L1-A works. - */ - sbus_writel((((1000000/HZ) + 1) << 10), &sun4c_timers->l10_limit); - - master_l10_counter = &sun4c_timers->l10_count; - - irq = sun4c_build_device_irq(NULL, prom_irqs[0].pri); - err = request_irq(irq, counter_fn, IRQF_TIMER, "timer", NULL); - if (err) { - prom_printf("sun4c_init_timers: request_irq() fails with %d\n", err); - prom_halt(); - } - - /* disable timer interrupt */ - sun4c_mask_irq(irq_get_irq_data(irq)); -} - -#ifdef CONFIG_SMP -static void sun4c_nop(void) -{ -} -#endif - -void __init sun4c_init_IRQ(void) -{ - struct device_node *dp; - const u32 *addr; - - dp = of_find_node_by_name(NULL, "interrupt-enable"); - if (!dp) { - prom_printf("sun4c_init_IRQ: Unable to find interrupt-enable\n"); - prom_halt(); - } - - addr = of_get_property(dp, "address", NULL); - of_node_put(dp); - if (!addr) { - prom_printf("sun4c_init_IRQ: No address property\n"); - prom_halt(); - } - - interrupt_enable = (void __iomem *) (unsigned long) addr[0]; - - BTFIXUPSET_CALL(clear_clock_irq, sun4c_clear_clock_irq, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(load_profile_irq, sun4c_load_profile_irq, BTFIXUPCALL_NOP); - - sparc_irq_config.init_timers = sun4c_init_timers; - sparc_irq_config.build_device_irq = sun4c_build_device_irq; - -#ifdef CONFIG_SMP - BTFIXUPSET_CALL(set_cpu_int, sun4c_nop, BTFIXUPCALL_NOP); - BTFIXUPSET_CALL(clear_cpu_int, sun4c_nop, BTFIXUPCALL_NOP); - BTFIXUPSET_CALL(set_irq_udt, sun4c_nop, BTFIXUPCALL_NOP); -#endif - sbus_writeb(SUN4C_INT_ENABLE, interrupt_enable); - /* Cannot enable interrupts until OBP ticker is disabled. */ -} diff --git a/arch/sparc/kernel/sun4d_irq.c b/arch/sparc/kernel/sun4d_irq.c index 1d13c5bda0b1..e490ac9327c7 100644 --- a/arch/sparc/kernel/sun4d_irq.c +++ b/arch/sparc/kernel/sun4d_irq.c @@ -15,6 +15,7 @@ #include <asm/sbi.h> #include <asm/cacheflush.h> #include <asm/setup.h> +#include <asm/oplib.h> #include "kernel.h" #include "irq.h" @@ -243,19 +244,6 @@ struct irq_chip sun4d_irq = { }; #ifdef CONFIG_SMP -static void sun4d_set_cpu_int(int cpu, int level) -{ - sun4d_send_ipi(cpu, level); -} - -static void sun4d_clear_ipi(int cpu, int level) -{ -} - -static void sun4d_set_udt(int cpu) -{ -} - /* Setup IRQ distribution scheme. */ void __init sun4d_distribute_irqs(void) { @@ -282,7 +270,8 @@ static void sun4d_clear_clock_irq(void) static void sun4d_load_profile_irq(int cpu, unsigned int limit) { - bw_set_prof_limit(cpu, limit); + unsigned int value = limit ? timer_value(limit) : 0; + bw_set_prof_limit(cpu, value); } static void __init sun4d_load_profile_irqs(void) @@ -418,12 +407,12 @@ static void __init sun4d_fixup_trap_table(void) trap_table->inst_two = lvl14_save[1]; trap_table->inst_three = lvl14_save[2]; trap_table->inst_four = lvl14_save[3]; - local_flush_cache_all(); + local_ops->cache_all(); local_irq_restore(flags); #endif } -static void __init sun4d_init_timers(irq_handler_t counter_fn) +static void __init sun4d_init_timers(void) { struct device_node *dp; struct resource res; @@ -466,12 +455,20 @@ static void __init sun4d_init_timers(irq_handler_t counter_fn) prom_halt(); } - sbus_writel((((1000000/HZ) + 1) << 10), &sun4d_timers->l10_timer_limit); +#ifdef CONFIG_SMP + sparc_config.cs_period = SBUS_CLOCK_RATE * 2; /* 2 seconds */ +#else + sparc_config.cs_period = SBUS_CLOCK_RATE / HZ; /* 1/HZ sec */ + sparc_config.features |= FEAT_L10_CLOCKEVENT; +#endif + sparc_config.features |= FEAT_L10_CLOCKSOURCE; + sbus_writel(timer_value(sparc_config.cs_period), + &sun4d_timers->l10_timer_limit); master_l10_counter = &sun4d_timers->l10_cur_count; irq = sun4d_build_timer_irq(board, SUN4D_TIMER_IRQ); - err = request_irq(irq, counter_fn, IRQF_TIMER, "timer", NULL); + err = request_irq(irq, timer_interrupt, IRQF_TIMER, "timer", NULL); if (err) { prom_printf("sun4d_init_timers: request_irq() failed with %d\n", err); @@ -509,16 +506,11 @@ void __init sun4d_init_IRQ(void) { local_irq_disable(); - BTFIXUPSET_CALL(clear_clock_irq, sun4d_clear_clock_irq, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(load_profile_irq, sun4d_load_profile_irq, BTFIXUPCALL_NORM); + sparc_config.init_timers = sun4d_init_timers; + sparc_config.build_device_irq = sun4d_build_device_irq; + sparc_config.clock_rate = SBUS_CLOCK_RATE; + sparc_config.clear_clock_irq = sun4d_clear_clock_irq; + sparc_config.load_profile_irq = sun4d_load_profile_irq; - sparc_irq_config.init_timers = sun4d_init_timers; - sparc_irq_config.build_device_irq = sun4d_build_device_irq; - -#ifdef CONFIG_SMP - BTFIXUPSET_CALL(set_cpu_int, sun4d_set_cpu_int, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(clear_cpu_int, sun4d_clear_ipi, BTFIXUPCALL_NOP); - BTFIXUPSET_CALL(set_irq_udt, sun4d_set_udt, BTFIXUPCALL_NOP); -#endif /* Cannot enable interrupts until OBP ticker is disabled. */ } diff --git a/arch/sparc/kernel/sun4d_smp.c b/arch/sparc/kernel/sun4d_smp.c index 540b2fec09f0..f9a1a33cbb2c 100644 --- a/arch/sparc/kernel/sun4d_smp.c +++ b/arch/sparc/kernel/sun4d_smp.c @@ -6,16 +6,20 @@ * Copyright (C) 1996 David S. Miller ([email protected]) */ +#include <linux/clockchips.h> #include <linux/interrupt.h> #include <linux/profile.h> #include <linux/delay.h> +#include <linux/sched.h> #include <linux/cpu.h> +#include <asm/cacheflush.h> +#include <asm/switch_to.h> +#include <asm/tlbflush.h> +#include <asm/timer.h> +#include <asm/oplib.h> #include <asm/sbi.h> #include <asm/mmu.h> -#include <asm/tlbflush.h> -#include <asm/switch_to.h> -#include <asm/cacheflush.h> #include "kernel.h" #include "irq.h" @@ -34,7 +38,6 @@ static inline unsigned long sun4d_swap(volatile unsigned long *ptr, unsigned lon } static void smp4d_ipi_init(void); -static void smp_setup_percpu_timer(void); static unsigned char cpu_leds[32]; @@ -49,7 +52,7 @@ static inline void show_leds(int cpuid) void __cpuinit smp4d_callin(void) { - int cpuid = hard_smp4d_processor_id(); + int cpuid = hard_smp_processor_id(); unsigned long flags; /* Show we are alive */ @@ -59,8 +62,8 @@ void __cpuinit smp4d_callin(void) /* Enable level15 interrupt, disable level14 interrupt for now */ cc_set_imsk((cc_get_imsk() & ~0x8000) | 0x4000); - local_flush_cache_all(); - local_flush_tlb_all(); + local_ops->cache_all(); + local_ops->tlb_all(); notify_cpu_starting(cpuid); /* @@ -70,17 +73,17 @@ void __cpuinit smp4d_callin(void) * to call the scheduler code. */ /* Get our local ticker going. */ - smp_setup_percpu_timer(); + register_percpu_ce(cpuid); calibrate_delay(); smp_store_cpu_info(cpuid); - local_flush_cache_all(); - local_flush_tlb_all(); + local_ops->cache_all(); + local_ops->tlb_all(); /* Allow master to continue. */ sun4d_swap((unsigned long *)&cpu_callin_map[cpuid], 1); - local_flush_cache_all(); - local_flush_tlb_all(); + local_ops->cache_all(); + local_ops->tlb_all(); while ((unsigned long)current_set[cpuid] < PAGE_OFFSET) barrier(); @@ -100,8 +103,8 @@ void __cpuinit smp4d_callin(void) atomic_inc(&init_mm.mm_count); current->active_mm = &init_mm; - local_flush_cache_all(); - local_flush_tlb_all(); + local_ops->cache_all(); + local_ops->tlb_all(); local_irq_enable(); /* We don't allow PIL 14 yet */ @@ -123,8 +126,7 @@ void __init smp4d_boot_cpus(void) smp4d_ipi_init(); if (boot_cpu_id) current_set[0] = NULL; - smp_setup_percpu_timer(); - local_flush_cache_all(); + local_ops->cache_all(); } int __cpuinit smp4d_boot_one_cpu(int i) @@ -150,7 +152,7 @@ int __cpuinit smp4d_boot_one_cpu(int i) /* whirrr, whirrr, whirrrrrrrrr... */ printk(KERN_INFO "Starting CPU %d at %p\n", i, entry); - local_flush_cache_all(); + local_ops->cache_all(); prom_startcpu(cpu_node, &smp_penguin_ctable, 0, (char *)entry); @@ -168,7 +170,7 @@ int __cpuinit smp4d_boot_one_cpu(int i) return -ENODEV; } - local_flush_cache_all(); + local_ops->cache_all(); return 0; } @@ -185,7 +187,7 @@ void __init smp4d_smp_done(void) prev = &cpu_data(i).next; } *prev = first; - local_flush_cache_all(); + local_ops->cache_all(); /* Ok, they are spinning and ready to go. */ smp_processors_ready = 1; @@ -233,7 +235,20 @@ void sun4d_ipi_interrupt(void) } } -static void smp4d_ipi_single(int cpu) +/* +-------+-------------+-----------+------------------------------------+ + * | bcast | devid | sid | levels mask | + * +-------+-------------+-----------+------------------------------------+ + * 31 30 23 22 15 14 0 + */ +#define IGEN_MESSAGE(bcast, devid, sid, levels) \ + (((bcast) << 31) | ((devid) << 23) | ((sid) << 15) | (levels)) + +static void sun4d_send_ipi(int cpu, int level) +{ + cc_set_igen(IGEN_MESSAGE(0, cpu << 3, 6 + ((level >> 1) & 7), 1 << (level - 1))); +} + +static void sun4d_ipi_single(int cpu) { struct sun4d_ipi_work *work = &per_cpu(sun4d_ipi_work, cpu); @@ -244,7 +259,7 @@ static void smp4d_ipi_single(int cpu) sun4d_send_ipi(cpu, SUN4D_IPI_IRQ); } -static void smp4d_ipi_mask_one(int cpu) +static void sun4d_ipi_mask_one(int cpu) { struct sun4d_ipi_work *work = &per_cpu(sun4d_ipi_work, cpu); @@ -255,7 +270,7 @@ static void smp4d_ipi_mask_one(int cpu) sun4d_send_ipi(cpu, SUN4D_IPI_IRQ); } -static void smp4d_ipi_resched(int cpu) +static void sun4d_ipi_resched(int cpu) { struct sun4d_ipi_work *work = &per_cpu(sun4d_ipi_work, cpu); @@ -280,7 +295,7 @@ static struct smp_funcall { static DEFINE_SPINLOCK(cross_call_lock); /* Cross calls must be serialized, at least currently. */ -static void smp4d_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1, +static void sun4d_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1, unsigned long arg2, unsigned long arg3, unsigned long arg4) { @@ -352,7 +367,7 @@ static void smp4d_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1, /* Running cross calls. */ void smp4d_cross_call_irq(void) { - int i = hard_smp4d_processor_id(); + int i = hard_smp_processor_id(); ccall_info.processors_in[i] = 1; ccall_info.func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3, @@ -363,7 +378,8 @@ void smp4d_cross_call_irq(void) void smp4d_percpu_timer_interrupt(struct pt_regs *regs) { struct pt_regs *old_regs; - int cpu = hard_smp4d_processor_id(); + int cpu = hard_smp_processor_id(); + struct clock_event_device *ce; static int cpu_tick[NR_CPUS]; static char led_mask[] = { 0xe, 0xd, 0xb, 0x7, 0xb, 0xd }; @@ -379,45 +395,21 @@ void smp4d_percpu_timer_interrupt(struct pt_regs *regs) show_leds(cpu); } - profile_tick(CPU_PROFILING); - - if (!--prof_counter(cpu)) { - int user = user_mode(regs); + ce = &per_cpu(sparc32_clockevent, cpu); - irq_enter(); - update_process_times(user); - irq_exit(); + irq_enter(); + ce->event_handler(ce); + irq_exit(); - prof_counter(cpu) = prof_multiplier(cpu); - } set_irq_regs(old_regs); } -static void __cpuinit smp_setup_percpu_timer(void) -{ - int cpu = hard_smp4d_processor_id(); - - prof_counter(cpu) = prof_multiplier(cpu) = 1; - load_profile_irq(cpu, lvl14_resolution); -} - -void __init smp4d_blackbox_id(unsigned *addr) -{ - int rd = *addr & 0x3e000000; - - addr[0] = 0xc0800800 | rd; /* lda [%g0] ASI_M_VIKING_TMP1, reg */ - addr[1] = 0x01000000; /* nop */ - addr[2] = 0x01000000; /* nop */ -} - -void __init smp4d_blackbox_current(unsigned *addr) -{ - int rd = *addr & 0x3e000000; - - addr[0] = 0xc0800800 | rd; /* lda [%g0] ASI_M_VIKING_TMP1, reg */ - addr[2] = 0x81282002 | rd | (rd >> 11); /* sll reg, 2, reg */ - addr[4] = 0x01000000; /* nop */ -} +static const struct sparc32_ipi_ops sun4d_ipi_ops = { + .cross_call = sun4d_cross_call, + .resched = sun4d_ipi_resched, + .single = sun4d_ipi_single, + .mask_one = sun4d_ipi_mask_one, +}; void __init sun4d_init_smp(void) { @@ -426,14 +418,7 @@ void __init sun4d_init_smp(void) /* Patch ipi15 trap table */ t_nmi[1] = t_nmi[1] + (linux_trap_ipi15_sun4d - linux_trap_ipi15_sun4m); - /* And set btfixup... */ - BTFIXUPSET_BLACKBOX(hard_smp_processor_id, smp4d_blackbox_id); - BTFIXUPSET_BLACKBOX(load_current, smp4d_blackbox_current); - BTFIXUPSET_CALL(smp_cross_call, smp4d_cross_call, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(__hard_smp_processor_id, __smp4d_processor_id, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(smp_ipi_resched, smp4d_ipi_resched, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(smp_ipi_single, smp4d_ipi_single, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(smp_ipi_mask_one, smp4d_ipi_mask_one, BTFIXUPCALL_NORM); + sparc32_ipi_ops = &sun4d_ipi_ops; for (i = 0; i < NR_CPUS; i++) { ccall_info.processors_in[i] = 1; diff --git a/arch/sparc/kernel/sun4m_irq.c b/arch/sparc/kernel/sun4m_irq.c index e61165161dd3..c5ade9d27a1d 100644 --- a/arch/sparc/kernel/sun4m_irq.c +++ b/arch/sparc/kernel/sun4m_irq.c @@ -112,9 +112,6 @@ struct sun4m_handler_data { #define SUN4M_INT_E14 0x00000080 #define SUN4M_INT_E10 0x00080000 -#define SUN4M_HARD_INT(x) (0x000000001 << (x)) -#define SUN4M_SOFT_INT(x) (0x000010000 << (x)) - #define SUN4M_INT_MASKALL 0x80000000 /* mask all interrupts */ #define SUN4M_INT_MODULE_ERR 0x40000000 /* module error */ #define SUN4M_INT_M2S_WRITE_ERR 0x20000000 /* write buffer error */ @@ -282,23 +279,6 @@ out: return irq; } -#ifdef CONFIG_SMP -static void sun4m_send_ipi(int cpu, int level) -{ - sbus_writel(SUN4M_SOFT_INT(level), &sun4m_irq_percpu[cpu]->set); -} - -static void sun4m_clear_ipi(int cpu, int level) -{ - sbus_writel(SUN4M_SOFT_INT(level), &sun4m_irq_percpu[cpu]->clear); -} - -static void sun4m_set_udt(int cpu) -{ - sbus_writel(cpu, &sun4m_irq_global->interrupt_target); -} -#endif - struct sun4m_timer_percpu { u32 l14_limit; u32 l14_count; @@ -318,9 +298,6 @@ struct sun4m_timer_global { static struct sun4m_timer_global __iomem *timers_global; - -unsigned int lvl14_resolution = (((1000000/HZ) + 1) << 10); - static void sun4m_clear_clock_irq(void) { sbus_readl(&timers_global->l10_limit); @@ -369,10 +346,11 @@ void sun4m_clear_profile_irq(int cpu) static void sun4m_load_profile_irq(int cpu, unsigned int limit) { - sbus_writel(limit, &timers_percpu[cpu]->l14_limit); + unsigned int value = limit ? timer_value(limit) : 0; + sbus_writel(value, &timers_percpu[cpu]->l14_limit); } -static void __init sun4m_init_timers(irq_handler_t counter_fn) +static void __init sun4m_init_timers(void) { struct device_node *dp = of_find_node_by_name(NULL, "counter"); int i, err, len, num_cpu_timers; @@ -402,13 +380,22 @@ static void __init sun4m_init_timers(irq_handler_t counter_fn) /* Every per-cpu timer works in timer mode */ sbus_writel(0x00000000, &timers_global->timer_config); - sbus_writel((((1000000/HZ) + 1) << 10), &timers_global->l10_limit); +#ifdef CONFIG_SMP + sparc_config.cs_period = SBUS_CLOCK_RATE * 2; /* 2 seconds */ + sparc_config.features |= FEAT_L14_ONESHOT; +#else + sparc_config.cs_period = SBUS_CLOCK_RATE / HZ; /* 1/HZ sec */ + sparc_config.features |= FEAT_L10_CLOCKEVENT; +#endif + sparc_config.features |= FEAT_L10_CLOCKSOURCE; + sbus_writel(timer_value(sparc_config.cs_period), + &timers_global->l10_limit); master_l10_counter = &timers_global->l10_count; irq = sun4m_build_device_irq(NULL, SUN4M_TIMER_IRQ); - err = request_irq(irq, counter_fn, IRQF_TIMER, "timer", NULL); + err = request_irq(irq, timer_interrupt, IRQF_TIMER, "timer", NULL); if (err) { printk(KERN_ERR "sun4m_init_timers: Register IRQ error %d.\n", err); @@ -434,7 +421,7 @@ static void __init sun4m_init_timers(irq_handler_t counter_fn) trap_table->inst_two = lvl14_save[1]; trap_table->inst_three = lvl14_save[2]; trap_table->inst_four = lvl14_save[3]; - local_flush_cache_all(); + local_ops->cache_all(); local_irq_restore(flags); } #endif @@ -475,17 +462,12 @@ void __init sun4m_init_IRQ(void) if (num_cpu_iregs == 4) sbus_writel(0, &sun4m_irq_global->interrupt_target); - BTFIXUPSET_CALL(clear_clock_irq, sun4m_clear_clock_irq, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(load_profile_irq, sun4m_load_profile_irq, BTFIXUPCALL_NORM); - - sparc_irq_config.init_timers = sun4m_init_timers; - sparc_irq_config.build_device_irq = sun4m_build_device_irq; + sparc_config.init_timers = sun4m_init_timers; + sparc_config.build_device_irq = sun4m_build_device_irq; + sparc_config.clock_rate = SBUS_CLOCK_RATE; + sparc_config.clear_clock_irq = sun4m_clear_clock_irq; + sparc_config.load_profile_irq = sun4m_load_profile_irq; -#ifdef CONFIG_SMP - BTFIXUPSET_CALL(set_cpu_int, sun4m_send_ipi, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(clear_cpu_int, sun4m_clear_ipi, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(set_irq_udt, sun4m_set_udt, BTFIXUPCALL_NORM); -#endif /* Cannot enable interrupts until OBP ticker is disabled. */ } diff --git a/arch/sparc/kernel/sun4m_smp.c b/arch/sparc/kernel/sun4m_smp.c index 02db9a0412ce..960e8ab47b12 100644 --- a/arch/sparc/kernel/sun4m_smp.c +++ b/arch/sparc/kernel/sun4m_smp.c @@ -4,14 +4,18 @@ * Copyright (C) 1996 David S. Miller ([email protected]) */ +#include <linux/clockchips.h> #include <linux/interrupt.h> #include <linux/profile.h> #include <linux/delay.h> +#include <linux/sched.h> #include <linux/cpu.h> #include <asm/cacheflush.h> #include <asm/switch_to.h> #include <asm/tlbflush.h> +#include <asm/timer.h> +#include <asm/oplib.h> #include "irq.h" #include "kernel.h" @@ -30,26 +34,22 @@ swap_ulong(volatile unsigned long *ptr, unsigned long val) return val; } -static void smp4m_ipi_init(void); -static void smp_setup_percpu_timer(void); - void __cpuinit smp4m_callin(void) { int cpuid = hard_smp_processor_id(); - local_flush_cache_all(); - local_flush_tlb_all(); + local_ops->cache_all(); + local_ops->tlb_all(); notify_cpu_starting(cpuid); - /* Get our local ticker going. */ - smp_setup_percpu_timer(); + register_percpu_ce(cpuid); calibrate_delay(); smp_store_cpu_info(cpuid); - local_flush_cache_all(); - local_flush_tlb_all(); + local_ops->cache_all(); + local_ops->tlb_all(); /* * Unblock the master CPU _only_ when the scheduler state @@ -61,8 +61,8 @@ void __cpuinit smp4m_callin(void) swap_ulong(&cpu_callin_map[cpuid], 1); /* XXX: What's up with all the flushes? */ - local_flush_cache_all(); - local_flush_tlb_all(); + local_ops->cache_all(); + local_ops->tlb_all(); /* Fix idle thread fields. */ __asm__ __volatile__("ld [%0], %%g6\n\t" @@ -86,9 +86,8 @@ void __cpuinit smp4m_callin(void) */ void __init smp4m_boot_cpus(void) { - smp4m_ipi_init(); - smp_setup_percpu_timer(); - local_flush_cache_all(); + sun4m_unmask_profile_irq(); + local_ops->cache_all(); } int __cpuinit smp4m_boot_one_cpu(int i) @@ -117,7 +116,7 @@ int __cpuinit smp4m_boot_one_cpu(int i) /* whirrr, whirrr, whirrrrrrrrr... */ printk(KERN_INFO "Starting CPU %d at %p\n", i, entry); - local_flush_cache_all(); + local_ops->cache_all(); prom_startcpu(cpu_node, &smp_penguin_ctable, 0, (char *)entry); /* wheee... it's going... */ @@ -132,7 +131,7 @@ int __cpuinit smp4m_boot_one_cpu(int i) return -ENODEV; } - local_flush_cache_all(); + local_ops->cache_all(); return 0; } @@ -149,30 +148,29 @@ void __init smp4m_smp_done(void) prev = &cpu_data(i).next; } *prev = first; - local_flush_cache_all(); + local_ops->cache_all(); /* Ok, they are spinning and ready to go. */ } - -/* Initialize IPIs on the SUN4M SMP machine */ -static void __init smp4m_ipi_init(void) +static void sun4m_send_ipi(int cpu, int level) { + sbus_writel(SUN4M_SOFT_INT(level), &sun4m_irq_percpu[cpu]->set); } -static void smp4m_ipi_resched(int cpu) +static void sun4m_ipi_resched(int cpu) { - set_cpu_int(cpu, IRQ_IPI_RESCHED); + sun4m_send_ipi(cpu, IRQ_IPI_RESCHED); } -static void smp4m_ipi_single(int cpu) +static void sun4m_ipi_single(int cpu) { - set_cpu_int(cpu, IRQ_IPI_SINGLE); + sun4m_send_ipi(cpu, IRQ_IPI_SINGLE); } -static void smp4m_ipi_mask_one(int cpu) +static void sun4m_ipi_mask_one(int cpu) { - set_cpu_int(cpu, IRQ_IPI_MASK); + sun4m_send_ipi(cpu, IRQ_IPI_MASK); } static struct smp_funcall { @@ -189,7 +187,7 @@ static struct smp_funcall { static DEFINE_SPINLOCK(cross_call_lock); /* Cross calls must be serialized, at least currently. */ -static void smp4m_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1, +static void sun4m_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1, unsigned long arg2, unsigned long arg3, unsigned long arg4) { @@ -216,7 +214,7 @@ static void smp4m_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1, if (cpumask_test_cpu(i, &mask)) { ccall_info.processors_in[i] = 0; ccall_info.processors_out[i] = 0; - set_cpu_int(i, IRQ_CROSS_CALL); + sun4m_send_ipi(i, IRQ_CROSS_CALL); } else { ccall_info.processors_in[i] = 1; ccall_info.processors_out[i] = 1; @@ -260,64 +258,33 @@ void smp4m_cross_call_irq(void) void smp4m_percpu_timer_interrupt(struct pt_regs *regs) { struct pt_regs *old_regs; + struct clock_event_device *ce; int cpu = smp_processor_id(); old_regs = set_irq_regs(regs); - sun4m_clear_profile_irq(cpu); - - profile_tick(CPU_PROFILING); + ce = &per_cpu(sparc32_clockevent, cpu); - if (!--prof_counter(cpu)) { - int user = user_mode(regs); + if (ce->mode & CLOCK_EVT_MODE_PERIODIC) + sun4m_clear_profile_irq(cpu); + else + sparc_config.load_profile_irq(cpu, 0); /* Is this needless? */ - irq_enter(); - update_process_times(user); - irq_exit(); + irq_enter(); + ce->event_handler(ce); + irq_exit(); - prof_counter(cpu) = prof_multiplier(cpu); - } set_irq_regs(old_regs); } -static void __cpuinit smp_setup_percpu_timer(void) -{ - int cpu = smp_processor_id(); - - prof_counter(cpu) = prof_multiplier(cpu) = 1; - load_profile_irq(cpu, lvl14_resolution); - - if (cpu == boot_cpu_id) - sun4m_unmask_profile_irq(); -} - -static void __init smp4m_blackbox_id(unsigned *addr) -{ - int rd = *addr & 0x3e000000; - int rs1 = rd >> 11; - - addr[0] = 0x81580000 | rd; /* rd %tbr, reg */ - addr[1] = 0x8130200c | rd | rs1; /* srl reg, 0xc, reg */ - addr[2] = 0x80082003 | rd | rs1; /* and reg, 3, reg */ -} - -static void __init smp4m_blackbox_current(unsigned *addr) -{ - int rd = *addr & 0x3e000000; - int rs1 = rd >> 11; - - addr[0] = 0x81580000 | rd; /* rd %tbr, reg */ - addr[2] = 0x8130200a | rd | rs1; /* srl reg, 0xa, reg */ - addr[4] = 0x8008200c | rd | rs1; /* and reg, 0xc, reg */ -} +static const struct sparc32_ipi_ops sun4m_ipi_ops = { + .cross_call = sun4m_cross_call, + .resched = sun4m_ipi_resched, + .single = sun4m_ipi_single, + .mask_one = sun4m_ipi_mask_one, +}; void __init sun4m_init_smp(void) { - BTFIXUPSET_BLACKBOX(hard_smp_processor_id, smp4m_blackbox_id); - BTFIXUPSET_BLACKBOX(load_current, smp4m_blackbox_current); - BTFIXUPSET_CALL(smp_cross_call, smp4m_cross_call, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(__hard_smp_processor_id, __smp4m_processor_id, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(smp_ipi_resched, smp4m_ipi_resched, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(smp_ipi_single, smp4m_ipi_single, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(smp_ipi_mask_one, smp4m_ipi_mask_one, BTFIXUPCALL_NORM); + sparc32_ipi_ops = &sun4m_ipi_ops; } diff --git a/arch/sparc/kernel/sys_sparc_32.c b/arch/sparc/kernel/sys_sparc_32.c index 42b282fa6112..627e89af1d71 100644 --- a/arch/sparc/kernel/sys_sparc_32.c +++ b/arch/sparc/kernel/sys_sparc_32.c @@ -53,8 +53,6 @@ unsigned long arch_get_unmapped_area(struct file *filp, unsigned long addr, unsi /* See asm-sparc/uaccess.h */ if (len > TASK_SIZE - PAGE_SIZE) return -ENOMEM; - if (ARCH_SUN4C && len > 0x20000000) - return -ENOMEM; if (!addr) addr = TASK_UNMAPPED_BASE; @@ -65,10 +63,6 @@ unsigned long arch_get_unmapped_area(struct file *filp, unsigned long addr, unsi for (vmm = find_vma(current->mm, addr); ; vmm = vmm->vm_next) { /* At this point: (!vmm || addr < vmm->vm_end). */ - if (ARCH_SUN4C && addr < 0xe0000000 && 0x20000000 - len < addr) { - addr = PAGE_OFFSET; - vmm = find_vma(current->mm, PAGE_OFFSET); - } if (TASK_SIZE - PAGE_SIZE - len < addr) return -ENOMEM; if (!vmm || addr + len <= vmm->vm_start) @@ -99,11 +93,6 @@ out: int sparc_mmap_check(unsigned long addr, unsigned long len) { - if (ARCH_SUN4C && - (len > 0x20000000 || - (addr < 0xe0000000 && addr + len > 0x20000000))) - return -EINVAL; - /* See asm-sparc/uaccess.h */ if (len > TASK_SIZE - PAGE_SIZE || addr + len > TASK_SIZE - PAGE_SIZE) return -EINVAL; diff --git a/arch/sparc/kernel/sys_sparc_64.c b/arch/sparc/kernel/sys_sparc_64.c index 232df9949530..3ee51f189a55 100644 --- a/arch/sparc/kernel/sys_sparc_64.c +++ b/arch/sparc/kernel/sys_sparc_64.c @@ -566,15 +566,10 @@ out: SYSCALL_DEFINE2(64_munmap, unsigned long, addr, size_t, len) { - long ret; - if (invalid_64bit_range(addr, len)) return -EINVAL; - down_write(¤t->mm->mmap_sem); - ret = do_munmap(current->mm, addr, len); - up_write(¤t->mm->mmap_sem); - return ret; + return vm_munmap(addr, len); } extern unsigned long do_mremap(unsigned long addr, diff --git a/arch/sparc/kernel/time_32.c b/arch/sparc/kernel/time_32.c index 7d0c088e8aba..953641549e82 100644 --- a/arch/sparc/kernel/time_32.c +++ b/arch/sparc/kernel/time_32.c @@ -26,6 +26,8 @@ #include <linux/rtc.h> #include <linux/rtc/m48t59.h> #include <linux/timex.h> +#include <linux/clocksource.h> +#include <linux/clockchips.h> #include <linux/init.h> #include <linux/pci.h> #include <linux/ioport.h> @@ -40,13 +42,24 @@ #include <asm/irq.h> #include <asm/io.h> #include <asm/idprom.h> -#include <asm/machines.h> #include <asm/page.h> #include <asm/pcic.h> #include <asm/irq_regs.h> +#include <asm/setup.h> #include "irq.h" +static __cacheline_aligned_in_smp DEFINE_SEQLOCK(timer_cs_lock); +static __volatile__ u64 timer_cs_internal_counter = 0; +static char timer_cs_enabled = 0; + +static struct clock_event_device timer_ce; +static char timer_ce_enabled = 0; + +#ifdef CONFIG_SMP +DEFINE_PER_CPU(struct clock_event_device, sparc32_clockevent); +#endif + DEFINE_SPINLOCK(rtc_lock); EXPORT_SYMBOL(rtc_lock); @@ -55,7 +68,6 @@ static int set_rtc_mmss(unsigned long); unsigned long profile_pc(struct pt_regs *regs) { extern char __copy_user_begin[], __copy_user_end[]; - extern char __atomic_begin[], __atomic_end[]; extern char __bzero_begin[], __bzero_end[]; unsigned long pc = regs->pc; @@ -63,8 +75,6 @@ unsigned long profile_pc(struct pt_regs *regs) if (in_lock_functions(pc) || (pc >= (unsigned long) __copy_user_begin && pc < (unsigned long) __copy_user_end) || - (pc >= (unsigned long) __atomic_begin && - pc < (unsigned long) __atomic_end) || (pc >= (unsigned long) __bzero_begin && pc < (unsigned long) __bzero_end)) pc = regs->u_regs[UREG_RETPC]; @@ -75,36 +85,168 @@ EXPORT_SYMBOL(profile_pc); __volatile__ unsigned int *master_l10_counter; -u32 (*do_arch_gettimeoffset)(void); - int update_persistent_clock(struct timespec now) { return set_rtc_mmss(now.tv_sec); } -/* - * timer_interrupt() needs to keep up the real-time clock, - * as well as call the "xtime_update()" routine every clocktick - */ +irqreturn_t notrace timer_interrupt(int dummy, void *dev_id) +{ + if (timer_cs_enabled) { + write_seqlock(&timer_cs_lock); + timer_cs_internal_counter++; + sparc_config.clear_clock_irq(); + write_sequnlock(&timer_cs_lock); + } else { + sparc_config.clear_clock_irq(); + } -#define TICK_SIZE (tick_nsec / 1000) + if (timer_ce_enabled) + timer_ce.event_handler(&timer_ce); -static irqreturn_t timer_interrupt(int dummy, void *dev_id) + return IRQ_HANDLED; +} + +static void timer_ce_set_mode(enum clock_event_mode mode, + struct clock_event_device *evt) { -#ifndef CONFIG_SMP - profile_tick(CPU_PROFILING); -#endif + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + case CLOCK_EVT_MODE_RESUME: + timer_ce_enabled = 1; + break; + case CLOCK_EVT_MODE_SHUTDOWN: + timer_ce_enabled = 0; + break; + default: + break; + } + smp_mb(); +} - clear_clock_irq(); +static __init void setup_timer_ce(void) +{ + struct clock_event_device *ce = &timer_ce; + + BUG_ON(smp_processor_id() != boot_cpu_id); + + ce->name = "timer_ce"; + ce->rating = 100; + ce->features = CLOCK_EVT_FEAT_PERIODIC; + ce->set_mode = timer_ce_set_mode; + ce->cpumask = cpu_possible_mask; + ce->shift = 32; + ce->mult = div_sc(sparc_config.clock_rate, NSEC_PER_SEC, + ce->shift); + clockevents_register_device(ce); +} - xtime_update(1); +static unsigned int sbus_cycles_offset(void) +{ + unsigned int val, offset; -#ifndef CONFIG_SMP - update_process_times(user_mode(get_irq_regs())); -#endif - return IRQ_HANDLED; + val = *master_l10_counter; + offset = (val >> TIMER_VALUE_SHIFT) & TIMER_VALUE_MASK; + + /* Limit hit? */ + if (val & TIMER_LIMIT_BIT) + offset += sparc_config.cs_period; + + return offset; +} + +static cycle_t timer_cs_read(struct clocksource *cs) +{ + unsigned int seq, offset; + u64 cycles; + + do { + seq = read_seqbegin(&timer_cs_lock); + + cycles = timer_cs_internal_counter; + offset = sparc_config.get_cycles_offset(); + } while (read_seqretry(&timer_cs_lock, seq)); + + /* Count absolute cycles */ + cycles *= sparc_config.cs_period; + cycles += offset; + + return cycles; +} + +static struct clocksource timer_cs = { + .name = "timer_cs", + .rating = 100, + .read = timer_cs_read, + .mask = CLOCKSOURCE_MASK(64), + .shift = 2, + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +static __init int setup_timer_cs(void) +{ + timer_cs_enabled = 1; + timer_cs.mult = clocksource_hz2mult(sparc_config.clock_rate, + timer_cs.shift); + + return clocksource_register(&timer_cs); } +#ifdef CONFIG_SMP +static void percpu_ce_setup(enum clock_event_mode mode, + struct clock_event_device *evt) +{ + int cpu = __first_cpu(evt->cpumask); + + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + sparc_config.load_profile_irq(cpu, + SBUS_CLOCK_RATE / HZ); + break; + case CLOCK_EVT_MODE_ONESHOT: + case CLOCK_EVT_MODE_SHUTDOWN: + case CLOCK_EVT_MODE_UNUSED: + sparc_config.load_profile_irq(cpu, 0); + break; + default: + break; + } +} + +static int percpu_ce_set_next_event(unsigned long delta, + struct clock_event_device *evt) +{ + int cpu = __first_cpu(evt->cpumask); + unsigned int next = (unsigned int)delta; + + sparc_config.load_profile_irq(cpu, next); + return 0; +} + +void register_percpu_ce(int cpu) +{ + struct clock_event_device *ce = &per_cpu(sparc32_clockevent, cpu); + unsigned int features = CLOCK_EVT_FEAT_PERIODIC; + + if (sparc_config.features & FEAT_L14_ONESHOT) + features |= CLOCK_EVT_FEAT_ONESHOT; + + ce->name = "percpu_ce"; + ce->rating = 200; + ce->features = features; + ce->set_mode = percpu_ce_setup; + ce->set_next_event = percpu_ce_set_next_event; + ce->cpumask = cpumask_of(cpu); + ce->shift = 32; + ce->mult = div_sc(sparc_config.clock_rate, NSEC_PER_SEC, + ce->shift); + ce->max_delta_ns = clockevent_delta2ns(sparc_config.clock_rate, ce); + ce->min_delta_ns = clockevent_delta2ns(100, ce); + + clockevents_register_device(ce); +} +#endif + static unsigned char mostek_read_byte(struct device *dev, u32 ofs) { struct platform_device *pdev = to_platform_device(dev); @@ -195,38 +337,28 @@ static int __init clock_init(void) */ fs_initcall(clock_init); - -u32 sbus_do_gettimeoffset(void) -{ - unsigned long val = *master_l10_counter; - unsigned long usec = (val >> 10) & 0x1fffff; - - /* Limit hit? */ - if (val & 0x80000000) - usec += 1000000 / HZ; - - return usec * 1000; -} - - -u32 arch_gettimeoffset(void) +static void __init sparc32_late_time_init(void) { - if (unlikely(!do_arch_gettimeoffset)) - return 0; - return do_arch_gettimeoffset(); + if (sparc_config.features & FEAT_L10_CLOCKEVENT) + setup_timer_ce(); + if (sparc_config.features & FEAT_L10_CLOCKSOURCE) + setup_timer_cs(); +#ifdef CONFIG_SMP + register_percpu_ce(smp_processor_id()); +#endif } static void __init sbus_time_init(void) { - do_arch_gettimeoffset = sbus_do_gettimeoffset; - - btfixup(); - - sparc_irq_config.init_timers(timer_interrupt); + sparc_config.get_cycles_offset = sbus_cycles_offset; + sparc_config.init_timers(); } void __init time_init(void) { + sparc_config.features = 0; + late_time_init = sparc32_late_time_init; + if (pcic_present()) pci_time_init(); else diff --git a/arch/sparc/kernel/trampoline_32.S b/arch/sparc/kernel/trampoline_32.S index 691f484e03b3..7364ddc9e5aa 100644 --- a/arch/sparc/kernel/trampoline_32.S +++ b/arch/sparc/kernel/trampoline_32.S @@ -15,8 +15,8 @@ #include <asm/contregs.h> #include <asm/thread_info.h> - .globl sun4m_cpu_startup, __smp4m_processor_id, __leon_processor_id - .globl sun4d_cpu_startup, __smp4d_processor_id + .globl sun4m_cpu_startup + .globl sun4d_cpu_startup __CPUINIT .align 4 @@ -94,24 +94,6 @@ smp_do_cpu_idle: call cpu_panic nop -__smp4m_processor_id: - rd %tbr, %g2 - srl %g2, 12, %g2 - and %g2, 3, %g2 - retl - mov %g1, %o7 - -__smp4d_processor_id: - lda [%g0] ASI_M_VIKING_TMP1, %g2 - retl - mov %g1, %o7 - -__leon_processor_id: - rd %asr17,%g2 - srl %g2,28,%g2 - retl - mov %g1, %o7 - /* CPUID in bootbus can be found at PA 0xff0140000 */ #define SUN4D_BOOTBUS_CPUID 0xf0140000 diff --git a/arch/sparc/kernel/traps_32.c b/arch/sparc/kernel/traps_32.c index d2de21333146..a5785ea2a85d 100644 --- a/arch/sparc/kernel/traps_32.c +++ b/arch/sparc/kernel/traps_32.c @@ -120,8 +120,6 @@ void do_illegal_instruction(struct pt_regs *regs, unsigned long pc, unsigned lon printk("Ill instr. at pc=%08lx instruction is %08lx\n", regs->pc, *(unsigned long *)regs->pc); #endif - if (!do_user_muldiv (regs, pc)) - return; info.si_signo = SIGILL; info.si_errno = 0; diff --git a/arch/sparc/kernel/ttable_32.S b/arch/sparc/kernel/ttable_32.S new file mode 100644 index 000000000000..8a7a96ca676f --- /dev/null +++ b/arch/sparc/kernel/ttable_32.S @@ -0,0 +1,417 @@ +/* The Sparc trap table, bootloader gives us control at _start. */ + __HEAD + + .globl _start +_start: + + .globl _stext +_stext: + + .globl trapbase +trapbase: + +#ifdef CONFIG_SMP +trapbase_cpu0: +#endif +/* We get control passed to us here at t_zero. */ +t_zero: b gokernel; nop; nop; nop; +t_tflt: SRMMU_TFAULT /* Inst. Access Exception */ +t_bins: TRAP_ENTRY(0x2, bad_instruction) /* Illegal Instruction */ +t_pins: TRAP_ENTRY(0x3, priv_instruction) /* Privileged Instruction */ +t_fpd: TRAP_ENTRY(0x4, fpd_trap_handler) /* Floating Point Disabled */ +t_wovf: WINDOW_SPILL /* Window Overflow */ +t_wunf: WINDOW_FILL /* Window Underflow */ +t_mna: TRAP_ENTRY(0x7, mna_handler) /* Memory Address Not Aligned */ +t_fpe: TRAP_ENTRY(0x8, fpe_trap_handler) /* Floating Point Exception */ +t_dflt: SRMMU_DFAULT /* Data Miss Exception */ +t_tio: TRAP_ENTRY(0xa, do_tag_overflow) /* Tagged Instruction Ovrflw */ +t_wpt: TRAP_ENTRY(0xb, do_watchpoint) /* Watchpoint Detected */ +t_badc: BAD_TRAP(0xc) BAD_TRAP(0xd) BAD_TRAP(0xe) BAD_TRAP(0xf) BAD_TRAP(0x10) +t_irq1: TRAP_ENTRY_INTERRUPT(1) /* IRQ Software/SBUS Level 1 */ +t_irq2: TRAP_ENTRY_INTERRUPT(2) /* IRQ SBUS Level 2 */ +t_irq3: TRAP_ENTRY_INTERRUPT(3) /* IRQ SCSI/DMA/SBUS Level 3 */ +t_irq4: TRAP_ENTRY_INTERRUPT(4) /* IRQ Software Level 4 */ +t_irq5: TRAP_ENTRY_INTERRUPT(5) /* IRQ SBUS/Ethernet Level 5 */ +t_irq6: TRAP_ENTRY_INTERRUPT(6) /* IRQ Software Level 6 */ +t_irq7: TRAP_ENTRY_INTERRUPT(7) /* IRQ Video/SBUS Level 5 */ +t_irq8: TRAP_ENTRY_INTERRUPT(8) /* IRQ SBUS Level 6 */ +t_irq9: TRAP_ENTRY_INTERRUPT(9) /* IRQ SBUS Level 7 */ +t_irq10:TRAP_ENTRY_INTERRUPT(10) /* IRQ Timer #1 (one we use) */ +t_irq11:TRAP_ENTRY_INTERRUPT(11) /* IRQ Floppy Intr. */ +t_irq12:TRAP_ENTRY_INTERRUPT(12) /* IRQ Zilog serial chip */ +t_irq13:TRAP_ENTRY_INTERRUPT(13) /* IRQ Audio Intr. */ +t_irq14:TRAP_ENTRY_INTERRUPT(14) /* IRQ Timer #2 */ + + .globl t_nmi +t_nmi: TRAP_ENTRY(0x1f, linux_trap_ipi15_sun4m) + +t_racc: TRAP_ENTRY(0x20, do_reg_access) /* General Register Access Error */ +t_iacce:BAD_TRAP(0x21) /* Instr Access Error */ +t_bad22:BAD_TRAP(0x22) + BAD_TRAP(0x23) +t_cpdis:TRAP_ENTRY(0x24, do_cp_disabled) /* Co-Processor Disabled */ +t_uflsh:SKIP_TRAP(0x25, unimp_flush) /* Unimplemented FLUSH inst. */ +t_bad26:BAD_TRAP(0x26) BAD_TRAP(0x27) +t_cpexc:TRAP_ENTRY(0x28, do_cp_exception) /* Co-Processor Exception */ +t_dacce:SRMMU_DFAULT /* Data Access Error */ +t_hwdz: TRAP_ENTRY(0x2a, do_hw_divzero) /* Division by zero, you lose... */ +t_dserr:BAD_TRAP(0x2b) /* Data Store Error */ +t_daccm:BAD_TRAP(0x2c) /* Data Access MMU-Miss */ +t_bad2d:BAD_TRAP(0x2d) BAD_TRAP(0x2e) BAD_TRAP(0x2f) BAD_TRAP(0x30) BAD_TRAP(0x31) +t_bad32:BAD_TRAP(0x32) BAD_TRAP(0x33) BAD_TRAP(0x34) BAD_TRAP(0x35) BAD_TRAP(0x36) +t_bad37:BAD_TRAP(0x37) BAD_TRAP(0x38) BAD_TRAP(0x39) BAD_TRAP(0x3a) BAD_TRAP(0x3b) +t_iaccm:BAD_TRAP(0x3c) /* Instr Access MMU-Miss */ +t_bad3d:BAD_TRAP(0x3d) BAD_TRAP(0x3e) BAD_TRAP(0x3f) BAD_TRAP(0x40) BAD_TRAP(0x41) +t_bad42:BAD_TRAP(0x42) BAD_TRAP(0x43) BAD_TRAP(0x44) BAD_TRAP(0x45) BAD_TRAP(0x46) +t_bad47:BAD_TRAP(0x47) BAD_TRAP(0x48) BAD_TRAP(0x49) BAD_TRAP(0x4a) BAD_TRAP(0x4b) +t_bad4c:BAD_TRAP(0x4c) BAD_TRAP(0x4d) BAD_TRAP(0x4e) BAD_TRAP(0x4f) BAD_TRAP(0x50) +t_bad51:BAD_TRAP(0x51) BAD_TRAP(0x52) BAD_TRAP(0x53) BAD_TRAP(0x54) BAD_TRAP(0x55) +t_bad56:BAD_TRAP(0x56) BAD_TRAP(0x57) BAD_TRAP(0x58) BAD_TRAP(0x59) BAD_TRAP(0x5a) +t_bad5b:BAD_TRAP(0x5b) BAD_TRAP(0x5c) BAD_TRAP(0x5d) BAD_TRAP(0x5e) BAD_TRAP(0x5f) +t_bad60:BAD_TRAP(0x60) BAD_TRAP(0x61) BAD_TRAP(0x62) BAD_TRAP(0x63) BAD_TRAP(0x64) +t_bad65:BAD_TRAP(0x65) BAD_TRAP(0x66) BAD_TRAP(0x67) BAD_TRAP(0x68) BAD_TRAP(0x69) +t_bad6a:BAD_TRAP(0x6a) BAD_TRAP(0x6b) BAD_TRAP(0x6c) BAD_TRAP(0x6d) BAD_TRAP(0x6e) +t_bad6f:BAD_TRAP(0x6f) BAD_TRAP(0x70) BAD_TRAP(0x71) BAD_TRAP(0x72) BAD_TRAP(0x73) +t_bad74:BAD_TRAP(0x74) BAD_TRAP(0x75) BAD_TRAP(0x76) BAD_TRAP(0x77) BAD_TRAP(0x78) +t_bad79:BAD_TRAP(0x79) BAD_TRAP(0x7a) BAD_TRAP(0x7b) BAD_TRAP(0x7c) BAD_TRAP(0x7d) +t_bad7e:BAD_TRAP(0x7e) BAD_TRAP(0x7f) +t_bad80:BAD_TRAP(0x80) /* SunOS System Call */ +t_sbkpt:BREAKPOINT_TRAP /* Software Breakpoint/KGDB */ +t_divz: TRAP_ENTRY(0x82, do_hw_divzero) /* Divide by zero trap */ +t_flwin:TRAP_ENTRY(0x83, do_flush_windows) /* Flush Windows Trap */ +t_clwin:BAD_TRAP(0x84) /* Clean Windows Trap */ +t_rchk: BAD_TRAP(0x85) /* Range Check */ +t_funal:BAD_TRAP(0x86) /* Fix Unaligned Access Trap */ +t_iovf: BAD_TRAP(0x87) /* Integer Overflow Trap */ +t_bad88:BAD_TRAP(0x88) /* Slowaris System Call */ +t_bad89:BAD_TRAP(0x89) /* Net-B.S. System Call */ +t_bad8a:BAD_TRAP(0x8a) BAD_TRAP(0x8b) BAD_TRAP(0x8c) BAD_TRAP(0x8d) BAD_TRAP(0x8e) +t_bad8f:BAD_TRAP(0x8f) +t_linux:LINUX_SYSCALL_TRAP /* Linux System Call */ +t_bad91:BAD_TRAP(0x91) BAD_TRAP(0x92) BAD_TRAP(0x93) BAD_TRAP(0x94) BAD_TRAP(0x95) +t_bad96:BAD_TRAP(0x96) BAD_TRAP(0x97) BAD_TRAP(0x98) BAD_TRAP(0x99) BAD_TRAP(0x9a) +t_bad9b:BAD_TRAP(0x9b) BAD_TRAP(0x9c) BAD_TRAP(0x9d) BAD_TRAP(0x9e) BAD_TRAP(0x9f) +t_getcc:GETCC_TRAP /* Get Condition Codes */ +t_setcc:SETCC_TRAP /* Set Condition Codes */ +t_getpsr:GETPSR_TRAP /* Get PSR Register */ +t_bada3:BAD_TRAP(0xa3) BAD_TRAP(0xa4) BAD_TRAP(0xa5) BAD_TRAP(0xa6) +t_bada7:BAD_TRAP(0xa7) +t_bada8:BAD_TRAP(0xa8) BAD_TRAP(0xa9) BAD_TRAP(0xaa) BAD_TRAP(0xab) +t_badac:BAD_TRAP(0xac) BAD_TRAP(0xad) BAD_TRAP(0xae) BAD_TRAP(0xaf) BAD_TRAP(0xb0) +t_badb1:BAD_TRAP(0xb1) BAD_TRAP(0xb2) BAD_TRAP(0xb3) BAD_TRAP(0xb4) BAD_TRAP(0xb5) +t_badb6:BAD_TRAP(0xb6) BAD_TRAP(0xb7) BAD_TRAP(0xb8) BAD_TRAP(0xb9) BAD_TRAP(0xba) +t_badbb:BAD_TRAP(0xbb) BAD_TRAP(0xbc) BAD_TRAP(0xbd) BAD_TRAP(0xbe) BAD_TRAP(0xbf) +t_badc0:BAD_TRAP(0xc0) BAD_TRAP(0xc1) BAD_TRAP(0xc2) BAD_TRAP(0xc3) BAD_TRAP(0xc4) +t_badc5:BAD_TRAP(0xc5) BAD_TRAP(0xc6) BAD_TRAP(0xc7) BAD_TRAP(0xc8) BAD_TRAP(0xc9) +t_badca:BAD_TRAP(0xca) BAD_TRAP(0xcb) BAD_TRAP(0xcc) BAD_TRAP(0xcd) BAD_TRAP(0xce) +t_badcf:BAD_TRAP(0xcf) BAD_TRAP(0xd0) BAD_TRAP(0xd1) BAD_TRAP(0xd2) BAD_TRAP(0xd3) +t_badd4:BAD_TRAP(0xd4) BAD_TRAP(0xd5) BAD_TRAP(0xd6) BAD_TRAP(0xd7) BAD_TRAP(0xd8) +t_badd9:BAD_TRAP(0xd9) BAD_TRAP(0xda) BAD_TRAP(0xdb) BAD_TRAP(0xdc) BAD_TRAP(0xdd) +t_badde:BAD_TRAP(0xde) BAD_TRAP(0xdf) BAD_TRAP(0xe0) BAD_TRAP(0xe1) BAD_TRAP(0xe2) +t_bade3:BAD_TRAP(0xe3) BAD_TRAP(0xe4) BAD_TRAP(0xe5) BAD_TRAP(0xe6) BAD_TRAP(0xe7) +t_bade8:BAD_TRAP(0xe8) BAD_TRAP(0xe9) BAD_TRAP(0xea) BAD_TRAP(0xeb) BAD_TRAP(0xec) +t_baded:BAD_TRAP(0xed) BAD_TRAP(0xee) BAD_TRAP(0xef) BAD_TRAP(0xf0) BAD_TRAP(0xf1) +t_badf2:BAD_TRAP(0xf2) BAD_TRAP(0xf3) BAD_TRAP(0xf4) BAD_TRAP(0xf5) BAD_TRAP(0xf6) +t_badf7:BAD_TRAP(0xf7) BAD_TRAP(0xf8) BAD_TRAP(0xf9) BAD_TRAP(0xfa) BAD_TRAP(0xfb) +t_badfc:BAD_TRAP(0xfc) +t_kgdb: KGDB_TRAP(0xfd) +dbtrap: BAD_TRAP(0xfe) /* Debugger/PROM breakpoint #1 */ +dbtrap2:BAD_TRAP(0xff) /* Debugger/PROM breakpoint #2 */ + + .globl end_traptable +end_traptable: + +#ifdef CONFIG_SMP + /* Trap tables for the other cpus. */ + .globl trapbase_cpu1, trapbase_cpu2, trapbase_cpu3 +trapbase_cpu1: + BAD_TRAP(0x0) + SRMMU_TFAULT + TRAP_ENTRY(0x2, bad_instruction) + TRAP_ENTRY(0x3, priv_instruction) + TRAP_ENTRY(0x4, fpd_trap_handler) + WINDOW_SPILL + WINDOW_FILL + TRAP_ENTRY(0x7, mna_handler) + TRAP_ENTRY(0x8, fpe_trap_handler) + SRMMU_DFAULT + TRAP_ENTRY(0xa, do_tag_overflow) + TRAP_ENTRY(0xb, do_watchpoint) + BAD_TRAP(0xc) BAD_TRAP(0xd) BAD_TRAP(0xe) BAD_TRAP(0xf) BAD_TRAP(0x10) + TRAP_ENTRY_INTERRUPT(1) TRAP_ENTRY_INTERRUPT(2) + TRAP_ENTRY_INTERRUPT(3) TRAP_ENTRY_INTERRUPT(4) + TRAP_ENTRY_INTERRUPT(5) TRAP_ENTRY_INTERRUPT(6) + TRAP_ENTRY_INTERRUPT(7) TRAP_ENTRY_INTERRUPT(8) + TRAP_ENTRY_INTERRUPT(9) TRAP_ENTRY_INTERRUPT(10) + TRAP_ENTRY_INTERRUPT(11) TRAP_ENTRY_INTERRUPT(12) + TRAP_ENTRY_INTERRUPT(13) TRAP_ENTRY_INTERRUPT(14) + TRAP_ENTRY(0x1f, linux_trap_ipi15_sun4m) + TRAP_ENTRY(0x20, do_reg_access) + BAD_TRAP(0x21) + BAD_TRAP(0x22) + BAD_TRAP(0x23) + TRAP_ENTRY(0x24, do_cp_disabled) + SKIP_TRAP(0x25, unimp_flush) + BAD_TRAP(0x26) + BAD_TRAP(0x27) + TRAP_ENTRY(0x28, do_cp_exception) + SRMMU_DFAULT + TRAP_ENTRY(0x2a, do_hw_divzero) + BAD_TRAP(0x2b) + BAD_TRAP(0x2c) + BAD_TRAP(0x2d) BAD_TRAP(0x2e) BAD_TRAP(0x2f) BAD_TRAP(0x30) BAD_TRAP(0x31) + BAD_TRAP(0x32) BAD_TRAP(0x33) BAD_TRAP(0x34) BAD_TRAP(0x35) BAD_TRAP(0x36) + BAD_TRAP(0x37) BAD_TRAP(0x38) BAD_TRAP(0x39) BAD_TRAP(0x3a) BAD_TRAP(0x3b) + BAD_TRAP(0x3c) BAD_TRAP(0x3d) BAD_TRAP(0x3e) BAD_TRAP(0x3f) BAD_TRAP(0x40) + BAD_TRAP(0x41) BAD_TRAP(0x42) BAD_TRAP(0x43) BAD_TRAP(0x44) BAD_TRAP(0x45) + BAD_TRAP(0x46) BAD_TRAP(0x47) BAD_TRAP(0x48) BAD_TRAP(0x49) BAD_TRAP(0x4a) + BAD_TRAP(0x4b) BAD_TRAP(0x4c) BAD_TRAP(0x4d) BAD_TRAP(0x4e) BAD_TRAP(0x4f) + BAD_TRAP(0x50) + BAD_TRAP(0x51) BAD_TRAP(0x52) BAD_TRAP(0x53) BAD_TRAP(0x54) BAD_TRAP(0x55) + BAD_TRAP(0x56) BAD_TRAP(0x57) BAD_TRAP(0x58) BAD_TRAP(0x59) BAD_TRAP(0x5a) + BAD_TRAP(0x5b) BAD_TRAP(0x5c) BAD_TRAP(0x5d) BAD_TRAP(0x5e) BAD_TRAP(0x5f) + BAD_TRAP(0x60) BAD_TRAP(0x61) BAD_TRAP(0x62) BAD_TRAP(0x63) BAD_TRAP(0x64) + BAD_TRAP(0x65) BAD_TRAP(0x66) BAD_TRAP(0x67) BAD_TRAP(0x68) BAD_TRAP(0x69) + BAD_TRAP(0x6a) BAD_TRAP(0x6b) BAD_TRAP(0x6c) BAD_TRAP(0x6d) BAD_TRAP(0x6e) + BAD_TRAP(0x6f) BAD_TRAP(0x70) BAD_TRAP(0x71) BAD_TRAP(0x72) BAD_TRAP(0x73) + BAD_TRAP(0x74) BAD_TRAP(0x75) BAD_TRAP(0x76) BAD_TRAP(0x77) BAD_TRAP(0x78) + BAD_TRAP(0x79) BAD_TRAP(0x7a) BAD_TRAP(0x7b) BAD_TRAP(0x7c) BAD_TRAP(0x7d) + BAD_TRAP(0x7e) BAD_TRAP(0x7f) + BAD_TRAP(0x80) + BREAKPOINT_TRAP + TRAP_ENTRY(0x82, do_hw_divzero) + TRAP_ENTRY(0x83, do_flush_windows) + BAD_TRAP(0x84) BAD_TRAP(0x85) BAD_TRAP(0x86) + BAD_TRAP(0x87) BAD_TRAP(0x88) BAD_TRAP(0x89) + BAD_TRAP(0x8a) BAD_TRAP(0x8b) BAD_TRAP(0x8c) + BAD_TRAP(0x8d) BAD_TRAP(0x8e) BAD_TRAP(0x8f) + LINUX_SYSCALL_TRAP BAD_TRAP(0x91) + BAD_TRAP(0x92) BAD_TRAP(0x93) BAD_TRAP(0x94) + BAD_TRAP(0x95) BAD_TRAP(0x96) BAD_TRAP(0x97) BAD_TRAP(0x98) BAD_TRAP(0x99) + BAD_TRAP(0x9a) BAD_TRAP(0x9b) BAD_TRAP(0x9c) BAD_TRAP(0x9d) BAD_TRAP(0x9e) + BAD_TRAP(0x9f) + GETCC_TRAP + SETCC_TRAP + GETPSR_TRAP + BAD_TRAP(0xa3) BAD_TRAP(0xa4) BAD_TRAP(0xa5) BAD_TRAP(0xa6) + BAD_TRAP(0xa7) BAD_TRAP(0xa8) BAD_TRAP(0xa9) BAD_TRAP(0xaa) BAD_TRAP(0xab) + BAD_TRAP(0xac) BAD_TRAP(0xad) BAD_TRAP(0xae) BAD_TRAP(0xaf) BAD_TRAP(0xb0) + BAD_TRAP(0xb1) BAD_TRAP(0xb2) BAD_TRAP(0xb3) BAD_TRAP(0xb4) BAD_TRAP(0xb5) + BAD_TRAP(0xb6) BAD_TRAP(0xb7) BAD_TRAP(0xb8) BAD_TRAP(0xb9) BAD_TRAP(0xba) + BAD_TRAP(0xbb) BAD_TRAP(0xbc) BAD_TRAP(0xbd) BAD_TRAP(0xbe) BAD_TRAP(0xbf) + BAD_TRAP(0xc0) BAD_TRAP(0xc1) BAD_TRAP(0xc2) BAD_TRAP(0xc3) BAD_TRAP(0xc4) + BAD_TRAP(0xc5) BAD_TRAP(0xc6) BAD_TRAP(0xc7) BAD_TRAP(0xc8) BAD_TRAP(0xc9) + BAD_TRAP(0xca) BAD_TRAP(0xcb) BAD_TRAP(0xcc) BAD_TRAP(0xcd) BAD_TRAP(0xce) + BAD_TRAP(0xcf) BAD_TRAP(0xd0) BAD_TRAP(0xd1) BAD_TRAP(0xd2) BAD_TRAP(0xd3) + BAD_TRAP(0xd4) BAD_TRAP(0xd5) BAD_TRAP(0xd6) BAD_TRAP(0xd7) BAD_TRAP(0xd8) + BAD_TRAP(0xd9) BAD_TRAP(0xda) BAD_TRAP(0xdb) BAD_TRAP(0xdc) BAD_TRAP(0xdd) + BAD_TRAP(0xde) BAD_TRAP(0xdf) BAD_TRAP(0xe0) BAD_TRAP(0xe1) BAD_TRAP(0xe2) + BAD_TRAP(0xe3) BAD_TRAP(0xe4) BAD_TRAP(0xe5) BAD_TRAP(0xe6) BAD_TRAP(0xe7) + BAD_TRAP(0xe8) BAD_TRAP(0xe9) BAD_TRAP(0xea) BAD_TRAP(0xeb) BAD_TRAP(0xec) + BAD_TRAP(0xed) BAD_TRAP(0xee) BAD_TRAP(0xef) BAD_TRAP(0xf0) BAD_TRAP(0xf1) + BAD_TRAP(0xf2) BAD_TRAP(0xf3) BAD_TRAP(0xf4) BAD_TRAP(0xf5) BAD_TRAP(0xf6) + BAD_TRAP(0xf7) BAD_TRAP(0xf8) BAD_TRAP(0xf9) BAD_TRAP(0xfa) BAD_TRAP(0xfb) + BAD_TRAP(0xfc) + KGDB_TRAP(0xfd) + BAD_TRAP(0xfe) + BAD_TRAP(0xff) + +trapbase_cpu2: + BAD_TRAP(0x0) + SRMMU_TFAULT + TRAP_ENTRY(0x2, bad_instruction) + TRAP_ENTRY(0x3, priv_instruction) + TRAP_ENTRY(0x4, fpd_trap_handler) + WINDOW_SPILL + WINDOW_FILL + TRAP_ENTRY(0x7, mna_handler) + TRAP_ENTRY(0x8, fpe_trap_handler) + SRMMU_DFAULT + TRAP_ENTRY(0xa, do_tag_overflow) + TRAP_ENTRY(0xb, do_watchpoint) + BAD_TRAP(0xc) BAD_TRAP(0xd) BAD_TRAP(0xe) BAD_TRAP(0xf) BAD_TRAP(0x10) + TRAP_ENTRY_INTERRUPT(1) + TRAP_ENTRY_INTERRUPT(2) + TRAP_ENTRY_INTERRUPT(3) + TRAP_ENTRY_INTERRUPT(4) + TRAP_ENTRY_INTERRUPT(5) + TRAP_ENTRY_INTERRUPT(6) + TRAP_ENTRY_INTERRUPT(7) + TRAP_ENTRY_INTERRUPT(8) + TRAP_ENTRY_INTERRUPT(9) + TRAP_ENTRY_INTERRUPT(10) + TRAP_ENTRY_INTERRUPT(11) + TRAP_ENTRY_INTERRUPT(12) + TRAP_ENTRY_INTERRUPT(13) + TRAP_ENTRY_INTERRUPT(14) + TRAP_ENTRY(0x1f, linux_trap_ipi15_sun4m) + TRAP_ENTRY(0x20, do_reg_access) + BAD_TRAP(0x21) + BAD_TRAP(0x22) + BAD_TRAP(0x23) + TRAP_ENTRY(0x24, do_cp_disabled) + SKIP_TRAP(0x25, unimp_flush) + BAD_TRAP(0x26) + BAD_TRAP(0x27) + TRAP_ENTRY(0x28, do_cp_exception) + SRMMU_DFAULT + TRAP_ENTRY(0x2a, do_hw_divzero) + BAD_TRAP(0x2b) + BAD_TRAP(0x2c) + BAD_TRAP(0x2d) BAD_TRAP(0x2e) BAD_TRAP(0x2f) BAD_TRAP(0x30) BAD_TRAP(0x31) + BAD_TRAP(0x32) BAD_TRAP(0x33) BAD_TRAP(0x34) BAD_TRAP(0x35) BAD_TRAP(0x36) + BAD_TRAP(0x37) BAD_TRAP(0x38) BAD_TRAP(0x39) BAD_TRAP(0x3a) BAD_TRAP(0x3b) + BAD_TRAP(0x3c) BAD_TRAP(0x3d) BAD_TRAP(0x3e) BAD_TRAP(0x3f) BAD_TRAP(0x40) + BAD_TRAP(0x41) BAD_TRAP(0x42) BAD_TRAP(0x43) BAD_TRAP(0x44) BAD_TRAP(0x45) + BAD_TRAP(0x46) BAD_TRAP(0x47) BAD_TRAP(0x48) BAD_TRAP(0x49) BAD_TRAP(0x4a) + BAD_TRAP(0x4b) BAD_TRAP(0x4c) BAD_TRAP(0x4d) BAD_TRAP(0x4e) BAD_TRAP(0x4f) + BAD_TRAP(0x50) + BAD_TRAP(0x51) BAD_TRAP(0x52) BAD_TRAP(0x53) BAD_TRAP(0x54) BAD_TRAP(0x55) + BAD_TRAP(0x56) BAD_TRAP(0x57) BAD_TRAP(0x58) BAD_TRAP(0x59) BAD_TRAP(0x5a) + BAD_TRAP(0x5b) BAD_TRAP(0x5c) BAD_TRAP(0x5d) BAD_TRAP(0x5e) BAD_TRAP(0x5f) + BAD_TRAP(0x60) BAD_TRAP(0x61) BAD_TRAP(0x62) BAD_TRAP(0x63) BAD_TRAP(0x64) + BAD_TRAP(0x65) BAD_TRAP(0x66) BAD_TRAP(0x67) BAD_TRAP(0x68) BAD_TRAP(0x69) + BAD_TRAP(0x6a) BAD_TRAP(0x6b) BAD_TRAP(0x6c) BAD_TRAP(0x6d) BAD_TRAP(0x6e) + BAD_TRAP(0x6f) BAD_TRAP(0x70) BAD_TRAP(0x71) BAD_TRAP(0x72) BAD_TRAP(0x73) + BAD_TRAP(0x74) BAD_TRAP(0x75) BAD_TRAP(0x76) BAD_TRAP(0x77) BAD_TRAP(0x78) + BAD_TRAP(0x79) BAD_TRAP(0x7a) BAD_TRAP(0x7b) BAD_TRAP(0x7c) BAD_TRAP(0x7d) + BAD_TRAP(0x7e) BAD_TRAP(0x7f) + BAD_TRAP(0x80) + BREAKPOINT_TRAP + TRAP_ENTRY(0x82, do_hw_divzero) + TRAP_ENTRY(0x83, do_flush_windows) + BAD_TRAP(0x84) + BAD_TRAP(0x85) + BAD_TRAP(0x86) BAD_TRAP(0x87) BAD_TRAP(0x88) + BAD_TRAP(0x89) BAD_TRAP(0x8a) BAD_TRAP(0x8b) BAD_TRAP(0x8c) + BAD_TRAP(0x8d) BAD_TRAP(0x8e) BAD_TRAP(0x8f) + LINUX_SYSCALL_TRAP BAD_TRAP(0x91) + BAD_TRAP(0x92) BAD_TRAP(0x93) BAD_TRAP(0x94) + BAD_TRAP(0x95) BAD_TRAP(0x96) BAD_TRAP(0x97) BAD_TRAP(0x98) BAD_TRAP(0x99) + BAD_TRAP(0x9a) BAD_TRAP(0x9b) BAD_TRAP(0x9c) BAD_TRAP(0x9d) BAD_TRAP(0x9e) + BAD_TRAP(0x9f) + GETCC_TRAP + SETCC_TRAP + GETPSR_TRAP + BAD_TRAP(0xa3) BAD_TRAP(0xa4) BAD_TRAP(0xa5) BAD_TRAP(0xa6) + BAD_TRAP(0xa7) BAD_TRAP(0xa8) BAD_TRAP(0xa9) BAD_TRAP(0xaa) BAD_TRAP(0xab) + BAD_TRAP(0xac) BAD_TRAP(0xad) BAD_TRAP(0xae) BAD_TRAP(0xaf) BAD_TRAP(0xb0) + BAD_TRAP(0xb1) BAD_TRAP(0xb2) BAD_TRAP(0xb3) BAD_TRAP(0xb4) BAD_TRAP(0xb5) + BAD_TRAP(0xb6) BAD_TRAP(0xb7) BAD_TRAP(0xb8) BAD_TRAP(0xb9) BAD_TRAP(0xba) + BAD_TRAP(0xbb) BAD_TRAP(0xbc) BAD_TRAP(0xbd) BAD_TRAP(0xbe) BAD_TRAP(0xbf) + BAD_TRAP(0xc0) BAD_TRAP(0xc1) BAD_TRAP(0xc2) BAD_TRAP(0xc3) BAD_TRAP(0xc4) + BAD_TRAP(0xc5) BAD_TRAP(0xc6) BAD_TRAP(0xc7) BAD_TRAP(0xc8) BAD_TRAP(0xc9) + BAD_TRAP(0xca) BAD_TRAP(0xcb) BAD_TRAP(0xcc) BAD_TRAP(0xcd) BAD_TRAP(0xce) + BAD_TRAP(0xcf) BAD_TRAP(0xd0) BAD_TRAP(0xd1) BAD_TRAP(0xd2) BAD_TRAP(0xd3) + BAD_TRAP(0xd4) BAD_TRAP(0xd5) BAD_TRAP(0xd6) BAD_TRAP(0xd7) BAD_TRAP(0xd8) + BAD_TRAP(0xd9) BAD_TRAP(0xda) BAD_TRAP(0xdb) BAD_TRAP(0xdc) BAD_TRAP(0xdd) + BAD_TRAP(0xde) BAD_TRAP(0xdf) BAD_TRAP(0xe0) BAD_TRAP(0xe1) BAD_TRAP(0xe2) + BAD_TRAP(0xe3) BAD_TRAP(0xe4) BAD_TRAP(0xe5) BAD_TRAP(0xe6) BAD_TRAP(0xe7) + BAD_TRAP(0xe8) BAD_TRAP(0xe9) BAD_TRAP(0xea) BAD_TRAP(0xeb) BAD_TRAP(0xec) + BAD_TRAP(0xed) BAD_TRAP(0xee) BAD_TRAP(0xef) BAD_TRAP(0xf0) BAD_TRAP(0xf1) + BAD_TRAP(0xf2) BAD_TRAP(0xf3) BAD_TRAP(0xf4) BAD_TRAP(0xf5) BAD_TRAP(0xf6) + BAD_TRAP(0xf7) BAD_TRAP(0xf8) BAD_TRAP(0xf9) BAD_TRAP(0xfa) BAD_TRAP(0xfb) + BAD_TRAP(0xfc) + KGDB_TRAP(0xfd) + BAD_TRAP(0xfe) + BAD_TRAP(0xff) + +trapbase_cpu3: + BAD_TRAP(0x0) + SRMMU_TFAULT + TRAP_ENTRY(0x2, bad_instruction) + TRAP_ENTRY(0x3, priv_instruction) + TRAP_ENTRY(0x4, fpd_trap_handler) + WINDOW_SPILL + WINDOW_FILL + TRAP_ENTRY(0x7, mna_handler) + TRAP_ENTRY(0x8, fpe_trap_handler) + SRMMU_DFAULT + TRAP_ENTRY(0xa, do_tag_overflow) + TRAP_ENTRY(0xb, do_watchpoint) + BAD_TRAP(0xc) BAD_TRAP(0xd) BAD_TRAP(0xe) BAD_TRAP(0xf) BAD_TRAP(0x10) + TRAP_ENTRY_INTERRUPT(1) + TRAP_ENTRY_INTERRUPT(2) + TRAP_ENTRY_INTERRUPT(3) + TRAP_ENTRY_INTERRUPT(4) + TRAP_ENTRY_INTERRUPT(5) + TRAP_ENTRY_INTERRUPT(6) + TRAP_ENTRY_INTERRUPT(7) + TRAP_ENTRY_INTERRUPT(8) + TRAP_ENTRY_INTERRUPT(9) + TRAP_ENTRY_INTERRUPT(10) + TRAP_ENTRY_INTERRUPT(11) + TRAP_ENTRY_INTERRUPT(12) + TRAP_ENTRY_INTERRUPT(13) + TRAP_ENTRY_INTERRUPT(14) + TRAP_ENTRY(0x1f, linux_trap_ipi15_sun4m) + TRAP_ENTRY(0x20, do_reg_access) + BAD_TRAP(0x21) + BAD_TRAP(0x22) + BAD_TRAP(0x23) + TRAP_ENTRY(0x24, do_cp_disabled) + SKIP_TRAP(0x25, unimp_flush) + BAD_TRAP(0x26) + BAD_TRAP(0x27) + TRAP_ENTRY(0x28, do_cp_exception) + SRMMU_DFAULT + TRAP_ENTRY(0x2a, do_hw_divzero) + BAD_TRAP(0x2b) BAD_TRAP(0x2c) + BAD_TRAP(0x2d) BAD_TRAP(0x2e) BAD_TRAP(0x2f) BAD_TRAP(0x30) BAD_TRAP(0x31) + BAD_TRAP(0x32) BAD_TRAP(0x33) BAD_TRAP(0x34) BAD_TRAP(0x35) BAD_TRAP(0x36) + BAD_TRAP(0x37) BAD_TRAP(0x38) BAD_TRAP(0x39) BAD_TRAP(0x3a) BAD_TRAP(0x3b) + BAD_TRAP(0x3c) BAD_TRAP(0x3d) BAD_TRAP(0x3e) BAD_TRAP(0x3f) BAD_TRAP(0x40) + BAD_TRAP(0x41) BAD_TRAP(0x42) BAD_TRAP(0x43) BAD_TRAP(0x44) BAD_TRAP(0x45) + BAD_TRAP(0x46) BAD_TRAP(0x47) BAD_TRAP(0x48) BAD_TRAP(0x49) BAD_TRAP(0x4a) + BAD_TRAP(0x4b) BAD_TRAP(0x4c) BAD_TRAP(0x4d) BAD_TRAP(0x4e) BAD_TRAP(0x4f) + BAD_TRAP(0x50) + BAD_TRAP(0x51) BAD_TRAP(0x52) BAD_TRAP(0x53) BAD_TRAP(0x54) BAD_TRAP(0x55) + BAD_TRAP(0x56) BAD_TRAP(0x57) BAD_TRAP(0x58) BAD_TRAP(0x59) BAD_TRAP(0x5a) + BAD_TRAP(0x5b) BAD_TRAP(0x5c) BAD_TRAP(0x5d) BAD_TRAP(0x5e) BAD_TRAP(0x5f) + BAD_TRAP(0x60) BAD_TRAP(0x61) BAD_TRAP(0x62) BAD_TRAP(0x63) BAD_TRAP(0x64) + BAD_TRAP(0x65) BAD_TRAP(0x66) BAD_TRAP(0x67) BAD_TRAP(0x68) BAD_TRAP(0x69) + BAD_TRAP(0x6a) BAD_TRAP(0x6b) BAD_TRAP(0x6c) BAD_TRAP(0x6d) BAD_TRAP(0x6e) + BAD_TRAP(0x6f) BAD_TRAP(0x70) BAD_TRAP(0x71) BAD_TRAP(0x72) BAD_TRAP(0x73) + BAD_TRAP(0x74) BAD_TRAP(0x75) BAD_TRAP(0x76) BAD_TRAP(0x77) BAD_TRAP(0x78) + BAD_TRAP(0x79) BAD_TRAP(0x7a) BAD_TRAP(0x7b) BAD_TRAP(0x7c) BAD_TRAP(0x7d) + BAD_TRAP(0x7e) BAD_TRAP(0x7f) + BAD_TRAP(0x80) + BREAKPOINT_TRAP + TRAP_ENTRY(0x82, do_hw_divzero) + TRAP_ENTRY(0x83, do_flush_windows) + BAD_TRAP(0x84) BAD_TRAP(0x85) + BAD_TRAP(0x86) BAD_TRAP(0x87) BAD_TRAP(0x88) + BAD_TRAP(0x89) BAD_TRAP(0x8a) BAD_TRAP(0x8b) BAD_TRAP(0x8c) + BAD_TRAP(0x8d) BAD_TRAP(0x8e) BAD_TRAP(0x8f) + LINUX_SYSCALL_TRAP + BAD_TRAP(0x91) BAD_TRAP(0x92) BAD_TRAP(0x93) BAD_TRAP(0x94) + BAD_TRAP(0x95) BAD_TRAP(0x96) BAD_TRAP(0x97) BAD_TRAP(0x98) BAD_TRAP(0x99) + BAD_TRAP(0x9a) BAD_TRAP(0x9b) BAD_TRAP(0x9c) BAD_TRAP(0x9d) BAD_TRAP(0x9e) + BAD_TRAP(0x9f) + GETCC_TRAP + SETCC_TRAP + GETPSR_TRAP + BAD_TRAP(0xa3) BAD_TRAP(0xa4) BAD_TRAP(0xa5) BAD_TRAP(0xa6) + BAD_TRAP(0xa7) BAD_TRAP(0xa8) BAD_TRAP(0xa9) BAD_TRAP(0xaa) BAD_TRAP(0xab) + BAD_TRAP(0xac) BAD_TRAP(0xad) BAD_TRAP(0xae) BAD_TRAP(0xaf) BAD_TRAP(0xb0) + BAD_TRAP(0xb1) BAD_TRAP(0xb2) BAD_TRAP(0xb3) BAD_TRAP(0xb4) BAD_TRAP(0xb5) + BAD_TRAP(0xb6) BAD_TRAP(0xb7) BAD_TRAP(0xb8) BAD_TRAP(0xb9) BAD_TRAP(0xba) + BAD_TRAP(0xbb) BAD_TRAP(0xbc) BAD_TRAP(0xbd) BAD_TRAP(0xbe) BAD_TRAP(0xbf) + BAD_TRAP(0xc0) BAD_TRAP(0xc1) BAD_TRAP(0xc2) BAD_TRAP(0xc3) BAD_TRAP(0xc4) + BAD_TRAP(0xc5) BAD_TRAP(0xc6) BAD_TRAP(0xc7) BAD_TRAP(0xc8) BAD_TRAP(0xc9) + BAD_TRAP(0xca) BAD_TRAP(0xcb) BAD_TRAP(0xcc) BAD_TRAP(0xcd) BAD_TRAP(0xce) + BAD_TRAP(0xcf) BAD_TRAP(0xd0) BAD_TRAP(0xd1) BAD_TRAP(0xd2) BAD_TRAP(0xd3) + BAD_TRAP(0xd4) BAD_TRAP(0xd5) BAD_TRAP(0xd6) BAD_TRAP(0xd7) BAD_TRAP(0xd8) + BAD_TRAP(0xd9) BAD_TRAP(0xda) BAD_TRAP(0xdb) BAD_TRAP(0xdc) BAD_TRAP(0xdd) + BAD_TRAP(0xde) BAD_TRAP(0xdf) BAD_TRAP(0xe0) BAD_TRAP(0xe1) BAD_TRAP(0xe2) + BAD_TRAP(0xe3) BAD_TRAP(0xe4) BAD_TRAP(0xe5) BAD_TRAP(0xe6) BAD_TRAP(0xe7) + BAD_TRAP(0xe8) BAD_TRAP(0xe9) BAD_TRAP(0xea) BAD_TRAP(0xeb) BAD_TRAP(0xec) + BAD_TRAP(0xed) BAD_TRAP(0xee) BAD_TRAP(0xef) BAD_TRAP(0xf0) BAD_TRAP(0xf1) + BAD_TRAP(0xf2) BAD_TRAP(0xf3) BAD_TRAP(0xf4) BAD_TRAP(0xf5) BAD_TRAP(0xf6) + BAD_TRAP(0xf7) BAD_TRAP(0xf8) BAD_TRAP(0xf9) BAD_TRAP(0xfa) BAD_TRAP(0xfb) + BAD_TRAP(0xfc) + KGDB_TRAP(0xfd) + BAD_TRAP(0xfe) + BAD_TRAP(0xff) + +#endif diff --git a/arch/sparc/kernel/ttable.S b/arch/sparc/kernel/ttable_64.S index c6dfdaa29e20..c6dfdaa29e20 100644 --- a/arch/sparc/kernel/ttable.S +++ b/arch/sparc/kernel/ttable_64.S diff --git a/arch/sparc/kernel/unaligned_64.c b/arch/sparc/kernel/unaligned_64.c index dae85bc2eda5..f81d038f7340 100644 --- a/arch/sparc/kernel/unaligned_64.c +++ b/arch/sparc/kernel/unaligned_64.c @@ -21,7 +21,6 @@ #include <linux/bitops.h> #include <linux/perf_event.h> #include <linux/ratelimit.h> -#include <linux/bitops.h> #include <asm/fpumacro.h> #include <asm/cacheflush.h> diff --git a/arch/sparc/kernel/wof.S b/arch/sparc/kernel/wof.S index 3bbcd8dc9abf..4c2de3cf309b 100644 --- a/arch/sparc/kernel/wof.S +++ b/arch/sparc/kernel/wof.S @@ -163,9 +163,8 @@ spwin_fromuser: * the label 'spwin_user_stack_is_bolixed' which will take * care of things at that point. */ - .globl spwin_mmu_patchme -spwin_mmu_patchme: b spwin_sun4c_stackchk - andcc %sp, 0x7, %g0 + b spwin_srmmu_stackchk + andcc %sp, 0x7, %g0 spwin_good_ustack: /* LOCATION: Window to be saved */ @@ -306,73 +305,6 @@ spwin_bad_ustack_from_kernel: * As noted above %curptr cannot be touched by this routine at all. */ -spwin_sun4c_stackchk: - /* LOCATION: Window to be saved on the stack */ - - /* See if the stack is in the address space hole but first, - * check results of callers andcc %sp, 0x7, %g0 - */ - be 1f - sra %sp, 29, %glob_tmp - - rd %psr, %glob_tmp - b spwin_user_stack_is_bolixed + 0x4 - nop - -1: - add %glob_tmp, 0x1, %glob_tmp - andncc %glob_tmp, 0x1, %g0 - be 1f - and %sp, 0xfff, %glob_tmp ! delay slot - - rd %psr, %glob_tmp - b spwin_user_stack_is_bolixed + 0x4 - nop - - /* See if our dump area will be on more than one - * page. - */ -1: - add %glob_tmp, 0x38, %glob_tmp - andncc %glob_tmp, 0xff8, %g0 - be spwin_sun4c_onepage ! only one page to check - lda [%sp] ASI_PTE, %glob_tmp ! have to check first page anyways - -spwin_sun4c_twopages: - /* Is first page ok permission wise? */ - srl %glob_tmp, 29, %glob_tmp - cmp %glob_tmp, 0x6 - be 1f - add %sp, 0x38, %glob_tmp /* Is second page in vma hole? */ - - rd %psr, %glob_tmp - b spwin_user_stack_is_bolixed + 0x4 - nop - -1: - sra %glob_tmp, 29, %glob_tmp - add %glob_tmp, 0x1, %glob_tmp - andncc %glob_tmp, 0x1, %g0 - be 1f - add %sp, 0x38, %glob_tmp - - rd %psr, %glob_tmp - b spwin_user_stack_is_bolixed + 0x4 - nop - -1: - lda [%glob_tmp] ASI_PTE, %glob_tmp - -spwin_sun4c_onepage: - srl %glob_tmp, 29, %glob_tmp - cmp %glob_tmp, 0x6 ! can user write to it? - be spwin_good_ustack ! success - nop - - rd %psr, %glob_tmp - b spwin_user_stack_is_bolixed + 0x4 - nop - /* This is a generic SRMMU routine. As far as I know this * works for all current v8/srmmu implementations, we'll * see... diff --git a/arch/sparc/kernel/wuf.S b/arch/sparc/kernel/wuf.S index 779ff750603d..9fde91a249e0 100644 --- a/arch/sparc/kernel/wuf.S +++ b/arch/sparc/kernel/wuf.S @@ -131,12 +131,9 @@ fwin_from_user: /* LOCATION: Window 'W' */ - /* Branch to the architecture specific stack validation - * routine. They can be found below... - */ - .globl fwin_mmu_patchme -fwin_mmu_patchme: b sun4c_fwin_stackchk - andcc %sp, 0x7, %g0 + /* Branch to the stack validation routine */ + b srmmu_fwin_stackchk + andcc %sp, 0x7, %g0 #define STACK_OFFSET (THREAD_SIZE - TRACEREG_SZ - STACKFRAME_SZ) @@ -242,57 +239,6 @@ fwin_user_finish_up: * 'someone elses' window possibly. */ - .align 4 -sun4c_fwin_stackchk: - /* LOCATION: Window 'W' */ - - /* Caller did 'andcc %sp, 0x7, %g0' */ - be 1f - and %sp, 0xfff, %l0 ! delay slot - - b,a fwin_user_stack_is_bolixed - - /* See if we have to check the sanity of one page or two */ -1: - add %l0, 0x38, %l0 - sra %sp, 29, %l5 - add %l5, 0x1, %l5 - andncc %l5, 0x1, %g0 - be 1f - andncc %l0, 0xff8, %g0 - - b,a fwin_user_stack_is_bolixed /* %sp is in vma hole, yuck */ - -1: - be sun4c_fwin_onepage /* Only one page to check */ - lda [%sp] ASI_PTE, %l1 -sun4c_fwin_twopages: - add %sp, 0x38, %l0 - sra %l0, 29, %l5 - add %l5, 0x1, %l5 - andncc %l5, 0x1, %g0 - be 1f - lda [%l0] ASI_PTE, %l1 - - b,a fwin_user_stack_is_bolixed /* Second page in vma hole */ - -1: - srl %l1, 29, %l1 - andcc %l1, 0x4, %g0 - bne sun4c_fwin_onepage - lda [%sp] ASI_PTE, %l1 - - b,a fwin_user_stack_is_bolixed /* Second page has bad perms */ - -sun4c_fwin_onepage: - srl %l1, 29, %l1 - andcc %l1, 0x4, %g0 - bne fwin_user_stack_is_ok - nop - - /* A page had bad page permissions, losing... */ - b,a fwin_user_stack_is_bolixed - .globl srmmu_fwin_stackchk srmmu_fwin_stackchk: /* LOCATION: Window 'W' */ diff --git a/arch/sparc/lib/Makefile b/arch/sparc/lib/Makefile index a3fc4375a150..389628f50a15 100644 --- a/arch/sparc/lib/Makefile +++ b/arch/sparc/lib/Makefile @@ -4,7 +4,7 @@ asflags-y := -ansi -DST_DIV0=0x02 ccflags-y := -Werror -lib-$(CONFIG_SPARC32) += mul.o rem.o sdiv.o udiv.o umul.o urem.o ashrdi3.o +lib-$(CONFIG_SPARC32) += ashrdi3.o lib-$(CONFIG_SPARC32) += memcpy.o memset.o lib-y += strlen.o lib-y += checksum_$(BITS).o @@ -13,7 +13,7 @@ lib-y += memscan_$(BITS).o memcmp.o strncmp_$(BITS).o lib-y += strncpy_from_user_$(BITS).o strlen_user_$(BITS).o lib-$(CONFIG_SPARC32) += divdi3.o udivdi3.o lib-$(CONFIG_SPARC32) += copy_user.o locks.o -lib-y += atomic_$(BITS).o +lib-$(CONFIG_SPARC64) += atomic_64.o lib-$(CONFIG_SPARC32) += lshrdi3.o ashldi3.o lib-$(CONFIG_SPARC32) += muldi3.o bitext.o cmpdi2.o @@ -40,7 +40,7 @@ lib-$(CONFIG_SPARC64) += copy_in_user.o user_fixup.o memmove.o lib-$(CONFIG_SPARC64) += mcount.o ipcsum.o xor.o hweight.o ffs.o obj-y += iomap.o -obj-$(CONFIG_SPARC32) += atomic32.o +obj-$(CONFIG_SPARC32) += atomic32.o ucmpdi2.o obj-y += ksyms.o obj-$(CONFIG_SPARC64) += PeeCeeI.o obj-y += usercopy.o diff --git a/arch/sparc/lib/ashldi3.S b/arch/sparc/lib/ashldi3.S index 17912e608716..86f60de07b0a 100644 --- a/arch/sparc/lib/ashldi3.S +++ b/arch/sparc/lib/ashldi3.S @@ -5,10 +5,10 @@ * Copyright (C) 1999 David S. Miller ([email protected]) */ +#include <linux/linkage.h> + .text - .align 4 - .globl __ashldi3 -__ashldi3: +ENTRY(__ashldi3) cmp %o2, 0 be 9f mov 0x20, %g2 @@ -32,3 +32,4 @@ __ashldi3: 9: retl nop +ENDPROC(__ashldi3) diff --git a/arch/sparc/lib/ashrdi3.S b/arch/sparc/lib/ashrdi3.S index 85398fd6dcc9..6eb8ba2dd50e 100644 --- a/arch/sparc/lib/ashrdi3.S +++ b/arch/sparc/lib/ashrdi3.S @@ -5,10 +5,10 @@ * Copyright (C) 1995 David S. Miller ([email protected]) */ +#include <linux/linkage.h> + .text - .align 4 - .globl __ashrdi3 -__ashrdi3: +ENTRY(__ashrdi3) tst %o2 be 3f or %g0, 32, %g2 @@ -34,3 +34,4 @@ __ashrdi3: 3: jmpl %o7 + 8, %g0 nop +ENDPROC(__ashrdi3) diff --git a/arch/sparc/lib/atomic_32.S b/arch/sparc/lib/atomic_32.S deleted file mode 100644 index eb6c7359cbd1..000000000000 --- a/arch/sparc/lib/atomic_32.S +++ /dev/null @@ -1,44 +0,0 @@ -/* atomic.S: Move this stuff here for better ICACHE hit rates. - * - * Copyright (C) 1996 David S. Miller ([email protected]) - */ - -#include <asm/ptrace.h> -#include <asm/psr.h> - - .text - .align 4 - - .globl __atomic_begin -__atomic_begin: - -#ifndef CONFIG_SMP - .globl ___xchg32_sun4c -___xchg32_sun4c: - rd %psr, %g3 - andcc %g3, PSR_PIL, %g0 - bne 1f - nop - wr %g3, PSR_PIL, %psr - nop; nop; nop -1: - andcc %g3, PSR_PIL, %g0 - ld [%g1], %g7 - bne 1f - st %g2, [%g1] - wr %g3, 0x0, %psr - nop; nop; nop -1: - mov %g7, %g2 - jmpl %o7 + 8, %g0 - mov %g4, %o7 - - .globl ___xchg32_sun4md -___xchg32_sun4md: - swap [%g1], %g2 - jmpl %o7 + 8, %g0 - mov %g4, %o7 -#endif - - .globl __atomic_end -__atomic_end: diff --git a/arch/sparc/lib/atomic_64.S b/arch/sparc/lib/atomic_64.S index 59186e0fcf39..4d502da3de78 100644 --- a/arch/sparc/lib/atomic_64.S +++ b/arch/sparc/lib/atomic_64.S @@ -3,6 +3,7 @@ * Copyright (C) 1999, 2007 David S. Miller ([email protected]) */ +#include <linux/linkage.h> #include <asm/asi.h> #include <asm/backoff.h> @@ -13,9 +14,7 @@ * memory barriers, and a second which returns * a value and does the barriers. */ - .globl atomic_add - .type atomic_add,#function -atomic_add: /* %o0 = increment, %o1 = atomic_ptr */ +ENTRY(atomic_add) /* %o0 = increment, %o1 = atomic_ptr */ BACKOFF_SETUP(%o2) 1: lduw [%o1], %g1 add %g1, %o0, %g7 @@ -26,11 +25,9 @@ atomic_add: /* %o0 = increment, %o1 = atomic_ptr */ retl nop 2: BACKOFF_SPIN(%o2, %o3, 1b) - .size atomic_add, .-atomic_add +ENDPROC(atomic_add) - .globl atomic_sub - .type atomic_sub,#function -atomic_sub: /* %o0 = decrement, %o1 = atomic_ptr */ +ENTRY(atomic_sub) /* %o0 = decrement, %o1 = atomic_ptr */ BACKOFF_SETUP(%o2) 1: lduw [%o1], %g1 sub %g1, %o0, %g7 @@ -41,11 +38,9 @@ atomic_sub: /* %o0 = decrement, %o1 = atomic_ptr */ retl nop 2: BACKOFF_SPIN(%o2, %o3, 1b) - .size atomic_sub, .-atomic_sub +ENDPROC(atomic_sub) - .globl atomic_add_ret - .type atomic_add_ret,#function -atomic_add_ret: /* %o0 = increment, %o1 = atomic_ptr */ +ENTRY(atomic_add_ret) /* %o0 = increment, %o1 = atomic_ptr */ BACKOFF_SETUP(%o2) 1: lduw [%o1], %g1 add %g1, %o0, %g7 @@ -56,11 +51,9 @@ atomic_add_ret: /* %o0 = increment, %o1 = atomic_ptr */ retl sra %g1, 0, %o0 2: BACKOFF_SPIN(%o2, %o3, 1b) - .size atomic_add_ret, .-atomic_add_ret +ENDPROC(atomic_add_ret) - .globl atomic_sub_ret - .type atomic_sub_ret,#function -atomic_sub_ret: /* %o0 = decrement, %o1 = atomic_ptr */ +ENTRY(atomic_sub_ret) /* %o0 = decrement, %o1 = atomic_ptr */ BACKOFF_SETUP(%o2) 1: lduw [%o1], %g1 sub %g1, %o0, %g7 @@ -71,11 +64,9 @@ atomic_sub_ret: /* %o0 = decrement, %o1 = atomic_ptr */ retl sra %g1, 0, %o0 2: BACKOFF_SPIN(%o2, %o3, 1b) - .size atomic_sub_ret, .-atomic_sub_ret +ENDPROC(atomic_sub_ret) - .globl atomic64_add - .type atomic64_add,#function -atomic64_add: /* %o0 = increment, %o1 = atomic_ptr */ +ENTRY(atomic64_add) /* %o0 = increment, %o1 = atomic_ptr */ BACKOFF_SETUP(%o2) 1: ldx [%o1], %g1 add %g1, %o0, %g7 @@ -86,11 +77,9 @@ atomic64_add: /* %o0 = increment, %o1 = atomic_ptr */ retl nop 2: BACKOFF_SPIN(%o2, %o3, 1b) - .size atomic64_add, .-atomic64_add +ENDPROC(atomic64_add) - .globl atomic64_sub - .type atomic64_sub,#function -atomic64_sub: /* %o0 = decrement, %o1 = atomic_ptr */ +ENTRY(atomic64_sub) /* %o0 = decrement, %o1 = atomic_ptr */ BACKOFF_SETUP(%o2) 1: ldx [%o1], %g1 sub %g1, %o0, %g7 @@ -101,11 +90,9 @@ atomic64_sub: /* %o0 = decrement, %o1 = atomic_ptr */ retl nop 2: BACKOFF_SPIN(%o2, %o3, 1b) - .size atomic64_sub, .-atomic64_sub +ENDPROC(atomic64_sub) - .globl atomic64_add_ret - .type atomic64_add_ret,#function -atomic64_add_ret: /* %o0 = increment, %o1 = atomic_ptr */ +ENTRY(atomic64_add_ret) /* %o0 = increment, %o1 = atomic_ptr */ BACKOFF_SETUP(%o2) 1: ldx [%o1], %g1 add %g1, %o0, %g7 @@ -116,11 +103,9 @@ atomic64_add_ret: /* %o0 = increment, %o1 = atomic_ptr */ retl add %g1, %o0, %o0 2: BACKOFF_SPIN(%o2, %o3, 1b) - .size atomic64_add_ret, .-atomic64_add_ret +ENDPROC(atomic64_add_ret) - .globl atomic64_sub_ret - .type atomic64_sub_ret,#function -atomic64_sub_ret: /* %o0 = decrement, %o1 = atomic_ptr */ +ENTRY(atomic64_sub_ret) /* %o0 = decrement, %o1 = atomic_ptr */ BACKOFF_SETUP(%o2) 1: ldx [%o1], %g1 sub %g1, %o0, %g7 @@ -131,4 +116,4 @@ atomic64_sub_ret: /* %o0 = decrement, %o1 = atomic_ptr */ retl sub %g1, %o0, %o0 2: BACKOFF_SPIN(%o2, %o3, 1b) - .size atomic64_sub_ret, .-atomic64_sub_ret +ENDPROC(atomic64_sub_ret) diff --git a/arch/sparc/lib/bitops.S b/arch/sparc/lib/bitops.S index 3dc61d5537c0..36f72cc0e67e 100644 --- a/arch/sparc/lib/bitops.S +++ b/arch/sparc/lib/bitops.S @@ -3,14 +3,13 @@ * Copyright (C) 2000, 2007 David S. Miller ([email protected]) */ +#include <linux/linkage.h> #include <asm/asi.h> #include <asm/backoff.h> .text - .globl test_and_set_bit - .type test_and_set_bit,#function -test_and_set_bit: /* %o0=nr, %o1=addr */ +ENTRY(test_and_set_bit) /* %o0=nr, %o1=addr */ BACKOFF_SETUP(%o3) srlx %o0, 6, %g1 mov 1, %o2 @@ -29,11 +28,9 @@ test_and_set_bit: /* %o0=nr, %o1=addr */ retl nop 2: BACKOFF_SPIN(%o3, %o4, 1b) - .size test_and_set_bit, .-test_and_set_bit +ENDPROC(test_and_set_bit) - .globl test_and_clear_bit - .type test_and_clear_bit,#function -test_and_clear_bit: /* %o0=nr, %o1=addr */ +ENTRY(test_and_clear_bit) /* %o0=nr, %o1=addr */ BACKOFF_SETUP(%o3) srlx %o0, 6, %g1 mov 1, %o2 @@ -52,11 +49,9 @@ test_and_clear_bit: /* %o0=nr, %o1=addr */ retl nop 2: BACKOFF_SPIN(%o3, %o4, 1b) - .size test_and_clear_bit, .-test_and_clear_bit +ENDPROC(test_and_clear_bit) - .globl test_and_change_bit - .type test_and_change_bit,#function -test_and_change_bit: /* %o0=nr, %o1=addr */ +ENTRY(test_and_change_bit) /* %o0=nr, %o1=addr */ BACKOFF_SETUP(%o3) srlx %o0, 6, %g1 mov 1, %o2 @@ -75,11 +70,9 @@ test_and_change_bit: /* %o0=nr, %o1=addr */ retl nop 2: BACKOFF_SPIN(%o3, %o4, 1b) - .size test_and_change_bit, .-test_and_change_bit +ENDPROC(test_and_change_bit) - .globl set_bit - .type set_bit,#function -set_bit: /* %o0=nr, %o1=addr */ +ENTRY(set_bit) /* %o0=nr, %o1=addr */ BACKOFF_SETUP(%o3) srlx %o0, 6, %g1 mov 1, %o2 @@ -96,11 +89,9 @@ set_bit: /* %o0=nr, %o1=addr */ retl nop 2: BACKOFF_SPIN(%o3, %o4, 1b) - .size set_bit, .-set_bit +ENDPROC(set_bit) - .globl clear_bit - .type clear_bit,#function -clear_bit: /* %o0=nr, %o1=addr */ +ENTRY(clear_bit) /* %o0=nr, %o1=addr */ BACKOFF_SETUP(%o3) srlx %o0, 6, %g1 mov 1, %o2 @@ -117,11 +108,9 @@ clear_bit: /* %o0=nr, %o1=addr */ retl nop 2: BACKOFF_SPIN(%o3, %o4, 1b) - .size clear_bit, .-clear_bit +ENDPROC(clear_bit) - .globl change_bit - .type change_bit,#function -change_bit: /* %o0=nr, %o1=addr */ +ENTRY(change_bit) /* %o0=nr, %o1=addr */ BACKOFF_SETUP(%o3) srlx %o0, 6, %g1 mov 1, %o2 @@ -138,4 +127,4 @@ change_bit: /* %o0=nr, %o1=addr */ retl nop 2: BACKOFF_SPIN(%o3, %o4, 1b) - .size change_bit, .-change_bit +ENDPROC(change_bit) diff --git a/arch/sparc/lib/blockops.S b/arch/sparc/lib/blockops.S index 804be87f9a42..3c771011ff4b 100644 --- a/arch/sparc/lib/blockops.S +++ b/arch/sparc/lib/blockops.S @@ -4,6 +4,7 @@ * Copyright (C) 1996 David S. Miller ([email protected]) */ +#include <linux/linkage.h> #include <asm/page.h> /* Zero out 64 bytes of memory at (buf + offset). @@ -44,10 +45,7 @@ */ .text - .align 4 - .globl bzero_1page, __copy_1page - -bzero_1page: +ENTRY(bzero_1page) /* NOTE: If you change the number of insns of this routine, please check * arch/sparc/mm/hypersparc.S */ /* %o0 = buf */ @@ -65,8 +63,9 @@ bzero_1page: retl nop +ENDPROC(bzero_1page) -__copy_1page: +ENTRY(__copy_1page) /* NOTE: If you change the number of insns of this routine, please check * arch/sparc/mm/hypersparc.S */ /* %o0 = dst, %o1 = src */ @@ -87,3 +86,4 @@ __copy_1page: retl nop +ENDPROC(__copy_1page) diff --git a/arch/sparc/lib/bzero.S b/arch/sparc/lib/bzero.S index 615f401edf69..8c058114b649 100644 --- a/arch/sparc/lib/bzero.S +++ b/arch/sparc/lib/bzero.S @@ -4,11 +4,11 @@ * Copyright (C) 2005 David S. Miller <[email protected]> */ +#include <linux/linkage.h> + .text - .globl memset - .type memset, #function -memset: /* %o0=buf, %o1=pat, %o2=len */ +ENTRY(memset) /* %o0=buf, %o1=pat, %o2=len */ and %o1, 0xff, %o3 mov %o2, %o1 sllx %o3, 8, %g1 @@ -19,9 +19,7 @@ memset: /* %o0=buf, %o1=pat, %o2=len */ ba,pt %xcc, 1f or %g1, %o2, %o2 - .globl __bzero - .type __bzero, #function -__bzero: /* %o0=buf, %o1=len */ +ENTRY(__bzero) /* %o0=buf, %o1=len */ clr %o2 1: mov %o0, %o3 brz,pn %o1, __bzero_done @@ -78,8 +76,8 @@ __bzero_tiny: __bzero_done: retl mov %o3, %o0 - .size __bzero, .-__bzero - .size memset, .-memset +ENDPROC(__bzero) +ENDPROC(memset) #define EX_ST(x,y) \ 98: x,y; \ @@ -89,9 +87,7 @@ __bzero_done: .text; \ .align 4; - .globl __clear_user - .type __clear_user, #function -__clear_user: /* %o0=buf, %o1=len */ +ENTRY(__clear_user) /* %o0=buf, %o1=len */ brz,pn %o1, __clear_user_done cmp %o1, 16 bl,pn %icc, __clear_user_tiny @@ -146,4 +142,4 @@ __clear_user_tiny: __clear_user_done: retl clr %o0 - .size __clear_user, .-__clear_user +ENDPROC(__clear_user) diff --git a/arch/sparc/lib/divdi3.S b/arch/sparc/lib/divdi3.S index d74bc0925f2d..9614b48b6ef8 100644 --- a/arch/sparc/lib/divdi3.S +++ b/arch/sparc/lib/divdi3.S @@ -19,7 +19,6 @@ Boston, MA 02111-1307, USA. */ .text .align 4 - .global .udiv .globl __divdi3 __divdi3: save %sp,-104,%sp @@ -83,8 +82,9 @@ __divdi3: bne .LL85 mov %i0,%o2 mov 1,%o0 - call .udiv,0 mov 0,%o1 + wr %g0, 0, %y + udiv %o0, %o1, %o0 mov %o0,%o4 mov %i0,%o2 .LL85: diff --git a/arch/sparc/lib/ipcsum.S b/arch/sparc/lib/ipcsum.S index 58ca5b9a8778..4742d59029ee 100644 --- a/arch/sparc/lib/ipcsum.S +++ b/arch/sparc/lib/ipcsum.S @@ -1,8 +1,7 @@ +#include <linux/linkage.h> + .text - .align 32 - .globl ip_fast_csum - .type ip_fast_csum,#function -ip_fast_csum: /* %o0 = iph, %o1 = ihl */ +ENTRY(ip_fast_csum) /* %o0 = iph, %o1 = ihl */ sub %o1, 4, %g7 lduw [%o0 + 0x00], %o2 lduw [%o0 + 0x04], %g2 @@ -31,4 +30,4 @@ ip_fast_csum: /* %o0 = iph, %o1 = ihl */ set 0xffff, %o1 retl and %o2, %o1, %o0 - .size ip_fast_csum, .-ip_fast_csum +ENDPROC(ip_fast_csum) diff --git a/arch/sparc/lib/ksyms.c b/arch/sparc/lib/ksyms.c index f73c2240fe60..2dc30875c8bc 100644 --- a/arch/sparc/lib/ksyms.c +++ b/arch/sparc/lib/ksyms.c @@ -56,23 +56,11 @@ extern int __divdi3(int, int); extern void (*__copy_1page)(void *, const void *); extern void (*bzero_1page)(void *); -extern int __strncmp(const char *, const char *, __kernel_size_t); - extern void ___rw_read_enter(void); extern void ___rw_read_try(void); extern void ___rw_read_exit(void); extern void ___rw_write_enter(void); -/* Alias functions whose names begin with "." and export the aliases. - * The module references will be fixed up by module_frob_arch_sections. - */ -extern int _Div(int, int); -extern int _Mul(int, int); -extern int _Rem(int, int); -extern unsigned _Udiv(unsigned, unsigned); -extern unsigned _Umul(unsigned, unsigned); -extern unsigned _Urem(unsigned, unsigned); - /* Networking helper routines. */ EXPORT_SYMBOL(__csum_partial_copy_sparc_generic); @@ -81,9 +69,6 @@ EXPORT_SYMBOL(__copy_1page); EXPORT_SYMBOL(__memmove); EXPORT_SYMBOL(bzero_1page); -/* string functions */ -EXPORT_SYMBOL(__strncmp); - /* Moving data to/from/in userspace. */ EXPORT_SYMBOL(__copy_user); @@ -100,13 +85,6 @@ EXPORT_SYMBOL(__ashldi3); EXPORT_SYMBOL(__lshrdi3); EXPORT_SYMBOL(__muldi3); EXPORT_SYMBOL(__divdi3); - -EXPORT_SYMBOL(_Rem); -EXPORT_SYMBOL(_Urem); -EXPORT_SYMBOL(_Mul); -EXPORT_SYMBOL(_Umul); -EXPORT_SYMBOL(_Div); -EXPORT_SYMBOL(_Udiv); #endif /* diff --git a/arch/sparc/lib/lshrdi3.S b/arch/sparc/lib/lshrdi3.S index 47a1354c1602..60ebc7cdbee0 100644 --- a/arch/sparc/lib/lshrdi3.S +++ b/arch/sparc/lib/lshrdi3.S @@ -1,6 +1,6 @@ +#include <linux/linkage.h> - .globl __lshrdi3 -__lshrdi3: +ENTRY(__lshrdi3) cmp %o2, 0 be 3f mov 0x20, %g2 @@ -24,3 +24,4 @@ __lshrdi3: 3: retl nop +ENDPROC(__lshrdi3) diff --git a/arch/sparc/lib/memmove.S b/arch/sparc/lib/memmove.S index 97395802c23c..b7f6334e159f 100644 --- a/arch/sparc/lib/memmove.S +++ b/arch/sparc/lib/memmove.S @@ -4,11 +4,10 @@ * Copyright (C) 1996, 1997, 1998, 1999 Jakub Jelinek ([email protected]) */ +#include <linux/linkage.h> + .text - .align 32 - .globl memmove - .type memmove,#function -memmove: /* o0=dst o1=src o2=len */ +ENTRY(memmove) /* o0=dst o1=src o2=len */ mov %o0, %g1 cmp %o0, %o1 bleu,pt %xcc, memcpy @@ -28,4 +27,4 @@ memmove: /* o0=dst o1=src o2=len */ retl mov %g1, %o0 - .size memmove, .-memmove +ENDPROC(memmove) diff --git a/arch/sparc/lib/mul.S b/arch/sparc/lib/mul.S deleted file mode 100644 index c45470d0b0ce..000000000000 --- a/arch/sparc/lib/mul.S +++ /dev/null @@ -1,137 +0,0 @@ -/* - * mul.S: This routine was taken from glibc-1.09 and is covered - * by the GNU Library General Public License Version 2. - */ - -/* - * Signed multiply, from Appendix E of the Sparc Version 8 - * Architecture Manual. - */ - -/* - * Returns %o0 * %o1 in %o1%o0 (i.e., %o1 holds the upper 32 bits of - * the 64-bit product). - * - * This code optimizes short (less than 13-bit) multiplies. - */ - - .globl .mul - .globl _Mul -.mul: -_Mul: /* needed for export */ - mov %o0, %y ! multiplier -> Y - andncc %o0, 0xfff, %g0 ! test bits 12..31 - be Lmul_shortway ! if zero, can do it the short way - andcc %g0, %g0, %o4 ! zero the partial product and clear N and V - - /* - * Long multiply. 32 steps, followed by a final shift step. - */ - mulscc %o4, %o1, %o4 ! 1 - mulscc %o4, %o1, %o4 ! 2 - mulscc %o4, %o1, %o4 ! 3 - mulscc %o4, %o1, %o4 ! 4 - mulscc %o4, %o1, %o4 ! 5 - mulscc %o4, %o1, %o4 ! 6 - mulscc %o4, %o1, %o4 ! 7 - mulscc %o4, %o1, %o4 ! 8 - mulscc %o4, %o1, %o4 ! 9 - mulscc %o4, %o1, %o4 ! 10 - mulscc %o4, %o1, %o4 ! 11 - mulscc %o4, %o1, %o4 ! 12 - mulscc %o4, %o1, %o4 ! 13 - mulscc %o4, %o1, %o4 ! 14 - mulscc %o4, %o1, %o4 ! 15 - mulscc %o4, %o1, %o4 ! 16 - mulscc %o4, %o1, %o4 ! 17 - mulscc %o4, %o1, %o4 ! 18 - mulscc %o4, %o1, %o4 ! 19 - mulscc %o4, %o1, %o4 ! 20 - mulscc %o4, %o1, %o4 ! 21 - mulscc %o4, %o1, %o4 ! 22 - mulscc %o4, %o1, %o4 ! 23 - mulscc %o4, %o1, %o4 ! 24 - mulscc %o4, %o1, %o4 ! 25 - mulscc %o4, %o1, %o4 ! 26 - mulscc %o4, %o1, %o4 ! 27 - mulscc %o4, %o1, %o4 ! 28 - mulscc %o4, %o1, %o4 ! 29 - mulscc %o4, %o1, %o4 ! 30 - mulscc %o4, %o1, %o4 ! 31 - mulscc %o4, %o1, %o4 ! 32 - mulscc %o4, %g0, %o4 ! final shift - - ! If %o0 was negative, the result is - ! (%o0 * %o1) + (%o1 << 32)) - ! We fix that here. - -#if 0 - tst %o0 - bge 1f - rd %y, %o0 - - ! %o0 was indeed negative; fix upper 32 bits of result by subtracting - ! %o1 (i.e., return %o4 - %o1 in %o1). - retl - sub %o4, %o1, %o1 - -1: - retl - mov %o4, %o1 -#else - /* Faster code adapted from [email protected]'s code for umul.S. */ - sra %o0, 31, %o2 ! make mask from sign bit - and %o1, %o2, %o2 ! %o2 = 0 or %o1, depending on sign of %o0 - rd %y, %o0 ! get lower half of product - retl - sub %o4, %o2, %o1 ! subtract compensation - ! and put upper half in place -#endif - -Lmul_shortway: - /* - * Short multiply. 12 steps, followed by a final shift step. - * The resulting bits are off by 12 and (32-12) = 20 bit positions, - * but there is no problem with %o0 being negative (unlike above). - */ - mulscc %o4, %o1, %o4 ! 1 - mulscc %o4, %o1, %o4 ! 2 - mulscc %o4, %o1, %o4 ! 3 - mulscc %o4, %o1, %o4 ! 4 - mulscc %o4, %o1, %o4 ! 5 - mulscc %o4, %o1, %o4 ! 6 - mulscc %o4, %o1, %o4 ! 7 - mulscc %o4, %o1, %o4 ! 8 - mulscc %o4, %o1, %o4 ! 9 - mulscc %o4, %o1, %o4 ! 10 - mulscc %o4, %o1, %o4 ! 11 - mulscc %o4, %o1, %o4 ! 12 - mulscc %o4, %g0, %o4 ! final shift - - /* - * %o4 has 20 of the bits that should be in the low part of the - * result; %y has the bottom 12 (as %y's top 12). That is: - * - * %o4 %y - * +----------------+----------------+ - * | -12- | -20- | -12- | -20- | - * +------(---------+------)---------+ - * --hi-- ----low-part---- - * - * The upper 12 bits of %o4 should be sign-extended to form the - * high part of the product (i.e., highpart = %o4 >> 20). - */ - - rd %y, %o5 - sll %o4, 12, %o0 ! shift middle bits left 12 - srl %o5, 20, %o5 ! shift low bits right 20, zero fill at left - or %o5, %o0, %o0 ! construct low part of result - retl - sra %o4, 20, %o1 ! ... and extract high part of result - - .globl .mul_patch -.mul_patch: - smul %o0, %o1, %o0 - retl - rd %y, %o1 - nop diff --git a/arch/sparc/lib/muldi3.S b/arch/sparc/lib/muldi3.S index 7f17872d0603..9794939d1c12 100644 --- a/arch/sparc/lib/muldi3.S +++ b/arch/sparc/lib/muldi3.S @@ -63,12 +63,12 @@ __muldi3: rd %y, %o1 mov %o1, %l3 mov %i1, %o0 - call .umul mov %i2, %o1 + umul %o0, %o1, %o0 mov %o0, %l0 mov %i0, %o0 - call .umul mov %i3, %o1 + umul %o0, %o1, %o0 add %l0, %o0, %l0 mov %l2, %i0 add %l2, %l0, %i0 diff --git a/arch/sparc/lib/rem.S b/arch/sparc/lib/rem.S deleted file mode 100644 index 42fb86252815..000000000000 --- a/arch/sparc/lib/rem.S +++ /dev/null @@ -1,384 +0,0 @@ -/* - * rem.S: This routine was taken from glibc-1.09 and is covered - * by the GNU Library General Public License Version 2. - */ - - -/* This file is generated from divrem.m4; DO NOT EDIT! */ -/* - * Division and remainder, from Appendix E of the Sparc Version 8 - * Architecture Manual, with fixes from Gordon Irlam. - */ - -/* - * Input: dividend and divisor in %o0 and %o1 respectively. - * - * m4 parameters: - * .rem name of function to generate - * rem rem=div => %o0 / %o1; rem=rem => %o0 % %o1 - * true true=true => signed; true=false => unsigned - * - * Algorithm parameters: - * N how many bits per iteration we try to get (4) - * WORDSIZE total number of bits (32) - * - * Derived constants: - * TOPBITS number of bits in the top decade of a number - * - * Important variables: - * Q the partial quotient under development (initially 0) - * R the remainder so far, initially the dividend - * ITER number of main division loop iterations required; - * equal to ceil(log2(quotient) / N). Note that this - * is the log base (2^N) of the quotient. - * V the current comparand, initially divisor*2^(ITER*N-1) - * - * Cost: - * Current estimate for non-large dividend is - * ceil(log2(quotient) / N) * (10 + 7N/2) + C - * A large dividend is one greater than 2^(31-TOPBITS) and takes a - * different path, as the upper bits of the quotient must be developed - * one bit at a time. - */ - - - .globl .rem - .globl _Rem -.rem: -_Rem: /* needed for export */ - ! compute sign of result; if neither is negative, no problem - orcc %o1, %o0, %g0 ! either negative? - bge 2f ! no, go do the divide - mov %o0, %g2 ! compute sign in any case - - tst %o1 - bge 1f - tst %o0 - ! %o1 is definitely negative; %o0 might also be negative - bge 2f ! if %o0 not negative... - sub %g0, %o1, %o1 ! in any case, make %o1 nonneg -1: ! %o0 is negative, %o1 is nonnegative - sub %g0, %o0, %o0 ! make %o0 nonnegative -2: - - ! Ready to divide. Compute size of quotient; scale comparand. - orcc %o1, %g0, %o5 - bne 1f - mov %o0, %o3 - - ! Divide by zero trap. If it returns, return 0 (about as - ! wrong as possible, but that is what SunOS does...). - ta ST_DIV0 - retl - clr %o0 - -1: - cmp %o3, %o5 ! if %o1 exceeds %o0, done - blu Lgot_result ! (and algorithm fails otherwise) - clr %o2 - - sethi %hi(1 << (32 - 4 - 1)), %g1 - - cmp %o3, %g1 - blu Lnot_really_big - clr %o4 - - ! Here the dividend is >= 2**(31-N) or so. We must be careful here, - ! as our usual N-at-a-shot divide step will cause overflow and havoc. - ! The number of bits in the result here is N*ITER+SC, where SC <= N. - ! Compute ITER in an unorthodox manner: know we need to shift V into - ! the top decade: so do not even bother to compare to R. - 1: - cmp %o5, %g1 - bgeu 3f - mov 1, %g7 - - sll %o5, 4, %o5 - - b 1b - add %o4, 1, %o4 - - ! Now compute %g7. - 2: - addcc %o5, %o5, %o5 - - bcc Lnot_too_big - add %g7, 1, %g7 - - ! We get here if the %o1 overflowed while shifting. - ! This means that %o3 has the high-order bit set. - ! Restore %o5 and subtract from %o3. - sll %g1, 4, %g1 ! high order bit - srl %o5, 1, %o5 ! rest of %o5 - add %o5, %g1, %o5 - - b Ldo_single_div - sub %g7, 1, %g7 - - Lnot_too_big: - 3: - cmp %o5, %o3 - blu 2b - nop - - be Ldo_single_div - nop - /* NB: these are commented out in the V8-Sparc manual as well */ - /* (I do not understand this) */ - ! %o5 > %o3: went too far: back up 1 step - ! srl %o5, 1, %o5 - ! dec %g7 - ! do single-bit divide steps - ! - ! We have to be careful here. We know that %o3 >= %o5, so we can do the - ! first divide step without thinking. BUT, the others are conditional, - ! and are only done if %o3 >= 0. Because both %o3 and %o5 may have the high- - ! order bit set in the first step, just falling into the regular - ! division loop will mess up the first time around. - ! So we unroll slightly... - Ldo_single_div: - subcc %g7, 1, %g7 - bl Lend_regular_divide - nop - - sub %o3, %o5, %o3 - mov 1, %o2 - - b Lend_single_divloop - nop - Lsingle_divloop: - sll %o2, 1, %o2 - - bl 1f - srl %o5, 1, %o5 - ! %o3 >= 0 - sub %o3, %o5, %o3 - - b 2f - add %o2, 1, %o2 - 1: ! %o3 < 0 - add %o3, %o5, %o3 - sub %o2, 1, %o2 - 2: - Lend_single_divloop: - subcc %g7, 1, %g7 - bge Lsingle_divloop - tst %o3 - - b,a Lend_regular_divide - -Lnot_really_big: -1: - sll %o5, 4, %o5 - cmp %o5, %o3 - bleu 1b - addcc %o4, 1, %o4 - be Lgot_result - sub %o4, 1, %o4 - - tst %o3 ! set up for initial iteration -Ldivloop: - sll %o2, 4, %o2 - ! depth 1, accumulated bits 0 - bl L.1.16 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - ! depth 2, accumulated bits 1 - bl L.2.17 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - ! depth 3, accumulated bits 3 - bl L.3.19 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - ! depth 4, accumulated bits 7 - bl L.4.23 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - - b 9f - add %o2, (7*2+1), %o2 - -L.4.23: - ! remainder is negative - addcc %o3,%o5,%o3 - b 9f - add %o2, (7*2-1), %o2 - -L.3.19: - ! remainder is negative - addcc %o3,%o5,%o3 - ! depth 4, accumulated bits 5 - bl L.4.21 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - b 9f - add %o2, (5*2+1), %o2 - -L.4.21: - ! remainder is negative - addcc %o3,%o5,%o3 - b 9f - add %o2, (5*2-1), %o2 - -L.2.17: - ! remainder is negative - addcc %o3,%o5,%o3 - ! depth 3, accumulated bits 1 - bl L.3.17 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - ! depth 4, accumulated bits 3 - bl L.4.19 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - b 9f - add %o2, (3*2+1), %o2 - -L.4.19: - ! remainder is negative - addcc %o3,%o5,%o3 - b 9f - add %o2, (3*2-1), %o2 - -L.3.17: - ! remainder is negative - addcc %o3,%o5,%o3 - ! depth 4, accumulated bits 1 - bl L.4.17 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - b 9f - add %o2, (1*2+1), %o2 - -L.4.17: - ! remainder is negative - addcc %o3,%o5,%o3 - b 9f - add %o2, (1*2-1), %o2 - -L.1.16: - ! remainder is negative - addcc %o3,%o5,%o3 - ! depth 2, accumulated bits -1 - bl L.2.15 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - ! depth 3, accumulated bits -1 - bl L.3.15 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - ! depth 4, accumulated bits -1 - bl L.4.15 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - b 9f - add %o2, (-1*2+1), %o2 - -L.4.15: - ! remainder is negative - addcc %o3,%o5,%o3 - b 9f - add %o2, (-1*2-1), %o2 - -L.3.15: - ! remainder is negative - addcc %o3,%o5,%o3 - ! depth 4, accumulated bits -3 - bl L.4.13 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - b 9f - add %o2, (-3*2+1), %o2 - -L.4.13: - ! remainder is negative - addcc %o3,%o5,%o3 - b 9f - add %o2, (-3*2-1), %o2 - -L.2.15: - ! remainder is negative - addcc %o3,%o5,%o3 - ! depth 3, accumulated bits -3 - bl L.3.13 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - ! depth 4, accumulated bits -5 - bl L.4.11 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - b 9f - add %o2, (-5*2+1), %o2 - -L.4.11: - ! remainder is negative - addcc %o3,%o5,%o3 - b 9f - add %o2, (-5*2-1), %o2 - - -L.3.13: - ! remainder is negative - addcc %o3,%o5,%o3 - ! depth 4, accumulated bits -7 - bl L.4.9 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - b 9f - add %o2, (-7*2+1), %o2 - -L.4.9: - ! remainder is negative - addcc %o3,%o5,%o3 - b 9f - add %o2, (-7*2-1), %o2 - - 9: -Lend_regular_divide: - subcc %o4, 1, %o4 - bge Ldivloop - tst %o3 - - bl,a Lgot_result - ! non-restoring fixup here (one instruction only!) - add %o3, %o1, %o3 - -Lgot_result: - ! check to see if answer should be < 0 - tst %g2 - bl,a 1f - sub %g0, %o3, %o3 -1: - retl - mov %o3, %o0 - - .globl .rem_patch -.rem_patch: - sra %o0, 0x1f, %o4 - wr %o4, 0x0, %y - nop - nop - nop - sdivcc %o0, %o1, %o2 - bvs,a 1f - xnor %o2, %g0, %o2 -1: smul %o2, %o1, %o2 - retl - sub %o0, %o2, %o0 - nop diff --git a/arch/sparc/lib/sdiv.S b/arch/sparc/lib/sdiv.S deleted file mode 100644 index f0a0d4e4db78..000000000000 --- a/arch/sparc/lib/sdiv.S +++ /dev/null @@ -1,381 +0,0 @@ -/* - * sdiv.S: This routine was taken from glibc-1.09 and is covered - * by the GNU Library General Public License Version 2. - */ - - -/* This file is generated from divrem.m4; DO NOT EDIT! */ -/* - * Division and remainder, from Appendix E of the Sparc Version 8 - * Architecture Manual, with fixes from Gordon Irlam. - */ - -/* - * Input: dividend and divisor in %o0 and %o1 respectively. - * - * m4 parameters: - * .div name of function to generate - * div div=div => %o0 / %o1; div=rem => %o0 % %o1 - * true true=true => signed; true=false => unsigned - * - * Algorithm parameters: - * N how many bits per iteration we try to get (4) - * WORDSIZE total number of bits (32) - * - * Derived constants: - * TOPBITS number of bits in the top decade of a number - * - * Important variables: - * Q the partial quotient under development (initially 0) - * R the remainder so far, initially the dividend - * ITER number of main division loop iterations required; - * equal to ceil(log2(quotient) / N). Note that this - * is the log base (2^N) of the quotient. - * V the current comparand, initially divisor*2^(ITER*N-1) - * - * Cost: - * Current estimate for non-large dividend is - * ceil(log2(quotient) / N) * (10 + 7N/2) + C - * A large dividend is one greater than 2^(31-TOPBITS) and takes a - * different path, as the upper bits of the quotient must be developed - * one bit at a time. - */ - - - .globl .div - .globl _Div -.div: -_Div: /* needed for export */ - ! compute sign of result; if neither is negative, no problem - orcc %o1, %o0, %g0 ! either negative? - bge 2f ! no, go do the divide - xor %o1, %o0, %g2 ! compute sign in any case - - tst %o1 - bge 1f - tst %o0 - ! %o1 is definitely negative; %o0 might also be negative - bge 2f ! if %o0 not negative... - sub %g0, %o1, %o1 ! in any case, make %o1 nonneg -1: ! %o0 is negative, %o1 is nonnegative - sub %g0, %o0, %o0 ! make %o0 nonnegative -2: - - ! Ready to divide. Compute size of quotient; scale comparand. - orcc %o1, %g0, %o5 - bne 1f - mov %o0, %o3 - - ! Divide by zero trap. If it returns, return 0 (about as - ! wrong as possible, but that is what SunOS does...). - ta ST_DIV0 - retl - clr %o0 - -1: - cmp %o3, %o5 ! if %o1 exceeds %o0, done - blu Lgot_result ! (and algorithm fails otherwise) - clr %o2 - - sethi %hi(1 << (32 - 4 - 1)), %g1 - - cmp %o3, %g1 - blu Lnot_really_big - clr %o4 - - ! Here the dividend is >= 2**(31-N) or so. We must be careful here, - ! as our usual N-at-a-shot divide step will cause overflow and havoc. - ! The number of bits in the result here is N*ITER+SC, where SC <= N. - ! Compute ITER in an unorthodox manner: know we need to shift V into - ! the top decade: so do not even bother to compare to R. - 1: - cmp %o5, %g1 - bgeu 3f - mov 1, %g7 - - sll %o5, 4, %o5 - - b 1b - add %o4, 1, %o4 - - ! Now compute %g7. - 2: - addcc %o5, %o5, %o5 - bcc Lnot_too_big - add %g7, 1, %g7 - - ! We get here if the %o1 overflowed while shifting. - ! This means that %o3 has the high-order bit set. - ! Restore %o5 and subtract from %o3. - sll %g1, 4, %g1 ! high order bit - srl %o5, 1, %o5 ! rest of %o5 - add %o5, %g1, %o5 - - b Ldo_single_div - sub %g7, 1, %g7 - - Lnot_too_big: - 3: - cmp %o5, %o3 - blu 2b - nop - - be Ldo_single_div - nop - /* NB: these are commented out in the V8-Sparc manual as well */ - /* (I do not understand this) */ - ! %o5 > %o3: went too far: back up 1 step - ! srl %o5, 1, %o5 - ! dec %g7 - ! do single-bit divide steps - ! - ! We have to be careful here. We know that %o3 >= %o5, so we can do the - ! first divide step without thinking. BUT, the others are conditional, - ! and are only done if %o3 >= 0. Because both %o3 and %o5 may have the high- - ! order bit set in the first step, just falling into the regular - ! division loop will mess up the first time around. - ! So we unroll slightly... - Ldo_single_div: - subcc %g7, 1, %g7 - bl Lend_regular_divide - nop - - sub %o3, %o5, %o3 - mov 1, %o2 - - b Lend_single_divloop - nop - Lsingle_divloop: - sll %o2, 1, %o2 - - bl 1f - srl %o5, 1, %o5 - ! %o3 >= 0 - sub %o3, %o5, %o3 - - b 2f - add %o2, 1, %o2 - 1: ! %o3 < 0 - add %o3, %o5, %o3 - sub %o2, 1, %o2 - 2: - Lend_single_divloop: - subcc %g7, 1, %g7 - bge Lsingle_divloop - tst %o3 - - b,a Lend_regular_divide - -Lnot_really_big: -1: - sll %o5, 4, %o5 - cmp %o5, %o3 - bleu 1b - addcc %o4, 1, %o4 - - be Lgot_result - sub %o4, 1, %o4 - - tst %o3 ! set up for initial iteration -Ldivloop: - sll %o2, 4, %o2 - ! depth 1, accumulated bits 0 - bl L.1.16 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - ! depth 2, accumulated bits 1 - bl L.2.17 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - ! depth 3, accumulated bits 3 - bl L.3.19 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - ! depth 4, accumulated bits 7 - bl L.4.23 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - b 9f - add %o2, (7*2+1), %o2 - -L.4.23: - ! remainder is negative - addcc %o3,%o5,%o3 - b 9f - add %o2, (7*2-1), %o2 - -L.3.19: - ! remainder is negative - addcc %o3,%o5,%o3 - ! depth 4, accumulated bits 5 - bl L.4.21 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - b 9f - add %o2, (5*2+1), %o2 - -L.4.21: - ! remainder is negative - addcc %o3,%o5,%o3 - b 9f - add %o2, (5*2-1), %o2 - -L.2.17: - ! remainder is negative - addcc %o3,%o5,%o3 - ! depth 3, accumulated bits 1 - bl L.3.17 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - ! depth 4, accumulated bits 3 - bl L.4.19 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - b 9f - add %o2, (3*2+1), %o2 - -L.4.19: - ! remainder is negative - addcc %o3,%o5,%o3 - b 9f - add %o2, (3*2-1), %o2 - - -L.3.17: - ! remainder is negative - addcc %o3,%o5,%o3 - ! depth 4, accumulated bits 1 - bl L.4.17 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - b 9f - add %o2, (1*2+1), %o2 - -L.4.17: - ! remainder is negative - addcc %o3,%o5,%o3 - b 9f - add %o2, (1*2-1), %o2 - -L.1.16: - ! remainder is negative - addcc %o3,%o5,%o3 - ! depth 2, accumulated bits -1 - bl L.2.15 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - ! depth 3, accumulated bits -1 - bl L.3.15 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - ! depth 4, accumulated bits -1 - bl L.4.15 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - b 9f - add %o2, (-1*2+1), %o2 - -L.4.15: - ! remainder is negative - addcc %o3,%o5,%o3 - b 9f - add %o2, (-1*2-1), %o2 - -L.3.15: - ! remainder is negative - addcc %o3,%o5,%o3 - ! depth 4, accumulated bits -3 - bl L.4.13 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - b 9f - add %o2, (-3*2+1), %o2 - -L.4.13: - ! remainder is negative - addcc %o3,%o5,%o3 - b 9f - add %o2, (-3*2-1), %o2 - -L.2.15: - ! remainder is negative - addcc %o3,%o5,%o3 - ! depth 3, accumulated bits -3 - bl L.3.13 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - ! depth 4, accumulated bits -5 - bl L.4.11 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - b 9f - add %o2, (-5*2+1), %o2 - -L.4.11: - ! remainder is negative - addcc %o3,%o5,%o3 - b 9f - add %o2, (-5*2-1), %o2 - -L.3.13: - ! remainder is negative - addcc %o3,%o5,%o3 - ! depth 4, accumulated bits -7 - bl L.4.9 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - b 9f - add %o2, (-7*2+1), %o2 - -L.4.9: - ! remainder is negative - addcc %o3,%o5,%o3 - b 9f - add %o2, (-7*2-1), %o2 - - 9: -Lend_regular_divide: - subcc %o4, 1, %o4 - bge Ldivloop - tst %o3 - - bl,a Lgot_result - ! non-restoring fixup here (one instruction only!) - sub %o2, 1, %o2 - -Lgot_result: - ! check to see if answer should be < 0 - tst %g2 - bl,a 1f - sub %g0, %o2, %o2 -1: - retl - mov %o2, %o0 - - .globl .div_patch -.div_patch: - sra %o0, 0x1f, %o2 - wr %o2, 0x0, %y - nop - nop - nop - sdivcc %o0, %o1, %o0 - bvs,a 1f - xnor %o0, %g0, %o0 -1: retl - nop diff --git a/arch/sparc/lib/strlen_user_64.S b/arch/sparc/lib/strlen_user_64.S index 114ed111e251..c3df71fa4928 100644 --- a/arch/sparc/lib/strlen_user_64.S +++ b/arch/sparc/lib/strlen_user_64.S @@ -8,16 +8,16 @@ * Copyright (C) 1996,1997 Jakub Jelinek ([email protected]) */ +#include <linux/linkage.h> #include <asm/asi.h> #define LO_MAGIC 0x01010101 #define HI_MAGIC 0x80808080 .align 4 - .global __strlen_user, __strnlen_user -__strlen_user: +ENTRY(__strlen_user) sethi %hi(32768), %o1 -__strnlen_user: +ENTRY(__strnlen_user) mov %o1, %g1 mov %o0, %o1 andcc %o0, 3, %g0 @@ -78,6 +78,8 @@ __strnlen_user: mov 2, %o0 23: retl mov 3, %o0 +ENDPROC(__strlen_user) +ENDPROC(__strnlen_user) .section .fixup,#alloc,#execinstr .align 4 diff --git a/arch/sparc/lib/strncmp_32.S b/arch/sparc/lib/strncmp_32.S index 494ec664537a..c0d1b568c1c5 100644 --- a/arch/sparc/lib/strncmp_32.S +++ b/arch/sparc/lib/strncmp_32.S @@ -3,11 +3,10 @@ * generic strncmp routine. */ +#include <linux/linkage.h> + .text - .align 4 - .global __strncmp, strncmp -__strncmp: -strncmp: +ENTRY(strncmp) mov %o0, %g3 mov 0, %o3 @@ -116,3 +115,4 @@ strncmp: and %g2, 0xff, %o0 retl sub %o3, %o0, %o0 +ENDPROC(strncmp) diff --git a/arch/sparc/lib/strncmp_64.S b/arch/sparc/lib/strncmp_64.S index 980e83751556..0656627166f3 100644 --- a/arch/sparc/lib/strncmp_64.S +++ b/arch/sparc/lib/strncmp_64.S @@ -4,13 +4,11 @@ * Copyright (C) 1997 Jakub Jelinek ([email protected]) */ +#include <linux/linkage.h> #include <asm/asi.h> .text - .align 32 - .globl strncmp - .type strncmp,#function -strncmp: +ENTRY(strncmp) brlez,pn %o2, 3f lduba [%o0] (ASI_PNF), %o3 1: @@ -29,4 +27,4 @@ strncmp: 3: retl clr %o0 - .size strncmp, .-strncmp +ENDPROC(strncmp) diff --git a/arch/sparc/lib/strncpy_from_user_32.S b/arch/sparc/lib/strncpy_from_user_32.S index d77198976a66..db0ed2964bdb 100644 --- a/arch/sparc/lib/strncpy_from_user_32.S +++ b/arch/sparc/lib/strncpy_from_user_32.S @@ -3,11 +3,11 @@ * Copyright(C) 1996 David S. Miller */ +#include <linux/linkage.h> #include <asm/ptrace.h> #include <asm/errno.h> .text - .align 4 /* Must return: * @@ -16,8 +16,7 @@ * bytes copied if we hit a null byte */ - .globl __strncpy_from_user -__strncpy_from_user: +ENTRY(__strncpy_from_user) /* %o0=dest, %o1=src, %o2=count */ mov %o2, %o3 1: @@ -35,6 +34,7 @@ __strncpy_from_user: add %o2, 1, %o0 retl sub %o3, %o0, %o0 +ENDPROC(__strncpy_from_user) .section .fixup,#alloc,#execinstr .align 4 diff --git a/arch/sparc/lib/strncpy_from_user_64.S b/arch/sparc/lib/strncpy_from_user_64.S index 511c8f136f95..d1246b713077 100644 --- a/arch/sparc/lib/strncpy_from_user_64.S +++ b/arch/sparc/lib/strncpy_from_user_64.S @@ -4,6 +4,7 @@ * Copyright (C) 1997, 1999 Jakub Jelinek ([email protected]) */ +#include <linux/linkage.h> #include <asm/asi.h> #include <asm/errno.h> @@ -12,7 +13,6 @@ 0: .xword 0x0101010101010101 .text - .align 32 /* Must return: * @@ -30,9 +30,7 @@ * and average length is 18 or so. */ - .globl __strncpy_from_user - .type __strncpy_from_user,#function -__strncpy_from_user: +ENTRY(__strncpy_from_user) /* %o0=dest, %o1=src, %o2=count */ andcc %o1, 7, %g0 ! IEU1 Group bne,pn %icc, 30f ! CTI @@ -123,7 +121,7 @@ __strncpy_from_user: mov %o2, %o0 2: retl add %o2, %o3, %o0 - .size __strncpy_from_user, .-__strncpy_from_user +ENDPROC(__strncpy_from_user) .section __ex_table,"a" .align 4 diff --git a/arch/sparc/lib/ucmpdi2.c b/arch/sparc/lib/ucmpdi2.c new file mode 100644 index 000000000000..1e06ed500682 --- /dev/null +++ b/arch/sparc/lib/ucmpdi2.c @@ -0,0 +1,19 @@ +#include <linux/module.h> +#include "libgcc.h" + +word_type __ucmpdi2(unsigned long long a, unsigned long long b) +{ + const DWunion au = {.ll = a}; + const DWunion bu = {.ll = b}; + + if ((unsigned int) au.s.high < (unsigned int) bu.s.high) + return 0; + else if ((unsigned int) au.s.high > (unsigned int) bu.s.high) + return 2; + if ((unsigned int) au.s.low < (unsigned int) bu.s.low) + return 0; + else if ((unsigned int) au.s.low > (unsigned int) bu.s.low) + return 2; + return 1; +} +EXPORT_SYMBOL(__ucmpdi2); diff --git a/arch/sparc/lib/udiv.S b/arch/sparc/lib/udiv.S deleted file mode 100644 index 2101405bdfcb..000000000000 --- a/arch/sparc/lib/udiv.S +++ /dev/null @@ -1,357 +0,0 @@ -/* - * udiv.S: This routine was taken from glibc-1.09 and is covered - * by the GNU Library General Public License Version 2. - */ - - -/* This file is generated from divrem.m4; DO NOT EDIT! */ -/* - * Division and remainder, from Appendix E of the Sparc Version 8 - * Architecture Manual, with fixes from Gordon Irlam. - */ - -/* - * Input: dividend and divisor in %o0 and %o1 respectively. - * - * m4 parameters: - * .udiv name of function to generate - * div div=div => %o0 / %o1; div=rem => %o0 % %o1 - * false false=true => signed; false=false => unsigned - * - * Algorithm parameters: - * N how many bits per iteration we try to get (4) - * WORDSIZE total number of bits (32) - * - * Derived constants: - * TOPBITS number of bits in the top decade of a number - * - * Important variables: - * Q the partial quotient under development (initially 0) - * R the remainder so far, initially the dividend - * ITER number of main division loop iterations required; - * equal to ceil(log2(quotient) / N). Note that this - * is the log base (2^N) of the quotient. - * V the current comparand, initially divisor*2^(ITER*N-1) - * - * Cost: - * Current estimate for non-large dividend is - * ceil(log2(quotient) / N) * (10 + 7N/2) + C - * A large dividend is one greater than 2^(31-TOPBITS) and takes a - * different path, as the upper bits of the quotient must be developed - * one bit at a time. - */ - - - .globl .udiv - .globl _Udiv -.udiv: -_Udiv: /* needed for export */ - - ! Ready to divide. Compute size of quotient; scale comparand. - orcc %o1, %g0, %o5 - bne 1f - mov %o0, %o3 - - ! Divide by zero trap. If it returns, return 0 (about as - ! wrong as possible, but that is what SunOS does...). - ta ST_DIV0 - retl - clr %o0 - -1: - cmp %o3, %o5 ! if %o1 exceeds %o0, done - blu Lgot_result ! (and algorithm fails otherwise) - clr %o2 - - sethi %hi(1 << (32 - 4 - 1)), %g1 - - cmp %o3, %g1 - blu Lnot_really_big - clr %o4 - - ! Here the dividend is >= 2**(31-N) or so. We must be careful here, - ! as our usual N-at-a-shot divide step will cause overflow and havoc. - ! The number of bits in the result here is N*ITER+SC, where SC <= N. - ! Compute ITER in an unorthodox manner: know we need to shift V into - ! the top decade: so do not even bother to compare to R. - 1: - cmp %o5, %g1 - bgeu 3f - mov 1, %g7 - - sll %o5, 4, %o5 - - b 1b - add %o4, 1, %o4 - - ! Now compute %g7. - 2: - addcc %o5, %o5, %o5 - bcc Lnot_too_big - add %g7, 1, %g7 - - ! We get here if the %o1 overflowed while shifting. - ! This means that %o3 has the high-order bit set. - ! Restore %o5 and subtract from %o3. - sll %g1, 4, %g1 ! high order bit - srl %o5, 1, %o5 ! rest of %o5 - add %o5, %g1, %o5 - - b Ldo_single_div - sub %g7, 1, %g7 - - Lnot_too_big: - 3: - cmp %o5, %o3 - blu 2b - nop - - be Ldo_single_div - nop - /* NB: these are commented out in the V8-Sparc manual as well */ - /* (I do not understand this) */ - ! %o5 > %o3: went too far: back up 1 step - ! srl %o5, 1, %o5 - ! dec %g7 - ! do single-bit divide steps - ! - ! We have to be careful here. We know that %o3 >= %o5, so we can do the - ! first divide step without thinking. BUT, the others are conditional, - ! and are only done if %o3 >= 0. Because both %o3 and %o5 may have the high- - ! order bit set in the first step, just falling into the regular - ! division loop will mess up the first time around. - ! So we unroll slightly... - Ldo_single_div: - subcc %g7, 1, %g7 - bl Lend_regular_divide - nop - - sub %o3, %o5, %o3 - mov 1, %o2 - - b Lend_single_divloop - nop - Lsingle_divloop: - sll %o2, 1, %o2 - bl 1f - srl %o5, 1, %o5 - ! %o3 >= 0 - sub %o3, %o5, %o3 - b 2f - add %o2, 1, %o2 - 1: ! %o3 < 0 - add %o3, %o5, %o3 - sub %o2, 1, %o2 - 2: - Lend_single_divloop: - subcc %g7, 1, %g7 - bge Lsingle_divloop - tst %o3 - - b,a Lend_regular_divide - -Lnot_really_big: -1: - sll %o5, 4, %o5 - - cmp %o5, %o3 - bleu 1b - addcc %o4, 1, %o4 - - be Lgot_result - sub %o4, 1, %o4 - - tst %o3 ! set up for initial iteration -Ldivloop: - sll %o2, 4, %o2 - ! depth 1, accumulated bits 0 - bl L.1.16 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - ! depth 2, accumulated bits 1 - bl L.2.17 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - ! depth 3, accumulated bits 3 - bl L.3.19 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - ! depth 4, accumulated bits 7 - bl L.4.23 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - b 9f - add %o2, (7*2+1), %o2 - -L.4.23: - ! remainder is negative - addcc %o3,%o5,%o3 - b 9f - add %o2, (7*2-1), %o2 - -L.3.19: - ! remainder is negative - addcc %o3,%o5,%o3 - ! depth 4, accumulated bits 5 - bl L.4.21 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - b 9f - add %o2, (5*2+1), %o2 - -L.4.21: - ! remainder is negative - addcc %o3,%o5,%o3 - b 9f - add %o2, (5*2-1), %o2 - -L.2.17: - ! remainder is negative - addcc %o3,%o5,%o3 - ! depth 3, accumulated bits 1 - bl L.3.17 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - ! depth 4, accumulated bits 3 - bl L.4.19 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - b 9f - add %o2, (3*2+1), %o2 - -L.4.19: - ! remainder is negative - addcc %o3,%o5,%o3 - b 9f - add %o2, (3*2-1), %o2 - -L.3.17: - ! remainder is negative - addcc %o3,%o5,%o3 - ! depth 4, accumulated bits 1 - bl L.4.17 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - b 9f - add %o2, (1*2+1), %o2 - -L.4.17: - ! remainder is negative - addcc %o3,%o5,%o3 - b 9f - add %o2, (1*2-1), %o2 - -L.1.16: - ! remainder is negative - addcc %o3,%o5,%o3 - ! depth 2, accumulated bits -1 - bl L.2.15 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - ! depth 3, accumulated bits -1 - bl L.3.15 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - ! depth 4, accumulated bits -1 - bl L.4.15 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - b 9f - add %o2, (-1*2+1), %o2 - -L.4.15: - ! remainder is negative - addcc %o3,%o5,%o3 - b 9f - add %o2, (-1*2-1), %o2 - -L.3.15: - ! remainder is negative - addcc %o3,%o5,%o3 - ! depth 4, accumulated bits -3 - bl L.4.13 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - b 9f - add %o2, (-3*2+1), %o2 - -L.4.13: - ! remainder is negative - addcc %o3,%o5,%o3 - b 9f - add %o2, (-3*2-1), %o2 - -L.2.15: - ! remainder is negative - addcc %o3,%o5,%o3 - ! depth 3, accumulated bits -3 - bl L.3.13 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - ! depth 4, accumulated bits -5 - bl L.4.11 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - b 9f - add %o2, (-5*2+1), %o2 - -L.4.11: - ! remainder is negative - addcc %o3,%o5,%o3 - b 9f - add %o2, (-5*2-1), %o2 - -L.3.13: - ! remainder is negative - addcc %o3,%o5,%o3 - ! depth 4, accumulated bits -7 - bl L.4.9 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - b 9f - add %o2, (-7*2+1), %o2 - -L.4.9: - ! remainder is negative - addcc %o3,%o5,%o3 - b 9f - add %o2, (-7*2-1), %o2 - - 9: -Lend_regular_divide: - subcc %o4, 1, %o4 - bge Ldivloop - tst %o3 - - bl,a Lgot_result - ! non-restoring fixup here (one instruction only!) - sub %o2, 1, %o2 - -Lgot_result: - - retl - mov %o2, %o0 - - .globl .udiv_patch -.udiv_patch: - wr %g0, 0x0, %y - nop - nop - retl - udiv %o0, %o1, %o0 - nop diff --git a/arch/sparc/lib/udivdi3.S b/arch/sparc/lib/udivdi3.S index b430f1f0ef62..24e0a355e2e8 100644 --- a/arch/sparc/lib/udivdi3.S +++ b/arch/sparc/lib/udivdi3.S @@ -60,8 +60,9 @@ __udivdi3: bne .LL77 mov %i0,%o2 mov 1,%o0 - call .udiv,0 mov 0,%o1 + wr %g0, 0, %y + udiv %o0, %o1, %o0 mov %o0,%o3 mov %i0,%o2 .LL77: diff --git a/arch/sparc/lib/umul.S b/arch/sparc/lib/umul.S deleted file mode 100644 index 1f36ae682529..000000000000 --- a/arch/sparc/lib/umul.S +++ /dev/null @@ -1,171 +0,0 @@ -/* - * umul.S: This routine was taken from glibc-1.09 and is covered - * by the GNU Library General Public License Version 2. - */ - - -/* - * Unsigned multiply. Returns %o0 * %o1 in %o1%o0 (i.e., %o1 holds the - * upper 32 bits of the 64-bit product). - * - * This code optimizes short (less than 13-bit) multiplies. Short - * multiplies require 25 instruction cycles, and long ones require - * 45 instruction cycles. - * - * On return, overflow has occurred (%o1 is not zero) if and only if - * the Z condition code is clear, allowing, e.g., the following: - * - * call .umul - * nop - * bnz overflow (or tnz) - */ - - .globl .umul - .globl _Umul -.umul: -_Umul: /* needed for export */ - or %o0, %o1, %o4 - mov %o0, %y ! multiplier -> Y - - andncc %o4, 0xfff, %g0 ! test bits 12..31 of *both* args - be Lmul_shortway ! if zero, can do it the short way - andcc %g0, %g0, %o4 ! zero the partial product and clear N and V - - /* - * Long multiply. 32 steps, followed by a final shift step. - */ - mulscc %o4, %o1, %o4 ! 1 - mulscc %o4, %o1, %o4 ! 2 - mulscc %o4, %o1, %o4 ! 3 - mulscc %o4, %o1, %o4 ! 4 - mulscc %o4, %o1, %o4 ! 5 - mulscc %o4, %o1, %o4 ! 6 - mulscc %o4, %o1, %o4 ! 7 - mulscc %o4, %o1, %o4 ! 8 - mulscc %o4, %o1, %o4 ! 9 - mulscc %o4, %o1, %o4 ! 10 - mulscc %o4, %o1, %o4 ! 11 - mulscc %o4, %o1, %o4 ! 12 - mulscc %o4, %o1, %o4 ! 13 - mulscc %o4, %o1, %o4 ! 14 - mulscc %o4, %o1, %o4 ! 15 - mulscc %o4, %o1, %o4 ! 16 - mulscc %o4, %o1, %o4 ! 17 - mulscc %o4, %o1, %o4 ! 18 - mulscc %o4, %o1, %o4 ! 19 - mulscc %o4, %o1, %o4 ! 20 - mulscc %o4, %o1, %o4 ! 21 - mulscc %o4, %o1, %o4 ! 22 - mulscc %o4, %o1, %o4 ! 23 - mulscc %o4, %o1, %o4 ! 24 - mulscc %o4, %o1, %o4 ! 25 - mulscc %o4, %o1, %o4 ! 26 - mulscc %o4, %o1, %o4 ! 27 - mulscc %o4, %o1, %o4 ! 28 - mulscc %o4, %o1, %o4 ! 29 - mulscc %o4, %o1, %o4 ! 30 - mulscc %o4, %o1, %o4 ! 31 - mulscc %o4, %o1, %o4 ! 32 - mulscc %o4, %g0, %o4 ! final shift - - - /* - * Normally, with the shift-and-add approach, if both numbers are - * positive you get the correct result. With 32-bit two's-complement - * numbers, -x is represented as - * - * x 32 - * ( 2 - ------ ) mod 2 * 2 - * 32 - * 2 - * - * (the `mod 2' subtracts 1 from 1.bbbb). To avoid lots of 2^32s, - * we can treat this as if the radix point were just to the left - * of the sign bit (multiply by 2^32), and get - * - * -x = (2 - x) mod 2 - * - * Then, ignoring the `mod 2's for convenience: - * - * x * y = xy - * -x * y = 2y - xy - * x * -y = 2x - xy - * -x * -y = 4 - 2x - 2y + xy - * - * For signed multiplies, we subtract (x << 32) from the partial - * product to fix this problem for negative multipliers (see mul.s). - * Because of the way the shift into the partial product is calculated - * (N xor V), this term is automatically removed for the multiplicand, - * so we don't have to adjust. - * - * But for unsigned multiplies, the high order bit wasn't a sign bit, - * and the correction is wrong. So for unsigned multiplies where the - * high order bit is one, we end up with xy - (y << 32). To fix it - * we add y << 32. - */ -#if 0 - tst %o1 - bl,a 1f ! if %o1 < 0 (high order bit = 1), - add %o4, %o0, %o4 ! %o4 += %o0 (add y to upper half) - -1: - rd %y, %o0 ! get lower half of product - retl - addcc %o4, %g0, %o1 ! put upper half in place and set Z for %o1==0 -#else - /* Faster code from [email protected]. */ - sra %o1, 31, %o2 ! make mask from sign bit - and %o0, %o2, %o2 ! %o2 = 0 or %o0, depending on sign of %o1 - rd %y, %o0 ! get lower half of product - retl - addcc %o4, %o2, %o1 ! add compensation and put upper half in place -#endif - -Lmul_shortway: - /* - * Short multiply. 12 steps, followed by a final shift step. - * The resulting bits are off by 12 and (32-12) = 20 bit positions, - * but there is no problem with %o0 being negative (unlike above), - * and overflow is impossible (the answer is at most 24 bits long). - */ - mulscc %o4, %o1, %o4 ! 1 - mulscc %o4, %o1, %o4 ! 2 - mulscc %o4, %o1, %o4 ! 3 - mulscc %o4, %o1, %o4 ! 4 - mulscc %o4, %o1, %o4 ! 5 - mulscc %o4, %o1, %o4 ! 6 - mulscc %o4, %o1, %o4 ! 7 - mulscc %o4, %o1, %o4 ! 8 - mulscc %o4, %o1, %o4 ! 9 - mulscc %o4, %o1, %o4 ! 10 - mulscc %o4, %o1, %o4 ! 11 - mulscc %o4, %o1, %o4 ! 12 - mulscc %o4, %g0, %o4 ! final shift - - /* - * %o4 has 20 of the bits that should be in the result; %y has - * the bottom 12 (as %y's top 12). That is: - * - * %o4 %y - * +----------------+----------------+ - * | -12- | -20- | -12- | -20- | - * +------(---------+------)---------+ - * -----result----- - * - * The 12 bits of %o4 left of the `result' area are all zero; - * in fact, all top 20 bits of %o4 are zero. - */ - - rd %y, %o5 - sll %o4, 12, %o0 ! shift middle bits left 12 - srl %o5, 20, %o5 ! shift low bits right 20 - or %o5, %o0, %o0 - retl - addcc %g0, %g0, %o1 ! %o1 = zero, and set Z - - .globl .umul_patch -.umul_patch: - umul %o0, %o1, %o0 - retl - rd %y, %o1 - nop diff --git a/arch/sparc/lib/urem.S b/arch/sparc/lib/urem.S deleted file mode 100644 index 77123eb83c44..000000000000 --- a/arch/sparc/lib/urem.S +++ /dev/null @@ -1,357 +0,0 @@ -/* - * urem.S: This routine was taken from glibc-1.09 and is covered - * by the GNU Library General Public License Version 2. - */ - -/* This file is generated from divrem.m4; DO NOT EDIT! */ -/* - * Division and remainder, from Appendix E of the Sparc Version 8 - * Architecture Manual, with fixes from Gordon Irlam. - */ - -/* - * Input: dividend and divisor in %o0 and %o1 respectively. - * - * m4 parameters: - * .urem name of function to generate - * rem rem=div => %o0 / %o1; rem=rem => %o0 % %o1 - * false false=true => signed; false=false => unsigned - * - * Algorithm parameters: - * N how many bits per iteration we try to get (4) - * WORDSIZE total number of bits (32) - * - * Derived constants: - * TOPBITS number of bits in the top decade of a number - * - * Important variables: - * Q the partial quotient under development (initially 0) - * R the remainder so far, initially the dividend - * ITER number of main division loop iterations required; - * equal to ceil(log2(quotient) / N). Note that this - * is the log base (2^N) of the quotient. - * V the current comparand, initially divisor*2^(ITER*N-1) - * - * Cost: - * Current estimate for non-large dividend is - * ceil(log2(quotient) / N) * (10 + 7N/2) + C - * A large dividend is one greater than 2^(31-TOPBITS) and takes a - * different path, as the upper bits of the quotient must be developed - * one bit at a time. - */ - - .globl .urem - .globl _Urem -.urem: -_Urem: /* needed for export */ - - ! Ready to divide. Compute size of quotient; scale comparand. - orcc %o1, %g0, %o5 - bne 1f - mov %o0, %o3 - - ! Divide by zero trap. If it returns, return 0 (about as - ! wrong as possible, but that is what SunOS does...). - ta ST_DIV0 - retl - clr %o0 - -1: - cmp %o3, %o5 ! if %o1 exceeds %o0, done - blu Lgot_result ! (and algorithm fails otherwise) - clr %o2 - - sethi %hi(1 << (32 - 4 - 1)), %g1 - - cmp %o3, %g1 - blu Lnot_really_big - clr %o4 - - ! Here the dividend is >= 2**(31-N) or so. We must be careful here, - ! as our usual N-at-a-shot divide step will cause overflow and havoc. - ! The number of bits in the result here is N*ITER+SC, where SC <= N. - ! Compute ITER in an unorthodox manner: know we need to shift V into - ! the top decade: so do not even bother to compare to R. - 1: - cmp %o5, %g1 - bgeu 3f - mov 1, %g7 - - sll %o5, 4, %o5 - - b 1b - add %o4, 1, %o4 - - ! Now compute %g7. - 2: - addcc %o5, %o5, %o5 - bcc Lnot_too_big - add %g7, 1, %g7 - - ! We get here if the %o1 overflowed while shifting. - ! This means that %o3 has the high-order bit set. - ! Restore %o5 and subtract from %o3. - sll %g1, 4, %g1 ! high order bit - srl %o5, 1, %o5 ! rest of %o5 - add %o5, %g1, %o5 - - b Ldo_single_div - sub %g7, 1, %g7 - - Lnot_too_big: - 3: - cmp %o5, %o3 - blu 2b - nop - - be Ldo_single_div - nop - /* NB: these are commented out in the V8-Sparc manual as well */ - /* (I do not understand this) */ - ! %o5 > %o3: went too far: back up 1 step - ! srl %o5, 1, %o5 - ! dec %g7 - ! do single-bit divide steps - ! - ! We have to be careful here. We know that %o3 >= %o5, so we can do the - ! first divide step without thinking. BUT, the others are conditional, - ! and are only done if %o3 >= 0. Because both %o3 and %o5 may have the high- - ! order bit set in the first step, just falling into the regular - ! division loop will mess up the first time around. - ! So we unroll slightly... - Ldo_single_div: - subcc %g7, 1, %g7 - bl Lend_regular_divide - nop - - sub %o3, %o5, %o3 - mov 1, %o2 - - b Lend_single_divloop - nop - Lsingle_divloop: - sll %o2, 1, %o2 - bl 1f - srl %o5, 1, %o5 - ! %o3 >= 0 - sub %o3, %o5, %o3 - b 2f - add %o2, 1, %o2 - 1: ! %o3 < 0 - add %o3, %o5, %o3 - sub %o2, 1, %o2 - 2: - Lend_single_divloop: - subcc %g7, 1, %g7 - bge Lsingle_divloop - tst %o3 - - b,a Lend_regular_divide - -Lnot_really_big: -1: - sll %o5, 4, %o5 - - cmp %o5, %o3 - bleu 1b - addcc %o4, 1, %o4 - - be Lgot_result - sub %o4, 1, %o4 - - tst %o3 ! set up for initial iteration -Ldivloop: - sll %o2, 4, %o2 - ! depth 1, accumulated bits 0 - bl L.1.16 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - ! depth 2, accumulated bits 1 - bl L.2.17 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - ! depth 3, accumulated bits 3 - bl L.3.19 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - ! depth 4, accumulated bits 7 - bl L.4.23 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - b 9f - add %o2, (7*2+1), %o2 - -L.4.23: - ! remainder is negative - addcc %o3,%o5,%o3 - b 9f - add %o2, (7*2-1), %o2 - -L.3.19: - ! remainder is negative - addcc %o3,%o5,%o3 - ! depth 4, accumulated bits 5 - bl L.4.21 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - b 9f - add %o2, (5*2+1), %o2 - -L.4.21: - ! remainder is negative - addcc %o3,%o5,%o3 - b 9f - add %o2, (5*2-1), %o2 - -L.2.17: - ! remainder is negative - addcc %o3,%o5,%o3 - ! depth 3, accumulated bits 1 - bl L.3.17 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - ! depth 4, accumulated bits 3 - bl L.4.19 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - b 9f - add %o2, (3*2+1), %o2 - -L.4.19: - ! remainder is negative - addcc %o3,%o5,%o3 - b 9f - add %o2, (3*2-1), %o2 - -L.3.17: - ! remainder is negative - addcc %o3,%o5,%o3 - ! depth 4, accumulated bits 1 - bl L.4.17 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - b 9f - add %o2, (1*2+1), %o2 - -L.4.17: - ! remainder is negative - addcc %o3,%o5,%o3 - b 9f - add %o2, (1*2-1), %o2 - -L.1.16: - ! remainder is negative - addcc %o3,%o5,%o3 - ! depth 2, accumulated bits -1 - bl L.2.15 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - ! depth 3, accumulated bits -1 - bl L.3.15 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - ! depth 4, accumulated bits -1 - bl L.4.15 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - b 9f - add %o2, (-1*2+1), %o2 - -L.4.15: - ! remainder is negative - addcc %o3,%o5,%o3 - b 9f - add %o2, (-1*2-1), %o2 - -L.3.15: - ! remainder is negative - addcc %o3,%o5,%o3 - ! depth 4, accumulated bits -3 - bl L.4.13 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - b 9f - add %o2, (-3*2+1), %o2 - -L.4.13: - ! remainder is negative - addcc %o3,%o5,%o3 - b 9f - add %o2, (-3*2-1), %o2 - -L.2.15: - ! remainder is negative - addcc %o3,%o5,%o3 - ! depth 3, accumulated bits -3 - bl L.3.13 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - ! depth 4, accumulated bits -5 - bl L.4.11 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - b 9f - add %o2, (-5*2+1), %o2 - -L.4.11: - ! remainder is negative - addcc %o3,%o5,%o3 - b 9f - add %o2, (-5*2-1), %o2 - -L.3.13: - ! remainder is negative - addcc %o3,%o5,%o3 - ! depth 4, accumulated bits -7 - bl L.4.9 - srl %o5,1,%o5 - ! remainder is positive - subcc %o3,%o5,%o3 - b 9f - add %o2, (-7*2+1), %o2 - -L.4.9: - ! remainder is negative - addcc %o3,%o5,%o3 - b 9f - add %o2, (-7*2-1), %o2 - - 9: -Lend_regular_divide: - subcc %o4, 1, %o4 - bge Ldivloop - tst %o3 - - bl,a Lgot_result - ! non-restoring fixup here (one instruction only!) - add %o3, %o1, %o3 - -Lgot_result: - - retl - mov %o3, %o0 - - .globl .urem_patch -.urem_patch: - wr %g0, 0x0, %y - nop - nop - nop - udiv %o0, %o1, %o2 - umul %o2, %o1, %o2 - retl - sub %o0, %o2, %o0 diff --git a/arch/sparc/lib/xor.S b/arch/sparc/lib/xor.S index f44f58f40234..2c05641c3263 100644 --- a/arch/sparc/lib/xor.S +++ b/arch/sparc/lib/xor.S @@ -8,6 +8,7 @@ * Copyright (C) 2006 David S. Miller <[email protected]> */ +#include <linux/linkage.h> #include <asm/visasm.h> #include <asm/asi.h> #include <asm/dcu.h> @@ -19,12 +20,9 @@ * !(len & 127) && len >= 256 */ .text - .align 32 /* VIS versions. */ - .globl xor_vis_2 - .type xor_vis_2,#function -xor_vis_2: +ENTRY(xor_vis_2) rd %fprs, %o5 andcc %o5, FPRS_FEF|FPRS_DU, %g0 be,pt %icc, 0f @@ -91,11 +89,9 @@ xor_vis_2: wr %g1, %g0, %asi retl wr %g0, 0, %fprs - .size xor_vis_2, .-xor_vis_2 +ENDPROC(xor_vis_2) - .globl xor_vis_3 - .type xor_vis_3,#function -xor_vis_3: +ENTRY(xor_vis_3) rd %fprs, %o5 andcc %o5, FPRS_FEF|FPRS_DU, %g0 be,pt %icc, 0f @@ -159,11 +155,9 @@ xor_vis_3: wr %g1, %g0, %asi retl wr %g0, 0, %fprs - .size xor_vis_3, .-xor_vis_3 +ENDPROC(xor_vis_3) - .globl xor_vis_4 - .type xor_vis_4,#function -xor_vis_4: +ENTRY(xor_vis_4) rd %fprs, %o5 andcc %o5, FPRS_FEF|FPRS_DU, %g0 be,pt %icc, 0f @@ -246,11 +240,9 @@ xor_vis_4: wr %g1, %g0, %asi retl wr %g0, 0, %fprs - .size xor_vis_4, .-xor_vis_4 +ENDPROC(xor_vis_4) - .globl xor_vis_5 - .type xor_vis_5,#function -xor_vis_5: +ENTRY(xor_vis_5) save %sp, -192, %sp rd %fprs, %o5 andcc %o5, FPRS_FEF|FPRS_DU, %g0 @@ -354,12 +346,10 @@ xor_vis_5: wr %g0, 0, %fprs ret restore - .size xor_vis_5, .-xor_vis_5 +ENDPROC(xor_vis_5) /* Niagara versions. */ - .globl xor_niagara_2 - .type xor_niagara_2,#function -xor_niagara_2: /* %o0=bytes, %o1=dest, %o2=src */ +ENTRY(xor_niagara_2) /* %o0=bytes, %o1=dest, %o2=src */ save %sp, -192, %sp prefetch [%i1], #n_writes prefetch [%i2], #one_read @@ -402,11 +392,9 @@ xor_niagara_2: /* %o0=bytes, %o1=dest, %o2=src */ wr %g7, 0x0, %asi ret restore - .size xor_niagara_2, .-xor_niagara_2 +ENDPROC(xor_niagara_2) - .globl xor_niagara_3 - .type xor_niagara_3,#function -xor_niagara_3: /* %o0=bytes, %o1=dest, %o2=src1, %o3=src2 */ +ENTRY(xor_niagara_3) /* %o0=bytes, %o1=dest, %o2=src1, %o3=src2 */ save %sp, -192, %sp prefetch [%i1], #n_writes prefetch [%i2], #one_read @@ -465,11 +453,9 @@ xor_niagara_3: /* %o0=bytes, %o1=dest, %o2=src1, %o3=src2 */ wr %g7, 0x0, %asi ret restore - .size xor_niagara_3, .-xor_niagara_3 +ENDPROC(xor_niagara_3) - .globl xor_niagara_4 - .type xor_niagara_4,#function -xor_niagara_4: /* %o0=bytes, %o1=dest, %o2=src1, %o3=src2, %o4=src3 */ +ENTRY(xor_niagara_4) /* %o0=bytes, %o1=dest, %o2=src1, %o3=src2, %o4=src3 */ save %sp, -192, %sp prefetch [%i1], #n_writes prefetch [%i2], #one_read @@ -549,11 +535,9 @@ xor_niagara_4: /* %o0=bytes, %o1=dest, %o2=src1, %o3=src2, %o4=src3 */ wr %g7, 0x0, %asi ret restore - .size xor_niagara_4, .-xor_niagara_4 +ENDPROC(xor_niagara_4) - .globl xor_niagara_5 - .type xor_niagara_5,#function -xor_niagara_5: /* %o0=bytes, %o1=dest, %o2=src1, %o3=src2, %o4=src3, %o5=src4 */ +ENTRY(xor_niagara_5) /* %o0=bytes, %o1=dest, %o2=src1, %o3=src2, %o4=src3, %o5=src4 */ save %sp, -192, %sp prefetch [%i1], #n_writes prefetch [%i2], #one_read @@ -649,4 +633,4 @@ xor_niagara_5: /* %o0=bytes, %o1=dest, %o2=src1, %o3=src2, %o4=src3, %o5=src4 * wr %g7, 0x0, %asi ret restore - .size xor_niagara_5, .-xor_niagara_5 +ENDPROC(xor_niagara_5) diff --git a/arch/sparc/mm/Makefile b/arch/sparc/mm/Makefile index 301421c11291..69ffd3112fed 100644 --- a/arch/sparc/mm/Makefile +++ b/arch/sparc/mm/Makefile @@ -7,8 +7,7 @@ ccflags-y := -Werror obj-$(CONFIG_SPARC64) += ultra.o tlb.o tsb.o gup.o obj-y += fault_$(BITS).o obj-y += init_$(BITS).o -obj-$(CONFIG_SPARC32) += loadmmu.o -obj-$(CONFIG_SPARC32) += extable.o btfixup.o srmmu.o iommu.o io-unit.o +obj-$(CONFIG_SPARC32) += extable.o srmmu.o iommu.o io-unit.o obj-$(CONFIG_SPARC32) += hypersparc.o viking.o tsunami.o swift.o obj-$(CONFIG_SPARC_LEON)+= leon_mm.o @@ -17,9 +16,3 @@ obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o # Only used by sparc32 obj-$(CONFIG_HIGHMEM) += highmem.o - -ifdef CONFIG_SMP -obj-$(CONFIG_SPARC32) += nosun4c.o -else -obj-$(CONFIG_SPARC32) += sun4c.o -endif diff --git a/arch/sparc/mm/btfixup.c b/arch/sparc/mm/btfixup.c deleted file mode 100644 index 09d6af22db2d..000000000000 --- a/arch/sparc/mm/btfixup.c +++ /dev/null @@ -1,328 +0,0 @@ -/* btfixup.c: Boot time code fixup and relocator, so that - * we can get rid of most indirect calls to achieve single - * image sun4c and srmmu kernel. - * - * Copyright (C) 1998 Jakub Jelinek ([email protected]) - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <asm/btfixup.h> -#include <asm/page.h> -#include <asm/pgalloc.h> -#include <asm/pgtable.h> -#include <asm/oplib.h> -#include <asm/cacheflush.h> - -#define BTFIXUP_OPTIMIZE_NOP -#define BTFIXUP_OPTIMIZE_OTHER - -extern char *srmmu_name; -static char version[] __initdata = "Boot time fixup v1.6. 4/Mar/98 Jakub Jelinek ([email protected]). Patching kernel for "; -static char str_sun4c[] __initdata = "sun4c\n"; -static char str_srmmu[] __initdata = "srmmu[%s]/"; -static char str_iommu[] __initdata = "iommu\n"; -static char str_iounit[] __initdata = "io-unit\n"; - -static int visited __initdata = 0; -extern unsigned int ___btfixup_start[], ___btfixup_end[], __init_begin[], __init_end[], __init_text_end[]; -extern unsigned int _stext[], _end[], __start___ksymtab[], __stop___ksymtab[]; -static char wrong_f[] __initdata = "Trying to set f fixup %p to invalid function %08x\n"; -static char wrong_b[] __initdata = "Trying to set b fixup %p to invalid function %08x\n"; -static char wrong_s[] __initdata = "Trying to set s fixup %p to invalid value %08x\n"; -static char wrong_h[] __initdata = "Trying to set h fixup %p to invalid value %08x\n"; -static char wrong_a[] __initdata = "Trying to set a fixup %p to invalid value %08x\n"; -static char wrong[] __initdata = "Wrong address for %c fixup %p\n"; -static char insn_f[] __initdata = "Fixup f %p refers to weird instructions at %p[%08x,%08x]\n"; -static char insn_b[] __initdata = "Fixup b %p doesn't refer to a SETHI at %p[%08x]\n"; -static char insn_s[] __initdata = "Fixup s %p doesn't refer to an OR at %p[%08x]\n"; -static char insn_h[] __initdata = "Fixup h %p doesn't refer to a SETHI at %p[%08x]\n"; -static char insn_a[] __initdata = "Fixup a %p doesn't refer to a SETHI nor OR at %p[%08x]\n"; -static char insn_i[] __initdata = "Fixup i %p doesn't refer to a valid instruction at %p[%08x]\n"; -static char fca_und[] __initdata = "flush_cache_all undefined in btfixup()\n"; -static char wrong_setaddr[] __initdata = "Garbled CALL/INT patch at %p[%08x,%08x,%08x]=%08x\n"; - -#ifdef BTFIXUP_OPTIMIZE_OTHER -static void __init set_addr(unsigned int *addr, unsigned int q1, int fmangled, unsigned int value) -{ - if (!fmangled) - *addr = value; - else { - unsigned int *q = (unsigned int *)q1; - if (*addr == 0x01000000) { - /* Noped */ - *q = value; - } else if (addr[-1] == *q) { - /* Moved */ - addr[-1] = value; - *q = value; - } else { - prom_printf(wrong_setaddr, addr-1, addr[-1], *addr, *q, value); - prom_halt(); - } - } -} -#else -static inline void set_addr(unsigned int *addr, unsigned int q1, int fmangled, unsigned int value) -{ - *addr = value; -} -#endif - -void __init btfixup(void) -{ - unsigned int *p, *q; - int type, count; - unsigned insn; - unsigned *addr; - int fmangled = 0; - void (*flush_cacheall)(void); - - if (!visited) { - visited++; - printk(version); - if (ARCH_SUN4C) - printk(str_sun4c); - else { - printk(str_srmmu, srmmu_name); - if (sparc_cpu_model == sun4d) - printk(str_iounit); - else - printk(str_iommu); - } - } - for (p = ___btfixup_start; p < ___btfixup_end; ) { - count = p[2]; - q = p + 3; - switch (type = *(unsigned char *)p) { - case 'f': - count = p[3]; - q = p + 4; - if (((p[0] & 1) || p[1]) - && ((p[1] & 3) || (unsigned *)(p[1]) < _stext || (unsigned *)(p[1]) >= _end)) { - prom_printf(wrong_f, p, p[1]); - prom_halt(); - } - break; - case 'b': - if (p[1] < (unsigned long)__init_begin || p[1] >= (unsigned long)__init_text_end || (p[1] & 3)) { - prom_printf(wrong_b, p, p[1]); - prom_halt(); - } - break; - case 's': - if (p[1] + 0x1000 >= 0x2000) { - prom_printf(wrong_s, p, p[1]); - prom_halt(); - } - break; - case 'h': - if (p[1] & 0x3ff) { - prom_printf(wrong_h, p, p[1]); - prom_halt(); - } - break; - case 'a': - if (p[1] + 0x1000 >= 0x2000 && (p[1] & 0x3ff)) { - prom_printf(wrong_a, p, p[1]); - prom_halt(); - } - break; - } - if (p[0] & 1) { - p[0] &= ~1; - while (count) { - fmangled = 0; - addr = (unsigned *)*q; - if (addr < _stext || addr >= _end) { - prom_printf(wrong, type, p); - prom_halt(); - } - insn = *addr; -#ifdef BTFIXUP_OPTIMIZE_OTHER - if (type != 'f' && q[1]) { - insn = *(unsigned int *)q[1]; - if (!insn || insn == 1) - insn = *addr; - else - fmangled = 1; - } -#endif - switch (type) { - case 'f': /* CALL */ - if (addr >= __start___ksymtab && addr < __stop___ksymtab) { - *addr = p[1]; - break; - } else if (!q[1]) { - if ((insn & 0xc1c00000) == 0x01000000) { /* SETHI */ - *addr = (insn & 0xffc00000) | (p[1] >> 10); break; - } else if ((insn & 0xc1f82000) == 0x80102000) { /* OR X, %LO(i), Y */ - *addr = (insn & 0xffffe000) | (p[1] & 0x3ff); break; - } else if ((insn & 0xc0000000) != 0x40000000) { /* !CALL */ - bad_f: - prom_printf(insn_f, p, addr, insn, addr[1]); - prom_halt(); - } - } else if (q[1] != 1) - addr[1] = q[1]; - if (p[2] == BTFIXUPCALL_NORM) { - norm_f: - *addr = 0x40000000 | ((p[1] - (unsigned)addr) >> 2); - q[1] = 0; - break; - } -#ifndef BTFIXUP_OPTIMIZE_NOP - goto norm_f; -#else - if (!(addr[1] & 0x80000000)) { - if ((addr[1] & 0xc1c00000) != 0x01000000) /* !SETHI */ - goto bad_f; /* CALL, Bicc, FBfcc, CBccc are weird in delay slot, aren't they? */ - } else { - if ((addr[1] & 0x01800000) == 0x01800000) { - if ((addr[1] & 0x01f80000) == 0x01e80000) { - /* RESTORE */ - goto norm_f; /* It is dangerous to patch that */ - } - goto bad_f; - } - if ((addr[1] & 0xffffe003) == 0x9e03e000) { - /* ADD %O7, XX, %o7 */ - int displac = (addr[1] << 19); - - displac = (displac >> 21) + 2; - *addr = (0x10800000) + (displac & 0x3fffff); - q[1] = addr[1]; - addr[1] = p[2]; - break; - } - if ((addr[1] & 0x201f) == 0x200f || (addr[1] & 0x7c000) == 0x3c000) - goto norm_f; /* Someone is playing bad tricks with us: rs1 or rs2 is o7 */ - if ((addr[1] & 0x3e000000) == 0x1e000000) - goto norm_f; /* rd is %o7. We'd better take care. */ - } - if (p[2] == BTFIXUPCALL_NOP) { - *addr = 0x01000000; - q[1] = 1; - break; - } -#ifndef BTFIXUP_OPTIMIZE_OTHER - goto norm_f; -#else - if (addr[1] == 0x01000000) { /* NOP in the delay slot */ - q[1] = addr[1]; - *addr = p[2]; - break; - } - if ((addr[1] & 0xc0000000) != 0xc0000000) { - /* Not a memory operation */ - if ((addr[1] & 0x30000000) == 0x10000000) { - /* Ok, non-memory op with rd %oX */ - if ((addr[1] & 0x3e000000) == 0x1c000000) - goto bad_f; /* Aiee. Someone is playing strange %sp tricks */ - if ((addr[1] & 0x3e000000) > 0x12000000 || - ((addr[1] & 0x3e000000) == 0x12000000 && - p[2] != BTFIXUPCALL_STO1O0 && p[2] != BTFIXUPCALL_SWAPO0O1) || - ((p[2] & 0xffffe000) == BTFIXUPCALL_RETINT(0))) { - /* Nobody uses the result. We can nop it out. */ - *addr = p[2]; - q[1] = addr[1]; - addr[1] = 0x01000000; - break; - } - if ((addr[1] & 0xf1ffffe0) == 0x90100000) { - /* MOV %reg, %Ox */ - if ((addr[1] & 0x3e000000) == 0x10000000 && - (p[2] & 0x7c000) == 0x20000) { - /* Ok, it is call xx; mov reg, %o0 and call optimizes - to doing something on %o0. Patch the patch. */ - *addr = (p[2] & ~0x7c000) | ((addr[1] & 0x1f) << 14); - q[1] = addr[1]; - addr[1] = 0x01000000; - break; - } - if ((addr[1] & 0x3e000000) == 0x12000000 && - p[2] == BTFIXUPCALL_STO1O0) { - *addr = (p[2] & ~0x3e000000) | ((addr[1] & 0x1f) << 25); - q[1] = addr[1]; - addr[1] = 0x01000000; - break; - } - } - } - } - *addr = addr[1]; - q[1] = addr[1]; - addr[1] = p[2]; - break; -#endif /* BTFIXUP_OPTIMIZE_OTHER */ -#endif /* BTFIXUP_OPTIMIZE_NOP */ - case 'b': /* BLACKBOX */ - /* Has to be sethi i, xx */ - if ((insn & 0xc1c00000) != 0x01000000) { - prom_printf(insn_b, p, addr, insn); - prom_halt(); - } else { - void (*do_fixup)(unsigned *); - - do_fixup = (void (*)(unsigned *))p[1]; - do_fixup(addr); - } - break; - case 's': /* SIMM13 */ - /* Has to be or %g0, i, xx */ - if ((insn & 0xc1ffe000) != 0x80102000) { - prom_printf(insn_s, p, addr, insn); - prom_halt(); - } - set_addr(addr, q[1], fmangled, (insn & 0xffffe000) | (p[1] & 0x1fff)); - break; - case 'h': /* SETHI */ - /* Has to be sethi i, xx */ - if ((insn & 0xc1c00000) != 0x01000000) { - prom_printf(insn_h, p, addr, insn); - prom_halt(); - } - set_addr(addr, q[1], fmangled, (insn & 0xffc00000) | (p[1] >> 10)); - break; - case 'a': /* HALF */ - /* Has to be sethi i, xx or or %g0, i, xx */ - if ((insn & 0xc1c00000) != 0x01000000 && - (insn & 0xc1ffe000) != 0x80102000) { - prom_printf(insn_a, p, addr, insn); - prom_halt(); - } - if (p[1] & 0x3ff) - set_addr(addr, q[1], fmangled, - (insn & 0x3e000000) | 0x80102000 | (p[1] & 0x1fff)); - else - set_addr(addr, q[1], fmangled, - (insn & 0x3e000000) | 0x01000000 | (p[1] >> 10)); - break; - case 'i': /* INT */ - if ((insn & 0xc1c00000) == 0x01000000) /* %HI */ - set_addr(addr, q[1], fmangled, (insn & 0xffc00000) | (p[1] >> 10)); - else if ((insn & 0x80002000) == 0x80002000) /* %LO */ - set_addr(addr, q[1], fmangled, (insn & 0xffffe000) | (p[1] & 0x3ff)); - else { - prom_printf(insn_i, p, addr, insn); - prom_halt(); - } - break; - } - count -= 2; - q += 2; - } - } else - p = q + count; - } -#ifdef CONFIG_SMP - flush_cacheall = (void (*)(void))BTFIXUPVAL_CALL(local_flush_cache_all); -#else - flush_cacheall = (void (*)(void))BTFIXUPVAL_CALL(flush_cache_all); -#endif - if (!flush_cacheall) { - prom_printf(fca_und); - prom_halt(); - } - (*flush_cacheall)(); -} diff --git a/arch/sparc/mm/fault_32.c b/arch/sparc/mm/fault_32.c index df3155a17991..f46cf6be3370 100644 --- a/arch/sparc/mm/fault_32.c +++ b/arch/sparc/mm/fault_32.c @@ -24,29 +24,19 @@ #include <asm/page.h> #include <asm/pgtable.h> -#include <asm/memreg.h> #include <asm/openprom.h> #include <asm/oplib.h> #include <asm/smp.h> #include <asm/traps.h> #include <asm/uaccess.h> -extern int prom_node_root; - int show_unhandled_signals = 1; /* At boot time we determine these two values necessary for setting * up the segment maps and page table entries (pte's). */ -int num_segmaps, num_contexts; -int invalid_segment; - -/* various Virtual Address Cache parameters we find at boot time... */ - -int vac_size, vac_linesize, vac_do_hw_vac_flushes; -int vac_entries_per_context, vac_entries_per_segment; -int vac_entries_per_page; +int num_contexts; /* Return how much physical memory we have. */ unsigned long probe_memory(void) @@ -60,55 +50,36 @@ unsigned long probe_memory(void) return total; } -extern void sun4c_complete_all_stores(void); - -/* Whee, a level 15 NMI interrupt memory error. Let's have fun... */ -asmlinkage void sparc_lvl15_nmi(struct pt_regs *regs, unsigned long serr, - unsigned long svaddr, unsigned long aerr, - unsigned long avaddr) -{ - sun4c_complete_all_stores(); - printk("FAULT: NMI received\n"); - printk("SREGS: Synchronous Error %08lx\n", serr); - printk(" Synchronous Vaddr %08lx\n", svaddr); - printk(" Asynchronous Error %08lx\n", aerr); - printk(" Asynchronous Vaddr %08lx\n", avaddr); - if (sun4c_memerr_reg) - printk(" Memory Parity Error %08lx\n", *sun4c_memerr_reg); - printk("REGISTER DUMP:\n"); - show_regs(regs); - prom_halt(); -} - static void unhandled_fault(unsigned long, struct task_struct *, struct pt_regs *) __attribute__ ((noreturn)); -static void unhandled_fault(unsigned long address, struct task_struct *tsk, - struct pt_regs *regs) +static void __noreturn unhandled_fault(unsigned long address, + struct task_struct *tsk, + struct pt_regs *regs) { - if((unsigned long) address < PAGE_SIZE) { + if ((unsigned long) address < PAGE_SIZE) { printk(KERN_ALERT "Unable to handle kernel NULL pointer dereference\n"); } else { - printk(KERN_ALERT "Unable to handle kernel paging request " - "at virtual address %08lx\n", address); + printk(KERN_ALERT "Unable to handle kernel paging request at virtual address %08lx\n", + address); } printk(KERN_ALERT "tsk->{mm,active_mm}->context = %08lx\n", (tsk->mm ? tsk->mm->context : tsk->active_mm->context)); printk(KERN_ALERT "tsk->{mm,active_mm}->pgd = %08lx\n", (tsk->mm ? (unsigned long) tsk->mm->pgd : - (unsigned long) tsk->active_mm->pgd)); + (unsigned long) tsk->active_mm->pgd)); die_if_kernel("Oops", regs); } -asmlinkage int lookup_fault(unsigned long pc, unsigned long ret_pc, +asmlinkage int lookup_fault(unsigned long pc, unsigned long ret_pc, unsigned long address) { struct pt_regs regs; unsigned long g2; unsigned int insn; int i; - + i = search_extables_range(ret_pc, &g2); switch (i) { case 3: @@ -128,14 +99,14 @@ asmlinkage int lookup_fault(unsigned long pc, unsigned long ret_pc, /* for _from_ macros */ insn = *((unsigned int *) pc); if (!((insn >> 21) & 1) || ((insn>>19)&0x3f) == 15) - return 2; - break; + return 2; + break; default: break; } - memset(®s, 0, sizeof (regs)); + memset(®s, 0, sizeof(regs)); regs.pc = pc; regs.npc = pc + 4; __asm__ __volatile__( @@ -198,11 +169,10 @@ static unsigned long compute_si_addr(struct pt_regs *regs, int text_fault) if (text_fault) return regs->pc; - if (regs->psr & PSR_PS) { + if (regs->psr & PSR_PS) insn = *(unsigned int *) regs->pc; - } else { + else __get_user(insn, (unsigned int *) regs->pc); - } return safe_compute_effective_address(regs, insn); } @@ -228,7 +198,7 @@ asmlinkage void do_sparc_fault(struct pt_regs *regs, int text_fault, int write, unsigned int flags = (FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE | (write ? FAULT_FLAG_WRITE : 0)); - if(text_fault) + if (text_fault) address = regs->pc; /* @@ -241,36 +211,32 @@ asmlinkage void do_sparc_fault(struct pt_regs *regs, int text_fault, int write, * nothing more. */ code = SEGV_MAPERR; - if (!ARCH_SUN4C && address >= TASK_SIZE) + if (address >= TASK_SIZE) goto vmalloc_fault; /* * If we're in an interrupt or have no user * context, we must not take the fault.. */ - if (in_atomic() || !mm) - goto no_context; + if (in_atomic() || !mm) + goto no_context; perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, address); retry: down_read(&mm->mmap_sem); - /* - * The kernel referencing a bad kernel pointer can lock up - * a sun4c machine completely, so we must attempt recovery. - */ - if(!from_user && address >= PAGE_OFFSET) + if (!from_user && address >= PAGE_OFFSET) goto bad_area; vma = find_vma(mm, address); - if(!vma) + if (!vma) goto bad_area; - if(vma->vm_start <= address) + if (vma->vm_start <= address) goto good_area; - if(!(vma->vm_flags & VM_GROWSDOWN)) + if (!(vma->vm_flags & VM_GROWSDOWN)) goto bad_area; - if(expand_stack(vma, address)) + if (expand_stack(vma, address)) goto bad_area; /* * Ok, we have a good vm_area for this memory access, so @@ -278,12 +244,12 @@ retry: */ good_area: code = SEGV_ACCERR; - if(write) { - if(!(vma->vm_flags & VM_WRITE)) + if (write) { + if (!(vma->vm_flags & VM_WRITE)) goto bad_area; } else { /* Allow reads even for write-only mappings */ - if(!(vma->vm_flags & (VM_READ | VM_EXEC))) + if (!(vma->vm_flags & (VM_READ | VM_EXEC))) goto bad_area; } @@ -349,14 +315,16 @@ no_context: g2 = regs->u_regs[UREG_G2]; if (!from_user) { fixup = search_extables_range(regs->pc, &g2); - if (fixup > 10) { /* Values below are reserved for other things */ + /* Values below 10 are reserved for other things */ + if (fixup > 10) { extern const unsigned __memset_start[]; extern const unsigned __memset_end[]; extern const unsigned __csum_partial_copy_start[]; extern const unsigned __csum_partial_copy_end[]; #ifdef DEBUG_EXCEPTIONS - printk("Exception: PC<%08lx> faddr<%08lx>\n", regs->pc, address); + printk("Exception: PC<%08lx> faddr<%08lx>\n", + regs->pc, address); printk("EX_TABLE: insn<%08lx> fixup<%08x> g2<%08lx>\n", regs->pc, fixup, g2); #endif @@ -364,7 +332,7 @@ no_context: regs->pc < (unsigned long)__memset_end) || (regs->pc >= (unsigned long)__csum_partial_copy_start && regs->pc < (unsigned long)__csum_partial_copy_end)) { - regs->u_regs[UREG_I4] = address; + regs->u_regs[UREG_I4] = address; regs->u_regs[UREG_I5] = regs->pc; } regs->u_regs[UREG_G2] = g2; @@ -373,8 +341,8 @@ no_context: return; } } - - unhandled_fault (address, tsk, regs); + + unhandled_fault(address, tsk, regs); do_exit(SIGKILL); /* @@ -420,97 +388,12 @@ vmalloc_fault: if (pmd_present(*pmd) || !pmd_present(*pmd_k)) goto bad_area_nosemaphore; + *pmd = *pmd_k; return; } } -asmlinkage void do_sun4c_fault(struct pt_regs *regs, int text_fault, int write, - unsigned long address) -{ - extern void sun4c_update_mmu_cache(struct vm_area_struct *, - unsigned long,pte_t *); - extern pte_t *sun4c_pte_offset_kernel(pmd_t *,unsigned long); - struct task_struct *tsk = current; - struct mm_struct *mm = tsk->mm; - pgd_t *pgdp; - pte_t *ptep; - - if (text_fault) { - address = regs->pc; - } else if (!write && - !(regs->psr & PSR_PS)) { - unsigned int insn, __user *ip; - - ip = (unsigned int __user *)regs->pc; - if (!get_user(insn, ip)) { - if ((insn & 0xc1680000) == 0xc0680000) - write = 1; - } - } - - if (!mm) { - /* We are oopsing. */ - do_sparc_fault(regs, text_fault, write, address); - BUG(); /* P3 Oops already, you bitch */ - } - - pgdp = pgd_offset(mm, address); - ptep = sun4c_pte_offset_kernel((pmd_t *) pgdp, address); - - if (pgd_val(*pgdp)) { - if (write) { - if ((pte_val(*ptep) & (_SUN4C_PAGE_WRITE|_SUN4C_PAGE_PRESENT)) - == (_SUN4C_PAGE_WRITE|_SUN4C_PAGE_PRESENT)) { - unsigned long flags; - - *ptep = __pte(pte_val(*ptep) | _SUN4C_PAGE_ACCESSED | - _SUN4C_PAGE_MODIFIED | - _SUN4C_PAGE_VALID | - _SUN4C_PAGE_DIRTY); - - local_irq_save(flags); - if (sun4c_get_segmap(address) != invalid_segment) { - sun4c_put_pte(address, pte_val(*ptep)); - local_irq_restore(flags); - return; - } - local_irq_restore(flags); - } - } else { - if ((pte_val(*ptep) & (_SUN4C_PAGE_READ|_SUN4C_PAGE_PRESENT)) - == (_SUN4C_PAGE_READ|_SUN4C_PAGE_PRESENT)) { - unsigned long flags; - - *ptep = __pte(pte_val(*ptep) | _SUN4C_PAGE_ACCESSED | - _SUN4C_PAGE_VALID); - - local_irq_save(flags); - if (sun4c_get_segmap(address) != invalid_segment) { - sun4c_put_pte(address, pte_val(*ptep)); - local_irq_restore(flags); - return; - } - local_irq_restore(flags); - } - } - } - - /* This conditional is 'interesting'. */ - if (pgd_val(*pgdp) && !(write && !(pte_val(*ptep) & _SUN4C_PAGE_WRITE)) - && (pte_val(*ptep) & _SUN4C_PAGE_VALID)) - /* Note: It is safe to not grab the MMAP semaphore here because - * we know that update_mmu_cache() will not sleep for - * any reason (at least not in the current implementation) - * and therefore there is no danger of another thread getting - * on the CPU and doing a shrink_mmap() on this vma. - */ - sun4c_update_mmu_cache (find_vma(current->mm, address), address, - ptep); - else - do_sparc_fault(regs, text_fault, write, address); -} - /* This always deals with user addresses. */ static void force_user_fault(unsigned long address, int write) { @@ -523,21 +406,21 @@ static void force_user_fault(unsigned long address, int write) down_read(&mm->mmap_sem); vma = find_vma(mm, address); - if(!vma) + if (!vma) goto bad_area; - if(vma->vm_start <= address) + if (vma->vm_start <= address) goto good_area; - if(!(vma->vm_flags & VM_GROWSDOWN)) + if (!(vma->vm_flags & VM_GROWSDOWN)) goto bad_area; - if(expand_stack(vma, address)) + if (expand_stack(vma, address)) goto bad_area; good_area: code = SEGV_ACCERR; - if(write) { - if(!(vma->vm_flags & VM_WRITE)) + if (write) { + if (!(vma->vm_flags & VM_WRITE)) goto bad_area; } else { - if(!(vma->vm_flags & (VM_READ | VM_EXEC))) + if (!(vma->vm_flags & (VM_READ | VM_EXEC))) goto bad_area; } switch (handle_mm_fault(mm, vma, address, write ? FAULT_FLAG_WRITE : 0)) { @@ -568,7 +451,7 @@ void window_overflow_fault(void) unsigned long sp; sp = current_thread_info()->rwbuf_stkptrs[0]; - if(((sp + 0x38) & PAGE_MASK) != (sp & PAGE_MASK)) + if (((sp + 0x38) & PAGE_MASK) != (sp & PAGE_MASK)) force_user_fault(sp + 0x38, 1); force_user_fault(sp, 1); @@ -577,7 +460,7 @@ void window_overflow_fault(void) void window_underflow_fault(unsigned long sp) { - if(((sp + 0x38) & PAGE_MASK) != (sp & PAGE_MASK)) + if (((sp + 0x38) & PAGE_MASK) != (sp & PAGE_MASK)) force_user_fault(sp + 0x38, 0); force_user_fault(sp, 0); @@ -589,7 +472,7 @@ void window_ret_fault(struct pt_regs *regs) unsigned long sp; sp = regs->u_regs[UREG_FP]; - if(((sp + 0x38) & PAGE_MASK) != (sp & PAGE_MASK)) + if (((sp + 0x38) & PAGE_MASK) != (sp & PAGE_MASK)) force_user_fault(sp + 0x38, 0); force_user_fault(sp, 0); diff --git a/arch/sparc/mm/init_32.c b/arch/sparc/mm/init_32.c index c5f9021b1a01..ef5c779ec855 100644 --- a/arch/sparc/mm/init_32.c +++ b/arch/sparc/mm/init_32.c @@ -27,7 +27,6 @@ #include <linux/gfp.h> #include <asm/sections.h> -#include <asm/vac-ops.h> #include <asm/page.h> #include <asm/pgtable.h> #include <asm/vaddrs.h> @@ -45,9 +44,6 @@ EXPORT_SYMBOL(phys_base); unsigned long pfn_base; EXPORT_SYMBOL(pfn_base); -unsigned long page_kernel; -EXPORT_SYMBOL(page_kernel); - struct sparc_phys_banks sp_banks[SPARC_PHYS_BANKS+1]; unsigned long sparc_unmapped_base; @@ -287,44 +283,16 @@ unsigned long __init bootmem_init(unsigned long *pages_avail) } /* - * check_pgt_cache - * - * This is called at the end of unmapping of VMA (zap_page_range), - * to rescan the page cache for architecture specific things, - * presumably something like sun4/sun4c PMEGs. Most architectures - * define check_pgt_cache empty. - * - * We simply copy the 2.4 implementation for now. - */ -static int pgt_cache_water[2] = { 25, 50 }; - -void check_pgt_cache(void) -{ - do_check_pgt_cache(pgt_cache_water[0], pgt_cache_water[1]); -} - -/* * paging_init() sets up the page tables: We call the MMU specific * init routine based upon the Sun model type on the Sparc. * */ -extern void sun4c_paging_init(void); extern void srmmu_paging_init(void); extern void device_scan(void); -pgprot_t PAGE_SHARED __read_mostly; -EXPORT_SYMBOL(PAGE_SHARED); - void __init paging_init(void) { switch(sparc_cpu_model) { - case sun4c: - case sun4e: - case sun4: - sun4c_paging_init(); - sparc_unmapped_base = 0xe0000000; - BTFIXUPSET_SETHI(sparc_unmapped_base, 0xe0000000); - break; case sparc_leon: leon_init(); /* fall through */ @@ -332,7 +300,6 @@ void __init paging_init(void) case sun4d: srmmu_paging_init(); sparc_unmapped_base = 0x50000000; - BTFIXUPSET_SETHI(sparc_unmapped_base, 0x50000000); break; default: prom_printf("paging_init: Cannot init paging on this Sparc\n"); @@ -341,24 +308,6 @@ void __init paging_init(void) prom_halt(); } - /* Initialize the protection map with non-constant, MMU dependent values. */ - protection_map[0] = PAGE_NONE; - protection_map[1] = PAGE_READONLY; - protection_map[2] = PAGE_COPY; - protection_map[3] = PAGE_COPY; - protection_map[4] = PAGE_READONLY; - protection_map[5] = PAGE_READONLY; - protection_map[6] = PAGE_COPY; - protection_map[7] = PAGE_COPY; - protection_map[8] = PAGE_NONE; - protection_map[9] = PAGE_READONLY; - protection_map[10] = PAGE_SHARED; - protection_map[11] = PAGE_SHARED; - protection_map[12] = PAGE_READONLY; - protection_map[13] = PAGE_READONLY; - protection_map[14] = PAGE_SHARED; - protection_map[15] = PAGE_SHARED; - btfixup(); prom_build_devicetree(); of_fill_in_cpu_data(); device_scan(); diff --git a/arch/sparc/mm/init_64.c b/arch/sparc/mm/init_64.c index 21faaeea85de..6026fdd1b2ed 100644 --- a/arch/sparc/mm/init_64.c +++ b/arch/sparc/mm/init_64.c @@ -741,7 +741,6 @@ static void __init find_ramdisk(unsigned long phys_base) struct node_mem_mask { unsigned long mask; unsigned long val; - unsigned long bootmem_paddr; }; static struct node_mem_mask node_masks[MAX_NUMNODES]; static int num_node_masks; @@ -806,12 +805,6 @@ static u64 memblock_nid_range(u64 start, u64 end, int *nid) return start; } -#else -static u64 memblock_nid_range(u64 start, u64 end, int *nid) -{ - *nid = 0; - return end; -} #endif /* This must be invoked after performing all of the necessary @@ -820,10 +813,11 @@ static u64 memblock_nid_range(u64 start, u64 end, int *nid) */ static void __init allocate_node_data(int nid) { - unsigned long paddr, num_pages, start_pfn, end_pfn; struct pglist_data *p; - + unsigned long start_pfn, end_pfn; #ifdef CONFIG_NEED_MULTIPLE_NODES + unsigned long paddr; + paddr = memblock_alloc_try_nid(sizeof(struct pglist_data), SMP_CACHE_BYTES, nid); if (!paddr) { prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid); @@ -832,7 +826,7 @@ static void __init allocate_node_data(int nid) NODE_DATA(nid) = __va(paddr); memset(NODE_DATA(nid), 0, sizeof(struct pglist_data)); - NODE_DATA(nid)->bdata = &bootmem_node_data[nid]; + NODE_DATA(nid)->node_id = nid; #endif p = NODE_DATA(nid); @@ -840,18 +834,6 @@ static void __init allocate_node_data(int nid) get_pfn_range_for_nid(nid, &start_pfn, &end_pfn); p->node_start_pfn = start_pfn; p->node_spanned_pages = end_pfn - start_pfn; - - if (p->node_spanned_pages) { - num_pages = bootmem_bootmap_pages(p->node_spanned_pages); - - paddr = memblock_alloc_try_nid(num_pages << PAGE_SHIFT, PAGE_SIZE, nid); - if (!paddr) { - prom_printf("Cannot allocate bootmap for nid[%d]\n", - nid); - prom_halt(); - } - node_masks[nid].bootmem_paddr = paddr; - } } static void init_node_masks_nonnuma(void) @@ -1292,75 +1274,9 @@ static void __init bootmem_init_nonnuma(void) node_set_online(0); } -static void __init reserve_range_in_node(int nid, unsigned long start, - unsigned long end) -{ - numadbg(" reserve_range_in_node(nid[%d],start[%lx],end[%lx]\n", - nid, start, end); - while (start < end) { - unsigned long this_end; - int n; - - this_end = memblock_nid_range(start, end, &n); - if (n == nid) { - numadbg(" MATCH reserving range [%lx:%lx]\n", - start, this_end); - reserve_bootmem_node(NODE_DATA(nid), start, - (this_end - start), BOOTMEM_DEFAULT); - } else - numadbg(" NO MATCH, advancing start to %lx\n", - this_end); - - start = this_end; - } -} - -static void __init trim_reserved_in_node(int nid) -{ - struct memblock_region *reg; - - numadbg(" trim_reserved_in_node(%d)\n", nid); - - for_each_memblock(reserved, reg) - reserve_range_in_node(nid, reg->base, reg->base + reg->size); -} - -static void __init bootmem_init_one_node(int nid) -{ - struct pglist_data *p; - - numadbg("bootmem_init_one_node(%d)\n", nid); - - p = NODE_DATA(nid); - - if (p->node_spanned_pages) { - unsigned long paddr = node_masks[nid].bootmem_paddr; - unsigned long end_pfn; - - end_pfn = p->node_start_pfn + p->node_spanned_pages; - - numadbg(" init_bootmem_node(%d, %lx, %lx, %lx)\n", - nid, paddr >> PAGE_SHIFT, p->node_start_pfn, end_pfn); - - init_bootmem_node(p, paddr >> PAGE_SHIFT, - p->node_start_pfn, end_pfn); - - numadbg(" free_bootmem_with_active_regions(%d, %lx)\n", - nid, end_pfn); - free_bootmem_with_active_regions(nid, end_pfn); - - trim_reserved_in_node(nid); - - numadbg(" sparse_memory_present_with_active_regions(%d)\n", - nid); - sparse_memory_present_with_active_regions(nid); - } -} - static unsigned long __init bootmem_init(unsigned long phys_base) { unsigned long end_pfn; - int nid; end_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT; max_pfn = max_low_pfn = end_pfn; @@ -1369,11 +1285,12 @@ static unsigned long __init bootmem_init(unsigned long phys_base) if (bootmem_init_numa() < 0) bootmem_init_nonnuma(); - /* XXX cpu notifier XXX */ + /* Dump memblock with node info. */ + memblock_dump_all(); - for_each_online_node(nid) - bootmem_init_one_node(nid); + /* XXX cpu notifier XXX */ + sparse_memory_present_with_active_regions(MAX_NUMNODES); sparse_init(); return end_pfn; @@ -1701,6 +1618,7 @@ void __init paging_init(void) { unsigned long end_pfn, shift, phys_base; unsigned long real_end, i; + int node; /* These build time checkes make sure that the dcache_dirty_cpu() * page->flags usage will work. @@ -1826,22 +1744,24 @@ void __init paging_init(void) #endif } + /* Setup bootmem... */ + last_valid_pfn = end_pfn = bootmem_init(phys_base); + /* Once the OF device tree and MDESC have been setup, we know * the list of possible cpus. Therefore we can allocate the * IRQ stacks. */ for_each_possible_cpu(i) { - /* XXX Use node local allocations... XXX */ - softirq_stack[i] = __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); - hardirq_stack[i] = __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); - } + node = cpu_to_node(i); - /* Setup bootmem... */ - last_valid_pfn = end_pfn = bootmem_init(phys_base); + softirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node), + THREAD_SIZE, + THREAD_SIZE, 0); + hardirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node), + THREAD_SIZE, + THREAD_SIZE, 0); + } -#ifndef CONFIG_NEED_MULTIPLE_NODES - max_mapnr = last_valid_pfn; -#endif kernel_physical_mapping_init(); { @@ -1973,6 +1893,7 @@ void __init mem_init(void) free_all_bootmem_node(NODE_DATA(i)); } } + totalram_pages += free_low_memory_core_early(MAX_NUMNODES); } #else totalram_pages = free_all_bootmem(); diff --git a/arch/sparc/mm/io-unit.c b/arch/sparc/mm/io-unit.c index fc58c3e917df..eb99862e9654 100644 --- a/arch/sparc/mm/io-unit.c +++ b/arch/sparc/mm/io-unit.c @@ -197,7 +197,7 @@ static void iounit_release_scsi_sgl(struct device *dev, struct scatterlist *sg, } #ifdef CONFIG_SBUS -static int iounit_map_dma_area(struct device *dev, dma_addr_t *pba, unsigned long va, __u32 addr, int len) +static int iounit_map_dma_area(struct device *dev, dma_addr_t *pba, unsigned long va, unsigned long addr, int len) { struct iounit_struct *iounit = dev->archdata.iommu; unsigned long page, end; @@ -242,29 +242,18 @@ static void iounit_unmap_dma_area(struct device *dev, unsigned long addr, int le } #endif -static char *iounit_lockarea(char *vaddr, unsigned long len) -{ -/* FIXME: Write this */ - return vaddr; -} - -static void iounit_unlockarea(char *vaddr, unsigned long len) -{ -/* FIXME: Write this */ -} +static const struct sparc32_dma_ops iounit_dma_ops = { + .get_scsi_one = iounit_get_scsi_one, + .get_scsi_sgl = iounit_get_scsi_sgl, + .release_scsi_one = iounit_release_scsi_one, + .release_scsi_sgl = iounit_release_scsi_sgl, +#ifdef CONFIG_SBUS + .map_dma_area = iounit_map_dma_area, + .unmap_dma_area = iounit_unmap_dma_area, +#endif +}; void __init ld_mmu_iounit(void) { - BTFIXUPSET_CALL(mmu_lockarea, iounit_lockarea, BTFIXUPCALL_RETO0); - BTFIXUPSET_CALL(mmu_unlockarea, iounit_unlockarea, BTFIXUPCALL_NOP); - - BTFIXUPSET_CALL(mmu_get_scsi_one, iounit_get_scsi_one, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(mmu_get_scsi_sgl, iounit_get_scsi_sgl, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(mmu_release_scsi_one, iounit_release_scsi_one, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(mmu_release_scsi_sgl, iounit_release_scsi_sgl, BTFIXUPCALL_NORM); - -#ifdef CONFIG_SBUS - BTFIXUPSET_CALL(mmu_map_dma_area, iounit_map_dma_area, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(mmu_unmap_dma_area, iounit_unmap_dma_area, BTFIXUPCALL_NORM); -#endif + sparc32_dma_ops = &iounit_dma_ops; } diff --git a/arch/sparc/mm/iommu.c b/arch/sparc/mm/iommu.c index 07fc6a65d9b6..a8a58cad9d2b 100644 --- a/arch/sparc/mm/iommu.c +++ b/arch/sparc/mm/iommu.c @@ -39,8 +39,6 @@ /* srmmu.c */ extern int viking_mxcc_present; -BTFIXUPDEF_CALL(void, flush_page_for_dma, unsigned long) -#define flush_page_for_dma(page) BTFIXUP_CALL(flush_page_for_dma)(page) extern int flush_page_for_dma_global; static int viking_flush; /* viking.S */ @@ -143,7 +141,6 @@ static int __init iommu_init(void) subsys_initcall(iommu_init); -/* This begs to be btfixup-ed by srmmu. */ /* Flush the iotlb entries to ram. */ /* This could be better if we didn't have to flush whole pages. */ static void iommu_flush_iotlb(iopte_t *iopte, unsigned int niopte) @@ -216,11 +213,6 @@ static u32 iommu_get_scsi_one(struct device *dev, char *vaddr, unsigned int len) return busa + off; } -static __u32 iommu_get_scsi_one_noflush(struct device *dev, char *vaddr, unsigned long len) -{ - return iommu_get_scsi_one(dev, vaddr, len); -} - static __u32 iommu_get_scsi_one_gflush(struct device *dev, char *vaddr, unsigned long len) { flush_page_for_dma(0); @@ -238,19 +230,6 @@ static __u32 iommu_get_scsi_one_pflush(struct device *dev, char *vaddr, unsigned return iommu_get_scsi_one(dev, vaddr, len); } -static void iommu_get_scsi_sgl_noflush(struct device *dev, struct scatterlist *sg, int sz) -{ - int n; - - while (sz != 0) { - --sz; - n = (sg->length + sg->offset + PAGE_SIZE-1) >> PAGE_SHIFT; - sg->dma_address = iommu_get_one(dev, sg_page(sg), n) + sg->offset; - sg->dma_length = sg->length; - sg = sg_next(sg); - } -} - static void iommu_get_scsi_sgl_gflush(struct device *dev, struct scatterlist *sg, int sz) { int n; @@ -426,40 +405,36 @@ static void iommu_unmap_dma_area(struct device *dev, unsigned long busa, int len } #endif -static char *iommu_lockarea(char *vaddr, unsigned long len) -{ - return vaddr; -} +static const struct sparc32_dma_ops iommu_dma_gflush_ops = { + .get_scsi_one = iommu_get_scsi_one_gflush, + .get_scsi_sgl = iommu_get_scsi_sgl_gflush, + .release_scsi_one = iommu_release_scsi_one, + .release_scsi_sgl = iommu_release_scsi_sgl, +#ifdef CONFIG_SBUS + .map_dma_area = iommu_map_dma_area, + .unmap_dma_area = iommu_unmap_dma_area, +#endif +}; -static void iommu_unlockarea(char *vaddr, unsigned long len) -{ -} +static const struct sparc32_dma_ops iommu_dma_pflush_ops = { + .get_scsi_one = iommu_get_scsi_one_pflush, + .get_scsi_sgl = iommu_get_scsi_sgl_pflush, + .release_scsi_one = iommu_release_scsi_one, + .release_scsi_sgl = iommu_release_scsi_sgl, +#ifdef CONFIG_SBUS + .map_dma_area = iommu_map_dma_area, + .unmap_dma_area = iommu_unmap_dma_area, +#endif +}; void __init ld_mmu_iommu(void) { - viking_flush = (BTFIXUPVAL_CALL(flush_page_for_dma) == (unsigned long)viking_flush_page); - BTFIXUPSET_CALL(mmu_lockarea, iommu_lockarea, BTFIXUPCALL_RETO0); - BTFIXUPSET_CALL(mmu_unlockarea, iommu_unlockarea, BTFIXUPCALL_NOP); - - if (!BTFIXUPVAL_CALL(flush_page_for_dma)) { - /* IO coherent chip */ - BTFIXUPSET_CALL(mmu_get_scsi_one, iommu_get_scsi_one_noflush, BTFIXUPCALL_RETO0); - BTFIXUPSET_CALL(mmu_get_scsi_sgl, iommu_get_scsi_sgl_noflush, BTFIXUPCALL_NORM); - } else if (flush_page_for_dma_global) { + if (flush_page_for_dma_global) { /* flush_page_for_dma flushes everything, no matter of what page is it */ - BTFIXUPSET_CALL(mmu_get_scsi_one, iommu_get_scsi_one_gflush, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(mmu_get_scsi_sgl, iommu_get_scsi_sgl_gflush, BTFIXUPCALL_NORM); + sparc32_dma_ops = &iommu_dma_gflush_ops; } else { - BTFIXUPSET_CALL(mmu_get_scsi_one, iommu_get_scsi_one_pflush, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(mmu_get_scsi_sgl, iommu_get_scsi_sgl_pflush, BTFIXUPCALL_NORM); + sparc32_dma_ops = &iommu_dma_pflush_ops; } - BTFIXUPSET_CALL(mmu_release_scsi_one, iommu_release_scsi_one, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(mmu_release_scsi_sgl, iommu_release_scsi_sgl, BTFIXUPCALL_NORM); - -#ifdef CONFIG_SBUS - BTFIXUPSET_CALL(mmu_map_dma_area, iommu_map_dma_area, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(mmu_unmap_dma_area, iommu_unmap_dma_area, BTFIXUPCALL_NORM); -#endif if (viking_mxcc_present || srmmu_modtype == HyperSparc) { dvma_prot = __pgprot(SRMMU_CACHE | SRMMU_ET_PTE | SRMMU_PRIV); diff --git a/arch/sparc/mm/leon_mm.c b/arch/sparc/mm/leon_mm.c index 13c2169822a8..4c67ae6e5023 100644 --- a/arch/sparc/mm/leon_mm.c +++ b/arch/sparc/mm/leon_mm.c @@ -15,9 +15,23 @@ #include <asm/leon.h> #include <asm/tlbflush.h> +#include "srmmu.h" + int leon_flush_during_switch = 1; int srmmu_swprobe_trace; +static inline unsigned long leon_get_ctable_ptr(void) +{ + unsigned int retval; + + __asm__ __volatile__("lda [%1] %2, %0\n\t" : + "=r" (retval) : + "r" (SRMMU_CTXTBL_PTR), + "i" (ASI_LEON_MMUREGS)); + return (retval & SRMMU_CTX_PMASK) << 4; +} + + unsigned long srmmu_swprobe(unsigned long vaddr, unsigned long *paddr) { @@ -33,10 +47,10 @@ unsigned long srmmu_swprobe(unsigned long vaddr, unsigned long *paddr) if (srmmu_swprobe_trace) printk(KERN_INFO "swprobe: trace on\n"); - ctxtbl = srmmu_get_ctable_ptr(); + ctxtbl = leon_get_ctable_ptr(); if (!(ctxtbl)) { if (srmmu_swprobe_trace) - printk(KERN_INFO "swprobe: srmmu_get_ctable_ptr returned 0=>0\n"); + printk(KERN_INFO "swprobe: leon_get_ctable_ptr returned 0=>0\n"); return 0; } if (!_pfn_valid(PFN(ctxtbl))) { @@ -258,3 +272,80 @@ void leon_switch_mm(void) if (leon_flush_during_switch) leon_flush_cache_all(); } + +static void leon_flush_cache_mm(struct mm_struct *mm) +{ + leon_flush_cache_all(); +} + +static void leon_flush_cache_page(struct vm_area_struct *vma, unsigned long page) +{ + leon_flush_pcache_all(vma, page); +} + +static void leon_flush_cache_range(struct vm_area_struct *vma, + unsigned long start, + unsigned long end) +{ + leon_flush_cache_all(); +} + +static void leon_flush_tlb_mm(struct mm_struct *mm) +{ + leon_flush_tlb_all(); +} + +static void leon_flush_tlb_page(struct vm_area_struct *vma, + unsigned long page) +{ + leon_flush_tlb_all(); +} + +static void leon_flush_tlb_range(struct vm_area_struct *vma, + unsigned long start, + unsigned long end) +{ + leon_flush_tlb_all(); +} + +static void leon_flush_page_to_ram(unsigned long page) +{ + leon_flush_cache_all(); +} + +static void leon_flush_sig_insns(struct mm_struct *mm, unsigned long page) +{ + leon_flush_cache_all(); +} + +static void leon_flush_page_for_dma(unsigned long page) +{ + leon_flush_dcache_all(); +} + +void __init poke_leonsparc(void) +{ +} + +static const struct sparc32_cachetlb_ops leon_ops = { + .cache_all = leon_flush_cache_all, + .cache_mm = leon_flush_cache_mm, + .cache_page = leon_flush_cache_page, + .cache_range = leon_flush_cache_range, + .tlb_all = leon_flush_tlb_all, + .tlb_mm = leon_flush_tlb_mm, + .tlb_page = leon_flush_tlb_page, + .tlb_range = leon_flush_tlb_range, + .page_to_ram = leon_flush_page_to_ram, + .sig_insns = leon_flush_sig_insns, + .page_for_dma = leon_flush_page_for_dma, +}; + +void __init init_leon(void) +{ + srmmu_name = "LEON"; + sparc32_cachetlb_ops = &leon_ops; + poke_srmmu = poke_leonsparc; + + leon_flush_during_switch = leon_flush_needed(); +} diff --git a/arch/sparc/mm/loadmmu.c b/arch/sparc/mm/loadmmu.c deleted file mode 100644 index c5bf2a6c3858..000000000000 --- a/arch/sparc/mm/loadmmu.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * loadmmu.c: This code loads up all the mm function pointers once the - * machine type has been determined. It also sets the static - * mmu values such as PAGE_NONE, etc. - * - * Copyright (C) 1995 David S. Miller ([email protected]) - * Copyright (C) 1998 Jakub Jelinek ([email protected]) - */ - -#include <linux/kernel.h> -#include <linux/mm.h> -#include <linux/init.h> - -#include <asm/page.h> -#include <asm/pgtable.h> -#include <asm/mmu_context.h> -#include <asm/oplib.h> - -struct ctx_list *ctx_list_pool; -struct ctx_list ctx_free; -struct ctx_list ctx_used; - -extern void ld_mmu_sun4c(void); -extern void ld_mmu_srmmu(void); - -void __init load_mmu(void) -{ - switch(sparc_cpu_model) { - case sun4c: - case sun4: - ld_mmu_sun4c(); - break; - case sun4m: - case sun4d: - case sparc_leon: - ld_mmu_srmmu(); - break; - default: - prom_printf("load_mmu: %d unsupported\n", (int)sparc_cpu_model); - prom_halt(); - } - btfixup(); -} diff --git a/arch/sparc/mm/nosun4c.c b/arch/sparc/mm/nosun4c.c deleted file mode 100644 index 4e62c27147c4..000000000000 --- a/arch/sparc/mm/nosun4c.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * nosun4c.c: This file is a bunch of dummies for SMP compiles, - * so that it does not need sun4c and avoid ifdefs. - * - * Copyright (C) 1998 Jakub Jelinek ([email protected]) - */ - -#include <linux/kernel.h> -#include <linux/mm.h> -#include <linux/init.h> -#include <asm/pgtable.h> - -static char shouldnothappen[] __initdata = "32bit SMP kernel only supports sun4m and sun4d\n"; - -/* Dummies */ -struct sun4c_mmu_ring { - unsigned long xxx1[3]; - unsigned char xxx2[2]; - int xxx3; -}; -struct sun4c_mmu_ring sun4c_kernel_ring; -struct sun4c_mmu_ring sun4c_kfree_ring; -unsigned long sun4c_kernel_faults; -unsigned long *sun4c_memerr_reg; - -static void __init should_not_happen(void) -{ - prom_printf(shouldnothappen); - prom_halt(); -} - -unsigned long __init sun4c_paging_init(unsigned long start_mem, unsigned long end_mem) -{ - should_not_happen(); - return 0; -} - -void __init ld_mmu_sun4c(void) -{ - should_not_happen(); -} - -void sun4c_mapioaddr(unsigned long physaddr, unsigned long virt_addr, int bus_type, int rdonly) -{ -} - -void sun4c_unmapioaddr(unsigned long virt_addr) -{ -} - -void sun4c_complete_all_stores(void) -{ -} - -pte_t *sun4c_pte_offset(pmd_t * dir, unsigned long address) -{ - return NULL; -} - -pte_t *sun4c_pte_offset_kernel(pmd_t *dir, unsigned long address) -{ - return NULL; -} - -void sun4c_update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep) -{ -} - -void __init sun4c_probe_vac(void) -{ - should_not_happen(); -} - -void __init sun4c_probe_memerr_reg(void) -{ - should_not_happen(); -} diff --git a/arch/sparc/mm/srmmu.c b/arch/sparc/mm/srmmu.c index cbef74e793b8..8e97e0305b01 100644 --- a/arch/sparc/mm/srmmu.c +++ b/arch/sparc/mm/srmmu.c @@ -48,39 +48,37 @@ #include <asm/turbosparc.h> #include <asm/leon.h> -#include <asm/btfixup.h> +#include "srmmu.h" enum mbus_module srmmu_modtype; static unsigned int hwbug_bitmask; int vac_cache_size; int vac_line_size; +struct ctx_list *ctx_list_pool; +struct ctx_list ctx_free; +struct ctx_list ctx_used; + extern struct resource sparc_iomap; extern unsigned long last_valid_pfn; -extern unsigned long page_kernel; - static pgd_t *srmmu_swapper_pg_dir; +const struct sparc32_cachetlb_ops *sparc32_cachetlb_ops; + #ifdef CONFIG_SMP +const struct sparc32_cachetlb_ops *local_ops; + #define FLUSH_BEGIN(mm) #define FLUSH_END #else -#define FLUSH_BEGIN(mm) if((mm)->context != NO_CONTEXT) { +#define FLUSH_BEGIN(mm) if ((mm)->context != NO_CONTEXT) { #define FLUSH_END } #endif -BTFIXUPDEF_CALL(void, flush_page_for_dma, unsigned long) -#define flush_page_for_dma(page) BTFIXUP_CALL(flush_page_for_dma)(page) - int flush_page_for_dma_global = 1; -#ifdef CONFIG_SMP -BTFIXUPDEF_CALL(void, local_flush_page_for_dma, unsigned long) -#define local_flush_page_for_dma(page) BTFIXUP_CALL(local_flush_page_for_dma)(page) -#endif - char *srmmu_name; ctxd_t *srmmu_ctx_table_phys; @@ -91,28 +89,6 @@ static DEFINE_SPINLOCK(srmmu_context_spinlock); static int is_hypersparc; -/* - * In general all page table modifications should use the V8 atomic - * swap instruction. This insures the mmu and the cpu are in sync - * with respect to ref/mod bits in the page tables. - */ -static inline unsigned long srmmu_swap(unsigned long *addr, unsigned long value) -{ - __asm__ __volatile__("swap [%2], %0" : "=&r" (value) : "0" (value), "r" (addr)); - return value; -} - -static inline void srmmu_set_pte(pte_t *ptep, pte_t pteval) -{ - srmmu_swap((unsigned long *)ptep, pte_val(pteval)); -} - -/* The very generic SRMMU page table operations. */ -static inline int srmmu_device_memory(unsigned long x) -{ - return ((x & 0xF0000000) != 0); -} - static int srmmu_cache_pagetables; /* these will be initialized in srmmu_nocache_calcsize() */ @@ -129,145 +105,39 @@ void *srmmu_nocache_pool; void *srmmu_nocache_bitmap; static struct bit_map srmmu_nocache_map; -static unsigned long srmmu_pte_pfn(pte_t pte) -{ - if (srmmu_device_memory(pte_val(pte))) { - /* Just return something that will cause - * pfn_valid() to return false. This makes - * copy_one_pte() to just directly copy to - * PTE over. - */ - return ~0UL; - } - return (pte_val(pte) & SRMMU_PTE_PMASK) >> (PAGE_SHIFT-4); -} - -static struct page *srmmu_pmd_page(pmd_t pmd) -{ - - if (srmmu_device_memory(pmd_val(pmd))) - BUG(); - return pfn_to_page((pmd_val(pmd) & SRMMU_PTD_PMASK) >> (PAGE_SHIFT-4)); -} - -static inline unsigned long srmmu_pgd_page(pgd_t pgd) -{ return srmmu_device_memory(pgd_val(pgd))?~0:(unsigned long)__nocache_va((pgd_val(pgd) & SRMMU_PTD_PMASK) << 4); } - - -static inline int srmmu_pte_none(pte_t pte) -{ return !(pte_val(pte) & 0xFFFFFFF); } - -static inline int srmmu_pte_present(pte_t pte) -{ return ((pte_val(pte) & SRMMU_ET_MASK) == SRMMU_ET_PTE); } - -static inline void srmmu_pte_clear(pte_t *ptep) -{ srmmu_set_pte(ptep, __pte(0)); } - static inline int srmmu_pmd_none(pmd_t pmd) { return !(pmd_val(pmd) & 0xFFFFFFF); } -static inline int srmmu_pmd_bad(pmd_t pmd) -{ return (pmd_val(pmd) & SRMMU_ET_MASK) != SRMMU_ET_PTD; } - -static inline int srmmu_pmd_present(pmd_t pmd) -{ return ((pmd_val(pmd) & SRMMU_ET_MASK) == SRMMU_ET_PTD); } - -static inline void srmmu_pmd_clear(pmd_t *pmdp) { - int i; - for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++) - srmmu_set_pte((pte_t *)&pmdp->pmdv[i], __pte(0)); -} - -static inline int srmmu_pgd_none(pgd_t pgd) -{ return !(pgd_val(pgd) & 0xFFFFFFF); } - -static inline int srmmu_pgd_bad(pgd_t pgd) -{ return (pgd_val(pgd) & SRMMU_ET_MASK) != SRMMU_ET_PTD; } - -static inline int srmmu_pgd_present(pgd_t pgd) -{ return ((pgd_val(pgd) & SRMMU_ET_MASK) == SRMMU_ET_PTD); } - -static inline void srmmu_pgd_clear(pgd_t * pgdp) -{ srmmu_set_pte((pte_t *)pgdp, __pte(0)); } - -static inline pte_t srmmu_pte_wrprotect(pte_t pte) -{ return __pte(pte_val(pte) & ~SRMMU_WRITE);} - -static inline pte_t srmmu_pte_mkclean(pte_t pte) -{ return __pte(pte_val(pte) & ~SRMMU_DIRTY);} - -static inline pte_t srmmu_pte_mkold(pte_t pte) -{ return __pte(pte_val(pte) & ~SRMMU_REF);} - -static inline pte_t srmmu_pte_mkwrite(pte_t pte) -{ return __pte(pte_val(pte) | SRMMU_WRITE);} - -static inline pte_t srmmu_pte_mkdirty(pte_t pte) -{ return __pte(pte_val(pte) | SRMMU_DIRTY);} - -static inline pte_t srmmu_pte_mkyoung(pte_t pte) -{ return __pte(pte_val(pte) | SRMMU_REF);} - -/* - * Conversion functions: convert a page and protection to a page entry, - * and a page entry and page directory to the page they refer to. - */ -static pte_t srmmu_mk_pte(struct page *page, pgprot_t pgprot) -{ return __pte((page_to_pfn(page) << (PAGE_SHIFT-4)) | pgprot_val(pgprot)); } - -static pte_t srmmu_mk_pte_phys(unsigned long page, pgprot_t pgprot) -{ return __pte(((page) >> 4) | pgprot_val(pgprot)); } - -static pte_t srmmu_mk_pte_io(unsigned long page, pgprot_t pgprot, int space) -{ return __pte(((page) >> 4) | (space << 28) | pgprot_val(pgprot)); } - /* XXX should we hyper_flush_whole_icache here - Anton */ static inline void srmmu_ctxd_set(ctxd_t *ctxp, pgd_t *pgdp) -{ srmmu_set_pte((pte_t *)ctxp, (SRMMU_ET_PTD | (__nocache_pa((unsigned long) pgdp) >> 4))); } +{ set_pte((pte_t *)ctxp, (SRMMU_ET_PTD | (__nocache_pa((unsigned long) pgdp) >> 4))); } -static inline void srmmu_pgd_set(pgd_t * pgdp, pmd_t * pmdp) -{ srmmu_set_pte((pte_t *)pgdp, (SRMMU_ET_PTD | (__nocache_pa((unsigned long) pmdp) >> 4))); } - -static void srmmu_pmd_set(pmd_t *pmdp, pte_t *ptep) +void pmd_set(pmd_t *pmdp, pte_t *ptep) { unsigned long ptp; /* Physical address, shifted right by 4 */ int i; ptp = __nocache_pa((unsigned long) ptep) >> 4; for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++) { - srmmu_set_pte((pte_t *)&pmdp->pmdv[i], SRMMU_ET_PTD | ptp); + set_pte((pte_t *)&pmdp->pmdv[i], SRMMU_ET_PTD | ptp); ptp += (SRMMU_REAL_PTRS_PER_PTE*sizeof(pte_t) >> 4); } } -static void srmmu_pmd_populate(pmd_t *pmdp, struct page *ptep) +void pmd_populate(struct mm_struct *mm, pmd_t *pmdp, struct page *ptep) { unsigned long ptp; /* Physical address, shifted right by 4 */ int i; ptp = page_to_pfn(ptep) << (PAGE_SHIFT-4); /* watch for overflow */ for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++) { - srmmu_set_pte((pte_t *)&pmdp->pmdv[i], SRMMU_ET_PTD | ptp); + set_pte((pte_t *)&pmdp->pmdv[i], SRMMU_ET_PTD | ptp); ptp += (SRMMU_REAL_PTRS_PER_PTE*sizeof(pte_t) >> 4); } } -static inline pte_t srmmu_pte_modify(pte_t pte, pgprot_t newprot) -{ return __pte((pte_val(pte) & SRMMU_CHG_MASK) | pgprot_val(newprot)); } - -/* to find an entry in a top-level page table... */ -static inline pgd_t *srmmu_pgd_offset(struct mm_struct * mm, unsigned long address) -{ return mm->pgd + (address >> SRMMU_PGDIR_SHIFT); } - -/* Find an entry in the second-level page table.. */ -static inline pmd_t *srmmu_pmd_offset(pgd_t * dir, unsigned long address) -{ - return (pmd_t *) srmmu_pgd_page(*dir) + - ((address >> PMD_SHIFT) & (PTRS_PER_PMD - 1)); -} - /* Find an entry in the third-level page table.. */ -static inline pte_t *srmmu_pte_offset(pmd_t * dir, unsigned long address) +pte_t *pte_offset_kernel(pmd_t * dir, unsigned long address) { void *pte; @@ -276,23 +146,6 @@ static inline pte_t *srmmu_pte_offset(pmd_t * dir, unsigned long address) ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)); } -static unsigned long srmmu_swp_type(swp_entry_t entry) -{ - return (entry.val >> SRMMU_SWP_TYPE_SHIFT) & SRMMU_SWP_TYPE_MASK; -} - -static unsigned long srmmu_swp_offset(swp_entry_t entry) -{ - return (entry.val >> SRMMU_SWP_OFF_SHIFT) & SRMMU_SWP_OFF_MASK; -} - -static swp_entry_t srmmu_swp_entry(unsigned long type, unsigned long offset) -{ - return (swp_entry_t) { - (type & SRMMU_SWP_TYPE_MASK) << SRMMU_SWP_TYPE_SHIFT - | (offset & SRMMU_SWP_OFF_MASK) << SRMMU_SWP_OFF_SHIFT }; -} - /* * size: bytes to allocate in the nocache area. * align: bytes, number to align at. @@ -325,7 +178,7 @@ static unsigned long __srmmu_get_nocache(int size, int align) return (SRMMU_NOCACHE_VADDR + (offset << SRMMU_NOCACHE_BITMAP_SHIFT)); } -static unsigned long srmmu_get_nocache(int size, int align) +unsigned long srmmu_get_nocache(int size, int align) { unsigned long tmp; @@ -337,7 +190,7 @@ static unsigned long srmmu_get_nocache(int size, int align) return tmp; } -static void srmmu_free_nocache(unsigned long vaddr, int size) +void srmmu_free_nocache(unsigned long vaddr, int size) { int offset; @@ -429,15 +282,15 @@ static void __init srmmu_nocache_init(void) while (vaddr < srmmu_nocache_end) { pgd = pgd_offset_k(vaddr); - pmd = srmmu_pmd_offset(__nocache_fix(pgd), vaddr); - pte = srmmu_pte_offset(__nocache_fix(pmd), vaddr); + pmd = pmd_offset(__nocache_fix(pgd), vaddr); + pte = pte_offset_kernel(__nocache_fix(pmd), vaddr); pteval = ((paddr >> 4) | SRMMU_ET_PTE | SRMMU_PRIV); if (srmmu_cache_pagetables) pteval |= SRMMU_CACHE; - srmmu_set_pte(__nocache_fix(pte), __pte(pteval)); + set_pte(__nocache_fix(pte), __pte(pteval)); vaddr += PAGE_SIZE; paddr += PAGE_SIZE; @@ -447,7 +300,7 @@ static void __init srmmu_nocache_init(void) flush_tlb_all(); } -static inline pgd_t *srmmu_get_pgd_fast(void) +pgd_t *get_pgd_fast(void) { pgd_t *pgd = NULL; @@ -462,21 +315,6 @@ static inline pgd_t *srmmu_get_pgd_fast(void) return pgd; } -static void srmmu_free_pgd_fast(pgd_t *pgd) -{ - srmmu_free_nocache((unsigned long)pgd, SRMMU_PGD_TABLE_SIZE); -} - -static pmd_t *srmmu_pmd_alloc_one(struct mm_struct *mm, unsigned long address) -{ - return (pmd_t *)srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE); -} - -static void srmmu_pmd_free(pmd_t * pmd) -{ - srmmu_free_nocache((unsigned long)pmd, SRMMU_PMD_TABLE_SIZE); -} - /* * Hardware needs alignment to 256 only, but we align to whole page size * to reduce fragmentation problems due to the buddy principle. @@ -485,31 +323,19 @@ static void srmmu_pmd_free(pmd_t * pmd) * Alignments up to the page size are the same for physical and virtual * addresses of the nocache area. */ -static pte_t * -srmmu_pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address) -{ - return (pte_t *)srmmu_get_nocache(PTE_SIZE, PTE_SIZE); -} - -static pgtable_t -srmmu_pte_alloc_one(struct mm_struct *mm, unsigned long address) +pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address) { unsigned long pte; struct page *page; - if ((pte = (unsigned long)srmmu_pte_alloc_one_kernel(mm, address)) == 0) + if ((pte = (unsigned long)pte_alloc_one_kernel(mm, address)) == 0) return NULL; page = pfn_to_page( __nocache_pa(pte) >> PAGE_SHIFT ); pgtable_page_ctor(page); return page; } -static void srmmu_free_pte_fast(pte_t *pte) -{ - srmmu_free_nocache((unsigned long)pte, PTE_SIZE); -} - -static void srmmu_pte_free(pgtable_t pte) +void pte_free(struct mm_struct *mm, pgtable_t pte) { unsigned long p; @@ -560,8 +386,8 @@ static inline void free_context(int context) } -static void srmmu_switch_mm(struct mm_struct *old_mm, struct mm_struct *mm, - struct task_struct *tsk, int cpu) +void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm, + struct task_struct *tsk) { if(mm->context == NO_CONTEXT) { spin_lock(&srmmu_context_spinlock); @@ -590,8 +416,8 @@ static inline void srmmu_mapioaddr(unsigned long physaddr, physaddr &= PAGE_MASK; pgdp = pgd_offset_k(virt_addr); - pmdp = srmmu_pmd_offset(pgdp, virt_addr); - ptep = srmmu_pte_offset(pmdp, virt_addr); + pmdp = pmd_offset(pgdp, virt_addr); + ptep = pte_offset_kernel(pmdp, virt_addr); tmp = (physaddr >> 4) | SRMMU_ET_PTE; /* @@ -602,11 +428,11 @@ static inline void srmmu_mapioaddr(unsigned long physaddr, tmp |= (bus_type << 28); tmp |= SRMMU_PRIV; __flush_page_to_ram(virt_addr); - srmmu_set_pte(ptep, __pte(tmp)); + set_pte(ptep, __pte(tmp)); } -static void srmmu_mapiorange(unsigned int bus, unsigned long xpa, - unsigned long xva, unsigned int len) +void srmmu_mapiorange(unsigned int bus, unsigned long xpa, + unsigned long xva, unsigned int len) { while (len != 0) { len -= PAGE_SIZE; @@ -624,14 +450,14 @@ static inline void srmmu_unmapioaddr(unsigned long virt_addr) pte_t *ptep; pgdp = pgd_offset_k(virt_addr); - pmdp = srmmu_pmd_offset(pgdp, virt_addr); - ptep = srmmu_pte_offset(pmdp, virt_addr); + pmdp = pmd_offset(pgdp, virt_addr); + ptep = pte_offset_kernel(pmdp, virt_addr); /* No need to flush uncacheable page. */ - srmmu_pte_clear(ptep); + __pte_clear(ptep); } -static void srmmu_unmapiorange(unsigned long virt_addr, unsigned int len) +void srmmu_unmapiorange(unsigned long virt_addr, unsigned int len) { while (len != 0) { len -= PAGE_SIZE; @@ -647,10 +473,9 @@ static void srmmu_unmapiorange(unsigned long virt_addr, unsigned int len) * pool. As a side effect we are putting a little too much pressure * on the gfp() subsystem. This setup also makes the logic of the * iommu mapping code a lot easier as we can transparently handle - * mappings on the kernel stack without any special code as we did - * need on the sun4c. + * mappings on the kernel stack without any special code. */ -static struct thread_info *srmmu_alloc_thread_info_node(int node) +struct thread_info *alloc_thread_info_node(struct task_struct *tsk, int node) { struct thread_info *ret; @@ -664,7 +489,7 @@ static struct thread_info *srmmu_alloc_thread_info_node(int node) return ret; } -static void srmmu_free_thread_info(struct thread_info *ti) +void free_thread_info(struct thread_info *ti) { free_pages((unsigned long)ti, THREAD_INFO_ORDER); } @@ -683,38 +508,6 @@ extern void tsunami_flush_tlb_range(struct vm_area_struct *vma, unsigned long st extern void tsunami_flush_tlb_page(struct vm_area_struct *vma, unsigned long page); extern void tsunami_setup_blockops(void); -/* - * Workaround, until we find what's going on with Swift. When low on memory, - * it sometimes loops in fault/handle_mm_fault incl. flush_tlb_page to find - * out it is already in page tables/ fault again on the same instruction. - * I really don't understand it, have checked it and contexts - * are right, flush_tlb_all is done as well, and it faults again... - * Strange. -jj - * - * The following code is a deadwood that may be necessary when - * we start to make precise page flushes again. --zaitcev - */ -static void swift_update_mmu_cache(struct vm_area_struct * vma, unsigned long address, pte_t *ptep) -{ -#if 0 - static unsigned long last; - unsigned int val; - /* unsigned int n; */ - - if (address == last) { - val = srmmu_hwprobe(address); - if (val != 0 && pte_val(*ptep) != val) { - printk("swift_update_mmu_cache: " - "addr %lx put %08x probed %08x from %p\n", - address, pte_val(*ptep), val, - __builtin_return_address(0)); - srmmu_flush_whole_tlb(); - } - } - last = address; -#endif -} - /* swift.S */ extern void swift_flush_cache_all(void); extern void swift_flush_cache_mm(struct mm_struct *mm); @@ -767,244 +560,6 @@ void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) * with respect to cache coherency. */ -/* Cypress flushes. */ -static void cypress_flush_cache_all(void) -{ - volatile unsigned long cypress_sucks; - unsigned long faddr, tagval; - - flush_user_windows(); - for(faddr = 0; faddr < 0x10000; faddr += 0x20) { - __asm__ __volatile__("lda [%1 + %2] %3, %0\n\t" : - "=r" (tagval) : - "r" (faddr), "r" (0x40000), - "i" (ASI_M_DATAC_TAG)); - - /* If modified and valid, kick it. */ - if((tagval & 0x60) == 0x60) - cypress_sucks = *(unsigned long *)(0xf0020000 + faddr); - } -} - -static void cypress_flush_cache_mm(struct mm_struct *mm) -{ - register unsigned long a, b, c, d, e, f, g; - unsigned long flags, faddr; - int octx; - - FLUSH_BEGIN(mm) - flush_user_windows(); - local_irq_save(flags); - octx = srmmu_get_context(); - srmmu_set_context(mm->context); - a = 0x20; b = 0x40; c = 0x60; - d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0; - - faddr = (0x10000 - 0x100); - goto inside; - do { - faddr -= 0x100; - inside: - __asm__ __volatile__("sta %%g0, [%0] %1\n\t" - "sta %%g0, [%0 + %2] %1\n\t" - "sta %%g0, [%0 + %3] %1\n\t" - "sta %%g0, [%0 + %4] %1\n\t" - "sta %%g0, [%0 + %5] %1\n\t" - "sta %%g0, [%0 + %6] %1\n\t" - "sta %%g0, [%0 + %7] %1\n\t" - "sta %%g0, [%0 + %8] %1\n\t" : : - "r" (faddr), "i" (ASI_M_FLUSH_CTX), - "r" (a), "r" (b), "r" (c), "r" (d), - "r" (e), "r" (f), "r" (g)); - } while(faddr); - srmmu_set_context(octx); - local_irq_restore(flags); - FLUSH_END -} - -static void cypress_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) -{ - struct mm_struct *mm = vma->vm_mm; - register unsigned long a, b, c, d, e, f, g; - unsigned long flags, faddr; - int octx; - - FLUSH_BEGIN(mm) - flush_user_windows(); - local_irq_save(flags); - octx = srmmu_get_context(); - srmmu_set_context(mm->context); - a = 0x20; b = 0x40; c = 0x60; - d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0; - - start &= SRMMU_REAL_PMD_MASK; - while(start < end) { - faddr = (start + (0x10000 - 0x100)); - goto inside; - do { - faddr -= 0x100; - inside: - __asm__ __volatile__("sta %%g0, [%0] %1\n\t" - "sta %%g0, [%0 + %2] %1\n\t" - "sta %%g0, [%0 + %3] %1\n\t" - "sta %%g0, [%0 + %4] %1\n\t" - "sta %%g0, [%0 + %5] %1\n\t" - "sta %%g0, [%0 + %6] %1\n\t" - "sta %%g0, [%0 + %7] %1\n\t" - "sta %%g0, [%0 + %8] %1\n\t" : : - "r" (faddr), - "i" (ASI_M_FLUSH_SEG), - "r" (a), "r" (b), "r" (c), "r" (d), - "r" (e), "r" (f), "r" (g)); - } while (faddr != start); - start += SRMMU_REAL_PMD_SIZE; - } - srmmu_set_context(octx); - local_irq_restore(flags); - FLUSH_END -} - -static void cypress_flush_cache_page(struct vm_area_struct *vma, unsigned long page) -{ - register unsigned long a, b, c, d, e, f, g; - struct mm_struct *mm = vma->vm_mm; - unsigned long flags, line; - int octx; - - FLUSH_BEGIN(mm) - flush_user_windows(); - local_irq_save(flags); - octx = srmmu_get_context(); - srmmu_set_context(mm->context); - a = 0x20; b = 0x40; c = 0x60; - d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0; - - page &= PAGE_MASK; - line = (page + PAGE_SIZE) - 0x100; - goto inside; - do { - line -= 0x100; - inside: - __asm__ __volatile__("sta %%g0, [%0] %1\n\t" - "sta %%g0, [%0 + %2] %1\n\t" - "sta %%g0, [%0 + %3] %1\n\t" - "sta %%g0, [%0 + %4] %1\n\t" - "sta %%g0, [%0 + %5] %1\n\t" - "sta %%g0, [%0 + %6] %1\n\t" - "sta %%g0, [%0 + %7] %1\n\t" - "sta %%g0, [%0 + %8] %1\n\t" : : - "r" (line), - "i" (ASI_M_FLUSH_PAGE), - "r" (a), "r" (b), "r" (c), "r" (d), - "r" (e), "r" (f), "r" (g)); - } while(line != page); - srmmu_set_context(octx); - local_irq_restore(flags); - FLUSH_END -} - -/* Cypress is copy-back, at least that is how we configure it. */ -static void cypress_flush_page_to_ram(unsigned long page) -{ - register unsigned long a, b, c, d, e, f, g; - unsigned long line; - - a = 0x20; b = 0x40; c = 0x60; d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0; - page &= PAGE_MASK; - line = (page + PAGE_SIZE) - 0x100; - goto inside; - do { - line -= 0x100; - inside: - __asm__ __volatile__("sta %%g0, [%0] %1\n\t" - "sta %%g0, [%0 + %2] %1\n\t" - "sta %%g0, [%0 + %3] %1\n\t" - "sta %%g0, [%0 + %4] %1\n\t" - "sta %%g0, [%0 + %5] %1\n\t" - "sta %%g0, [%0 + %6] %1\n\t" - "sta %%g0, [%0 + %7] %1\n\t" - "sta %%g0, [%0 + %8] %1\n\t" : : - "r" (line), - "i" (ASI_M_FLUSH_PAGE), - "r" (a), "r" (b), "r" (c), "r" (d), - "r" (e), "r" (f), "r" (g)); - } while(line != page); -} - -/* Cypress is also IO cache coherent. */ -static void cypress_flush_page_for_dma(unsigned long page) -{ -} - -/* Cypress has unified L2 VIPT, from which both instructions and data - * are stored. It does not have an onboard icache of any sort, therefore - * no flush is necessary. - */ -static void cypress_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr) -{ -} - -static void cypress_flush_tlb_all(void) -{ - srmmu_flush_whole_tlb(); -} - -static void cypress_flush_tlb_mm(struct mm_struct *mm) -{ - FLUSH_BEGIN(mm) - __asm__ __volatile__( - "lda [%0] %3, %%g5\n\t" - "sta %2, [%0] %3\n\t" - "sta %%g0, [%1] %4\n\t" - "sta %%g5, [%0] %3\n" - : /* no outputs */ - : "r" (SRMMU_CTX_REG), "r" (0x300), "r" (mm->context), - "i" (ASI_M_MMUREGS), "i" (ASI_M_FLUSH_PROBE) - : "g5"); - FLUSH_END -} - -static void cypress_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) -{ - struct mm_struct *mm = vma->vm_mm; - unsigned long size; - - FLUSH_BEGIN(mm) - start &= SRMMU_PGDIR_MASK; - size = SRMMU_PGDIR_ALIGN(end) - start; - __asm__ __volatile__( - "lda [%0] %5, %%g5\n\t" - "sta %1, [%0] %5\n" - "1:\n\t" - "subcc %3, %4, %3\n\t" - "bne 1b\n\t" - " sta %%g0, [%2 + %3] %6\n\t" - "sta %%g5, [%0] %5\n" - : /* no outputs */ - : "r" (SRMMU_CTX_REG), "r" (mm->context), "r" (start | 0x200), - "r" (size), "r" (SRMMU_PGDIR_SIZE), "i" (ASI_M_MMUREGS), - "i" (ASI_M_FLUSH_PROBE) - : "g5", "cc"); - FLUSH_END -} - -static void cypress_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) -{ - struct mm_struct *mm = vma->vm_mm; - - FLUSH_BEGIN(mm) - __asm__ __volatile__( - "lda [%0] %3, %%g5\n\t" - "sta %1, [%0] %3\n\t" - "sta %%g0, [%2] %4\n\t" - "sta %%g5, [%0] %3\n" - : /* no outputs */ - : "r" (SRMMU_CTX_REG), "r" (mm->context), "r" (page & PAGE_MASK), - "i" (ASI_M_MMUREGS), "i" (ASI_M_FLUSH_PROBE) - : "g5"); - FLUSH_END -} - /* viking.S */ extern void viking_flush_cache_all(void); extern void viking_flush_cache_mm(struct mm_struct *mm); @@ -1065,21 +620,21 @@ static void __init srmmu_early_allocate_ptable_skeleton(unsigned long start, while(start < end) { pgdp = pgd_offset_k(start); - if(srmmu_pgd_none(*(pgd_t *)__nocache_fix(pgdp))) { + if (pgd_none(*(pgd_t *)__nocache_fix(pgdp))) { pmdp = (pmd_t *) __srmmu_get_nocache( SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE); if (pmdp == NULL) early_pgtable_allocfail("pmd"); memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE); - srmmu_pgd_set(__nocache_fix(pgdp), pmdp); + pgd_set(__nocache_fix(pgdp), pmdp); } - pmdp = srmmu_pmd_offset(__nocache_fix(pgdp), start); + pmdp = pmd_offset(__nocache_fix(pgdp), start); if(srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) { ptep = (pte_t *)__srmmu_get_nocache(PTE_SIZE, PTE_SIZE); if (ptep == NULL) early_pgtable_allocfail("pte"); memset(__nocache_fix(ptep), 0, PTE_SIZE); - srmmu_pmd_set(__nocache_fix(pmdp), ptep); + pmd_set(__nocache_fix(pmdp), ptep); } if (start > (0xffffffffUL - PMD_SIZE)) break; @@ -1096,21 +651,21 @@ static void __init srmmu_allocate_ptable_skeleton(unsigned long start, while(start < end) { pgdp = pgd_offset_k(start); - if(srmmu_pgd_none(*pgdp)) { + if (pgd_none(*pgdp)) { pmdp = (pmd_t *)__srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE); if (pmdp == NULL) early_pgtable_allocfail("pmd"); memset(pmdp, 0, SRMMU_PMD_TABLE_SIZE); - srmmu_pgd_set(pgdp, pmdp); + pgd_set(pgdp, pmdp); } - pmdp = srmmu_pmd_offset(pgdp, start); + pmdp = pmd_offset(pgdp, start); if(srmmu_pmd_none(*pmdp)) { ptep = (pte_t *) __srmmu_get_nocache(PTE_SIZE, PTE_SIZE); if (ptep == NULL) early_pgtable_allocfail("pte"); memset(ptep, 0, PTE_SIZE); - srmmu_pmd_set(pmdp, ptep); + pmd_set(pmdp, ptep); } if (start > (0xffffffffUL - PMD_SIZE)) break; @@ -1162,21 +717,21 @@ static void __init srmmu_inherit_prom_mappings(unsigned long start, start += SRMMU_PGDIR_SIZE; continue; } - if(srmmu_pgd_none(*(pgd_t *)__nocache_fix(pgdp))) { + if (pgd_none(*(pgd_t *)__nocache_fix(pgdp))) { pmdp = (pmd_t *)__srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE); if (pmdp == NULL) early_pgtable_allocfail("pmd"); memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE); - srmmu_pgd_set(__nocache_fix(pgdp), pmdp); + pgd_set(__nocache_fix(pgdp), pmdp); } - pmdp = srmmu_pmd_offset(__nocache_fix(pgdp), start); + pmdp = pmd_offset(__nocache_fix(pgdp), start); if(srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) { ptep = (pte_t *) __srmmu_get_nocache(PTE_SIZE, PTE_SIZE); if (ptep == NULL) early_pgtable_allocfail("pte"); memset(__nocache_fix(ptep), 0, PTE_SIZE); - srmmu_pmd_set(__nocache_fix(pmdp), ptep); + pmd_set(__nocache_fix(pmdp), ptep); } if(what == 1) { /* @@ -1190,7 +745,7 @@ static void __init srmmu_inherit_prom_mappings(unsigned long start, start += SRMMU_REAL_PMD_SIZE; continue; } - ptep = srmmu_pte_offset(__nocache_fix(pmdp), start); + ptep = pte_offset_kernel(__nocache_fix(pmdp), start); *(pte_t *)__nocache_fix(ptep) = __pte(prompte); start += PAGE_SIZE; } @@ -1231,13 +786,6 @@ static unsigned long __init map_spbank(unsigned long vbase, int sp_entry) return vstart; } -static inline void memprobe_error(char *msg) -{ - prom_printf(msg); - prom_printf("Halting now...\n"); - prom_halt(); -} - static inline void map_kernel(void) { int i; @@ -1249,8 +797,6 @@ static inline void map_kernel(void) for (i = 0; sp_banks[i].num_bytes != 0; i++) { map_spbank((unsigned long)__va(sp_banks[i].base_addr), i); } - - BTFIXUPSET_SIMM13(user_ptrs_per_pgd, PAGE_OFFSET / SRMMU_PGDIR_SIZE); } /* Paging initialization on the Sparc Reference MMU. */ @@ -1312,7 +858,7 @@ void __init srmmu_paging_init(void) srmmu_set_ctable_ptr((unsigned long)srmmu_ctx_table_phys); #ifdef CONFIG_SMP /* Stop from hanging here... */ - local_flush_tlb_all(); + local_ops->tlb_all(); #else flush_tlb_all(); #endif @@ -1326,8 +872,8 @@ void __init srmmu_paging_init(void) srmmu_allocate_ptable_skeleton(PKMAP_BASE, PKMAP_END); pgd = pgd_offset_k(PKMAP_BASE); - pmd = srmmu_pmd_offset(pgd, PKMAP_BASE); - pte = srmmu_pte_offset(pmd, PKMAP_BASE); + pmd = pmd_offset(pgd, PKMAP_BASE); + pte = pte_offset_kernel(pmd, PKMAP_BASE); pkmap_page_table = pte; flush_cache_all(); @@ -1359,7 +905,7 @@ void __init srmmu_paging_init(void) } } -static void srmmu_mmu_info(struct seq_file *m) +void mmu_info(struct seq_file *m) { seq_printf(m, "MMU type\t: %s\n" @@ -1372,11 +918,7 @@ static void srmmu_mmu_info(struct seq_file *m) srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT); } -static void srmmu_update_mmu_cache(struct vm_area_struct * vma, unsigned long address, pte_t pte) -{ -} - -static void srmmu_destroy_context(struct mm_struct *mm) +void destroy_context(struct mm_struct *mm) { if(mm->context != NO_CONTEXT) { @@ -1474,6 +1016,20 @@ static void __cpuinit poke_hypersparc(void) clear = srmmu_get_fstatus(); } +static const struct sparc32_cachetlb_ops hypersparc_ops = { + .cache_all = hypersparc_flush_cache_all, + .cache_mm = hypersparc_flush_cache_mm, + .cache_page = hypersparc_flush_cache_page, + .cache_range = hypersparc_flush_cache_range, + .tlb_all = hypersparc_flush_tlb_all, + .tlb_mm = hypersparc_flush_tlb_mm, + .tlb_page = hypersparc_flush_tlb_page, + .tlb_range = hypersparc_flush_tlb_range, + .page_to_ram = hypersparc_flush_page_to_ram, + .sig_insns = hypersparc_flush_sig_insns, + .page_for_dma = hypersparc_flush_page_for_dma, +}; + static void __init init_hypersparc(void) { srmmu_name = "ROSS HyperSparc"; @@ -1482,118 +1038,13 @@ static void __init init_hypersparc(void) init_vac_layout(); is_hypersparc = 1; - - BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(pmd_clear, srmmu_pmd_clear, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(pgd_clear, srmmu_pgd_clear, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_cache_all, hypersparc_flush_cache_all, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_cache_mm, hypersparc_flush_cache_mm, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_cache_range, hypersparc_flush_cache_range, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_cache_page, hypersparc_flush_cache_page, BTFIXUPCALL_NORM); - - BTFIXUPSET_CALL(flush_tlb_all, hypersparc_flush_tlb_all, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_tlb_mm, hypersparc_flush_tlb_mm, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_tlb_range, hypersparc_flush_tlb_range, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_tlb_page, hypersparc_flush_tlb_page, BTFIXUPCALL_NORM); - - BTFIXUPSET_CALL(__flush_page_to_ram, hypersparc_flush_page_to_ram, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_sig_insns, hypersparc_flush_sig_insns, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_page_for_dma, hypersparc_flush_page_for_dma, BTFIXUPCALL_NOP); - + sparc32_cachetlb_ops = &hypersparc_ops; poke_srmmu = poke_hypersparc; hypersparc_setup_blockops(); } -static void __cpuinit poke_cypress(void) -{ - unsigned long mreg = srmmu_get_mmureg(); - unsigned long faddr, tagval; - volatile unsigned long cypress_sucks; - volatile unsigned long clear; - - clear = srmmu_get_faddr(); - clear = srmmu_get_fstatus(); - - if (!(mreg & CYPRESS_CENABLE)) { - for(faddr = 0x0; faddr < 0x10000; faddr += 20) { - __asm__ __volatile__("sta %%g0, [%0 + %1] %2\n\t" - "sta %%g0, [%0] %2\n\t" : : - "r" (faddr), "r" (0x40000), - "i" (ASI_M_DATAC_TAG)); - } - } else { - for(faddr = 0; faddr < 0x10000; faddr += 0x20) { - __asm__ __volatile__("lda [%1 + %2] %3, %0\n\t" : - "=r" (tagval) : - "r" (faddr), "r" (0x40000), - "i" (ASI_M_DATAC_TAG)); - - /* If modified and valid, kick it. */ - if((tagval & 0x60) == 0x60) - cypress_sucks = *(unsigned long *) - (0xf0020000 + faddr); - } - } - - /* And one more, for our good neighbor, Mr. Broken Cypress. */ - clear = srmmu_get_faddr(); - clear = srmmu_get_fstatus(); - - mreg |= (CYPRESS_CENABLE | CYPRESS_CMODE); - srmmu_set_mmureg(mreg); -} - -static void __init init_cypress_common(void) -{ - init_vac_layout(); - - BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(pmd_clear, srmmu_pmd_clear, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(pgd_clear, srmmu_pgd_clear, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_cache_all, cypress_flush_cache_all, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_cache_mm, cypress_flush_cache_mm, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_cache_range, cypress_flush_cache_range, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_cache_page, cypress_flush_cache_page, BTFIXUPCALL_NORM); - - BTFIXUPSET_CALL(flush_tlb_all, cypress_flush_tlb_all, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_tlb_mm, cypress_flush_tlb_mm, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_tlb_page, cypress_flush_tlb_page, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_tlb_range, cypress_flush_tlb_range, BTFIXUPCALL_NORM); - - - BTFIXUPSET_CALL(__flush_page_to_ram, cypress_flush_page_to_ram, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_sig_insns, cypress_flush_sig_insns, BTFIXUPCALL_NOP); - BTFIXUPSET_CALL(flush_page_for_dma, cypress_flush_page_for_dma, BTFIXUPCALL_NOP); - - poke_srmmu = poke_cypress; -} - -static void __init init_cypress_604(void) -{ - srmmu_name = "ROSS Cypress-604(UP)"; - srmmu_modtype = Cypress; - init_cypress_common(); -} - -static void __init init_cypress_605(unsigned long mrev) -{ - srmmu_name = "ROSS Cypress-605(MP)"; - if(mrev == 0xe) { - srmmu_modtype = Cypress_vE; - hwbug_bitmask |= HWBUG_COPYBACK_BROKEN; - } else { - if(mrev == 0xd) { - srmmu_modtype = Cypress_vD; - hwbug_bitmask |= HWBUG_ASIFLUSH_BROKEN; - } else { - srmmu_modtype = Cypress; - } - } - init_cypress_common(); -} - static void __cpuinit poke_swift(void) { unsigned long mreg; @@ -1617,6 +1068,20 @@ static void __cpuinit poke_swift(void) srmmu_set_mmureg(mreg); } +static const struct sparc32_cachetlb_ops swift_ops = { + .cache_all = swift_flush_cache_all, + .cache_mm = swift_flush_cache_mm, + .cache_page = swift_flush_cache_page, + .cache_range = swift_flush_cache_range, + .tlb_all = swift_flush_tlb_all, + .tlb_mm = swift_flush_tlb_mm, + .tlb_page = swift_flush_tlb_page, + .tlb_range = swift_flush_tlb_range, + .page_to_ram = swift_flush_page_to_ram, + .sig_insns = swift_flush_sig_insns, + .page_for_dma = swift_flush_page_for_dma, +}; + #define SWIFT_MASKID_ADDR 0x10003018 static void __init init_swift(void) { @@ -1667,23 +1132,7 @@ static void __init init_swift(void) break; } - BTFIXUPSET_CALL(flush_cache_all, swift_flush_cache_all, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_cache_mm, swift_flush_cache_mm, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_cache_page, swift_flush_cache_page, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_cache_range, swift_flush_cache_range, BTFIXUPCALL_NORM); - - - BTFIXUPSET_CALL(flush_tlb_all, swift_flush_tlb_all, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_tlb_mm, swift_flush_tlb_mm, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_tlb_page, swift_flush_tlb_page, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_tlb_range, swift_flush_tlb_range, BTFIXUPCALL_NORM); - - BTFIXUPSET_CALL(__flush_page_to_ram, swift_flush_page_to_ram, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_sig_insns, swift_flush_sig_insns, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_page_for_dma, swift_flush_page_for_dma, BTFIXUPCALL_NORM); - - BTFIXUPSET_CALL(update_mmu_cache, swift_update_mmu_cache, BTFIXUPCALL_NORM); - + sparc32_cachetlb_ops = &swift_ops; flush_page_for_dma_global = 0; /* @@ -1816,26 +1265,25 @@ static void __cpuinit poke_turbosparc(void) srmmu_set_mmureg(mreg); } +static const struct sparc32_cachetlb_ops turbosparc_ops = { + .cache_all = turbosparc_flush_cache_all, + .cache_mm = turbosparc_flush_cache_mm, + .cache_page = turbosparc_flush_cache_page, + .cache_range = turbosparc_flush_cache_range, + .tlb_all = turbosparc_flush_tlb_all, + .tlb_mm = turbosparc_flush_tlb_mm, + .tlb_page = turbosparc_flush_tlb_page, + .tlb_range = turbosparc_flush_tlb_range, + .page_to_ram = turbosparc_flush_page_to_ram, + .sig_insns = turbosparc_flush_sig_insns, + .page_for_dma = turbosparc_flush_page_for_dma, +}; + static void __init init_turbosparc(void) { srmmu_name = "Fujitsu TurboSparc"; srmmu_modtype = TurboSparc; - - BTFIXUPSET_CALL(flush_cache_all, turbosparc_flush_cache_all, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_cache_mm, turbosparc_flush_cache_mm, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_cache_page, turbosparc_flush_cache_page, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_cache_range, turbosparc_flush_cache_range, BTFIXUPCALL_NORM); - - BTFIXUPSET_CALL(flush_tlb_all, turbosparc_flush_tlb_all, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_tlb_mm, turbosparc_flush_tlb_mm, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_tlb_page, turbosparc_flush_tlb_page, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_tlb_range, turbosparc_flush_tlb_range, BTFIXUPCALL_NORM); - - BTFIXUPSET_CALL(__flush_page_to_ram, turbosparc_flush_page_to_ram, BTFIXUPCALL_NORM); - - BTFIXUPSET_CALL(flush_sig_insns, turbosparc_flush_sig_insns, BTFIXUPCALL_NOP); - BTFIXUPSET_CALL(flush_page_for_dma, turbosparc_flush_page_for_dma, BTFIXUPCALL_NORM); - + sparc32_cachetlb_ops = &turbosparc_ops; poke_srmmu = poke_turbosparc; } @@ -1850,6 +1298,20 @@ static void __cpuinit poke_tsunami(void) srmmu_set_mmureg(mreg); } +static const struct sparc32_cachetlb_ops tsunami_ops = { + .cache_all = tsunami_flush_cache_all, + .cache_mm = tsunami_flush_cache_mm, + .cache_page = tsunami_flush_cache_page, + .cache_range = tsunami_flush_cache_range, + .tlb_all = tsunami_flush_tlb_all, + .tlb_mm = tsunami_flush_tlb_mm, + .tlb_page = tsunami_flush_tlb_page, + .tlb_range = tsunami_flush_tlb_range, + .page_to_ram = tsunami_flush_page_to_ram, + .sig_insns = tsunami_flush_sig_insns, + .page_for_dma = tsunami_flush_page_for_dma, +}; + static void __init init_tsunami(void) { /* @@ -1860,22 +1322,7 @@ static void __init init_tsunami(void) srmmu_name = "TI Tsunami"; srmmu_modtype = Tsunami; - - BTFIXUPSET_CALL(flush_cache_all, tsunami_flush_cache_all, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_cache_mm, tsunami_flush_cache_mm, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_cache_page, tsunami_flush_cache_page, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_cache_range, tsunami_flush_cache_range, BTFIXUPCALL_NORM); - - - BTFIXUPSET_CALL(flush_tlb_all, tsunami_flush_tlb_all, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_tlb_mm, tsunami_flush_tlb_mm, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_tlb_page, tsunami_flush_tlb_page, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_tlb_range, tsunami_flush_tlb_range, BTFIXUPCALL_NORM); - - BTFIXUPSET_CALL(__flush_page_to_ram, tsunami_flush_page_to_ram, BTFIXUPCALL_NOP); - BTFIXUPSET_CALL(flush_sig_insns, tsunami_flush_sig_insns, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_page_for_dma, tsunami_flush_page_for_dma, BTFIXUPCALL_NORM); - + sparc32_cachetlb_ops = &tsunami_ops; poke_srmmu = poke_tsunami; tsunami_setup_blockops(); @@ -1886,7 +1333,7 @@ static void __cpuinit poke_viking(void) unsigned long mreg = srmmu_get_mmureg(); static int smp_catch; - if(viking_mxcc_present) { + if (viking_mxcc_present) { unsigned long mxcc_control = mxcc_get_creg(); mxcc_control |= (MXCC_CTL_ECE | MXCC_CTL_PRE | MXCC_CTL_MCE); @@ -1923,6 +1370,52 @@ static void __cpuinit poke_viking(void) srmmu_set_mmureg(mreg); } +static struct sparc32_cachetlb_ops viking_ops = { + .cache_all = viking_flush_cache_all, + .cache_mm = viking_flush_cache_mm, + .cache_page = viking_flush_cache_page, + .cache_range = viking_flush_cache_range, + .tlb_all = viking_flush_tlb_all, + .tlb_mm = viking_flush_tlb_mm, + .tlb_page = viking_flush_tlb_page, + .tlb_range = viking_flush_tlb_range, + .page_to_ram = viking_flush_page_to_ram, + .sig_insns = viking_flush_sig_insns, + .page_for_dma = viking_flush_page_for_dma, +}; + +#ifdef CONFIG_SMP +/* On sun4d the cpu broadcasts local TLB flushes, so we can just + * perform the local TLB flush and all the other cpus will see it. + * But, unfortunately, there is a bug in the sun4d XBUS backplane + * that requires that we add some synchronization to these flushes. + * + * The bug is that the fifo which keeps track of all the pending TLB + * broadcasts in the system is an entry or two too small, so if we + * have too many going at once we'll overflow that fifo and lose a TLB + * flush resulting in corruption. + * + * Our workaround is to take a global spinlock around the TLB flushes, + * which guarentees we won't ever have too many pending. It's a big + * hammer, but a semaphore like system to make sure we only have N TLB + * flushes going at once will require SMP locking anyways so there's + * no real value in trying any harder than this. + */ +static struct sparc32_cachetlb_ops viking_sun4d_smp_ops = { + .cache_all = viking_flush_cache_all, + .cache_mm = viking_flush_cache_mm, + .cache_page = viking_flush_cache_page, + .cache_range = viking_flush_cache_range, + .tlb_all = sun4dsmp_flush_tlb_all, + .tlb_mm = sun4dsmp_flush_tlb_mm, + .tlb_page = sun4dsmp_flush_tlb_page, + .tlb_range = sun4dsmp_flush_tlb_range, + .page_to_ram = viking_flush_page_to_ram, + .sig_insns = viking_flush_sig_insns, + .page_for_dma = viking_flush_page_for_dma, +}; +#endif + static void __init init_viking(void) { unsigned long mreg = srmmu_get_mmureg(); @@ -1933,10 +1426,6 @@ static void __init init_viking(void) viking_mxcc_present = 0; msi_set_sync(); - BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(pmd_clear, srmmu_pmd_clear, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(pgd_clear, srmmu_pgd_clear, BTFIXUPCALL_NORM); - /* * We need this to make sure old viking takes no hits * on it's cache for dma snoops to workaround the @@ -1944,84 +1433,28 @@ static void __init init_viking(void) * This is only necessary because of the new way in * which we use the IOMMU. */ - BTFIXUPSET_CALL(flush_page_for_dma, viking_flush_page, BTFIXUPCALL_NORM); - + viking_ops.page_for_dma = viking_flush_page; +#ifdef CONFIG_SMP + viking_sun4d_smp_ops.page_for_dma = viking_flush_page; +#endif flush_page_for_dma_global = 0; } else { srmmu_name = "TI Viking/MXCC"; viking_mxcc_present = 1; - srmmu_cache_pagetables = 1; - - /* MXCC vikings lack the DMA snooping bug. */ - BTFIXUPSET_CALL(flush_page_for_dma, viking_flush_page_for_dma, BTFIXUPCALL_NOP); } - BTFIXUPSET_CALL(flush_cache_all, viking_flush_cache_all, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_cache_mm, viking_flush_cache_mm, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_cache_page, viking_flush_cache_page, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_cache_range, viking_flush_cache_range, BTFIXUPCALL_NORM); - + sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *) + &viking_ops; #ifdef CONFIG_SMP - if (sparc_cpu_model == sun4d) { - BTFIXUPSET_CALL(flush_tlb_all, sun4dsmp_flush_tlb_all, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_tlb_mm, sun4dsmp_flush_tlb_mm, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_tlb_page, sun4dsmp_flush_tlb_page, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_tlb_range, sun4dsmp_flush_tlb_range, BTFIXUPCALL_NORM); - } else + if (sparc_cpu_model == sun4d) + sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *) + &viking_sun4d_smp_ops; #endif - { - BTFIXUPSET_CALL(flush_tlb_all, viking_flush_tlb_all, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_tlb_mm, viking_flush_tlb_mm, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_tlb_page, viking_flush_tlb_page, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_tlb_range, viking_flush_tlb_range, BTFIXUPCALL_NORM); - } - - BTFIXUPSET_CALL(__flush_page_to_ram, viking_flush_page_to_ram, BTFIXUPCALL_NOP); - BTFIXUPSET_CALL(flush_sig_insns, viking_flush_sig_insns, BTFIXUPCALL_NOP); poke_srmmu = poke_viking; } -#ifdef CONFIG_SPARC_LEON - -void __init poke_leonsparc(void) -{ -} - -void __init init_leon(void) -{ - - srmmu_name = "LEON"; - - BTFIXUPSET_CALL(flush_cache_all, leon_flush_cache_all, - BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_cache_mm, leon_flush_cache_all, - BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_cache_page, leon_flush_pcache_all, - BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_cache_range, leon_flush_cache_all, - BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_page_for_dma, leon_flush_dcache_all, - BTFIXUPCALL_NORM); - - BTFIXUPSET_CALL(flush_tlb_all, leon_flush_tlb_all, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_tlb_mm, leon_flush_tlb_all, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_tlb_page, leon_flush_tlb_all, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_tlb_range, leon_flush_tlb_all, BTFIXUPCALL_NORM); - - BTFIXUPSET_CALL(__flush_page_to_ram, leon_flush_cache_all, - BTFIXUPCALL_NOP); - BTFIXUPSET_CALL(flush_sig_insns, leon_flush_cache_all, BTFIXUPCALL_NOP); - - poke_srmmu = poke_leonsparc; - - srmmu_cache_pagetables = 0; - - leon_flush_during_switch = leon_flush_needed(); -} -#endif - /* Probe for the srmmu chip version. */ static void __init get_srmmu_type(void) { @@ -2052,22 +1485,15 @@ static void __init get_srmmu_type(void) break; case 0: case 2: - /* Uniprocessor Cypress */ - init_cypress_604(); - break; case 10: case 11: case 12: - /* _REALLY OLD_ Cypress MP chips... */ case 13: case 14: case 15: - /* MP Cypress mmu/cache-controller */ - init_cypress_605(mod_rev); - break; default: - /* Some other Cypress revision, assume a 605. */ - init_cypress_605(mod_rev); + prom_printf("Sparc-Linux Cypress support does not longer exit.\n"); + prom_halt(); break; } return; @@ -2123,203 +1549,193 @@ static void __init get_srmmu_type(void) srmmu_is_bad(); } -/* don't laugh, static pagetables */ -static void srmmu_check_pgt_cache(int low, int high) +#ifdef CONFIG_SMP +/* Local cross-calls. */ +static void smp_flush_page_for_dma(unsigned long page) { + xc1((smpfunc_t) local_ops->page_for_dma, page); + local_ops->page_for_dma(page); } -extern unsigned long spwin_mmu_patchme, fwin_mmu_patchme, - tsetup_mmu_patchme, rtrap_mmu_patchme; - -extern unsigned long spwin_srmmu_stackchk, srmmu_fwin_stackchk, - tsetup_srmmu_stackchk, srmmu_rett_stackchk; - -extern unsigned long srmmu_fault; - -#define PATCH_BRANCH(insn, dest) do { \ - iaddr = &(insn); \ - daddr = &(dest); \ - *iaddr = SPARC_BRANCH((unsigned long) daddr, (unsigned long) iaddr); \ - } while(0) - -static void __init patch_window_trap_handlers(void) +static void smp_flush_cache_all(void) { - unsigned long *iaddr, *daddr; - - PATCH_BRANCH(spwin_mmu_patchme, spwin_srmmu_stackchk); - PATCH_BRANCH(fwin_mmu_patchme, srmmu_fwin_stackchk); - PATCH_BRANCH(tsetup_mmu_patchme, tsetup_srmmu_stackchk); - PATCH_BRANCH(rtrap_mmu_patchme, srmmu_rett_stackchk); - PATCH_BRANCH(sparc_ttable[SP_TRAP_TFLT].inst_three, srmmu_fault); - PATCH_BRANCH(sparc_ttable[SP_TRAP_DFLT].inst_three, srmmu_fault); - PATCH_BRANCH(sparc_ttable[SP_TRAP_DACC].inst_three, srmmu_fault); + xc0((smpfunc_t) local_ops->cache_all); + local_ops->cache_all(); } -#ifdef CONFIG_SMP -/* Local cross-calls. */ -static void smp_flush_page_for_dma(unsigned long page) +static void smp_flush_tlb_all(void) { - xc1((smpfunc_t) BTFIXUP_CALL(local_flush_page_for_dma), page); - local_flush_page_for_dma(page); + xc0((smpfunc_t) local_ops->tlb_all); + local_ops->tlb_all(); } -#endif - -static pte_t srmmu_pgoff_to_pte(unsigned long pgoff) +static void smp_flush_cache_mm(struct mm_struct *mm) { - return __pte((pgoff << SRMMU_PTE_FILE_SHIFT) | SRMMU_FILE); + if (mm->context != NO_CONTEXT) { + cpumask_t cpu_mask; + cpumask_copy(&cpu_mask, mm_cpumask(mm)); + cpumask_clear_cpu(smp_processor_id(), &cpu_mask); + if (!cpumask_empty(&cpu_mask)) + xc1((smpfunc_t) local_ops->cache_mm, (unsigned long) mm); + local_ops->cache_mm(mm); + } } -static unsigned long srmmu_pte_to_pgoff(pte_t pte) +static void smp_flush_tlb_mm(struct mm_struct *mm) { - return pte_val(pte) >> SRMMU_PTE_FILE_SHIFT; + if (mm->context != NO_CONTEXT) { + cpumask_t cpu_mask; + cpumask_copy(&cpu_mask, mm_cpumask(mm)); + cpumask_clear_cpu(smp_processor_id(), &cpu_mask); + if (!cpumask_empty(&cpu_mask)) { + xc1((smpfunc_t) local_ops->tlb_mm, (unsigned long) mm); + if (atomic_read(&mm->mm_users) == 1 && current->active_mm == mm) + cpumask_copy(mm_cpumask(mm), + cpumask_of(smp_processor_id())); + } + local_ops->tlb_mm(mm); + } } -static pgprot_t srmmu_pgprot_noncached(pgprot_t prot) +static void smp_flush_cache_range(struct vm_area_struct *vma, + unsigned long start, + unsigned long end) { - prot &= ~__pgprot(SRMMU_CACHE); + struct mm_struct *mm = vma->vm_mm; - return prot; + if (mm->context != NO_CONTEXT) { + cpumask_t cpu_mask; + cpumask_copy(&cpu_mask, mm_cpumask(mm)); + cpumask_clear_cpu(smp_processor_id(), &cpu_mask); + if (!cpumask_empty(&cpu_mask)) + xc3((smpfunc_t) local_ops->cache_range, + (unsigned long) vma, start, end); + local_ops->cache_range(vma, start, end); + } } -/* Load up routines and constants for sun4m and sun4d mmu */ -void __init ld_mmu_srmmu(void) +static void smp_flush_tlb_range(struct vm_area_struct *vma, + unsigned long start, + unsigned long end) { - extern void ld_mmu_iommu(void); - extern void ld_mmu_iounit(void); - extern void ___xchg32_sun4md(void); - - BTFIXUPSET_SIMM13(pgdir_shift, SRMMU_PGDIR_SHIFT); - BTFIXUPSET_SETHI(pgdir_size, SRMMU_PGDIR_SIZE); - BTFIXUPSET_SETHI(pgdir_mask, SRMMU_PGDIR_MASK); - - BTFIXUPSET_SIMM13(ptrs_per_pmd, SRMMU_PTRS_PER_PMD); - BTFIXUPSET_SIMM13(ptrs_per_pgd, SRMMU_PTRS_PER_PGD); - - BTFIXUPSET_INT(page_none, pgprot_val(SRMMU_PAGE_NONE)); - PAGE_SHARED = pgprot_val(SRMMU_PAGE_SHARED); - BTFIXUPSET_INT(page_copy, pgprot_val(SRMMU_PAGE_COPY)); - BTFIXUPSET_INT(page_readonly, pgprot_val(SRMMU_PAGE_RDONLY)); - BTFIXUPSET_INT(page_kernel, pgprot_val(SRMMU_PAGE_KERNEL)); - page_kernel = pgprot_val(SRMMU_PAGE_KERNEL); + struct mm_struct *mm = vma->vm_mm; - /* Functions */ - BTFIXUPSET_CALL(pgprot_noncached, srmmu_pgprot_noncached, BTFIXUPCALL_NORM); -#ifndef CONFIG_SMP - BTFIXUPSET_CALL(___xchg32, ___xchg32_sun4md, BTFIXUPCALL_SWAPG1G2); -#endif - BTFIXUPSET_CALL(do_check_pgt_cache, srmmu_check_pgt_cache, BTFIXUPCALL_NOP); + if (mm->context != NO_CONTEXT) { + cpumask_t cpu_mask; + cpumask_copy(&cpu_mask, mm_cpumask(mm)); + cpumask_clear_cpu(smp_processor_id(), &cpu_mask); + if (!cpumask_empty(&cpu_mask)) + xc3((smpfunc_t) local_ops->tlb_range, + (unsigned long) vma, start, end); + local_ops->tlb_range(vma, start, end); + } +} - BTFIXUPSET_CALL(set_pte, srmmu_set_pte, BTFIXUPCALL_SWAPO0O1); - BTFIXUPSET_CALL(switch_mm, srmmu_switch_mm, BTFIXUPCALL_NORM); +static void smp_flush_cache_page(struct vm_area_struct *vma, unsigned long page) +{ + struct mm_struct *mm = vma->vm_mm; - BTFIXUPSET_CALL(pte_pfn, srmmu_pte_pfn, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(pmd_page, srmmu_pmd_page, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(pgd_page_vaddr, srmmu_pgd_page, BTFIXUPCALL_NORM); + if (mm->context != NO_CONTEXT) { + cpumask_t cpu_mask; + cpumask_copy(&cpu_mask, mm_cpumask(mm)); + cpumask_clear_cpu(smp_processor_id(), &cpu_mask); + if (!cpumask_empty(&cpu_mask)) + xc2((smpfunc_t) local_ops->cache_page, + (unsigned long) vma, page); + local_ops->cache_page(vma, page); + } +} - BTFIXUPSET_CALL(pte_present, srmmu_pte_present, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_SWAPO0G0); +static void smp_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) +{ + struct mm_struct *mm = vma->vm_mm; - BTFIXUPSET_CALL(pmd_bad, srmmu_pmd_bad, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(pmd_present, srmmu_pmd_present, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(pmd_clear, srmmu_pmd_clear, BTFIXUPCALL_SWAPO0G0); + if (mm->context != NO_CONTEXT) { + cpumask_t cpu_mask; + cpumask_copy(&cpu_mask, mm_cpumask(mm)); + cpumask_clear_cpu(smp_processor_id(), &cpu_mask); + if (!cpumask_empty(&cpu_mask)) + xc2((smpfunc_t) local_ops->tlb_page, + (unsigned long) vma, page); + local_ops->tlb_page(vma, page); + } +} - BTFIXUPSET_CALL(pgd_none, srmmu_pgd_none, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(pgd_bad, srmmu_pgd_bad, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(pgd_present, srmmu_pgd_present, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(pgd_clear, srmmu_pgd_clear, BTFIXUPCALL_SWAPO0G0); +static void smp_flush_page_to_ram(unsigned long page) +{ + /* Current theory is that those who call this are the one's + * who have just dirtied their cache with the pages contents + * in kernel space, therefore we only run this on local cpu. + * + * XXX This experiment failed, research further... -DaveM + */ +#if 1 + xc1((smpfunc_t) local_ops->page_to_ram, page); +#endif + local_ops->page_to_ram(page); +} + +static void smp_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr) +{ + cpumask_t cpu_mask; + cpumask_copy(&cpu_mask, mm_cpumask(mm)); + cpumask_clear_cpu(smp_processor_id(), &cpu_mask); + if (!cpumask_empty(&cpu_mask)) + xc2((smpfunc_t) local_ops->sig_insns, + (unsigned long) mm, insn_addr); + local_ops->sig_insns(mm, insn_addr); +} + +static struct sparc32_cachetlb_ops smp_cachetlb_ops = { + .cache_all = smp_flush_cache_all, + .cache_mm = smp_flush_cache_mm, + .cache_page = smp_flush_cache_page, + .cache_range = smp_flush_cache_range, + .tlb_all = smp_flush_tlb_all, + .tlb_mm = smp_flush_tlb_mm, + .tlb_page = smp_flush_tlb_page, + .tlb_range = smp_flush_tlb_range, + .page_to_ram = smp_flush_page_to_ram, + .sig_insns = smp_flush_sig_insns, + .page_for_dma = smp_flush_page_for_dma, +}; +#endif - BTFIXUPSET_CALL(mk_pte, srmmu_mk_pte, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(mk_pte_phys, srmmu_mk_pte_phys, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(mk_pte_io, srmmu_mk_pte_io, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(pgd_set, srmmu_pgd_set, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(pmd_set, srmmu_pmd_set, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(pmd_populate, srmmu_pmd_populate, BTFIXUPCALL_NORM); - - BTFIXUPSET_INT(pte_modify_mask, SRMMU_CHG_MASK); - BTFIXUPSET_CALL(pmd_offset, srmmu_pmd_offset, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(pte_offset_kernel, srmmu_pte_offset, BTFIXUPCALL_NORM); - - BTFIXUPSET_CALL(free_pte_fast, srmmu_free_pte_fast, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(pte_free, srmmu_pte_free, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(pte_alloc_one_kernel, srmmu_pte_alloc_one_kernel, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(pte_alloc_one, srmmu_pte_alloc_one, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(free_pmd_fast, srmmu_pmd_free, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(pmd_alloc_one, srmmu_pmd_alloc_one, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(free_pgd_fast, srmmu_free_pgd_fast, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(get_pgd_fast, srmmu_get_pgd_fast, BTFIXUPCALL_NORM); - - BTFIXUPSET_HALF(pte_writei, SRMMU_WRITE); - BTFIXUPSET_HALF(pte_dirtyi, SRMMU_DIRTY); - BTFIXUPSET_HALF(pte_youngi, SRMMU_REF); - BTFIXUPSET_HALF(pte_filei, SRMMU_FILE); - BTFIXUPSET_HALF(pte_wrprotecti, SRMMU_WRITE); - BTFIXUPSET_HALF(pte_mkcleani, SRMMU_DIRTY); - BTFIXUPSET_HALF(pte_mkoldi, SRMMU_REF); - BTFIXUPSET_CALL(pte_mkwrite, srmmu_pte_mkwrite, BTFIXUPCALL_ORINT(SRMMU_WRITE)); - BTFIXUPSET_CALL(pte_mkdirty, srmmu_pte_mkdirty, BTFIXUPCALL_ORINT(SRMMU_DIRTY)); - BTFIXUPSET_CALL(pte_mkyoung, srmmu_pte_mkyoung, BTFIXUPCALL_ORINT(SRMMU_REF)); - BTFIXUPSET_CALL(update_mmu_cache, srmmu_update_mmu_cache, BTFIXUPCALL_NOP); - BTFIXUPSET_CALL(destroy_context, srmmu_destroy_context, BTFIXUPCALL_NORM); - - BTFIXUPSET_CALL(sparc_mapiorange, srmmu_mapiorange, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(sparc_unmapiorange, srmmu_unmapiorange, BTFIXUPCALL_NORM); - - BTFIXUPSET_CALL(__swp_type, srmmu_swp_type, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(__swp_offset, srmmu_swp_offset, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(__swp_entry, srmmu_swp_entry, BTFIXUPCALL_NORM); - - BTFIXUPSET_CALL(mmu_info, srmmu_mmu_info, BTFIXUPCALL_NORM); - - BTFIXUPSET_CALL(alloc_thread_info_node, srmmu_alloc_thread_info_node, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(free_thread_info, srmmu_free_thread_info, BTFIXUPCALL_NORM); - - BTFIXUPSET_CALL(pte_to_pgoff, srmmu_pte_to_pgoff, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(pgoff_to_pte, srmmu_pgoff_to_pte, BTFIXUPCALL_NORM); +/* Load up routines and constants for sun4m and sun4d mmu */ +void __init load_mmu(void) +{ + extern void ld_mmu_iommu(void); + extern void ld_mmu_iounit(void); + /* Functions */ get_srmmu_type(); - patch_window_trap_handlers(); #ifdef CONFIG_SMP /* El switcheroo... */ + local_ops = sparc32_cachetlb_ops; - BTFIXUPCOPY_CALL(local_flush_cache_all, flush_cache_all); - BTFIXUPCOPY_CALL(local_flush_cache_mm, flush_cache_mm); - BTFIXUPCOPY_CALL(local_flush_cache_range, flush_cache_range); - BTFIXUPCOPY_CALL(local_flush_cache_page, flush_cache_page); - BTFIXUPCOPY_CALL(local_flush_tlb_all, flush_tlb_all); - BTFIXUPCOPY_CALL(local_flush_tlb_mm, flush_tlb_mm); - BTFIXUPCOPY_CALL(local_flush_tlb_range, flush_tlb_range); - BTFIXUPCOPY_CALL(local_flush_tlb_page, flush_tlb_page); - BTFIXUPCOPY_CALL(local_flush_page_to_ram, __flush_page_to_ram); - BTFIXUPCOPY_CALL(local_flush_sig_insns, flush_sig_insns); - BTFIXUPCOPY_CALL(local_flush_page_for_dma, flush_page_for_dma); - - BTFIXUPSET_CALL(flush_cache_all, smp_flush_cache_all, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_cache_mm, smp_flush_cache_mm, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_cache_range, smp_flush_cache_range, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_cache_page, smp_flush_cache_page, BTFIXUPCALL_NORM); - if (sparc_cpu_model != sun4d && - sparc_cpu_model != sparc_leon) { - BTFIXUPSET_CALL(flush_tlb_all, smp_flush_tlb_all, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_tlb_mm, smp_flush_tlb_mm, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_tlb_range, smp_flush_tlb_range, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_tlb_page, smp_flush_tlb_page, BTFIXUPCALL_NORM); + if (sparc_cpu_model == sun4d || sparc_cpu_model == sparc_leon) { + smp_cachetlb_ops.tlb_all = local_ops->tlb_all; + smp_cachetlb_ops.tlb_mm = local_ops->tlb_mm; + smp_cachetlb_ops.tlb_range = local_ops->tlb_range; + smp_cachetlb_ops.tlb_page = local_ops->tlb_page; } - BTFIXUPSET_CALL(__flush_page_to_ram, smp_flush_page_to_ram, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_sig_insns, smp_flush_sig_insns, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_page_for_dma, smp_flush_page_for_dma, BTFIXUPCALL_NORM); if (poke_srmmu == poke_viking) { /* Avoid unnecessary cross calls. */ - BTFIXUPCOPY_CALL(flush_cache_all, local_flush_cache_all); - BTFIXUPCOPY_CALL(flush_cache_mm, local_flush_cache_mm); - BTFIXUPCOPY_CALL(flush_cache_range, local_flush_cache_range); - BTFIXUPCOPY_CALL(flush_cache_page, local_flush_cache_page); - BTFIXUPCOPY_CALL(__flush_page_to_ram, local_flush_page_to_ram); - BTFIXUPCOPY_CALL(flush_sig_insns, local_flush_sig_insns); - BTFIXUPCOPY_CALL(flush_page_for_dma, local_flush_page_for_dma); + smp_cachetlb_ops.cache_all = local_ops->cache_all; + smp_cachetlb_ops.cache_mm = local_ops->cache_mm; + smp_cachetlb_ops.cache_range = local_ops->cache_range; + smp_cachetlb_ops.cache_page = local_ops->cache_page; + + smp_cachetlb_ops.page_to_ram = local_ops->page_to_ram; + smp_cachetlb_ops.sig_insns = local_ops->sig_insns; + smp_cachetlb_ops.page_for_dma = local_ops->page_for_dma; } + + /* It really is const after this point. */ + sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *) + &smp_cachetlb_ops; #endif if (sparc_cpu_model == sun4d) diff --git a/arch/sparc/mm/srmmu.h b/arch/sparc/mm/srmmu.h new file mode 100644 index 000000000000..5703274ccf89 --- /dev/null +++ b/arch/sparc/mm/srmmu.h @@ -0,0 +1,4 @@ +/* srmmu.c */ +extern char *srmmu_name; + +extern void (*poke_srmmu)(void); diff --git a/arch/sparc/mm/sun4c.c b/arch/sparc/mm/sun4c.c deleted file mode 100644 index 1cf4f198709a..000000000000 --- a/arch/sparc/mm/sun4c.c +++ /dev/null @@ -1,2166 +0,0 @@ -/* sun4c.c: Doing in software what should be done in hardware. - * - * Copyright (C) 1996 David S. Miller ([email protected]) - * Copyright (C) 1996 Eddie C. Dost ([email protected]) - * Copyright (C) 1996 Andrew Tridgell ([email protected]) - * Copyright (C) 1997-2000 Anton Blanchard ([email protected]) - * Copyright (C) 1998 Jakub Jelinek ([email protected]) - */ - -#define NR_TASK_BUCKETS 512 - -#include <linux/kernel.h> -#include <linux/mm.h> -#include <linux/init.h> -#include <linux/slab.h> -#include <linux/bootmem.h> -#include <linux/highmem.h> -#include <linux/fs.h> -#include <linux/seq_file.h> -#include <linux/scatterlist.h> -#include <linux/bitmap.h> - -#include <asm/sections.h> -#include <asm/page.h> -#include <asm/pgalloc.h> -#include <asm/pgtable.h> -#include <asm/vaddrs.h> -#include <asm/idprom.h> -#include <asm/machines.h> -#include <asm/memreg.h> -#include <asm/processor.h> -#include <asm/auxio.h> -#include <asm/io.h> -#include <asm/oplib.h> -#include <asm/openprom.h> -#include <asm/mmu_context.h> -#include <asm/highmem.h> -#include <asm/btfixup.h> -#include <asm/cacheflush.h> -#include <asm/tlbflush.h> - -/* Because of our dynamic kernel TLB miss strategy, and how - * our DVMA mapping allocation works, you _MUST_: - * - * 1) Disable interrupts _and_ not touch any dynamic kernel - * memory while messing with kernel MMU state. By - * dynamic memory I mean any object which is not in - * the kernel image itself or a thread_union (both of - * which are locked into the MMU). - * 2) Disable interrupts while messing with user MMU state. - */ - -extern int num_segmaps, num_contexts; - -extern unsigned long page_kernel; - -/* That's it, we prom_halt() on sun4c if the cache size is something other than 65536. - * So let's save some cycles and just use that everywhere except for that bootup - * sanity check. - */ -#define SUN4C_VAC_SIZE 65536 - -#define SUN4C_KERNEL_BUCKETS 32 - -/* Flushing the cache. */ -struct sun4c_vac_props sun4c_vacinfo; -unsigned long sun4c_kernel_faults; - -/* Invalidate every sun4c cache line tag. */ -static void __init sun4c_flush_all(void) -{ - unsigned long begin, end; - - if (sun4c_vacinfo.on) - panic("SUN4C: AIEEE, trying to invalidate vac while it is on."); - - /* Clear 'valid' bit in all cache line tags */ - begin = AC_CACHETAGS; - end = (AC_CACHETAGS + SUN4C_VAC_SIZE); - while (begin < end) { - __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : : - "r" (begin), "i" (ASI_CONTROL)); - begin += sun4c_vacinfo.linesize; - } -} - -static void sun4c_flush_context_hw(void) -{ - unsigned long end = SUN4C_VAC_SIZE; - - __asm__ __volatile__( - "1: addcc %0, -4096, %0\n\t" - " bne 1b\n\t" - " sta %%g0, [%0] %2" - : "=&r" (end) - : "0" (end), "i" (ASI_HWFLUSHCONTEXT) - : "cc"); -} - -/* Must be called minimally with IRQs disabled. */ -static void sun4c_flush_segment_hw(unsigned long addr) -{ - if (sun4c_get_segmap(addr) != invalid_segment) { - unsigned long vac_size = SUN4C_VAC_SIZE; - - __asm__ __volatile__( - "1: addcc %0, -4096, %0\n\t" - " bne 1b\n\t" - " sta %%g0, [%2 + %0] %3" - : "=&r" (vac_size) - : "0" (vac_size), "r" (addr), "i" (ASI_HWFLUSHSEG) - : "cc"); - } -} - -/* File local boot time fixups. */ -BTFIXUPDEF_CALL(void, sun4c_flush_page, unsigned long) -BTFIXUPDEF_CALL(void, sun4c_flush_segment, unsigned long) -BTFIXUPDEF_CALL(void, sun4c_flush_context, void) - -#define sun4c_flush_page(addr) BTFIXUP_CALL(sun4c_flush_page)(addr) -#define sun4c_flush_segment(addr) BTFIXUP_CALL(sun4c_flush_segment)(addr) -#define sun4c_flush_context() BTFIXUP_CALL(sun4c_flush_context)() - -/* Must be called minimally with interrupts disabled. */ -static void sun4c_flush_page_hw(unsigned long addr) -{ - addr &= PAGE_MASK; - if ((int)sun4c_get_pte(addr) < 0) - __asm__ __volatile__("sta %%g0, [%0] %1" - : : "r" (addr), "i" (ASI_HWFLUSHPAGE)); -} - -/* Don't inline the software version as it eats too many cache lines if expanded. */ -static void sun4c_flush_context_sw(void) -{ - unsigned long nbytes = SUN4C_VAC_SIZE; - unsigned long lsize = sun4c_vacinfo.linesize; - - __asm__ __volatile__( - "add %2, %2, %%g1\n\t" - "add %2, %%g1, %%g2\n\t" - "add %2, %%g2, %%g3\n\t" - "add %2, %%g3, %%g4\n\t" - "add %2, %%g4, %%g5\n\t" - "add %2, %%g5, %%o4\n\t" - "add %2, %%o4, %%o5\n" - "1:\n\t" - "subcc %0, %%o5, %0\n\t" - "sta %%g0, [%0] %3\n\t" - "sta %%g0, [%0 + %2] %3\n\t" - "sta %%g0, [%0 + %%g1] %3\n\t" - "sta %%g0, [%0 + %%g2] %3\n\t" - "sta %%g0, [%0 + %%g3] %3\n\t" - "sta %%g0, [%0 + %%g4] %3\n\t" - "sta %%g0, [%0 + %%g5] %3\n\t" - "bg 1b\n\t" - " sta %%g0, [%1 + %%o4] %3\n" - : "=&r" (nbytes) - : "0" (nbytes), "r" (lsize), "i" (ASI_FLUSHCTX) - : "g1", "g2", "g3", "g4", "g5", "o4", "o5", "cc"); -} - -/* Don't inline the software version as it eats too many cache lines if expanded. */ -static void sun4c_flush_segment_sw(unsigned long addr) -{ - if (sun4c_get_segmap(addr) != invalid_segment) { - unsigned long nbytes = SUN4C_VAC_SIZE; - unsigned long lsize = sun4c_vacinfo.linesize; - - __asm__ __volatile__( - "add %2, %2, %%g1\n\t" - "add %2, %%g1, %%g2\n\t" - "add %2, %%g2, %%g3\n\t" - "add %2, %%g3, %%g4\n\t" - "add %2, %%g4, %%g5\n\t" - "add %2, %%g5, %%o4\n\t" - "add %2, %%o4, %%o5\n" - "1:\n\t" - "subcc %1, %%o5, %1\n\t" - "sta %%g0, [%0] %6\n\t" - "sta %%g0, [%0 + %2] %6\n\t" - "sta %%g0, [%0 + %%g1] %6\n\t" - "sta %%g0, [%0 + %%g2] %6\n\t" - "sta %%g0, [%0 + %%g3] %6\n\t" - "sta %%g0, [%0 + %%g4] %6\n\t" - "sta %%g0, [%0 + %%g5] %6\n\t" - "sta %%g0, [%0 + %%o4] %6\n\t" - "bg 1b\n\t" - " add %0, %%o5, %0\n" - : "=&r" (addr), "=&r" (nbytes), "=&r" (lsize) - : "0" (addr), "1" (nbytes), "2" (lsize), - "i" (ASI_FLUSHSEG) - : "g1", "g2", "g3", "g4", "g5", "o4", "o5", "cc"); - } -} - -/* Don't inline the software version as it eats too many cache lines if expanded. */ -static void sun4c_flush_page_sw(unsigned long addr) -{ - addr &= PAGE_MASK; - if ((sun4c_get_pte(addr) & (_SUN4C_PAGE_NOCACHE | _SUN4C_PAGE_VALID)) == - _SUN4C_PAGE_VALID) { - unsigned long left = PAGE_SIZE; - unsigned long lsize = sun4c_vacinfo.linesize; - - __asm__ __volatile__( - "add %2, %2, %%g1\n\t" - "add %2, %%g1, %%g2\n\t" - "add %2, %%g2, %%g3\n\t" - "add %2, %%g3, %%g4\n\t" - "add %2, %%g4, %%g5\n\t" - "add %2, %%g5, %%o4\n\t" - "add %2, %%o4, %%o5\n" - "1:\n\t" - "subcc %1, %%o5, %1\n\t" - "sta %%g0, [%0] %6\n\t" - "sta %%g0, [%0 + %2] %6\n\t" - "sta %%g0, [%0 + %%g1] %6\n\t" - "sta %%g0, [%0 + %%g2] %6\n\t" - "sta %%g0, [%0 + %%g3] %6\n\t" - "sta %%g0, [%0 + %%g4] %6\n\t" - "sta %%g0, [%0 + %%g5] %6\n\t" - "sta %%g0, [%0 + %%o4] %6\n\t" - "bg 1b\n\t" - " add %0, %%o5, %0\n" - : "=&r" (addr), "=&r" (left), "=&r" (lsize) - : "0" (addr), "1" (left), "2" (lsize), - "i" (ASI_FLUSHPG) - : "g1", "g2", "g3", "g4", "g5", "o4", "o5", "cc"); - } -} - -/* The sun4c's do have an on chip store buffer. And the way you - * clear them out isn't so obvious. The only way I can think of - * to accomplish this is to read the current context register, - * store the same value there, then read an external hardware - * register. - */ -void sun4c_complete_all_stores(void) -{ - volatile int _unused; - - _unused = sun4c_get_context(); - sun4c_set_context(_unused); - _unused = get_auxio(); -} - -/* Bootup utility functions. */ -static inline void sun4c_init_clean_segmap(unsigned char pseg) -{ - unsigned long vaddr; - - sun4c_put_segmap(0, pseg); - for (vaddr = 0; vaddr < SUN4C_REAL_PGDIR_SIZE; vaddr += PAGE_SIZE) - sun4c_put_pte(vaddr, 0); - sun4c_put_segmap(0, invalid_segment); -} - -static inline void sun4c_init_clean_mmu(unsigned long kernel_end) -{ - unsigned long vaddr; - unsigned char savectx, ctx; - - savectx = sun4c_get_context(); - for (ctx = 0; ctx < num_contexts; ctx++) { - sun4c_set_context(ctx); - for (vaddr = 0; vaddr < 0x20000000; vaddr += SUN4C_REAL_PGDIR_SIZE) - sun4c_put_segmap(vaddr, invalid_segment); - for (vaddr = 0xe0000000; vaddr < KERNBASE; vaddr += SUN4C_REAL_PGDIR_SIZE) - sun4c_put_segmap(vaddr, invalid_segment); - for (vaddr = kernel_end; vaddr < KADB_DEBUGGER_BEGVM; vaddr += SUN4C_REAL_PGDIR_SIZE) - sun4c_put_segmap(vaddr, invalid_segment); - for (vaddr = LINUX_OPPROM_ENDVM; vaddr; vaddr += SUN4C_REAL_PGDIR_SIZE) - sun4c_put_segmap(vaddr, invalid_segment); - } - sun4c_set_context(savectx); -} - -void __init sun4c_probe_vac(void) -{ - sun4c_disable_vac(); - - if ((idprom->id_machtype == (SM_SUN4C | SM_4C_SS1)) || - (idprom->id_machtype == (SM_SUN4C | SM_4C_SS1PLUS))) { - /* PROM on SS1 lacks this info, to be super safe we - * hard code it here since this arch is cast in stone. - */ - sun4c_vacinfo.num_bytes = 65536; - sun4c_vacinfo.linesize = 16; - } else { - sun4c_vacinfo.num_bytes = - prom_getintdefault(prom_root_node, "vac-size", 65536); - sun4c_vacinfo.linesize = - prom_getintdefault(prom_root_node, "vac-linesize", 16); - } - sun4c_vacinfo.do_hwflushes = - prom_getintdefault(prom_root_node, "vac-hwflush", 0); - - if (sun4c_vacinfo.do_hwflushes == 0) - sun4c_vacinfo.do_hwflushes = - prom_getintdefault(prom_root_node, "vac_hwflush", 0); - - if (sun4c_vacinfo.num_bytes != 65536) { - prom_printf("WEIRD Sun4C VAC cache size, " - "tell [email protected]"); - prom_halt(); - } - - switch (sun4c_vacinfo.linesize) { - case 16: - sun4c_vacinfo.log2lsize = 4; - break; - case 32: - sun4c_vacinfo.log2lsize = 5; - break; - default: - prom_printf("probe_vac: Didn't expect vac-linesize of %d, halting\n", - sun4c_vacinfo.linesize); - prom_halt(); - } - - sun4c_flush_all(); - sun4c_enable_vac(); -} - -/* Patch instructions for the low level kernel fault handler. */ -extern unsigned long invalid_segment_patch1, invalid_segment_patch1_ff; -extern unsigned long invalid_segment_patch2, invalid_segment_patch2_ff; -extern unsigned long invalid_segment_patch1_1ff, invalid_segment_patch2_1ff; -extern unsigned long num_context_patch1, num_context_patch1_16; -extern unsigned long num_context_patch2_16; -extern unsigned long vac_linesize_patch, vac_linesize_patch_32; -extern unsigned long vac_hwflush_patch1, vac_hwflush_patch1_on; -extern unsigned long vac_hwflush_patch2, vac_hwflush_patch2_on; - -#define PATCH_INSN(src, dst) do { \ - daddr = &(dst); \ - iaddr = &(src); \ - *daddr = *iaddr; \ - } while (0) - -static void __init patch_kernel_fault_handler(void) -{ - unsigned long *iaddr, *daddr; - - switch (num_segmaps) { - case 128: - /* Default, nothing to do. */ - break; - case 256: - PATCH_INSN(invalid_segment_patch1_ff, - invalid_segment_patch1); - PATCH_INSN(invalid_segment_patch2_ff, - invalid_segment_patch2); - break; - case 512: - PATCH_INSN(invalid_segment_patch1_1ff, - invalid_segment_patch1); - PATCH_INSN(invalid_segment_patch2_1ff, - invalid_segment_patch2); - break; - default: - prom_printf("Unhandled number of segmaps: %d\n", - num_segmaps); - prom_halt(); - } - switch (num_contexts) { - case 8: - /* Default, nothing to do. */ - break; - case 16: - PATCH_INSN(num_context_patch1_16, - num_context_patch1); - break; - default: - prom_printf("Unhandled number of contexts: %d\n", - num_contexts); - prom_halt(); - } - - if (sun4c_vacinfo.do_hwflushes != 0) { - PATCH_INSN(vac_hwflush_patch1_on, vac_hwflush_patch1); - PATCH_INSN(vac_hwflush_patch2_on, vac_hwflush_patch2); - } else { - switch (sun4c_vacinfo.linesize) { - case 16: - /* Default, nothing to do. */ - break; - case 32: - PATCH_INSN(vac_linesize_patch_32, vac_linesize_patch); - break; - default: - prom_printf("Impossible VAC linesize %d, halting...\n", - sun4c_vacinfo.linesize); - prom_halt(); - } - } -} - -static void __init sun4c_probe_mmu(void) -{ - if ((idprom->id_machtype == (SM_SUN4C | SM_4C_SS1)) || - (idprom->id_machtype == (SM_SUN4C | SM_4C_SS1PLUS))) { - /* Hardcode these just to be safe, PROM on SS1 does - * not have this info available in the root node. - */ - num_segmaps = 128; - num_contexts = 8; - } else { - num_segmaps = - prom_getintdefault(prom_root_node, "mmu-npmg", 128); - num_contexts = - prom_getintdefault(prom_root_node, "mmu-nctx", 0x8); - } - patch_kernel_fault_handler(); -} - -volatile unsigned long __iomem *sun4c_memerr_reg = NULL; - -void __init sun4c_probe_memerr_reg(void) -{ - phandle node; - struct linux_prom_registers regs[1]; - - node = prom_getchild(prom_root_node); - node = prom_searchsiblings(prom_root_node, "memory-error"); - if (!node) - return; - if (prom_getproperty(node, "reg", (char *)regs, sizeof(regs)) <= 0) - return; - /* hmm I think regs[0].which_io is zero here anyways */ - sun4c_memerr_reg = ioremap(regs[0].phys_addr, regs[0].reg_size); -} - -static inline void sun4c_init_ss2_cache_bug(void) -{ - if ((idprom->id_machtype == (SM_SUN4C | SM_4C_SS2)) || - (idprom->id_machtype == (SM_SUN4C | SM_4C_IPX)) || - (idprom->id_machtype == (SM_SUN4C | SM_4C_ELC))) { - /* Whee.. */ - printk("SS2 cache bug detected, uncaching trap table page\n"); - sun4c_flush_page((unsigned int) &_start); - sun4c_put_pte(((unsigned long) &_start), - (sun4c_get_pte((unsigned long) &_start) | _SUN4C_PAGE_NOCACHE)); - } -} - -/* Addr is always aligned on a page boundary for us already. */ -static int sun4c_map_dma_area(struct device *dev, dma_addr_t *pba, unsigned long va, - unsigned long addr, int len) -{ - unsigned long page, end; - - *pba = addr; - - end = PAGE_ALIGN((addr + len)); - while (addr < end) { - page = va; - sun4c_flush_page(page); - page -= PAGE_OFFSET; - page >>= PAGE_SHIFT; - page |= (_SUN4C_PAGE_VALID | _SUN4C_PAGE_DIRTY | - _SUN4C_PAGE_NOCACHE | _SUN4C_PAGE_PRIV); - sun4c_put_pte(addr, page); - addr += PAGE_SIZE; - va += PAGE_SIZE; - } - - return 0; -} - -static void sun4c_unmap_dma_area(struct device *dev, unsigned long busa, int len) -{ - /* Fortunately for us, bus_addr == uncached_virt in sun4c. */ - /* XXX Implement this */ -} - -/* TLB management. */ - -/* Don't change this struct without changing entry.S. This is used - * in the in-window kernel fault handler, and you don't want to mess - * with that. (See sun4c_fault in entry.S). - */ -struct sun4c_mmu_entry { - struct sun4c_mmu_entry *next; - struct sun4c_mmu_entry *prev; - unsigned long vaddr; - unsigned char pseg; - unsigned char locked; - - /* For user mappings only, and completely hidden from kernel - * TLB miss code. - */ - unsigned char ctx; - struct sun4c_mmu_entry *lru_next; - struct sun4c_mmu_entry *lru_prev; -}; - -static struct sun4c_mmu_entry mmu_entry_pool[SUN4C_MAX_SEGMAPS]; - -static void __init sun4c_init_mmu_entry_pool(void) -{ - int i; - - for (i=0; i < SUN4C_MAX_SEGMAPS; i++) { - mmu_entry_pool[i].pseg = i; - mmu_entry_pool[i].next = NULL; - mmu_entry_pool[i].prev = NULL; - mmu_entry_pool[i].vaddr = 0; - mmu_entry_pool[i].locked = 0; - mmu_entry_pool[i].ctx = 0; - mmu_entry_pool[i].lru_next = NULL; - mmu_entry_pool[i].lru_prev = NULL; - } - mmu_entry_pool[invalid_segment].locked = 1; -} - -static inline void fix_permissions(unsigned long vaddr, unsigned long bits_on, - unsigned long bits_off) -{ - unsigned long start, end; - - end = vaddr + SUN4C_REAL_PGDIR_SIZE; - for (start = vaddr; start < end; start += PAGE_SIZE) - if (sun4c_get_pte(start) & _SUN4C_PAGE_VALID) - sun4c_put_pte(start, (sun4c_get_pte(start) | bits_on) & - ~bits_off); -} - -static inline void sun4c_init_map_kernelprom(unsigned long kernel_end) -{ - unsigned long vaddr; - unsigned char pseg, ctx; - - for (vaddr = KADB_DEBUGGER_BEGVM; - vaddr < LINUX_OPPROM_ENDVM; - vaddr += SUN4C_REAL_PGDIR_SIZE) { - pseg = sun4c_get_segmap(vaddr); - if (pseg != invalid_segment) { - mmu_entry_pool[pseg].locked = 1; - for (ctx = 0; ctx < num_contexts; ctx++) - prom_putsegment(ctx, vaddr, pseg); - fix_permissions(vaddr, _SUN4C_PAGE_PRIV, 0); - } - } - - for (vaddr = KERNBASE; vaddr < kernel_end; vaddr += SUN4C_REAL_PGDIR_SIZE) { - pseg = sun4c_get_segmap(vaddr); - mmu_entry_pool[pseg].locked = 1; - for (ctx = 0; ctx < num_contexts; ctx++) - prom_putsegment(ctx, vaddr, pseg); - fix_permissions(vaddr, _SUN4C_PAGE_PRIV, _SUN4C_PAGE_NOCACHE); - } -} - -static void __init sun4c_init_lock_area(unsigned long start, unsigned long end) -{ - int i, ctx; - - while (start < end) { - for (i = 0; i < invalid_segment; i++) - if (!mmu_entry_pool[i].locked) - break; - mmu_entry_pool[i].locked = 1; - sun4c_init_clean_segmap(i); - for (ctx = 0; ctx < num_contexts; ctx++) - prom_putsegment(ctx, start, mmu_entry_pool[i].pseg); - start += SUN4C_REAL_PGDIR_SIZE; - } -} - -/* Don't change this struct without changing entry.S. This is used - * in the in-window kernel fault handler, and you don't want to mess - * with that. (See sun4c_fault in entry.S). - */ -struct sun4c_mmu_ring { - struct sun4c_mmu_entry ringhd; - int num_entries; -}; - -static struct sun4c_mmu_ring sun4c_context_ring[SUN4C_MAX_CONTEXTS]; /* used user entries */ -static struct sun4c_mmu_ring sun4c_ufree_ring; /* free user entries */ -static struct sun4c_mmu_ring sun4c_ulru_ring; /* LRU user entries */ -struct sun4c_mmu_ring sun4c_kernel_ring; /* used kernel entries */ -struct sun4c_mmu_ring sun4c_kfree_ring; /* free kernel entries */ - -static inline void sun4c_init_rings(void) -{ - int i; - - for (i = 0; i < SUN4C_MAX_CONTEXTS; i++) { - sun4c_context_ring[i].ringhd.next = - sun4c_context_ring[i].ringhd.prev = - &sun4c_context_ring[i].ringhd; - sun4c_context_ring[i].num_entries = 0; - } - sun4c_ufree_ring.ringhd.next = sun4c_ufree_ring.ringhd.prev = - &sun4c_ufree_ring.ringhd; - sun4c_ufree_ring.num_entries = 0; - sun4c_ulru_ring.ringhd.lru_next = sun4c_ulru_ring.ringhd.lru_prev = - &sun4c_ulru_ring.ringhd; - sun4c_ulru_ring.num_entries = 0; - sun4c_kernel_ring.ringhd.next = sun4c_kernel_ring.ringhd.prev = - &sun4c_kernel_ring.ringhd; - sun4c_kernel_ring.num_entries = 0; - sun4c_kfree_ring.ringhd.next = sun4c_kfree_ring.ringhd.prev = - &sun4c_kfree_ring.ringhd; - sun4c_kfree_ring.num_entries = 0; -} - -static void add_ring(struct sun4c_mmu_ring *ring, - struct sun4c_mmu_entry *entry) -{ - struct sun4c_mmu_entry *head = &ring->ringhd; - - entry->prev = head; - (entry->next = head->next)->prev = entry; - head->next = entry; - ring->num_entries++; -} - -static inline void add_lru(struct sun4c_mmu_entry *entry) -{ - struct sun4c_mmu_ring *ring = &sun4c_ulru_ring; - struct sun4c_mmu_entry *head = &ring->ringhd; - - entry->lru_next = head; - (entry->lru_prev = head->lru_prev)->lru_next = entry; - head->lru_prev = entry; -} - -static void add_ring_ordered(struct sun4c_mmu_ring *ring, - struct sun4c_mmu_entry *entry) -{ - struct sun4c_mmu_entry *head = &ring->ringhd; - unsigned long addr = entry->vaddr; - - while ((head->next != &ring->ringhd) && (head->next->vaddr < addr)) - head = head->next; - - entry->prev = head; - (entry->next = head->next)->prev = entry; - head->next = entry; - ring->num_entries++; - - add_lru(entry); -} - -static inline void remove_ring(struct sun4c_mmu_ring *ring, - struct sun4c_mmu_entry *entry) -{ - struct sun4c_mmu_entry *next = entry->next; - - (next->prev = entry->prev)->next = next; - ring->num_entries--; -} - -static void remove_lru(struct sun4c_mmu_entry *entry) -{ - struct sun4c_mmu_entry *next = entry->lru_next; - - (next->lru_prev = entry->lru_prev)->lru_next = next; -} - -static void free_user_entry(int ctx, struct sun4c_mmu_entry *entry) -{ - remove_ring(sun4c_context_ring+ctx, entry); - remove_lru(entry); - add_ring(&sun4c_ufree_ring, entry); -} - -static void free_kernel_entry(struct sun4c_mmu_entry *entry, - struct sun4c_mmu_ring *ring) -{ - remove_ring(ring, entry); - add_ring(&sun4c_kfree_ring, entry); -} - -static void __init sun4c_init_fill_kernel_ring(int howmany) -{ - int i; - - while (howmany) { - for (i = 0; i < invalid_segment; i++) - if (!mmu_entry_pool[i].locked) - break; - mmu_entry_pool[i].locked = 1; - sun4c_init_clean_segmap(i); - add_ring(&sun4c_kfree_ring, &mmu_entry_pool[i]); - howmany--; - } -} - -static void __init sun4c_init_fill_user_ring(void) -{ - int i; - - for (i = 0; i < invalid_segment; i++) { - if (mmu_entry_pool[i].locked) - continue; - sun4c_init_clean_segmap(i); - add_ring(&sun4c_ufree_ring, &mmu_entry_pool[i]); - } -} - -static void sun4c_kernel_unmap(struct sun4c_mmu_entry *kentry) -{ - int savectx, ctx; - - savectx = sun4c_get_context(); - for (ctx = 0; ctx < num_contexts; ctx++) { - sun4c_set_context(ctx); - sun4c_put_segmap(kentry->vaddr, invalid_segment); - } - sun4c_set_context(savectx); -} - -static void sun4c_kernel_map(struct sun4c_mmu_entry *kentry) -{ - int savectx, ctx; - - savectx = sun4c_get_context(); - for (ctx = 0; ctx < num_contexts; ctx++) { - sun4c_set_context(ctx); - sun4c_put_segmap(kentry->vaddr, kentry->pseg); - } - sun4c_set_context(savectx); -} - -#define sun4c_user_unmap(__entry) \ - sun4c_put_segmap((__entry)->vaddr, invalid_segment) - -static void sun4c_demap_context(struct sun4c_mmu_ring *crp, unsigned char ctx) -{ - struct sun4c_mmu_entry *head = &crp->ringhd; - unsigned long flags; - - local_irq_save(flags); - if (head->next != head) { - struct sun4c_mmu_entry *entry = head->next; - int savectx = sun4c_get_context(); - - flush_user_windows(); - sun4c_set_context(ctx); - sun4c_flush_context(); - do { - struct sun4c_mmu_entry *next = entry->next; - - sun4c_user_unmap(entry); - free_user_entry(ctx, entry); - - entry = next; - } while (entry != head); - sun4c_set_context(savectx); - } - local_irq_restore(flags); -} - -static int sun4c_user_taken_entries; /* This is how much we have. */ -static int max_user_taken_entries; /* This limits us and prevents deadlock. */ - -static struct sun4c_mmu_entry *sun4c_kernel_strategy(void) -{ - struct sun4c_mmu_entry *this_entry; - - /* If some are free, return first one. */ - if (sun4c_kfree_ring.num_entries) { - this_entry = sun4c_kfree_ring.ringhd.next; - return this_entry; - } - - /* Else free one up. */ - this_entry = sun4c_kernel_ring.ringhd.prev; - sun4c_flush_segment(this_entry->vaddr); - sun4c_kernel_unmap(this_entry); - free_kernel_entry(this_entry, &sun4c_kernel_ring); - this_entry = sun4c_kfree_ring.ringhd.next; - - return this_entry; -} - -/* Using this method to free up mmu entries eliminates a lot of - * potential races since we have a kernel that incurs tlb - * replacement faults. There may be performance penalties. - * - * NOTE: Must be called with interrupts disabled. - */ -static struct sun4c_mmu_entry *sun4c_user_strategy(void) -{ - struct sun4c_mmu_entry *entry; - unsigned char ctx; - int savectx; - - /* If some are free, return first one. */ - if (sun4c_ufree_ring.num_entries) { - entry = sun4c_ufree_ring.ringhd.next; - goto unlink_out; - } - - if (sun4c_user_taken_entries) { - entry = sun4c_kernel_strategy(); - sun4c_user_taken_entries--; - goto kunlink_out; - } - - /* Grab from the beginning of the LRU list. */ - entry = sun4c_ulru_ring.ringhd.lru_next; - ctx = entry->ctx; - - savectx = sun4c_get_context(); - flush_user_windows(); - sun4c_set_context(ctx); - sun4c_flush_segment(entry->vaddr); - sun4c_user_unmap(entry); - remove_ring(sun4c_context_ring + ctx, entry); - remove_lru(entry); - sun4c_set_context(savectx); - - return entry; - -unlink_out: - remove_ring(&sun4c_ufree_ring, entry); - return entry; -kunlink_out: - remove_ring(&sun4c_kfree_ring, entry); - return entry; -} - -/* NOTE: Must be called with interrupts disabled. */ -void sun4c_grow_kernel_ring(void) -{ - struct sun4c_mmu_entry *entry; - - /* Prevent deadlock condition. */ - if (sun4c_user_taken_entries >= max_user_taken_entries) - return; - - if (sun4c_ufree_ring.num_entries) { - entry = sun4c_ufree_ring.ringhd.next; - remove_ring(&sun4c_ufree_ring, entry); - add_ring(&sun4c_kfree_ring, entry); - sun4c_user_taken_entries++; - } -} - -/* 2 page buckets for task struct and kernel stack allocation. - * - * TASK_STACK_BEGIN - * bucket[0] - * bucket[1] - * [ ... ] - * bucket[NR_TASK_BUCKETS-1] - * TASK_STACK_BEGIN + (sizeof(struct task_bucket) * NR_TASK_BUCKETS) - * - * Each slot looks like: - * - * page 1 -- task struct + beginning of kernel stack - * page 2 -- rest of kernel stack - */ - -union task_union *sun4c_bucket[NR_TASK_BUCKETS]; - -static int sun4c_lowbucket_avail; - -#define BUCKET_EMPTY ((union task_union *) 0) -#define BUCKET_SHIFT (PAGE_SHIFT + 1) /* log2(sizeof(struct task_bucket)) */ -#define BUCKET_SIZE (1 << BUCKET_SHIFT) -#define BUCKET_NUM(addr) ((((addr) - SUN4C_LOCK_VADDR) >> BUCKET_SHIFT)) -#define BUCKET_ADDR(num) (((num) << BUCKET_SHIFT) + SUN4C_LOCK_VADDR) -#define BUCKET_PTE(page) \ - ((((page) - PAGE_OFFSET) >> PAGE_SHIFT) | pgprot_val(SUN4C_PAGE_KERNEL)) -#define BUCKET_PTE_PAGE(pte) \ - (PAGE_OFFSET + (((pte) & SUN4C_PFN_MASK) << PAGE_SHIFT)) - -static void get_locked_segment(unsigned long addr) -{ - struct sun4c_mmu_entry *stolen; - unsigned long flags; - - local_irq_save(flags); - addr &= SUN4C_REAL_PGDIR_MASK; - stolen = sun4c_user_strategy(); - max_user_taken_entries--; - stolen->vaddr = addr; - flush_user_windows(); - sun4c_kernel_map(stolen); - local_irq_restore(flags); -} - -static void free_locked_segment(unsigned long addr) -{ - struct sun4c_mmu_entry *entry; - unsigned long flags; - unsigned char pseg; - - local_irq_save(flags); - addr &= SUN4C_REAL_PGDIR_MASK; - pseg = sun4c_get_segmap(addr); - entry = &mmu_entry_pool[pseg]; - - flush_user_windows(); - sun4c_flush_segment(addr); - sun4c_kernel_unmap(entry); - add_ring(&sun4c_ufree_ring, entry); - max_user_taken_entries++; - local_irq_restore(flags); -} - -static inline void garbage_collect(int entry) -{ - int start, end; - - /* 32 buckets per segment... */ - entry &= ~31; - start = entry; - for (end = (start + 32); start < end; start++) - if (sun4c_bucket[start] != BUCKET_EMPTY) - return; - - /* Entire segment empty, release it. */ - free_locked_segment(BUCKET_ADDR(entry)); -} - -static struct thread_info *sun4c_alloc_thread_info_node(int node) -{ - unsigned long addr, pages; - int entry; - - pages = __get_free_pages(GFP_KERNEL, THREAD_INFO_ORDER); - if (!pages) - return NULL; - - for (entry = sun4c_lowbucket_avail; entry < NR_TASK_BUCKETS; entry++) - if (sun4c_bucket[entry] == BUCKET_EMPTY) - break; - if (entry == NR_TASK_BUCKETS) { - free_pages(pages, THREAD_INFO_ORDER); - return NULL; - } - if (entry >= sun4c_lowbucket_avail) - sun4c_lowbucket_avail = entry + 1; - - addr = BUCKET_ADDR(entry); - sun4c_bucket[entry] = (union task_union *) addr; - if(sun4c_get_segmap(addr) == invalid_segment) - get_locked_segment(addr); - - /* We are changing the virtual color of the page(s) - * so we must flush the cache to guarantee consistency. - */ - sun4c_flush_page(pages); - sun4c_flush_page(pages + PAGE_SIZE); - - sun4c_put_pte(addr, BUCKET_PTE(pages)); - sun4c_put_pte(addr + PAGE_SIZE, BUCKET_PTE(pages + PAGE_SIZE)); - -#ifdef CONFIG_DEBUG_STACK_USAGE - memset((void *)addr, 0, PAGE_SIZE << THREAD_INFO_ORDER); -#endif /* DEBUG_STACK_USAGE */ - - return (struct thread_info *) addr; -} - -static void sun4c_free_thread_info(struct thread_info *ti) -{ - unsigned long tiaddr = (unsigned long) ti; - unsigned long pages = BUCKET_PTE_PAGE(sun4c_get_pte(tiaddr)); - int entry = BUCKET_NUM(tiaddr); - - /* We are deleting a mapping, so the flush here is mandatory. */ - sun4c_flush_page(tiaddr); - sun4c_flush_page(tiaddr + PAGE_SIZE); - - sun4c_put_pte(tiaddr, 0); - sun4c_put_pte(tiaddr + PAGE_SIZE, 0); - - sun4c_bucket[entry] = BUCKET_EMPTY; - if (entry < sun4c_lowbucket_avail) - sun4c_lowbucket_avail = entry; - - free_pages(pages, THREAD_INFO_ORDER); - garbage_collect(entry); -} - -static void __init sun4c_init_buckets(void) -{ - int entry; - - if (sizeof(union thread_union) != (PAGE_SIZE << THREAD_INFO_ORDER)) { - extern void thread_info_size_is_bolixed_pete(void); - thread_info_size_is_bolixed_pete(); - } - - for (entry = 0; entry < NR_TASK_BUCKETS; entry++) - sun4c_bucket[entry] = BUCKET_EMPTY; - sun4c_lowbucket_avail = 0; -} - -static unsigned long sun4c_iobuffer_start; -static unsigned long sun4c_iobuffer_end; -static unsigned long sun4c_iobuffer_high; -static unsigned long *sun4c_iobuffer_map; -static int iobuffer_map_size; - -/* - * Alias our pages so they do not cause a trap. - * Also one page may be aliased into several I/O areas and we may - * finish these I/O separately. - */ -static char *sun4c_lockarea(char *vaddr, unsigned long size) -{ - unsigned long base, scan; - unsigned long npages; - unsigned long vpage; - unsigned long pte; - unsigned long apage; - unsigned long high; - unsigned long flags; - - npages = (((unsigned long)vaddr & ~PAGE_MASK) + - size + (PAGE_SIZE-1)) >> PAGE_SHIFT; - - local_irq_save(flags); - base = bitmap_find_next_zero_area(sun4c_iobuffer_map, iobuffer_map_size, - 0, npages, 0); - if (base >= iobuffer_map_size) - goto abend; - - high = ((base + npages) << PAGE_SHIFT) + sun4c_iobuffer_start; - high = SUN4C_REAL_PGDIR_ALIGN(high); - while (high > sun4c_iobuffer_high) { - get_locked_segment(sun4c_iobuffer_high); - sun4c_iobuffer_high += SUN4C_REAL_PGDIR_SIZE; - } - - vpage = ((unsigned long) vaddr) & PAGE_MASK; - for (scan = base; scan < base+npages; scan++) { - pte = ((vpage-PAGE_OFFSET) >> PAGE_SHIFT); - pte |= pgprot_val(SUN4C_PAGE_KERNEL); - pte |= _SUN4C_PAGE_NOCACHE; - set_bit(scan, sun4c_iobuffer_map); - apage = (scan << PAGE_SHIFT) + sun4c_iobuffer_start; - - /* Flush original mapping so we see the right things later. */ - sun4c_flush_page(vpage); - - sun4c_put_pte(apage, pte); - vpage += PAGE_SIZE; - } - local_irq_restore(flags); - return (char *) ((base << PAGE_SHIFT) + sun4c_iobuffer_start + - (((unsigned long) vaddr) & ~PAGE_MASK)); - -abend: - local_irq_restore(flags); - printk("DMA vaddr=0x%p size=%08lx\n", vaddr, size); - panic("Out of iobuffer table"); - return NULL; -} - -static void sun4c_unlockarea(char *vaddr, unsigned long size) -{ - unsigned long vpage, npages; - unsigned long flags; - int scan, high; - - vpage = (unsigned long)vaddr & PAGE_MASK; - npages = (((unsigned long)vaddr & ~PAGE_MASK) + - size + (PAGE_SIZE-1)) >> PAGE_SHIFT; - - local_irq_save(flags); - while (npages != 0) { - --npages; - - /* This mapping is marked non-cachable, no flush necessary. */ - sun4c_put_pte(vpage, 0); - clear_bit((vpage - sun4c_iobuffer_start) >> PAGE_SHIFT, - sun4c_iobuffer_map); - vpage += PAGE_SIZE; - } - - /* garbage collect */ - scan = (sun4c_iobuffer_high - sun4c_iobuffer_start) >> PAGE_SHIFT; - while (scan >= 0 && !sun4c_iobuffer_map[scan >> 5]) - scan -= 32; - scan += 32; - high = sun4c_iobuffer_start + (scan << PAGE_SHIFT); - high = SUN4C_REAL_PGDIR_ALIGN(high) + SUN4C_REAL_PGDIR_SIZE; - while (high < sun4c_iobuffer_high) { - sun4c_iobuffer_high -= SUN4C_REAL_PGDIR_SIZE; - free_locked_segment(sun4c_iobuffer_high); - } - local_irq_restore(flags); -} - -/* Note the scsi code at init time passes to here buffers - * which sit on the kernel stack, those are already locked - * by implication and fool the page locking code above - * if passed to by mistake. - */ -static __u32 sun4c_get_scsi_one(struct device *dev, char *bufptr, unsigned long len) -{ - unsigned long page; - - page = ((unsigned long)bufptr) & PAGE_MASK; - if (!virt_addr_valid(page)) { - sun4c_flush_page(page); - return (__u32)bufptr; /* already locked */ - } - return (__u32)sun4c_lockarea(bufptr, len); -} - -static void sun4c_get_scsi_sgl(struct device *dev, struct scatterlist *sg, int sz) -{ - while (sz != 0) { - --sz; - sg->dma_address = (__u32)sun4c_lockarea(sg_virt(sg), sg->length); - sg->dma_length = sg->length; - sg = sg_next(sg); - } -} - -static void sun4c_release_scsi_one(struct device *dev, __u32 bufptr, unsigned long len) -{ - if (bufptr < sun4c_iobuffer_start) - return; /* On kernel stack or similar, see above */ - sun4c_unlockarea((char *)bufptr, len); -} - -static void sun4c_release_scsi_sgl(struct device *dev, struct scatterlist *sg, int sz) -{ - while (sz != 0) { - --sz; - sun4c_unlockarea((char *)sg->dma_address, sg->length); - sg = sg_next(sg); - } -} - -#define TASK_ENTRY_SIZE BUCKET_SIZE /* see above */ -#define LONG_ALIGN(x) (((x)+(sizeof(long))-1)&~((sizeof(long))-1)) - -struct vm_area_struct sun4c_kstack_vma; - -static void __init sun4c_init_lock_areas(void) -{ - unsigned long sun4c_taskstack_start; - unsigned long sun4c_taskstack_end; - int bitmap_size; - - sun4c_init_buckets(); - sun4c_taskstack_start = SUN4C_LOCK_VADDR; - sun4c_taskstack_end = (sun4c_taskstack_start + - (TASK_ENTRY_SIZE * NR_TASK_BUCKETS)); - if (sun4c_taskstack_end >= SUN4C_LOCK_END) { - prom_printf("Too many tasks, decrease NR_TASK_BUCKETS please.\n"); - prom_halt(); - } - - sun4c_iobuffer_start = sun4c_iobuffer_high = - SUN4C_REAL_PGDIR_ALIGN(sun4c_taskstack_end); - sun4c_iobuffer_end = SUN4C_LOCK_END; - bitmap_size = (sun4c_iobuffer_end - sun4c_iobuffer_start) >> PAGE_SHIFT; - bitmap_size = (bitmap_size + 7) >> 3; - bitmap_size = LONG_ALIGN(bitmap_size); - iobuffer_map_size = bitmap_size << 3; - sun4c_iobuffer_map = __alloc_bootmem(bitmap_size, SMP_CACHE_BYTES, 0UL); - memset((void *) sun4c_iobuffer_map, 0, bitmap_size); - - sun4c_kstack_vma.vm_mm = &init_mm; - sun4c_kstack_vma.vm_start = sun4c_taskstack_start; - sun4c_kstack_vma.vm_end = sun4c_taskstack_end; - sun4c_kstack_vma.vm_page_prot = PAGE_SHARED; - sun4c_kstack_vma.vm_flags = VM_READ | VM_WRITE | VM_EXEC; - insert_vm_struct(&init_mm, &sun4c_kstack_vma); -} - -/* Cache flushing on the sun4c. */ -static void sun4c_flush_cache_all(void) -{ - unsigned long begin, end; - - flush_user_windows(); - begin = (KERNBASE + SUN4C_REAL_PGDIR_SIZE); - end = (begin + SUN4C_VAC_SIZE); - - if (sun4c_vacinfo.linesize == 32) { - while (begin < end) { - __asm__ __volatile__( - "ld [%0 + 0x00], %%g0\n\t" - "ld [%0 + 0x20], %%g0\n\t" - "ld [%0 + 0x40], %%g0\n\t" - "ld [%0 + 0x60], %%g0\n\t" - "ld [%0 + 0x80], %%g0\n\t" - "ld [%0 + 0xa0], %%g0\n\t" - "ld [%0 + 0xc0], %%g0\n\t" - "ld [%0 + 0xe0], %%g0\n\t" - "ld [%0 + 0x100], %%g0\n\t" - "ld [%0 + 0x120], %%g0\n\t" - "ld [%0 + 0x140], %%g0\n\t" - "ld [%0 + 0x160], %%g0\n\t" - "ld [%0 + 0x180], %%g0\n\t" - "ld [%0 + 0x1a0], %%g0\n\t" - "ld [%0 + 0x1c0], %%g0\n\t" - "ld [%0 + 0x1e0], %%g0\n" - : : "r" (begin)); - begin += 512; - } - } else { - while (begin < end) { - __asm__ __volatile__( - "ld [%0 + 0x00], %%g0\n\t" - "ld [%0 + 0x10], %%g0\n\t" - "ld [%0 + 0x20], %%g0\n\t" - "ld [%0 + 0x30], %%g0\n\t" - "ld [%0 + 0x40], %%g0\n\t" - "ld [%0 + 0x50], %%g0\n\t" - "ld [%0 + 0x60], %%g0\n\t" - "ld [%0 + 0x70], %%g0\n\t" - "ld [%0 + 0x80], %%g0\n\t" - "ld [%0 + 0x90], %%g0\n\t" - "ld [%0 + 0xa0], %%g0\n\t" - "ld [%0 + 0xb0], %%g0\n\t" - "ld [%0 + 0xc0], %%g0\n\t" - "ld [%0 + 0xd0], %%g0\n\t" - "ld [%0 + 0xe0], %%g0\n\t" - "ld [%0 + 0xf0], %%g0\n" - : : "r" (begin)); - begin += 256; - } - } -} - -static void sun4c_flush_cache_mm(struct mm_struct *mm) -{ - int new_ctx = mm->context; - - if (new_ctx != NO_CONTEXT) { - flush_user_windows(); - - if (sun4c_context_ring[new_ctx].num_entries) { - struct sun4c_mmu_entry *head = &sun4c_context_ring[new_ctx].ringhd; - unsigned long flags; - - local_irq_save(flags); - if (head->next != head) { - struct sun4c_mmu_entry *entry = head->next; - int savectx = sun4c_get_context(); - - sun4c_set_context(new_ctx); - sun4c_flush_context(); - do { - struct sun4c_mmu_entry *next = entry->next; - - sun4c_user_unmap(entry); - free_user_entry(new_ctx, entry); - - entry = next; - } while (entry != head); - sun4c_set_context(savectx); - } - local_irq_restore(flags); - } - } -} - -static void sun4c_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) -{ - struct mm_struct *mm = vma->vm_mm; - int new_ctx = mm->context; - - if (new_ctx != NO_CONTEXT) { - struct sun4c_mmu_entry *head = &sun4c_context_ring[new_ctx].ringhd; - struct sun4c_mmu_entry *entry; - unsigned long flags; - - flush_user_windows(); - - local_irq_save(flags); - /* All user segmap chains are ordered on entry->vaddr. */ - for (entry = head->next; - (entry != head) && ((entry->vaddr+SUN4C_REAL_PGDIR_SIZE) < start); - entry = entry->next) - ; - - /* Tracing various job mixtures showed that this conditional - * only passes ~35% of the time for most worse case situations, - * therefore we avoid all of this gross overhead ~65% of the time. - */ - if ((entry != head) && (entry->vaddr < end)) { - int octx = sun4c_get_context(); - sun4c_set_context(new_ctx); - - /* At this point, always, (start >= entry->vaddr) and - * (entry->vaddr < end), once the latter condition - * ceases to hold, or we hit the end of the list, we - * exit the loop. The ordering of all user allocated - * segmaps makes this all work out so beautifully. - */ - do { - struct sun4c_mmu_entry *next = entry->next; - unsigned long realend; - - /* "realstart" is always >= entry->vaddr */ - realend = entry->vaddr + SUN4C_REAL_PGDIR_SIZE; - if (end < realend) - realend = end; - if ((realend - entry->vaddr) <= (PAGE_SIZE << 3)) { - unsigned long page = entry->vaddr; - while (page < realend) { - sun4c_flush_page(page); - page += PAGE_SIZE; - } - } else { - sun4c_flush_segment(entry->vaddr); - sun4c_user_unmap(entry); - free_user_entry(new_ctx, entry); - } - entry = next; - } while ((entry != head) && (entry->vaddr < end)); - sun4c_set_context(octx); - } - local_irq_restore(flags); - } -} - -static void sun4c_flush_cache_page(struct vm_area_struct *vma, unsigned long page) -{ - struct mm_struct *mm = vma->vm_mm; - int new_ctx = mm->context; - - /* Sun4c has no separate I/D caches so cannot optimize for non - * text page flushes. - */ - if (new_ctx != NO_CONTEXT) { - int octx = sun4c_get_context(); - unsigned long flags; - - flush_user_windows(); - local_irq_save(flags); - sun4c_set_context(new_ctx); - sun4c_flush_page(page); - sun4c_set_context(octx); - local_irq_restore(flags); - } -} - -static void sun4c_flush_page_to_ram(unsigned long page) -{ - unsigned long flags; - - local_irq_save(flags); - sun4c_flush_page(page); - local_irq_restore(flags); -} - -/* Sun4c cache is unified, both instructions and data live there, so - * no need to flush the on-stack instructions for new signal handlers. - */ -static void sun4c_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr) -{ -} - -/* TLB flushing on the sun4c. These routines count on the cache - * flushing code to flush the user register windows so that we need - * not do so when we get here. - */ - -static void sun4c_flush_tlb_all(void) -{ - struct sun4c_mmu_entry *this_entry, *next_entry; - unsigned long flags; - int savectx, ctx; - - local_irq_save(flags); - this_entry = sun4c_kernel_ring.ringhd.next; - savectx = sun4c_get_context(); - flush_user_windows(); - while (sun4c_kernel_ring.num_entries) { - next_entry = this_entry->next; - sun4c_flush_segment(this_entry->vaddr); - for (ctx = 0; ctx < num_contexts; ctx++) { - sun4c_set_context(ctx); - sun4c_put_segmap(this_entry->vaddr, invalid_segment); - } - free_kernel_entry(this_entry, &sun4c_kernel_ring); - this_entry = next_entry; - } - sun4c_set_context(savectx); - local_irq_restore(flags); -} - -static void sun4c_flush_tlb_mm(struct mm_struct *mm) -{ - int new_ctx = mm->context; - - if (new_ctx != NO_CONTEXT) { - struct sun4c_mmu_entry *head = &sun4c_context_ring[new_ctx].ringhd; - unsigned long flags; - - local_irq_save(flags); - if (head->next != head) { - struct sun4c_mmu_entry *entry = head->next; - int savectx = sun4c_get_context(); - - sun4c_set_context(new_ctx); - sun4c_flush_context(); - do { - struct sun4c_mmu_entry *next = entry->next; - - sun4c_user_unmap(entry); - free_user_entry(new_ctx, entry); - - entry = next; - } while (entry != head); - sun4c_set_context(savectx); - } - local_irq_restore(flags); - } -} - -static void sun4c_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) -{ - struct mm_struct *mm = vma->vm_mm; - int new_ctx = mm->context; - - if (new_ctx != NO_CONTEXT) { - struct sun4c_mmu_entry *head = &sun4c_context_ring[new_ctx].ringhd; - struct sun4c_mmu_entry *entry; - unsigned long flags; - - local_irq_save(flags); - /* See commentary in sun4c_flush_cache_range(). */ - for (entry = head->next; - (entry != head) && ((entry->vaddr+SUN4C_REAL_PGDIR_SIZE) < start); - entry = entry->next) - ; - - if ((entry != head) && (entry->vaddr < end)) { - int octx = sun4c_get_context(); - - sun4c_set_context(new_ctx); - do { - struct sun4c_mmu_entry *next = entry->next; - - sun4c_flush_segment(entry->vaddr); - sun4c_user_unmap(entry); - free_user_entry(new_ctx, entry); - - entry = next; - } while ((entry != head) && (entry->vaddr < end)); - sun4c_set_context(octx); - } - local_irq_restore(flags); - } -} - -static void sun4c_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) -{ - struct mm_struct *mm = vma->vm_mm; - int new_ctx = mm->context; - - if (new_ctx != NO_CONTEXT) { - int savectx = sun4c_get_context(); - unsigned long flags; - - local_irq_save(flags); - sun4c_set_context(new_ctx); - page &= PAGE_MASK; - sun4c_flush_page(page); - sun4c_put_pte(page, 0); - sun4c_set_context(savectx); - local_irq_restore(flags); - } -} - -static inline void sun4c_mapioaddr(unsigned long physaddr, unsigned long virt_addr) -{ - unsigned long page_entry, pg_iobits; - - pg_iobits = _SUN4C_PAGE_PRESENT | _SUN4C_READABLE | _SUN4C_WRITEABLE | - _SUN4C_PAGE_IO | _SUN4C_PAGE_NOCACHE; - - page_entry = ((physaddr >> PAGE_SHIFT) & SUN4C_PFN_MASK); - page_entry |= ((pg_iobits | _SUN4C_PAGE_PRIV) & ~(_SUN4C_PAGE_PRESENT)); - sun4c_put_pte(virt_addr, page_entry); -} - -static void sun4c_mapiorange(unsigned int bus, unsigned long xpa, - unsigned long xva, unsigned int len) -{ - while (len != 0) { - len -= PAGE_SIZE; - sun4c_mapioaddr(xpa, xva); - xva += PAGE_SIZE; - xpa += PAGE_SIZE; - } -} - -static void sun4c_unmapiorange(unsigned long virt_addr, unsigned int len) -{ - while (len != 0) { - len -= PAGE_SIZE; - sun4c_put_pte(virt_addr, 0); - virt_addr += PAGE_SIZE; - } -} - -static void sun4c_alloc_context(struct mm_struct *old_mm, struct mm_struct *mm) -{ - struct ctx_list *ctxp; - - ctxp = ctx_free.next; - if (ctxp != &ctx_free) { - remove_from_ctx_list(ctxp); - add_to_used_ctxlist(ctxp); - mm->context = ctxp->ctx_number; - ctxp->ctx_mm = mm; - return; - } - ctxp = ctx_used.next; - if (ctxp->ctx_mm == old_mm) - ctxp = ctxp->next; - remove_from_ctx_list(ctxp); - add_to_used_ctxlist(ctxp); - ctxp->ctx_mm->context = NO_CONTEXT; - ctxp->ctx_mm = mm; - mm->context = ctxp->ctx_number; - sun4c_demap_context(&sun4c_context_ring[ctxp->ctx_number], - ctxp->ctx_number); -} - -/* Switch the current MM context. */ -static void sun4c_switch_mm(struct mm_struct *old_mm, struct mm_struct *mm, struct task_struct *tsk, int cpu) -{ - struct ctx_list *ctx; - int dirty = 0; - - if (mm->context == NO_CONTEXT) { - dirty = 1; - sun4c_alloc_context(old_mm, mm); - } else { - /* Update the LRU ring of contexts. */ - ctx = ctx_list_pool + mm->context; - remove_from_ctx_list(ctx); - add_to_used_ctxlist(ctx); - } - if (dirty || old_mm != mm) - sun4c_set_context(mm->context); -} - -static void sun4c_destroy_context(struct mm_struct *mm) -{ - struct ctx_list *ctx_old; - - if (mm->context != NO_CONTEXT) { - sun4c_demap_context(&sun4c_context_ring[mm->context], mm->context); - ctx_old = ctx_list_pool + mm->context; - remove_from_ctx_list(ctx_old); - add_to_free_ctxlist(ctx_old); - mm->context = NO_CONTEXT; - } -} - -static void sun4c_mmu_info(struct seq_file *m) -{ - int used_user_entries, i; - - used_user_entries = 0; - for (i = 0; i < num_contexts; i++) - used_user_entries += sun4c_context_ring[i].num_entries; - - seq_printf(m, - "vacsize\t\t: %d bytes\n" - "vachwflush\t: %s\n" - "vaclinesize\t: %d bytes\n" - "mmuctxs\t\t: %d\n" - "mmupsegs\t: %d\n" - "kernelpsegs\t: %d\n" - "kfreepsegs\t: %d\n" - "usedpsegs\t: %d\n" - "ufreepsegs\t: %d\n" - "user_taken\t: %d\n" - "max_taken\t: %d\n", - sun4c_vacinfo.num_bytes, - (sun4c_vacinfo.do_hwflushes ? "yes" : "no"), - sun4c_vacinfo.linesize, - num_contexts, - (invalid_segment + 1), - sun4c_kernel_ring.num_entries, - sun4c_kfree_ring.num_entries, - used_user_entries, - sun4c_ufree_ring.num_entries, - sun4c_user_taken_entries, - max_user_taken_entries); -} - -/* Nothing below here should touch the mmu hardware nor the mmu_entry - * data structures. - */ - -/* First the functions which the mid-level code uses to directly - * manipulate the software page tables. Some defines since we are - * emulating the i386 page directory layout. - */ -#define PGD_PRESENT 0x001 -#define PGD_RW 0x002 -#define PGD_USER 0x004 -#define PGD_ACCESSED 0x020 -#define PGD_DIRTY 0x040 -#define PGD_TABLE (PGD_PRESENT | PGD_RW | PGD_USER | PGD_ACCESSED | PGD_DIRTY) - -static void sun4c_set_pte(pte_t *ptep, pte_t pte) -{ - *ptep = pte; -} - -static void sun4c_pgd_set(pgd_t * pgdp, pmd_t * pmdp) -{ -} - -static void sun4c_pmd_set(pmd_t * pmdp, pte_t * ptep) -{ - pmdp->pmdv[0] = PGD_TABLE | (unsigned long) ptep; -} - -static void sun4c_pmd_populate(pmd_t * pmdp, struct page * ptep) -{ - if (page_address(ptep) == NULL) BUG(); /* No highmem on sun4c */ - pmdp->pmdv[0] = PGD_TABLE | (unsigned long) page_address(ptep); -} - -static int sun4c_pte_present(pte_t pte) -{ - return ((pte_val(pte) & (_SUN4C_PAGE_PRESENT | _SUN4C_PAGE_PRIV)) != 0); -} -static void sun4c_pte_clear(pte_t *ptep) { *ptep = __pte(0); } - -static int sun4c_pmd_bad(pmd_t pmd) -{ - return (((pmd_val(pmd) & ~PAGE_MASK) != PGD_TABLE) || - (!virt_addr_valid(pmd_val(pmd)))); -} - -static int sun4c_pmd_present(pmd_t pmd) -{ - return ((pmd_val(pmd) & PGD_PRESENT) != 0); -} - -#if 0 /* if PMD takes one word */ -static void sun4c_pmd_clear(pmd_t *pmdp) { *pmdp = __pmd(0); } -#else /* if pmd_t is a longish aggregate */ -static void sun4c_pmd_clear(pmd_t *pmdp) { - memset((void *)pmdp, 0, sizeof(pmd_t)); -} -#endif - -static int sun4c_pgd_none(pgd_t pgd) { return 0; } -static int sun4c_pgd_bad(pgd_t pgd) { return 0; } -static int sun4c_pgd_present(pgd_t pgd) { return 1; } -static void sun4c_pgd_clear(pgd_t * pgdp) { } - -/* - * The following only work if pte_present() is true. - * Undefined behaviour if not.. - */ -static pte_t sun4c_pte_mkwrite(pte_t pte) -{ - pte = __pte(pte_val(pte) | _SUN4C_PAGE_WRITE); - if (pte_val(pte) & _SUN4C_PAGE_MODIFIED) - pte = __pte(pte_val(pte) | _SUN4C_PAGE_SILENT_WRITE); - return pte; -} - -static pte_t sun4c_pte_mkdirty(pte_t pte) -{ - pte = __pte(pte_val(pte) | _SUN4C_PAGE_MODIFIED); - if (pte_val(pte) & _SUN4C_PAGE_WRITE) - pte = __pte(pte_val(pte) | _SUN4C_PAGE_SILENT_WRITE); - return pte; -} - -static pte_t sun4c_pte_mkyoung(pte_t pte) -{ - pte = __pte(pte_val(pte) | _SUN4C_PAGE_ACCESSED); - if (pte_val(pte) & _SUN4C_PAGE_READ) - pte = __pte(pte_val(pte) | _SUN4C_PAGE_SILENT_READ); - return pte; -} - -/* - * Conversion functions: convert a page and protection to a page entry, - * and a page entry and page directory to the page they refer to. - */ -static pte_t sun4c_mk_pte(struct page *page, pgprot_t pgprot) -{ - return __pte(page_to_pfn(page) | pgprot_val(pgprot)); -} - -static pte_t sun4c_mk_pte_phys(unsigned long phys_page, pgprot_t pgprot) -{ - return __pte((phys_page >> PAGE_SHIFT) | pgprot_val(pgprot)); -} - -static pte_t sun4c_mk_pte_io(unsigned long page, pgprot_t pgprot, int space) -{ - return __pte(((page - PAGE_OFFSET) >> PAGE_SHIFT) | pgprot_val(pgprot)); -} - -static unsigned long sun4c_pte_pfn(pte_t pte) -{ - return pte_val(pte) & SUN4C_PFN_MASK; -} - -static pte_t sun4c_pgoff_to_pte(unsigned long pgoff) -{ - return __pte(pgoff | _SUN4C_PAGE_FILE); -} - -static unsigned long sun4c_pte_to_pgoff(pte_t pte) -{ - return pte_val(pte) & ((1UL << PTE_FILE_MAX_BITS) - 1); -} - - -static inline unsigned long sun4c_pmd_page_v(pmd_t pmd) -{ - return (pmd_val(pmd) & PAGE_MASK); -} - -static struct page *sun4c_pmd_page(pmd_t pmd) -{ - return virt_to_page(sun4c_pmd_page_v(pmd)); -} - -static unsigned long sun4c_pgd_page(pgd_t pgd) { return 0; } - -/* to find an entry in a page-table-directory */ -static inline pgd_t *sun4c_pgd_offset(struct mm_struct * mm, unsigned long address) -{ - return mm->pgd + (address >> SUN4C_PGDIR_SHIFT); -} - -/* Find an entry in the second-level page table.. */ -static pmd_t *sun4c_pmd_offset(pgd_t * dir, unsigned long address) -{ - return (pmd_t *) dir; -} - -/* Find an entry in the third-level page table.. */ -pte_t *sun4c_pte_offset_kernel(pmd_t * dir, unsigned long address) -{ - return (pte_t *) sun4c_pmd_page_v(*dir) + - ((address >> PAGE_SHIFT) & (SUN4C_PTRS_PER_PTE - 1)); -} - -static unsigned long sun4c_swp_type(swp_entry_t entry) -{ - return (entry.val & SUN4C_SWP_TYPE_MASK); -} - -static unsigned long sun4c_swp_offset(swp_entry_t entry) -{ - return (entry.val >> SUN4C_SWP_OFF_SHIFT) & SUN4C_SWP_OFF_MASK; -} - -static swp_entry_t sun4c_swp_entry(unsigned long type, unsigned long offset) -{ - return (swp_entry_t) { - (offset & SUN4C_SWP_OFF_MASK) << SUN4C_SWP_OFF_SHIFT - | (type & SUN4C_SWP_TYPE_MASK) }; -} - -static void sun4c_free_pte_slow(pte_t *pte) -{ - free_page((unsigned long)pte); -} - -static void sun4c_free_pgd_slow(pgd_t *pgd) -{ - free_page((unsigned long)pgd); -} - -static pgd_t *sun4c_get_pgd_fast(void) -{ - unsigned long *ret; - - if ((ret = pgd_quicklist) != NULL) { - pgd_quicklist = (unsigned long *)(*ret); - ret[0] = ret[1]; - pgtable_cache_size--; - } else { - pgd_t *init; - - ret = (unsigned long *)__get_free_page(GFP_KERNEL); - memset (ret, 0, (KERNBASE / SUN4C_PGDIR_SIZE) * sizeof(pgd_t)); - init = sun4c_pgd_offset(&init_mm, 0); - memcpy (((pgd_t *)ret) + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD, - (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t)); - } - return (pgd_t *)ret; -} - -static void sun4c_free_pgd_fast(pgd_t *pgd) -{ - *(unsigned long *)pgd = (unsigned long) pgd_quicklist; - pgd_quicklist = (unsigned long *) pgd; - pgtable_cache_size++; -} - - -static inline pte_t * -sun4c_pte_alloc_one_fast(struct mm_struct *mm, unsigned long address) -{ - unsigned long *ret; - - if ((ret = (unsigned long *)pte_quicklist) != NULL) { - pte_quicklist = (unsigned long *)(*ret); - ret[0] = ret[1]; - pgtable_cache_size--; - } - return (pte_t *)ret; -} - -static pte_t *sun4c_pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address) -{ - pte_t *pte; - - if ((pte = sun4c_pte_alloc_one_fast(mm, address)) != NULL) - return pte; - - pte = (pte_t *)get_zeroed_page(GFP_KERNEL|__GFP_REPEAT); - return pte; -} - -static pgtable_t sun4c_pte_alloc_one(struct mm_struct *mm, unsigned long address) -{ - pte_t *pte; - struct page *page; - - pte = sun4c_pte_alloc_one_kernel(mm, address); - if (pte == NULL) - return NULL; - page = virt_to_page(pte); - pgtable_page_ctor(page); - return page; -} - -static inline void sun4c_free_pte_fast(pte_t *pte) -{ - *(unsigned long *)pte = (unsigned long) pte_quicklist; - pte_quicklist = (unsigned long *) pte; - pgtable_cache_size++; -} - -static void sun4c_pte_free(pgtable_t pte) -{ - pgtable_page_dtor(pte); - sun4c_free_pte_fast(page_address(pte)); -} - -/* - * allocating and freeing a pmd is trivial: the 1-entry pmd is - * inside the pgd, so has no extra memory associated with it. - */ -static pmd_t *sun4c_pmd_alloc_one(struct mm_struct *mm, unsigned long address) -{ - BUG(); - return NULL; -} - -static void sun4c_free_pmd_fast(pmd_t * pmd) { } - -static void sun4c_check_pgt_cache(int low, int high) -{ - if (pgtable_cache_size > high) { - do { - if (pgd_quicklist) - sun4c_free_pgd_slow(sun4c_get_pgd_fast()); - if (pte_quicklist) - sun4c_free_pte_slow(sun4c_pte_alloc_one_fast(NULL, 0)); - } while (pgtable_cache_size > low); - } -} - -/* An experiment, turn off by default for now... -DaveM */ -#define SUN4C_PRELOAD_PSEG - -void sun4c_update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep) -{ - unsigned long flags; - int pseg; - - if (vma->vm_mm->context == NO_CONTEXT) - return; - - local_irq_save(flags); - address &= PAGE_MASK; - if ((pseg = sun4c_get_segmap(address)) == invalid_segment) { - struct sun4c_mmu_entry *entry = sun4c_user_strategy(); - struct mm_struct *mm = vma->vm_mm; - unsigned long start, end; - - entry->vaddr = start = (address & SUN4C_REAL_PGDIR_MASK); - entry->ctx = mm->context; - add_ring_ordered(sun4c_context_ring + mm->context, entry); - sun4c_put_segmap(entry->vaddr, entry->pseg); - end = start + SUN4C_REAL_PGDIR_SIZE; - while (start < end) { -#ifdef SUN4C_PRELOAD_PSEG - pgd_t *pgdp = sun4c_pgd_offset(mm, start); - pte_t *ptep; - - if (!pgdp) - goto no_mapping; - ptep = sun4c_pte_offset_kernel((pmd_t *) pgdp, start); - if (!ptep || !(pte_val(*ptep) & _SUN4C_PAGE_PRESENT)) - goto no_mapping; - sun4c_put_pte(start, pte_val(*ptep)); - goto next; - - no_mapping: -#endif - sun4c_put_pte(start, 0); -#ifdef SUN4C_PRELOAD_PSEG - next: -#endif - start += PAGE_SIZE; - } -#ifndef SUN4C_PRELOAD_PSEG - sun4c_put_pte(address, pte_val(*ptep)); -#endif - local_irq_restore(flags); - return; - } else { - struct sun4c_mmu_entry *entry = &mmu_entry_pool[pseg]; - - remove_lru(entry); - add_lru(entry); - } - - sun4c_put_pte(address, pte_val(*ptep)); - local_irq_restore(flags); -} - -extern void sparc_context_init(int); -extern unsigned long bootmem_init(unsigned long *pages_avail); -extern unsigned long last_valid_pfn; - -void __init sun4c_paging_init(void) -{ - int i, cnt; - unsigned long kernel_end, vaddr; - extern struct resource sparc_iomap; - unsigned long end_pfn, pages_avail; - - kernel_end = (unsigned long) &_end; - kernel_end = SUN4C_REAL_PGDIR_ALIGN(kernel_end); - - pages_avail = 0; - last_valid_pfn = bootmem_init(&pages_avail); - end_pfn = last_valid_pfn; - - sun4c_probe_mmu(); - invalid_segment = (num_segmaps - 1); - sun4c_init_mmu_entry_pool(); - sun4c_init_rings(); - sun4c_init_map_kernelprom(kernel_end); - sun4c_init_clean_mmu(kernel_end); - sun4c_init_fill_kernel_ring(SUN4C_KERNEL_BUCKETS); - sun4c_init_lock_area(sparc_iomap.start, IOBASE_END); - sun4c_init_lock_area(DVMA_VADDR, DVMA_END); - sun4c_init_lock_areas(); - sun4c_init_fill_user_ring(); - - sun4c_set_context(0); - memset(swapper_pg_dir, 0, PAGE_SIZE); - memset(pg0, 0, PAGE_SIZE); - memset(pg1, 0, PAGE_SIZE); - memset(pg2, 0, PAGE_SIZE); - memset(pg3, 0, PAGE_SIZE); - - /* Save work later. */ - vaddr = VMALLOC_START; - swapper_pg_dir[vaddr>>SUN4C_PGDIR_SHIFT] = __pgd(PGD_TABLE | (unsigned long) pg0); - vaddr += SUN4C_PGDIR_SIZE; - swapper_pg_dir[vaddr>>SUN4C_PGDIR_SHIFT] = __pgd(PGD_TABLE | (unsigned long) pg1); - vaddr += SUN4C_PGDIR_SIZE; - swapper_pg_dir[vaddr>>SUN4C_PGDIR_SHIFT] = __pgd(PGD_TABLE | (unsigned long) pg2); - vaddr += SUN4C_PGDIR_SIZE; - swapper_pg_dir[vaddr>>SUN4C_PGDIR_SHIFT] = __pgd(PGD_TABLE | (unsigned long) pg3); - sun4c_init_ss2_cache_bug(); - sparc_context_init(num_contexts); - - { - unsigned long zones_size[MAX_NR_ZONES]; - unsigned long zholes_size[MAX_NR_ZONES]; - unsigned long npages; - int znum; - - for (znum = 0; znum < MAX_NR_ZONES; znum++) - zones_size[znum] = zholes_size[znum] = 0; - - npages = max_low_pfn - pfn_base; - - zones_size[ZONE_DMA] = npages; - zholes_size[ZONE_DMA] = npages - pages_avail; - - npages = highend_pfn - max_low_pfn; - zones_size[ZONE_HIGHMEM] = npages; - zholes_size[ZONE_HIGHMEM] = npages - calc_highpages(); - - free_area_init_node(0, zones_size, pfn_base, zholes_size); - } - - cnt = 0; - for (i = 0; i < num_segmaps; i++) - if (mmu_entry_pool[i].locked) - cnt++; - - max_user_taken_entries = num_segmaps - cnt - 40 - 1; - - printk("SUN4C: %d mmu entries for the kernel\n", cnt); -} - -static pgprot_t sun4c_pgprot_noncached(pgprot_t prot) -{ - prot |= __pgprot(_SUN4C_PAGE_IO | _SUN4C_PAGE_NOCACHE); - - return prot; -} - -/* Load up routines and constants for sun4c mmu */ -void __init ld_mmu_sun4c(void) -{ - extern void ___xchg32_sun4c(void); - - printk("Loading sun4c MMU routines\n"); - - /* First the constants */ - BTFIXUPSET_SIMM13(pgdir_shift, SUN4C_PGDIR_SHIFT); - BTFIXUPSET_SETHI(pgdir_size, SUN4C_PGDIR_SIZE); - BTFIXUPSET_SETHI(pgdir_mask, SUN4C_PGDIR_MASK); - - BTFIXUPSET_SIMM13(ptrs_per_pmd, SUN4C_PTRS_PER_PMD); - BTFIXUPSET_SIMM13(ptrs_per_pgd, SUN4C_PTRS_PER_PGD); - BTFIXUPSET_SIMM13(user_ptrs_per_pgd, KERNBASE / SUN4C_PGDIR_SIZE); - - BTFIXUPSET_INT(page_none, pgprot_val(SUN4C_PAGE_NONE)); - PAGE_SHARED = pgprot_val(SUN4C_PAGE_SHARED); - BTFIXUPSET_INT(page_copy, pgprot_val(SUN4C_PAGE_COPY)); - BTFIXUPSET_INT(page_readonly, pgprot_val(SUN4C_PAGE_READONLY)); - BTFIXUPSET_INT(page_kernel, pgprot_val(SUN4C_PAGE_KERNEL)); - page_kernel = pgprot_val(SUN4C_PAGE_KERNEL); - - /* Functions */ - BTFIXUPSET_CALL(pgprot_noncached, sun4c_pgprot_noncached, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(___xchg32, ___xchg32_sun4c, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(do_check_pgt_cache, sun4c_check_pgt_cache, BTFIXUPCALL_NORM); - - BTFIXUPSET_CALL(flush_cache_all, sun4c_flush_cache_all, BTFIXUPCALL_NORM); - - if (sun4c_vacinfo.do_hwflushes) { - BTFIXUPSET_CALL(sun4c_flush_page, sun4c_flush_page_hw, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(sun4c_flush_segment, sun4c_flush_segment_hw, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(sun4c_flush_context, sun4c_flush_context_hw, BTFIXUPCALL_NORM); - } else { - BTFIXUPSET_CALL(sun4c_flush_page, sun4c_flush_page_sw, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(sun4c_flush_segment, sun4c_flush_segment_sw, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(sun4c_flush_context, sun4c_flush_context_sw, BTFIXUPCALL_NORM); - } - - BTFIXUPSET_CALL(flush_tlb_mm, sun4c_flush_tlb_mm, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_cache_mm, sun4c_flush_cache_mm, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(destroy_context, sun4c_destroy_context, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(switch_mm, sun4c_switch_mm, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_cache_page, sun4c_flush_cache_page, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_tlb_page, sun4c_flush_tlb_page, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_tlb_range, sun4c_flush_tlb_range, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_cache_range, sun4c_flush_cache_range, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(__flush_page_to_ram, sun4c_flush_page_to_ram, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(flush_tlb_all, sun4c_flush_tlb_all, BTFIXUPCALL_NORM); - - BTFIXUPSET_CALL(flush_sig_insns, sun4c_flush_sig_insns, BTFIXUPCALL_NOP); - - BTFIXUPSET_CALL(set_pte, sun4c_set_pte, BTFIXUPCALL_STO1O0); - - BTFIXUPSET_CALL(pte_pfn, sun4c_pte_pfn, BTFIXUPCALL_NORM); -#if 0 /* PAGE_SHIFT <= 12 */ /* Eek. Investigate. XXX */ - BTFIXUPSET_CALL(pmd_page, sun4c_pmd_page, BTFIXUPCALL_ANDNINT(PAGE_SIZE - 1)); -#else - BTFIXUPSET_CALL(pmd_page, sun4c_pmd_page, BTFIXUPCALL_NORM); -#endif - BTFIXUPSET_CALL(pmd_set, sun4c_pmd_set, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(pmd_populate, sun4c_pmd_populate, BTFIXUPCALL_NORM); - - BTFIXUPSET_CALL(pte_present, sun4c_pte_present, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(pte_clear, sun4c_pte_clear, BTFIXUPCALL_STG0O0); - - BTFIXUPSET_CALL(pmd_bad, sun4c_pmd_bad, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(pmd_present, sun4c_pmd_present, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(pmd_clear, sun4c_pmd_clear, BTFIXUPCALL_STG0O0); - - BTFIXUPSET_CALL(pgd_none, sun4c_pgd_none, BTFIXUPCALL_RETINT(0)); - BTFIXUPSET_CALL(pgd_bad, sun4c_pgd_bad, BTFIXUPCALL_RETINT(0)); - BTFIXUPSET_CALL(pgd_present, sun4c_pgd_present, BTFIXUPCALL_RETINT(1)); - BTFIXUPSET_CALL(pgd_clear, sun4c_pgd_clear, BTFIXUPCALL_NOP); - - BTFIXUPSET_CALL(mk_pte, sun4c_mk_pte, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(mk_pte_phys, sun4c_mk_pte_phys, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(mk_pte_io, sun4c_mk_pte_io, BTFIXUPCALL_NORM); - - BTFIXUPSET_INT(pte_modify_mask, _SUN4C_PAGE_CHG_MASK); - BTFIXUPSET_CALL(pmd_offset, sun4c_pmd_offset, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(pte_offset_kernel, sun4c_pte_offset_kernel, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(free_pte_fast, sun4c_free_pte_fast, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(pte_free, sun4c_pte_free, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(pte_alloc_one_kernel, sun4c_pte_alloc_one_kernel, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(pte_alloc_one, sun4c_pte_alloc_one, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(free_pmd_fast, sun4c_free_pmd_fast, BTFIXUPCALL_NOP); - BTFIXUPSET_CALL(pmd_alloc_one, sun4c_pmd_alloc_one, BTFIXUPCALL_RETO0); - BTFIXUPSET_CALL(free_pgd_fast, sun4c_free_pgd_fast, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(get_pgd_fast, sun4c_get_pgd_fast, BTFIXUPCALL_NORM); - - BTFIXUPSET_HALF(pte_writei, _SUN4C_PAGE_WRITE); - BTFIXUPSET_HALF(pte_dirtyi, _SUN4C_PAGE_MODIFIED); - BTFIXUPSET_HALF(pte_youngi, _SUN4C_PAGE_ACCESSED); - BTFIXUPSET_HALF(pte_filei, _SUN4C_PAGE_FILE); - BTFIXUPSET_HALF(pte_wrprotecti, _SUN4C_PAGE_WRITE|_SUN4C_PAGE_SILENT_WRITE); - BTFIXUPSET_HALF(pte_mkcleani, _SUN4C_PAGE_MODIFIED|_SUN4C_PAGE_SILENT_WRITE); - BTFIXUPSET_HALF(pte_mkoldi, _SUN4C_PAGE_ACCESSED|_SUN4C_PAGE_SILENT_READ); - BTFIXUPSET_CALL(pte_mkwrite, sun4c_pte_mkwrite, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(pte_mkdirty, sun4c_pte_mkdirty, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(pte_mkyoung, sun4c_pte_mkyoung, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(update_mmu_cache, sun4c_update_mmu_cache, BTFIXUPCALL_NORM); - - BTFIXUPSET_CALL(pte_to_pgoff, sun4c_pte_to_pgoff, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(pgoff_to_pte, sun4c_pgoff_to_pte, BTFIXUPCALL_NORM); - - BTFIXUPSET_CALL(mmu_lockarea, sun4c_lockarea, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(mmu_unlockarea, sun4c_unlockarea, BTFIXUPCALL_NORM); - - BTFIXUPSET_CALL(mmu_get_scsi_one, sun4c_get_scsi_one, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(mmu_get_scsi_sgl, sun4c_get_scsi_sgl, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(mmu_release_scsi_one, sun4c_release_scsi_one, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(mmu_release_scsi_sgl, sun4c_release_scsi_sgl, BTFIXUPCALL_NORM); - - BTFIXUPSET_CALL(mmu_map_dma_area, sun4c_map_dma_area, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(mmu_unmap_dma_area, sun4c_unmap_dma_area, BTFIXUPCALL_NORM); - - BTFIXUPSET_CALL(sparc_mapiorange, sun4c_mapiorange, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(sparc_unmapiorange, sun4c_unmapiorange, BTFIXUPCALL_NORM); - - BTFIXUPSET_CALL(__swp_type, sun4c_swp_type, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(__swp_offset, sun4c_swp_offset, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(__swp_entry, sun4c_swp_entry, BTFIXUPCALL_NORM); - - BTFIXUPSET_CALL(alloc_thread_info_node, sun4c_alloc_thread_info_node, BTFIXUPCALL_NORM); - BTFIXUPSET_CALL(free_thread_info, sun4c_free_thread_info, BTFIXUPCALL_NORM); - - BTFIXUPSET_CALL(mmu_info, sun4c_mmu_info, BTFIXUPCALL_NORM); - - /* These should _never_ get called with two level tables. */ - BTFIXUPSET_CALL(pgd_set, sun4c_pgd_set, BTFIXUPCALL_NOP); - BTFIXUPSET_CALL(pgd_page_vaddr, sun4c_pgd_page, BTFIXUPCALL_RETO0); -} diff --git a/arch/sparc/mm/ultra.S b/arch/sparc/mm/ultra.S index b57a5942ba64..874162a11ceb 100644 --- a/arch/sparc/mm/ultra.S +++ b/arch/sparc/mm/ultra.S @@ -495,11 +495,11 @@ xcall_fetch_glob_regs: stx %o7, [%g1 + GR_SNAP_O7] stx %i7, [%g1 + GR_SNAP_I7] /* Don't try this at home kids... */ - rdpr %cwp, %g2 - sub %g2, 1, %g7 + rdpr %cwp, %g3 + sub %g3, 1, %g7 wrpr %g7, %cwp mov %i7, %g7 - wrpr %g2, %cwp + wrpr %g3, %cwp stx %g7, [%g1 + GR_SNAP_RPC] sethi %hi(trap_block), %g7 or %g7, %lo(trap_block), %g7 diff --git a/arch/sparc/mm/viking.S b/arch/sparc/mm/viking.S index 6dfcc13d3100..bf8ee0613ae7 100644 --- a/arch/sparc/mm/viking.S +++ b/arch/sparc/mm/viking.S @@ -14,7 +14,6 @@ #include <asm/page.h> #include <asm/pgtsrmmu.h> #include <asm/viking.h> -#include <asm/btfixup.h> #ifdef CONFIG_SMP .data diff --git a/arch/sparc/net/Makefile b/arch/sparc/net/Makefile new file mode 100644 index 000000000000..1306a58ac541 --- /dev/null +++ b/arch/sparc/net/Makefile @@ -0,0 +1,4 @@ +# +# Arch-specific network modules +# +obj-$(CONFIG_BPF_JIT) += bpf_jit_asm.o bpf_jit_comp.o diff --git a/arch/sparc/net/bpf_jit.h b/arch/sparc/net/bpf_jit.h new file mode 100644 index 000000000000..33d6b375ff12 --- /dev/null +++ b/arch/sparc/net/bpf_jit.h @@ -0,0 +1,68 @@ +#ifndef _BPF_JIT_H +#define _BPF_JIT_H + +/* Conventions: + * %g1 : temporary + * %g2 : Secondary temporary used by SKB data helper stubs. + * %g3 : packet offset passed into SKB data helper stubs. + * %o0 : pointer to skb (first argument given to JIT function) + * %o1 : BPF A accumulator + * %o2 : BPF X accumulator + * %o3 : Holds saved %o7 so we can call helper functions without needing + * to allocate a register window. + * %o4 : skb->len - skb->data_len + * %o5 : skb->data + */ + +#ifndef __ASSEMBLER__ +#define G0 0x00 +#define G1 0x01 +#define G3 0x03 +#define G6 0x06 +#define O0 0x08 +#define O1 0x09 +#define O2 0x0a +#define O3 0x0b +#define O4 0x0c +#define O5 0x0d +#define SP 0x0e +#define O7 0x0f +#define FP 0x1e + +#define r_SKB O0 +#define r_A O1 +#define r_X O2 +#define r_saved_O7 O3 +#define r_HEADLEN O4 +#define r_SKB_DATA O5 +#define r_TMP G1 +#define r_TMP2 G2 +#define r_OFF G3 + +/* assembly code in arch/sparc/net/bpf_jit_asm.S */ +extern u32 bpf_jit_load_word[]; +extern u32 bpf_jit_load_half[]; +extern u32 bpf_jit_load_byte[]; +extern u32 bpf_jit_load_byte_msh[]; +extern u32 bpf_jit_load_word_positive_offset[]; +extern u32 bpf_jit_load_half_positive_offset[]; +extern u32 bpf_jit_load_byte_positive_offset[]; +extern u32 bpf_jit_load_byte_msh_positive_offset[]; +extern u32 bpf_jit_load_word_negative_offset[]; +extern u32 bpf_jit_load_half_negative_offset[]; +extern u32 bpf_jit_load_byte_negative_offset[]; +extern u32 bpf_jit_load_byte_msh_negative_offset[]; + +#else +#define r_SKB %o0 +#define r_A %o1 +#define r_X %o2 +#define r_saved_O7 %o3 +#define r_HEADLEN %o4 +#define r_SKB_DATA %o5 +#define r_TMP %g1 +#define r_TMP2 %g2 +#define r_OFF %g3 +#endif + +#endif /* _BPF_JIT_H */ diff --git a/arch/sparc/net/bpf_jit_asm.S b/arch/sparc/net/bpf_jit_asm.S new file mode 100644 index 000000000000..9d016c7017f7 --- /dev/null +++ b/arch/sparc/net/bpf_jit_asm.S @@ -0,0 +1,205 @@ +#include <asm/ptrace.h> + +#include "bpf_jit.h" + +#ifdef CONFIG_SPARC64 +#define SAVE_SZ 176 +#define SCRATCH_OFF STACK_BIAS + 128 +#define BE_PTR(label) be,pn %xcc, label +#else +#define SAVE_SZ 96 +#define SCRATCH_OFF 72 +#define BE_PTR(label) be label +#endif + +#define SKF_MAX_NEG_OFF (-0x200000) /* SKF_LL_OFF from filter.h */ + + .text + .globl bpf_jit_load_word +bpf_jit_load_word: + cmp r_OFF, 0 + bl bpf_slow_path_word_neg + nop + .globl bpf_jit_load_word_positive_offset +bpf_jit_load_word_positive_offset: + sub r_HEADLEN, r_OFF, r_TMP + cmp r_TMP, 3 + ble bpf_slow_path_word + add r_SKB_DATA, r_OFF, r_TMP + andcc r_TMP, 3, %g0 + bne load_word_unaligned + nop + retl + ld [r_TMP], r_A +load_word_unaligned: + ldub [r_TMP + 0x0], r_OFF + ldub [r_TMP + 0x1], r_TMP2 + sll r_OFF, 8, r_OFF + or r_OFF, r_TMP2, r_OFF + ldub [r_TMP + 0x2], r_TMP2 + sll r_OFF, 8, r_OFF + or r_OFF, r_TMP2, r_OFF + ldub [r_TMP + 0x3], r_TMP2 + sll r_OFF, 8, r_OFF + retl + or r_OFF, r_TMP2, r_A + + .globl bpf_jit_load_half +bpf_jit_load_half: + cmp r_OFF, 0 + bl bpf_slow_path_half_neg + nop + .globl bpf_jit_load_half_positive_offset +bpf_jit_load_half_positive_offset: + sub r_HEADLEN, r_OFF, r_TMP + cmp r_TMP, 1 + ble bpf_slow_path_half + add r_SKB_DATA, r_OFF, r_TMP + andcc r_TMP, 1, %g0 + bne load_half_unaligned + nop + retl + lduh [r_TMP], r_A +load_half_unaligned: + ldub [r_TMP + 0x0], r_OFF + ldub [r_TMP + 0x1], r_TMP2 + sll r_OFF, 8, r_OFF + retl + or r_OFF, r_TMP2, r_A + + .globl bpf_jit_load_byte +bpf_jit_load_byte: + cmp r_OFF, 0 + bl bpf_slow_path_byte_neg + nop + .globl bpf_jit_load_byte_positive_offset +bpf_jit_load_byte_positive_offset: + cmp r_OFF, r_HEADLEN + bge bpf_slow_path_byte + nop + retl + ldub [r_SKB_DATA + r_OFF], r_A + + .globl bpf_jit_load_byte_msh +bpf_jit_load_byte_msh: + cmp r_OFF, 0 + bl bpf_slow_path_byte_msh_neg + nop + .globl bpf_jit_load_byte_msh_positive_offset +bpf_jit_load_byte_msh_positive_offset: + cmp r_OFF, r_HEADLEN + bge bpf_slow_path_byte_msh + nop + ldub [r_SKB_DATA + r_OFF], r_OFF + and r_OFF, 0xf, r_OFF + retl + sll r_OFF, 2, r_X + +#define bpf_slow_path_common(LEN) \ + save %sp, -SAVE_SZ, %sp; \ + mov %i0, %o0; \ + mov r_OFF, %o1; \ + add %fp, SCRATCH_OFF, %o2; \ + call skb_copy_bits; \ + mov (LEN), %o3; \ + cmp %o0, 0; \ + restore; + +bpf_slow_path_word: + bpf_slow_path_common(4) + bl bpf_error + ld [%sp + SCRATCH_OFF], r_A + retl + nop +bpf_slow_path_half: + bpf_slow_path_common(2) + bl bpf_error + lduh [%sp + SCRATCH_OFF], r_A + retl + nop +bpf_slow_path_byte: + bpf_slow_path_common(1) + bl bpf_error + ldub [%sp + SCRATCH_OFF], r_A + retl + nop +bpf_slow_path_byte_msh: + bpf_slow_path_common(1) + bl bpf_error + ldub [%sp + SCRATCH_OFF], r_A + and r_OFF, 0xf, r_OFF + retl + sll r_OFF, 2, r_X + +#define bpf_negative_common(LEN) \ + save %sp, -SAVE_SZ, %sp; \ + mov %i0, %o0; \ + mov r_OFF, %o1; \ + call bpf_internal_load_pointer_neg_helper; \ + mov (LEN), %o2; \ + mov %o0, r_TMP; \ + cmp %o0, 0; \ + BE_PTR(bpf_error); \ + restore; + +bpf_slow_path_word_neg: + sethi %hi(SKF_MAX_NEG_OFF), r_TMP + cmp r_OFF, r_TMP + bl bpf_error + nop + .globl bpf_jit_load_word_negative_offset +bpf_jit_load_word_negative_offset: + bpf_negative_common(4) + andcc r_TMP, 3, %g0 + bne load_word_unaligned + nop + retl + ld [r_TMP], r_A + +bpf_slow_path_half_neg: + sethi %hi(SKF_MAX_NEG_OFF), r_TMP + cmp r_OFF, r_TMP + bl bpf_error + nop + .globl bpf_jit_load_half_negative_offset +bpf_jit_load_half_negative_offset: + bpf_negative_common(2) + andcc r_TMP, 1, %g0 + bne load_half_unaligned + nop + retl + lduh [r_TMP], r_A + +bpf_slow_path_byte_neg: + sethi %hi(SKF_MAX_NEG_OFF), r_TMP + cmp r_OFF, r_TMP + bl bpf_error + nop + .globl bpf_jit_load_byte_negative_offset +bpf_jit_load_byte_negative_offset: + bpf_negative_common(1) + retl + ldub [r_TMP], r_A + +bpf_slow_path_byte_msh_neg: + sethi %hi(SKF_MAX_NEG_OFF), r_TMP + cmp r_OFF, r_TMP + bl bpf_error + nop + .globl bpf_jit_load_byte_msh_negative_offset +bpf_jit_load_byte_msh_negative_offset: + bpf_negative_common(1) + ldub [r_TMP], r_OFF + and r_OFF, 0xf, r_OFF + retl + sll r_OFF, 2, r_X + +bpf_error: + /* Make the JIT program return zero. The JIT epilogue + * stores away the original %o7 into r_saved_O7. The + * normal leaf function return is to use "retl" which + * would evalute to "jmpl %o7 + 8, %g0" but we want to + * use the saved value thus the sequence you see here. + */ + jmpl r_saved_O7 + 8, %g0 + clr %o0 diff --git a/arch/sparc/net/bpf_jit_comp.c b/arch/sparc/net/bpf_jit_comp.c new file mode 100644 index 000000000000..1a69244e785b --- /dev/null +++ b/arch/sparc/net/bpf_jit_comp.c @@ -0,0 +1,802 @@ +#include <linux/moduleloader.h> +#include <linux/workqueue.h> +#include <linux/netdevice.h> +#include <linux/filter.h> +#include <linux/cache.h> + +#include <asm/cacheflush.h> +#include <asm/ptrace.h> + +#include "bpf_jit.h" + +int bpf_jit_enable __read_mostly; + +static inline bool is_simm13(unsigned int value) +{ + return value + 0x1000 < 0x2000; +} + +static void bpf_flush_icache(void *start_, void *end_) +{ +#ifdef CONFIG_SPARC64 + /* Cheetah's I-cache is fully coherent. */ + if (tlb_type == spitfire) { + unsigned long start = (unsigned long) start_; + unsigned long end = (unsigned long) end_; + + start &= ~7UL; + end = (end + 7UL) & ~7UL; + while (start < end) { + flushi(start); + start += 32; + } + } +#endif +} + +#define SEEN_DATAREF 1 /* might call external helpers */ +#define SEEN_XREG 2 /* ebx is used */ +#define SEEN_MEM 4 /* use mem[] for temporary storage */ + +#define S13(X) ((X) & 0x1fff) +#define IMMED 0x00002000 +#define RD(X) ((X) << 25) +#define RS1(X) ((X) << 14) +#define RS2(X) ((X)) +#define OP(X) ((X) << 30) +#define OP2(X) ((X) << 22) +#define OP3(X) ((X) << 19) +#define COND(X) ((X) << 25) +#define F1(X) OP(X) +#define F2(X, Y) (OP(X) | OP2(Y)) +#define F3(X, Y) (OP(X) | OP3(Y)) + +#define CONDN COND(0x0) +#define CONDE COND(0x1) +#define CONDLE COND(0x2) +#define CONDL COND(0x3) +#define CONDLEU COND(0x4) +#define CONDCS COND(0x5) +#define CONDNEG COND(0x6) +#define CONDVC COND(0x7) +#define CONDA COND(0x8) +#define CONDNE COND(0x9) +#define CONDG COND(0xa) +#define CONDGE COND(0xb) +#define CONDGU COND(0xc) +#define CONDCC COND(0xd) +#define CONDPOS COND(0xe) +#define CONDVS COND(0xf) + +#define CONDGEU CONDCC +#define CONDLU CONDCS + +#define WDISP22(X) (((X) >> 2) & 0x3fffff) + +#define BA (F2(0, 2) | CONDA) +#define BGU (F2(0, 2) | CONDGU) +#define BLEU (F2(0, 2) | CONDLEU) +#define BGEU (F2(0, 2) | CONDGEU) +#define BLU (F2(0, 2) | CONDLU) +#define BE (F2(0, 2) | CONDE) +#define BNE (F2(0, 2) | CONDNE) + +#ifdef CONFIG_SPARC64 +#define BNE_PTR (F2(0, 1) | CONDNE | (2 << 20)) +#else +#define BNE_PTR BNE +#endif + +#define SETHI(K, REG) \ + (F2(0, 0x4) | RD(REG) | (((K) >> 10) & 0x3fffff)) +#define OR_LO(K, REG) \ + (F3(2, 0x02) | IMMED | RS1(REG) | ((K) & 0x3ff) | RD(REG)) + +#define ADD F3(2, 0x00) +#define AND F3(2, 0x01) +#define ANDCC F3(2, 0x11) +#define OR F3(2, 0x02) +#define SUB F3(2, 0x04) +#define SUBCC F3(2, 0x14) +#define MUL F3(2, 0x0a) /* umul */ +#define DIV F3(2, 0x0e) /* udiv */ +#define SLL F3(2, 0x25) +#define SRL F3(2, 0x26) +#define JMPL F3(2, 0x38) +#define CALL F1(1) +#define BR F2(0, 0x01) +#define RD_Y F3(2, 0x28) +#define WR_Y F3(2, 0x30) + +#define LD32 F3(3, 0x00) +#define LD8 F3(3, 0x01) +#define LD16 F3(3, 0x02) +#define LD64 F3(3, 0x0b) +#define ST32 F3(3, 0x04) + +#ifdef CONFIG_SPARC64 +#define LDPTR LD64 +#define BASE_STACKFRAME 176 +#else +#define LDPTR LD32 +#define BASE_STACKFRAME 96 +#endif + +#define LD32I (LD32 | IMMED) +#define LD8I (LD8 | IMMED) +#define LD16I (LD16 | IMMED) +#define LD64I (LD64 | IMMED) +#define LDPTRI (LDPTR | IMMED) +#define ST32I (ST32 | IMMED) + +#define emit_nop() \ +do { \ + *prog++ = SETHI(0, G0); \ +} while (0) + +#define emit_neg() \ +do { /* sub %g0, r_A, r_A */ \ + *prog++ = SUB | RS1(G0) | RS2(r_A) | RD(r_A); \ +} while (0) + +#define emit_reg_move(FROM, TO) \ +do { /* or %g0, FROM, TO */ \ + *prog++ = OR | RS1(G0) | RS2(FROM) | RD(TO); \ +} while (0) + +#define emit_clear(REG) \ +do { /* or %g0, %g0, REG */ \ + *prog++ = OR | RS1(G0) | RS2(G0) | RD(REG); \ +} while (0) + +#define emit_set_const(K, REG) \ +do { /* sethi %hi(K), REG */ \ + *prog++ = SETHI(K, REG); \ + /* or REG, %lo(K), REG */ \ + *prog++ = OR_LO(K, REG); \ +} while (0) + + /* Emit + * + * OP r_A, r_X, r_A + */ +#define emit_alu_X(OPCODE) \ +do { \ + seen |= SEEN_XREG; \ + *prog++ = OPCODE | RS1(r_A) | RS2(r_X) | RD(r_A); \ +} while (0) + + /* Emit either: + * + * OP r_A, K, r_A + * + * or + * + * sethi %hi(K), r_TMP + * or r_TMP, %lo(K), r_TMP + * OP r_A, r_TMP, r_A + * + * depending upon whether K fits in a signed 13-bit + * immediate instruction field. Emit nothing if K + * is zero. + */ +#define emit_alu_K(OPCODE, K) \ +do { \ + if (K) { \ + unsigned int _insn = OPCODE; \ + _insn |= RS1(r_A) | RD(r_A); \ + if (is_simm13(K)) { \ + *prog++ = _insn | IMMED | S13(K); \ + } else { \ + emit_set_const(K, r_TMP); \ + *prog++ = _insn | RS2(r_TMP); \ + } \ + } \ +} while (0) + +#define emit_loadimm(K, DEST) \ +do { \ + if (is_simm13(K)) { \ + /* or %g0, K, DEST */ \ + *prog++ = OR | IMMED | RS1(G0) | S13(K) | RD(DEST); \ + } else { \ + emit_set_const(K, DEST); \ + } \ +} while (0) + +#define emit_loadptr(BASE, STRUCT, FIELD, DEST) \ +do { unsigned int _off = offsetof(STRUCT, FIELD); \ + BUILD_BUG_ON(FIELD_SIZEOF(STRUCT, FIELD) != sizeof(void *)); \ + *prog++ = LDPTRI | RS1(BASE) | S13(_off) | RD(DEST); \ +} while (0) + +#define emit_load32(BASE, STRUCT, FIELD, DEST) \ +do { unsigned int _off = offsetof(STRUCT, FIELD); \ + BUILD_BUG_ON(FIELD_SIZEOF(STRUCT, FIELD) != sizeof(u32)); \ + *prog++ = LD32I | RS1(BASE) | S13(_off) | RD(DEST); \ +} while (0) + +#define emit_load16(BASE, STRUCT, FIELD, DEST) \ +do { unsigned int _off = offsetof(STRUCT, FIELD); \ + BUILD_BUG_ON(FIELD_SIZEOF(STRUCT, FIELD) != sizeof(u16)); \ + *prog++ = LD16I | RS1(BASE) | S13(_off) | RD(DEST); \ +} while (0) + +#define __emit_load8(BASE, STRUCT, FIELD, DEST) \ +do { unsigned int _off = offsetof(STRUCT, FIELD); \ + *prog++ = LD8I | RS1(BASE) | S13(_off) | RD(DEST); \ +} while (0) + +#define emit_load8(BASE, STRUCT, FIELD, DEST) \ +do { BUILD_BUG_ON(FIELD_SIZEOF(STRUCT, FIELD) != sizeof(u8)); \ + __emit_load8(BASE, STRUCT, FIELD, DEST); \ +} while (0) + +#define emit_ldmem(OFF, DEST) \ +do { *prog++ = LD32I | RS1(FP) | S13(-(OFF)) | RD(DEST); \ +} while (0) + +#define emit_stmem(OFF, SRC) \ +do { *prog++ = LD32I | RS1(FP) | S13(-(OFF)) | RD(SRC); \ +} while (0) + +#ifdef CONFIG_SMP +#ifdef CONFIG_SPARC64 +#define emit_load_cpu(REG) \ + emit_load16(G6, struct thread_info, cpu, REG) +#else +#define emit_load_cpu(REG) \ + emit_load32(G6, struct thread_info, cpu, REG) +#endif +#else +#define emit_load_cpu(REG) emit_clear(REG) +#endif + +#define emit_skb_loadptr(FIELD, DEST) \ + emit_loadptr(r_SKB, struct sk_buff, FIELD, DEST) +#define emit_skb_load32(FIELD, DEST) \ + emit_load32(r_SKB, struct sk_buff, FIELD, DEST) +#define emit_skb_load16(FIELD, DEST) \ + emit_load16(r_SKB, struct sk_buff, FIELD, DEST) +#define __emit_skb_load8(FIELD, DEST) \ + __emit_load8(r_SKB, struct sk_buff, FIELD, DEST) +#define emit_skb_load8(FIELD, DEST) \ + emit_load8(r_SKB, struct sk_buff, FIELD, DEST) + +#define emit_jmpl(BASE, IMM_OFF, LREG) \ + *prog++ = (JMPL | IMMED | RS1(BASE) | S13(IMM_OFF) | RD(LREG)) + +#define emit_call(FUNC) \ +do { void *_here = image + addrs[i] - 8; \ + unsigned int _off = (void *)(FUNC) - _here; \ + *prog++ = CALL | (((_off) >> 2) & 0x3fffffff); \ + emit_nop(); \ +} while (0) + +#define emit_branch(BR_OPC, DEST) \ +do { unsigned int _here = addrs[i] - 8; \ + *prog++ = BR_OPC | WDISP22((DEST) - _here); \ +} while (0) + +#define emit_branch_off(BR_OPC, OFF) \ +do { *prog++ = BR_OPC | WDISP22(OFF); \ +} while (0) + +#define emit_jump(DEST) emit_branch(BA, DEST) + +#define emit_read_y(REG) *prog++ = RD_Y | RD(REG) +#define emit_write_y(REG) *prog++ = WR_Y | IMMED | RS1(REG) | S13(0) + +#define emit_cmp(R1, R2) \ + *prog++ = (SUBCC | RS1(R1) | RS2(R2) | RD(G0)) + +#define emit_cmpi(R1, IMM) \ + *prog++ = (SUBCC | IMMED | RS1(R1) | S13(IMM) | RD(G0)); + +#define emit_btst(R1, R2) \ + *prog++ = (ANDCC | RS1(R1) | RS2(R2) | RD(G0)) + +#define emit_btsti(R1, IMM) \ + *prog++ = (ANDCC | IMMED | RS1(R1) | S13(IMM) | RD(G0)); + +#define emit_sub(R1, R2, R3) \ + *prog++ = (SUB | RS1(R1) | RS2(R2) | RD(R3)) + +#define emit_subi(R1, IMM, R3) \ + *prog++ = (SUB | IMMED | RS1(R1) | S13(IMM) | RD(R3)) + +#define emit_add(R1, R2, R3) \ + *prog++ = (ADD | RS1(R1) | RS2(R2) | RD(R3)) + +#define emit_addi(R1, IMM, R3) \ + *prog++ = (ADD | IMMED | RS1(R1) | S13(IMM) | RD(R3)) + +#define emit_alloc_stack(SZ) \ + *prog++ = (SUB | IMMED | RS1(SP) | S13(SZ) | RD(SP)) + +#define emit_release_stack(SZ) \ + *prog++ = (ADD | IMMED | RS1(SP) | S13(SZ) | RD(SP)) + +/* A note about branch offset calculations. The addrs[] array, + * indexed by BPF instruction, records the address after all the + * sparc instructions emitted for that BPF instruction. + * + * The most common case is to emit a branch at the end of such + * a code sequence. So this would be two instructions, the + * branch and it's delay slot. + * + * Therefore by default the branch emitters calculate the branch + * offset field as: + * + * destination - (addrs[i] - 8) + * + * This "addrs[i] - 8" is the address of the branch itself or + * what "." would be in assembler notation. The "8" part is + * how we take into consideration the branch and it's delay + * slot mentioned above. + * + * Sometimes we need to emit a branch earlier in the code + * sequence. And in these situations we adjust "destination" + * to accomodate this difference. For example, if we needed + * to emit a branch (and it's delay slot) right before the + * final instruction emitted for a BPF opcode, we'd use + * "destination + 4" instead of just plain "destination" above. + * + * This is why you see all of these funny emit_branch() and + * emit_jump() calls with adjusted offsets. + */ + +void bpf_jit_compile(struct sk_filter *fp) +{ + unsigned int cleanup_addr, proglen, oldproglen = 0; + u32 temp[8], *prog, *func, seen = 0, pass; + const struct sock_filter *filter = fp->insns; + int i, flen = fp->len, pc_ret0 = -1; + unsigned int *addrs; + void *image; + + if (!bpf_jit_enable) + return; + + addrs = kmalloc(flen * sizeof(*addrs), GFP_KERNEL); + if (addrs == NULL) + return; + + /* Before first pass, make a rough estimation of addrs[] + * each bpf instruction is translated to less than 64 bytes + */ + for (proglen = 0, i = 0; i < flen; i++) { + proglen += 64; + addrs[i] = proglen; + } + cleanup_addr = proglen; /* epilogue address */ + image = NULL; + for (pass = 0; pass < 10; pass++) { + u8 seen_or_pass0 = (pass == 0) ? (SEEN_XREG | SEEN_DATAREF | SEEN_MEM) : seen; + + /* no prologue/epilogue for trivial filters (RET something) */ + proglen = 0; + prog = temp; + + /* Prologue */ + if (seen_or_pass0) { + if (seen_or_pass0 & SEEN_MEM) { + unsigned int sz = BASE_STACKFRAME; + sz += BPF_MEMWORDS * sizeof(u32); + emit_alloc_stack(sz); + } + + /* Make sure we dont leek kernel memory. */ + if (seen_or_pass0 & SEEN_XREG) + emit_clear(r_X); + + /* If this filter needs to access skb data, + * load %o4 and %o5 with: + * %o4 = skb->len - skb->data_len + * %o5 = skb->data + * And also back up %o7 into r_saved_O7 so we can + * invoke the stubs using 'call'. + */ + if (seen_or_pass0 & SEEN_DATAREF) { + emit_load32(r_SKB, struct sk_buff, len, r_HEADLEN); + emit_load32(r_SKB, struct sk_buff, data_len, r_TMP); + emit_sub(r_HEADLEN, r_TMP, r_HEADLEN); + emit_loadptr(r_SKB, struct sk_buff, data, r_SKB_DATA); + } + } + emit_reg_move(O7, r_saved_O7); + + switch (filter[0].code) { + case BPF_S_RET_K: + case BPF_S_LD_W_LEN: + case BPF_S_ANC_PROTOCOL: + case BPF_S_ANC_PKTTYPE: + case BPF_S_ANC_IFINDEX: + case BPF_S_ANC_MARK: + case BPF_S_ANC_RXHASH: + case BPF_S_ANC_CPU: + case BPF_S_ANC_QUEUE: + case BPF_S_LD_W_ABS: + case BPF_S_LD_H_ABS: + case BPF_S_LD_B_ABS: + /* The first instruction sets the A register (or is + * a "RET 'constant'") + */ + break; + default: + /* Make sure we dont leak kernel information to the + * user. + */ + emit_clear(r_A); /* A = 0 */ + } + + for (i = 0; i < flen; i++) { + unsigned int K = filter[i].k; + unsigned int t_offset; + unsigned int f_offset; + u32 t_op, f_op; + int ilen; + + switch (filter[i].code) { + case BPF_S_ALU_ADD_X: /* A += X; */ + emit_alu_X(ADD); + break; + case BPF_S_ALU_ADD_K: /* A += K; */ + emit_alu_K(ADD, K); + break; + case BPF_S_ALU_SUB_X: /* A -= X; */ + emit_alu_X(SUB); + break; + case BPF_S_ALU_SUB_K: /* A -= K */ + emit_alu_K(SUB, K); + break; + case BPF_S_ALU_AND_X: /* A &= X */ + emit_alu_X(AND); + break; + case BPF_S_ALU_AND_K: /* A &= K */ + emit_alu_K(AND, K); + break; + case BPF_S_ALU_OR_X: /* A |= X */ + emit_alu_X(OR); + break; + case BPF_S_ALU_OR_K: /* A |= K */ + emit_alu_K(OR, K); + break; + case BPF_S_ALU_LSH_X: /* A <<= X */ + emit_alu_X(SLL); + break; + case BPF_S_ALU_LSH_K: /* A <<= K */ + emit_alu_K(SLL, K); + break; + case BPF_S_ALU_RSH_X: /* A >>= X */ + emit_alu_X(SRL); + break; + case BPF_S_ALU_RSH_K: /* A >>= K */ + emit_alu_K(SRL, K); + break; + case BPF_S_ALU_MUL_X: /* A *= X; */ + emit_alu_X(MUL); + break; + case BPF_S_ALU_MUL_K: /* A *= K */ + emit_alu_K(MUL, K); + break; + case BPF_S_ALU_DIV_K: /* A /= K */ + emit_alu_K(MUL, K); + emit_read_y(r_A); + break; + case BPF_S_ALU_DIV_X: /* A /= X; */ + emit_cmpi(r_X, 0); + if (pc_ret0 > 0) { + t_offset = addrs[pc_ret0 - 1]; +#ifdef CONFIG_SPARC32 + emit_branch(BE, t_offset + 20); +#else + emit_branch(BE, t_offset + 8); +#endif + emit_nop(); /* delay slot */ + } else { + emit_branch_off(BNE, 16); + emit_nop(); +#ifdef CONFIG_SPARC32 + emit_jump(cleanup_addr + 20); +#else + emit_jump(cleanup_addr + 8); +#endif + emit_clear(r_A); + } + emit_write_y(G0); +#ifdef CONFIG_SPARC32 + /* The Sparc v8 architecture requires + * three instructions between a %y + * register write and the first use. + */ + emit_nop(); + emit_nop(); + emit_nop(); +#endif + emit_alu_X(DIV); + break; + case BPF_S_ALU_NEG: + emit_neg(); + break; + case BPF_S_RET_K: + if (!K) { + if (pc_ret0 == -1) + pc_ret0 = i; + emit_clear(r_A); + } else { + emit_loadimm(K, r_A); + } + /* Fallthrough */ + case BPF_S_RET_A: + if (seen_or_pass0) { + if (i != flen - 1) { + emit_jump(cleanup_addr); + emit_nop(); + break; + } + if (seen_or_pass0 & SEEN_MEM) { + unsigned int sz = BASE_STACKFRAME; + sz += BPF_MEMWORDS * sizeof(u32); + emit_release_stack(sz); + } + } + /* jmpl %r_saved_O7 + 8, %g0 */ + emit_jmpl(r_saved_O7, 8, G0); + emit_reg_move(r_A, O0); /* delay slot */ + break; + case BPF_S_MISC_TAX: + seen |= SEEN_XREG; + emit_reg_move(r_A, r_X); + break; + case BPF_S_MISC_TXA: + seen |= SEEN_XREG; + emit_reg_move(r_X, r_A); + break; + case BPF_S_ANC_CPU: + emit_load_cpu(r_A); + break; + case BPF_S_ANC_PROTOCOL: + emit_skb_load16(protocol, r_A); + break; +#if 0 + /* GCC won't let us take the address of + * a bit field even though we very much + * know what we are doing here. + */ + case BPF_S_ANC_PKTTYPE: + __emit_skb_load8(pkt_type, r_A); + emit_alu_K(SRL, 5); + break; +#endif + case BPF_S_ANC_IFINDEX: + emit_skb_loadptr(dev, r_A); + emit_cmpi(r_A, 0); + emit_branch(BNE_PTR, cleanup_addr + 4); + emit_nop(); + emit_load32(r_A, struct net_device, ifindex, r_A); + break; + case BPF_S_ANC_MARK: + emit_skb_load32(mark, r_A); + break; + case BPF_S_ANC_QUEUE: + emit_skb_load16(queue_mapping, r_A); + break; + case BPF_S_ANC_HATYPE: + emit_skb_loadptr(dev, r_A); + emit_cmpi(r_A, 0); + emit_branch(BNE_PTR, cleanup_addr + 4); + emit_nop(); + emit_load16(r_A, struct net_device, type, r_A); + break; + case BPF_S_ANC_RXHASH: + emit_skb_load32(rxhash, r_A); + break; + + case BPF_S_LD_IMM: + emit_loadimm(K, r_A); + break; + case BPF_S_LDX_IMM: + emit_loadimm(K, r_X); + break; + case BPF_S_LD_MEM: + emit_ldmem(K * 4, r_A); + break; + case BPF_S_LDX_MEM: + emit_ldmem(K * 4, r_X); + break; + case BPF_S_ST: + emit_stmem(K * 4, r_A); + break; + case BPF_S_STX: + emit_stmem(K * 4, r_X); + break; + +#define CHOOSE_LOAD_FUNC(K, func) \ + ((int)K < 0 ? ((int)K >= SKF_LL_OFF ? func##_negative_offset : func) : func##_positive_offset) + + case BPF_S_LD_W_ABS: + func = CHOOSE_LOAD_FUNC(K, bpf_jit_load_word); +common_load: seen |= SEEN_DATAREF; + emit_loadimm(K, r_OFF); + emit_call(func); + break; + case BPF_S_LD_H_ABS: + func = CHOOSE_LOAD_FUNC(K, bpf_jit_load_half); + goto common_load; + case BPF_S_LD_B_ABS: + func = CHOOSE_LOAD_FUNC(K, bpf_jit_load_byte); + goto common_load; + case BPF_S_LDX_B_MSH: + func = CHOOSE_LOAD_FUNC(K, bpf_jit_load_byte_msh); + goto common_load; + case BPF_S_LD_W_IND: + func = bpf_jit_load_word; +common_load_ind: seen |= SEEN_DATAREF | SEEN_XREG; + if (K) { + if (is_simm13(K)) { + emit_addi(r_X, K, r_OFF); + } else { + emit_loadimm(K, r_TMP); + emit_add(r_X, r_TMP, r_OFF); + } + } else { + emit_reg_move(r_X, r_OFF); + } + emit_call(func); + break; + case BPF_S_LD_H_IND: + func = bpf_jit_load_half; + goto common_load_ind; + case BPF_S_LD_B_IND: + func = bpf_jit_load_byte; + goto common_load_ind; + case BPF_S_JMP_JA: + emit_jump(addrs[i + K]); + emit_nop(); + break; + +#define COND_SEL(CODE, TOP, FOP) \ + case CODE: \ + t_op = TOP; \ + f_op = FOP; \ + goto cond_branch + + COND_SEL(BPF_S_JMP_JGT_K, BGU, BLEU); + COND_SEL(BPF_S_JMP_JGE_K, BGEU, BLU); + COND_SEL(BPF_S_JMP_JEQ_K, BE, BNE); + COND_SEL(BPF_S_JMP_JSET_K, BNE, BE); + COND_SEL(BPF_S_JMP_JGT_X, BGU, BLEU); + COND_SEL(BPF_S_JMP_JGE_X, BGEU, BLU); + COND_SEL(BPF_S_JMP_JEQ_X, BE, BNE); + COND_SEL(BPF_S_JMP_JSET_X, BNE, BE); + +cond_branch: f_offset = addrs[i + filter[i].jf]; + t_offset = addrs[i + filter[i].jt]; + + /* same targets, can avoid doing the test :) */ + if (filter[i].jt == filter[i].jf) { + emit_jump(t_offset); + emit_nop(); + break; + } + + switch (filter[i].code) { + case BPF_S_JMP_JGT_X: + case BPF_S_JMP_JGE_X: + case BPF_S_JMP_JEQ_X: + seen |= SEEN_XREG; + emit_cmp(r_A, r_X); + break; + case BPF_S_JMP_JSET_X: + seen |= SEEN_XREG; + emit_btst(r_A, r_X); + break; + case BPF_S_JMP_JEQ_K: + case BPF_S_JMP_JGT_K: + case BPF_S_JMP_JGE_K: + if (is_simm13(K)) { + emit_cmpi(r_A, K); + } else { + emit_loadimm(K, r_TMP); + emit_cmp(r_A, r_TMP); + } + break; + case BPF_S_JMP_JSET_K: + if (is_simm13(K)) { + emit_btsti(r_A, K); + } else { + emit_loadimm(K, r_TMP); + emit_btst(r_A, r_TMP); + } + break; + } + if (filter[i].jt != 0) { + if (filter[i].jf) + t_offset += 8; + emit_branch(t_op, t_offset); + emit_nop(); /* delay slot */ + if (filter[i].jf) { + emit_jump(f_offset); + emit_nop(); + } + break; + } + emit_branch(f_op, f_offset); + emit_nop(); /* delay slot */ + break; + + default: + /* hmm, too complex filter, give up with jit compiler */ + goto out; + } + ilen = (void *) prog - (void *) temp; + if (image) { + if (unlikely(proglen + ilen > oldproglen)) { + pr_err("bpb_jit_compile fatal error\n"); + kfree(addrs); + module_free(NULL, image); + return; + } + memcpy(image + proglen, temp, ilen); + } + proglen += ilen; + addrs[i] = proglen; + prog = temp; + } + /* last bpf instruction is always a RET : + * use it to give the cleanup instruction(s) addr + */ + cleanup_addr = proglen - 8; /* jmpl; mov r_A,%o0; */ + if (seen_or_pass0 & SEEN_MEM) + cleanup_addr -= 4; /* add %sp, X, %sp; */ + + if (image) { + if (proglen != oldproglen) + pr_err("bpb_jit_compile proglen=%u != oldproglen=%u\n", + proglen, oldproglen); + break; + } + if (proglen == oldproglen) { + image = module_alloc(max_t(unsigned int, + proglen, + sizeof(struct work_struct))); + if (!image) + goto out; + } + oldproglen = proglen; + } + + if (bpf_jit_enable > 1) + pr_err("flen=%d proglen=%u pass=%d image=%p\n", + flen, proglen, pass, image); + + if (image) { + if (bpf_jit_enable > 1) + print_hex_dump(KERN_ERR, "JIT code: ", DUMP_PREFIX_ADDRESS, + 16, 1, image, proglen, false); + bpf_flush_icache(image, image + proglen); + fp->bpf_func = (void *)image; + } +out: + kfree(addrs); + return; +} + +static void jit_free_defer(struct work_struct *arg) +{ + module_free(NULL, arg); +} + +/* run from softirq, we must use a work_struct to call + * module_free() from process context + */ +void bpf_jit_free(struct sk_filter *fp) +{ + if (fp->bpf_func != sk_run_filter) { + struct work_struct *work = (struct work_struct *)fp->bpf_func; + + INIT_WORK(work, jit_free_defer); + schedule_work(work); + } +} diff --git a/arch/sparc/prom/Makefile b/arch/sparc/prom/Makefile index 8287bbe88768..020300b18c0b 100644 --- a/arch/sparc/prom/Makefile +++ b/arch/sparc/prom/Makefile @@ -10,7 +10,6 @@ lib-$(CONFIG_SPARC32) += memory.o lib-y += misc_$(BITS).o lib-$(CONFIG_SPARC32) += mp.o lib-$(CONFIG_SPARC32) += ranges.o -lib-$(CONFIG_SPARC32) += segment.o lib-y += console_$(BITS).o lib-y += printf.o lib-y += tree_$(BITS).o diff --git a/arch/sparc/prom/segment.c b/arch/sparc/prom/segment.c deleted file mode 100644 index 86a663f1d3c5..000000000000 --- a/arch/sparc/prom/segment.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * segment.c: Prom routine to map segments in other contexts before - * a standalone is completely mapped. This is for sun4 and - * sun4c architectures only. - * - * Copyright (C) 1995 David S. Miller ([email protected]) - */ - -#include <linux/types.h> -#include <linux/kernel.h> -#include <linux/sched.h> -#include <asm/openprom.h> -#include <asm/oplib.h> - -extern void restore_current(void); - -/* Set physical segment 'segment' at virtual address 'vaddr' in - * context 'ctx'. - */ -void -prom_putsegment(int ctx, unsigned long vaddr, int segment) -{ - unsigned long flags; - spin_lock_irqsave(&prom_lock, flags); - (*(romvec->pv_setctxt))(ctx, (char *) vaddr, segment); - restore_current(); - spin_unlock_irqrestore(&prom_lock, flags); -} diff --git a/arch/tile/Kconfig b/arch/tile/Kconfig index 96033e2d6845..74239dd77e06 100644 --- a/arch/tile/Kconfig +++ b/arch/tile/Kconfig @@ -11,6 +11,7 @@ config TILE select GENERIC_IRQ_PROBE select GENERIC_PENDING_IRQ if SMP select GENERIC_IRQ_SHOW + select HAVE_SYSCALL_WRAPPERS if TILEGX select SYS_HYPERVISOR select ARCH_HAVE_NMI_SAFE_CMPXCHG diff --git a/arch/tile/include/asm/pci.h b/arch/tile/include/asm/pci.h index 5d5a635530bd..32e6cbe8dff3 100644 --- a/arch/tile/include/asm/pci.h +++ b/arch/tile/include/asm/pci.h @@ -47,8 +47,8 @@ struct pci_controller { */ #define PCI_DMA_BUS_IS_PHYS 1 -int __devinit tile_pci_init(void); -int __devinit pcibios_init(void); +int __init tile_pci_init(void); +int __init pcibios_init(void); static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {} diff --git a/arch/tile/include/asm/thread_info.h b/arch/tile/include/asm/thread_info.h index bc4f562bd459..7594764d8a69 100644 --- a/arch/tile/include/asm/thread_info.h +++ b/arch/tile/include/asm/thread_info.h @@ -100,9 +100,14 @@ extern void cpu_idle_on_new_stack(struct thread_info *old_ti, #else /* __ASSEMBLY__ */ -/* how to get the thread information struct from ASM */ +/* + * How to get the thread information struct from assembly. + * Note that we use different macros since different architectures + * have different semantics in their "mm" instruction and we would + * like to guarantee that the macro expands to exactly one instruction. + */ #ifdef __tilegx__ -#define GET_THREAD_INFO(reg) move reg, sp; mm reg, zero, LOG2_THREAD_SIZE, 63 +#define EXTRACT_THREAD_INFO(reg) mm reg, zero, LOG2_THREAD_SIZE, 63 #else #define GET_THREAD_INFO(reg) mm reg, sp, zero, LOG2_THREAD_SIZE, 31 #endif diff --git a/arch/tile/kernel/compat_signal.c b/arch/tile/kernel/compat_signal.c index 77763ccd5a7d..cdef6e5ec022 100644 --- a/arch/tile/kernel/compat_signal.c +++ b/arch/tile/kernel/compat_signal.c @@ -403,19 +403,17 @@ int compat_setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info, * Set up registers for signal handler. * Registers that we don't modify keep the value they had from * user-space at the time we took the signal. + * We always pass siginfo and mcontext, regardless of SA_SIGINFO, + * since some things rely on this (e.g. glibc's debug/segfault.c). */ regs->pc = ptr_to_compat_reg(ka->sa.sa_handler); regs->ex1 = PL_ICS_EX1(USER_PL, 1); /* set crit sec in handler */ regs->sp = ptr_to_compat_reg(frame); regs->lr = restorer; regs->regs[0] = (unsigned long) usig; - - if (ka->sa.sa_flags & SA_SIGINFO) { - /* Need extra arguments, so mark to restore caller-saves. */ - regs->regs[1] = ptr_to_compat_reg(&frame->info); - regs->regs[2] = ptr_to_compat_reg(&frame->uc); - regs->flags |= PT_FLAGS_CALLER_SAVES; - } + regs->regs[1] = ptr_to_compat_reg(&frame->info); + regs->regs[2] = ptr_to_compat_reg(&frame->uc); + regs->flags |= PT_FLAGS_CALLER_SAVES; /* * Notify any tracer that was single-stepping it. diff --git a/arch/tile/kernel/intvec_32.S b/arch/tile/kernel/intvec_32.S index 5d56a1ef5ba5..6943515100f8 100644 --- a/arch/tile/kernel/intvec_32.S +++ b/arch/tile/kernel/intvec_32.S @@ -839,6 +839,18 @@ STD_ENTRY(interrupt_return) FEEDBACK_REENTER(interrupt_return) /* + * Use r33 to hold whether we have already loaded the callee-saves + * into ptregs. We don't want to do it twice in this loop, since + * then we'd clobber whatever changes are made by ptrace, etc. + * Get base of stack in r32. + */ + { + GET_THREAD_INFO(r32) + movei r33, 0 + } + +.Lretry_work_pending: + /* * Disable interrupts so as to make sure we don't * miss an interrupt that sets any of the thread flags (like * need_resched or sigpending) between sampling and the iret. @@ -848,9 +860,6 @@ STD_ENTRY(interrupt_return) IRQ_DISABLE(r20, r21) TRACE_IRQS_OFF /* Note: clobbers registers r0-r29 */ - /* Get base of stack in r32; note r30/31 are used as arguments here. */ - GET_THREAD_INFO(r32) - /* Check to see if there is any work to do before returning to user. */ { @@ -866,16 +875,18 @@ STD_ENTRY(interrupt_return) /* * Make sure we have all the registers saved for signal - * handling or single-step. Call out to C code to figure out - * exactly what we need to do for each flag bit, then if - * necessary, reload the flags and recheck. + * handling, notify-resume, or single-step. Call out to C + * code to figure out exactly what we need to do for each flag bit, + * then if necessary, reload the flags and recheck. */ - push_extra_callee_saves r0 { PTREGS_PTR(r0, PTREGS_OFFSET_BASE) - jal do_work_pending + bnz r33, 1f } - bnz r0, .Lresume_userspace + push_extra_callee_saves r0 + movei r33, 1 +1: jal do_work_pending + bnz r0, .Lretry_work_pending /* * In the NMI case we @@ -1180,10 +1191,12 @@ handle_syscall: add r20, r20, tp lw r21, r20 addi r21, r21, 1 - sw r20, r21 + { + sw r20, r21 + GET_THREAD_INFO(r31) + } /* Trace syscalls, if requested. */ - GET_THREAD_INFO(r31) addi r31, r31, THREAD_INFO_FLAGS_OFFSET lw r30, r31 andi r30, r30, _TIF_SYSCALL_TRACE @@ -1362,7 +1375,10 @@ handle_ill: 3: /* set PC and continue */ lw r26, r24 - sw r28, r26 + { + sw r28, r26 + GET_THREAD_INFO(r0) + } /* * Clear TIF_SINGLESTEP to prevent recursion if we execute an ill. @@ -1370,7 +1386,6 @@ handle_ill: * need to clear it here and can't really impose on all other arches. * So what's another write between friends? */ - GET_THREAD_INFO(r0) addi r1, r0, THREAD_INFO_FLAGS_OFFSET { diff --git a/arch/tile/kernel/intvec_64.S b/arch/tile/kernel/intvec_64.S index 49d9d6621682..30ae76e50c44 100644 --- a/arch/tile/kernel/intvec_64.S +++ b/arch/tile/kernel/intvec_64.S @@ -647,6 +647,20 @@ STD_ENTRY(interrupt_return) FEEDBACK_REENTER(interrupt_return) /* + * Use r33 to hold whether we have already loaded the callee-saves + * into ptregs. We don't want to do it twice in this loop, since + * then we'd clobber whatever changes are made by ptrace, etc. + */ + { + movei r33, 0 + move r32, sp + } + + /* Get base of stack in r32. */ + EXTRACT_THREAD_INFO(r32) + +.Lretry_work_pending: + /* * Disable interrupts so as to make sure we don't * miss an interrupt that sets any of the thread flags (like * need_resched or sigpending) between sampling and the iret. @@ -656,9 +670,6 @@ STD_ENTRY(interrupt_return) IRQ_DISABLE(r20, r21) TRACE_IRQS_OFF /* Note: clobbers registers r0-r29 */ - /* Get base of stack in r32; note r30/31 are used as arguments here. */ - GET_THREAD_INFO(r32) - /* Check to see if there is any work to do before returning to user. */ { @@ -674,16 +685,18 @@ STD_ENTRY(interrupt_return) /* * Make sure we have all the registers saved for signal - * handling or single-step. Call out to C code to figure out + * handling or notify-resume. Call out to C code to figure out * exactly what we need to do for each flag bit, then if * necessary, reload the flags and recheck. */ - push_extra_callee_saves r0 { PTREGS_PTR(r0, PTREGS_OFFSET_BASE) - jal do_work_pending + bnez r33, 1f } - bnez r0, .Lresume_userspace + push_extra_callee_saves r0 + movei r33, 1 +1: jal do_work_pending + bnez r0, .Lretry_work_pending /* * In the NMI case we @@ -968,11 +981,16 @@ handle_syscall: shl16insli r20, r20, hw0(irq_stat + IRQ_CPUSTAT_SYSCALL_COUNT_OFFSET) add r20, r20, tp ld4s r21, r20 - addi r21, r21, 1 - st4 r20, r21 + { + addi r21, r21, 1 + move r31, sp + } + { + st4 r20, r21 + EXTRACT_THREAD_INFO(r31) + } /* Trace syscalls, if requested. */ - GET_THREAD_INFO(r31) addi r31, r31, THREAD_INFO_FLAGS_OFFSET ld r30, r31 andi r30, r30, _TIF_SYSCALL_TRACE diff --git a/arch/tile/kernel/pci.c b/arch/tile/kernel/pci.c index a1bb59eecc18..b56d12bf5900 100644 --- a/arch/tile/kernel/pci.c +++ b/arch/tile/kernel/pci.c @@ -141,7 +141,7 @@ static int __devinit tile_init_irqs(int controller_id, * * Returns the number of controllers discovered. */ -int __devinit tile_pci_init(void) +int __init tile_pci_init(void) { int i; @@ -287,7 +287,7 @@ static void __devinit fixup_read_and_payload_sizes(void) * The controllers have been set up by the time we get here, by a call to * tile_pci_init. */ -int __devinit pcibios_init(void) +int __init pcibios_init(void) { int i; diff --git a/arch/tile/kernel/proc.c b/arch/tile/kernel/proc.c index 7a9327046404..446a7f52cc11 100644 --- a/arch/tile/kernel/proc.c +++ b/arch/tile/kernel/proc.c @@ -146,7 +146,6 @@ static ctl_table unaligned_table[] = { }, {} }; -#endif static struct ctl_path tile_path[] = { { .procname = "tile" }, @@ -155,10 +154,9 @@ static struct ctl_path tile_path[] = { static int __init proc_sys_tile_init(void) { -#ifndef __tilegx__ /* FIXME: GX: no support for unaligned access yet */ register_sysctl_paths(tile_path, unaligned_table); -#endif return 0; } arch_initcall(proc_sys_tile_init); +#endif diff --git a/arch/tile/kernel/process.c b/arch/tile/kernel/process.c index 2d5ef617bb39..54e6c64b85cc 100644 --- a/arch/tile/kernel/process.c +++ b/arch/tile/kernel/process.c @@ -567,6 +567,10 @@ struct task_struct *__sched _switch_to(struct task_struct *prev, */ int do_work_pending(struct pt_regs *regs, u32 thread_info_flags) { + /* If we enter in kernel mode, do nothing and exit the caller loop. */ + if (!user_mode(regs)) + return 0; + if (thread_info_flags & _TIF_NEED_RESCHED) { schedule(); return 1; @@ -589,8 +593,7 @@ int do_work_pending(struct pt_regs *regs, u32 thread_info_flags) return 1; } if (thread_info_flags & _TIF_SINGLESTEP) { - if ((regs->ex1 & SPR_EX_CONTEXT_1_1__PL_MASK) == 0) - single_step_once(regs); + single_step_once(regs); return 0; } panic("work_pending: bad flags %#x\n", thread_info_flags); diff --git a/arch/tile/kernel/single_step.c b/arch/tile/kernel/single_step.c index 9efbc1391b3c..89529c9f0605 100644 --- a/arch/tile/kernel/single_step.c +++ b/arch/tile/kernel/single_step.c @@ -346,12 +346,10 @@ void single_step_once(struct pt_regs *regs) } /* allocate a cache line of writable, executable memory */ - down_write(¤t->mm->mmap_sem); - buffer = (void __user *) do_mmap(NULL, 0, 64, + buffer = (void __user *) vm_mmap(NULL, 0, 64, PROT_EXEC | PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS, 0); - up_write(¤t->mm->mmap_sem); if (IS_ERR((void __force *)buffer)) { kfree(state); diff --git a/arch/tile/kernel/smpboot.c b/arch/tile/kernel/smpboot.c index b949edcec200..172aef7d3159 100644 --- a/arch/tile/kernel/smpboot.c +++ b/arch/tile/kernel/smpboot.c @@ -196,6 +196,8 @@ void __cpuinit online_secondary(void) /* This must be done before setting cpu_online_mask */ wmb(); + notify_cpu_starting(smp_processor_id()); + /* * We need to hold call_lock, so there is no inconsistency * between the time smp_call_function() determines number of diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 1d14cc6b79ad..25f87bccbf8f 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -77,11 +77,11 @@ config X86 select GENERIC_CLOCKEVENTS_MIN_ADJUST select IRQ_FORCED_THREADING select USE_GENERIC_SMP_HELPERS if SMP - select HAVE_BPF_JIT if (X86_64 && NET) + select HAVE_BPF_JIT if X86_64 select CLKEVT_I8253 select ARCH_HAVE_NMI_SAFE_CMPXCHG select GENERIC_IOMAP - select DCACHE_WORD_ACCESS if !DEBUG_PAGEALLOC + select DCACHE_WORD_ACCESS config INSTRUCTION_DECODER def_bool (KPROBES || PERF_EVENTS) diff --git a/arch/x86/Makefile b/arch/x86/Makefile index 41a7237606a3..94e91e401da9 100644 --- a/arch/x86/Makefile +++ b/arch/x86/Makefile @@ -134,6 +134,9 @@ KBUILD_CFLAGS += $(call cc-option,-mno-avx,) KBUILD_CFLAGS += $(mflags-y) KBUILD_AFLAGS += $(mflags-y) +archscripts: + $(Q)$(MAKE) $(build)=arch/x86/tools relocs + ### # Syscall table generation diff --git a/arch/x86/boot/compressed/Makefile b/arch/x86/boot/compressed/Makefile index fd55a2ff3ad8..e398bb5d63bb 100644 --- a/arch/x86/boot/compressed/Makefile +++ b/arch/x86/boot/compressed/Makefile @@ -40,13 +40,12 @@ OBJCOPYFLAGS_vmlinux.bin := -R .comment -S $(obj)/vmlinux.bin: vmlinux FORCE $(call if_changed,objcopy) +targets += vmlinux.bin.all vmlinux.relocs -targets += vmlinux.bin.all vmlinux.relocs relocs -hostprogs-$(CONFIG_X86_NEED_RELOCS) += relocs - +CMD_RELOCS = arch/x86/tools/relocs quiet_cmd_relocs = RELOCS $@ - cmd_relocs = $(obj)/relocs $< > $@;$(obj)/relocs --abs-relocs $< -$(obj)/vmlinux.relocs: vmlinux $(obj)/relocs FORCE + cmd_relocs = $(CMD_RELOCS) $< > $@;$(CMD_RELOCS) --abs-relocs $< +$(obj)/vmlinux.relocs: vmlinux FORCE $(call if_changed,relocs) vmlinux.bin.all-y := $(obj)/vmlinux.bin diff --git a/arch/x86/boot/compressed/head_32.S b/arch/x86/boot/compressed/head_32.S index a0559930a180..c85e3ac99bba 100644 --- a/arch/x86/boot/compressed/head_32.S +++ b/arch/x86/boot/compressed/head_32.S @@ -33,6 +33,9 @@ __HEAD ENTRY(startup_32) #ifdef CONFIG_EFI_STUB + jmp preferred_addr + + .balign 0x10 /* * We don't need the return address, so set up the stack so * efi_main() can find its arugments. @@ -41,12 +44,17 @@ ENTRY(startup_32) call efi_main cmpl $0, %eax - je preferred_addr movl %eax, %esi - call 1f + jne 2f 1: + /* EFI init failed, so hang. */ + hlt + jmp 1b +2: + call 3f +3: popl %eax - subl $1b, %eax + subl $3b, %eax subl BP_pref_address(%esi), %eax add BP_code32_start(%esi), %eax leal preferred_addr(%eax), %eax diff --git a/arch/x86/boot/compressed/head_64.S b/arch/x86/boot/compressed/head_64.S index 558d76ce23bc..87e03a13d8e3 100644 --- a/arch/x86/boot/compressed/head_64.S +++ b/arch/x86/boot/compressed/head_64.S @@ -200,18 +200,28 @@ ENTRY(startup_64) * entire text+data+bss and hopefully all of memory. */ #ifdef CONFIG_EFI_STUB - pushq %rsi + /* + * The entry point for the PE/COFF executable is 0x210, so only + * legacy boot loaders will execute this jmp. + */ + jmp preferred_addr + + .org 0x210 mov %rcx, %rdi mov %rdx, %rsi call efi_main - popq %rsi - cmpq $0,%rax - je preferred_addr movq %rax,%rsi - call 1f + cmpq $0,%rax + jne 2f 1: + /* EFI init failed, so hang. */ + hlt + jmp 1b +2: + call 3f +3: popq %rax - subq $1b, %rax + subq $3b, %rax subq BP_pref_address(%rsi), %rax add BP_code32_start(%esi), %eax leaq preferred_addr(%rax), %rax diff --git a/arch/x86/boot/tools/build.c b/arch/x86/boot/tools/build.c index ed549767a231..24443a332083 100644 --- a/arch/x86/boot/tools/build.c +++ b/arch/x86/boot/tools/build.c @@ -205,8 +205,13 @@ int main(int argc, char ** argv) put_unaligned_le32(file_sz, &buf[pe_header + 0x50]); #ifdef CONFIG_X86_32 - /* Address of entry point */ - put_unaligned_le32(i, &buf[pe_header + 0x28]); + /* + * Address of entry point. + * + * The EFI stub entry point is +16 bytes from the start of + * the .text section. + */ + put_unaligned_le32(i + 16, &buf[pe_header + 0x28]); /* .text size */ put_unaligned_le32(file_sz, &buf[pe_header + 0xb0]); @@ -217,9 +222,11 @@ int main(int argc, char ** argv) /* * Address of entry point. startup_32 is at the beginning and * the 64-bit entry point (startup_64) is always 512 bytes - * after. + * after. The EFI stub entry point is 16 bytes after that, as + * the first instruction allows legacy loaders to jump over + * the EFI stub initialisation */ - put_unaligned_le32(i + 512, &buf[pe_header + 0x28]); + put_unaligned_le32(i + 528, &buf[pe_header + 0x28]); /* .text size */ put_unaligned_le32(file_sz, &buf[pe_header + 0xc0]); diff --git a/arch/x86/ia32/ia32_aout.c b/arch/x86/ia32/ia32_aout.c index d511d951a052..07b3a68d2d29 100644 --- a/arch/x86/ia32/ia32_aout.c +++ b/arch/x86/ia32/ia32_aout.c @@ -119,9 +119,7 @@ static void set_brk(unsigned long start, unsigned long end) end = PAGE_ALIGN(end); if (end <= start) return; - down_write(¤t->mm->mmap_sem); - do_brk(start, end - start); - up_write(¤t->mm->mmap_sem); + vm_brk(start, end - start); } #ifdef CORE_DUMP @@ -296,8 +294,7 @@ static int load_aout_binary(struct linux_binprm *bprm, struct pt_regs *regs) /* OK, This is the point of no return */ set_personality(PER_LINUX); - set_thread_flag(TIF_IA32); - current->mm->context.ia32_compat = 1; + set_personality_ia32(false); setup_new_exec(bprm); @@ -332,9 +329,7 @@ static int load_aout_binary(struct linux_binprm *bprm, struct pt_regs *regs) pos = 32; map_size = ex.a_text+ex.a_data; - down_write(¤t->mm->mmap_sem); - error = do_brk(text_addr & PAGE_MASK, map_size); - up_write(¤t->mm->mmap_sem); + error = vm_brk(text_addr & PAGE_MASK, map_size); if (error != (text_addr & PAGE_MASK)) { send_sig(SIGKILL, current, 0); @@ -373,9 +368,7 @@ static int load_aout_binary(struct linux_binprm *bprm, struct pt_regs *regs) if (!bprm->file->f_op->mmap || (fd_offset & ~PAGE_MASK) != 0) { loff_t pos = fd_offset; - down_write(¤t->mm->mmap_sem); - do_brk(N_TXTADDR(ex), ex.a_text+ex.a_data); - up_write(¤t->mm->mmap_sem); + vm_brk(N_TXTADDR(ex), ex.a_text+ex.a_data); bprm->file->f_op->read(bprm->file, (char __user *)N_TXTADDR(ex), ex.a_text+ex.a_data, &pos); @@ -385,26 +378,22 @@ static int load_aout_binary(struct linux_binprm *bprm, struct pt_regs *regs) goto beyond_if; } - down_write(¤t->mm->mmap_sem); - error = do_mmap(bprm->file, N_TXTADDR(ex), ex.a_text, + error = vm_mmap(bprm->file, N_TXTADDR(ex), ex.a_text, PROT_READ | PROT_EXEC, MAP_FIXED | MAP_PRIVATE | MAP_DENYWRITE | MAP_EXECUTABLE | MAP_32BIT, fd_offset); - up_write(¤t->mm->mmap_sem); if (error != N_TXTADDR(ex)) { send_sig(SIGKILL, current, 0); return error; } - down_write(¤t->mm->mmap_sem); - error = do_mmap(bprm->file, N_DATADDR(ex), ex.a_data, + error = vm_mmap(bprm->file, N_DATADDR(ex), ex.a_data, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_FIXED | MAP_PRIVATE | MAP_DENYWRITE | MAP_EXECUTABLE | MAP_32BIT, fd_offset + ex.a_text); - up_write(¤t->mm->mmap_sem); if (error != N_DATADDR(ex)) { send_sig(SIGKILL, current, 0); return error; @@ -476,9 +465,7 @@ static int load_aout_library(struct file *file) error_time = jiffies; } #endif - down_write(¤t->mm->mmap_sem); - do_brk(start_addr, ex.a_text + ex.a_data + ex.a_bss); - up_write(¤t->mm->mmap_sem); + vm_brk(start_addr, ex.a_text + ex.a_data + ex.a_bss); file->f_op->read(file, (char __user *)start_addr, ex.a_text + ex.a_data, &pos); @@ -490,12 +477,10 @@ static int load_aout_library(struct file *file) goto out; } /* Now use mmap to map the library into memory. */ - down_write(¤t->mm->mmap_sem); - error = do_mmap(file, start_addr, ex.a_text + ex.a_data, + error = vm_mmap(file, start_addr, ex.a_text + ex.a_data, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_FIXED | MAP_PRIVATE | MAP_DENYWRITE | MAP_32BIT, N_TXTOFF(ex)); - up_write(¤t->mm->mmap_sem); retval = error; if (error != start_addr) goto out; @@ -503,9 +488,7 @@ static int load_aout_library(struct file *file) len = PAGE_ALIGN(ex.a_text + ex.a_data); bss = ex.a_text + ex.a_data + ex.a_bss; if (bss > len) { - down_write(¤t->mm->mmap_sem); - error = do_brk(start_addr + len, bss - len); - up_write(¤t->mm->mmap_sem); + error = vm_brk(start_addr + len, bss - len); retval = error; if (error != start_addr + len) goto out; diff --git a/arch/x86/include/asm/cmpxchg.h b/arch/x86/include/asm/cmpxchg.h index b3b733262909..99480e55973d 100644 --- a/arch/x86/include/asm/cmpxchg.h +++ b/arch/x86/include/asm/cmpxchg.h @@ -43,7 +43,7 @@ extern void __add_wrong_size(void) switch (sizeof(*(ptr))) { \ case __X86_CASE_B: \ asm volatile (lock #op "b %b0, %1\n" \ - : "+r" (__ret), "+m" (*(ptr)) \ + : "+q" (__ret), "+m" (*(ptr)) \ : : "memory", "cc"); \ break; \ case __X86_CASE_W: \ @@ -173,7 +173,7 @@ extern void __add_wrong_size(void) switch (sizeof(*(ptr))) { \ case __X86_CASE_B: \ asm volatile (lock "addb %b1, %0\n" \ - : "+m" (*(ptr)) : "ri" (inc) \ + : "+m" (*(ptr)) : "qi" (inc) \ : "memory", "cc"); \ break; \ case __X86_CASE_W: \ diff --git a/arch/x86/include/asm/kvm_para.h b/arch/x86/include/asm/kvm_para.h index 734c3767cfac..183922e13de1 100644 --- a/arch/x86/include/asm/kvm_para.h +++ b/arch/x86/include/asm/kvm_para.h @@ -170,6 +170,9 @@ static inline int kvm_para_available(void) unsigned int eax, ebx, ecx, edx; char signature[13]; + if (boot_cpu_data.cpuid_level < 0) + return 0; /* So we don't blow up on old processors */ + cpuid(KVM_CPUID_SIGNATURE, &eax, &ebx, &ecx, &edx); memcpy(signature + 0, &ebx, 4); memcpy(signature + 4, &ecx, 4); diff --git a/arch/x86/include/asm/posix_types.h b/arch/x86/include/asm/posix_types.h index 3427b7798dbc..7ef7c3020e5c 100644 --- a/arch/x86/include/asm/posix_types.h +++ b/arch/x86/include/asm/posix_types.h @@ -7,9 +7,9 @@ #else # ifdef __i386__ # include "posix_types_32.h" -# elif defined(__LP64__) -# include "posix_types_64.h" -# else +# elif defined(__ILP32__) # include "posix_types_x32.h" +# else +# include "posix_types_64.h" # endif #endif diff --git a/arch/x86/include/asm/sigcontext.h b/arch/x86/include/asm/sigcontext.h index 4a085383af27..5ca71c065eef 100644 --- a/arch/x86/include/asm/sigcontext.h +++ b/arch/x86/include/asm/sigcontext.h @@ -257,7 +257,7 @@ struct sigcontext { __u64 oldmask; __u64 cr2; struct _fpstate __user *fpstate; /* zero when no FPU context */ -#ifndef __LP64__ +#ifdef __ILP32__ __u32 __fpstate_pad; #endif __u64 reserved1[8]; diff --git a/arch/x86/include/asm/siginfo.h b/arch/x86/include/asm/siginfo.h index fc1aa5535646..34c47b3341c0 100644 --- a/arch/x86/include/asm/siginfo.h +++ b/arch/x86/include/asm/siginfo.h @@ -2,7 +2,13 @@ #define _ASM_X86_SIGINFO_H #ifdef __x86_64__ -# define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int)) +# ifdef __ILP32__ /* x32 */ +typedef long long __kernel_si_clock_t __attribute__((aligned(4))); +# define __ARCH_SI_CLOCK_T __kernel_si_clock_t +# define __ARCH_SI_ATTRIBUTES __attribute__((aligned(8))) +# else /* x86-64 */ +# define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int)) +# endif #endif #include <asm-generic/siginfo.h> diff --git a/arch/x86/include/asm/stat.h b/arch/x86/include/asm/stat.h index e0b1d9bbcbc6..7b3ddc348585 100644 --- a/arch/x86/include/asm/stat.h +++ b/arch/x86/include/asm/stat.h @@ -25,6 +25,12 @@ struct stat { unsigned long __unused5; }; +/* We don't need to memset the whole thing just to initialize the padding */ +#define INIT_STRUCT_STAT_PADDING(st) do { \ + st.__unused4 = 0; \ + st.__unused5 = 0; \ +} while (0) + #define STAT64_HAS_BROKEN_ST_INO 1 /* This matches struct stat64 in glibc2.1, hence the absolutely @@ -63,6 +69,12 @@ struct stat64 { unsigned long long st_ino; }; +/* We don't need to memset the whole thing just to initialize the padding */ +#define INIT_STRUCT_STAT64_PADDING(st) do { \ + memset(&st.__pad0, 0, sizeof(st.__pad0)); \ + memset(&st.__pad3, 0, sizeof(st.__pad3)); \ +} while (0) + #else /* __i386__ */ struct stat { @@ -87,6 +99,15 @@ struct stat { unsigned long st_ctime_nsec; long __unused[3]; }; + +/* We don't need to memset the whole thing just to initialize the padding */ +#define INIT_STRUCT_STAT_PADDING(st) do { \ + st.__pad0 = 0; \ + st.__unused[0] = 0; \ + st.__unused[1] = 0; \ + st.__unused[2] = 0; \ +} while (0) + #endif /* for 32bit emulation and 32 bit kernels */ diff --git a/arch/x86/include/asm/uaccess.h b/arch/x86/include/asm/uaccess.h index 8be5f54d9360..e0544597cfe7 100644 --- a/arch/x86/include/asm/uaccess.h +++ b/arch/x86/include/asm/uaccess.h @@ -557,6 +557,8 @@ struct __large_struct { unsigned long buf[100]; }; extern unsigned long copy_from_user_nmi(void *to, const void __user *from, unsigned long n); +extern __must_check long +strncpy_from_user(char *dst, const char __user *src, long count); /* * movsl can be slow when source and dest are not both 8-byte aligned diff --git a/arch/x86/include/asm/uaccess_32.h b/arch/x86/include/asm/uaccess_32.h index 566e803cc602..8084bc73b18c 100644 --- a/arch/x86/include/asm/uaccess_32.h +++ b/arch/x86/include/asm/uaccess_32.h @@ -213,11 +213,6 @@ static inline unsigned long __must_check copy_from_user(void *to, return n; } -long __must_check strncpy_from_user(char *dst, const char __user *src, - long count); -long __must_check __strncpy_from_user(char *dst, - const char __user *src, long count); - /** * strlen_user: - Get the size of a string in user space. * @str: The string to measure. diff --git a/arch/x86/include/asm/uaccess_64.h b/arch/x86/include/asm/uaccess_64.h index 1c66d30971ad..fcd4b6f3ef02 100644 --- a/arch/x86/include/asm/uaccess_64.h +++ b/arch/x86/include/asm/uaccess_64.h @@ -208,10 +208,6 @@ int __copy_in_user(void __user *dst, const void __user *src, unsigned size) } } -__must_check long -strncpy_from_user(char *dst, const char __user *src, long count); -__must_check long -__strncpy_from_user(char *dst, const char __user *src, long count); __must_check long strnlen_user(const char __user *str, long n); __must_check long __strnlen_user(const char __user *str, long n); __must_check long strlen_user(const char __user *str); diff --git a/arch/x86/include/asm/unistd.h b/arch/x86/include/asm/unistd.h index 37cdc9d99bb1..4437001d8e3d 100644 --- a/arch/x86/include/asm/unistd.h +++ b/arch/x86/include/asm/unistd.h @@ -63,10 +63,10 @@ #else # ifdef __i386__ # include <asm/unistd_32.h> -# elif defined(__LP64__) -# include <asm/unistd_64.h> -# else +# elif defined(__ILP32__) # include <asm/unistd_x32.h> +# else +# include <asm/unistd_64.h> # endif #endif diff --git a/arch/x86/include/asm/word-at-a-time.h b/arch/x86/include/asm/word-at-a-time.h index 6fe6767b7124..e58f03b206c3 100644 --- a/arch/x86/include/asm/word-at-a-time.h +++ b/arch/x86/include/asm/word-at-a-time.h @@ -43,4 +43,37 @@ static inline unsigned long has_zero(unsigned long a) return ((a - REPEAT_BYTE(0x01)) & ~a) & REPEAT_BYTE(0x80); } +/* + * Load an unaligned word from kernel space. + * + * In the (very unlikely) case of the word being a page-crosser + * and the next page not being mapped, take the exception and + * return zeroes in the non-existing part. + */ +static inline unsigned long load_unaligned_zeropad(const void *addr) +{ + unsigned long ret, dummy; + + asm( + "1:\tmov %2,%0\n" + "2:\n" + ".section .fixup,\"ax\"\n" + "3:\t" + "lea %2,%1\n\t" + "and %3,%1\n\t" + "mov (%1),%0\n\t" + "leal %2,%%ecx\n\t" + "andl %4,%%ecx\n\t" + "shll $3,%%ecx\n\t" + "shr %%cl,%0\n\t" + "jmp 2b\n" + ".previous\n" + _ASM_EXTABLE(1b, 3b) + :"=&r" (ret),"=&c" (dummy) + :"m" (*(unsigned long *)addr), + "i" (-sizeof(unsigned long)), + "i" (sizeof(unsigned long)-1)); + return ret; +} + #endif /* _ASM_WORD_AT_A_TIME_H */ diff --git a/arch/x86/include/asm/x86_init.h b/arch/x86/include/asm/x86_init.h index baaca8defec8..764b66a4cf89 100644 --- a/arch/x86/include/asm/x86_init.h +++ b/arch/x86/include/asm/x86_init.h @@ -195,6 +195,5 @@ extern struct x86_msi_ops x86_msi; extern void x86_init_noop(void); extern void x86_init_uint_noop(unsigned int unused); -extern void x86_default_fixup_cpu_id(struct cpuinfo_x86 *c, int node); #endif diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c index a415b1f44365..7c439fe4941b 100644 --- a/arch/x86/kernel/acpi/boot.c +++ b/arch/x86/kernel/acpi/boot.c @@ -593,7 +593,7 @@ void __init acpi_set_irq_model_ioapic(void) #ifdef CONFIG_ACPI_HOTPLUG_CPU #include <acpi/processor.h> -static void __cpuinitdata acpi_map_cpu2node(acpi_handle handle, int cpu, int physid) +static void __cpuinit acpi_map_cpu2node(acpi_handle handle, int cpu, int physid) { #ifdef CONFIG_ACPI_NUMA int nid; diff --git a/arch/x86/kernel/acpi/sleep.c b/arch/x86/kernel/acpi/sleep.c index 103b6ab368d3..146a49c763a4 100644 --- a/arch/x86/kernel/acpi/sleep.c +++ b/arch/x86/kernel/acpi/sleep.c @@ -24,6 +24,10 @@ unsigned long acpi_realmode_flags; static char temp_stack[4096]; #endif +asmlinkage void acpi_enter_s3(void) +{ + acpi_enter_sleep_state(3, wake_sleep_flags); +} /** * acpi_suspend_lowlevel - save kernel state * diff --git a/arch/x86/kernel/acpi/sleep.h b/arch/x86/kernel/acpi/sleep.h index 416d4be13fef..d68677a2a010 100644 --- a/arch/x86/kernel/acpi/sleep.h +++ b/arch/x86/kernel/acpi/sleep.h @@ -3,12 +3,16 @@ */ #include <asm/trampoline.h> +#include <linux/linkage.h> extern unsigned long saved_video_mode; extern long saved_magic; extern int wakeup_pmode_return; +extern u8 wake_sleep_flags; +extern asmlinkage void acpi_enter_s3(void); + extern unsigned long acpi_copy_wakeup_routine(unsigned long); extern void wakeup_long64(void); diff --git a/arch/x86/kernel/acpi/wakeup_32.S b/arch/x86/kernel/acpi/wakeup_32.S index 13ab720573e3..72610839f03b 100644 --- a/arch/x86/kernel/acpi/wakeup_32.S +++ b/arch/x86/kernel/acpi/wakeup_32.S @@ -74,9 +74,7 @@ restore_registers: ENTRY(do_suspend_lowlevel) call save_processor_state call save_registers - pushl $3 - call acpi_enter_sleep_state - addl $4, %esp + call acpi_enter_s3 # In case of S3 failure, we'll emerge here. Jump # to ret_point to recover diff --git a/arch/x86/kernel/acpi/wakeup_64.S b/arch/x86/kernel/acpi/wakeup_64.S index 8ea5164cbd04..014d1d28c397 100644 --- a/arch/x86/kernel/acpi/wakeup_64.S +++ b/arch/x86/kernel/acpi/wakeup_64.S @@ -71,9 +71,7 @@ ENTRY(do_suspend_lowlevel) movq %rsi, saved_rsi addq $8, %rsp - movl $3, %edi - xorl %eax, %eax - call acpi_enter_sleep_state + call acpi_enter_s3 /* in case something went wrong, restore the machine status and go on */ jmp resume_point diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index 11544d8f1e97..edc24480469f 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -1637,9 +1637,11 @@ static int __init apic_verify(void) mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; /* The BIOS may have set up the APIC at some other address */ - rdmsr(MSR_IA32_APICBASE, l, h); - if (l & MSR_IA32_APICBASE_ENABLE) - mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; + if (boot_cpu_data.x86 >= 6) { + rdmsr(MSR_IA32_APICBASE, l, h); + if (l & MSR_IA32_APICBASE_ENABLE) + mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; + } pr_info("Found and enabled local APIC!\n"); return 0; @@ -1657,13 +1659,15 @@ int __init apic_force_enable(unsigned long addr) * MSR. This can only be done in software for Intel P6 or later * and AMD K7 (Model > 1) or later. */ - rdmsr(MSR_IA32_APICBASE, l, h); - if (!(l & MSR_IA32_APICBASE_ENABLE)) { - pr_info("Local APIC disabled by BIOS -- reenabling.\n"); - l &= ~MSR_IA32_APICBASE_BASE; - l |= MSR_IA32_APICBASE_ENABLE | addr; - wrmsr(MSR_IA32_APICBASE, l, h); - enabled_via_apicbase = 1; + if (boot_cpu_data.x86 >= 6) { + rdmsr(MSR_IA32_APICBASE, l, h); + if (!(l & MSR_IA32_APICBASE_ENABLE)) { + pr_info("Local APIC disabled by BIOS -- reenabling.\n"); + l &= ~MSR_IA32_APICBASE_BASE; + l |= MSR_IA32_APICBASE_ENABLE | addr; + wrmsr(MSR_IA32_APICBASE, l, h); + enabled_via_apicbase = 1; + } } return apic_verify(); } @@ -2209,10 +2213,12 @@ static void lapic_resume(void) * FIXME! This will be wrong if we ever support suspend on * SMP! We'll need to do this as part of the CPU restore! */ - rdmsr(MSR_IA32_APICBASE, l, h); - l &= ~MSR_IA32_APICBASE_BASE; - l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; - wrmsr(MSR_IA32_APICBASE, l, h); + if (boot_cpu_data.x86 >= 6) { + rdmsr(MSR_IA32_APICBASE, l, h); + l &= ~MSR_IA32_APICBASE_BASE; + l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; + wrmsr(MSR_IA32_APICBASE, l, h); + } } maxlvt = lapic_get_maxlvt(); diff --git a/arch/x86/kernel/apic/apic_numachip.c b/arch/x86/kernel/apic/apic_numachip.c index 899803e03214..23e75422e013 100644 --- a/arch/x86/kernel/apic/apic_numachip.c +++ b/arch/x86/kernel/apic/apic_numachip.c @@ -207,8 +207,11 @@ static void __init map_csrs(void) static void fixup_cpu_id(struct cpuinfo_x86 *c, int node) { - c->phys_proc_id = node; - per_cpu(cpu_llc_id, smp_processor_id()) = node; + + if (c->phys_proc_id != node) { + c->phys_proc_id = node; + per_cpu(cpu_llc_id, smp_processor_id()) = node; + } } static int __init numachip_system_init(void) diff --git a/arch/x86/kernel/apic/x2apic_phys.c b/arch/x86/kernel/apic/x2apic_phys.c index 8a778db45e3a..991e315f4227 100644 --- a/arch/x86/kernel/apic/x2apic_phys.c +++ b/arch/x86/kernel/apic/x2apic_phys.c @@ -24,6 +24,12 @@ static int x2apic_acpi_madt_oem_check(char *oem_id, char *oem_table_id) { if (x2apic_phys) return x2apic_enabled(); + else if ((acpi_gbl_FADT.header.revision >= FADT2_REVISION_ID) && + (acpi_gbl_FADT.flags & ACPI_FADT_APIC_PHYSICAL) && + x2apic_enabled()) { + printk(KERN_DEBUG "System requires x2apic physical mode\n"); + return 1; + } else return 0; } diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 0a44b90602b0..146bb6218eec 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -26,7 +26,8 @@ * contact AMD for precise details and a CPU swap. * * See http://www.multimania.com/poulot/k6bug.html - * http://www.amd.com/K6/k6docs/revgd.html + * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6" + * (Publication # 21266 Issue Date: August 1998) * * The following test is erm.. interesting. AMD neglected to up * the chip setting when fixing the bug but they also tweaked some @@ -94,7 +95,6 @@ static void __cpuinit init_amd_k6(struct cpuinfo_x86 *c) "system stability may be impaired when more than 32 MB are used.\n"); else printk(KERN_CONT "probably OK (after B9730xxxx).\n"); - printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n"); } /* K6 with old style WHCR */ @@ -353,10 +353,11 @@ static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c) node = per_cpu(cpu_llc_id, cpu); /* - * If core numbers are inconsistent, it's likely a multi-fabric platform, - * so invoke platform-specific handler + * On multi-fabric platform (e.g. Numascale NumaChip) a + * platform-specific handler needs to be called to fixup some + * IDs of the CPU. */ - if (c->phys_proc_id != node) + if (x86_cpuinit.fixup_cpu_id) x86_cpuinit.fixup_cpu_id(c, node); if (!node_online(node)) { @@ -579,6 +580,24 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c) } } + /* re-enable TopologyExtensions if switched off by BIOS */ + if ((c->x86 == 0x15) && + (c->x86_model >= 0x10) && (c->x86_model <= 0x1f) && + !cpu_has(c, X86_FEATURE_TOPOEXT)) { + u64 val; + + if (!rdmsrl_amd_safe(0xc0011005, &val)) { + val |= 1ULL << 54; + wrmsrl_amd_safe(0xc0011005, val); + rdmsrl(0xc0011005, val); + if (val & (1ULL << 54)) { + set_cpu_cap(c, X86_FEATURE_TOPOEXT); + printk(KERN_INFO FW_INFO "CPU: Re-enabling " + "disabled Topology Extensions Support\n"); + } + } + } + cpu_detect_cache_sizes(c); /* Multi core CPU? */ diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 67e258362a3d..cf79302198a6 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1163,15 +1163,6 @@ static void dbg_restore_debug_regs(void) #endif /* ! CONFIG_KGDB */ /* - * Prints an error where the NUMA and configured core-number mismatch and the - * platform didn't override this to fix it up - */ -void __cpuinit x86_default_fixup_cpu_id(struct cpuinfo_x86 *c, int node) -{ - pr_err("NUMA core number %d differs from configured core number %d\n", node, c->phys_proc_id); -} - -/* * cpu_init() initializes state that is per-CPU. Some data is already * initialized (naturally) in the bootstrap process, such as the GDT * and IDT. We reload them nevertheless, this function acts as a diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c index 73d08ed98a64..b8f3653dddbc 100644 --- a/arch/x86/kernel/cpu/intel_cacheinfo.c +++ b/arch/x86/kernel/cpu/intel_cacheinfo.c @@ -433,14 +433,14 @@ int amd_set_l3_disable_slot(struct amd_northbridge *nb, int cpu, unsigned slot, /* check if @slot is already used or the index is already disabled */ ret = amd_get_l3_disable_slot(nb, slot); if (ret >= 0) - return -EINVAL; + return -EEXIST; if (index > nb->l3_cache.indices) return -EINVAL; /* check whether the other slot has disabled the same index already */ if (index == amd_get_l3_disable_slot(nb, !slot)) - return -EINVAL; + return -EEXIST; amd_l3_disable_index(nb, cpu, slot, index); @@ -468,8 +468,8 @@ static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf, err = amd_set_l3_disable_slot(this_leaf->base.nb, cpu, slot, val); if (err) { if (err == -EEXIST) - printk(KERN_WARNING "L3 disable slot %d in use!\n", - slot); + pr_warning("L3 slot %d in use/index already disabled!\n", + slot); return err; } return count; diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c index d086a09c087d..11c9166c3337 100644 --- a/arch/x86/kernel/cpu/mcheck/mce.c +++ b/arch/x86/kernel/cpu/mcheck/mce.c @@ -945,9 +945,10 @@ struct mce_info { atomic_t inuse; struct task_struct *t; __u64 paddr; + int restartable; } mce_info[MCE_INFO_MAX]; -static void mce_save_info(__u64 addr) +static void mce_save_info(__u64 addr, int c) { struct mce_info *mi; @@ -955,6 +956,7 @@ static void mce_save_info(__u64 addr) if (atomic_cmpxchg(&mi->inuse, 0, 1) == 0) { mi->t = current; mi->paddr = addr; + mi->restartable = c; return; } } @@ -1130,7 +1132,7 @@ void do_machine_check(struct pt_regs *regs, long error_code) mce_panic("Fatal machine check on current CPU", &m, msg); if (worst == MCE_AR_SEVERITY) { /* schedule action before return to userland */ - mce_save_info(m.addr); + mce_save_info(m.addr, m.mcgstatus & MCG_STATUS_RIPV); set_thread_flag(TIF_MCE_NOTIFY); } else if (kill_it) { force_sig(SIGBUS, current); @@ -1179,7 +1181,13 @@ void mce_notify_process(void) pr_err("Uncorrected hardware memory error in user-access at %llx", mi->paddr); - if (memory_failure(pfn, MCE_VECTOR, MF_ACTION_REQUIRED) < 0) { + /* + * We must call memory_failure() here even if the current process is + * doomed. We still need to mark the page as poisoned and alert any + * other users of the page. + */ + if (memory_failure(pfn, MCE_VECTOR, MF_ACTION_REQUIRED) < 0 || + mi->restartable == 0) { pr_err("Memory error not recovered"); force_sig(SIGBUS, current); } diff --git a/arch/x86/kernel/i387.c b/arch/x86/kernel/i387.c index 7734bcbb5a3a..2d6e6498c176 100644 --- a/arch/x86/kernel/i387.c +++ b/arch/x86/kernel/i387.c @@ -235,6 +235,7 @@ int init_fpu(struct task_struct *tsk) if (tsk_used_math(tsk)) { if (HAVE_HWFP && tsk == current) unlazy_fpu(tsk); + tsk->thread.fpu.last_cpu = ~0; return 0; } diff --git a/arch/x86/kernel/kvm.c b/arch/x86/kernel/kvm.c index b8ba6e4a27e4..e554e5ad2fe8 100644 --- a/arch/x86/kernel/kvm.c +++ b/arch/x86/kernel/kvm.c @@ -79,7 +79,6 @@ struct kvm_task_sleep_node { u32 token; int cpu; bool halted; - struct mm_struct *mm; }; static struct kvm_task_sleep_head { @@ -126,9 +125,7 @@ void kvm_async_pf_task_wait(u32 token) n.token = token; n.cpu = smp_processor_id(); - n.mm = current->active_mm; n.halted = idle || preempt_count() > 1; - atomic_inc(&n.mm->mm_count); init_waitqueue_head(&n.wq); hlist_add_head(&n.link, &b->list); spin_unlock(&b->lock); @@ -161,9 +158,6 @@ EXPORT_SYMBOL_GPL(kvm_async_pf_task_wait); static void apf_task_wake_one(struct kvm_task_sleep_node *n) { hlist_del_init(&n->link); - if (!n->mm) - return; - mmdrop(n->mm); if (n->halted) smp_send_reschedule(n->cpu); else if (waitqueue_active(&n->wq)) @@ -207,7 +201,7 @@ again: * async PF was not yet handled. * Add dummy entry for the token. */ - n = kmalloc(sizeof(*n), GFP_ATOMIC); + n = kzalloc(sizeof(*n), GFP_ATOMIC); if (!n) { /* * Allocation failed! Busy wait while other cpu @@ -219,7 +213,6 @@ again: } n->token = token; n->cpu = smp_processor_id(); - n->mm = NULL; init_waitqueue_head(&n->wq); hlist_add_head(&n->link, &b->list); } else diff --git a/arch/x86/kernel/microcode_amd.c b/arch/x86/kernel/microcode_amd.c index 73465aab28f8..8a2ce8fd41c0 100644 --- a/arch/x86/kernel/microcode_amd.c +++ b/arch/x86/kernel/microcode_amd.c @@ -82,11 +82,6 @@ static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig) { struct cpuinfo_x86 *c = &cpu_data(cpu); - if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) { - pr_warning("CPU%d: family %d not supported\n", cpu, c->x86); - return -1; - } - csig->rev = c->microcode; pr_info("CPU%d: patch_level=0x%08x\n", cpu, csig->rev); @@ -380,6 +375,13 @@ static struct microcode_ops microcode_amd_ops = { struct microcode_ops * __init init_amd_microcode(void) { + struct cpuinfo_x86 *c = &cpu_data(0); + + if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) { + pr_warning("AMD CPU family 0x%x not supported\n", c->x86); + return NULL; + } + patch = (void *)get_zeroed_page(GFP_KERNEL); if (!patch) return NULL; diff --git a/arch/x86/kernel/microcode_core.c b/arch/x86/kernel/microcode_core.c index 87a0f8688301..c9bda6d6035c 100644 --- a/arch/x86/kernel/microcode_core.c +++ b/arch/x86/kernel/microcode_core.c @@ -419,10 +419,8 @@ static int mc_device_add(struct device *dev, struct subsys_interface *sif) if (err) return err; - if (microcode_init_cpu(cpu) == UCODE_ERROR) { - sysfs_remove_group(&dev->kobj, &mc_attr_group); + if (microcode_init_cpu(cpu) == UCODE_ERROR) return -EINVAL; - } return err; } @@ -528,11 +526,11 @@ static int __init microcode_init(void) microcode_ops = init_intel_microcode(); else if (c->x86_vendor == X86_VENDOR_AMD) microcode_ops = init_amd_microcode(); - - if (!microcode_ops) { + else pr_err("no support for this CPU vendor\n"); + + if (!microcode_ops) return -ENODEV; - } microcode_pdev = platform_device_register_simple("microcode", -1, NULL, 0); diff --git a/arch/x86/kernel/microcode_intel.c b/arch/x86/kernel/microcode_intel.c index 3ca42d0e43a2..0327e2b3c408 100644 --- a/arch/x86/kernel/microcode_intel.c +++ b/arch/x86/kernel/microcode_intel.c @@ -147,12 +147,6 @@ static int collect_cpu_info(int cpu_num, struct cpu_signature *csig) memset(csig, 0, sizeof(*csig)); - if (c->x86_vendor != X86_VENDOR_INTEL || c->x86 < 6 || - cpu_has(c, X86_FEATURE_IA64)) { - pr_err("CPU%d not a capable Intel processor\n", cpu_num); - return -1; - } - csig->sig = cpuid_eax(0x00000001); if ((c->x86_model >= 5) || (c->x86 > 6)) { @@ -463,6 +457,14 @@ static struct microcode_ops microcode_intel_ops = { struct microcode_ops * __init init_intel_microcode(void) { + struct cpuinfo_x86 *c = &cpu_data(0); + + if (c->x86_vendor != X86_VENDOR_INTEL || c->x86 < 6 || + cpu_has(c, X86_FEATURE_IA64)) { + pr_err("Intel CPU family 0x%x not supported\n", c->x86); + return NULL; + } + return µcode_intel_ops; } diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c index 733ca39f367e..43d8b48b23e6 100644 --- a/arch/x86/kernel/process_64.c +++ b/arch/x86/kernel/process_64.c @@ -423,6 +423,7 @@ void set_personality_ia32(bool x32) current_thread_info()->status |= TS_COMPAT; } } +EXPORT_SYMBOL_GPL(set_personality_ia32); unsigned long get_wchan(struct task_struct *p) { diff --git a/arch/x86/kernel/setup_percpu.c b/arch/x86/kernel/setup_percpu.c index 71f4727da373..5a98aa272184 100644 --- a/arch/x86/kernel/setup_percpu.c +++ b/arch/x86/kernel/setup_percpu.c @@ -185,10 +185,22 @@ void __init setup_per_cpu_areas(void) #endif rc = -EINVAL; if (pcpu_chosen_fc != PCPU_FC_PAGE) { - const size_t atom_size = cpu_has_pse ? PMD_SIZE : PAGE_SIZE; const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE - PERCPU_FIRST_CHUNK_RESERVE; + size_t atom_size; + /* + * On 64bit, use PMD_SIZE for atom_size so that embedded + * percpu areas are aligned to PMD. This, in the future, + * can also allow using PMD mappings in vmalloc area. Use + * PAGE_SIZE on 32bit as vmalloc space is highly contended + * and large vmalloc area allocs can easily fail. + */ +#ifdef CONFIG_X86_64 + atom_size = PMD_SIZE; +#else + atom_size = PAGE_SIZE; +#endif rc = pcpu_embed_first_chunk(PERCPU_FIRST_CHUNK_RESERVE, dyn_size, atom_size, pcpu_cpu_distance, diff --git a/arch/x86/kernel/vsyscall_64.c b/arch/x86/kernel/vsyscall_64.c index f386dc49f988..7515cf0e1805 100644 --- a/arch/x86/kernel/vsyscall_64.c +++ b/arch/x86/kernel/vsyscall_64.c @@ -216,9 +216,9 @@ bool emulate_vsyscall(struct pt_regs *regs, unsigned long address) current_thread_info()->sig_on_uaccess_error = 1; /* - * 0 is a valid user pointer (in the access_ok sense) on 32-bit and + * NULL is a valid user pointer (in the access_ok sense) on 32-bit and * 64-bit, so we don't need to special-case it here. For all the - * vsyscalls, 0 means "don't write anything" not "write it at + * vsyscalls, NULL means "don't write anything" not "write it at * address 0". */ ret = -EFAULT; @@ -247,7 +247,7 @@ bool emulate_vsyscall(struct pt_regs *regs, unsigned long address) ret = sys_getcpu((unsigned __user *)regs->di, (unsigned __user *)regs->si, - 0); + NULL); break; } diff --git a/arch/x86/kernel/x86_init.c b/arch/x86/kernel/x86_init.c index e9f265fd79ae..9cf71d0b2d37 100644 --- a/arch/x86/kernel/x86_init.c +++ b/arch/x86/kernel/x86_init.c @@ -93,7 +93,6 @@ struct x86_init_ops x86_init __initdata = { struct x86_cpuinit_ops x86_cpuinit __cpuinitdata = { .early_percpu_clock_init = x86_init_noop, .setup_percpu_clockev = setup_secondary_APIC_clock, - .fixup_cpu_id = x86_default_fixup_cpu_id, }; static void default_nmi_init(void) { }; diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index 173df38dbda5..2e88438ffd83 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -459,17 +459,17 @@ void kvm_pmu_cpuid_update(struct kvm_vcpu *vcpu) pmu->available_event_types = ~entry->ebx & ((1ull << bitmap_len) - 1); if (pmu->version == 1) { - pmu->global_ctrl = (1 << pmu->nr_arch_gp_counters) - 1; - return; + pmu->nr_arch_fixed_counters = 0; + } else { + pmu->nr_arch_fixed_counters = min((int)(entry->edx & 0x1f), + X86_PMC_MAX_FIXED); + pmu->counter_bitmask[KVM_PMC_FIXED] = + ((u64)1 << ((entry->edx >> 5) & 0xff)) - 1; } - pmu->nr_arch_fixed_counters = min((int)(entry->edx & 0x1f), - X86_PMC_MAX_FIXED); - pmu->counter_bitmask[KVM_PMC_FIXED] = - ((u64)1 << ((entry->edx >> 5) & 0xff)) - 1; - pmu->global_ctrl_mask = ~(((1 << pmu->nr_arch_gp_counters) - 1) - | (((1ull << pmu->nr_arch_fixed_counters) - 1) - << X86_PMC_IDX_FIXED)); + pmu->global_ctrl = ((1 << pmu->nr_arch_gp_counters) - 1) | + (((1ull << pmu->nr_arch_fixed_counters) - 1) << X86_PMC_IDX_FIXED); + pmu->global_ctrl_mask = ~pmu->global_ctrl; } void kvm_pmu_init(struct kvm_vcpu *vcpu) diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index ad85adfef843..4ff0ab9bc3c8 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -2210,9 +2210,12 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data) msr = find_msr_entry(vmx, msr_index); if (msr) { msr->data = data; - if (msr - vmx->guest_msrs < vmx->save_nmsrs) + if (msr - vmx->guest_msrs < vmx->save_nmsrs) { + preempt_disable(); kvm_set_shared_msr(msr->index, msr->data, msr->mask); + preempt_enable(); + } break; } ret = kvm_set_msr_common(vcpu, msr_index, data); diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 4044ce0bf7c1..185a2b823a2d 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -6336,13 +6336,11 @@ int kvm_arch_prepare_memory_region(struct kvm *kvm, if (npages && !old.rmap) { unsigned long userspace_addr; - down_write(¤t->mm->mmap_sem); - userspace_addr = do_mmap(NULL, 0, + userspace_addr = vm_mmap(NULL, 0, npages * PAGE_SIZE, PROT_READ | PROT_WRITE, map_flags, 0); - up_write(¤t->mm->mmap_sem); if (IS_ERR((void *)userspace_addr)) return PTR_ERR((void *)userspace_addr); @@ -6366,10 +6364,8 @@ void kvm_arch_commit_memory_region(struct kvm *kvm, if (!user_alloc && !old.user_alloc && old.rmap && !npages) { int ret; - down_write(¤t->mm->mmap_sem); - ret = do_munmap(current->mm, old.userspace_addr, + ret = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE); - up_write(¤t->mm->mmap_sem); if (ret < 0) printk(KERN_WARNING "kvm_vm_ioctl_set_memory_region: " @@ -6585,6 +6581,7 @@ void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, kvm_inject_page_fault(vcpu, &fault); } vcpu->arch.apf.halted = false; + vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; } bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu) diff --git a/arch/x86/lib/insn.c b/arch/x86/lib/insn.c index 25feb1ae71c5..b1e6c4b2e8eb 100644 --- a/arch/x86/lib/insn.c +++ b/arch/x86/lib/insn.c @@ -379,8 +379,8 @@ err_out: return; } -/* Decode moffset16/32/64 */ -static void __get_moffset(struct insn *insn) +/* Decode moffset16/32/64. Return 0 if failed */ +static int __get_moffset(struct insn *insn) { switch (insn->addr_bytes) { case 2: @@ -397,15 +397,19 @@ static void __get_moffset(struct insn *insn) insn->moffset2.value = get_next(int, insn); insn->moffset2.nbytes = 4; break; + default: /* opnd_bytes must be modified manually */ + goto err_out; } insn->moffset1.got = insn->moffset2.got = 1; + return 1; + err_out: - return; + return 0; } -/* Decode imm v32(Iz) */ -static void __get_immv32(struct insn *insn) +/* Decode imm v32(Iz). Return 0 if failed */ +static int __get_immv32(struct insn *insn) { switch (insn->opnd_bytes) { case 2: @@ -417,14 +421,18 @@ static void __get_immv32(struct insn *insn) insn->immediate.value = get_next(int, insn); insn->immediate.nbytes = 4; break; + default: /* opnd_bytes must be modified manually */ + goto err_out; } + return 1; + err_out: - return; + return 0; } -/* Decode imm v64(Iv/Ov) */ -static void __get_immv(struct insn *insn) +/* Decode imm v64(Iv/Ov), Return 0 if failed */ +static int __get_immv(struct insn *insn) { switch (insn->opnd_bytes) { case 2: @@ -441,15 +449,18 @@ static void __get_immv(struct insn *insn) insn->immediate2.value = get_next(int, insn); insn->immediate2.nbytes = 4; break; + default: /* opnd_bytes must be modified manually */ + goto err_out; } insn->immediate1.got = insn->immediate2.got = 1; + return 1; err_out: - return; + return 0; } /* Decode ptr16:16/32(Ap) */ -static void __get_immptr(struct insn *insn) +static int __get_immptr(struct insn *insn) { switch (insn->opnd_bytes) { case 2: @@ -462,14 +473,17 @@ static void __get_immptr(struct insn *insn) break; case 8: /* ptr16:64 is not exist (no segment) */ - return; + return 0; + default: /* opnd_bytes must be modified manually */ + goto err_out; } insn->immediate2.value = get_next(unsigned short, insn); insn->immediate2.nbytes = 2; insn->immediate1.got = insn->immediate2.got = 1; + return 1; err_out: - return; + return 0; } /** @@ -489,7 +503,8 @@ void insn_get_immediate(struct insn *insn) insn_get_displacement(insn); if (inat_has_moffset(insn->attr)) { - __get_moffset(insn); + if (!__get_moffset(insn)) + goto err_out; goto done; } @@ -517,16 +532,20 @@ void insn_get_immediate(struct insn *insn) insn->immediate2.nbytes = 4; break; case INAT_IMM_PTR: - __get_immptr(insn); + if (!__get_immptr(insn)) + goto err_out; break; case INAT_IMM_VWORD32: - __get_immv32(insn); + if (!__get_immv32(insn)) + goto err_out; break; case INAT_IMM_VWORD: - __get_immv(insn); + if (!__get_immv(insn)) + goto err_out; break; default: - break; + /* Here, insn must have an immediate, but failed */ + goto err_out; } if (inat_has_second_immediate(insn->attr)) { insn->immediate2.value = get_next(char, insn); diff --git a/arch/x86/lib/usercopy.c b/arch/x86/lib/usercopy.c index 97be9cb54483..2e4e4b02c37a 100644 --- a/arch/x86/lib/usercopy.c +++ b/arch/x86/lib/usercopy.c @@ -7,6 +7,8 @@ #include <linux/highmem.h> #include <linux/module.h> +#include <asm/word-at-a-time.h> + /* * best effort, GUP based copy_from_user() that is NMI-safe */ @@ -41,3 +43,100 @@ copy_from_user_nmi(void *to, const void __user *from, unsigned long n) return len; } EXPORT_SYMBOL_GPL(copy_from_user_nmi); + +/* + * Do a strncpy, return length of string without final '\0'. + * 'count' is the user-supplied count (return 'count' if we + * hit it), 'max' is the address space maximum (and we return + * -EFAULT if we hit it). + */ +static inline long do_strncpy_from_user(char *dst, const char __user *src, long count, unsigned long max) +{ + long res = 0; + + /* + * Truncate 'max' to the user-specified limit, so that + * we only have one limit we need to check in the loop + */ + if (max > count) + max = count; + + while (max >= sizeof(unsigned long)) { + unsigned long c, mask; + + /* Fall back to byte-at-a-time if we get a page fault */ + if (unlikely(__get_user(c,(unsigned long __user *)(src+res)))) + break; + mask = has_zero(c); + if (mask) { + mask = (mask - 1) & ~mask; + mask >>= 7; + *(unsigned long *)(dst+res) = c & mask; + return res + count_masked_bytes(mask); + } + *(unsigned long *)(dst+res) = c; + res += sizeof(unsigned long); + max -= sizeof(unsigned long); + } + + while (max) { + char c; + + if (unlikely(__get_user(c,src+res))) + return -EFAULT; + dst[res] = c; + if (!c) + return res; + res++; + max--; + } + + /* + * Uhhuh. We hit 'max'. But was that the user-specified maximum + * too? If so, that's ok - we got as much as the user asked for. + */ + if (res >= count) + return res; + + /* + * Nope: we hit the address space limit, and we still had more + * characters the caller would have wanted. That's an EFAULT. + */ + return -EFAULT; +} + +/** + * strncpy_from_user: - Copy a NUL terminated string from userspace. + * @dst: Destination address, in kernel space. This buffer must be at + * least @count bytes long. + * @src: Source address, in user space. + * @count: Maximum number of bytes to copy, including the trailing NUL. + * + * Copies a NUL-terminated string from userspace to kernel space. + * + * On success, returns the length of the string (not including the trailing + * NUL). + * + * If access to userspace fails, returns -EFAULT (some data may have been + * copied). + * + * If @count is smaller than the length of the string, copies @count bytes + * and returns @count. + */ +long +strncpy_from_user(char *dst, const char __user *src, long count) +{ + unsigned long max_addr, src_addr; + + if (unlikely(count <= 0)) + return 0; + + max_addr = current_thread_info()->addr_limit.seg; + src_addr = (unsigned long)src; + if (likely(src_addr < max_addr)) { + unsigned long max = max_addr - src_addr; + return do_strncpy_from_user(dst, src, count, max); + } + return -EFAULT; +} +EXPORT_SYMBOL(strncpy_from_user); diff --git a/arch/x86/lib/usercopy_32.c b/arch/x86/lib/usercopy_32.c index d9b094ca7aaa..ef2a6a5d78e3 100644 --- a/arch/x86/lib/usercopy_32.c +++ b/arch/x86/lib/usercopy_32.c @@ -33,93 +33,6 @@ static inline int __movsl_is_ok(unsigned long a1, unsigned long a2, unsigned lon __movsl_is_ok((unsigned long)(a1), (unsigned long)(a2), (n)) /* - * Copy a null terminated string from userspace. - */ - -#define __do_strncpy_from_user(dst, src, count, res) \ -do { \ - int __d0, __d1, __d2; \ - might_fault(); \ - __asm__ __volatile__( \ - " testl %1,%1\n" \ - " jz 2f\n" \ - "0: lodsb\n" \ - " stosb\n" \ - " testb %%al,%%al\n" \ - " jz 1f\n" \ - " decl %1\n" \ - " jnz 0b\n" \ - "1: subl %1,%0\n" \ - "2:\n" \ - ".section .fixup,\"ax\"\n" \ - "3: movl %5,%0\n" \ - " jmp 2b\n" \ - ".previous\n" \ - _ASM_EXTABLE(0b,3b) \ - : "=&d"(res), "=&c"(count), "=&a" (__d0), "=&S" (__d1), \ - "=&D" (__d2) \ - : "i"(-EFAULT), "0"(count), "1"(count), "3"(src), "4"(dst) \ - : "memory"); \ -} while (0) - -/** - * __strncpy_from_user: - Copy a NUL terminated string from userspace, with less checking. - * @dst: Destination address, in kernel space. This buffer must be at - * least @count bytes long. - * @src: Source address, in user space. - * @count: Maximum number of bytes to copy, including the trailing NUL. - * - * Copies a NUL-terminated string from userspace to kernel space. - * Caller must check the specified block with access_ok() before calling - * this function. - * - * On success, returns the length of the string (not including the trailing - * NUL). - * - * If access to userspace fails, returns -EFAULT (some data may have been - * copied). - * - * If @count is smaller than the length of the string, copies @count bytes - * and returns @count. - */ -long -__strncpy_from_user(char *dst, const char __user *src, long count) -{ - long res; - __do_strncpy_from_user(dst, src, count, res); - return res; -} -EXPORT_SYMBOL(__strncpy_from_user); - -/** - * strncpy_from_user: - Copy a NUL terminated string from userspace. - * @dst: Destination address, in kernel space. This buffer must be at - * least @count bytes long. - * @src: Source address, in user space. - * @count: Maximum number of bytes to copy, including the trailing NUL. - * - * Copies a NUL-terminated string from userspace to kernel space. - * - * On success, returns the length of the string (not including the trailing - * NUL). - * - * If access to userspace fails, returns -EFAULT (some data may have been - * copied). - * - * If @count is smaller than the length of the string, copies @count bytes - * and returns @count. - */ -long -strncpy_from_user(char *dst, const char __user *src, long count) -{ - long res = -EFAULT; - if (access_ok(VERIFY_READ, src, 1)) - __do_strncpy_from_user(dst, src, count, res); - return res; -} -EXPORT_SYMBOL(strncpy_from_user); - -/* * Zero Userspace */ diff --git a/arch/x86/lib/usercopy_64.c b/arch/x86/lib/usercopy_64.c index b7c2849ffb66..0d0326f388c0 100644 --- a/arch/x86/lib/usercopy_64.c +++ b/arch/x86/lib/usercopy_64.c @@ -9,55 +9,6 @@ #include <asm/uaccess.h> /* - * Copy a null terminated string from userspace. - */ - -#define __do_strncpy_from_user(dst,src,count,res) \ -do { \ - long __d0, __d1, __d2; \ - might_fault(); \ - __asm__ __volatile__( \ - " testq %1,%1\n" \ - " jz 2f\n" \ - "0: lodsb\n" \ - " stosb\n" \ - " testb %%al,%%al\n" \ - " jz 1f\n" \ - " decq %1\n" \ - " jnz 0b\n" \ - "1: subq %1,%0\n" \ - "2:\n" \ - ".section .fixup,\"ax\"\n" \ - "3: movq %5,%0\n" \ - " jmp 2b\n" \ - ".previous\n" \ - _ASM_EXTABLE(0b,3b) \ - : "=&r"(res), "=&c"(count), "=&a" (__d0), "=&S" (__d1), \ - "=&D" (__d2) \ - : "i"(-EFAULT), "0"(count), "1"(count), "3"(src), "4"(dst) \ - : "memory"); \ -} while (0) - -long -__strncpy_from_user(char *dst, const char __user *src, long count) -{ - long res; - __do_strncpy_from_user(dst, src, count, res); - return res; -} -EXPORT_SYMBOL(__strncpy_from_user); - -long -strncpy_from_user(char *dst, const char __user *src, long count) -{ - long res = -EFAULT; - if (access_ok(VERIFY_READ, src, 1)) - return __strncpy_from_user(dst, src, count); - return res; -} -EXPORT_SYMBOL(strncpy_from_user); - -/* * Zero Userspace */ diff --git a/arch/x86/pci/acpi.c b/arch/x86/pci/acpi.c index ed2835e148b5..fc09c2754e08 100644 --- a/arch/x86/pci/acpi.c +++ b/arch/x86/pci/acpi.c @@ -9,11 +9,11 @@ struct pci_root_info { struct acpi_device *bridge; - char *name; + char name[16]; unsigned int res_num; struct resource *res; - struct list_head *resources; int busnum; + struct pci_sysdata sd; }; static bool pci_use_crs = true; @@ -245,13 +245,6 @@ setup_resource(struct acpi_resource *acpi_res, void *data) return AE_OK; } -static bool resource_contains(struct resource *res, resource_size_t point) -{ - if (res->start <= point && point <= res->end) - return true; - return false; -} - static void coalesce_windows(struct pci_root_info *info, unsigned long type) { int i, j; @@ -272,10 +265,7 @@ static void coalesce_windows(struct pci_root_info *info, unsigned long type) * our resources no longer match the ACPI _CRS, but * the kernel resource tree doesn't allow overlaps. */ - if (resource_contains(res1, res2->start) || - resource_contains(res1, res2->end) || - resource_contains(res2, res1->start) || - resource_contains(res2, res1->end)) { + if (resource_overlaps(res1, res2)) { res1->start = min(res1->start, res2->start); res1->end = max(res1->end, res2->end); dev_info(&info->bridge->dev, @@ -287,7 +277,8 @@ static void coalesce_windows(struct pci_root_info *info, unsigned long type) } } -static void add_resources(struct pci_root_info *info) +static void add_resources(struct pci_root_info *info, + struct list_head *resources) { int i; struct resource *res, *root, *conflict; @@ -311,53 +302,74 @@ static void add_resources(struct pci_root_info *info) "ignoring host bridge window %pR (conflicts with %s %pR)\n", res, conflict->name, conflict); else - pci_add_resource(info->resources, res); + pci_add_resource(resources, res); } } +static void free_pci_root_info_res(struct pci_root_info *info) +{ + kfree(info->res); + info->res = NULL; + info->res_num = 0; +} + +static void __release_pci_root_info(struct pci_root_info *info) +{ + int i; + struct resource *res; + + for (i = 0; i < info->res_num; i++) { + res = &info->res[i]; + + if (!res->parent) + continue; + + if (!(res->flags & (IORESOURCE_MEM | IORESOURCE_IO))) + continue; + + release_resource(res); + } + + free_pci_root_info_res(info); + + kfree(info); +} +static void release_pci_root_info(struct pci_host_bridge *bridge) +{ + struct pci_root_info *info = bridge->release_data; + + __release_pci_root_info(info); +} + static void -get_current_resources(struct acpi_device *device, int busnum, - int domain, struct list_head *resources) +probe_pci_root_info(struct pci_root_info *info, struct acpi_device *device, + int busnum, int domain) { - struct pci_root_info info; size_t size; - info.bridge = device; - info.res_num = 0; - info.resources = resources; + info->bridge = device; + info->res_num = 0; acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_resource, - &info); - if (!info.res_num) + info); + if (!info->res_num) return; - size = sizeof(*info.res) * info.res_num; - info.res = kmalloc(size, GFP_KERNEL); - if (!info.res) + size = sizeof(*info->res) * info->res_num; + info->res_num = 0; + info->res = kmalloc(size, GFP_KERNEL); + if (!info->res) return; - info.name = kasprintf(GFP_KERNEL, "PCI Bus %04x:%02x", domain, busnum); - if (!info.name) - goto name_alloc_fail; + sprintf(info->name, "PCI Bus %04x:%02x", domain, busnum); - info.res_num = 0; acpi_walk_resources(device->handle, METHOD_NAME__CRS, setup_resource, - &info); - - if (pci_use_crs) { - add_resources(&info); - - return; - } - - kfree(info.name); - -name_alloc_fail: - kfree(info.res); + info); } struct pci_bus * __devinit pci_acpi_scan_root(struct acpi_pci_root *root) { struct acpi_device *device = root->device; + struct pci_root_info *info = NULL; int domain = root->segment; int busnum = root->secondary.start; LIST_HEAD(resources); @@ -389,17 +401,14 @@ struct pci_bus * __devinit pci_acpi_scan_root(struct acpi_pci_root *root) if (node != -1 && !node_online(node)) node = -1; - /* Allocate per-root-bus (not per bus) arch-specific data. - * TODO: leak; this memory is never freed. - * It's arguable whether it's worth the trouble to care. - */ - sd = kzalloc(sizeof(*sd), GFP_KERNEL); - if (!sd) { + info = kzalloc(sizeof(*info), GFP_KERNEL); + if (!info) { printk(KERN_WARNING "pci_bus %04x:%02x: " "ignored (out of memory)\n", domain, busnum); return NULL; } + sd = &info->sd; sd->domain = domain; sd->node = node; /* @@ -413,22 +422,32 @@ struct pci_bus * __devinit pci_acpi_scan_root(struct acpi_pci_root *root) * be replaced by sd. */ memcpy(bus->sysdata, sd, sizeof(*sd)); - kfree(sd); + kfree(info); } else { - get_current_resources(device, busnum, domain, &resources); + probe_pci_root_info(info, device, busnum, domain); /* * _CRS with no apertures is normal, so only fall back to * defaults or native bridge info if we're ignoring _CRS. */ - if (!pci_use_crs) + if (pci_use_crs) + add_resources(info, &resources); + else { + free_pci_root_info_res(info); x86_pci_root_bus_resources(busnum, &resources); + } + bus = pci_create_root_bus(NULL, busnum, &pci_root_ops, sd, &resources); - if (bus) + if (bus) { bus->subordinate = pci_scan_child_bus(bus); - else + pci_set_host_bridge_release( + to_pci_host_bridge(bus->bridge), + release_pci_root_info, info); + } else { pci_free_resource_list(&resources); + __release_pci_root_info(info); + } } /* After the PCI-E bus has been walked and all devices discovered, @@ -445,9 +464,6 @@ struct pci_bus * __devinit pci_acpi_scan_root(struct acpi_pci_root *root) } } - if (!bus) - kfree(sd); - if (bus && node != -1) { #ifdef CONFIG_ACPI_NUMA if (pxm >= 0) diff --git a/arch/x86/pci/amd_bus.c b/arch/x86/pci/amd_bus.c index 0567df3890e1..5aed49bff058 100644 --- a/arch/x86/pci/amd_bus.c +++ b/arch/x86/pci/amd_bus.c @@ -32,6 +32,27 @@ static struct pci_hostbridge_probe pci_probes[] __initdata = { #define RANGE_NUM 16 +static struct pci_root_info __init *find_pci_root_info(int node, int link) +{ + struct pci_root_info *info; + + /* find the position */ + list_for_each_entry(info, &pci_root_infos, list) + if (info->node == node && info->link == link) + return info; + + return NULL; +} + +static void __init set_mp_bus_range_to_node(int min_bus, int max_bus, int node) +{ +#ifdef CONFIG_NUMA + int j; + + for (j = min_bus; j <= max_bus; j++) + set_mp_bus_to_node(j, node); +#endif +} /** * early_fill_mp_bus_to_node() * called before pcibios_scan_root and pci_scan_bus @@ -41,7 +62,6 @@ static struct pci_hostbridge_probe pci_probes[] __initdata = { static int __init early_fill_mp_bus_info(void) { int i; - int j; unsigned bus; unsigned slot; int node; @@ -50,7 +70,6 @@ static int __init early_fill_mp_bus_info(void) int def_link; struct pci_root_info *info; u32 reg; - struct resource *res; u64 start; u64 end; struct range range[RANGE_NUM]; @@ -86,7 +105,6 @@ static int __init early_fill_mp_bus_info(void) if (!found) return 0; - pci_root_num = 0; for (i = 0; i < 4; i++) { int min_bus; int max_bus; @@ -99,19 +117,11 @@ static int __init early_fill_mp_bus_info(void) min_bus = (reg >> 16) & 0xff; max_bus = (reg >> 24) & 0xff; node = (reg >> 4) & 0x07; -#ifdef CONFIG_NUMA - for (j = min_bus; j <= max_bus; j++) - set_mp_bus_to_node(j, node); -#endif + set_mp_bus_range_to_node(min_bus, max_bus, node); link = (reg >> 8) & 0x03; - info = &pci_root_info[pci_root_num]; - info->bus_min = min_bus; - info->bus_max = max_bus; - info->node = node; - info->link = link; + info = alloc_pci_root_info(min_bus, max_bus, node, link); sprintf(info->name, "PCI Bus #%02x", min_bus); - pci_root_num++; } /* get the default node and link for left over res */ @@ -134,16 +144,10 @@ static int __init early_fill_mp_bus_info(void) link = (reg >> 4) & 0x03; end = (reg & 0xfff000) | 0xfff; - /* find the position */ - for (j = 0; j < pci_root_num; j++) { - info = &pci_root_info[j]; - if (info->node == node && info->link == link) - break; - } - if (j == pci_root_num) + info = find_pci_root_info(node, link); + if (!info) continue; /* not found */ - info = &pci_root_info[j]; printk(KERN_DEBUG "node %d link %d: io port [%llx, %llx]\n", node, link, start, end); @@ -155,13 +159,8 @@ static int __init early_fill_mp_bus_info(void) } /* add left over io port range to def node/link, [0, 0xffff] */ /* find the position */ - for (j = 0; j < pci_root_num; j++) { - info = &pci_root_info[j]; - if (info->node == def_node && info->link == def_link) - break; - } - if (j < pci_root_num) { - info = &pci_root_info[j]; + info = find_pci_root_info(def_node, def_link); + if (info) { for (i = 0; i < RANGE_NUM; i++) { if (!range[i].end) continue; @@ -214,16 +213,10 @@ static int __init early_fill_mp_bus_info(void) end <<= 8; end |= 0xffff; - /* find the position */ - for (j = 0; j < pci_root_num; j++) { - info = &pci_root_info[j]; - if (info->node == node && info->link == link) - break; - } - if (j == pci_root_num) - continue; /* not found */ + info = find_pci_root_info(node, link); - info = &pci_root_info[j]; + if (!info) + continue; printk(KERN_DEBUG "node %d link %d: mmio [%llx, %llx]", node, link, start, end); @@ -291,14 +284,8 @@ static int __init early_fill_mp_bus_info(void) * add left over mmio range to def node/link ? * that is tricky, just record range in from start_min to 4G */ - for (j = 0; j < pci_root_num; j++) { - info = &pci_root_info[j]; - if (info->node == def_node && info->link == def_link) - break; - } - if (j < pci_root_num) { - info = &pci_root_info[j]; - + info = find_pci_root_info(def_node, def_link); + if (info) { for (i = 0; i < RANGE_NUM; i++) { if (!range[i].end) continue; @@ -309,20 +296,16 @@ static int __init early_fill_mp_bus_info(void) } } - for (i = 0; i < pci_root_num; i++) { - int res_num; + list_for_each_entry(info, &pci_root_infos, list) { int busnum; + struct pci_root_res *root_res; - info = &pci_root_info[i]; - res_num = info->res_num; busnum = info->bus_min; printk(KERN_DEBUG "bus: [%02x, %02x] on node %x link %x\n", info->bus_min, info->bus_max, info->node, info->link); - for (j = 0; j < res_num; j++) { - res = &info->res[j]; - printk(KERN_DEBUG "bus: %02x index %x %pR\n", - busnum, j, res); - } + list_for_each_entry(root_res, &info->resources, list) + printk(KERN_DEBUG "bus: %02x %pR\n", + busnum, &root_res->res); } return 0; diff --git a/arch/x86/pci/broadcom_bus.c b/arch/x86/pci/broadcom_bus.c index f3a7c569a403..614392ced7d6 100644 --- a/arch/x86/pci/broadcom_bus.c +++ b/arch/x86/pci/broadcom_bus.c @@ -22,19 +22,15 @@ static void __init cnb20le_res(u8 bus, u8 slot, u8 func) { struct pci_root_info *info; + struct pci_root_res *root_res; struct resource res; u16 word1, word2; u8 fbus, lbus; - int i; - - info = &pci_root_info[pci_root_num]; - pci_root_num++; /* read the PCI bus numbers */ fbus = read_pci_config_byte(bus, slot, func, 0x44); lbus = read_pci_config_byte(bus, slot, func, 0x45); - info->bus_min = fbus; - info->bus_max = lbus; + info = alloc_pci_root_info(fbus, lbus, 0, 0); /* * Add the legacy IDE ports on bus 0 @@ -86,8 +82,8 @@ static void __init cnb20le_res(u8 bus, u8 slot, u8 func) res.flags = IORESOURCE_BUS; printk(KERN_INFO "CNB20LE PCI Host Bridge (domain 0000 %pR)\n", &res); - for (i = 0; i < info->res_num; i++) - printk(KERN_INFO "host bridge window %pR\n", &info->res[i]); + list_for_each_entry(root_res, &info->resources, list) + printk(KERN_INFO "host bridge window %pR\n", &root_res->res); } static int __init broadcom_postcore_init(void) diff --git a/arch/x86/pci/bus_numa.c b/arch/x86/pci/bus_numa.c index fd3f65510e9d..306579f7d0fd 100644 --- a/arch/x86/pci/bus_numa.c +++ b/arch/x86/pci/bus_numa.c @@ -4,35 +4,38 @@ #include "bus_numa.h" -int pci_root_num; -struct pci_root_info pci_root_info[PCI_ROOT_NR]; +LIST_HEAD(pci_root_infos); -void x86_pci_root_bus_resources(int bus, struct list_head *resources) +static struct pci_root_info *x86_find_pci_root_info(int bus) { - int i; - int j; struct pci_root_info *info; - if (!pci_root_num) - goto default_resources; + if (list_empty(&pci_root_infos)) + return NULL; - for (i = 0; i < pci_root_num; i++) { - if (pci_root_info[i].bus_min == bus) - break; - } + list_for_each_entry(info, &pci_root_infos, list) + if (info->bus_min == bus) + return info; + + return NULL; +} - if (i == pci_root_num) +void x86_pci_root_bus_resources(int bus, struct list_head *resources) +{ + struct pci_root_info *info = x86_find_pci_root_info(bus); + struct pci_root_res *root_res; + + if (!info) goto default_resources; printk(KERN_DEBUG "PCI: root bus %02x: hardware-probed resources\n", bus); - info = &pci_root_info[i]; - for (j = 0; j < info->res_num; j++) { + list_for_each_entry(root_res, &info->resources, list) { struct resource *res; struct resource *root; - res = &info->res[j]; + res = &root_res->res; pci_add_resource(resources, res); if (res->flags & IORESOURCE_IO) root = &ioport_resource; @@ -53,11 +56,32 @@ default_resources: pci_add_resource(resources, &iomem_resource); } +struct pci_root_info __init *alloc_pci_root_info(int bus_min, int bus_max, + int node, int link) +{ + struct pci_root_info *info; + + info = kzalloc(sizeof(*info), GFP_KERNEL); + + if (!info) + return info; + + INIT_LIST_HEAD(&info->resources); + info->bus_min = bus_min; + info->bus_max = bus_max; + info->node = node; + info->link = link; + + list_add_tail(&info->list, &pci_root_infos); + + return info; +} + void __devinit update_res(struct pci_root_info *info, resource_size_t start, resource_size_t end, unsigned long flags, int merge) { - int i; struct resource *res; + struct pci_root_res *root_res; if (start > end) return; @@ -69,11 +93,11 @@ void __devinit update_res(struct pci_root_info *info, resource_size_t start, goto addit; /* try to merge it with old one */ - for (i = 0; i < info->res_num; i++) { + list_for_each_entry(root_res, &info->resources, list) { resource_size_t final_start, final_end; resource_size_t common_start, common_end; - res = &info->res[i]; + res = &root_res->res; if (res->flags != flags) continue; @@ -93,14 +117,15 @@ void __devinit update_res(struct pci_root_info *info, resource_size_t start, addit: /* need to add that */ - if (info->res_num >= RES_NUM) + root_res = kzalloc(sizeof(*root_res), GFP_KERNEL); + if (!root_res) return; - res = &info->res[info->res_num]; + res = &root_res->res; res->name = info->name; res->flags = flags; res->start = start; res->end = end; - res->child = NULL; - info->res_num++; + + list_add_tail(&root_res->list, &info->resources); } diff --git a/arch/x86/pci/bus_numa.h b/arch/x86/pci/bus_numa.h index 804a4b40c31a..226a466b2b2b 100644 --- a/arch/x86/pci/bus_numa.h +++ b/arch/x86/pci/bus_numa.h @@ -4,22 +4,24 @@ * sub bus (transparent) will use entres from 3 to store extra from * root, so need to make sure we have enough slot there. */ -#define RES_NUM 16 +struct pci_root_res { + struct list_head list; + struct resource res; +}; + struct pci_root_info { + struct list_head list; char name[12]; - unsigned int res_num; - struct resource res[RES_NUM]; + struct list_head resources; int bus_min; int bus_max; int node; int link; }; -/* 4 at this time, it may become to 32 */ -#define PCI_ROOT_NR 4 -extern int pci_root_num; -extern struct pci_root_info pci_root_info[PCI_ROOT_NR]; - +extern struct list_head pci_root_infos; +struct pci_root_info *alloc_pci_root_info(int bus_min, int bus_max, + int node, int link); extern void update_res(struct pci_root_info *info, resource_size_t start, resource_size_t end, unsigned long flags, int merge); #endif diff --git a/arch/x86/pci/common.c b/arch/x86/pci/common.c index 323481e06ef8..0ad990a20d4a 100644 --- a/arch/x86/pci/common.c +++ b/arch/x86/pci/common.c @@ -11,6 +11,7 @@ #include <linux/dmi.h> #include <linux/slab.h> +#include <asm-generic/pci-bridge.h> #include <asm/acpi.h> #include <asm/segment.h> #include <asm/io.h> @@ -229,6 +230,14 @@ static int __devinit assign_all_busses(const struct dmi_system_id *d) } #endif +static int __devinit set_scan_all(const struct dmi_system_id *d) +{ + printk(KERN_INFO "PCI: %s detected, enabling pci=pcie_scan_all\n", + d->ident); + pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS); + return 0; +} + static const struct dmi_system_id __devinitconst pciprobe_dmi_table[] = { #ifdef __i386__ /* @@ -420,6 +429,13 @@ static const struct dmi_system_id __devinitconst pciprobe_dmi_table[] = { DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL585 G2"), }, }, + { + .callback = set_scan_all, + .ident = "Stratus/NEC ftServer", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "ftServer"), + }, + }, {} }; @@ -430,9 +446,7 @@ void __init dmi_check_pciprobe(void) struct pci_bus * __devinit pcibios_scan_root(int busnum) { - LIST_HEAD(resources); struct pci_bus *bus = NULL; - struct pci_sysdata *sd; while ((bus = pci_find_next_bus(bus)) != NULL) { if (bus->number == busnum) { @@ -441,28 +455,10 @@ struct pci_bus * __devinit pcibios_scan_root(int busnum) } } - /* Allocate per-root-bus (not per bus) arch-specific data. - * TODO: leak; this memory is never freed. - * It's arguable whether it's worth the trouble to care. - */ - sd = kzalloc(sizeof(*sd), GFP_KERNEL); - if (!sd) { - printk(KERN_ERR "PCI: OOM, not probing PCI bus %02x\n", busnum); - return NULL; - } - - sd->node = get_mp_bus_to_node(busnum); - - printk(KERN_DEBUG "PCI: Probing PCI hardware (bus %02x)\n", busnum); - x86_pci_root_bus_resources(busnum, &resources); - bus = pci_scan_root_bus(NULL, busnum, &pci_root_ops, sd, &resources); - if (!bus) { - pci_free_resource_list(&resources); - kfree(sd); - } - - return bus; + return pci_scan_bus_on_node(busnum, &pci_root_ops, + get_mp_bus_to_node(busnum)); } + void __init pcibios_set_cache_line_size(void) { struct cpuinfo_x86 *c = &boot_cpu_data; @@ -656,6 +652,7 @@ struct pci_bus * __devinit pci_scan_bus_on_node(int busno, struct pci_ops *ops, } sd->node = node; x86_pci_root_bus_resources(busno, &resources); + printk(KERN_DEBUG "PCI: Probing PCI hardware (bus %02x)\n", busno); bus = pci_scan_root_bus(NULL, busno, ops, sd, &resources); if (!bus) { pci_free_resource_list(&resources); diff --git a/arch/x86/pci/i386.c b/arch/x86/pci/i386.c index 831971e731f7..dd8ca6f7223b 100644 --- a/arch/x86/pci/i386.c +++ b/arch/x86/pci/i386.c @@ -57,7 +57,7 @@ static struct pcibios_fwaddrmap *pcibios_fwaddrmap_lookup(struct pci_dev *dev) { struct pcibios_fwaddrmap *map; - WARN_ON(!spin_is_locked(&pcibios_fwaddrmap_lock)); + WARN_ON_SMP(!spin_is_locked(&pcibios_fwaddrmap_lock)); list_for_each_entry(map, &pcibios_fwaddrmappings, list) if (map->dev == dev) diff --git a/arch/x86/platform/geode/net5501.c b/arch/x86/platform/geode/net5501.c index 66d377e334f7..646e3b5b4bb6 100644 --- a/arch/x86/platform/geode/net5501.c +++ b/arch/x86/platform/geode/net5501.c @@ -63,7 +63,7 @@ static struct gpio_led net5501_leds[] = { .name = "net5501:1", .gpio = 6, .default_trigger = "default-on", - .active_low = 1, + .active_low = 0, }, }; diff --git a/arch/x86/platform/mrst/mrst.c b/arch/x86/platform/mrst/mrst.c index e0a37233c0af..e31bcd8f2eee 100644 --- a/arch/x86/platform/mrst/mrst.c +++ b/arch/x86/platform/mrst/mrst.c @@ -805,7 +805,7 @@ void intel_scu_devices_create(void) } else i2c_register_board_info(i2c_bus[i], i2c_devs[i], 1); } - intel_scu_notifier_post(SCU_AVAILABLE, 0L); + intel_scu_notifier_post(SCU_AVAILABLE, NULL); } EXPORT_SYMBOL_GPL(intel_scu_devices_create); @@ -814,7 +814,7 @@ void intel_scu_devices_destroy(void) { int i; - intel_scu_notifier_post(SCU_DOWN, 0L); + intel_scu_notifier_post(SCU_DOWN, NULL); for (i = 0; i < ipc_next_dev; i++) platform_device_del(ipc_devs[i]); diff --git a/arch/x86/tools/.gitignore b/arch/x86/tools/.gitignore new file mode 100644 index 000000000000..be0ed065249b --- /dev/null +++ b/arch/x86/tools/.gitignore @@ -0,0 +1 @@ +relocs diff --git a/arch/x86/tools/Makefile b/arch/x86/tools/Makefile index d511aa97533a..733057b435b0 100644 --- a/arch/x86/tools/Makefile +++ b/arch/x86/tools/Makefile @@ -36,3 +36,7 @@ HOSTCFLAGS_insn_sanity.o := -Wall -I$(objtree)/arch/x86/lib/ -I$(srctree)/arch/x $(obj)/test_get_len.o: $(srctree)/arch/x86/lib/insn.c $(srctree)/arch/x86/lib/inat.c $(srctree)/arch/x86/include/asm/inat_types.h $(srctree)/arch/x86/include/asm/inat.h $(srctree)/arch/x86/include/asm/insn.h $(objtree)/arch/x86/lib/inat-tables.c $(obj)/insn_sanity.o: $(srctree)/arch/x86/lib/insn.c $(srctree)/arch/x86/lib/inat.c $(srctree)/arch/x86/include/asm/inat_types.h $(srctree)/arch/x86/include/asm/inat.h $(srctree)/arch/x86/include/asm/insn.h $(objtree)/arch/x86/lib/inat-tables.c + +HOST_EXTRACFLAGS += -I$(srctree)/tools/include +hostprogs-y += relocs +relocs: $(obj)/relocs diff --git a/arch/x86/boot/compressed/relocs.c b/arch/x86/tools/relocs.c index d3c0b0277666..b43cfcd9bf40 100644 --- a/arch/x86/boot/compressed/relocs.c +++ b/arch/x86/tools/relocs.c @@ -18,6 +18,8 @@ static void die(char *fmt, ...); static Elf32_Ehdr ehdr; static unsigned long reloc_count, reloc_idx; static unsigned long *relocs; +static unsigned long reloc16_count, reloc16_idx; +static unsigned long *relocs16; struct section { Elf32_Shdr shdr; @@ -28,52 +30,86 @@ struct section { }; static struct section *secs; +enum symtype { + S_ABS, + S_REL, + S_SEG, + S_LIN, + S_NSYMTYPES +}; + +static const char * const sym_regex_kernel[S_NSYMTYPES] = { /* * Following symbols have been audited. There values are constant and do * not change if bzImage is loaded at a different physical address than * the address for which it has been compiled. Don't warn user about * absolute relocations present w.r.t these symbols. */ -static const char abs_sym_regex[] = + [S_ABS] = "^(xen_irq_disable_direct_reloc$|" "xen_save_fl_direct_reloc$|" "VDSO|" - "__crc_)"; -static regex_t abs_sym_regex_c; -static int is_abs_reloc(const char *sym_name) -{ - return !regexec(&abs_sym_regex_c, sym_name, 0, NULL, 0); -} + "__crc_)", /* * These symbols are known to be relative, even if the linker marks them * as absolute (typically defined outside any section in the linker script.) */ -static const char rel_sym_regex[] = - "^_end$"; -static regex_t rel_sym_regex_c; -static int is_rel_reloc(const char *sym_name) + [S_REL] = + "^(__init_(begin|end)|" + "__x86_cpu_dev_(start|end)|" + "(__parainstructions|__alt_instructions)(|_end)|" + "(__iommu_table|__apicdrivers|__smp_locks)(|_end)|" + "_end)$" +}; + + +static const char * const sym_regex_realmode[S_NSYMTYPES] = { +/* + * These are 16-bit segment symbols when compiling 16-bit code. + */ + [S_SEG] = + "^real_mode_seg$", + +/* + * These are offsets belonging to segments, as opposed to linear addresses, + * when compiling 16-bit code. + */ + [S_LIN] = + "^pa_", +}; + +static const char * const *sym_regex; + +static regex_t sym_regex_c[S_NSYMTYPES]; +static int is_reloc(enum symtype type, const char *sym_name) { - return !regexec(&rel_sym_regex_c, sym_name, 0, NULL, 0); + return sym_regex[type] && + !regexec(&sym_regex_c[type], sym_name, 0, NULL, 0); } -static void regex_init(void) +static void regex_init(int use_real_mode) { char errbuf[128]; int err; - - err = regcomp(&abs_sym_regex_c, abs_sym_regex, - REG_EXTENDED|REG_NOSUB); - if (err) { - regerror(err, &abs_sym_regex_c, errbuf, sizeof errbuf); - die("%s", errbuf); - } + int i; + + if (use_real_mode) + sym_regex = sym_regex_realmode; + else + sym_regex = sym_regex_kernel; - err = regcomp(&rel_sym_regex_c, rel_sym_regex, - REG_EXTENDED|REG_NOSUB); - if (err) { - regerror(err, &rel_sym_regex_c, errbuf, sizeof errbuf); - die("%s", errbuf); + for (i = 0; i < S_NSYMTYPES; i++) { + if (!sym_regex[i]) + continue; + + err = regcomp(&sym_regex_c[i], sym_regex[i], + REG_EXTENDED|REG_NOSUB); + + if (err) { + regerror(err, &sym_regex_c[i], errbuf, sizeof errbuf); + die("%s", errbuf); + } } } @@ -154,6 +190,10 @@ static const char *rel_type(unsigned type) REL_TYPE(R_386_RELATIVE), REL_TYPE(R_386_GOTOFF), REL_TYPE(R_386_GOTPC), + REL_TYPE(R_386_8), + REL_TYPE(R_386_PC8), + REL_TYPE(R_386_16), + REL_TYPE(R_386_PC16), #undef REL_TYPE }; const char *name = "unknown type rel type name"; @@ -189,7 +229,7 @@ static const char *sym_name(const char *sym_strtab, Elf32_Sym *sym) name = sym_strtab + sym->st_name; } else { - name = sec_name(secs[sym->st_shndx].shdr.sh_name); + name = sec_name(sym->st_shndx); } return name; } @@ -403,13 +443,11 @@ static void print_absolute_symbols(void) for (i = 0; i < ehdr.e_shnum; i++) { struct section *sec = &secs[i]; char *sym_strtab; - Elf32_Sym *sh_symtab; int j; if (sec->shdr.sh_type != SHT_SYMTAB) { continue; } - sh_symtab = sec->symtab; sym_strtab = sec->link->strtab; for (j = 0; j < sec->shdr.sh_size/sizeof(Elf32_Sym); j++) { Elf32_Sym *sym; @@ -474,7 +512,7 @@ static void print_absolute_relocs(void) * Before warning check if this absolute symbol * relocation is harmless. */ - if (is_abs_reloc(name) || is_rel_reloc(name)) + if (is_reloc(S_ABS, name) || is_reloc(S_REL, name)) continue; if (!printed) { @@ -498,7 +536,8 @@ static void print_absolute_relocs(void) printf("\n"); } -static void walk_relocs(void (*visit)(Elf32_Rel *rel, Elf32_Sym *sym)) +static void walk_relocs(void (*visit)(Elf32_Rel *rel, Elf32_Sym *sym), + int use_real_mode) { int i; /* Walk through the relocations */ @@ -523,30 +562,67 @@ static void walk_relocs(void (*visit)(Elf32_Rel *rel, Elf32_Sym *sym)) Elf32_Rel *rel; Elf32_Sym *sym; unsigned r_type; + const char *symname; + int shn_abs; + rel = &sec->reltab[j]; sym = &sh_symtab[ELF32_R_SYM(rel->r_info)]; r_type = ELF32_R_TYPE(rel->r_info); - /* Don't visit relocations to absolute symbols */ - if (sym->st_shndx == SHN_ABS && - !is_rel_reloc(sym_name(sym_strtab, sym))) { - continue; - } + + shn_abs = sym->st_shndx == SHN_ABS; + switch (r_type) { case R_386_NONE: case R_386_PC32: + case R_386_PC16: + case R_386_PC8: /* * NONE can be ignored and and PC relative * relocations don't need to be adjusted. */ break; + + case R_386_16: + symname = sym_name(sym_strtab, sym); + if (!use_real_mode) + goto bad; + if (shn_abs) { + if (is_reloc(S_ABS, symname)) + break; + else if (!is_reloc(S_SEG, symname)) + goto bad; + } else { + if (is_reloc(S_LIN, symname)) + goto bad; + else + break; + } + visit(rel, sym); + break; + case R_386_32: - /* Visit relocations that need to be adjusted */ + symname = sym_name(sym_strtab, sym); + if (shn_abs) { + if (is_reloc(S_ABS, symname)) + break; + else if (!is_reloc(S_REL, symname)) + goto bad; + } else { + if (use_real_mode && + !is_reloc(S_LIN, symname)) + break; + } visit(rel, sym); break; default: die("Unsupported relocation type: %s (%d)\n", rel_type(r_type), r_type); break; + bad: + symname = sym_name(sym_strtab, sym); + die("Invalid %s %s relocation: %s\n", + shn_abs ? "absolute" : "relative", + rel_type(r_type), symname); } } } @@ -554,13 +630,19 @@ static void walk_relocs(void (*visit)(Elf32_Rel *rel, Elf32_Sym *sym)) static void count_reloc(Elf32_Rel *rel, Elf32_Sym *sym) { - reloc_count += 1; + if (ELF32_R_TYPE(rel->r_info) == R_386_16) + reloc16_count++; + else + reloc_count++; } static void collect_reloc(Elf32_Rel *rel, Elf32_Sym *sym) { /* Remember the address that needs to be adjusted. */ - relocs[reloc_idx++] = rel->r_offset; + if (ELF32_R_TYPE(rel->r_info) == R_386_16) + relocs16[reloc16_idx++] = rel->r_offset; + else + relocs[reloc_idx++] = rel->r_offset; } static int cmp_relocs(const void *va, const void *vb) @@ -570,23 +652,41 @@ static int cmp_relocs(const void *va, const void *vb) return (*a == *b)? 0 : (*a > *b)? 1 : -1; } -static void emit_relocs(int as_text) +static int write32(unsigned int v, FILE *f) +{ + unsigned char buf[4]; + + put_unaligned_le32(v, buf); + return fwrite(buf, 1, 4, f) == 4 ? 0 : -1; +} + +static void emit_relocs(int as_text, int use_real_mode) { int i; /* Count how many relocations I have and allocate space for them. */ reloc_count = 0; - walk_relocs(count_reloc); + walk_relocs(count_reloc, use_real_mode); relocs = malloc(reloc_count * sizeof(relocs[0])); if (!relocs) { die("malloc of %d entries for relocs failed\n", reloc_count); } + + relocs16 = malloc(reloc16_count * sizeof(relocs[0])); + if (!relocs16) { + die("malloc of %d entries for relocs16 failed\n", + reloc16_count); + } /* Collect up the relocations */ reloc_idx = 0; - walk_relocs(collect_reloc); + walk_relocs(collect_reloc, use_real_mode); + + if (reloc16_count && !use_real_mode) + die("Segment relocations found but --realmode not specified\n"); /* Order the relocations for more efficient processing */ qsort(relocs, reloc_count, sizeof(relocs[0]), cmp_relocs); + qsort(relocs16, reloc16_count, sizeof(relocs16[0]), cmp_relocs); /* Print the relocations */ if (as_text) { @@ -595,58 +695,83 @@ static void emit_relocs(int as_text) */ printf(".section \".data.reloc\",\"a\"\n"); printf(".balign 4\n"); - for (i = 0; i < reloc_count; i++) { - printf("\t .long 0x%08lx\n", relocs[i]); + if (use_real_mode) { + printf("\t.long %lu\n", reloc16_count); + for (i = 0; i < reloc16_count; i++) + printf("\t.long 0x%08lx\n", relocs16[i]); + printf("\t.long %lu\n", reloc_count); + for (i = 0; i < reloc_count; i++) { + printf("\t.long 0x%08lx\n", relocs[i]); + } + } else { + /* Print a stop */ + printf("\t.long 0x%08lx\n", (unsigned long)0); + for (i = 0; i < reloc_count; i++) { + printf("\t.long 0x%08lx\n", relocs[i]); + } } + printf("\n"); } else { - unsigned char buf[4]; - /* Print a stop */ - fwrite("\0\0\0\0", 4, 1, stdout); - /* Now print each relocation */ - for (i = 0; i < reloc_count; i++) { - put_unaligned_le32(relocs[i], buf); - fwrite(buf, 4, 1, stdout); + if (use_real_mode) { + write32(reloc16_count, stdout); + for (i = 0; i < reloc16_count; i++) + write32(relocs16[i], stdout); + write32(reloc_count, stdout); + + /* Now print each relocation */ + for (i = 0; i < reloc_count; i++) + write32(relocs[i], stdout); + } else { + /* Print a stop */ + write32(0, stdout); + + /* Now print each relocation */ + for (i = 0; i < reloc_count; i++) { + write32(relocs[i], stdout); + } } } } static void usage(void) { - die("relocs [--abs-syms |--abs-relocs | --text] vmlinux\n"); + die("relocs [--abs-syms|--abs-relocs|--text|--realmode] vmlinux\n"); } int main(int argc, char **argv) { int show_absolute_syms, show_absolute_relocs; - int as_text; + int as_text, use_real_mode; const char *fname; FILE *fp; int i; - regex_init(); - show_absolute_syms = 0; show_absolute_relocs = 0; as_text = 0; + use_real_mode = 0; fname = NULL; for (i = 1; i < argc; i++) { char *arg = argv[i]; if (*arg == '-') { - if (strcmp(argv[1], "--abs-syms") == 0) { + if (strcmp(arg, "--abs-syms") == 0) { show_absolute_syms = 1; continue; } - - if (strcmp(argv[1], "--abs-relocs") == 0) { + if (strcmp(arg, "--abs-relocs") == 0) { show_absolute_relocs = 1; continue; } - else if (strcmp(argv[1], "--text") == 0) { + if (strcmp(arg, "--text") == 0) { as_text = 1; continue; } + if (strcmp(arg, "--realmode") == 0) { + use_real_mode = 1; + continue; + } } else if (!fname) { fname = arg; @@ -657,6 +782,7 @@ int main(int argc, char **argv) if (!fname) { usage(); } + regex_init(use_real_mode); fp = fopen(fname, "r"); if (!fp) { die("Cannot open %s: %s\n", @@ -675,6 +801,6 @@ int main(int argc, char **argv) print_absolute_relocs(); return 0; } - emit_relocs(as_text); + emit_relocs(as_text, use_real_mode); return 0; } diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c index 4f51bebac02c..95dccce8e979 100644 --- a/arch/x86/xen/enlighten.c +++ b/arch/x86/xen/enlighten.c @@ -63,6 +63,7 @@ #include <asm/stackprotector.h> #include <asm/hypervisor.h> #include <asm/mwait.h> +#include <asm/pci_x86.h> #ifdef CONFIG_ACPI #include <linux/acpi.h> @@ -261,7 +262,8 @@ static void xen_cpuid(unsigned int *ax, unsigned int *bx, static bool __init xen_check_mwait(void) { -#ifdef CONFIG_ACPI +#if defined(CONFIG_ACPI) && !defined(CONFIG_ACPI_PROCESSOR_AGGREGATOR) && \ + !defined(CONFIG_ACPI_PROCESSOR_AGGREGATOR_MODULE) struct xen_platform_op op = { .cmd = XENPF_set_processor_pminfo, .u.set_pminfo.id = -1, @@ -349,7 +351,6 @@ static void __init xen_init_cpuid_mask(void) /* Xen will set CR4.OSXSAVE if supported and not disabled by force */ if ((cx & xsave_mask) != xsave_mask) cpuid_leaf1_ecx_mask &= ~xsave_mask; /* disable XSAVE & OSXSAVE */ - if (xen_check_mwait()) cpuid_leaf1_ecx_set_mask = (1 << (X86_FEATURE_MWAIT % 32)); } @@ -809,9 +810,40 @@ static void xen_io_delay(void) } #ifdef CONFIG_X86_LOCAL_APIC +static unsigned long xen_set_apic_id(unsigned int x) +{ + WARN_ON(1); + return x; +} +static unsigned int xen_get_apic_id(unsigned long x) +{ + return ((x)>>24) & 0xFFu; +} static u32 xen_apic_read(u32 reg) { - return 0; + struct xen_platform_op op = { + .cmd = XENPF_get_cpuinfo, + .interface_version = XENPF_INTERFACE_VERSION, + .u.pcpu_info.xen_cpuid = 0, + }; + int ret = 0; + + /* Shouldn't need this as APIC is turned off for PV, and we only + * get called on the bootup processor. But just in case. */ + if (!xen_initial_domain() || smp_processor_id()) + return 0; + + if (reg == APIC_LVR) + return 0x10; + + if (reg != APIC_ID) + return 0; + + ret = HYPERVISOR_dom0_op(&op); + if (ret) + return 0; + + return op.u.pcpu_info.apic_id << 24; } static void xen_apic_write(u32 reg, u32 val) @@ -849,6 +881,8 @@ static void set_xen_basic_apic_ops(void) apic->icr_write = xen_apic_icr_write; apic->wait_icr_idle = xen_apic_wait_icr_idle; apic->safe_wait_icr_idle = xen_safe_apic_wait_icr_idle; + apic->set_apic_id = xen_set_apic_id; + apic->get_apic_id = xen_get_apic_id; } #endif @@ -1365,8 +1399,10 @@ asmlinkage void __init xen_start_kernel(void) /* Make sure ACS will be enabled */ pci_request_acs(); } - - +#ifdef CONFIG_PCI + /* PCI BIOS service won't work from a PV guest. */ + pci_probe &= ~PCI_PROBE_BIOS; +#endif xen_raw_console_write("about to get started...\n"); xen_setup_runstate_info(0); diff --git a/arch/x86/xen/mmu.c b/arch/x86/xen/mmu.c index b8e279479a6b..69f5857660ac 100644 --- a/arch/x86/xen/mmu.c +++ b/arch/x86/xen/mmu.c @@ -353,8 +353,13 @@ static pteval_t pte_mfn_to_pfn(pteval_t val) { if (val & _PAGE_PRESENT) { unsigned long mfn = (val & PTE_PFN_MASK) >> PAGE_SHIFT; + unsigned long pfn = mfn_to_pfn(mfn); + pteval_t flags = val & PTE_FLAGS_MASK; - val = ((pteval_t)mfn_to_pfn(mfn) << PAGE_SHIFT) | flags; + if (unlikely(pfn == ~0)) + val = flags & ~_PAGE_PRESENT; + else + val = ((pteval_t)pfn << PAGE_SHIFT) | flags; } return val; diff --git a/arch/x86/xen/smp.c b/arch/x86/xen/smp.c index 5fac6919b957..0503c0c493a9 100644 --- a/arch/x86/xen/smp.c +++ b/arch/x86/xen/smp.c @@ -178,6 +178,7 @@ static void __init xen_fill_possible_map(void) static void __init xen_filter_cpu_maps(void) { int i, rc; + unsigned int subtract = 0; if (!xen_initial_domain()) return; @@ -192,8 +193,22 @@ static void __init xen_filter_cpu_maps(void) } else { set_cpu_possible(i, false); set_cpu_present(i, false); + subtract++; } } +#ifdef CONFIG_HOTPLUG_CPU + /* This is akin to using 'nr_cpus' on the Linux command line. + * Which is OK as when we use 'dom0_max_vcpus=X' we can only + * have up to X, while nr_cpu_ids is greater than X. This + * normally is not a problem, except when CPU hotplugging + * is involved and then there might be more than X CPUs + * in the guest - which will not work as there is no + * hypercall to expand the max number of VCPUs an already + * running guest has. So cap it up to X. */ + if (subtract) + nr_cpu_ids = nr_cpu_ids - subtract; +#endif + } static void __init xen_smp_prepare_boot_cpu(void) diff --git a/arch/x86/xen/xen-asm.S b/arch/x86/xen/xen-asm.S index 79d7362ad6d1..3e45aa000718 100644 --- a/arch/x86/xen/xen-asm.S +++ b/arch/x86/xen/xen-asm.S @@ -96,7 +96,7 @@ ENTRY(xen_restore_fl_direct) /* check for unmasked and pending */ cmpw $0x0001, PER_CPU_VAR(xen_vcpu_info) + XEN_vcpu_info_pending - jz 1f + jnz 1f 2: call check_events 1: ENDPATCH(xen_restore_fl_direct) diff --git a/arch/xtensa/configs/common_defconfig b/arch/xtensa/configs/common_defconfig index b90038e40dd3..a182a4e6d688 100644 --- a/arch/xtensa/configs/common_defconfig +++ b/arch/xtensa/configs/common_defconfig @@ -333,11 +333,6 @@ CONFIG_XT2000_SONIC=y # CONFIG_S2IO is not set # -# Token Ring devices -# -# CONFIG_TR is not set - -# # Wireless LAN (non-hamradio) # CONFIG_NET_RADIO=y diff --git a/arch/xtensa/include/asm/hardirq.h b/arch/xtensa/include/asm/hardirq.h index 26664cef8f11..91695a135498 100644 --- a/arch/xtensa/include/asm/hardirq.h +++ b/arch/xtensa/include/asm/hardirq.h @@ -11,9 +11,6 @@ #ifndef _XTENSA_HARDIRQ_H #define _XTENSA_HARDIRQ_H -void ack_bad_irq(unsigned int irq); -#define ack_bad_irq ack_bad_irq - #include <asm-generic/hardirq.h> #endif /* _XTENSA_HARDIRQ_H */ diff --git a/arch/xtensa/include/asm/io.h b/arch/xtensa/include/asm/io.h index d04cd3a625fa..4beb43c087d3 100644 --- a/arch/xtensa/include/asm/io.h +++ b/arch/xtensa/include/asm/io.h @@ -14,6 +14,7 @@ #ifdef __KERNEL__ #include <asm/byteorder.h> #include <asm/page.h> +#include <linux/bug.h> #include <linux/kernel.h> #include <linux/types.h> diff --git a/arch/xtensa/kernel/signal.c b/arch/xtensa/kernel/signal.c index b69b000349fc..d78869a00b11 100644 --- a/arch/xtensa/kernel/signal.c +++ b/arch/xtensa/kernel/signal.c @@ -496,6 +496,7 @@ int do_signal(struct pt_regs *regs, sigset_t *oldset) signr = get_signal_to_deliver(&info, &ka, regs, NULL); if (signr > 0) { + int ret; /* Are we from a system call? */ |