diff options
Diffstat (limited to 'arch/sparc')
| -rw-r--r-- | arch/sparc/Kconfig | 3 | ||||
| -rw-r--r-- | arch/sparc/kernel/smp.c | 10 | ||||
| -rw-r--r-- | arch/sparc/lib/atomic32.c | 4 |
3 files changed, 5 insertions, 12 deletions
diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig index fbcc00c6c06e..8567cc901942 100644 --- a/arch/sparc/Kconfig +++ b/arch/sparc/Kconfig @@ -210,6 +210,9 @@ config PCI CP-1200, JavaEngine-1, Corona, Red October, and Serengeti SGSC. All of these platforms are extremely obscure, so say N if unsure. +config PCI_SYSCALL + def_bool PCI + source "drivers/pci/Kconfig" endif diff --git a/arch/sparc/kernel/smp.c b/arch/sparc/kernel/smp.c index 4d9ad59031bb..4fea3ac7bff0 100644 --- a/arch/sparc/kernel/smp.c +++ b/arch/sparc/kernel/smp.c @@ -68,16 +68,6 @@ void __cpuinit smp_store_cpu_info(int id) cpu_data(id).prom_node = cpu_node; cpu_data(id).mid = cpu_get_hwmid(cpu_node); - /* this is required to tune the scheduler correctly */ - /* is it possible to have CPUs with different cache sizes? */ - if (id == boot_cpu_id) { - int cache_line,cache_nlines; - cache_line = 0x20; - cache_line = prom_getintdefault(cpu_node, "ecache-line-size", cache_line); - cache_nlines = 0x8000; - cache_nlines = prom_getintdefault(cpu_node, "ecache-nlines", cache_nlines); - max_cache_size = cache_line * cache_nlines; - } if (cpu_data(id).mid < 0) panic("No MID found for CPU%d at node 0x%08d", id, cpu_node); } diff --git a/arch/sparc/lib/atomic32.c b/arch/sparc/lib/atomic32.c index 617d29832e19..cbddeb38ffda 100644 --- a/arch/sparc/lib/atomic32.c +++ b/arch/sparc/lib/atomic32.c @@ -124,10 +124,10 @@ unsigned long __cmpxchg_u32(volatile u32 *ptr, u32 old, u32 new) unsigned long flags; u32 prev; - spin_lock_irqsave(ATOMIC_HASH(addr), flags); + spin_lock_irqsave(ATOMIC_HASH(ptr), flags); if ((prev = *ptr) == old) *ptr = new; - spin_unlock_irqrestore(ATOMIC_HASH(addr), flags); + spin_unlock_irqrestore(ATOMIC_HASH(ptr), flags); return (unsigned long)prev; } |