diff options
Diffstat (limited to 'arch/mips/pci')
| -rw-r--r-- | arch/mips/pci/pci-mt7620.c | 15 | ||||
| -rw-r--r-- | arch/mips/pci/pcie-octeon.c | 12 |
2 files changed, 13 insertions, 14 deletions
diff --git a/arch/mips/pci/pci-mt7620.c b/arch/mips/pci/pci-mt7620.c index 90fba9bf98da..407f155f0bb6 100644 --- a/arch/mips/pci/pci-mt7620.c +++ b/arch/mips/pci/pci-mt7620.c @@ -33,14 +33,13 @@ #define RALINK_GPIOMODE 0x60 #define PPLL_CFG1 0x9c -#define PDRV_SW_SET BIT(23) #define PPLL_DRV 0xa0 -#define PDRV_SW_SET (1<<31) -#define LC_CKDRVPD (1<<19) -#define LC_CKDRVOHZ (1<<18) -#define LC_CKDRVHZ (1<<17) -#define LC_CKTEST (1<<16) +#define PDRV_SW_SET BIT(31) +#define LC_CKDRVPD BIT(19) +#define LC_CKDRVOHZ BIT(18) +#define LC_CKDRVHZ BIT(17) +#define LC_CKTEST BIT(16) /* PCI Bridge registers */ #define RALINK_PCI_PCICFG_ADDR 0x00 @@ -66,7 +65,7 @@ #define PCIEPHY0_CFG 0x90 #define RALINK_PCIEPHY_P0_CTL_OFFSET 0x7498 -#define RALINK_PCIE0_CLK_EN (1 << 26) +#define RALINK_PCIE0_CLK_EN BIT(26) #define BUSY 0x80000000 #define WAITRETRY_MAX 10 @@ -121,7 +120,7 @@ static int wait_pciephy_busy(void) else break; if (retry++ > WAITRETRY_MAX) { - printk(KERN_WARN "PCIE-PHY retry failed.\n"); + pr_warn("PCIE-PHY retry failed.\n"); return -1; } } diff --git a/arch/mips/pci/pcie-octeon.c b/arch/mips/pci/pcie-octeon.c index fd2887415bc8..87ba86bd8696 100644 --- a/arch/mips/pci/pcie-octeon.c +++ b/arch/mips/pci/pcie-octeon.c @@ -639,7 +639,7 @@ static int __cvmx_pcie_rc_initialize_link_gen1(int pcie_port) cvmx_dprintf("PCIe: Port %d link timeout\n", pcie_port); return -1; } - cvmx_wait(10000); + __delay(10000); pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port)); } while (pciercx_cfg032.s.dlla == 0); @@ -821,7 +821,7 @@ retry: * don't poll PESCX_CTL_STATUS2[PCIERST], but simply wait a * fixed number of cycles. */ - cvmx_wait(400000); + __delay(400000); /* * PESCX_BIST_STATUS2[PCLK_RUN] was missing on pass 1 of @@ -1018,7 +1018,7 @@ retry: i = in_p_offset; while (i--) { cvmx_write64_uint32(write_address, 0); - cvmx_wait(10000); + __delay(10000); } /* @@ -1034,7 +1034,7 @@ retry: dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA); old_in_fif_p_count = dbg_data.s.data & 0xff; cvmx_write64_uint32(write_address, 0); - cvmx_wait(10000); + __delay(10000); dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA); in_fif_p_count = dbg_data.s.data & 0xff; } while (in_fif_p_count != ((old_in_fif_p_count+1) & 0xff)); @@ -1053,7 +1053,7 @@ retry: cvmx_dprintf("PCIe: Port %d aligning TLP counters as workaround to maintain ordering\n", pcie_port); while (in_fif_p_count != 0) { cvmx_write64_uint32(write_address, 0); - cvmx_wait(10000); + __delay(10000); in_fif_p_count = (in_fif_p_count + 1) & 0xff; } /* @@ -1105,7 +1105,7 @@ static int __cvmx_pcie_rc_initialize_link_gen2(int pcie_port) do { if (cvmx_get_cycle() - start_cycle > octeon_get_clock_rate()) return -1; - cvmx_wait(10000); + __delay(10000); pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port)); } while ((pciercx_cfg032.s.dlla == 0) || (pciercx_cfg032.s.lt == 1)); |