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Diffstat (limited to 'arch/arm64/boot/dts/qcom/sc7280.dtsi')
-rw-r--r--arch/arm64/boot/dts/qcom/sc7280.dtsi432
1 files changed, 218 insertions, 214 deletions
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 4cdc88d33944..0adf13399e64 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -752,6 +752,17 @@
interrupt-controller;
#interrupt-cells = <2>;
};
+
+ wlan_smp2p_out: wlan-ap-to-wpss {
+ qcom,entry-name = "wlan";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ wlan_smp2p_in: wlan-wpss-to-ap {
+ qcom,entry-name = "wlan";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
};
pmu {
@@ -920,7 +931,7 @@
gpi_dma0: dma-controller@900000 {
#dma-cells = <3>;
- compatible = "qcom,sc7280-gpi-dma";
+ compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma";
reg = <0 0x00900000 0 0x60000>;
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
@@ -967,6 +978,8 @@
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7280_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
<&gpi_dma0 1 0 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
@@ -1025,6 +1038,8 @@
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7280_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
<&gpi_dma0 1 1 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
@@ -1083,6 +1098,8 @@
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7280_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
<&gpi_dma0 1 2 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
@@ -1141,6 +1158,8 @@
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7280_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
<&gpi_dma0 1 3 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
@@ -1199,6 +1218,8 @@
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7280_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
<&gpi_dma0 1 4 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
@@ -1257,6 +1278,8 @@
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7280_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
<&gpi_dma0 1 5 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
@@ -1315,6 +1338,8 @@
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7280_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
<&gpi_dma0 1 6 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
@@ -1373,6 +1398,8 @@
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7280_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
<&gpi_dma0 1 7 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
@@ -1419,7 +1446,7 @@
gpi_dma1: dma-controller@a00000 {
#dma-cells = <3>;
- compatible = "qcom,sc7280-gpi-dma";
+ compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma";
reg = <0 0x00a00000 0 0x60000>;
interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
@@ -1466,6 +1493,8 @@
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7280_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
<&gpi_dma1 1 0 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
@@ -1524,6 +1553,8 @@
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7280_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
<&gpi_dma1 1 1 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
@@ -1582,6 +1613,8 @@
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7280_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
<&gpi_dma1 1 2 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
@@ -1640,6 +1673,8 @@
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7280_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
<&gpi_dma1 1 3 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
@@ -1698,6 +1733,8 @@
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7280_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
<&gpi_dma1 1 4 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
@@ -1756,6 +1793,8 @@
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7280_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
<&gpi_dma1 1 5 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
@@ -1814,6 +1853,8 @@
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7280_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
<&gpi_dma1 1 6 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
@@ -1872,6 +1913,8 @@
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7280_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
<&gpi_dma1 1 7 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
@@ -2004,6 +2047,8 @@
qcom,rproc = <&remoteproc_wpss>;
memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>;
status = "disabled";
+ qcom,smem-states = <&wlan_smp2p_out 0>;
+ qcom,smem-state-names = "wlan-smp2p-out";
};
pcie1: pci@1c08000 {
@@ -2285,7 +2330,6 @@
qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>;
qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>;
qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>;
- qcom,port-offset = <1>;
#sound-dai-cells = <1>;
#address-cells = <2>;
@@ -2434,84 +2478,42 @@
#gpio-cells = <2>;
gpio-ranges = <&lpass_tlmm 0 0 15>;
- #clock-cells = <1>;
-
- lpass_dmic01_clk: dmic01-clk {
- pins = "gpio6";
- function = "dmic1_clk";
- };
-
- lpass_dmic01_clk_sleep: dmic01-clk-sleep {
+ lpass_dmic01_clk: dmic01-clk-state {
pins = "gpio6";
function = "dmic1_clk";
};
- lpass_dmic01_data: dmic01-data {
+ lpass_dmic01_data: dmic01-data-state {
pins = "gpio7";
function = "dmic1_data";
};
- lpass_dmic01_data_sleep: dmic01-data-sleep {
- pins = "gpio7";
- function = "dmic1_data";
- };
-
- lpass_dmic23_clk: dmic23-clk {
- pins = "gpio8";
- function = "dmic2_clk";
- };
-
- lpass_dmic23_clk_sleep: dmic23-clk-sleep {
+ lpass_dmic23_clk: dmic23-clk-state {
pins = "gpio8";
function = "dmic2_clk";
};
- lpass_dmic23_data: dmic23-data {
+ lpass_dmic23_data: dmic23-data-state {
pins = "gpio9";
function = "dmic2_data";
};
- lpass_dmic23_data_sleep: dmic23-data-sleep {
- pins = "gpio9";
- function = "dmic2_data";
- };
-
- lpass_rx_swr_clk: rx-swr-clk {
+ lpass_rx_swr_clk: rx-swr-clk-state {
pins = "gpio3";
function = "swr_rx_clk";
};
- lpass_rx_swr_clk_sleep: rx-swr-clk-sleep {
- pins = "gpio3";
- function = "swr_rx_clk";
- };
-
- lpass_rx_swr_data: rx-swr-data {
+ lpass_rx_swr_data: rx-swr-data-state {
pins = "gpio4", "gpio5";
function = "swr_rx_data";
};
- lpass_rx_swr_data_sleep: rx-swr-data-sleep {
- pins = "gpio4", "gpio5";
- function = "swr_rx_data";
- };
-
- lpass_tx_swr_clk: tx-swr-clk {
- pins = "gpio0";
- function = "swr_tx_clk";
- };
-
- lpass_tx_swr_clk_sleep: tx-swr-clk-sleep {
+ lpass_tx_swr_clk: tx-swr-clk-state {
pins = "gpio0";
function = "swr_tx_clk";
};
- lpass_tx_swr_data: tx-swr-data {
- pins = "gpio1", "gpio2", "gpio14";
- function = "swr_tx_data";
- };
-
- lpass_tx_swr_data_sleep: tx-swr-data-sleep {
+ lpass_tx_swr_data: tx-swr-data-state {
pins = "gpio1", "gpio2", "gpio14";
function = "swr_tx_data";
};
@@ -3924,11 +3926,13 @@
"iface",
"bus";
+ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>;
+
operating-points-v2 = <&dsi_opp_table>;
power-domains = <&rpmhpd SC7280_CX>;
phys = <&mdss_dsi_phy>;
- phy-names = "dsi";
#address-cells = <1>;
#size-cells = <0>;
@@ -4259,791 +4263,791 @@
gpio-ranges = <&tlmm 0 0 175>;
wakeup-parent = <&pdc>;
- dp_hot_plug_det: dp-hot-plug-det-pins {
+ dp_hot_plug_det: dp-hot-plug-det-state {
pins = "gpio47";
function = "dp_hot";
};
- edp_hot_plug_det: edp-hot-plug-det-pins {
+ edp_hot_plug_det: edp-hot-plug-det-state {
pins = "gpio60";
function = "edp_hot";
};
- mi2s0_data0: mi2s0-data0-pins {
+ mi2s0_data0: mi2s0-data0-state {
pins = "gpio98";
function = "mi2s0_data0";
};
- mi2s0_data1: mi2s0-data1-pins {
+ mi2s0_data1: mi2s0-data1-state {
pins = "gpio99";
function = "mi2s0_data1";
};
- mi2s0_mclk: mi2s0-mclk-pins {
+ mi2s0_mclk: mi2s0-mclk-state {
pins = "gpio96";
function = "pri_mi2s";
};
- mi2s0_sclk: mi2s0-sclk-pins {
+ mi2s0_sclk: mi2s0-sclk-state {
pins = "gpio97";
function = "mi2s0_sck";
};
- mi2s0_ws: mi2s0-ws-pins {
+ mi2s0_ws: mi2s0-ws-state {
pins = "gpio100";
function = "mi2s0_ws";
};
- mi2s1_data0: mi2s1-data0-pins {
+ mi2s1_data0: mi2s1-data0-state {
pins = "gpio107";
function = "mi2s1_data0";
};
- mi2s1_sclk: mi2s1-sclk-pins {
+ mi2s1_sclk: mi2s1-sclk-state {
pins = "gpio106";
function = "mi2s1_sck";
};
- mi2s1_ws: mi2s1-ws-pins {
+ mi2s1_ws: mi2s1-ws-state {
pins = "gpio108";
function = "mi2s1_ws";
};
- pcie1_clkreq_n: pcie1-clkreq-n-pins {
+ pcie1_clkreq_n: pcie1-clkreq-n-state {
pins = "gpio79";
function = "pcie1_clkreqn";
};
- qspi_clk: qspi-clk-pins {
+ qspi_clk: qspi-clk-state {
pins = "gpio14";
function = "qspi_clk";
};
- qspi_cs0: qspi-cs0-pins {
+ qspi_cs0: qspi-cs0-state {
pins = "gpio15";
function = "qspi_cs";
};
- qspi_cs1: qspi-cs1-pins {
+ qspi_cs1: qspi-cs1-state {
pins = "gpio19";
function = "qspi_cs";
};
- qspi_data01: qspi-data01-pins {
+ qspi_data01: qspi-data01-state {
pins = "gpio12", "gpio13";
function = "qspi_data";
};
- qspi_data12: qspi-data12-pins {
+ qspi_data12: qspi-data12-state {
pins = "gpio16", "gpio17";
function = "qspi_data";
};
- qup_i2c0_data_clk: qup-i2c0-data-clk-pins {
+ qup_i2c0_data_clk: qup-i2c0-data-clk-state {
pins = "gpio0", "gpio1";
function = "qup00";
};
- qup_i2c1_data_clk: qup-i2c1-data-clk-pins {
+ qup_i2c1_data_clk: qup-i2c1-data-clk-state {
pins = "gpio4", "gpio5";
function = "qup01";
};
- qup_i2c2_data_clk: qup-i2c2-data-clk-pins {
+ qup_i2c2_data_clk: qup-i2c2-data-clk-state {
pins = "gpio8", "gpio9";
function = "qup02";
};
- qup_i2c3_data_clk: qup-i2c3-data-clk-pins {
+ qup_i2c3_data_clk: qup-i2c3-data-clk-state {
pins = "gpio12", "gpio13";
function = "qup03";
};
- qup_i2c4_data_clk: qup-i2c4-data-clk-pins {
+ qup_i2c4_data_clk: qup-i2c4-data-clk-state {
pins = "gpio16", "gpio17";
function = "qup04";
};
- qup_i2c5_data_clk: qup-i2c5-data-clk-pins {
+ qup_i2c5_data_clk: qup-i2c5-data-clk-state {
pins = "gpio20", "gpio21";
function = "qup05";
};
- qup_i2c6_data_clk: qup-i2c6-data-clk-pins {
+ qup_i2c6_data_clk: qup-i2c6-data-clk-state {
pins = "gpio24", "gpio25";
function = "qup06";
};
- qup_i2c7_data_clk: qup-i2c7-data-clk-pins {
+ qup_i2c7_data_clk: qup-i2c7-data-clk-state {
pins = "gpio28", "gpio29";
function = "qup07";
};
- qup_i2c8_data_clk: qup-i2c8-data-clk-pins {
+ qup_i2c8_data_clk: qup-i2c8-data-clk-state {
pins = "gpio32", "gpio33";
function = "qup10";
};
- qup_i2c9_data_clk: qup-i2c9-data-clk-pins {
+ qup_i2c9_data_clk: qup-i2c9-data-clk-state {
pins = "gpio36", "gpio37";
function = "qup11";
};
- qup_i2c10_data_clk: qup-i2c10-data-clk-pins {
+ qup_i2c10_data_clk: qup-i2c10-data-clk-state {
pins = "gpio40", "gpio41";
function = "qup12";
};
- qup_i2c11_data_clk: qup-i2c11-data-clk-pins {
+ qup_i2c11_data_clk: qup-i2c11-data-clk-state {
pins = "gpio44", "gpio45";
function = "qup13";
};
- qup_i2c12_data_clk: qup-i2c12-data-clk-pins {
+ qup_i2c12_data_clk: qup-i2c12-data-clk-state {
pins = "gpio48", "gpio49";
function = "qup14";
};
- qup_i2c13_data_clk: qup-i2c13-data-clk-pins {
+ qup_i2c13_data_clk: qup-i2c13-data-clk-state {
pins = "gpio52", "gpio53";
function = "qup15";
};
- qup_i2c14_data_clk: qup-i2c14-data-clk-pins {
+ qup_i2c14_data_clk: qup-i2c14-data-clk-state {
pins = "gpio56", "gpio57";
function = "qup16";
};
- qup_i2c15_data_clk: qup-i2c15-data-clk-pins {
+ qup_i2c15_data_clk: qup-i2c15-data-clk-state {
pins = "gpio60", "gpio61";
function = "qup17";
};
- qup_spi0_data_clk: qup-spi0-data-clk-pins {
+ qup_spi0_data_clk: qup-spi0-data-clk-state {
pins = "gpio0", "gpio1", "gpio2";
function = "qup00";
};
- qup_spi0_cs: qup-spi0-cs-pins {
+ qup_spi0_cs: qup-spi0-cs-state {
pins = "gpio3";
function = "qup00";
};
- qup_spi0_cs_gpio: qup-spi0-cs-gpio-pins {
+ qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
pins = "gpio3";
function = "gpio";
};
- qup_spi1_data_clk: qup-spi1-data-clk-pins {
+ qup_spi1_data_clk: qup-spi1-data-clk-state {
pins = "gpio4", "gpio5", "gpio6";
function = "qup01";
};
- qup_spi1_cs: qup-spi1-cs-pins {
+ qup_spi1_cs: qup-spi1-cs-state {
pins = "gpio7";
function = "qup01";
};
- qup_spi1_cs_gpio: qup-spi1-cs-gpio-pins {
+ qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
pins = "gpio7";
function = "gpio";
};
- qup_spi2_data_clk: qup-spi2-data-clk-pins {
+ qup_spi2_data_clk: qup-spi2-data-clk-state {
pins = "gpio8", "gpio9", "gpio10";
function = "qup02";
};
- qup_spi2_cs: qup-spi2-cs-pins {
+ qup_spi2_cs: qup-spi2-cs-state {
pins = "gpio11";
function = "qup02";
};
- qup_spi2_cs_gpio: qup-spi2-cs-gpio-pins {
+ qup_spi2_cs_gpio: qup-spi2-cs-gpio-state {
pins = "gpio11";
function = "gpio";
};
- qup_spi3_data_clk: qup-spi3-data-clk-pins {
+ qup_spi3_data_clk: qup-spi3-data-clk-state {
pins = "gpio12", "gpio13", "gpio14";
function = "qup03";
};
- qup_spi3_cs: qup-spi3-cs-pins {
+ qup_spi3_cs: qup-spi3-cs-state {
pins = "gpio15";
function = "qup03";
};
- qup_spi3_cs_gpio: qup-spi3-cs-gpio-pins {
+ qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
pins = "gpio15";
function = "gpio";
};
- qup_spi4_data_clk: qup-spi4-data-clk-pins {
+ qup_spi4_data_clk: qup-spi4-data-clk-state {
pins = "gpio16", "gpio17", "gpio18";
function = "qup04";
};
- qup_spi4_cs: qup-spi4-cs-pins {
+ qup_spi4_cs: qup-spi4-cs-state {
pins = "gpio19";
function = "qup04";
};
- qup_spi4_cs_gpio: qup-spi4-cs-gpio-pins {
+ qup_spi4_cs_gpio: qup-spi4-cs-gpio-state {
pins = "gpio19";
function = "gpio";
};
- qup_spi5_data_clk: qup-spi5-data-clk-pins {
+ qup_spi5_data_clk: qup-spi5-data-clk-state {
pins = "gpio20", "gpio21", "gpio22";
function = "qup05";
};
- qup_spi5_cs: qup-spi5-cs-pins {
+ qup_spi5_cs: qup-spi5-cs-state {
pins = "gpio23";
function = "qup05";
};
- qup_spi5_cs_gpio: qup-spi5-cs-gpio-pins {
+ qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
pins = "gpio23";
function = "gpio";
};
- qup_spi6_data_clk: qup-spi6-data-clk-pins {
+ qup_spi6_data_clk: qup-spi6-data-clk-state {
pins = "gpio24", "gpio25", "gpio26";
function = "qup06";
};
- qup_spi6_cs: qup-spi6-cs-pins {
+ qup_spi6_cs: qup-spi6-cs-state {
pins = "gpio27";
function = "qup06";
};
- qup_spi6_cs_gpio: qup-spi6-cs-gpio-pins {
+ qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
pins = "gpio27";
function = "gpio";
};
- qup_spi7_data_clk: qup-spi7-data-clk-pins {
+ qup_spi7_data_clk: qup-spi7-data-clk-state {
pins = "gpio28", "gpio29", "gpio30";
function = "qup07";
};
- qup_spi7_cs: qup-spi7-cs-pins {
+ qup_spi7_cs: qup-spi7-cs-state {
pins = "gpio31";
function = "qup07";
};
- qup_spi7_cs_gpio: qup-spi7-cs-gpio-pins {
+ qup_spi7_cs_gpio: qup-spi7-cs-gpio-state {
pins = "gpio31";
function = "gpio";
};
- qup_spi8_data_clk: qup-spi8-data-clk-pins {
+ qup_spi8_data_clk: qup-spi8-data-clk-state {
pins = "gpio32", "gpio33", "gpio34";
function = "qup10";
};
- qup_spi8_cs: qup-spi8-cs-pins {
+ qup_spi8_cs: qup-spi8-cs-state {
pins = "gpio35";
function = "qup10";
};
- qup_spi8_cs_gpio: qup-spi8-cs-gpio-pins {
+ qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
pins = "gpio35";
function = "gpio";
};
- qup_spi9_data_clk: qup-spi9-data-clk-pins {
+ qup_spi9_data_clk: qup-spi9-data-clk-state {
pins = "gpio36", "gpio37", "gpio38";
function = "qup11";
};
- qup_spi9_cs: qup-spi9-cs-pins {
+ qup_spi9_cs: qup-spi9-cs-state {
pins = "gpio39";
function = "qup11";
};
- qup_spi9_cs_gpio: qup-spi9-cs-gpio-pins {
+ qup_spi9_cs_gpio: qup-spi9-cs-gpio-state {
pins = "gpio39";
function = "gpio";
};
- qup_spi10_data_clk: qup-spi10-data-clk-pins {
+ qup_spi10_data_clk: qup-spi10-data-clk-state {
pins = "gpio40", "gpio41", "gpio42";
function = "qup12";
};
- qup_spi10_cs: qup-spi10-cs-pins {
+ qup_spi10_cs: qup-spi10-cs-state {
pins = "gpio43";
function = "qup12";
};
- qup_spi10_cs_gpio: qup-spi10-cs-gpio-pins {
+ qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
pins = "gpio43";
function = "gpio";
};
- qup_spi11_data_clk: qup-spi11-data-clk-pins {
+ qup_spi11_data_clk: qup-spi11-data-clk-state {
pins = "gpio44", "gpio45", "gpio46";
function = "qup13";
};
- qup_spi11_cs: qup-spi11-cs-pins {
+ qup_spi11_cs: qup-spi11-cs-state {
pins = "gpio47";
function = "qup13";
};
- qup_spi11_cs_gpio: qup-spi11-cs-gpio-pins {
+ qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
pins = "gpio47";
function = "gpio";
};
- qup_spi12_data_clk: qup-spi12-data-clk-pins {
+ qup_spi12_data_clk: qup-spi12-data-clk-state {
pins = "gpio48", "gpio49", "gpio50";
function = "qup14";
};
- qup_spi12_cs: qup-spi12-cs-pins {
+ qup_spi12_cs: qup-spi12-cs-state {
pins = "gpio51";
function = "qup14";
};
- qup_spi12_cs_gpio: qup-spi12-cs-gpio-pins {
+ qup_spi12_cs_gpio: qup-spi12-cs-gpio-state {
pins = "gpio51";
function = "gpio";
};
- qup_spi13_data_clk: qup-spi13-data-clk-pins {
+ qup_spi13_data_clk: qup-spi13-data-clk-state {
pins = "gpio52", "gpio53", "gpio54";
function = "qup15";
};
- qup_spi13_cs: qup-spi13-cs-pins {
+ qup_spi13_cs: qup-spi13-cs-state {
pins = "gpio55";
function = "qup15";
};
- qup_spi13_cs_gpio: qup-spi13-cs-gpio-pins {
+ qup_spi13_cs_gpio: qup-spi13-cs-gpio-state {
pins = "gpio55";
function = "gpio";
};
- qup_spi14_data_clk: qup-spi14-data-clk-pins {
+ qup_spi14_data_clk: qup-spi14-data-clk-state {
pins = "gpio56", "gpio57", "gpio58";
function = "qup16";
};
- qup_spi14_cs: qup-spi14-cs-pins {
+ qup_spi14_cs: qup-spi14-cs-state {
pins = "gpio59";
function = "qup16";
};
- qup_spi14_cs_gpio: qup-spi14-cs-gpio-pins {
+ qup_spi14_cs_gpio: qup-spi14-cs-gpio-state {
pins = "gpio59";
function = "gpio";
};
- qup_spi15_data_clk: qup-spi15-data-clk-pins {
+ qup_spi15_data_clk: qup-spi15-data-clk-state {
pins = "gpio60", "gpio61", "gpio62";
function = "qup17";
};
- qup_spi15_cs: qup-spi15-cs-pins {
+ qup_spi15_cs: qup-spi15-cs-state {
pins = "gpio63";
function = "qup17";
};
- qup_spi15_cs_gpio: qup-spi15-cs-gpio-pins {
+ qup_spi15_cs_gpio: qup-spi15-cs-gpio-state {
pins = "gpio63";
function = "gpio";
};
- qup_uart0_cts: qup-uart0-cts-pins {
+ qup_uart0_cts: qup-uart0-cts-state {
pins = "gpio0";
function = "qup00";
};
- qup_uart0_rts: qup-uart0-rts-pins {
+ qup_uart0_rts: qup-uart0-rts-state {
pins = "gpio1";
function = "qup00";
};
- qup_uart0_tx: qup-uart0-tx-pins {
+ qup_uart0_tx: qup-uart0-tx-state {
pins = "gpio2";
function = "qup00";
};
- qup_uart0_rx: qup-uart0-rx-pins {
+ qup_uart0_rx: qup-uart0-rx-state {
pins = "gpio3";
function = "qup00";
};
- qup_uart1_cts: qup-uart1-cts-pins {
+ qup_uart1_cts: qup-uart1-cts-state {
pins = "gpio4";
function = "qup01";
};
- qup_uart1_rts: qup-uart1-rts-pins {
+ qup_uart1_rts: qup-uart1-rts-state {
pins = "gpio5";
function = "qup01";
};
- qup_uart1_tx: qup-uart1-tx-pins {
+ qup_uart1_tx: qup-uart1-tx-state {
pins = "gpio6";
function = "qup01";
};
- qup_uart1_rx: qup-uart1-rx-pins {
+ qup_uart1_rx: qup-uart1-rx-state {
pins = "gpio7";
function = "qup01";
};
- qup_uart2_cts: qup-uart2-cts-pins {
+ qup_uart2_cts: qup-uart2-cts-state {
pins = "gpio8";
function = "qup02";
};
- qup_uart2_rts: qup-uart2-rts-pins {
+ qup_uart2_rts: qup-uart2-rts-state {
pins = "gpio9";
function = "qup02";
};
- qup_uart2_tx: qup-uart2-tx-pins {
+ qup_uart2_tx: qup-uart2-tx-state {
pins = "gpio10";
function = "qup02";
};
- qup_uart2_rx: qup-uart2-rx-pins {
+ qup_uart2_rx: qup-uart2-rx-state {
pins = "gpio11";
function = "qup02";
};
- qup_uart3_cts: qup-uart3-cts-pins {
+ qup_uart3_cts: qup-uart3-cts-state {
pins = "gpio12";
function = "qup03";
};
- qup_uart3_rts: qup-uart3-rts-pins {
+ qup_uart3_rts: qup-uart3-rts-state {
pins = "gpio13";
function = "qup03";
};
- qup_uart3_tx: qup-uart3-tx-pins {
+ qup_uart3_tx: qup-uart3-tx-state {
pins = "gpio14";
function = "qup03";
};
- qup_uart3_rx: qup-uart3-rx-pins {
+ qup_uart3_rx: qup-uart3-rx-state {
pins = "gpio15";
function = "qup03";
};
- qup_uart4_cts: qup-uart4-cts-pins {
+ qup_uart4_cts: qup-uart4-cts-state {
pins = "gpio16";
function = "qup04";
};
- qup_uart4_rts: qup-uart4-rts-pins {
+ qup_uart4_rts: qup-uart4-rts-state {
pins = "gpio17";
function = "qup04";
};
- qup_uart4_tx: qup-uart4-tx-pins {
+ qup_uart4_tx: qup-uart4-tx-state {
pins = "gpio18";
function = "qup04";
};
- qup_uart4_rx: qup-uart4-rx-pins {
+ qup_uart4_rx: qup-uart4-rx-state {
pins = "gpio19";
function = "qup04";
};
- qup_uart5_cts: qup-uart5-cts-pins {
+ qup_uart5_cts: qup-uart5-cts-state {
pins = "gpio20";
function = "qup05";
};
- qup_uart5_rts: qup-uart5-rts-pins {
+ qup_uart5_rts: qup-uart5-rts-state {
pins = "gpio21";
function = "qup05";
};
- qup_uart5_tx: qup-uart5-tx-pins {
+ qup_uart5_tx: qup-uart5-tx-state {
pins = "gpio22";
function = "qup05";
};
- qup_uart5_rx: qup-uart5-rx-pins {
+ qup_uart5_rx: qup-uart5-rx-state {
pins = "gpio23";
function = "qup05";
};
- qup_uart6_cts: qup-uart6-cts-pins {
+ qup_uart6_cts: qup-uart6-cts-state {
pins = "gpio24";
function = "qup06";
};
- qup_uart6_rts: qup-uart6-rts-pins {
+ qup_uart6_rts: qup-uart6-rts-state {
pins = "gpio25";
function = "qup06";
};
- qup_uart6_tx: qup-uart6-tx-pins {
+ qup_uart6_tx: qup-uart6-tx-state {
pins = "gpio26";
function = "qup06";
};
- qup_uart6_rx: qup-uart6-rx-pins {
+ qup_uart6_rx: qup-uart6-rx-state {
pins = "gpio27";
function = "qup06";
};
- qup_uart7_cts: qup-uart7-cts-pins {
+ qup_uart7_cts: qup-uart7-cts-state {
pins = "gpio28";
function = "qup07";
};
- qup_uart7_rts: qup-uart7-rts-pins {
+ qup_uart7_rts: qup-uart7-rts-state {
pins = "gpio29";
function = "qup07";
};
- qup_uart7_tx: qup-uart7-tx-pins {
+ qup_uart7_tx: qup-uart7-tx-state {
pins = "gpio30";
function = "qup07";
};
- qup_uart7_rx: qup-uart7-rx-pins {
+ qup_uart7_rx: qup-uart7-rx-state {
pins = "gpio31";
function = "qup07";
};
- qup_uart8_cts: qup-uart8-cts-pins {
+ qup_uart8_cts: qup-uart8-cts-state {
pins = "gpio32";
function = "qup10";
};
- qup_uart8_rts: qup-uart8-rts-pins {
+ qup_uart8_rts: qup-uart8-rts-state {
pins = "gpio33";
function = "qup10";
};
- qup_uart8_tx: qup-uart8-tx-pins {
+ qup_uart8_tx: qup-uart8-tx-state {
pins = "gpio34";
function = "qup10";
};
- qup_uart8_rx: qup-uart8-rx-pins {
+ qup_uart8_rx: qup-uart8-rx-state {
pins = "gpio35";
function = "qup10";
};
- qup_uart9_cts: qup-uart9-cts-pins {
+ qup_uart9_cts: qup-uart9-cts-state {
pins = "gpio36";
function = "qup11";
};
- qup_uart9_rts: qup-uart9-rts-pins {
+ qup_uart9_rts: qup-uart9-rts-state {
pins = "gpio37";
function = "qup11";
};
- qup_uart9_tx: qup-uart9-tx-pins {
+ qup_uart9_tx: qup-uart9-tx-state {
pins = "gpio38";
function = "qup11";
};
- qup_uart9_rx: qup-uart9-rx-pins {
+ qup_uart9_rx: qup-uart9-rx-state {
pins = "gpio39";
function = "qup11";
};
- qup_uart10_cts: qup-uart10-cts-pins {
+ qup_uart10_cts: qup-uart10-cts-state {
pins = "gpio40";
function = "qup12";
};
- qup_uart10_rts: qup-uart10-rts-pins {
+ qup_uart10_rts: qup-uart10-rts-state {
pins = "gpio41";
function = "qup12";
};
- qup_uart10_tx: qup-uart10-tx-pins {
+ qup_uart10_tx: qup-uart10-tx-state {
pins = "gpio42";
function = "qup12";
};
- qup_uart10_rx: qup-uart10-rx-pins {
+ qup_uart10_rx: qup-uart10-rx-state {
pins = "gpio43";
function = "qup12";
};
- qup_uart11_cts: qup-uart11-cts-pins {
+ qup_uart11_cts: qup-uart11-cts-state {
pins = "gpio44";
function = "qup13";
};
- qup_uart11_rts: qup-uart11-rts-pins {
+ qup_uart11_rts: qup-uart11-rts-state {
pins = "gpio45";
function = "qup13";
};
- qup_uart11_tx: qup-uart11-tx-pins {
+ qup_uart11_tx: qup-uart11-tx-state {
pins = "gpio46";
function = "qup13";
};
- qup_uart11_rx: qup-uart11-rx-pins {
+ qup_uart11_rx: qup-uart11-rx-state {
pins = "gpio47";
function = "qup13";
};
- qup_uart12_cts: qup-uart12-cts-pins {
+ qup_uart12_cts: qup-uart12-cts-state {
pins = "gpio48";
function = "qup14";
};
- qup_uart12_rts: qup-uart12-rts-pins {
+ qup_uart12_rts: qup-uart12-rts-state {
pins = "gpio49";
function = "qup14";
};
- qup_uart12_tx: qup-uart12-tx-pins {
+ qup_uart12_tx: qup-uart12-tx-state {
pins = "gpio50";
function = "qup14";
};
- qup_uart12_rx: qup-uart12-rx-pins {
+ qup_uart12_rx: qup-uart12-rx-state {
pins = "gpio51";
function = "qup14";
};
- qup_uart13_cts: qup-uart13-cts-pins {
+ qup_uart13_cts: qup-uart13-cts-state {
pins = "gpio52";
function = "qup15";
};
- qup_uart13_rts: qup-uart13-rts-pins {
+ qup_uart13_rts: qup-uart13-rts-state {
pins = "gpio53";
function = "qup15";
};
- qup_uart13_tx: qup-uart13-tx-pins {
+ qup_uart13_tx: qup-uart13-tx-state {
pins = "gpio54";
function = "qup15";
};
- qup_uart13_rx: qup-uart13-rx-pins {
+ qup_uart13_rx: qup-uart13-rx-state {
pins = "gpio55";
function = "qup15";
};
- qup_uart14_cts: qup-uart14-cts-pins {
+ qup_uart14_cts: qup-uart14-cts-state {
pins = "gpio56";
function = "qup16";
};
- qup_uart14_rts: qup-uart14-rts-pins {
+ qup_uart14_rts: qup-uart14-rts-state {
pins = "gpio57";
function = "qup16";
};
- qup_uart14_tx: qup-uart14-tx-pins {
+ qup_uart14_tx: qup-uart14-tx-state {
pins = "gpio58";
function = "qup16";
};
- qup_uart14_rx: qup-uart14-rx-pins {
+ qup_uart14_rx: qup-uart14-rx-state {
pins = "gpio59";
function = "qup16";
};
- qup_uart15_cts: qup-uart15-cts-pins {
+ qup_uart15_cts: qup-uart15-cts-state {
pins = "gpio60";
function = "qup17";
};
- qup_uart15_rts: qup-uart15-rts-pins {
+ qup_uart15_rts: qup-uart15-rts-state {
pins = "gpio61";
function = "qup17";
};
- qup_uart15_tx: qup-uart15-tx-pins {
+ qup_uart15_tx: qup-uart15-tx-state {
pins = "gpio62";
function = "qup17";
};
- qup_uart15_rx: qup-uart15-rx-pins {
+ qup_uart15_rx: qup-uart15-rx-state {
pins = "gpio63";
function = "qup17";
};
- sdc1_clk: sdc1-clk-pins {
+ sdc1_clk: sdc1-clk-state {
pins = "sdc1_clk";
};
- sdc1_cmd: sdc1-cmd-pins {
+ sdc1_cmd: sdc1-cmd-state {
pins = "sdc1_cmd";
};
- sdc1_data: sdc1-data-pins {
+ sdc1_data: sdc1-data-state {
pins = "sdc1_data";
};
- sdc1_rclk: sdc1-rclk-pins {
+ sdc1_rclk: sdc1-rclk-state {
pins = "sdc1_rclk";
};
- sdc1_clk_sleep: sdc1-clk-sleep-pins {
+ sdc1_clk_sleep: sdc1-clk-sleep-state {
pins = "sdc1_clk";
drive-strength = <2>;
bias-bus-hold;
};
- sdc1_cmd_sleep: sdc1-cmd-sleep-pins {
+ sdc1_cmd_sleep: sdc1-cmd-sleep-state {
pins = "sdc1_cmd";
drive-strength = <2>;
bias-bus-hold;
};
- sdc1_data_sleep: sdc1-data-sleep-pins {
+ sdc1_data_sleep: sdc1-data-sleep-state {
pins = "sdc1_data";
drive-strength = <2>;
bias-bus-hold;
};
- sdc1_rclk_sleep: sdc1-rclk-sleep-pins {
+ sdc1_rclk_sleep: sdc1-rclk-sleep-state {
pins = "sdc1_rclk";
drive-strength = <2>;
bias-bus-hold;
};
- sdc2_clk: sdc2-clk-pins {
+ sdc2_clk: sdc2-clk-state {
pins = "sdc2_clk";
};
- sdc2_cmd: sdc2-cmd-pins {
+ sdc2_cmd: sdc2-cmd-state {
pins = "sdc2_cmd";
};
- sdc2_data: sdc2-data-pins {
+ sdc2_data: sdc2-data-state {
pins = "sdc2_data";
};
- sdc2_clk_sleep: sdc2-clk-sleep-pins {
+ sdc2_clk_sleep: sdc2-clk-sleep-state {
pins = "sdc2_clk";
drive-strength = <2>;
bias-bus-hold;
};
- sdc2_cmd_sleep: sdc2-cmd-sleep-pins {
+ sdc2_cmd_sleep: sdc2-cmd-sleep-state {
pins = "sdc2_cmd";
drive-strength = <2>;
bias-bus-hold;
};
- sdc2_data_sleep: sdc2-data-sleep-pins {
+ sdc2_data_sleep: sdc2-data-sleep-state {
pins = "sdc2_data";
drive-strength = <2>;
bias-bus-hold;
@@ -5314,7 +5318,7 @@
};
epss_l3: interconnect@18590000 {
- compatible = "qcom,sc7280-epss-l3";
+ compatible = "qcom,sc7280-epss-l3", "qcom,epss-l3";
reg = <0 0x18590000 0 0x1000>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
clock-names = "xo", "alternate";
@@ -5322,7 +5326,7 @@
};
cpufreq_hw: cpufreq@18591000 {
- compatible = "qcom,cpufreq-epss";
+ compatible = "qcom,sc7280-cpufreq-epss", "qcom,cpufreq-epss";
reg = <0 0x18591000 0 0x1000>,
<0 0x18592000 0 0x1000>,
<0 0x18593000 0 0x1000>;
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