diff options
51 files changed, 5123 insertions, 328 deletions
diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm11351-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/brcm,bcm11351-pinctrl.txt index 4eaae32821ae..e047a198db38 100644 --- a/Documentation/devicetree/bindings/pinctrl/brcm,bcm11351-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm11351-pinctrl.txt @@ -85,7 +85,7 @@ Optional Properties (for I2C pins): - function: String. Specifies the pin mux selection. Values must be one of: "alt1", "alt2", "alt3", "alt4" - bias-pull-up: Integer. Pull up strength in Ohm. There are 3 - pull-up resisitors (1.2k, 1.8k, 2.7k) available + pull-up resistors (1.2k, 1.8k, 2.7k) available in parallel for I2C pins, so the valid values are: 568, 720, 831, 1080, 1200, 1800, 2700 Ohm. - bias-disable: No arguments. Disable pin bias. diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml new file mode 100644 index 000000000000..175a992f15e1 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/brcm,bcm4908-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM4908 pin controller + +maintainers: + - Rafał Miłecki <[email protected]> + +description: + Binding for pin controller present on BCM4908 family SoCs. + +properties: + compatible: + const: brcm,bcm4908-pinctrl + + reg: + maxItems: 1 + +patternProperties: + '-pins$': + type: object + $ref: pinmux-node.yaml# + + properties: + function: + enum: [ led_0, led_1, led_2, led_3, led_4, led_5, led_6, led_7, led_8, + led_9, led_10, led_11, led_12, led_13, led_14, led_15, led_16, + led_17, led_18, led_19, led_20, led_21, led_22, led_23, led_24, + led_25, led_26, led_27, led_28, led_29, led_30, led_31, + hs_uart, i2c, i2s, nand_ctrl, nand_data, emmc_ctrl, usb0_pwr, + usb1_pwr ] + + groups: + minItems: 1 + maxItems: 2 + items: + enum: [ led_0_grp_a, led_1_grp_a, led_2_grp_a, led_3_grp_a, + led_4_grp_a, led_5_grp_a, led_6_grp_a, led_7_grp_a, + led_8_grp_a, led_9_grp_a, led_10_grp_a, led_10_grp_b, + led_11_grp_a, led_11_grp_b, led_12_grp_a, led_12_grp_b, + led_13_grp_a, led_13_grp_b, led_14_grp_a, led_15_grp_a, + led_16_grp_a, led_17_grp_a, led_18_grp_a, led_19_grp_a, + led_20_grp_a, led_21_grp_a, led_22_grp_a, led_23_grp_a, + led_24_grp_a, led_25_grp_a, led_26_grp_a, led_27_grp_a, + led_28_grp_a, led_29_grp_a, led_30_grp_a, led_31_grp_a, + led_31_grp_b, hs_uart_grp, i2c_grp_a, i2c_grp_b, i2s_grp, + nand_ctrl_grp, nand_data_grp, emmc_ctrl_grp, usb0_pwr_grp, + usb1_pwr_grp ] + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + pinctrl@ff800560 { + compatible = "brcm,bcm4908-pinctrl"; + reg = <0xff800560 0x10>; + + led_0-a-pins { + function = "led_0"; + groups = "led_0_grp_a"; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt index 0aff1f28495c..8146193bd8ac 100644 --- a/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt @@ -16,6 +16,7 @@ Required properties for the root node: "amlogic,meson-g12a-periphs-pinctrl" "amlogic,meson-g12a-aobus-pinctrl" "amlogic,meson-a1-periphs-pinctrl" + "amlogic,meson-s4-periphs-pinctrl" - reg: address and size of registers controlling irq functionality === GPIO sub-nodes === diff --git a/Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml b/Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml index cb554084bdf1..0df4e114fdd6 100644 --- a/Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml +++ b/Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml @@ -145,7 +145,7 @@ examples: clocks = <&sys_clk>; pinctrl-0 = <&sgpio2_pins>; pinctrl-names = "default"; - reg = <0x1101059c 0x100>; + reg = <0x1101059c 0x118>; microchip,sgpio-port-ranges = <0 0>, <16 18>, <28 31>; bus-frequency = <25000000>; sgpio_in2: gpio@0 { diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt index 3bb76487669f..5d84fd299ccf 100644 --- a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt @@ -4,8 +4,8 @@ Microsemi Ocelot pin controller Device Tree Bindings Required properties: - compatible : Should be "mscc,ocelot-pinctrl", "mscc,jaguar2-pinctrl", "microchip,sparx5-pinctrl", - "mscc,luton-pinctrl", "mscc,serval-pinctrl" or - "microchip,lan966x-pinctrl" + "mscc,luton-pinctrl", "mscc,serval-pinctrl", + "microchip,lan966x-pinctrl" or "mscc,servalt-pinctrl" - reg : Address and length of the register set for the device - gpio-controller : Indicates this device is a GPIO controller - #gpio-cells : Must be 2. diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml index 328ea59c5466..8299662c2c09 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml @@ -99,6 +99,14 @@ patternProperties: enum: [2, 4, 6, 8, 10, 12, 14, 16] bias-pull-down: + oneOf: + - type: boolean + - enum: [100, 101, 102, 103] + description: mt8195 pull down PUPD/R0/R1 type define value. + - enum: [200, 201, 202, 203, 204, 205, 206, 207] + description: mt8195 pull down RSEL type define value. + - enum: [75000, 5000] + description: mt8195 pull down RSEL type si unit value(ohm). description: | For pull down type is normal, it don't need add RSEL & R1R0 define and resistance value. @@ -115,13 +123,6 @@ patternProperties: & "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111" define in mt8195. It can also support resistance value(ohm) "75000" & "5000" in mt8195. - oneOf: - - enum: [100, 101, 102, 103] - - description: mt8195 pull down PUPD/R0/R1 type define value. - - enum: [200, 201, 202, 203, 204, 205, 206, 207] - - description: mt8195 pull down RSEL type define value. - - enum: [75000, 5000] - - description: mt8195 pull down RSEL type si unit value(ohm). An example of using RSEL define: pincontroller { @@ -146,6 +147,14 @@ patternProperties: }; bias-pull-up: + oneOf: + - type: boolean + - enum: [100, 101, 102, 103] + description: mt8195 pull up PUPD/R0/R1 type define value. + - enum: [200, 201, 202, 203, 204, 205, 206, 207] + description: mt8195 pull up RSEL type define value. + - enum: [1000, 1500, 2000, 3000, 4000, 5000, 10000, 75000] + description: mt8195 pull up RSEL type si unit value(ohm). description: | For pull up type is normal, it don't need add RSEL & R1R0 define and resistance value. @@ -163,13 +172,6 @@ patternProperties: define in mt8195. It can also support resistance value(ohm) "1000" & "1500" & "2000" & "3000" & "4000" & "5000" & "10000" & "75000" in mt8195. - oneOf: - - enum: [100, 101, 102, 103] - - description: mt8195 pull up PUPD/R0/R1 type define value. - - enum: [200, 201, 202, 203, 204, 205, 206, 207] - - description: mt8195 pull up RSEL type define value. - - enum: [1000, 1500, 2000, 3000, 4000, 5000, 10000, 75000] - - description: mt8195 pull up RSEL type si unit value(ohm). An example of using RSEL define: pincontroller { i2c0-pins { diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml index 64c0a41ca0c3..d4da558cde54 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml @@ -34,6 +34,8 @@ properties: gpio-controller: true + gpio-reserved-ranges: true + '#gpio-cells': description: Specifying the pin number and flags, as defined in include/dt-bindings/gpio/gpio.h diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml index 35c846f59979..df79274d0ec3 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml @@ -21,6 +21,7 @@ properties: - qcom,pm8019-mpp - qcom,pm8038-mpp - qcom,pm8058-mpp + - qcom,pm8226-mpp - qcom,pm8821-mpp - qcom,pm8841-mpp - qcom,pm8916-mpp diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml index be8cb0ead62f..780f15bb5e40 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml @@ -73,7 +73,6 @@ $defs: properties: drive-strength: enum: [2, 4, 6, 8, 10, 12, 14, 16] - default: 2 description: Selects the drive strength for the specified pins, in mA. diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml index b749c82edebd..9ccf54870aa4 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -4,14 +4,14 @@ $id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Renesas RZ/G2L combined Pin and GPIO controller +title: Renesas RZ/{G2L,V2L} combined Pin and GPIO controller maintainers: - Geert Uytterhoeven <[email protected]> - Lad Prabhakar <[email protected]> description: - The Renesas SoCs of the RZ/G2L series feature a combined Pin and GPIO + The Renesas SoCs of the RZ/{G2L,V2L} series feature a combined Pin and GPIO controller. Pin multiplexing and GPIO configuration is performed on a per-pin basis. Each port features up to 8 pins, each of them configurable for GPIO function @@ -20,8 +20,15 @@ description: properties: compatible: - enum: - - renesas,r9a07g044-pinctrl # RZ/G2{L,LC} + oneOf: + - items: + - enum: + - renesas,r9a07g044-pinctrl # RZ/G2{L,LC} + + - items: + - enum: + - renesas,r9a07g054-pinctrl # RZ/V2L + - const: renesas,r9a07g044-pinctrl # RZ/G2{L,LC} fallback for RZ/V2L reg: maxItems: 1 @@ -76,6 +83,7 @@ additionalProperties: output-impedance-ohms: enum: [ 33, 50, 66, 100 ] power-source: + description: I/O voltage in millivolt. enum: [ 1800, 2500, 3300 ] slew-rate: true gpio-hog: true diff --git a/Documentation/devicetree/bindings/pinctrl/sunplus,sp7021-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/sunplus,sp7021-pinctrl.yaml new file mode 100644 index 000000000000..d8e75b3e64f1 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/sunplus,sp7021-pinctrl.yaml @@ -0,0 +1,374 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) Sunplus Co., Ltd. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/sunplus,sp7021-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sunplus SP7021 Pin Controller Device Tree Bindings + +maintainers: + - Dvorkin Dmitry <[email protected]> + - Wells Lu <[email protected]> + +description: | + The Sunplus SP7021 pin controller is used to control SoC pins. Please + refer to pinctrl-bindings.txt in this directory for details of the common + pinctrl bindings used by client devices. + + SP7021 has 99 digital GPIO pins which are numbered from GPIO 0 to 98. All + are multiplexed with some special function pins. SP7021 has 3 types of + special function pins: + + (1) function-group pins: + Ex 1 (SPI-NOR flash): + If control-field SPI_FLASH_SEL is set to 1, GPIO 83, 84, 86 and 87 + will be pins of SPI-NOR flash. If it is set to 2, GPIO 76, 78, 79 + and 81 will be pins of SPI-NOR flash. + + Ex 2 (UART_0): + If control-bit UA0_SEL is set to 1, GPIO 88 and 89 will be TX and + RX pins of UART_0 (UART channel 0). + + Ex 3 (eMMC): + If control-bit EMMC_SEL is set to 1, GPIO 72, 73, 74, 75, 76, 77, + 78, 79, 80, 81 will be pins of an eMMC device. + + Properties "function" and "groups" are used to select function-group + pins. + + (2) fully pin-mux (like phone exchange mux) pins: + GPIO 8 to 71 are 'fully pin-mux' pins. Any pins of peripherals of + SP7021 (ex: UART_1, UART_2, UART_3, UART_4, I2C_0, I2C_1, and etc.) + can be routed to any pins of fully pin-mux pins. + + Ex 1 (UART channel 1): + If control-field UA1_TX_SEL is set to 3, TX pin of UART_1 will be + routed to GPIO 10 (3 - 1 + 8 = 10). + If control-field UA1_RX_SEL is set to 4, RX pin of UART_1 will be + routed to GPIO 11 (4 - 1 + 8 = 11). + If control-field UA1_RTS_SEL is set to 5, RTS pin of UART_1 will + be routed to GPIO 12 (5 - 1 + 8 = 12). + If control-field UA1_CTS_SEL is set to 6, CTS pin of UART_1 will + be routed to GPIO 13 (6 - 1 + 8 = 13). + + Ex 2 (I2C channel 0): + If control-field I2C0_CLK_SEL is set to 20, CLK pin of I2C_0 will + be routed to GPIO 27 (20 - 1 + 8 = 27). + If control-field I2C0_DATA_SEL is set to 21, DATA pin of I2C_0 + will be routed to GPIO 28 (21 - 1 + 9 = 28). + + Totally, SP7021 has 120 peripheral pins. The peripheral pins can be + routed to any of 64 'fully pin-mux' pins. + + (3) I/O processor pins + SP7021 has a built-in I/O processor. + Any GPIO pins (GPIO 0 to 98) can be set to pins of I/O processor. + + Vendor property "sunplus,pins" is used to select "fully pin-mux" pins, + "I/O processor pins" and "digital GPIO" pins. + + The device node of pin controller of Sunplus SP7021 has following + properties. + +properties: + compatible: + const: sunplus,sp7021-pctl + + gpio-controller: true + + '#gpio-cells': + const: 2 + + reg: + items: + - description: the MOON2 registers + - description: the GPIOXT registers + - description: the FIRST registers + - description: the MOON1 registers + + reg-names: + items: + - const: moon2 + - const: gpioxt + - const: first + - const: moon1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + +patternProperties: + '-pins$': + type: object + description: | + A pinctrl node should contain at least one subnodes representing the + pins or function-pins group available on the machine. Each subnode + will list the pins it needs, and how they should be configured. + + Pinctrl node's client devices use subnodes for desired pin + configuration. Client device subnodes use below standard properties. + $ref: pinmux-node.yaml# + + properties: + sunplus,pins: + description: | + Define 'sunplus,pins' which are used by pinctrl node's client + device. + + It consists of one or more integers which represents the config + setting for corresponding pin. Each integer defines a individual + pin in which: + + Bit 32~24: defines GPIO number. Its range is 0 ~ 98. + Bit 23~16: defines types: (1) fully pin-mux pins + (2) IO processor pins + (3) digital GPIO pins + Bit 15~8: defines pins of peripherals (which are defined in + 'include/dt-binging/pinctrl/sppctl.h'). + Bit 7~0: defines types or initial-state of digital GPIO pins. + + Please use macro SPPCTL_IOPAD to define the integers for pins. + + $ref: /schemas/types.yaml#/definitions/uint32-array + + function: + description: | + Define pin-function which is used by pinctrl node's client device. + The name should be one of string in the following enumeration. + $ref: "/schemas/types.yaml#/definitions/string" + enum: [ SPI_FLASH, SPI_FLASH_4BIT, SPI_NAND, CARD0_EMMC, SD_CARD, + UA0, FPGA_IFX, HDMI_TX, LCDIF, USB0_OTG, USB1_OTG ] + + groups: + description: | + Define pin-group in a specified pin-function. + The name should be one of string in the following enumeration. + $ref: "/schemas/types.yaml#/definitions/string" + enum: [ SPI_FLASH1, SPI_FLASH2, SPI_FLASH_4BIT1, SPI_FLASH_4BIT2, + SPI_NAND, CARD0_EMMC, SD_CARD, UA0, FPGA_IFX, HDMI_TX1, + HDMI_TX2, HDMI_TX3, LCDIF, USB0_OTG, USB1_OTG ] + + sunplus,zerofunc: + description: | + This is a vendor specific property. It is used to disable pins + which are not used by pinctrl node's client device. + Some pins may be enabled by boot-loader. We can use this + property to disable them. + $ref: /schemas/types.yaml#/definitions/uint32-array + + additionalProperties: false + + allOf: + - if: + properties: + function: + enum: + - SPI_FLASH + then: + properties: + groups: + enum: + - SPI_FLASH1 + - SPI_FLASH2 + - if: + properties: + function: + enum: + - SPI_FLASH_4BIT + then: + properties: + groups: + enum: + - SPI_FLASH_4BIT1 + - SPI_FLASH_4BIT2 + - if: + properties: + function: + enum: + - SPI_NAND + then: + properties: + groups: + enum: + - SPI_NAND + - if: + properties: + function: + enum: + - CARD0_EMMC + then: + properties: + groups: + enum: + - CARD0_EMMC + - if: + properties: + function: + enum: + - SD_CARD + then: + properties: + groups: + enum: + - SD_CARD + - if: + properties: + function: + enum: + - UA0 + then: + properties: + groups: + enum: + - UA0 + - if: + properties: + function: + enum: + - FPGA_IFX + then: + properties: + groups: + enum: + - FPGA_IFX + - if: + properties: + function: + enum: + - HDMI_TX + then: + properties: + groups: + enum: + - HDMI_TX1 + - HDMI_TX2 + - HDMI_TX3 + - if: + properties: + function: + enum: + - LCDIF + then: + properties: + groups: + enum: + - LCDIF + - if: + properties: + function: + enum: + - USB0_OTG + then: + properties: + groups: + enum: + - USB0_OTG + - if: + properties: + function: + enum: + - USB1_OTG + then: + properties: + groups: + enum: + - USB1_OTG + +required: + - compatible + - reg + - reg-names + - "#gpio-cells" + - gpio-controller + - clocks + - resets + +additionalProperties: false + +examples: + - | + #include <dt-bindings/pinctrl/sppctl-sp7021.h> + + pinctl@9c000100 { + compatible = "sunplus,sp7021-pctl"; + reg = <0x9c000100 0x100>, <0x9c000300 0x100>, + <0x9c0032e4 0x1c>, <0x9c000080 0x20>; + reg-names = "moon2", "gpioxt", "first", "moon1"; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clkc 0x83>; + resets = <&rstc 0x73>; + + uart0-pins { + function = "UA0"; + groups = "UA0"; + }; + + spinand0-pins { + function = "SPI_NAND"; + groups = "SPI_NAND"; + }; + + uart1-pins { + sunplus,pins = < + SPPCTL_IOPAD(11, SPPCTL_PCTL_G_PMUX, MUXF_UA1_TX, 0) + SPPCTL_IOPAD(10, SPPCTL_PCTL_G_PMUX, MUXF_UA1_RX, 0) + >; + }; + + uart2-pins { + sunplus,pins = < + SPPCTL_IOPAD(20, SPPCTL_PCTL_G_PMUX, MUXF_UA1_TX, 0) + SPPCTL_IOPAD(21, SPPCTL_PCTL_G_PMUX, MUXF_UA1_RX, 0) + SPPCTL_IOPAD(22, SPPCTL_PCTL_G_PMUX, MUXF_UA1_RTS, 0) + SPPCTL_IOPAD(23, SPPCTL_PCTL_G_PMUX, MUXF_UA1_CTS, 0) + >; + }; + + emmc-pins { + function = "CARD0_EMMC"; + groups = "CARD0_EMMC"; + }; + + sdcard-pins { + function = "SD_CARD"; + groups = "SD_CARD"; + sunplus,pins = < SPPCTL_IOPAD(91, SPPCTL_PCTL_G_GPIO, 0, 0) >; + }; + + hdmi_A_tx1-pins { + function = "HDMI_TX"; + groups = "HDMI_TX1"; + }; + hdmi_A_tx2-pins { + function = "HDMI_TX"; + groups = "HDMI_TX2"; + }; + hdmi_A_tx3-pins { + function = "HDMI_TX"; + groups = "HDMI_TX3"; + }; + + ethernet-pins { + sunplus,pins = < + SPPCTL_IOPAD(49,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_CLK_OUT,0) + SPPCTL_IOPAD(44,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_MAC_SMI_MDC,0) + SPPCTL_IOPAD(43,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_MAC_SMI_MDIO,0) + SPPCTL_IOPAD(52,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXEN,0) + SPPCTL_IOPAD(50,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXD0,0) + SPPCTL_IOPAD(51,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXD1,0) + SPPCTL_IOPAD(46,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_CRSDV,0) + SPPCTL_IOPAD(47,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXD0,0) + SPPCTL_IOPAD(48,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXD1,0) + >; + sunplus,zerofunc = < + MUXF_L2SW_LED_FLASH0 + MUXF_L2SW_LED_ON0 + MUXF_L2SW_P0_MAC_RMII_RXER + >; + }; + }; +... diff --git a/MAINTAINERS b/MAINTAINERS index 89f23af16451..1c2c44c6cef5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3688,6 +3688,14 @@ F: Documentation/devicetree/bindings/net/brcm,bcm4908-enet.yaml F: drivers/net/ethernet/broadcom/bcm4908_enet.* F: drivers/net/ethernet/broadcom/unimac.h +BROADCOM BCM4908 PINMUX DRIVER +M: Rafał Miłecki <[email protected]> +S: Maintained +F: Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml +F: drivers/pinctrl/bcm/pinctrl-bcm4908.c + BROADCOM BCM5301X ARM ARCHITECTURE M: Florian Fainelli <[email protected]> M: Hauke Mehrtens <[email protected]> @@ -15302,6 +15310,16 @@ M: Lakshmi Sowjanya D <[email protected]> S: Supported F: drivers/pinctrl/pinctrl-thunderbay.c +PIN CONTROLLER - SUNPLUS / TIBBO +M: Dvorkin Dmitry <[email protected]> +M: Wells Lu <[email protected]> +L: [email protected] (moderated for non-subscribers) +S: Maintained +W: https://sunplus.atlassian.net/wiki/spaces/doc/overview +F: Documentation/devicetree/bindings/pinctrl/sunplus,* +F: drivers/pinctrl/sunplus/ +F: include/dt-bindings/pinctrl/sppctl*.h + PKTCDVD DRIVER S: Orphan diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 6fc56d6598e2..f52960d2dfbe 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -527,6 +527,7 @@ source "drivers/pinctrl/samsung/Kconfig" source "drivers/pinctrl/spear/Kconfig" source "drivers/pinctrl/sprd/Kconfig" source "drivers/pinctrl/stm32/Kconfig" +source "drivers/pinctrl/sunplus/Kconfig" source "drivers/pinctrl/sunxi/Kconfig" source "drivers/pinctrl/tegra/Kconfig" source "drivers/pinctrl/ti/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 08c364d611f5..b09c5345f82c 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -71,6 +71,7 @@ obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/ obj-$(CONFIG_PINCTRL_SPEAR) += spear/ obj-y += sprd/ obj-$(CONFIG_PINCTRL_STM32) += stm32/ +obj-y += sunplus/ obj-$(CONFIG_PINCTRL_SUNXI) += sunxi/ obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-y += ti/ diff --git a/drivers/pinctrl/bcm/Kconfig b/drivers/pinctrl/bcm/Kconfig index 5123f4c33854..042ec2494698 100644 --- a/drivers/pinctrl/bcm/Kconfig +++ b/drivers/pinctrl/bcm/Kconfig @@ -29,6 +29,20 @@ config PINCTRL_BCM2835 help Say Y here to enable the Broadcom BCM2835 GPIO driver. +config PINCTRL_BCM4908 + tristate "Broadcom BCM4908 pinmux driver" + depends on OF && (ARCH_BCM4908 || COMPILE_TEST) + select PINMUX + select PINCONF + select GENERIC_PINCONF + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + default ARCH_BCM4908 + help + Driver for BCM4908 family SoCs with integrated pin controller. + + If compiled as module it will be called pinctrl-bcm4908. + config PINCTRL_BCM63XX bool select PINMUX diff --git a/drivers/pinctrl/bcm/Makefile b/drivers/pinctrl/bcm/Makefile index 00c7b7775e63..82b868ec1471 100644 --- a/drivers/pinctrl/bcm/Makefile +++ b/drivers/pinctrl/bcm/Makefile @@ -3,6 +3,7 @@ obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o +obj-$(CONFIG_PINCTRL_BCM4908) += pinctrl-bcm4908.o obj-$(CONFIG_PINCTRL_BCM63XX) += pinctrl-bcm63xx.o obj-$(CONFIG_PINCTRL_BCM6318) += pinctrl-bcm6318.o obj-$(CONFIG_PINCTRL_BCM6328) += pinctrl-bcm6328.o diff --git a/drivers/pinctrl/bcm/pinctrl-bcm4908.c b/drivers/pinctrl/bcm/pinctrl-bcm4908.c new file mode 100644 index 000000000000..cdfa165fc033 --- /dev/null +++ b/drivers/pinctrl/bcm/pinctrl-bcm4908.c @@ -0,0 +1,563 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (C) 2021 Rafał Miłecki <[email protected]> */ + +#include <linux/err.h> +#include <linux/io.h> +#include <linux/mod_devicetable.h> +#include <linux/module.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/string_helpers.h> + +#include "../core.h" +#include "../pinmux.h" + +#define BCM4908_NUM_PINS 86 + +#define BCM4908_TEST_PORT_BLOCK_EN_LSB 0x00 +#define BCM4908_TEST_PORT_BLOCK_DATA_MSB 0x04 +#define BCM4908_TEST_PORT_BLOCK_DATA_LSB 0x08 +#define BCM4908_TEST_PORT_LSB_PINMUX_DATA_SHIFT 12 +#define BCM4908_TEST_PORT_COMMAND 0x0c +#define BCM4908_TEST_PORT_CMD_LOAD_MUX_REG 0x00000021 + +struct bcm4908_pinctrl { + struct device *dev; + void __iomem *base; + struct mutex mutex; + struct pinctrl_dev *pctldev; + struct pinctrl_desc pctldesc; +}; + +/* + * Groups + */ + +struct bcm4908_pinctrl_pin_setup { + unsigned int number; + unsigned int function; +}; + +static const struct bcm4908_pinctrl_pin_setup led_0_pins_a[] = { + { 0, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_1_pins_a[] = { + { 1, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_2_pins_a[] = { + { 2, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_3_pins_a[] = { + { 3, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_4_pins_a[] = { + { 4, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_5_pins_a[] = { + { 5, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_6_pins_a[] = { + { 6, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_7_pins_a[] = { + { 7, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_8_pins_a[] = { + { 8, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_9_pins_a[] = { + { 9, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_10_pins_a[] = { + { 10, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_11_pins_a[] = { + { 11, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_12_pins_a[] = { + { 12, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_13_pins_a[] = { + { 13, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_14_pins_a[] = { + { 14, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_15_pins_a[] = { + { 15, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_16_pins_a[] = { + { 16, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_17_pins_a[] = { + { 17, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_18_pins_a[] = { + { 18, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_19_pins_a[] = { + { 19, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_20_pins_a[] = { + { 20, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_21_pins_a[] = { + { 21, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_22_pins_a[] = { + { 22, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_23_pins_a[] = { + { 23, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_24_pins_a[] = { + { 24, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_25_pins_a[] = { + { 25, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_26_pins_a[] = { + { 26, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_27_pins_a[] = { + { 27, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_28_pins_a[] = { + { 28, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_29_pins_a[] = { + { 29, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_30_pins_a[] = { + { 30, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_31_pins_a[] = { + { 31, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_10_pins_b[] = { + { 8, 2 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_11_pins_b[] = { + { 9, 2 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_12_pins_b[] = { + { 0, 2 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_13_pins_b[] = { + { 1, 2 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_31_pins_b[] = { + { 30, 2 }, +}; + +static const struct bcm4908_pinctrl_pin_setup hs_uart_pins[] = { + { 10, 0 }, /* CTS */ + { 11, 0 }, /* RTS */ + { 12, 0 }, /* RXD */ + { 13, 0 }, /* TXD */ +}; + +static const struct bcm4908_pinctrl_pin_setup i2c_pins_a[] = { + { 18, 0 }, /* SDA */ + { 19, 0 }, /* SCL */ +}; + +static const struct bcm4908_pinctrl_pin_setup i2c_pins_b[] = { + { 22, 0 }, /* SDA */ + { 23, 0 }, /* SCL */ +}; + +static const struct bcm4908_pinctrl_pin_setup i2s_pins[] = { + { 27, 0 }, /* MCLK */ + { 28, 0 }, /* LRCK */ + { 29, 0 }, /* SDATA */ + { 30, 0 }, /* SCLK */ +}; + +static const struct bcm4908_pinctrl_pin_setup nand_ctrl_pins[] = { + { 32, 0 }, + { 33, 0 }, + { 34, 0 }, + { 43, 0 }, + { 44, 0 }, + { 45, 0 }, + { 56, 1 }, +}; + +static const struct bcm4908_pinctrl_pin_setup nand_data_pins[] = { + { 35, 0 }, + { 36, 0 }, + { 37, 0 }, + { 38, 0 }, + { 39, 0 }, + { 40, 0 }, + { 41, 0 }, + { 42, 0 }, +}; + +static const struct bcm4908_pinctrl_pin_setup emmc_ctrl_pins[] = { + { 46, 0 }, + { 47, 0 }, +}; + +static const struct bcm4908_pinctrl_pin_setup usb0_pwr_pins[] = { + { 63, 0 }, + { 64, 0 }, +}; + +static const struct bcm4908_pinctrl_pin_setup usb1_pwr_pins[] = { + { 66, 0 }, + { 67, 0 }, +}; + +struct bcm4908_pinctrl_grp { + const char *name; + const struct bcm4908_pinctrl_pin_setup *pins; + const unsigned int num_pins; +}; + +static const struct bcm4908_pinctrl_grp bcm4908_pinctrl_grps[] = { + { "led_0_grp_a", led_0_pins_a, ARRAY_SIZE(led_0_pins_a) }, + { "led_1_grp_a", led_1_pins_a, ARRAY_SIZE(led_1_pins_a) }, + { "led_2_grp_a", led_2_pins_a, ARRAY_SIZE(led_2_pins_a) }, + { "led_3_grp_a", led_3_pins_a, ARRAY_SIZE(led_3_pins_a) }, + { "led_4_grp_a", led_4_pins_a, ARRAY_SIZE(led_4_pins_a) }, + { "led_5_grp_a", led_5_pins_a, ARRAY_SIZE(led_5_pins_a) }, + { "led_6_grp_a", led_6_pins_a, ARRAY_SIZE(led_6_pins_a) }, + { "led_7_grp_a", led_7_pins_a, ARRAY_SIZE(led_7_pins_a) }, + { "led_8_grp_a", led_8_pins_a, ARRAY_SIZE(led_8_pins_a) }, + { "led_9_grp_a", led_9_pins_a, ARRAY_SIZE(led_9_pins_a) }, + { "led_10_grp_a", led_10_pins_a, ARRAY_SIZE(led_10_pins_a) }, + { "led_11_grp_a", led_11_pins_a, ARRAY_SIZE(led_11_pins_a) }, + { "led_12_grp_a", led_12_pins_a, ARRAY_SIZE(led_12_pins_a) }, + { "led_13_grp_a", led_13_pins_a, ARRAY_SIZE(led_13_pins_a) }, + { "led_14_grp_a", led_14_pins_a, ARRAY_SIZE(led_14_pins_a) }, + { "led_15_grp_a", led_15_pins_a, ARRAY_SIZE(led_15_pins_a) }, + { "led_16_grp_a", led_16_pins_a, ARRAY_SIZE(led_16_pins_a) }, + { "led_17_grp_a", led_17_pins_a, ARRAY_SIZE(led_17_pins_a) }, + { "led_18_grp_a", led_18_pins_a, ARRAY_SIZE(led_18_pins_a) }, + { "led_19_grp_a", led_19_pins_a, ARRAY_SIZE(led_19_pins_a) }, + { "led_20_grp_a", led_20_pins_a, ARRAY_SIZE(led_20_pins_a) }, + { "led_21_grp_a", led_21_pins_a, ARRAY_SIZE(led_21_pins_a) }, + { "led_22_grp_a", led_22_pins_a, ARRAY_SIZE(led_22_pins_a) }, + { "led_23_grp_a", led_23_pins_a, ARRAY_SIZE(led_23_pins_a) }, + { "led_24_grp_a", led_24_pins_a, ARRAY_SIZE(led_24_pins_a) }, + { "led_25_grp_a", led_25_pins_a, ARRAY_SIZE(led_25_pins_a) }, + { "led_26_grp_a", led_26_pins_a, ARRAY_SIZE(led_26_pins_a) }, + { "led_27_grp_a", led_27_pins_a, ARRAY_SIZE(led_27_pins_a) }, + { "led_28_grp_a", led_28_pins_a, ARRAY_SIZE(led_28_pins_a) }, + { "led_29_grp_a", led_29_pins_a, ARRAY_SIZE(led_29_pins_a) }, + { "led_30_grp_a", led_30_pins_a, ARRAY_SIZE(led_30_pins_a) }, + { "led_31_grp_a", led_31_pins_a, ARRAY_SIZE(led_31_pins_a) }, + { "led_10_grp_b", led_10_pins_b, ARRAY_SIZE(led_10_pins_b) }, + { "led_11_grp_b", led_11_pins_b, ARRAY_SIZE(led_11_pins_b) }, + { "led_12_grp_b", led_12_pins_b, ARRAY_SIZE(led_12_pins_b) }, + { "led_13_grp_b", led_13_pins_b, ARRAY_SIZE(led_13_pins_b) }, + { "led_31_grp_b", led_31_pins_b, ARRAY_SIZE(led_31_pins_b) }, + { "hs_uart_grp", hs_uart_pins, ARRAY_SIZE(hs_uart_pins) }, + { "i2c_grp_a", i2c_pins_a, ARRAY_SIZE(i2c_pins_a) }, + { "i2c_grp_b", i2c_pins_b, ARRAY_SIZE(i2c_pins_b) }, + { "i2s_grp", i2s_pins, ARRAY_SIZE(i2s_pins) }, + { "nand_ctrl_grp", nand_ctrl_pins, ARRAY_SIZE(nand_ctrl_pins) }, + { "nand_data_grp", nand_data_pins, ARRAY_SIZE(nand_data_pins) }, + { "emmc_ctrl_grp", emmc_ctrl_pins, ARRAY_SIZE(emmc_ctrl_pins) }, + { "usb0_pwr_grp", usb0_pwr_pins, ARRAY_SIZE(usb0_pwr_pins) }, + { "usb1_pwr_grp", usb1_pwr_pins, ARRAY_SIZE(usb1_pwr_pins) }, +}; + +/* + * Functions + */ + +struct bcm4908_pinctrl_function { + const char *name; + const char * const *groups; + const unsigned int num_groups; +}; + +static const char * const led_0_groups[] = { "led_0_grp_a" }; +static const char * const led_1_groups[] = { "led_1_grp_a" }; +static const char * const led_2_groups[] = { "led_2_grp_a" }; +static const char * const led_3_groups[] = { "led_3_grp_a" }; +static const char * const led_4_groups[] = { "led_4_grp_a" }; +static const char * const led_5_groups[] = { "led_5_grp_a" }; +static const char * const led_6_groups[] = { "led_6_grp_a" }; +static const char * const led_7_groups[] = { "led_7_grp_a" }; +static const char * const led_8_groups[] = { "led_8_grp_a" }; +static const char * const led_9_groups[] = { "led_9_grp_a" }; +static const char * const led_10_groups[] = { "led_10_grp_a", "led_10_grp_b" }; +static const char * const led_11_groups[] = { "led_11_grp_a", "led_11_grp_b" }; +static const char * const led_12_groups[] = { "led_12_grp_a", "led_12_grp_b" }; +static const char * const led_13_groups[] = { "led_13_grp_a", "led_13_grp_b" }; +static const char * const led_14_groups[] = { "led_14_grp_a" }; +static const char * const led_15_groups[] = { "led_15_grp_a" }; +static const char * const led_16_groups[] = { "led_16_grp_a" }; +static const char * const led_17_groups[] = { "led_17_grp_a" }; +static const char * const led_18_groups[] = { "led_18_grp_a" }; +static const char * const led_19_groups[] = { "led_19_grp_a" }; +static const char * const led_20_groups[] = { "led_20_grp_a" }; +static const char * const led_21_groups[] = { "led_21_grp_a" }; +static const char * const led_22_groups[] = { "led_22_grp_a" }; +static const char * const led_23_groups[] = { "led_23_grp_a" }; +static const char * const led_24_groups[] = { "led_24_grp_a" }; +static const char * const led_25_groups[] = { "led_25_grp_a" }; +static const char * const led_26_groups[] = { "led_26_grp_a" }; +static const char * const led_27_groups[] = { "led_27_grp_a" }; +static const char * const led_28_groups[] = { "led_28_grp_a" }; +static const char * const led_29_groups[] = { "led_29_grp_a" }; +static const char * const led_30_groups[] = { "led_30_grp_a" }; +static const char * const led_31_groups[] = { "led_31_grp_a", "led_31_grp_b" }; +static const char * const hs_uart_groups[] = { "hs_uart_grp" }; +static const char * const i2c_groups[] = { "i2c_grp_a", "i2c_grp_b" }; +static const char * const i2s_groups[] = { "i2s_grp" }; +static const char * const nand_ctrl_groups[] = { "nand_ctrl_grp" }; +static const char * const nand_data_groups[] = { "nand_data_grp" }; +static const char * const emmc_ctrl_groups[] = { "emmc_ctrl_grp" }; +static const char * const usb0_pwr_groups[] = { "usb0_pwr_grp" }; +static const char * const usb1_pwr_groups[] = { "usb1_pwr_grp" }; + +static const struct bcm4908_pinctrl_function bcm4908_pinctrl_functions[] = { + { "led_0", led_0_groups, ARRAY_SIZE(led_0_groups) }, + { "led_1", led_1_groups, ARRAY_SIZE(led_1_groups) }, + { "led_2", led_2_groups, ARRAY_SIZE(led_2_groups) }, + { "led_3", led_3_groups, ARRAY_SIZE(led_3_groups) }, + { "led_4", led_4_groups, ARRAY_SIZE(led_4_groups) }, + { "led_5", led_5_groups, ARRAY_SIZE(led_5_groups) }, + { "led_6", led_6_groups, ARRAY_SIZE(led_6_groups) }, + { "led_7", led_7_groups, ARRAY_SIZE(led_7_groups) }, + { "led_8", led_8_groups, ARRAY_SIZE(led_8_groups) }, + { "led_9", led_9_groups, ARRAY_SIZE(led_9_groups) }, + { "led_10", led_10_groups, ARRAY_SIZE(led_10_groups) }, + { "led_11", led_11_groups, ARRAY_SIZE(led_11_groups) }, + { "led_12", led_12_groups, ARRAY_SIZE(led_12_groups) }, + { "led_13", led_13_groups, ARRAY_SIZE(led_13_groups) }, + { "led_14", led_14_groups, ARRAY_SIZE(led_14_groups) }, + { "led_15", led_15_groups, ARRAY_SIZE(led_15_groups) }, + { "led_16", led_16_groups, ARRAY_SIZE(led_16_groups) }, + { "led_17", led_17_groups, ARRAY_SIZE(led_17_groups) }, + { "led_18", led_18_groups, ARRAY_SIZE(led_18_groups) }, + { "led_19", led_19_groups, ARRAY_SIZE(led_19_groups) }, + { "led_20", led_20_groups, ARRAY_SIZE(led_20_groups) }, + { "led_21", led_21_groups, ARRAY_SIZE(led_21_groups) }, + { "led_22", led_22_groups, ARRAY_SIZE(led_22_groups) }, + { "led_23", led_23_groups, ARRAY_SIZE(led_23_groups) }, + { "led_24", led_24_groups, ARRAY_SIZE(led_24_groups) }, + { "led_25", led_25_groups, ARRAY_SIZE(led_25_groups) }, + { "led_26", led_26_groups, ARRAY_SIZE(led_26_groups) }, + { "led_27", led_27_groups, ARRAY_SIZE(led_27_groups) }, + { "led_28", led_28_groups, ARRAY_SIZE(led_28_groups) }, + { "led_29", led_29_groups, ARRAY_SIZE(led_29_groups) }, + { "led_30", led_30_groups, ARRAY_SIZE(led_30_groups) }, + { "led_31", led_31_groups, ARRAY_SIZE(led_31_groups) }, + { "hs_uart", hs_uart_groups, ARRAY_SIZE(hs_uart_groups) }, + { "i2c", i2c_groups, ARRAY_SIZE(i2c_groups) }, + { "i2s", i2s_groups, ARRAY_SIZE(i2s_groups) }, + { "nand_ctrl", nand_ctrl_groups, ARRAY_SIZE(nand_ctrl_groups) }, + { "nand_data", nand_data_groups, ARRAY_SIZE(nand_data_groups) }, + { "emmc_ctrl", emmc_ctrl_groups, ARRAY_SIZE(emmc_ctrl_groups) }, + { "usb0_pwr", usb0_pwr_groups, ARRAY_SIZE(usb0_pwr_groups) }, + { "usb1_pwr", usb1_pwr_groups, ARRAY_SIZE(usb1_pwr_groups) }, +}; + +/* + * Groups code + */ + +static const struct pinctrl_ops bcm4908_pinctrl_ops = { + .get_groups_count = pinctrl_generic_get_group_count, + .get_group_name = pinctrl_generic_get_group_name, + .get_group_pins = pinctrl_generic_get_group_pins, + .dt_node_to_map = pinconf_generic_dt_node_to_map_group, + .dt_free_map = pinconf_generic_dt_free_map, +}; + +/* + * Functions code + */ + +static int bcm4908_pinctrl_set_mux(struct pinctrl_dev *pctrl_dev, + unsigned int func_selector, + unsigned int group_selector) +{ + struct bcm4908_pinctrl *bcm4908_pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); + const struct bcm4908_pinctrl_grp *group; + struct group_desc *group_desc; + int i; + + group_desc = pinctrl_generic_get_group(pctrl_dev, group_selector); + if (!group_desc) + return -EINVAL; + group = group_desc->data; + + mutex_lock(&bcm4908_pinctrl->mutex); + for (i = 0; i < group->num_pins; i++) { + u32 lsb = 0; + + lsb |= group->pins[i].number; + lsb |= group->pins[i].function << BCM4908_TEST_PORT_LSB_PINMUX_DATA_SHIFT; + + writel(0x0, bcm4908_pinctrl->base + BCM4908_TEST_PORT_BLOCK_DATA_MSB); + writel(lsb, bcm4908_pinctrl->base + BCM4908_TEST_PORT_BLOCK_DATA_LSB); + writel(BCM4908_TEST_PORT_CMD_LOAD_MUX_REG, + bcm4908_pinctrl->base + BCM4908_TEST_PORT_COMMAND); + } + mutex_unlock(&bcm4908_pinctrl->mutex); + + return 0; +} + +static const struct pinmux_ops bcm4908_pinctrl_pmxops = { + .get_functions_count = pinmux_generic_get_function_count, + .get_function_name = pinmux_generic_get_function_name, + .get_function_groups = pinmux_generic_get_function_groups, + .set_mux = bcm4908_pinctrl_set_mux, +}; + +/* + * Controller code + */ + +static struct pinctrl_desc bcm4908_pinctrl_desc = { + .name = "bcm4908-pinctrl", + .pctlops = &bcm4908_pinctrl_ops, + .pmxops = &bcm4908_pinctrl_pmxops, +}; + +static const struct of_device_id bcm4908_pinctrl_of_match_table[] = { + { .compatible = "brcm,bcm4908-pinctrl", }, + { } +}; + +static int bcm4908_pinctrl_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct bcm4908_pinctrl *bcm4908_pinctrl; + struct pinctrl_desc *pctldesc; + struct pinctrl_pin_desc *pins; + char **pin_names; + int i; + + bcm4908_pinctrl = devm_kzalloc(dev, sizeof(*bcm4908_pinctrl), GFP_KERNEL); + if (!bcm4908_pinctrl) + return -ENOMEM; + pctldesc = &bcm4908_pinctrl->pctldesc; + platform_set_drvdata(pdev, bcm4908_pinctrl); + + /* Set basic properties */ + + bcm4908_pinctrl->dev = dev; + + bcm4908_pinctrl->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(bcm4908_pinctrl->base)) + return PTR_ERR(bcm4908_pinctrl->base); + + mutex_init(&bcm4908_pinctrl->mutex); + + memcpy(pctldesc, &bcm4908_pinctrl_desc, sizeof(*pctldesc)); + + /* Set pinctrl properties */ + + pin_names = devm_kasprintf_strarray(dev, "pin", BCM4908_NUM_PINS); + if (IS_ERR(pin_names)) + return PTR_ERR(pin_names); + + pins = devm_kcalloc(dev, BCM4908_NUM_PINS, sizeof(*pins), GFP_KERNEL); + if (!pins) + return -ENOMEM; + for (i = 0; i < BCM4908_NUM_PINS; i++) { + pins[i].number = i; + pins[i].name = pin_names[i]; + } + pctldesc->pins = pins; + pctldesc->npins = BCM4908_NUM_PINS; + + /* Register */ + + bcm4908_pinctrl->pctldev = devm_pinctrl_register(dev, pctldesc, bcm4908_pinctrl); + if (IS_ERR(bcm4908_pinctrl->pctldev)) + return dev_err_probe(dev, PTR_ERR(bcm4908_pinctrl->pctldev), + "Failed to register pinctrl\n"); + + /* Groups */ + + for (i = 0; i < ARRAY_SIZE(bcm4908_pinctrl_grps); i++) { + const struct bcm4908_pinctrl_grp *group = &bcm4908_pinctrl_grps[i]; + int *pins; + int j; + + pins = devm_kcalloc(dev, group->num_pins, sizeof(*pins), GFP_KERNEL); + if (!pins) + return -ENOMEM; + for (j = 0; j < group->num_pins; j++) + pins[j] = group->pins[j].number; + + pinctrl_generic_add_group(bcm4908_pinctrl->pctldev, group->name, + pins, group->num_pins, (void *)group); + } + + /* Functions */ + + for (i = 0; i < ARRAY_SIZE(bcm4908_pinctrl_functions); i++) { + const struct bcm4908_pinctrl_function *function = &bcm4908_pinctrl_functions[i]; + + pinmux_generic_add_function(bcm4908_pinctrl->pctldev, + function->name, + function->groups, + function->num_groups, NULL); + } + + return 0; +} + +static struct platform_driver bcm4908_pinctrl_driver = { + .probe = bcm4908_pinctrl_probe, + .driver = { + .name = "bcm4908-pinctrl", + .of_match_table = bcm4908_pinctrl_of_match_table, + }, +}; + +module_platform_driver(bcm4908_pinctrl_driver); + +MODULE_AUTHOR("Rafał Miłecki"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, bcm4908_pinctrl_of_match_table); diff --git a/drivers/pinctrl/meson/Kconfig b/drivers/pinctrl/meson/Kconfig index b2855e341a75..d1955c65b4b6 100644 --- a/drivers/pinctrl/meson/Kconfig +++ b/drivers/pinctrl/meson/Kconfig @@ -61,4 +61,10 @@ config PINCTRL_MESON_A1 select PINCTRL_MESON_AXG_PMX default y +config PINCTRL_MESON_S4 + tristate "Meson s4 Soc pinctrl driver" + depends on ARM64 + select PINCTRL_MESON_AXG_PMX + default y + endif diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile index 1a5bffe953f9..694f0596bfbc 100644 --- a/drivers/pinctrl/meson/Makefile +++ b/drivers/pinctrl/meson/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_PINCTRL_MESON_AXG_PMX) += pinctrl-meson-axg-pmx.o obj-$(CONFIG_PINCTRL_MESON_AXG) += pinctrl-meson-axg.o obj-$(CONFIG_PINCTRL_MESON_G12A) += pinctrl-meson-g12a.o obj-$(CONFIG_PINCTRL_MESON_A1) += pinctrl-meson-a1.o +obj-$(CONFIG_PINCTRL_MESON_S4) += pinctrl-meson-s4.o diff --git a/drivers/pinctrl/meson/pinctrl-meson-g12a.c b/drivers/pinctrl/meson/pinctrl-meson-g12a.c index cd9656b13836..d182a575981e 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-g12a.c +++ b/drivers/pinctrl/meson/pinctrl-meson-g12a.c @@ -283,6 +283,8 @@ static const unsigned int pwm_d_x6_pins[] = { GPIOX_6 }; static const unsigned int pwm_e_pins[] = { GPIOX_16 }; /* pwm_f */ +static const unsigned int pwm_f_z_pins[] = { GPIOZ_12 }; +static const unsigned int pwm_f_a_pins[] = { GPIOA_11 }; static const unsigned int pwm_f_x_pins[] = { GPIOX_7 }; static const unsigned int pwm_f_h_pins[] = { GPIOH_5 }; @@ -618,6 +620,7 @@ static struct meson_pmx_group meson_g12a_periphs_groups[] = { GROUP(tdm_c_dout2_z, 4), GROUP(tdm_c_dout3_z, 4), GROUP(mclk1_z, 4), + GROUP(pwm_f_z, 5), /* bank GPIOX */ GROUP(sdio_d0, 1), @@ -768,6 +771,7 @@ static struct meson_pmx_group meson_g12a_periphs_groups[] = { GROUP(tdm_c_dout3_a, 2), GROUP(mclk0_a, 1), GROUP(mclk1_a, 2), + GROUP(pwm_f_a, 3), }; /* uart_ao_a */ @@ -1069,7 +1073,7 @@ static const char * const pwm_e_groups[] = { }; static const char * const pwm_f_groups[] = { - "pwm_f_x", "pwm_f_h", + "pwm_f_z", "pwm_f_a", "pwm_f_x", "pwm_f_h", }; static const char * const cec_ao_a_h_groups[] = { diff --git a/drivers/pinctrl/meson/pinctrl-meson-s4.c b/drivers/pinctrl/meson/pinctrl-meson-s4.c new file mode 100644 index 000000000000..3c7358f53302 --- /dev/null +++ b/drivers/pinctrl/meson/pinctrl-meson-s4.c @@ -0,0 +1,1232 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Pin controller and GPIO driver for Amlogic Meson S4 SoC. + * + * Copyright (c) 2021 Amlogic, Inc. All rights reserved. + * Author: Qianggui Song <[email protected]> + */ + +#include <dt-bindings/gpio/meson-s4-gpio.h> +#include "pinctrl-meson.h" +#include "pinctrl-meson-axg-pmx.h" + +static const struct pinctrl_pin_desc meson_s4_periphs_pins[] = { + MESON_PIN(GPIOE_0), + MESON_PIN(GPIOE_1), + + MESON_PIN(GPIOB_0), + MESON_PIN(GPIOB_1), + MESON_PIN(GPIOB_2), + MESON_PIN(GPIOB_3), + MESON_PIN(GPIOB_4), + MESON_PIN(GPIOB_5), + MESON_PIN(GPIOB_6), + MESON_PIN(GPIOB_7), + MESON_PIN(GPIOB_8), + MESON_PIN(GPIOB_9), + MESON_PIN(GPIOB_10), + MESON_PIN(GPIOB_11), + MESON_PIN(GPIOB_12), + MESON_PIN(GPIOB_13), + + MESON_PIN(GPIOC_0), + MESON_PIN(GPIOC_1), + MESON_PIN(GPIOC_2), + MESON_PIN(GPIOC_3), + MESON_PIN(GPIOC_4), + MESON_PIN(GPIOC_5), + MESON_PIN(GPIOC_6), + MESON_PIN(GPIOC_7), + + MESON_PIN(GPIOD_0), + MESON_PIN(GPIOD_1), + MESON_PIN(GPIOD_2), + MESON_PIN(GPIOD_3), + MESON_PIN(GPIOD_4), + MESON_PIN(GPIOD_5), + MESON_PIN(GPIOD_6), + MESON_PIN(GPIOD_7), + MESON_PIN(GPIOD_8), + MESON_PIN(GPIOD_9), + MESON_PIN(GPIOD_10), + MESON_PIN(GPIOD_11), + + MESON_PIN(GPIOH_0), + MESON_PIN(GPIOH_1), + MESON_PIN(GPIOH_2), + MESON_PIN(GPIOH_3), + MESON_PIN(GPIOH_4), + MESON_PIN(GPIOH_5), + MESON_PIN(GPIOH_6), + MESON_PIN(GPIOH_7), + MESON_PIN(GPIOH_8), + MESON_PIN(GPIOH_9), + MESON_PIN(GPIOH_10), + MESON_PIN(GPIOH_11), + + MESON_PIN(GPIOX_0), + MESON_PIN(GPIOX_1), + MESON_PIN(GPIOX_2), + MESON_PIN(GPIOX_3), + MESON_PIN(GPIOX_4), + MESON_PIN(GPIOX_5), + MESON_PIN(GPIOX_6), + MESON_PIN(GPIOX_7), + MESON_PIN(GPIOX_8), + MESON_PIN(GPIOX_9), + MESON_PIN(GPIOX_10), + MESON_PIN(GPIOX_11), + MESON_PIN(GPIOX_12), + MESON_PIN(GPIOX_13), + MESON_PIN(GPIOX_14), + MESON_PIN(GPIOX_15), + MESON_PIN(GPIOX_16), + MESON_PIN(GPIOX_17), + MESON_PIN(GPIOX_18), + MESON_PIN(GPIOX_19), + + MESON_PIN(GPIOZ_0), + MESON_PIN(GPIOZ_1), + MESON_PIN(GPIOZ_2), + MESON_PIN(GPIOZ_3), + MESON_PIN(GPIOZ_4), + MESON_PIN(GPIOZ_5), + MESON_PIN(GPIOZ_6), + MESON_PIN(GPIOZ_7), + MESON_PIN(GPIOZ_8), + MESON_PIN(GPIOZ_9), + MESON_PIN(GPIOZ_10), + MESON_PIN(GPIOZ_11), + MESON_PIN(GPIOZ_12), + + MESON_PIN(GPIO_TEST_N), +}; + +/* BANK E func1 */ +static const unsigned int i2c0_sda_pins[] = { GPIOE_0 }; +static const unsigned int i2c0_scl_pins[] = { GPIOE_1 }; + +/* BANK E func2 */ +static const unsigned int uart_b_tx_e_pins[] = { GPIOE_0 }; +static const unsigned int uart_b_rx_e_pins[] = { GPIOE_1 }; + +/* BANK E func3 */ +static const unsigned int pwm_h_pins[] = { GPIOE_0 }; +static const unsigned int pwm_j_pins[] = { GPIOE_1 }; + +/* BANK B func1 */ +static const unsigned int emmc_nand_d0_pins[] = { GPIOB_0 }; +static const unsigned int emmc_nand_d1_pins[] = { GPIOB_1 }; +static const unsigned int emmc_nand_d2_pins[] = { GPIOB_2 }; +static const unsigned int emmc_nand_d3_pins[] = { GPIOB_3 }; +static const unsigned int emmc_nand_d4_pins[] = { GPIOB_4 }; +static const unsigned int emmc_nand_d5_pins[] = { GPIOB_5 }; +static const unsigned int emmc_nand_d6_pins[] = { GPIOB_6 }; +static const unsigned int emmc_nand_d7_pins[] = { GPIOB_7 }; +static const unsigned int emmc_clk_pins[] = { GPIOB_8 }; +static const unsigned int emmc_rst_pins[] = { GPIOB_9 }; +static const unsigned int emmc_cmd_pins[] = { GPIOB_10 }; +static const unsigned int emmc_nand_ds_pins[] = { GPIOB_11 }; + +/* Bank B func2 */ +static const unsigned int nand_wen_clk_pins[] = { GPIOB_8 }; +static const unsigned int nand_ale_pins[] = { GPIOB_9 }; +static const unsigned int nand_ren_wr_pins[] = { GPIOB_10 }; +static const unsigned int nand_cle_pins[] = { GPIOB_11 }; +static const unsigned int nand_ce0_pins[] = { GPIOB_12 }; + +/* Bank B func3 */ +static const unsigned int spif_hold_pins[] = { GPIOB_3 }; +static const unsigned int spif_mo_pins[] = { GPIOB_4 }; +static const unsigned int spif_mi_pins[] = { GPIOB_5 }; +static const unsigned int spif_clk_pins[] = { GPIOB_6 }; +static const unsigned int spif_wp_pins[] = { GPIOB_7 }; +static const unsigned int spif_cs_pins[] = { GPIOB_13 }; + +/* Bank C func1 */ +static const unsigned int sdcard_d0_c_pins[] = { GPIOC_0 }; +static const unsigned int sdcard_d1_c_pins[] = { GPIOC_1 }; +static const unsigned int sdcard_d2_c_pins[] = { GPIOC_2 }; +static const unsigned int sdcard_d3_c_pins[] = { GPIOC_3 }; +static const unsigned int sdcard_clk_c_pins[] = { GPIOC_4 }; +static const unsigned int sdcard_cmd_c_pins[] = { GPIOC_5 }; +static const unsigned int sdcard_cd_pins[] = { GPIOC_6 }; + +/* Bank C func2 */ +static const unsigned int jtag_2_tdo_pins[] = { GPIOC_0 }; +static const unsigned int jtag_2_tdi_pins[] = { GPIOC_1 }; +static const unsigned int uart_b_rx_c_pins[] = { GPIOC_2 }; +static const unsigned int uart_b_tx_c_pins[] = { GPIOC_3 }; +static const unsigned int jtag_2_clk_pins[] = { GPIOC_4 }; +static const unsigned int jtag_2_tms_pins[] = { GPIOC_5 }; +static const unsigned int i2c1_sda_c_pins[] = { GPIOC_6 }; +static const unsigned int i2c1_scl_c_pins[] = { GPIOC_7 }; + +/* Bank C func3 */ +static const unsigned int pdm_din1_c_pins[] = { GPIOC_0 }; +static const unsigned int pdm_din0_c_pins[] = { GPIOC_1 }; +static const unsigned int i2c4_sda_c_pins[] = { GPIOC_2 }; +static const unsigned int i2c4_scl_c_pins[] = { GPIOC_3 }; +static const unsigned int pdm_dclk_c_pins[] = { GPIOC_4 }; +static const unsigned int iso7816_clk_c_pins[] = { GPIOC_5 }; +static const unsigned int iso7816_data_c_pins[] = { GPIOC_6 }; + +/* Bank C func4 */ +static const unsigned int tdm_d2_c_pins[] = { GPIOC_0 }; +static const unsigned int tdm_d3_c_pins[] = { GPIOC_1 }; +static const unsigned int tdm_fs1_c_pins[] = { GPIOC_2 }; +static const unsigned int tdm_sclk1_c_pins[] = { GPIOC_3 }; +static const unsigned int mclk_1_c_pins[] = { GPIOC_4 }; +static const unsigned int tdm_d4_c_pins[] = { GPIOC_5 }; +static const unsigned int tdm_d5_c_pins[] = { GPIOC_6 }; + +/* Bank D func1 */ +static const unsigned int uart_b_tx_d_pins[] = { GPIOD_0 }; +static const unsigned int uart_b_rx_d_pins[] = { GPIOD_1 }; +static const unsigned int uart_b_cts_d_pins[] = { GPIOD_2 }; +static const unsigned int uart_b_rts_d_pins[] = { GPIOD_3 }; +static const unsigned int remote_out_pins[] = { GPIOD_4 }; +static const unsigned int remote_in_pins[] = { GPIOD_5 }; +static const unsigned int jtag_1_clk_pins[] = { GPIOD_6 }; +static const unsigned int jtag_1_tms_pins[] = { GPIOD_7 }; +static const unsigned int jtag_1_tdi_pins[] = { GPIOD_8 }; +static const unsigned int jtag_1_tdo_pins[] = { GPIOD_9 }; +static const unsigned int clk12_24_pins[] = { GPIOD_10 }; +static const unsigned int pwm_g_hiz_pins[] = { GPIOD_11 }; + +/* Bank D func2 */ +static const unsigned int i2c4_sda_d_pins[] = { GPIOD_2 }; +static const unsigned int i2c4_scl_d_pins[] = { GPIOD_3 }; +static const unsigned int mclk_1_d_pins[] = { GPIOD_4 }; +static const unsigned int tdm_sclk1_d_pins[] = { GPIOD_6 }; +static const unsigned int tdm_fs1_d_pins[] = { GPIOD_7 }; +static const unsigned int tdm_d4_d_pins[] = { GPIOD_8 }; +static const unsigned int tdm_d3_d_pins[] = { GPIOD_9 }; +static const unsigned int tdm_d2_d_pins[] = { GPIOD_10 }; +static const unsigned int pwm_g_d_pins[] = { GPIOD_11 }; + +/* Bank D func3 */ +static const unsigned int uart_c_tx_pins[] = { GPIOD_2 }; +static const unsigned int uart_c_rx_pins[] = { GPIOD_3 }; +static const unsigned int pwm_b_d_pins[] = { GPIOD_4 }; +static const unsigned int pwm_a_d_pins[] = { GPIOD_6 }; +static const unsigned int pwm_c_d_pins[] = { GPIOD_7 }; +static const unsigned int pwm_d_d_pins[] = { GPIOD_8 }; +static const unsigned int pwm_i_d_pins[] = { GPIOD_9 }; + +/* Bank D func4 */ +static const unsigned int clk_32k_in_pins[] = { GPIOD_2 }; +static const unsigned int pwm_b_hiz_pins[] = { GPIOD_4 }; +static const unsigned int pwm_a_hiz_pins[] = { GPIOD_6 }; +static const unsigned int pwm_c_hiz_pins[] = { GPIOD_7 }; +static const unsigned int pdm_dclk_d_pins[] = { GPIOD_8 }; +static const unsigned int pdm_din0_d_pins[] = { GPIOD_9 }; +static const unsigned int pdm_din1_d_pins[] = { GPIOD_10 }; + +/* Bank D func5 */ +static const unsigned int mic_mute_en_pins[] = { GPIOD_2 }; +static const unsigned int mic_mute_key_pins[] = { GPIOD_3 }; +static const unsigned int i2c1_sda_d_pins[] = { GPIOD_6 }; +static const unsigned int i2c1_scl_d_pins[] = { GPIOD_7 }; +static const unsigned int i2c2_sda_d_pins[] = { GPIOD_10 }; +static const unsigned int i2c2_scl_d_pins[] = { GPIOD_11 }; + +/* Bank D func6 */ +static const unsigned int gen_clk_d_pins[] = { GPIOD_10 }; +static const unsigned int tsin_b_clk_c_pins[] = { GPIOD_6 }; +static const unsigned int tsin_b_sop_c_pins[] = { GPIOD_7 }; +static const unsigned int tsin_b_valid_c_pins[] = { GPIOD_8 }; +static const unsigned int tsin_b_d0_c_pins[] = { GPIOD_9 }; + +/* Bank H func1 */ +static const unsigned int hdmitx_sda_pins[] = { GPIOH_0 }; +static const unsigned int hdmitx_sck_pins[] = { GPIOH_1 }; +static const unsigned int hdmitx_hpd_in_pins[] = { GPIOH_2 }; +static const unsigned int ao_cec_a_pins[] = { GPIOH_3 }; +static const unsigned int spdif_out_h_pins[] = { GPIOH_4 }; +static const unsigned int spdif_in_pins[] = { GPIOH_5 }; +static const unsigned int i2c1_sda_h_pins[] = { GPIOH_6 }; +static const unsigned int i2c1_scl_h_pins[] = { GPIOH_7 }; +static const unsigned int i2c2_sda_h8_pins[] = { GPIOH_8 }; +static const unsigned int i2c2_scl_h9_pins[] = { GPIOH_9 }; +static const unsigned int eth_link_led_pins[] = { GPIOH_10 }; +static const unsigned int eth_act_led_pins[] = { GPIOH_11 }; + +/* Bank H func2 */ +static const unsigned int i2c2_sda_h0_pins[] = { GPIOH_0 }; +static const unsigned int i2c2_scl_h1_pins[] = { GPIOH_1 }; +static const unsigned int ao_cec_b_pins[] = { GPIOH_3 }; +static const unsigned int uart_d_tx_h_pins[] = { GPIOH_4 }; +static const unsigned int uart_d_rx_h_pins[] = { GPIOH_5 }; +static const unsigned int uart_d_cts_h_pins[] = { GPIOH_6 }; +static const unsigned int uart_d_rts_h_pins[] = { GPIOH_7 }; +static const unsigned int iso7816_clk_h_pins[] = { GPIOH_8 }; +static const unsigned int iso7816_data_h_pins[] = { GPIOH_9 }; +static const unsigned int uart_e_tx_h_pins[] = { GPIOH_10 }; +static const unsigned int uart_e_rx_h_pins[] = { GPIOH_11 }; + +/* Bank H func3 */ +static const unsigned int pwm_d_h_pins[] = { GPIOH_6 }; +static const unsigned int pwm_i_h_pins[] = { GPIOH_7 }; +static const unsigned int pdm_dclk_h_pins[] = { GPIOH_8 }; +static const unsigned int pdm_din0_h_pins[] = { GPIOH_9 }; +static const unsigned int pdm_din1_h_pins[] = { GPIOH_10 }; + +/* Bank H func4 */ +static const unsigned int mclk_1_h_pins[] = { GPIOH_4 }; +static const unsigned int tdm_sclk1_h_pins[] = { GPIOH_5 }; +static const unsigned int tdm_fs1_h_pins[] = { GPIOH_6 }; +static const unsigned int tdm_d2_h_pins[] = { GPIOH_7 }; +static const unsigned int tdm_d3_h_pins[] = { GPIOH_8 }; +static const unsigned int tdm_d4_h_pins[] = { GPIOH_9 }; + +/* Bank H func5 */ +static const unsigned int spi_a_miso_h_pins[] = { GPIOH_4 }; +static const unsigned int spi_a_mosi_h_pins[] = { GPIOH_5 }; +static const unsigned int spi_a_clk_h_pins[] = { GPIOH_6 }; +static const unsigned int spi_a_ss0_h_pins[] = { GPIOH_7 }; + +/* Bank H func6 */ +static const unsigned int gen_clk_h_pins[] = { GPIOH_11 }; +static const unsigned int tsin_b1_clk_pins[] = { GPIOH_4 }; +static const unsigned int tsin_b1_sop_pins[] = { GPIOH_5 }; +static const unsigned int tsin_b1_valid_pins[] = { GPIOH_6 }; +static const unsigned int tsin_b1_d0_pins[] = { GPIOH_7 }; + +/* Bank X func1 */ +static const unsigned int sdio_d0_pins[] = { GPIOX_0 }; +static const unsigned int sdio_d1_pins[] = { GPIOX_1 }; +static const unsigned int sdio_d2_pins[] = { GPIOX_2 }; +static const unsigned int sdio_d3_pins[] = { GPIOX_3 }; +static const unsigned int sdio_clk_pins[] = { GPIOX_4 }; +static const unsigned int sdio_cmd_pins[] = { GPIOX_5 }; +static const unsigned int pwm_a_x_pins[] = { GPIOX_6 }; +static const unsigned int pwm_f_x_pins[] = { GPIOX_7 }; +static const unsigned int tdm_d1_pins[] = { GPIOX_8 }; +static const unsigned int tdm_d0_pins[] = { GPIOX_9 }; +static const unsigned int tdm_fs0_pins[] = { GPIOX_10 }; +static const unsigned int tdm_sclk0_pins[] = { GPIOX_11 }; +static const unsigned int uart_a_tx_pins[] = { GPIOX_12 }; +static const unsigned int uart_a_rx_pins[] = { GPIOX_13 }; +static const unsigned int uart_a_cts_pins[] = { GPIOX_14 }; +static const unsigned int uart_a_rts_pins[] = { GPIOX_15 }; +static const unsigned int pwm_e_x_pins[] = { GPIOX_16 }; +static const unsigned int i2c1_sda_x_pins[] = { GPIOX_17 }; +static const unsigned int i2c1_scl_x_pins[] = { GPIOX_18 }; +static const unsigned int pwm_b_x_pins[] = { GPIOX_19 }; + +/* Bank X func2 */ +static const unsigned int pdm_din0_x_pins[] = { GPIOX_8 }; +static const unsigned int pdm_din1_x_pins[] = { GPIOX_9 }; +static const unsigned int pdm_dclk_x_pins[] = { GPIOX_11 }; + +/* Bank X func3 */ +static const unsigned int spi_a_mosi_x_pins[] = { GPIOX_8 }; +static const unsigned int spi_a_miso_x_pins[] = { GPIOX_9 }; +static const unsigned int spi_a_ss0_x_pins[] = { GPIOX_10 }; +static const unsigned int spi_a_clk_x_pins[] = { GPIOX_11 }; + +/* Bank X func4 */ +static const unsigned int pwm_c_x_pins[] = { GPIOX_8 }; +static const unsigned int i2c_slave_scl_pins[] = { GPIOX_10 }; +static const unsigned int i2c_slave_sda_pins[] = { GPIOX_11 }; + +/* Bank X func5 */ +static const unsigned int i2c3_sda_x_pins[] = { GPIOX_10 }; +static const unsigned int i2c3_scl_x_pins[] = { GPIOX_11 }; + +/* Bank Z func1 */ +static const unsigned int tdm_fs2_pins[] = { GPIOZ_0 }; +static const unsigned int tdm_sclk2_pins[] = { GPIOZ_1 }; +static const unsigned int tdm_d4_z_pins[] = { GPIOZ_2 }; +static const unsigned int tdm_d5_z_pins[] = { GPIOZ_3 }; +static const unsigned int tdm_d6_pins[] = { GPIOZ_4 }; +static const unsigned int tdm_d7_pins[] = { GPIOZ_5 }; +static const unsigned int mclk_2_pins[] = { GPIOZ_6 }; +static const unsigned int spdif_out_z_pins[] = { GPIOZ_9 }; +static const unsigned int dtv_a_if_agc_z10_pins[] = { GPIOZ_10 }; +static const unsigned int uart_e_tx_z11_pins[] = { GPIOZ_11 }; +static const unsigned int uart_e_rx_z12_pins[] = { GPIOZ_12 }; + +/* Bank Z func2 */ +static const unsigned int tsin_a_clk_pins[] = { GPIOZ_0 }; +static const unsigned int tsin_a_sop_pins[] = { GPIOZ_1 }; +static const unsigned int tsin_a_valid_pins[] = { GPIOZ_2 }; +static const unsigned int tsin_a_din0_pins[] = { GPIOZ_3 }; +static const unsigned int dtv_a_if_agc_z6_pins[] = { GPIOZ_6 }; +static const unsigned int dtv_b_if_agc_pins[] = { GPIOZ_7 }; +static const unsigned int i2c3_sda_z_pins[] = { GPIOZ_8 }; +static const unsigned int i2c3_scl_z_pins[] = { GPIOZ_9 }; +static const unsigned int dtv_a_rf_agc_pins[] = { GPIOZ_10 }; +static const unsigned int dtv_b_rf_agc_pins[] = { GPIOZ_11 }; + +/* Bank Z func3 */ +static const unsigned int sdcard_d0_z_pins[] = { GPIOZ_0 }; +static const unsigned int sdcard_d1_z_pins[] = { GPIOZ_1 }; +static const unsigned int sdcard_d2_z_pins[] = { GPIOZ_2 }; +static const unsigned int sdcard_d3_z_pins[] = { GPIOZ_3 }; +static const unsigned int sdcard_clk_z_pins[] = { GPIOZ_4 }; +static const unsigned int sdcard_cmd_z_pins[] = { GPIOZ_5 }; +static const unsigned int uart_e_tx_z8_pins[] = { GPIOZ_8 }; +static const unsigned int uart_e_rx_z9_pins[] = { GPIOZ_9 }; +static const unsigned int pdm_din1_z_pins[] = { GPIOZ_10 }; +static const unsigned int pdm_din0_z_pins[] = { GPIOZ_11 }; +static const unsigned int pdm_dclk_z_pins[] = { GPIOZ_12 }; + +/* Bank Z func4 */ +static const unsigned int spi_a_miso_z_pins[] = { GPIOZ_0 }; +static const unsigned int spi_a_mosi_z_pins[] = { GPIOZ_1 }; +static const unsigned int spi_a_clk_z_pins[] = { GPIOZ_2 }; +static const unsigned int spi_a_ss0_z_pins[] = { GPIOZ_3 }; +static const unsigned int spi_a_ss1_z_pins[] = { GPIOZ_4 }; +static const unsigned int spi_a_ss2_z_pins[] = { GPIOZ_5 }; +static const unsigned int i2c4_scl_z_pins[] = { GPIOZ_11 }; +static const unsigned int i2c4_sda_z_pins[] = { GPIOZ_12 }; + +/* Bank Z func5 */ +static const unsigned int uart_d_tx_z_pins[] = { GPIOZ_0 }; +static const unsigned int uart_d_rx_z_pins[] = { GPIOZ_1 }; +static const unsigned int uart_d_cts_z_pins[] = { GPIOZ_2 }; +static const unsigned int uart_d_rts_z_pins[] = { GPIOZ_3 }; +static const unsigned int pwm_g_z_pins[] = { GPIOZ_4 }; +static const unsigned int pwm_f_z_pins[] = { GPIOZ_5 }; +static const unsigned int pwm_e_z_pins[] = { GPIOZ_6 }; +static const unsigned int tsin_b_clk_z_pins[] = { GPIOZ_7 }; +static const unsigned int tsin_b_sop_z_pins[] = { GPIOZ_10 }; +static const unsigned int tsin_b_valid_z_pins[] = { GPIOZ_11 }; +static const unsigned int tsin_b_d0_z_pins[] = { GPIOZ_12 }; + +/* Bank Z func6 */ +static const unsigned int s2_demod_gpio7_pins[] = { GPIOZ_0 }; +static const unsigned int s2_demod_gpio6_pins[] = { GPIOZ_1 }; +static const unsigned int s2_demod_gpio5_pins[] = { GPIOZ_2 }; +static const unsigned int s2_demod_gpio4_pins[] = { GPIOZ_3 }; +static const unsigned int s2_demod_gpio3_pins[] = { GPIOZ_4 }; +static const unsigned int s2_demod_gpio2_pins[] = { GPIOZ_5 }; +static const unsigned int diseqc_out_pins[] = { GPIOZ_7 }; +static const unsigned int s2_demod_gpio1_pins[] = { GPIOZ_8 }; +static const unsigned int s2_demod_gpio0_pins[] = { GPIOZ_12 }; + +/* Bank Z func7 */ +static const unsigned int gen_clk_z9_pins[] = { GPIOZ_9 }; +static const unsigned int gen_clk_z12_pins[] = { GPIOZ_12 }; + +static struct meson_pmx_group meson_s4_periphs_groups[] = { + GPIO_GROUP(GPIOE_0), + GPIO_GROUP(GPIOE_1), + + GPIO_GROUP(GPIOB_0), + GPIO_GROUP(GPIOB_1), + GPIO_GROUP(GPIOB_2), + GPIO_GROUP(GPIOB_3), + GPIO_GROUP(GPIOB_4), + GPIO_GROUP(GPIOB_5), + GPIO_GROUP(GPIOB_6), + GPIO_GROUP(GPIOB_7), + GPIO_GROUP(GPIOB_8), + GPIO_GROUP(GPIOB_9), + GPIO_GROUP(GPIOB_10), + GPIO_GROUP(GPIOB_11), + GPIO_GROUP(GPIOB_12), + GPIO_GROUP(GPIOB_13), + + GPIO_GROUP(GPIOC_0), + GPIO_GROUP(GPIOC_1), + GPIO_GROUP(GPIOC_2), + GPIO_GROUP(GPIOC_3), + GPIO_GROUP(GPIOC_4), + GPIO_GROUP(GPIOC_5), + GPIO_GROUP(GPIOC_6), + GPIO_GROUP(GPIOC_7), + + GPIO_GROUP(GPIOD_0), + GPIO_GROUP(GPIOD_1), + GPIO_GROUP(GPIOD_2), + GPIO_GROUP(GPIOD_3), + GPIO_GROUP(GPIOD_4), + GPIO_GROUP(GPIOD_5), + GPIO_GROUP(GPIOD_6), + GPIO_GROUP(GPIOD_7), + GPIO_GROUP(GPIOD_8), + GPIO_GROUP(GPIOD_9), + GPIO_GROUP(GPIOD_10), + GPIO_GROUP(GPIOD_11), + + GPIO_GROUP(GPIOH_0), + GPIO_GROUP(GPIOH_1), + GPIO_GROUP(GPIOH_2), + GPIO_GROUP(GPIOH_3), + GPIO_GROUP(GPIOH_4), + GPIO_GROUP(GPIOH_5), + GPIO_GROUP(GPIOH_6), + GPIO_GROUP(GPIOH_7), + GPIO_GROUP(GPIOH_8), + GPIO_GROUP(GPIOH_9), + GPIO_GROUP(GPIOH_10), + GPIO_GROUP(GPIOH_11), + + GPIO_GROUP(GPIOX_0), + GPIO_GROUP(GPIOX_1), + GPIO_GROUP(GPIOX_2), + GPIO_GROUP(GPIOX_3), + GPIO_GROUP(GPIOX_4), + GPIO_GROUP(GPIOX_5), + GPIO_GROUP(GPIOX_6), + GPIO_GROUP(GPIOX_7), + GPIO_GROUP(GPIOX_8), + GPIO_GROUP(GPIOX_9), + GPIO_GROUP(GPIOX_10), + GPIO_GROUP(GPIOX_11), + GPIO_GROUP(GPIOX_12), + GPIO_GROUP(GPIOX_13), + GPIO_GROUP(GPIOX_14), + GPIO_GROUP(GPIOX_15), + GPIO_GROUP(GPIOX_16), + GPIO_GROUP(GPIOX_17), + GPIO_GROUP(GPIOX_18), + GPIO_GROUP(GPIOX_19), + + GPIO_GROUP(GPIOZ_0), + GPIO_GROUP(GPIOZ_1), + GPIO_GROUP(GPIOZ_2), + GPIO_GROUP(GPIOZ_3), + GPIO_GROUP(GPIOZ_4), + GPIO_GROUP(GPIOZ_5), + GPIO_GROUP(GPIOZ_6), + GPIO_GROUP(GPIOZ_7), + GPIO_GROUP(GPIOZ_8), + GPIO_GROUP(GPIOZ_9), + GPIO_GROUP(GPIOZ_10), + GPIO_GROUP(GPIOZ_11), + GPIO_GROUP(GPIOZ_12), + + GPIO_GROUP(GPIO_TEST_N), + + /* BANK E func1 */ + GROUP(i2c0_sda, 1), + GROUP(i2c0_scl, 1), + + /* BANK E func2 */ + GROUP(uart_b_tx_e, 2), + GROUP(uart_b_rx_e, 2), + + /* BANK E func3 */ + GROUP(pwm_h, 3), + GROUP(pwm_j, 3), + + /* BANK B func1 */ + GROUP(emmc_nand_d0, 1), + GROUP(emmc_nand_d1, 1), + GROUP(emmc_nand_d2, 1), + GROUP(emmc_nand_d3, 1), + GROUP(emmc_nand_d4, 1), + GROUP(emmc_nand_d5, 1), + GROUP(emmc_nand_d6, 1), + GROUP(emmc_nand_d7, 1), + GROUP(emmc_clk, 1), + GROUP(emmc_rst, 1), + GROUP(emmc_cmd, 1), + GROUP(emmc_nand_ds, 1), + + /* Bank B func2 */ + GROUP(nand_wen_clk, 2), + GROUP(nand_ale, 2), + GROUP(nand_ren_wr, 2), + GROUP(nand_cle, 2), + GROUP(nand_ce0, 2), + + /* Bank B func3 */ + GROUP(spif_hold, 3), + GROUP(spif_mo, 3), + GROUP(spif_mi, 3), + GROUP(spif_clk, 3), + GROUP(spif_wp, 3), + GROUP(spif_cs, 3), + + /* Bank C func1 */ + GROUP(sdcard_d0_c, 1), + GROUP(sdcard_d1_c, 1), + GROUP(sdcard_d2_c, 1), + GROUP(sdcard_d3_c, 1), + GROUP(sdcard_clk_c, 1), + GROUP(sdcard_cmd_c, 1), + GROUP(sdcard_cd, 1), + + /* Bank C func2 */ + GROUP(jtag_2_tdo, 2), + GROUP(jtag_2_tdi, 2), + GROUP(uart_b_rx_c, 2), + GROUP(uart_b_tx_c, 2), + GROUP(jtag_2_clk, 2), + GROUP(jtag_2_tms, 2), + GROUP(i2c1_sda_c, 2), + GROUP(i2c1_scl_c, 2), + + /* Bank C func3 */ + GROUP(pdm_din1_c, 3), + GROUP(pdm_din0_c, 3), + GROUP(i2c4_sda_c, 3), + GROUP(i2c4_scl_c, 3), + GROUP(pdm_dclk_c, 3), + GROUP(iso7816_clk_c, 3), + GROUP(iso7816_data_c, 3), + + /* Bank C func4 */ + GROUP(tdm_d2_c, 4), + GROUP(tdm_d3_c, 4), + GROUP(tdm_fs1_c, 4), + GROUP(mclk_1_c, 4), + GROUP(tdm_d4_c, 4), + GROUP(tdm_d5_c, 4), + + /* Bank D func1 */ + GROUP(uart_b_tx_d, 1), + GROUP(uart_b_rx_d, 1), + GROUP(uart_b_cts_d, 1), + GROUP(uart_b_rts_d, 1), + GROUP(remote_out, 1), + GROUP(remote_in, 1), + GROUP(jtag_1_clk, 1), + GROUP(jtag_1_tms, 1), + GROUP(jtag_1_tdi, 1), + GROUP(jtag_1_tdo, 1), + GROUP(clk12_24, 1), + GROUP(pwm_g_hiz, 1), + + /* Bank D func2 */ + GROUP(i2c4_sda_d, 2), + GROUP(i2c4_scl_d, 2), + GROUP(mclk_1_d, 2), + GROUP(tdm_sclk1_d, 2), + GROUP(tdm_fs1_d, 2), + GROUP(tdm_d4_d, 2), + GROUP(tdm_d3_d, 2), + GROUP(tdm_d2_d, 2), + GROUP(pwm_g_d, 2), + + /* Bank D func3 */ + GROUP(uart_c_tx, 3), + GROUP(uart_c_rx, 3), + GROUP(pwm_b_d, 3), + GROUP(pwm_a_d, 3), + GROUP(pwm_c_d, 3), + GROUP(pwm_d_d, 3), + GROUP(pwm_i_d, 3), + + /* Bank D func4 */ + GROUP(clk_32k_in, 4), + GROUP(pwm_b_hiz, 4), + GROUP(pwm_a_hiz, 4), + GROUP(pwm_c_hiz, 4), + GROUP(pdm_dclk_d, 4), + GROUP(pdm_din0_d, 4), + GROUP(pdm_din1_d, 4), + + /* Bank D func5 */ + GROUP(mic_mute_en, 5), + GROUP(mic_mute_key, 5), + GROUP(i2c1_sda_d, 5), + GROUP(i2c1_scl_d, 5), + GROUP(i2c2_sda_d, 5), + GROUP(i2c2_scl_d, 5), + + /* Bank D func6 */ + GROUP(gen_clk_d, 6), + GROUP(tsin_b_clk_c, 6), + GROUP(tsin_b_sop_c, 6), + GROUP(tsin_b_valid_c, 6), + GROUP(tsin_b_d0_c, 6), + + /* Bank H func1 */ + GROUP(hdmitx_sda, 1), + GROUP(hdmitx_sck, 1), + GROUP(hdmitx_hpd_in, 1), + GROUP(ao_cec_a, 1), + GROUP(spdif_out_h, 1), + GROUP(spdif_in, 1), + GROUP(i2c1_sda_h, 1), + GROUP(i2c1_scl_h, 1), + GROUP(i2c2_sda_h8, 1), + GROUP(i2c2_scl_h9, 1), + GROUP(eth_link_led, 1), + GROUP(eth_act_led, 1), + + /* Bank H func2 */ + GROUP(i2c2_sda_h0, 2), + GROUP(i2c2_scl_h1, 2), + GROUP(ao_cec_b, 2), + GROUP(uart_d_tx_h, 2), + GROUP(uart_d_rx_h, 2), + GROUP(uart_d_cts_h, 2), + GROUP(uart_d_rts_h, 2), + GROUP(iso7816_clk_h, 2), + GROUP(iso7816_data_h, 2), + GROUP(uart_e_tx_h, 2), + GROUP(uart_e_rx_h, 2), + + /* Bank H func3 */ + GROUP(pwm_d_h, 3), + GROUP(pwm_i_h, 3), + GROUP(pdm_dclk_h, 3), + GROUP(pdm_din0_h, 3), + GROUP(pdm_din1_h, 3), + + /* Bank H func4 */ + GROUP(mclk_1_h, 4), + GROUP(tdm_sclk1_h, 4), + GROUP(tdm_fs1_h, 4), + GROUP(tdm_d2_h, 4), + GROUP(tdm_d3_h, 4), + GROUP(tdm_d4_h, 4), + + /* Bank H func5 */ + GROUP(spi_a_miso_h, 5), + GROUP(spi_a_mosi_h, 5), + GROUP(spi_a_clk_h, 5), + GROUP(spi_a_ss0_h, 5), + + /* Bank H func6 */ + GROUP(gen_clk_h, 6), + GROUP(tsin_b1_clk, 6), + GROUP(tsin_b1_sop, 6), + GROUP(tsin_b1_valid, 6), + GROUP(tsin_b1_d0, 6), + + /* Bank X func1 */ + GROUP(sdio_d0, 1), + GROUP(sdio_d1, 1), + GROUP(sdio_d2, 1), + GROUP(sdio_d3, 1), + GROUP(sdio_clk, 1), + GROUP(sdio_cmd, 1), + GROUP(pwm_a_x, 1), + GROUP(pwm_f_x, 1), + GROUP(tdm_d1, 1), + GROUP(tdm_d0, 1), + GROUP(tdm_fs0, 1), + GROUP(tdm_sclk0, 1), + GROUP(uart_a_tx, 1), + GROUP(uart_a_rx, 1), + GROUP(uart_a_cts, 1), + GROUP(uart_a_rts, 1), + GROUP(pwm_e_x, 1), + GROUP(i2c1_sda_x, 1), + GROUP(i2c1_scl_x, 1), + GROUP(pwm_b_x, 1), + + /* Bank X func2 */ + GROUP(pdm_din0_x, 2), + GROUP(pdm_din1_x, 2), + GROUP(pdm_dclk_x, 2), + + /* Bank X func3 */ + GROUP(spi_a_mosi_x, 3), + GROUP(spi_a_miso_x, 3), + GROUP(spi_a_ss0_x, 3), + GROUP(spi_a_clk_x, 3), + + /* Bank X func4 */ + GROUP(pwm_c_x, 4), + GROUP(i2c_slave_scl, 4), + GROUP(i2c_slave_sda, 4), + + /* Bank X func5 */ + GROUP(i2c3_sda_x, 5), + GROUP(i2c3_scl_x, 5), + + /* Bank Z func1 */ + GROUP(tdm_fs2, 1), + GROUP(tdm_sclk2, 1), + GROUP(tdm_d4_z, 1), + GROUP(tdm_d5_z, 1), + GROUP(tdm_d6, 1), + GROUP(tdm_d7, 1), + GROUP(mclk_2, 1), + GROUP(spdif_out_z, 1), + GROUP(dtv_a_if_agc_z10, 1), + GROUP(uart_e_tx_z11, 1), + GROUP(uart_e_rx_z12, 1), + + /* Bank Z func2 */ + GROUP(tsin_a_clk, 2), + GROUP(tsin_a_sop, 2), + GROUP(tsin_a_valid, 2), + GROUP(tsin_a_din0, 2), + GROUP(dtv_a_if_agc_z6, 2), + GROUP(dtv_b_if_agc, 2), + GROUP(i2c3_sda_z, 2), + GROUP(i2c3_scl_z, 2), + GROUP(dtv_a_rf_agc, 2), + GROUP(dtv_b_rf_agc, 2), + + /* Bank Z func3 */ + GROUP(sdcard_d0_z, 3), + GROUP(sdcard_d1_z, 3), + GROUP(sdcard_d2_z, 3), + GROUP(sdcard_d3_z, 3), + GROUP(sdcard_clk_z, 3), + GROUP(sdcard_cmd_z, 3), + GROUP(uart_e_tx_z8, 3), + GROUP(uart_e_rx_z9, 3), + GROUP(pdm_din1_z, 3), + GROUP(pdm_din0_z, 3), + GROUP(pdm_dclk_z, 3), + + /* Bank Z func4 */ + GROUP(spi_a_miso_z, 4), + GROUP(spi_a_mosi_z, 4), + GROUP(spi_a_clk_z, 4), + GROUP(spi_a_ss0_z, 4), + GROUP(spi_a_ss1_z, 4), + GROUP(spi_a_ss2_z, 4), + GROUP(i2c4_scl_z, 4), + GROUP(i2c4_sda_z, 4), + + /* Bank Z func5 */ + GROUP(uart_d_tx_z, 5), + GROUP(uart_d_rx_z, 5), + GROUP(uart_d_cts_z, 5), + GROUP(uart_d_rts_z, 5), + GROUP(pwm_g_z, 5), + GROUP(pwm_f_z, 5), + GROUP(pwm_e_z, 5), + GROUP(tsin_b_clk_z, 5), + GROUP(tsin_b_sop_z, 5), + GROUP(tsin_b_valid_z, 5), + GROUP(tsin_b_d0_z, 5), + + /* Bank Z func6 */ + GROUP(s2_demod_gpio7, 6), + GROUP(s2_demod_gpio6, 6), + GROUP(s2_demod_gpio5, 6), + GROUP(s2_demod_gpio4, 6), + GROUP(s2_demod_gpio3, 6), + GROUP(s2_demod_gpio2, 6), + GROUP(diseqc_out, 6), + GROUP(s2_demod_gpio1, 6), + GROUP(s2_demod_gpio0, 6), + + /* Bank Z func7 */ + GROUP(gen_clk_z9, 7), + GROUP(gen_clk_z12, 7), +}; + +static const char * const gpio_periphs_groups[] = { + "GPIOE_0", "GPIOE_1", + + "GPIOB_0", "GPIOB_1", "GPIOB_2", "GPIOB_3", "GPIOB_4", "GPIOB_5", + "GPIOB_6", "GPIOB_7", "GPIOB_8", "GPIOB_9", "GPIOB_10", "GPIOB_11", + "GPIOB_12", "GPIOB_13", + + "GPIOC_0", "GPIOC_1", "GPIOC_2", "GPIOC_3", "GPIOC_4", "GPIOC_5", + "GPIOC_6", "GPIOC_7", + + "GPIOD_0", "GPIOD_1", "GPIOD_2", "GPIOD_3", "GPIOD_4", "GPIOD_5", + "GPIOD_6", "GPIOD_7", "GPIOD_8", "GPIOD_9", "GPIOD_10", "GPIOD_11", + + "GPIOH_0", "GPIOH_1", "GPIOH_2", "GPIOH_3", "GPIOH_4", "GPIOH_5", + "GPIOH_6", "GPIOH_7", "GPIOH_8", "GPIOH_9", "GPIOH_10", "GPIOH_11", + + "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4", "GPIOX_5", + "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9", "GPIOX_10", "GPIOX_11", + "GPIOX_12", "GPIOX_13", "GPIOX_14", "GPIOX_15", "GPIOX_16", "GPIOX_17", + "GPIOX_18", "GPIOX_19", + + "GPIOZ_0", "GPIOZ_1", "GPIOZ_2", "GPIOZ_3", "GPIOZ_4", "GPIOZ_5", + "GPIOZ_6", "GPIOZ_7", "GPIOZ_8", "GPIOZ_9", "GPIOZ_10", + "GPIOZ_11", "GPIOZ_12", + + "GPIO_TEST_N", +}; + +static const char * const i2c0_groups[] = { + "i2c0_sda", "i2c0_scl", +}; + +static const char * const i2c1_groups[] = { + "i2c1_sda_c", "i2c1_scl_c", + "i2c1_sda_d", "i2c1_scl_d", + "i2c1_sda_h", "i2c1_scl_h", + "i2c1_sda_x", "i2c1_scl_x", +}; + +static const char * const i2c2_groups[] = { + "i2c2_sda_d", "i2c2_scl_d", + "i2c2_sda_h8", "i2c2_scl_h9", + "i2c2_sda_h0", "i2c2_scl_h1l," +}; + +static const char * const i2c3_groups[] = { + "i2c3_sda_x", "i2c3_scl_x", + "i2c3_sda_z", "i2c3_scl_z", +}; + +static const char * const i2c4_groups[] = { + "i2c4_sda_c", "i2c4_scl_c", + "i2c4_sda_d", "i2c4_scl_d", + "i2c4_scl_z", "i2c4_sda_z", +}; + +static const char * const uart_a_groups[] = { + "uart_a_tx", "uart_a_rx", "uart_a_cts", "uart_a_rts", +}; + +static const char * const uart_b_groups[] = { + "uart_b_tx_e", "uart_b_rx_e", "uart_b_rx_c", "uart_b_tx_c", + "uart_b_tx_d", "uart_b_rx_d", "uart_b_cts_d", "uart_b_rts_d", +}; + +static const char * const uart_c_groups[] = { + "uart_c_tx", "uart_c_rx", +}; + +static const char * const uart_d_groups[] = { + "uart_d_tx_h", "uart_d_rx_h", "uart_d_cts_h", "uart_d_rts_h", + "uart_d_tx_z", "uart_d_rx_z", "uart_d_cts_z", "uart_d_rts_z", +}; + +static const char * const uart_e_groups[] = { + "uart_e_tx_h", "uart_e_rx_h", "uart_e_tx_z11", "uart_e_rx_z12", + "uart_e_tx_z8", "uart_e_rx_z9", +}; + +static const char * const emmc_groups[] = { + "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", "emmc_nand_d3", + "emmc_nand_d4", "emmc_nand_d5", "emmc_nand_d6", "emmc_nand_d7", + "emmc_clk", "emmc_rst", "emmc_cmd", "emmc_nand_ds", +}; + +static const char * const nand_groups[] = { + "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", "emmc_nand_d3", + "emmc_nand_d4", "emmc_nand_d5", "emmc_nand_d6", "emmc_nand_d7", + "nand_wen_clk", "nand_ale", "nand_ren_wr", "nand_cle", "nand_ce0", +}; + +static const char * const spif_groups[] = { + "spif_hold", "spif_mo", "spif_mi", "spif_clk", "spif_wp", + "spif_cs", +}; + +static const char * const sdcard_groups[] = { + "sdcard_d0_c", "sdcard_d1_c", "sdcard_d2_c", "sdcard_d3_c", + "sdcard_clk_c", "sdcard_cmd_c", "sdcard_cd", + "sdcard_d0_z", "sdcard_d1_z", "sdcard_d2_z", "sdcard_d3_z", + "sdcard_clk_z", "sdcard_cmd_z", +}; + +static const char * const jtag_1_groups[] = { + "jtag_1_clk", "jtag_1_tms", "jtag_1_tdi", "jtag_1_tdo", +}; + +static const char * const jtag_2_groups[] = { + "jtag_2_tdo", "jtag_2_tdi", "jtag_2_clk", "jtag_2_tms", +}; + +static const char * const pdm_groups[] = { + "pdm_din1_c", "pdm_din0_c", "pdm_dclk_c", + "pdm_dclk_d", "pdm_din0_d", "pdm_din1_d", + "pdm_dclk_h", "pdm_din0_h", "pdm_din1_h", + "pdm_din0_x", "pdm_din1_x", "pdm_dclk_x", + "pdm_din1_z", "pdm_din0_z", "pdm_dclk_z", +}; + +static const char * const iso7816_groups[] = { + "iso7816_clk_c", "iso7816_data_c", + "iso7816_clk_h", "iso7816_data_h", +}; + +static const char * const tdm_groups[] = { + "tdm_d2_c", "tdm_d3_c", "tdm_fs1_c", "tdm_d4_c", "tdm_d5_c", + "tdm_fs1_d", "tdm_d4_d", "tdm_d3_d", "tdm_d2_d", "tdm_sclk1_d", + "tdm_sclk1_h", "tdm_fs1_h", "tdm_d2_h", "tdm_d3_h", "tdm_d4_h", + "tdm_d1", "tdm_d0", "tdm_fs0", "tdm_sclk0", "tdm_fs2", "tdm_sclk2", + "tdm_d4_z", "tdm_d5_z", "tdm_d6", "tdm_d7", +}; + +static const char * const mclk_1_groups[] = { + "mclk_1_c", "mclk_1_d", "mclk_1_h", "mclk_2", +}; + +static const char * const mclk_2_groups[] = { + "mclk_2", +}; + +static const char * const remote_out_groups[] = { + "remote_out", +}; + +static const char * const remote_in_groups[] = { + "remote_in", +}; + +static const char * const clk12_24_groups[] = { + "clk12_24", +}; + +static const char * const clk_32k_in_groups[] = { + "clk_32k_in", +}; + +static const char * const pwm_a_hiz_groups[] = { + "pwm_a_hiz", +}; + +static const char * const pwm_b_hiz_groups[] = { + "pwm_b_hiz", +}; + +static const char * const pwm_c_hiz_groups[] = { + "pwm_c_hiz", +}; + +static const char * const pwm_g_hiz_groups[] = { + "pwm_g_hiz", +}; + +static const char * const pwm_a_groups[] = { + "pwm_a_d", +}; + +static const char * const pwm_b_groups[] = { + "pwm_b_d", "pwm_b_x", +}; + +static const char * const pwm_c_groups[] = { + "pwm_c_d", "pwm_c_x", +}; + +static const char * const pwm_d_groups[] = { + "pwm_d_d", "pwm_d_h", +}; + +static const char * const pwm_e_groups[] = { + "pwm_e_x", "pwm_e_z", +}; + +static const char * const pwm_f_groups[] = { + "pwm_f_x", "pwm_f_z", +}; + +static const char * const pwm_g_groups[] = { + "pwm_g_d", "pwm_g_z", +}; + +static const char * const pwm_h_groups[] = { + "pwm_h", +}; + +static const char * const pwm_i_groups[] = { + "pwm_i_d", "pwm_i_h" +}; + +static const char * const pwm_j_groups[] = { + "pwm_j", +}; + +static const char * const mic_mute_groups[] = { + "mic_mute_en", "mic_mute_key", +}; + +static const char * const hdmitx_groups[] = { + "hdmitx_sda", "hdmitx_sck", "hdmitx_hpd_in", +}; + +static const char * const ao_cec_a_groups[] = { + "ao_cec_a", +}; + +static const char * const ao_cec_b_groups[] = { + "ao_cec_b", +}; + +static const char * const spdif_out_groups[] = { + "spdif_out_h", "spdif_out_z", +}; + +static const char * const spdif_in_groups[] = { + "spdif_in", +}; + +static const char * const eth_groups[] = { + "eth_link_led", "eth_act_led", +}; + +static const char * const spi_a_groups[] = { + "spi_a_miso_h", "spi_a_mosi_h", "spi_a_clk_h", "spi_a_ss0_h", + + "spi_a_mosi_x", "spi_a_miso_x", "spi_a_ss0_x", "spi_a_clk_x", + + "spi_a_miso_z", "spi_a_mosi_z", "spi_a_clk_z", "spi_a_ss0_z", + "spi_a_ss1_z", "spi_a_ss2_z", +}; + +static const char * const gen_clk_groups[] = { + "gen_clk_h", "gen_clk_z9", "gen_clk_z12", +}; + +static const char * const sdio_groups[] = { + "sdio_d0", "sdio_d1", "sdio_d2", "sdio_d3", "sdio_clk", "sdio_cmd", +}; + +static const char * const i2c_slave_groups[] = { + "i2c_slave_scl", "i2c_slave_sda", +}; + +static const char * const dtv_groups[] = { + "dtv_a_if_agc_z10", "dtv_a_if_agc_z6", "dtv_b_if_agc", + "dtv_a_rf_agc", "dtv_b_rf_agc", +}; + +static const char * const tsin_a_groups[] = { + "tsin_a_clk", "tsin_a_sop", "tsin_a_valid", "tsin_a_din0", +}; + +static const char * const tsin_b_groups[] = { + "tsin_b_clk_c", "tsin_b_sop_c", "tsin_b_valid_c", "tsin_b_d0_c", + "tsin_b_clk_z", "tsin_b_sop_z", "tsin_b_valid_z", "tsin_b_d0_z", +}; + +static const char * const tsin_b1_groups[] = { + "tsin_b1_clk", "tsin_b1_sop", "tsin_b1_valid", "tsin_b1_d0", +}; + +static const char * const diseqc_out_groups[] = { + "diseqc_out", +}; + +static const char * const s2_demod_groups[] = { + "s2_demod_gpio7", "s2_demod_gpio6", "s2_demod_gpio5", "s2_demod_gpio4", + "s2_demod_gpio3", "s2_demod_gpio2", "s2_demod_gpio1", "s2_demod_gpio0", +}; + +static struct meson_pmx_func meson_s4_periphs_functions[] = { + FUNCTION(gpio_periphs), + FUNCTION(i2c0), + FUNCTION(i2c1), + FUNCTION(i2c2), + FUNCTION(i2c3), + FUNCTION(i2c4), + FUNCTION(uart_a), + FUNCTION(uart_b), + FUNCTION(uart_c), + FUNCTION(uart_d), + FUNCTION(uart_e), + FUNCTION(emmc), + FUNCTION(nand), + FUNCTION(spif), + FUNCTION(sdcard), + FUNCTION(jtag_1), + FUNCTION(jtag_2), + FUNCTION(pdm), + FUNCTION(iso7816), + FUNCTION(tdm), + FUNCTION(mclk_1), + FUNCTION(mclk_2), + FUNCTION(remote_out), + FUNCTION(remote_in), + FUNCTION(clk12_24), + FUNCTION(clk_32k_in), + FUNCTION(pwm_a_hiz), + FUNCTION(pwm_b_hiz), + FUNCTION(pwm_c_hiz), + FUNCTION(pwm_g_hiz), + FUNCTION(pwm_a), + FUNCTION(pwm_b), + FUNCTION(pwm_c), + FUNCTION(pwm_d), + FUNCTION(pwm_e), + FUNCTION(pwm_f), + FUNCTION(pwm_g), + FUNCTION(pwm_h), + FUNCTION(pwm_i), + FUNCTION(pwm_j), + FUNCTION(mic_mute), + FUNCTION(hdmitx), + FUNCTION(ao_cec_a), + FUNCTION(ao_cec_b), + FUNCTION(spdif_out), + FUNCTION(spdif_in), + FUNCTION(eth), + FUNCTION(spi_a), + FUNCTION(gen_clk), + FUNCTION(sdio), + FUNCTION(i2c_slave), + FUNCTION(dtv), + FUNCTION(tsin_a), + FUNCTION(tsin_b), + FUNCTION(tsin_b1), + FUNCTION(diseqc_out), + FUNCTION(s2_demod), +}; + +static struct meson_bank meson_s4_periphs_banks[] = { + /* name first last irq pullen pull dir out in */ + BANK_DS("B", GPIOB_0, GPIOB_13, 0, 13, + 0x63, 0, 0x64, 0, 0x62, 0, 0x61, 0, 0x60, 0, 0x67, 0), + BANK_DS("C", GPIOC_0, GPIOC_7, 14, 21, + 0x53, 0, 0x54, 0, 0x52, 0, 0x51, 0, 0x50, 0, 0x57, 0), + BANK_DS("E", GPIOE_0, GPIOE_1, 22, 23, + 0x43, 0, 0x44, 0, 0x42, 0, 0x41, 0, 0x40, 0, 0x47, 0), + BANK_DS("D", GPIOD_0, GPIOD_11, 24, 35, + 0x33, 0, 0x34, 0, 0x32, 0, 0x31, 0, 0x30, 0, 0x37, 0), + BANK_DS("H", GPIOH_0, GPIOH_11, 36, 47, + 0x23, 0, 0x24, 0, 0x22, 0, 0x21, 0, 0x20, 0, 0x27, 0), + BANK_DS("X", GPIOX_0, GPIOX_19, 48, 67, + 0x13, 0, 0x14, 0, 0x12, 0, 0x11, 0, 0x10, 0, 0x17, 0), + BANK_DS("Z", GPIOZ_0, GPIOZ_12, 68, 80, + 0x03, 0, 0x04, 0, 0x02, 0, 0x01, 0, 0x00, 0, 0x07, 0), + BANK_DS("TEST_N", GPIO_TEST_N, GPIO_TEST_N, -1, -1, + 0x83, 0, 0x84, 0, 0x82, 0, 0x81, 0, 0x80, 0, 0x87, 0), +}; + +static struct meson_pmx_bank meson_s4_periphs_pmx_banks[] = { + /*name first lask reg offset*/ + BANK_PMX("B", GPIOB_0, GPIOB_13, 0x00, 0), + BANK_PMX("C", GPIOC_0, GPIOC_7, 0x9, 0), + BANK_PMX("E", GPIOE_0, GPIOE_1, 0x12, 0), + BANK_PMX("D", GPIOD_0, GPIOD_11, 0x10, 0), + BANK_PMX("H", GPIOH_0, GPIOH_11, 0xb, 0), + BANK_PMX("X", GPIOX_0, GPIOX_19, 0x3, 0), + BANK_PMX("Z", GPIOZ_0, GPIOZ_12, 0x6, 0), + BANK_PMX("TEST_N", GPIO_TEST_N, GPIO_TEST_N, 0xf, 0) +}; + +static struct meson_axg_pmx_data meson_s4_periphs_pmx_banks_data = { + .pmx_banks = meson_s4_periphs_pmx_banks, + .num_pmx_banks = ARRAY_SIZE(meson_s4_periphs_pmx_banks), +}; + +static struct meson_pinctrl_data meson_s4_periphs_pinctrl_data = { + .name = "periphs-banks", + .pins = meson_s4_periphs_pins, + .groups = meson_s4_periphs_groups, + .funcs = meson_s4_periphs_functions, + .banks = meson_s4_periphs_banks, + .num_pins = ARRAY_SIZE(meson_s4_periphs_pins), + .num_groups = ARRAY_SIZE(meson_s4_periphs_groups), + .num_funcs = ARRAY_SIZE(meson_s4_periphs_functions), + .num_banks = ARRAY_SIZE(meson_s4_periphs_banks), + .pmx_ops = &meson_axg_pmx_ops, + .pmx_data = &meson_s4_periphs_pmx_banks_data, + .parse_dt = &meson_a1_parse_dt_extra, +}; + +static const struct of_device_id meson_s4_pinctrl_dt_match[] = { + { + .compatible = "amlogic,meson-s4-periphs-pinctrl", + .data = &meson_s4_periphs_pinctrl_data, + }, + { } +}; +MODULE_DEVICE_TABLE(of, meson_s4_pinctrl_dt_match); + +static struct platform_driver meson_s4_pinctrl_driver = { + .probe = meson_pinctrl_probe, + .driver = { + .name = "meson-s4-pinctrl", + .of_match_table = meson_s4_pinctrl_dt_match, + }, +}; +module_platform_driver(meson_s4_pinctrl_driver); + +MODULE_LICENSE("Dual BSD/GPL"); diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c index 4d81908d6725..6656bac3f384 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c @@ -905,7 +905,7 @@ static struct npcm7xx_func npcm7xx_funcs[] = { #define DRIVE_STRENGTH_HI_SHIFT 12 #define DRIVE_STRENGTH_MASK 0x0000FF00 -#define DS(lo, hi) (((lo) << DRIVE_STRENGTH_LO_SHIFT) | \ +#define DSTR(lo, hi) (((lo) << DRIVE_STRENGTH_LO_SHIFT) | \ ((hi) << DRIVE_STRENGTH_HI_SHIFT)) #define DSLO(x) (((x) >> DRIVE_STRENGTH_LO_SHIFT) & 0xF) #define DSHI(x) (((x) >> DRIVE_STRENGTH_HI_SHIFT) & 0xF) @@ -925,31 +925,31 @@ struct npcm7xx_pincfg { static const struct npcm7xx_pincfg pincfg[] = { /* PIN FUNCTION 1 FUNCTION 2 FUNCTION 3 FLAGS */ NPCM7XX_PINCFG(0, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, 0), - NPCM7XX_PINCFG(1, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, DS(8, 12)), - NPCM7XX_PINCFG(2, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, DS(8, 12)), + NPCM7XX_PINCFG(1, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), + NPCM7XX_PINCFG(2, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), NPCM7XX_PINCFG(3, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(4, iox2, MFSEL3, 14, smb1d, I2CSEGSEL, 7, none, NONE, 0, SLEW), NPCM7XX_PINCFG(5, iox2, MFSEL3, 14, smb1d, I2CSEGSEL, 7, none, NONE, 0, SLEW), NPCM7XX_PINCFG(6, iox2, MFSEL3, 14, smb2d, I2CSEGSEL, 10, none, NONE, 0, SLEW), NPCM7XX_PINCFG(7, iox2, MFSEL3, 14, smb2d, I2CSEGSEL, 10, none, NONE, 0, SLEW), - NPCM7XX_PINCFG(8, lkgpo1, FLOCKR1, 4, none, NONE, 0, none, NONE, 0, DS(8, 12)), - NPCM7XX_PINCFG(9, lkgpo2, FLOCKR1, 8, none, NONE, 0, none, NONE, 0, DS(8, 12)), - NPCM7XX_PINCFG(10, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DS(8, 12)), - NPCM7XX_PINCFG(11, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DS(8, 12)), + NPCM7XX_PINCFG(8, lkgpo1, FLOCKR1, 4, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), + NPCM7XX_PINCFG(9, lkgpo2, FLOCKR1, 8, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), + NPCM7XX_PINCFG(10, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), + NPCM7XX_PINCFG(11, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), NPCM7XX_PINCFG(12, gspi, MFSEL1, 24, smb5b, I2CSEGSEL, 19, none, NONE, 0, SLEW), NPCM7XX_PINCFG(13, gspi, MFSEL1, 24, smb5b, I2CSEGSEL, 19, none, NONE, 0, SLEW), NPCM7XX_PINCFG(14, gspi, MFSEL1, 24, smb5c, I2CSEGSEL, 20, none, NONE, 0, SLEW), NPCM7XX_PINCFG(15, gspi, MFSEL1, 24, smb5c, I2CSEGSEL, 20, none, NONE, 0, SLEW), - NPCM7XX_PINCFG(16, lkgpo0, FLOCKR1, 0, none, NONE, 0, none, NONE, 0, DS(8, 12)), - NPCM7XX_PINCFG(17, pspi2, MFSEL3, 13, smb4den, I2CSEGSEL, 23, none, NONE, 0, DS(8, 12)), - NPCM7XX_PINCFG(18, pspi2, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, DS(8, 12)), - NPCM7XX_PINCFG(19, pspi2, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, DS(8, 12)), + NPCM7XX_PINCFG(16, lkgpo0, FLOCKR1, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), + NPCM7XX_PINCFG(17, pspi2, MFSEL3, 13, smb4den, I2CSEGSEL, 23, none, NONE, 0, DSTR(8, 12)), + NPCM7XX_PINCFG(18, pspi2, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, DSTR(8, 12)), + NPCM7XX_PINCFG(19, pspi2, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, DSTR(8, 12)), NPCM7XX_PINCFG(20, smb4c, I2CSEGSEL, 15, smb15, MFSEL3, 8, none, NONE, 0, 0), NPCM7XX_PINCFG(21, smb4c, I2CSEGSEL, 15, smb15, MFSEL3, 8, none, NONE, 0, 0), NPCM7XX_PINCFG(22, smb4d, I2CSEGSEL, 16, smb14, MFSEL3, 7, none, NONE, 0, 0), NPCM7XX_PINCFG(23, smb4d, I2CSEGSEL, 16, smb14, MFSEL3, 7, none, NONE, 0, 0), - NPCM7XX_PINCFG(24, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DS(8, 12)), - NPCM7XX_PINCFG(25, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DS(8, 12)), + NPCM7XX_PINCFG(24, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), + NPCM7XX_PINCFG(25, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), NPCM7XX_PINCFG(26, smb5, MFSEL1, 2, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(27, smb5, MFSEL1, 2, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(28, smb4, MFSEL1, 1, none, NONE, 0, none, NONE, 0, 0), @@ -965,12 +965,12 @@ static const struct npcm7xx_pincfg pincfg[] = { NPCM7XX_PINCFG(39, smb3b, I2CSEGSEL, 11, none, NONE, 0, none, NONE, 0, SLEW), NPCM7XX_PINCFG(40, smb3b, I2CSEGSEL, 11, none, NONE, 0, none, NONE, 0, SLEW), NPCM7XX_PINCFG(41, bmcuart0a, MFSEL1, 9, none, NONE, 0, none, NONE, 0, 0), - NPCM7XX_PINCFG(42, bmcuart0a, MFSEL1, 9, none, NONE, 0, none, NONE, 0, DS(2, 4) | GPO), + NPCM7XX_PINCFG(42, bmcuart0a, MFSEL1, 9, none, NONE, 0, none, NONE, 0, DSTR(2, 4) | GPO), NPCM7XX_PINCFG(43, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, bmcuart1, MFSEL3, 24, 0), NPCM7XX_PINCFG(44, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, bmcuart1, MFSEL3, 24, 0), NPCM7XX_PINCFG(45, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, 0), - NPCM7XX_PINCFG(46, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, DS(2, 8)), - NPCM7XX_PINCFG(47, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, DS(2, 8)), + NPCM7XX_PINCFG(46, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, DSTR(2, 8)), + NPCM7XX_PINCFG(47, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, DSTR(2, 8)), NPCM7XX_PINCFG(48, uart2, MFSEL1, 11, bmcuart0b, MFSEL4, 1, none, NONE, 0, GPO), NPCM7XX_PINCFG(49, uart2, MFSEL1, 11, bmcuart0b, MFSEL4, 1, none, NONE, 0, 0), NPCM7XX_PINCFG(50, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0), @@ -980,8 +980,8 @@ static const struct npcm7xx_pincfg pincfg[] = { NPCM7XX_PINCFG(54, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(55, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(56, r1err, MFSEL1, 12, none, NONE, 0, none, NONE, 0, 0), - NPCM7XX_PINCFG(57, r1md, MFSEL1, 13, none, NONE, 0, none, NONE, 0, DS(2, 4)), - NPCM7XX_PINCFG(58, r1md, MFSEL1, 13, none, NONE, 0, none, NONE, 0, DS(2, 4)), + NPCM7XX_PINCFG(57, r1md, MFSEL1, 13, none, NONE, 0, none, NONE, 0, DSTR(2, 4)), + NPCM7XX_PINCFG(58, r1md, MFSEL1, 13, none, NONE, 0, none, NONE, 0, DSTR(2, 4)), NPCM7XX_PINCFG(59, smb3d, I2CSEGSEL, 13, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(60, smb3d, I2CSEGSEL, 13, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(61, uart1, MFSEL1, 10, none, NONE, 0, none, NONE, 0, GPO), @@ -1004,19 +1004,19 @@ static const struct npcm7xx_pincfg pincfg[] = { NPCM7XX_PINCFG(77, fanin13, MFSEL2, 13, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(78, fanin14, MFSEL2, 14, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(79, fanin15, MFSEL2, 15, none, NONE, 0, none, NONE, 0, 0), - NPCM7XX_PINCFG(80, pwm0, MFSEL2, 16, none, NONE, 0, none, NONE, 0, DS(4, 8)), - NPCM7XX_PINCFG(81, pwm1, MFSEL2, 17, none, NONE, 0, none, NONE, 0, DS(4, 8)), - NPCM7XX_PINCFG(82, pwm2, MFSEL2, 18, none, NONE, 0, none, NONE, 0, DS(4, 8)), - NPCM7XX_PINCFG(83, pwm3, MFSEL2, 19, none, NONE, 0, none, NONE, 0, DS(4, 8)), - NPCM7XX_PINCFG(84, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(85, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(86, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), + NPCM7XX_PINCFG(80, pwm0, MFSEL2, 16, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), + NPCM7XX_PINCFG(81, pwm1, MFSEL2, 17, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), + NPCM7XX_PINCFG(82, pwm2, MFSEL2, 18, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), + NPCM7XX_PINCFG(83, pwm3, MFSEL2, 19, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), + NPCM7XX_PINCFG(84, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(85, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(86, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), NPCM7XX_PINCFG(87, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(88, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(89, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(90, r2err, MFSEL1, 15, none, NONE, 0, none, NONE, 0, 0), - NPCM7XX_PINCFG(91, r2md, MFSEL1, 16, none, NONE, 0, none, NONE, 0, DS(2, 4)), - NPCM7XX_PINCFG(92, r2md, MFSEL1, 16, none, NONE, 0, none, NONE, 0, DS(2, 4)), + NPCM7XX_PINCFG(91, r2md, MFSEL1, 16, none, NONE, 0, none, NONE, 0, DSTR(2, 4)), + NPCM7XX_PINCFG(92, r2md, MFSEL1, 16, none, NONE, 0, none, NONE, 0, DSTR(2, 4)), NPCM7XX_PINCFG(93, ga20kbc, MFSEL1, 17, smb5d, I2CSEGSEL, 21, none, NONE, 0, 0), NPCM7XX_PINCFG(94, ga20kbc, MFSEL1, 17, smb5d, I2CSEGSEL, 21, none, NONE, 0, 0), NPCM7XX_PINCFG(95, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, 0), @@ -1062,34 +1062,34 @@ static const struct npcm7xx_pincfg pincfg[] = { NPCM7XX_PINCFG(133, smb10, MFSEL4, 13, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(134, smb11, MFSEL4, 14, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(135, smb11, MFSEL4, 14, none, NONE, 0, none, NONE, 0, 0), - NPCM7XX_PINCFG(136, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(137, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(138, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(139, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(140, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), + NPCM7XX_PINCFG(136, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(137, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(138, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(139, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(140, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), NPCM7XX_PINCFG(141, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, 0), - NPCM7XX_PINCFG(142, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), + NPCM7XX_PINCFG(142, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), NPCM7XX_PINCFG(143, sd1, MFSEL3, 12, sd1pwr, MFSEL4, 5, none, NONE, 0, 0), - NPCM7XX_PINCFG(144, pwm4, MFSEL2, 20, none, NONE, 0, none, NONE, 0, DS(4, 8)), - NPCM7XX_PINCFG(145, pwm5, MFSEL2, 21, none, NONE, 0, none, NONE, 0, DS(4, 8)), - NPCM7XX_PINCFG(146, pwm6, MFSEL2, 22, none, NONE, 0, none, NONE, 0, DS(4, 8)), - NPCM7XX_PINCFG(147, pwm7, MFSEL2, 23, none, NONE, 0, none, NONE, 0, DS(4, 8)), - NPCM7XX_PINCFG(148, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(149, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(150, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(151, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(152, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), + NPCM7XX_PINCFG(144, pwm4, MFSEL2, 20, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), + NPCM7XX_PINCFG(145, pwm5, MFSEL2, 21, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), + NPCM7XX_PINCFG(146, pwm6, MFSEL2, 22, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), + NPCM7XX_PINCFG(147, pwm7, MFSEL2, 23, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), + NPCM7XX_PINCFG(148, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(149, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(150, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(151, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(152, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), NPCM7XX_PINCFG(153, mmcwp, FLOCKR1, 24, none, NONE, 0, none, NONE, 0, 0), /* Z1/A1 */ - NPCM7XX_PINCFG(154, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), + NPCM7XX_PINCFG(154, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), NPCM7XX_PINCFG(155, mmccd, MFSEL3, 25, mmcrst, MFSEL4, 6, none, NONE, 0, 0), /* Z1/A1 */ - NPCM7XX_PINCFG(156, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(157, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(158, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(159, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - - NPCM7XX_PINCFG(160, clkout, MFSEL1, 21, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(161, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, DS(8, 12)), - NPCM7XX_PINCFG(162, serirq, NONE, 0, gpio, MFSEL1, 31, none, NONE, 0, DS(8, 12)), + NPCM7XX_PINCFG(156, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(157, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(158, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(159, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + + NPCM7XX_PINCFG(160, clkout, MFSEL1, 21, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(161, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, DSTR(8, 12)), + NPCM7XX_PINCFG(162, serirq, NONE, 0, gpio, MFSEL1, 31, none, NONE, 0, DSTR(8, 12)), NPCM7XX_PINCFG(163, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, 0), NPCM7XX_PINCFG(164, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC), NPCM7XX_PINCFG(165, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC), @@ -1102,25 +1102,25 @@ static const struct npcm7xx_pincfg pincfg[] = { NPCM7XX_PINCFG(172, smb6, MFSEL3, 1, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(173, smb7, MFSEL3, 2, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(174, smb7, MFSEL3, 2, none, NONE, 0, none, NONE, 0, 0), - NPCM7XX_PINCFG(175, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DS(8, 12)), - NPCM7XX_PINCFG(176, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DS(8, 12)), - NPCM7XX_PINCFG(177, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DS(8, 12)), - NPCM7XX_PINCFG(178, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(179, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(180, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), + NPCM7XX_PINCFG(175, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DSTR(8, 12)), + NPCM7XX_PINCFG(176, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DSTR(8, 12)), + NPCM7XX_PINCFG(177, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DSTR(8, 12)), + NPCM7XX_PINCFG(178, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(179, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(180, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), NPCM7XX_PINCFG(181, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(182, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0), - NPCM7XX_PINCFG(183, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(184, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW | GPO), - NPCM7XX_PINCFG(185, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW | GPO), - NPCM7XX_PINCFG(186, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DS(8, 12)), - NPCM7XX_PINCFG(187, spi3cs1, MFSEL4, 17, none, NONE, 0, none, NONE, 0, DS(8, 12)), - NPCM7XX_PINCFG(188, spi3quad, MFSEL4, 20, spi3cs2, MFSEL4, 18, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(189, spi3quad, MFSEL4, 20, spi3cs3, MFSEL4, 19, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(190, gpio, FLOCKR1, 20, nprd_smi, NONE, 0, none, NONE, 0, DS(2, 4)), - NPCM7XX_PINCFG(191, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12)), /* XX */ - - NPCM7XX_PINCFG(192, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12)), /* XX */ + NPCM7XX_PINCFG(183, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(184, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO), + NPCM7XX_PINCFG(185, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO), + NPCM7XX_PINCFG(186, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), + NPCM7XX_PINCFG(187, spi3cs1, MFSEL4, 17, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), + NPCM7XX_PINCFG(188, spi3quad, MFSEL4, 20, spi3cs2, MFSEL4, 18, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(189, spi3quad, MFSEL4, 20, spi3cs3, MFSEL4, 19, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(190, gpio, FLOCKR1, 20, nprd_smi, NONE, 0, none, NONE, 0, DSTR(2, 4)), + NPCM7XX_PINCFG(191, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), /* XX */ + + NPCM7XX_PINCFG(192, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), /* XX */ NPCM7XX_PINCFG(193, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(194, smb0b, I2CSEGSEL, 0, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(195, smb0b, I2CSEGSEL, 0, none, NONE, 0, none, NONE, 0, 0), @@ -1131,11 +1131,11 @@ static const struct npcm7xx_pincfg pincfg[] = { NPCM7XX_PINCFG(200, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(201, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(202, smb0c, I2CSEGSEL, 1, none, NONE, 0, none, NONE, 0, 0), - NPCM7XX_PINCFG(203, faninx, MFSEL3, 3, none, NONE, 0, none, NONE, 0, DS(8, 12)), + NPCM7XX_PINCFG(203, faninx, MFSEL3, 3, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), NPCM7XX_PINCFG(204, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, SLEW), NPCM7XX_PINCFG(205, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, SLEW), - NPCM7XX_PINCFG(206, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, DS(4, 8)), - NPCM7XX_PINCFG(207, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, DS(4, 8)), + NPCM7XX_PINCFG(206, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, DSTR(4, 8)), + NPCM7XX_PINCFG(207, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, DSTR(4, 8)), NPCM7XX_PINCFG(208, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0), NPCM7XX_PINCFG(209, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0), NPCM7XX_PINCFG(210, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0), @@ -1147,20 +1147,20 @@ static const struct npcm7xx_pincfg pincfg[] = { NPCM7XX_PINCFG(216, rg2mdio, MFSEL4, 23, ddr, MFSEL3, 26, none, NONE, 0, 0), NPCM7XX_PINCFG(217, rg2mdio, MFSEL4, 23, ddr, MFSEL3, 26, none, NONE, 0, 0), NPCM7XX_PINCFG(218, wdog1, MFSEL3, 19, none, NONE, 0, none, NONE, 0, 0), - NPCM7XX_PINCFG(219, wdog2, MFSEL3, 20, none, NONE, 0, none, NONE, 0, DS(4, 8)), + NPCM7XX_PINCFG(219, wdog2, MFSEL3, 20, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), NPCM7XX_PINCFG(220, smb12, MFSEL3, 5, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(221, smb12, MFSEL3, 5, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(222, smb13, MFSEL3, 6, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(223, smb13, MFSEL3, 6, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(224, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, SLEW), - NPCM7XX_PINCFG(225, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW | GPO), - NPCM7XX_PINCFG(226, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW | GPO), - NPCM7XX_PINCFG(227, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(228, spixcs1, MFSEL4, 28, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(229, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(230, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(231, clkreq, MFSEL4, 9, none, NONE, 0, none, NONE, 0, DS(8, 12)), + NPCM7XX_PINCFG(225, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO), + NPCM7XX_PINCFG(226, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO), + NPCM7XX_PINCFG(227, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(228, spixcs1, MFSEL4, 28, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(229, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(230, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(231, clkreq, MFSEL4, 9, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), NPCM7XX_PINCFG(253, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* SDHC1 power */ NPCM7XX_PINCFG(254, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* SDHC2 power */ NPCM7XX_PINCFG(255, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* DACOSEL */ @@ -1561,7 +1561,7 @@ static int npcm7xx_get_groups_count(struct pinctrl_dev *pctldev) { struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev); - dev_dbg(npcm->dev, "group size: %d\n", ARRAY_SIZE(npcm7xx_groups)); + dev_dbg(npcm->dev, "group size: %zu\n", ARRAY_SIZE(npcm7xx_groups)); return ARRAY_SIZE(npcm7xx_groups); } diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c index fafd1f55cba7..517f2a6330ad 100644 --- a/drivers/pinctrl/pinctrl-at91-pio4.c +++ b/drivers/pinctrl/pinctrl-at91-pio4.c @@ -1045,7 +1045,6 @@ static int atmel_pinctrl_probe(struct platform_device *pdev) const char **group_names; const struct of_device_id *match; int i, ret; - struct resource *res; struct atmel_pioctrl *atmel_pioctrl; const struct atmel_pioctrl_data *atmel_pioctrl_data; @@ -1164,16 +1163,15 @@ static int atmel_pinctrl_probe(struct platform_device *pdev) /* There is one controller but each bank has its own irq line. */ for (i = 0; i < atmel_pioctrl->nbanks; i++) { - res = platform_get_resource(pdev, IORESOURCE_IRQ, i); - if (!res) { - dev_err(dev, "missing irq resource for group %c\n", + ret = platform_get_irq(pdev, i); + if (ret < 0) { + dev_dbg(dev, "missing irq resource for group %c\n", 'A' + i); - return -EINVAL; + return ret; } - atmel_pioctrl->irqs[i] = res->start; - irq_set_chained_handler_and_data(res->start, - atmel_gpio_irq_handler, atmel_pioctrl); - dev_dbg(dev, "bank %i: irq=%pr\n", i, res); + atmel_pioctrl->irqs[i] = ret; + irq_set_chained_handler_and_data(ret, atmel_gpio_irq_handler, atmel_pioctrl); + dev_dbg(dev, "bank %i: irq=%d\n", i, ret); } atmel_pioctrl->irq_domain = irq_domain_add_linear(dev->of_node, diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c index fc969208d904..685c79e08d40 100644 --- a/drivers/pinctrl/pinctrl-ocelot.c +++ b/drivers/pinctrl/pinctrl-ocelot.c @@ -695,6 +695,98 @@ static const struct pinctrl_pin_desc jaguar2_pins[] = { JAGUAR2_PIN(63), }; +#define SERVALT_P(p, f0, f1, f2) \ +static struct ocelot_pin_caps servalt_pin_##p = { \ + .pin = p, \ + .functions = { \ + FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2 \ + }, \ +} + +SERVALT_P(0, SG0, NONE, NONE); +SERVALT_P(1, SG0, NONE, NONE); +SERVALT_P(2, SG0, NONE, NONE); +SERVALT_P(3, SG0, NONE, NONE); +SERVALT_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M); +SERVALT_P(5, IRQ1_IN, IRQ1_OUT, TWI_SCL_M); +SERVALT_P(6, UART, NONE, NONE); +SERVALT_P(7, UART, NONE, NONE); +SERVALT_P(8, SI, SFP, TWI_SCL_M); +SERVALT_P(9, PCI_WAKE, SFP, SI); +SERVALT_P(10, PTP0, SFP, TWI_SCL_M); +SERVALT_P(11, PTP1, SFP, TWI_SCL_M); +SERVALT_P(12, REF_CLK, SFP, TWI_SCL_M); +SERVALT_P(13, REF_CLK, SFP, TWI_SCL_M); +SERVALT_P(14, REF_CLK, IRQ0_OUT, SI); +SERVALT_P(15, REF_CLK, IRQ1_OUT, SI); +SERVALT_P(16, TACHO, SFP, SI); +SERVALT_P(17, PWM, NONE, TWI_SCL_M); +SERVALT_P(18, PTP2, SFP, SI); +SERVALT_P(19, PTP3, SFP, SI); +SERVALT_P(20, UART2, SFP, SI); +SERVALT_P(21, UART2, NONE, NONE); +SERVALT_P(22, MIIM, SFP, TWI2); +SERVALT_P(23, MIIM, SFP, TWI2); +SERVALT_P(24, TWI, NONE, NONE); +SERVALT_P(25, TWI, SFP, TWI_SCL_M); +SERVALT_P(26, TWI_SCL_M, SFP, SI); +SERVALT_P(27, TWI_SCL_M, SFP, SI); +SERVALT_P(28, TWI_SCL_M, SFP, SI); +SERVALT_P(29, TWI_SCL_M, NONE, NONE); +SERVALT_P(30, TWI_SCL_M, NONE, NONE); +SERVALT_P(31, TWI_SCL_M, NONE, NONE); +SERVALT_P(32, TWI_SCL_M, NONE, NONE); +SERVALT_P(33, RCVRD_CLK, NONE, NONE); +SERVALT_P(34, RCVRD_CLK, NONE, NONE); +SERVALT_P(35, RCVRD_CLK, NONE, NONE); +SERVALT_P(36, RCVRD_CLK, NONE, NONE); + +#define SERVALT_PIN(n) { \ + .number = n, \ + .name = "GPIO_"#n, \ + .drv_data = &servalt_pin_##n \ +} + +static const struct pinctrl_pin_desc servalt_pins[] = { + SERVALT_PIN(0), + SERVALT_PIN(1), + SERVALT_PIN(2), + SERVALT_PIN(3), + SERVALT_PIN(4), + SERVALT_PIN(5), + SERVALT_PIN(6), + SERVALT_PIN(7), + SERVALT_PIN(8), + SERVALT_PIN(9), + SERVALT_PIN(10), + SERVALT_PIN(11), + SERVALT_PIN(12), + SERVALT_PIN(13), + SERVALT_PIN(14), + SERVALT_PIN(15), + SERVALT_PIN(16), + SERVALT_PIN(17), + SERVALT_PIN(18), + SERVALT_PIN(19), + SERVALT_PIN(20), + SERVALT_PIN(21), + SERVALT_PIN(22), + SERVALT_PIN(23), + SERVALT_PIN(24), + SERVALT_PIN(25), + SERVALT_PIN(26), + SERVALT_PIN(27), + SERVALT_PIN(28), + SERVALT_PIN(29), + SERVALT_PIN(30), + SERVALT_PIN(31), + SERVALT_PIN(32), + SERVALT_PIN(33), + SERVALT_PIN(34), + SERVALT_PIN(35), + SERVALT_PIN(36), +}; + #define SPARX5_P(p, f0, f1, f2) \ static struct ocelot_pin_caps sparx5_pin_##p = { \ .pin = p, \ @@ -1497,6 +1589,15 @@ static struct pinctrl_desc jaguar2_desc = { .owner = THIS_MODULE, }; +static struct pinctrl_desc servalt_desc = { + .name = "servalt-pinctrl", + .pins = servalt_pins, + .npins = ARRAY_SIZE(servalt_pins), + .pctlops = &ocelot_pctl_ops, + .pmxops = &ocelot_pmx_ops, + .owner = THIS_MODULE, +}; + static struct pinctrl_desc sparx5_desc = { .name = "sparx5-pinctrl", .pins = sparx5_pins, @@ -1774,6 +1875,7 @@ static const struct of_device_id ocelot_pinctrl_of_match[] = { { .compatible = "mscc,serval-pinctrl", .data = &serval_desc }, { .compatible = "mscc,ocelot-pinctrl", .data = &ocelot_desc }, { .compatible = "mscc,jaguar2-pinctrl", .data = &jaguar2_desc }, + { .compatible = "mscc,servalt-pinctrl", .data = &servalt_desc }, { .compatible = "microchip,sparx5-pinctrl", .data = &sparx5_desc }, { .compatible = "microchip,lan966x-pinctrl", .data = &lan966x_desc }, {}, diff --git a/drivers/pinctrl/pinctrl-starfive.c b/drivers/pinctrl/pinctrl-starfive.c index 0b912152a405..ed6c9b36849b 100644 --- a/drivers/pinctrl/pinctrl-starfive.c +++ b/drivers/pinctrl/pinctrl-starfive.c @@ -1026,7 +1026,7 @@ static int starfive_gpio_set_config(struct gpio_chip *gc, unsigned int gpio, break; default: return -ENOTSUPP; - }; + } starfive_padctl_rmw(sfp, starfive_gpio_to_pin(sfp, gpio), mask, value); return 0; diff --git a/drivers/pinctrl/pxa/pinctrl-pxa27x.c b/drivers/pinctrl/pxa/pinctrl-pxa27x.c index 48ccfb50b23e..ff9302e4803a 100644 --- a/drivers/pinctrl/pxa/pinctrl-pxa27x.c +++ b/drivers/pinctrl/pxa/pinctrl-pxa27x.c @@ -504,7 +504,7 @@ static const struct pxa_desc_pin pxa27x_pins[] = { static int pxa27x_pinctrl_probe(struct platform_device *pdev) { - int ret, i; + int i; void __iomem *base_af[8]; void __iomem *base_dir[4]; void __iomem *base_sleep[4]; @@ -532,9 +532,8 @@ static int pxa27x_pinctrl_probe(struct platform_device *pdev) for (i = 0; i < ARRAY_SIZE(base_sleep); i++) base_sleep[i] = base_sleep[0] + sizeof(base_af[0]) * i; - ret = pxa2xx_pinctrl_init(pdev, pxa27x_pins, ARRAY_SIZE(pxa27x_pins), + return pxa2xx_pinctrl_init(pdev, pxa27x_pins, ARRAY_SIZE(pxa27x_pins), base_af, base_dir, base_sleep); - return ret; } static const struct of_device_id pxa27x_pinctrl_match[] = { diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 780878dede9e..966ea6622ff3 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -615,6 +615,7 @@ static void msm_gpio_dbg_show_one(struct seq_file *s, int drive; int pull; int val; + int egpio_enable; u32 ctl_reg, io_reg; static const char * const pulls_keeper[] = { @@ -641,12 +642,20 @@ static void msm_gpio_dbg_show_one(struct seq_file *s, func = (ctl_reg >> g->mux_bit) & 7; drive = (ctl_reg >> g->drv_bit) & 7; pull = (ctl_reg >> g->pull_bit) & 3; + egpio_enable = 0; + if (pctrl->soc->egpio_func && ctl_reg & BIT(g->egpio_present)) + egpio_enable = !(ctl_reg & BIT(g->egpio_enable)); if (is_out) val = !!(io_reg & BIT(g->out_bit)); else val = !!(io_reg & BIT(g->in_bit)); + if (egpio_enable) { + seq_printf(s, " %-8s: egpio\n", g->name); + return; + } + seq_printf(s, " %-8s: %-3s", g->name, is_out ? "out" : "in"); seq_printf(s, " %-4s func%d", val ? "high" : "low", func); seq_printf(s, " %dmA", msm_regval_to_drive(drive)); @@ -1168,7 +1177,7 @@ static int msm_gpio_irq_set_affinity(struct irq_data *d, if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) return irq_chip_set_affinity_parent(d, dest, force); - return 0; + return -EINVAL; } static int msm_gpio_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info) @@ -1179,7 +1188,7 @@ static int msm_gpio_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info) if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) return irq_chip_set_vcpu_affinity_parent(d, vcpu_info); - return 0; + return -EINVAL; } static void msm_gpio_irq_handler(struct irq_desc *desc) diff --git a/drivers/pinctrl/qcom/pinctrl-qcm2290.c b/drivers/pinctrl/qcom/pinctrl-qcm2290.c index 3f05c0a24b79..aa9325f333fb 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcm2290.c +++ b/drivers/pinctrl/qcom/pinctrl-qcm2290.c @@ -1083,6 +1083,16 @@ static const struct msm_pingroup qcm2290_groups[] = { [133] = SDC_QDSD_PINGROUP(sdc2_data, 0x86000, 9, 0), }; +static const struct msm_gpio_wakeirq_map qcm2290_mpm_map[] = { + { 0, 84 }, { 3, 75 }, { 4, 16 }, { 6, 59 }, { 8, 63 }, { 11, 17 }, + { 13, 18 }, { 14, 51 }, { 17, 20 }, { 18, 52 }, { 19, 53 }, { 24, 6 }, + { 25, 71 }, { 27, 73 }, { 28, 41 }, { 31, 27 }, { 32, 54 }, { 33, 55 }, + { 34, 56 }, { 35, 57 }, { 36, 58 }, { 39, 28 }, { 46, 29 }, { 62, 60 }, + { 63, 61 }, { 64, 62 }, { 69, 33 }, { 70, 34 }, { 72, 72 }, { 75, 35 }, + { 79, 36 }, { 80, 21 }, { 81, 38 }, { 86, 19 }, { 87, 42 }, { 88, 43 }, + { 89, 45 }, { 91, 74 }, { 94, 47 }, { 95, 48 }, { 96, 49 }, { 97, 50 }, +}; + static const struct msm_pinctrl_soc_data qcm2290_pinctrl = { .pins = qcm2290_pins, .npins = ARRAY_SIZE(qcm2290_pins), @@ -1091,6 +1101,8 @@ static const struct msm_pinctrl_soc_data qcm2290_pinctrl = { .groups = qcm2290_groups, .ngroups = ARRAY_SIZE(qcm2290_groups), .ngpios = 127, + .wakeirq_map = qcm2290_mpm_map, + .nwakeirq_map = ARRAY_SIZE(qcm2290_mpm_map), }; static int qcm2290_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/qcom/pinctrl-sm8450.c b/drivers/pinctrl/qcom/pinctrl-sm8450.c index c6fa3dbc14a1..3110d7bf5698 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8450.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8450.c @@ -46,6 +46,8 @@ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ + .egpio_enable = 12, \ + .egpio_present = 11, \ .oe_bit = 9, \ .in_bit = 0, \ .out_bit = 1, \ @@ -567,6 +569,7 @@ enum sm8450_functions { msm_mux_ddr_pxi2, msm_mux_ddr_pxi3, msm_mux_dp_hot, + msm_mux_egpio, msm_mux_gcc_gp1, msm_mux_gcc_gp2, msm_mux_gcc_gp3, @@ -719,6 +722,17 @@ static const char * const gpio_groups[] = { "gpio207", "gpio208", "gpio209", }; +static const char * const egpio_groups[] = { + "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170", + "gpio171", "gpio172", "gpio173", "gpio174", "gpio175", "gpio176", + "gpio177", "gpio178", "gpio179", "gpio180", "gpio181", "gpio182", + "gpio183", "gpio184", "gpio185", "gpio186", "gpio187", "gpio188", + "gpio189", "gpio190", "gpio191", "gpio192", "gpio193", "gpio194", + "gpio195", "gpio196", "gpio197", "gpio198", "gpio199", "gpio200", + "gpio201", "gpio202", "gpio203", "gpio204", "gpio205", "gpio206", + "gpio207", "gpio208", "gpio209", +}; + static const char * const aon_cam_groups[] = { "gpio108", }; @@ -1285,6 +1299,7 @@ static const struct msm_function sm8450_functions[] = { FUNCTION(ddr_pxi2), FUNCTION(ddr_pxi3), FUNCTION(dp_hot), + FUNCTION(egpio), FUNCTION(gcc_gp1), FUNCTION(gcc_gp2), FUNCTION(gcc_gp3), @@ -1571,51 +1586,51 @@ static const struct msm_pingroup sm8450_groups[] = { [162] = PINGROUP(162, qlink2_request, _, _, _, _, _, _, _, _), [163] = PINGROUP(163, qlink2_enable, _, _, _, _, _, _, _, _), [164] = PINGROUP(164, qlink2_wmss, _, _, _, _, _, _, _, _), - [165] = PINGROUP(165, _, _, _, _, _, _, _, _, _), - [166] = PINGROUP(166, _, _, _, _, _, _, _, _, _), - [167] = PINGROUP(167, _, _, _, _, _, _, _, _, _), - [168] = PINGROUP(168, _, _, _, _, _, _, _, _, _), - [169] = PINGROUP(169, _, _, _, _, _, _, _, _, _), - [170] = PINGROUP(170, _, _, _, _, _, _, _, _, _), - [171] = PINGROUP(171, _, _, _, _, _, _, _, _, _), - [172] = PINGROUP(172, _, _, _, _, _, _, _, _, _), - [173] = PINGROUP(173, _, _, _, _, _, _, _, _, _), - [174] = PINGROUP(174, _, _, _, _, _, _, _, _, _), - [175] = PINGROUP(175, _, _, _, _, _, _, _, _, _), - [176] = PINGROUP(176, _, _, _, _, _, _, _, _, _), - [177] = PINGROUP(177, _, _, _, _, _, _, _, _, _), - [178] = PINGROUP(178, _, _, _, _, _, _, _, _, _), - [179] = PINGROUP(179, _, _, _, _, _, _, _, _, _), - [180] = PINGROUP(180, _, _, _, _, _, _, _, _, _), - [181] = PINGROUP(181, _, _, _, _, _, _, _, _, _), - [182] = PINGROUP(182, _, _, _, _, _, _, _, _, _), - [183] = PINGROUP(183, _, _, _, _, _, _, _, _, _), - [184] = PINGROUP(184, _, _, _, _, _, _, _, _, _), - [185] = PINGROUP(185, _, _, _, _, _, _, _, _, _), - [186] = PINGROUP(186, _, _, _, _, _, _, _, _, _), - [187] = PINGROUP(187, _, _, _, _, _, _, _, _, _), - [188] = PINGROUP(188, _, qdss_gpio, _, _, _, _, _, _, _), - [189] = PINGROUP(189, _, qdss_gpio, _, _, _, _, _, _, _), - [190] = PINGROUP(190, qdss_gpio, _, _, _, _, _, _, _, _), - [191] = PINGROUP(191, qdss_gpio, _, _, _, _, _, _, _, _), - [192] = PINGROUP(192, _, qdss_gpio, _, _, _, _, _, _, _), - [193] = PINGROUP(193, _, qdss_gpio, _, _, _, _, _, _, _), - [194] = PINGROUP(194, _, qdss_gpio, _, _, _, _, _, _, _), - [195] = PINGROUP(195, _, qdss_gpio, _, _, _, _, _, _, _), - [196] = PINGROUP(196, _, qdss_gpio, _, _, _, _, _, _, _), - [197] = PINGROUP(197, _, qdss_gpio, _, _, _, _, _, _, _), - [198] = PINGROUP(198, _, qdss_gpio, _, _, _, _, _, _, _), - [199] = PINGROUP(199, _, qdss_gpio, _, _, _, _, _, _, _), - [200] = PINGROUP(200, _, qdss_gpio, _, _, _, _, _, _, _), - [201] = PINGROUP(201, _, qdss_gpio, _, _, _, _, _, _, _), - [202] = PINGROUP(202, qdss_gpio, _, _, _, _, _, _, _, _), - [203] = PINGROUP(203, qdss_gpio, _, _, _, _, _, _, _, _), - [204] = PINGROUP(204, qdss_gpio, _, _, _, _, _, _, _, _), - [205] = PINGROUP(205, qdss_gpio, _, _, _, _, _, _, _, _), - [206] = PINGROUP(206, qup5, _, _, _, _, _, _, _, _), - [207] = PINGROUP(207, qup5, _, _, _, _, _, _, _, _), - [208] = PINGROUP(208, cci_i2c, _, _, _, _, _, _, _, _), - [209] = PINGROUP(209, cci_i2c, _, _, _, _, _, _, _, _), + [165] = PINGROUP(165, _, _, _, _, _, _, _, _, egpio), + [166] = PINGROUP(166, _, _, _, _, _, _, _, _, egpio), + [167] = PINGROUP(167, _, _, _, _, _, _, _, _, egpio), + [168] = PINGROUP(168, _, _, _, _, _, _, _, _, egpio), + [169] = PINGROUP(169, _, _, _, _, _, _, _, _, egpio), + [170] = PINGROUP(170, _, _, _, _, _, _, _, _, egpio), + [171] = PINGROUP(171, _, _, _, _, _, _, _, _, egpio), + [172] = PINGROUP(172, _, _, _, _, _, _, _, _, egpio), + [173] = PINGROUP(173, _, _, _, _, _, _, _, _, egpio), + [174] = PINGROUP(174, _, _, _, _, _, _, _, _, egpio), + [175] = PINGROUP(175, _, _, _, _, _, _, _, _, egpio), + [176] = PINGROUP(176, _, _, _, _, _, _, _, _, egpio), + [177] = PINGROUP(177, _, _, _, _, _, _, _, _, egpio), + [178] = PINGROUP(178, _, _, _, _, _, _, _, _, egpio), + [179] = PINGROUP(179, _, _, _, _, _, _, _, _, egpio), + [180] = PINGROUP(180, _, _, _, _, _, _, _, _, egpio), + [181] = PINGROUP(181, _, _, _, _, _, _, _, _, egpio), + [182] = PINGROUP(182, _, _, _, _, _, _, _, _, egpio), + [183] = PINGROUP(183, _, _, _, _, _, _, _, _, egpio), + [184] = PINGROUP(184, _, _, _, _, _, _, _, _, egpio), + [185] = PINGROUP(185, _, _, _, _, _, _, _, _, egpio), + [186] = PINGROUP(186, _, _, _, _, _, _, _, _, egpio), + [187] = PINGROUP(187, _, _, _, _, _, _, _, _, egpio), + [188] = PINGROUP(188, _, qdss_gpio, _, _, _, _, _, _, egpio), + [189] = PINGROUP(189, _, qdss_gpio, _, _, _, _, _, _, egpio), + [190] = PINGROUP(190, qdss_gpio, _, _, _, _, _, _, _, egpio), + [191] = PINGROUP(191, qdss_gpio, _, _, _, _, _, _, _, egpio), + [192] = PINGROUP(192, _, qdss_gpio, _, _, _, _, _, _, egpio), + [193] = PINGROUP(193, _, qdss_gpio, _, _, _, _, _, _, egpio), + [194] = PINGROUP(194, _, qdss_gpio, _, _, _, _, _, _, egpio), + [195] = PINGROUP(195, _, qdss_gpio, _, _, _, _, _, _, egpio), + [196] = PINGROUP(196, _, qdss_gpio, _, _, _, _, _, _, egpio), + [197] = PINGROUP(197, _, qdss_gpio, _, _, _, _, _, _, egpio), + [198] = PINGROUP(198, _, qdss_gpio, _, _, _, _, _, _, egpio), + [199] = PINGROUP(199, _, qdss_gpio, _, _, _, _, _, _, egpio), + [200] = PINGROUP(200, _, qdss_gpio, _, _, _, _, _, _, egpio), + [201] = PINGROUP(201, _, qdss_gpio, _, _, _, _, _, _, egpio), + [202] = PINGROUP(202, qdss_gpio, _, _, _, _, _, _, _, egpio), + [203] = PINGROUP(203, qdss_gpio, _, _, _, _, _, _, _, egpio), + [204] = PINGROUP(204, qdss_gpio, _, _, _, _, _, _, _, egpio), + [205] = PINGROUP(205, qdss_gpio, _, _, _, _, _, _, _, egpio), + [206] = PINGROUP(206, qup5, _, _, _, _, _, _, _, egpio), + [207] = PINGROUP(207, qup5, _, _, _, _, _, _, _, egpio), + [208] = PINGROUP(208, cci_i2c, _, _, _, _, _, _, _, egpio), + [209] = PINGROUP(209, cci_i2c, _, _, _, _, _, _, _, egpio), [210] = UFS_RESET(ufs_reset, 0xde000), [211] = SDC_QDSD_PINGROUP(sdc2_clk, 0xd6000, 14, 6), [212] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xd6000, 11, 3), @@ -1651,6 +1666,7 @@ static const struct msm_pinctrl_soc_data sm8450_tlmm = { .ngpios = 211, .wakeirq_map = sm8450_pdc_map, .nwakeirq_map = ARRAY_SIZE(sm8450_pdc_map), + .egpio_func = 9, }; static int sm8450_tlmm_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c index b80723928b7e..6937157f50b3 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c @@ -961,6 +961,7 @@ static int pmic_mpp_remove(struct platform_device *pdev) static const struct of_device_id pmic_mpp_of_match[] = { { .compatible = "qcom,pm8019-mpp", .data = (void *) 6 }, + { .compatible = "qcom,pm8226-mpp", .data = (void *) 8 }, { .compatible = "qcom,pm8841-mpp", .data = (void *) 4 }, { .compatible = "qcom,pm8916-mpp", .data = (void *) 4 }, { .compatible = "qcom,pm8941-mpp", .data = (void *) 8 }, diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig index 9a72999084b3..c0c740e660b8 100644 --- a/drivers/pinctrl/renesas/Kconfig +++ b/drivers/pinctrl/renesas/Kconfig @@ -38,6 +38,7 @@ config PINCTRL_RENESAS select PINCTRL_PFC_R8A77995 if ARCH_R8A77995 select PINCTRL_PFC_R8A779A0 if ARCH_R8A779A0 select PINCTRL_RZG2L if ARCH_R9A07G044 + select PINCTRL_RZG2L if ARCH_R9A07G054 select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203 select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264 select PINCTRL_PFC_SH7269 if CPU_SUBTYPE_SH7269 @@ -178,14 +179,15 @@ config PINCTRL_RZA2 This selects GPIO and pinctrl driver for Renesas RZ/A2 platforms. config PINCTRL_RZG2L - bool "pin control support for RZ/G2L" if COMPILE_TEST + bool "pin control support for RZ/{G2L,V2L}" if COMPILE_TEST depends on OF select GPIOLIB select GENERIC_PINCTRL_GROUPS select GENERIC_PINMUX_FUNCTIONS select GENERIC_PINCONF help - This selects GPIO and pinctrl driver for Renesas RZ/G2L platforms. + This selects GPIO and pinctrl driver for Renesas RZ/{G2L,V2L} + platforms. config PINCTRL_PFC_R8A77470 bool "pin control support for RZ/G1C" if COMPILE_TEST diff --git a/drivers/pinctrl/renesas/pfc-r8a7779.c b/drivers/pinctrl/renesas/pfc-r8a7779.c index 3e47cdc1411d..2b6dec2007b6 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7779.c +++ b/drivers/pinctrl/renesas/pfc-r8a7779.c @@ -3133,10 +3133,6 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(lbsc), SH_PFC_FUNCTION(mmc0), SH_PFC_FUNCTION(mmc1), - SH_PFC_FUNCTION(sdhi0), - SH_PFC_FUNCTION(sdhi1), - SH_PFC_FUNCTION(sdhi2), - SH_PFC_FUNCTION(sdhi3), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), SH_PFC_FUNCTION(scif2), @@ -3144,6 +3140,10 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(scif4), SH_PFC_FUNCTION(scif5), SH_PFC_FUNCTION(scif_clk), + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), + SH_PFC_FUNCTION(sdhi2), + SH_PFC_FUNCTION(sdhi3), SH_PFC_FUNCTION(usb0), SH_PFC_FUNCTION(usb1), SH_PFC_FUNCTION(usb2), diff --git a/drivers/pinctrl/renesas/pfc-r8a7790.c b/drivers/pinctrl/renesas/pfc-r8a7790.c index 08c0a23edf68..1fd1856ab3e3 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7790.c +++ b/drivers/pinctrl/renesas/pfc-r8a7790.c @@ -194,24 +194,24 @@ enum { FN_CAN1_TX, FN_DRACK0, FN_IETX_C, FN_RD_N, FN_CAN0_TX, FN_SCIFA0_SCK_B, FN_RD_WR_N, FN_VI1_G3, FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B, - FN_INTC_IRQ4_N, FN_WE0_N, FN_IECLK, FN_CAN_CLK, + FN_WE0_N, FN_IECLK, FN_CAN_CLK, FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4, FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, - FN_IERX_C, FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N, + FN_IERX_C, FN_EX_WAIT0, FN_IRQ3, FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B, FN_MSIOF0_SCK_B, FN_DREQ0_N, FN_VI1_HSYNC_N, FN_VI1_HSYNC_N_B, FN_VI2_R7, FN_SSI_SCK78_C, FN_SSI_WS78_B, /* IPSR6 */ - FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B, + FN_DACK0, FN_IRQ0, FN_SSI_SCK6_B, FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B, FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1, - FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C, + FN_SSI_WS6_B, FN_SSI_SDATA8_C, FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, - FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N, + FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, FN_ETH_CRS_DV, FN_STP_ISCLK_0_B, FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E, @@ -568,23 +568,23 @@ enum { CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK, CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK, VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK, - INTC_IRQ4_N_MARK, WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK, + WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK, VI2_VSYNC_N_MARK, SCIFA0_TXD_B_MARK, VI2_VSYNC_N_B_MARK, WE1_N_MARK, IERX_MARK, CAN1_RX_MARK, VI1_G4_MARK, VI1_G4_B_MARK, VI2_R6_MARK, SCIFA0_CTS_N_B_MARK, - IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK, INTC_IRQ3_N_MARK, + IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK, VI3_CLK_MARK, SCIFA0_RTS_N_B_MARK, HRX0_B_MARK, MSIOF0_SCK_B_MARK, DREQ0_N_MARK, VI1_HSYNC_N_MARK, VI1_HSYNC_N_B_MARK, VI2_R7_MARK, SSI_SCK78_C_MARK, SSI_WS78_B_MARK, - DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK, + DACK0_MARK, IRQ0_MARK, SSI_SCK6_B_MARK, VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK, DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK, SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK, - INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK, + SSI_WS6_B_MARK, SSI_SDATA8_C_MARK, DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK, - MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK, + MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK, ETH_CRS_DV_MARK, STP_ISCLK_0_B_MARK, TS_SDEN0_D_MARK, GLO_Q0_C_MARK, IIC2_SCL_E_MARK, @@ -1094,7 +1094,6 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP5_17_15, VI1_G3_B, SEL_VI1_1), PINMUX_IPSR_GPSR(IP5_17_15, VI2_R5), PINMUX_IPSR_MSEL(IP5_17_15, SCIFA0_RXD_B, SEL_SCFA_1), - PINMUX_IPSR_GPSR(IP5_17_15, INTC_IRQ4_N), PINMUX_IPSR_GPSR(IP5_20_18, WE0_N), PINMUX_IPSR_MSEL(IP5_20_18, IECLK, SEL_IEB_0), PINMUX_IPSR_MSEL(IP5_20_18, CAN_CLK, SEL_CANCLK_0), @@ -1111,7 +1110,6 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP5_23_21, IERX_C, SEL_IEB_2), PINMUX_IPSR_MSEL(IP5_26_24, EX_WAIT0, SEL_LBS_0), PINMUX_IPSR_GPSR(IP5_26_24, IRQ3), - PINMUX_IPSR_GPSR(IP5_26_24, INTC_IRQ3_N), PINMUX_IPSR_MSEL(IP5_26_24, VI3_CLK, SEL_VI3_0), PINMUX_IPSR_MSEL(IP5_26_24, SCIFA0_RTS_N_B, SEL_SCFA_1), PINMUX_IPSR_MSEL(IP5_26_24, HRX0_B, SEL_HSCIF0_1), @@ -1125,7 +1123,6 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP6_2_0, DACK0), PINMUX_IPSR_GPSR(IP6_2_0, IRQ0), - PINMUX_IPSR_GPSR(IP6_2_0, INTC_IRQ0_N), PINMUX_IPSR_MSEL(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1), PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0), PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1), @@ -1137,7 +1134,6 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1), PINMUX_IPSR_GPSR(IP6_8_6, DACK1), PINMUX_IPSR_GPSR(IP6_8_6, IRQ1), - PINMUX_IPSR_GPSR(IP6_8_6, INTC_IRQ1_N), PINMUX_IPSR_MSEL(IP6_8_6, SSI_WS6_B, SEL_SSI6_1), PINMUX_IPSR_MSEL(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2), PINMUX_IPSR_GPSR(IP6_10_9, DREQ2_N), @@ -1146,7 +1142,6 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1), PINMUX_IPSR_GPSR(IP6_13_11, DACK2), PINMUX_IPSR_GPSR(IP6_13_11, IRQ2), - PINMUX_IPSR_GPSR(IP6_13_11, INTC_IRQ2_N), PINMUX_IPSR_MSEL(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1), PINMUX_IPSR_MSEL(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1), PINMUX_IPSR_MSEL(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1), @@ -4964,10 +4959,10 @@ static const struct { .common = { SH_PFC_FUNCTION(audio_clk), SH_PFC_FUNCTION(avb), - SH_PFC_FUNCTION(du), SH_PFC_FUNCTION(can0), SH_PFC_FUNCTION(can1), SH_PFC_FUNCTION(can_clk), + SH_PFC_FUNCTION(du), SH_PFC_FUNCTION(du0), SH_PFC_FUNCTION(du1), SH_PFC_FUNCTION(du2), @@ -5415,9 +5410,8 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_DREQ0_N, FN_VI1_HSYNC_N, FN_VI1_HSYNC_N_B, FN_VI2_R7, FN_SSI_SCK78_C, FN_SSI_WS78_B, 0, 0, /* IP5_26_24 [3] */ - FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N, - FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B, - FN_MSIOF0_SCK_B, 0, + FN_EX_WAIT0, FN_IRQ3, 0, FN_VI3_CLK, FN_SCIFA0_RTS_N_B, + FN_HRX0_B, FN_MSIOF0_SCK_B, 0, /* IP5_23_21 [3] */ FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4, FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, FN_IERX_C, @@ -5426,7 +5420,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 0, 0, /* IP5_17_15 [3] */ FN_RD_WR_N, FN_VI1_G3, FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B, - FN_INTC_IRQ4_N, 0, 0, + 0, 0, 0, /* IP5_14_13 [2] */ FN_RD_N, FN_CAN0_TX, FN_SCIFA0_SCK_B, 0, /* IP5_12_10 [3] */ @@ -5467,19 +5461,18 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E, FN_I2C2_SCL_E, 0, /* IP6_13_11 [3] */ - FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N, - FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0, + FN_DACK2, FN_IRQ2, 0, FN_SSI_SDATA6_B, FN_HRTS0_N_B, + FN_MSIOF0_RXD_B, 0, 0, /* IP6_10_9 [2] */ FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B, /* IP6_8_6 [3] */ - FN_DACK1, FN_IRQ1, FN_INTC_IRQ1_N, FN_SSI_WS6_B, - FN_SSI_SDATA8_C, 0, 0, 0, + FN_DACK1, FN_IRQ1, 0, FN_SSI_WS6_B, FN_SSI_SDATA8_C, 0, 0, 0, /* IP6_5_3 [3] */ FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B, FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0, /* IP6_2_0 [3] */ - FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B, - FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, )) + FN_DACK0, FN_IRQ0, 0, FN_SSI_SCK6_B, FN_VI1_VSYNC_N, + FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32, GROUP(1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3), diff --git a/drivers/pinctrl/renesas/pfc-r8a7791.c b/drivers/pinctrl/renesas/pfc-r8a7791.c index fe4ccab6b0b8..e3b886b95545 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7791.c +++ b/drivers/pinctrl/renesas/pfc-r8a7791.c @@ -234,11 +234,11 @@ enum { FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2, FN_SCIFA2_RXD, FN_FMIN_E, FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD, - FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N, - FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N, - FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, - FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N, - FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N, + FN_IRQ0, FN_SCIFB1_RXD_D, + FN_IRQ1, FN_SCIFB1_SCK_C, + FN_IRQ2, FN_SCIFB1_TXD_D, + FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, + FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E, FN_IRQ5, FN_HTX1_C, FN_I2C1_SCL_E, FN_MSIOF2_SCK_E, FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, FN_I2C1_SDA_E, FN_MSIOF2_SYNC_E, FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, FN_GPS_CLK_C, FN_GPS_CLK_D, @@ -606,12 +606,12 @@ enum { AUDIO_CLKC_MARK, SCIFB0_SCK_C_MARK, MSIOF1_SYNC_B_MARK, RX2_MARK, SCIFA2_RXD_MARK, FMIN_E_MARK, AUDIO_CLKOUT_MARK, MSIOF1_SS1_B_MARK, TX2_MARK, SCIFA2_TXD_MARK, - IRQ0_MARK, SCIFB1_RXD_D_MARK, INTC_IRQ0_N_MARK, - IRQ1_MARK, SCIFB1_SCK_C_MARK, INTC_IRQ1_N_MARK, - IRQ2_MARK, SCIFB1_TXD_D_MARK, INTC_IRQ2_N_MARK, - IRQ3_MARK, I2C4_SCL_C_MARK, MSIOF2_TXD_E_MARK, INTC_IRQ3_N_MARK, + IRQ0_MARK, SCIFB1_RXD_D_MARK, + IRQ1_MARK, SCIFB1_SCK_C_MARK, + IRQ2_MARK, SCIFB1_TXD_D_MARK, + IRQ3_MARK, I2C4_SCL_C_MARK, MSIOF2_TXD_E_MARK, IRQ4_MARK, HRX1_C_MARK, I2C4_SDA_C_MARK, - MSIOF2_RXD_E_MARK, INTC_IRQ4_N_MARK, + MSIOF2_RXD_E_MARK, IRQ5_MARK, HTX1_C_MARK, I2C1_SCL_E_MARK, MSIOF2_SCK_E_MARK, IRQ6_MARK, HSCK1_C_MARK, MSIOF1_SS2_B_MARK, I2C1_SDA_E_MARK, MSIOF2_SYNC_E_MARK, @@ -1140,22 +1140,17 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0), PINMUX_IPSR_GPSR(IP6_9_8, IRQ0), PINMUX_IPSR_MSEL(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3), - PINMUX_IPSR_GPSR(IP6_9_8, INTC_IRQ0_N), PINMUX_IPSR_GPSR(IP6_11_10, IRQ1), PINMUX_IPSR_MSEL(IP6_11_10, SCIFB1_SCK_C, SEL_SCIFB1_2), - PINMUX_IPSR_GPSR(IP6_11_10, INTC_IRQ1_N), PINMUX_IPSR_GPSR(IP6_13_12, IRQ2), PINMUX_IPSR_MSEL(IP6_13_12, SCIFB1_TXD_D, SEL_SCIFB1_3), - PINMUX_IPSR_GPSR(IP6_13_12, INTC_IRQ2_N), PINMUX_IPSR_GPSR(IP6_15_14, IRQ3), PINMUX_IPSR_MSEL(IP6_15_14, I2C4_SCL_C, SEL_I2C4_2), PINMUX_IPSR_MSEL(IP6_15_14, MSIOF2_TXD_E, SEL_SOF2_4), - PINMUX_IPSR_GPSR(IP6_15_14, INTC_IRQ4_N), PINMUX_IPSR_GPSR(IP6_18_16, IRQ4), PINMUX_IPSR_MSEL(IP6_18_16, HRX1_C, SEL_HSCIF1_2), PINMUX_IPSR_MSEL(IP6_18_16, I2C4_SDA_C, SEL_I2C4_2), PINMUX_IPSR_MSEL(IP6_18_16, MSIOF2_RXD_E, SEL_SOF2_4), - PINMUX_IPSR_GPSR(IP6_18_16, INTC_IRQ4_N), PINMUX_IPSR_GPSR(IP6_20_19, IRQ5), PINMUX_IPSR_MSEL(IP6_20_19, HTX1_C, SEL_HSCIF1_2), PINMUX_IPSR_MSEL(IP6_20_19, I2C1_SCL_E, SEL_I2C1_4), @@ -6033,15 +6028,15 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_IRQ5, FN_HTX1_C, FN_I2C1_SCL_E, FN_MSIOF2_SCK_E, /* IP6_18_16 [3] */ FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E, - FN_INTC_IRQ4_N, 0, 0, 0, + 0, 0, 0, 0, /* IP6_15_14 [2] */ - FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N, + FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, 0, /* IP6_13_12 [2] */ - FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, 0, + FN_IRQ2, FN_SCIFB1_TXD_D, 0, 0, /* IP6_11_10 [2] */ - FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N, 0, + FN_IRQ1, FN_SCIFB1_SCK_C, 0, 0, /* IP6_9_8 [2] */ - FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N, 0, + FN_IRQ0, FN_SCIFB1_RXD_D, 0, 0, /* IP6_7_6 [2] */ FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD, /* IP6_5_3 [3] */ diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c b/drivers/pinctrl/renesas/pfc-r8a77990.c index f44c7da3ec16..b7ab4c520ae5 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77990.c +++ b/drivers/pinctrl/renesas/pfc-r8a77990.c @@ -2339,6 +2339,16 @@ static const unsigned int intc_ex_irq5_mux[] = { IRQ5_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_R8A77990 +/* - MLB+ ------------------------------------------------------------------- */ +static const unsigned int mlb_3pin_pins[] = { + RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), +}; +static const unsigned int mlb_3pin_mux[] = { + MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK, +}; +#endif /* CONFIG_PINCTRL_PFC_R8A77990 */ + /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* SCK */ @@ -3842,7 +3852,7 @@ static const unsigned int vin5_clk_b_mux[] = { static const struct { struct sh_pfc_pin_group common[255]; #ifdef CONFIG_PINCTRL_PFC_R8A77990 - struct sh_pfc_pin_group automotive[21]; + struct sh_pfc_pin_group automotive[22]; #endif } pinmux_groups = { .common = { @@ -4125,6 +4135,7 @@ static const struct { SH_PFC_PIN_GROUP(drif3_ctrl_b), SH_PFC_PIN_GROUP(drif3_data0_b), SH_PFC_PIN_GROUP(drif3_data1_b), + SH_PFC_PIN_GROUP(mlb_3pin), } #endif /* CONFIG_PINCTRL_PFC_R8A77990 */ }; @@ -4315,6 +4326,12 @@ static const char * const intc_ex_groups[] = { "intc_ex_irq5", }; +#ifdef CONFIG_PINCTRL_PFC_R8A77990 +static const char * const mlb_3pin_groups[] = { + "mlb_3pin", +}; +#endif /* CONFIG_PINCTRL_PFC_R8A77990 */ + static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -4569,7 +4586,7 @@ static const char * const vin5_groups[] = { static const struct { struct sh_pfc_function common[49]; #ifdef CONFIG_PINCTRL_PFC_R8A77990 - struct sh_pfc_function automotive[4]; + struct sh_pfc_function automotive[5]; #endif } pinmux_functions = { .common = { @@ -4629,6 +4646,7 @@ static const struct { SH_PFC_FUNCTION(drif1), SH_PFC_FUNCTION(drif2), SH_PFC_FUNCTION(drif3), + SH_PFC_FUNCTION(mlb_3pin), } #endif /* CONFIG_PINCTRL_PFC_R8A77990 */ }; diff --git a/drivers/pinctrl/renesas/pfc-r8a77995.c b/drivers/pinctrl/renesas/pfc-r8a77995.c index c56e1e4c13b3..5cbbd43f3f21 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77995.c +++ b/drivers/pinctrl/renesas/pfc-r8a77995.c @@ -1257,6 +1257,14 @@ static const unsigned int i2c3_b_mux[] = { SCL3_B_MARK, SDA3_B_MARK, }; +/* - MLB+ ------------------------------------------------------------------- */ +static const unsigned int mlb_3pin_pins[] = { + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), +}; +static const unsigned int mlb_3pin_mux[] = { + MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK, +}; + /* - MMC ------------------------------------------------------------------- */ static const unsigned int mmc_data1_pins[] = { /* D0 */ @@ -2049,6 +2057,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(i2c2_b), SH_PFC_PIN_GROUP(i2c3_a), SH_PFC_PIN_GROUP(i2c3_b), + SH_PFC_PIN_GROUP(mlb_3pin), SH_PFC_PIN_GROUP(mmc_data1), SH_PFC_PIN_GROUP(mmc_data4), SH_PFC_PIN_GROUP(mmc_data8), @@ -2210,6 +2219,10 @@ static const char * const i2c3_groups[] = { "i2c3_b", }; +static const char * const mlb_3pin_groups[] = { + "mlb_3pin", +}; + static const char * const mmc_groups[] = { "mmc_data1", "mmc_data4", @@ -2217,6 +2230,49 @@ static const char * const mmc_groups[] = { "mmc_ctrl", }; +static const char * const msiof0_groups[] = { + "msiof0_clk", + "msiof0_sync", + "msiof0_ss1", + "msiof0_ss2", + "msiof0_txd", + "msiof0_rxd", +}; + +static const char * const msiof1_groups[] = { + "msiof1_clk", + "msiof1_sync", + "msiof1_ss1", + "msiof1_ss2", + "msiof1_txd", + "msiof1_rxd", +}; + +static const char * const msiof2_groups[] = { + "msiof2_clk", + "msiof2_sync_a", + "msiof2_sync_b", + "msiof2_ss1", + "msiof2_ss2", + "msiof2_txd", + "msiof2_rxd", +}; + +static const char * const msiof3_groups[] = { + "msiof3_clk_a", + "msiof3_sync_a", + "msiof3_ss1_a", + "msiof3_ss2_a", + "msiof3_txd_a", + "msiof3_rxd_a", + "msiof3_clk_b", + "msiof3_sync_b", + "msiof3_ss1_b", + "msiof3_ss2_b", + "msiof3_txd_b", + "msiof3_rxd_b", +}; + static const char * const pwm0_groups[] = { "pwm0_a", "pwm0_b", @@ -2314,49 +2370,6 @@ static const char * const vin4_groups[] = { "vin4_clk", }; -static const char * const msiof0_groups[] = { - "msiof0_clk", - "msiof0_sync", - "msiof0_ss1", - "msiof0_ss2", - "msiof0_txd", - "msiof0_rxd", -}; - -static const char * const msiof1_groups[] = { - "msiof1_clk", - "msiof1_sync", - "msiof1_ss1", - "msiof1_ss2", - "msiof1_txd", - "msiof1_rxd", -}; - -static const char * const msiof2_groups[] = { - "msiof2_clk", - "msiof2_sync_a", - "msiof2_sync_b", - "msiof2_ss1", - "msiof2_ss2", - "msiof2_txd", - "msiof2_rxd", -}; - -static const char * const msiof3_groups[] = { - "msiof3_clk_a", - "msiof3_sync_a", - "msiof3_ss1_a", - "msiof3_ss2_a", - "msiof3_txd_a", - "msiof3_rxd_a", - "msiof3_clk_b", - "msiof3_sync_b", - "msiof3_ss1_b", - "msiof3_ss2_b", - "msiof3_txd_b", - "msiof3_rxd_b", -}; - static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(audio_clk), SH_PFC_FUNCTION(avb0), @@ -2370,6 +2383,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(i2c1), SH_PFC_FUNCTION(i2c2), SH_PFC_FUNCTION(i2c3), + SH_PFC_FUNCTION(mlb_3pin), SH_PFC_FUNCTION(mmc), SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), diff --git a/drivers/pinctrl/renesas/pfc-r8a779a0.c b/drivers/pinctrl/renesas/pfc-r8a779a0.c index 83580385c3ca..aeb0905998ae 100644 --- a/drivers/pinctrl/renesas/pfc-r8a779a0.c +++ b/drivers/pinctrl/renesas/pfc-r8a779a0.c @@ -576,23 +576,23 @@ FM(IP0SR5_27_24) IP0SR5_27_24 FM(IP1SR5_27_24) IP1SR5_27_24 FM(IP2SR5_27_24) IP2 FM(IP0SR5_31_28) IP0SR5_31_28 FM(IP1SR5_31_28) IP1SR5_31_28 FM(IP2SR5_31_28) IP2SR5_31_28 /* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ -#define MOD_SEL2_14_15 FM(SEL_I2C6_0) F_(0, 0) F_(0, 0) FM(SEL_I2C6_3) -#define MOD_SEL2_12_13 FM(SEL_I2C5_0) F_(0, 0) F_(0, 0) FM(SEL_I2C5_3) -#define MOD_SEL2_10_11 FM(SEL_I2C4_0) F_(0, 0) F_(0, 0) FM(SEL_I2C4_3) -#define MOD_SEL2_8_9 FM(SEL_I2C3_0) F_(0, 0) F_(0, 0) FM(SEL_I2C3_3) -#define MOD_SEL2_6_7 FM(SEL_I2C2_0) F_(0, 0) F_(0, 0) FM(SEL_I2C2_3) -#define MOD_SEL2_4_5 FM(SEL_I2C1_0) F_(0, 0) F_(0, 0) FM(SEL_I2C1_3) -#define MOD_SEL2_2_3 FM(SEL_I2C0_0) F_(0, 0) F_(0, 0) FM(SEL_I2C0_3) +#define MOD_SEL2_15_14 FM(SEL_I2C6_0) F_(0, 0) F_(0, 0) FM(SEL_I2C6_3) +#define MOD_SEL2_13_12 FM(SEL_I2C5_0) F_(0, 0) F_(0, 0) FM(SEL_I2C5_3) +#define MOD_SEL2_11_10 FM(SEL_I2C4_0) F_(0, 0) F_(0, 0) FM(SEL_I2C4_3) +#define MOD_SEL2_9_8 FM(SEL_I2C3_0) F_(0, 0) F_(0, 0) FM(SEL_I2C3_3) +#define MOD_SEL2_7_6 FM(SEL_I2C2_0) F_(0, 0) F_(0, 0) FM(SEL_I2C2_3) +#define MOD_SEL2_5_4 FM(SEL_I2C1_0) F_(0, 0) F_(0, 0) FM(SEL_I2C1_3) +#define MOD_SEL2_3_2 FM(SEL_I2C0_0) F_(0, 0) F_(0, 0) FM(SEL_I2C0_3) #define PINMUX_MOD_SELS \ \ -MOD_SEL2_14_15 \ -MOD_SEL2_12_13 \ -MOD_SEL2_10_11 \ -MOD_SEL2_8_9 \ -MOD_SEL2_6_7 \ -MOD_SEL2_4_5 \ -MOD_SEL2_2_3 +MOD_SEL2_15_14 \ +MOD_SEL2_13_12 \ +MOD_SEL2_11_10 \ +MOD_SEL2_9_8 \ +MOD_SEL2_7_6 \ +MOD_SEL2_5_4 \ +MOD_SEL2_3_2 #define PINMUX_PHYS \ FM(SCL0) FM(SDA0) FM(SCL1) FM(SDA1) FM(SCL2) FM(SDA2) FM(SCL3) FM(SDA3) \ @@ -3696,13 +3696,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* RESERVED 19, 18, 17, 16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - MOD_SEL2_14_15 - MOD_SEL2_12_13 - MOD_SEL2_10_11 - MOD_SEL2_8_9 - MOD_SEL2_6_7 - MOD_SEL2_4_5 - MOD_SEL2_2_3 + MOD_SEL2_15_14 + MOD_SEL2_13_12 + MOD_SEL2_11_10 + MOD_SEL2_9_8 + MOD_SEL2_7_6 + MOD_SEL2_5_4 + MOD_SEL2_3_2 0, 0, 0, 0, )) }, diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index ccee9c9e2e22..cb805502fb0f 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -1090,12 +1090,12 @@ static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl) } if (of_args.args[0] != 0 || of_args.args[1] != 0 || - of_args.args[2] != ARRAY_SIZE(rzg2l_gpio_names)) { + of_args.args[2] != pctrl->data->n_port_pins) { dev_err(pctrl->dev, "gpio-ranges does not match selected SOC\n"); return -EINVAL; } - chip->names = rzg2l_gpio_names; + chip->names = pctrl->data->port_pins; chip->request = rzg2l_gpio_request; chip->free = rzg2l_gpio_free; chip->get_direction = rzg2l_gpio_get_direction; diff --git a/drivers/pinctrl/renesas/pinctrl.c b/drivers/pinctrl/renesas/pinctrl.c index 96b9de974246..401e64725032 100644 --- a/drivers/pinctrl/renesas/pinctrl.c +++ b/drivers/pinctrl/renesas/pinctrl.c @@ -397,7 +397,7 @@ static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev, spin_lock_irqsave(&pfc->lock, flags); - if (!pfc->gpio) { + if (!pfc->gpio && !cfg->mux_mark) { /* If GPIOs are handled externally the pin mux type needs to be * set to GPIO here. */ diff --git a/drivers/pinctrl/sunplus/Kconfig b/drivers/pinctrl/sunplus/Kconfig new file mode 100644 index 000000000000..4b5c47c193d9 --- /dev/null +++ b/drivers/pinctrl/sunplus/Kconfig @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Sunplus Pin control driver configuration +# + +config PINCTRL_SPPCTL + tristate "Sunplus SP7021 PinMux and GPIO driver" + depends on SOC_SP7021 + depends on OF && HAS_IOMEM + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + select GENERIC_PINCONF + select PINCONF + select PINMUX + select GPIOLIB + select OF_GPIO + help + Say Y here to support Sunplus SP7021 pinmux controller. + This driver requires the pinctrl framework. + GPIO is provided by the same driver. + To compile this driver as a module, choose M here. + The module will be called sppinctrl. diff --git a/drivers/pinctrl/sunplus/Makefile b/drivers/pinctrl/sunplus/Makefile new file mode 100644 index 000000000000..a26952c5286a --- /dev/null +++ b/drivers/pinctrl/sunplus/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Makefile for the Sunplus Pin control drivers. +# +obj-$(CONFIG_PINCTRL_SPPCTL) += sppinctrl.o +sppinctrl-objs := sppctl.o sppctl_sp7021.o diff --git a/drivers/pinctrl/sunplus/sppctl.c b/drivers/pinctrl/sunplus/sppctl.c new file mode 100644 index 000000000000..3ba47040ac42 --- /dev/null +++ b/drivers/pinctrl/sunplus/sppctl.c @@ -0,0 +1,1118 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SP7021 Pin Controller Driver. + * Copyright (C) Sunplus Tech / Tibbo Tech. + */ + +#include <linux/bitfield.h> +#include <linux/device.h> +#include <linux/err.h> +#include <linux/gpio/driver.h> +#include <linux/init.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/overflow.h> +#include <linux/platform_device.h> +#include <linux/seq_file.h> +#include <linux/slab.h> + +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinmux.h> + +#include <dt-bindings/pinctrl/sppctl-sp7021.h> + +#include "../core.h" +#include "../pinctrl-utils.h" + +#include "sppctl.h" + +struct sppctl_gpio_chip { + void __iomem *gpioxt_base; /* MASTER, OE, OUT, IN, I_INV, O_INV, OD */ + void __iomem *first_base; /* GPIO_FIRST */ + + struct gpio_chip chip; + spinlock_t lock; /* lock for accessing OE register */ +}; + +static inline u32 sppctl_first_readl(struct sppctl_gpio_chip *spp_gchip, u32 off) +{ + return readl(spp_gchip->first_base + SPPCTL_GPIO_OFF_FIRST + off); +} + +static inline void sppctl_first_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, u32 off) +{ + writel(val, spp_gchip->first_base + SPPCTL_GPIO_OFF_FIRST + off); +} + +static inline u32 sppctl_gpio_master_readl(struct sppctl_gpio_chip *spp_gchip, u32 off) +{ + return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_MASTER + off); +} + +static inline void sppctl_gpio_master_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, + u32 off) +{ + writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_MASTER + off); +} + +static inline u32 sppctl_gpio_oe_readl(struct sppctl_gpio_chip *spp_gchip, u32 off) +{ + return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OE + off); +} + +static inline void sppctl_gpio_oe_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, u32 off) +{ + writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OE + off); +} + +static inline void sppctl_gpio_out_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, u32 off) +{ + writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OUT + off); +} + +static inline u32 sppctl_gpio_in_readl(struct sppctl_gpio_chip *spp_gchip, u32 off) +{ + return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_IN + off); +} + +static inline u32 sppctl_gpio_iinv_readl(struct sppctl_gpio_chip *spp_gchip, u32 off) +{ + return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_IINV + off); +} + +static inline void sppctl_gpio_iinv_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, + u32 off) +{ + writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_IINV + off); +} + +static inline u32 sppctl_gpio_oinv_readl(struct sppctl_gpio_chip *spp_gchip, u32 off) +{ + return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OINV + off); +} + +static inline void sppctl_gpio_oinv_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, + u32 off) +{ + writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OINV + off); +} + +static inline u32 sppctl_gpio_od_readl(struct sppctl_gpio_chip *spp_gchip, u32 off) +{ + return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OD + off); +} + +static inline void sppctl_gpio_od_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, u32 off) +{ + writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OD + off); +} + +static inline u32 sppctl_get_reg_and_bit_offset(unsigned int offset, u32 *reg_off) +{ + u32 bit_off; + + /* Each register has 32 bits. */ + *reg_off = (offset / 32) * 4; + bit_off = offset % 32; + + return bit_off; +} + +static inline u32 sppctl_get_moon_reg_and_bit_offset(unsigned int offset, u32 *reg_off) +{ + u32 bit_off; + + /* + * Each MOON register has 32 bits. Upper 16-bit word are mask-fields. + * The lower 16-bit word are the control-fields. The corresponding + * bits in mask-field should be set then you can write something to + * control-field. + */ + *reg_off = (offset / 16) * 4; + bit_off = offset % 16; + + return bit_off; +} + +static inline u32 sppctl_prep_moon_reg_and_offset(unsigned int offset, u32 *reg_off, int val) +{ + u32 bit_off; + + bit_off = sppctl_get_moon_reg_and_bit_offset(offset, reg_off); + if (val) + return SPPCTL_SET_MOON_REG_BIT(bit_off); + else + return SPPCTL_CLR_MOON_REG_BIT(bit_off); +} + +/** + * sppctl_func_set() - Set pin of fully-pinmux function. + * + * Mask-fields and control-fields of fully-pinmux function of SP7021 are + * arranged as shown below: + * + * func# | register | mask-field | control-field + * -------+----------+--------------+--------------- + * 0 | base[0] | (22 : 16) | ( 6 : 0) + * 1 | base[0] | (30 : 24) | (14 : 8) + * 2 | base[1] | (22 : 16) | ( 6 : 0) + * 3 | baeg[1] | (30 : 24) | (14 : 8) + * : | : | : | : + * + * where mask-fields are used to protect control-fields from write-in + * accidentally. Set the corresponding bits in the mask-field before + * you write a value into a control-field. + * + * Control-fields are used to set where the function pin is going to + * be routed to. + * + * Note that mask-fields and control-fields of even number of 'func' + * are located at bits (22:16) and (6:0), while odd number of 'func's + * are located at bits (30:24) and (14:8). + */ +static void sppctl_func_set(struct sppctl_pdata *pctl, u8 func, u8 val) +{ + u32 reg, offset; + + /* + * Note that upper 16-bit word are mask-fields and lower 16-bit + * word are the control-fields. Set corresponding bits in mask- + * field before write to a control-field. + */ + reg = SPPCTL_FULLY_PINMUX_MASK_MASK | val; + + /* + * MUXF_L2SW_CLK_OUT is the first fully-pinmux pin + * and its register offset is 0. + */ + func -= MUXF_L2SW_CLK_OUT; + + /* + * Check if 'func' is an odd number or not. Mask and control- + * fields of odd number 'func' is located at upper portion of + * a register. Extra shift is needed. + */ + if (func & BIT(0)) + reg <<= SPPCTL_FULLY_PINMUX_UPPER_SHIFT; + + /* Convert func# to register offset w.r.t. base register. */ + offset = func * 2; + offset &= GENMASK(31, 2); + + writel(reg, pctl->moon2_base + offset); +} + +/** + * sppctl_gmx_set() - Set pin of group-pinmux. + * + * Mask-fields and control-fields of group-pinmux function of SP7021 are + * arranged as shown below: + * + * register | mask-fields | control-fields + * ----------+--------------+---------------- + * base[0] | (31 : 16) | (15 : 0) + * base[1] | (31 : 24) | (15 : 0) + * base[2] | (31 : 24) | (15 : 0) + * : | : | : + * + * where mask-fields are used to protect control-fields from write-in + * accidentally. Set the corresponding bits in the mask-field before + * you write a value into a control-field. + * + * Control-fields are used to set where the function pin is going to + * be routed to. A control-field consists of one or more bits. + */ +static void sppctl_gmx_set(struct sppctl_pdata *pctl, u8 reg_off, u8 bit_off, u8 bit_sz, + u8 val) +{ + u32 mask, reg; + + /* + * Note that upper 16-bit word are mask-fields and lower 16-bit + * word are the control-fields. Set corresponding bits in mask- + * field before write to a control-field. + */ + mask = GENMASK(bit_sz - 1, 0) << SPPCTL_MOON_REG_MASK_SHIFT; + reg = (mask | val) << bit_off; + + writel(reg, pctl->moon1_base + reg_off * 4); +} + +/** + * sppctl_first_get() - get bit of FIRST register. + * + * There are 4 FIRST registers. Each has 32 control-bits. + * Totally, there are 4 * 32 = 128 control-bits. + * Control-bits are arranged as shown below: + * + * registers | control-bits + * -----------+-------------- + * first[0] | (31 : 0) + * first[1] | (63 : 32) + * first[2] | (95 : 64) + * first[3] | (127 : 96) + * + * Each control-bit sets type of a GPIO pin. + * 0: a fully-pinmux pin + * 1: a GPIO or IOP pin + */ +static int sppctl_first_get(struct gpio_chip *chip, unsigned int offset) +{ + struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); + u32 reg_off, bit_off, reg; + + bit_off = sppctl_get_reg_and_bit_offset(offset, ®_off); + reg = sppctl_first_readl(spp_gchip, reg_off); + + return (reg & BIT(bit_off)) ? 1 : 0; +} + +/** + * sppctl_master_get() - get bit of MASTER register. + * + * There are 8 MASTER registers. Each has 16 mask-bits and 16 control-bits. + * Upper 16-bit of MASTER registers are mask-bits while lower 16-bit are + * control-bits. Totally, there are 128 mask-bits and 128 control-bits. + * They are arranged as shown below: + * + * register | mask-bits | control-bits + * -----------+-------------+-------------- + * master[0] | (15 : 0) | (15 : 0) + * master[1] | (31 : 16) | (31 : 16) + * master[2] | (47 : 32) | (47 : 32) + * : | : | : + * master[7] | (127 : 112) | (127 : 112) + * + * where mask-bits are used to protect control-bits from write-in + * accidentally. Set the corresponding mask-bit before you write + * a value into a control-bit. + * + * Each control-bit sets type of a GPIO pin when FIRST bit is 1. + * 0: a IOP pin + * 1: a GPIO pin + */ +static int sppctl_master_get(struct gpio_chip *chip, unsigned int offset) +{ + struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); + u32 reg_off, bit_off, reg; + + bit_off = sppctl_get_moon_reg_and_bit_offset(offset, ®_off); + reg = sppctl_gpio_master_readl(spp_gchip, reg_off); + return (reg & BIT(bit_off)) ? 1 : 0; +} + +static void sppctl_first_master_set(struct gpio_chip *chip, unsigned int offset, + enum mux_first_reg first, enum mux_master_reg master) +{ + struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); + u32 reg_off, bit_off, reg; + enum mux_first_reg val; + + /* FIRST register */ + if (first != mux_f_keep) { + bit_off = sppctl_get_reg_and_bit_offset(offset, ®_off); + reg = sppctl_first_readl(spp_gchip, reg_off); + val = (reg & BIT(bit_off)) ? mux_f_gpio : mux_f_mux; + + if (first != val) + switch (first) { + case mux_f_gpio: + reg |= BIT(bit_off); + sppctl_first_writel(spp_gchip, reg, reg_off); + break; + + case mux_f_mux: + reg &= ~BIT(bit_off); + sppctl_first_writel(spp_gchip, reg, reg_off); + break; + + case mux_f_keep: + break; + } + } + + /* MASTER register */ + if (master != mux_m_keep) { + reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, (master == mux_m_gpio)); + sppctl_gpio_master_writel(spp_gchip, reg, reg_off); + } +} + +static void sppctl_gpio_input_inv_set(struct gpio_chip *chip, unsigned int offset) +{ + struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); + u32 reg_off, reg; + + reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, 1); + sppctl_gpio_iinv_writel(spp_gchip, reg, reg_off); +} + +static void sppctl_gpio_output_inv_set(struct gpio_chip *chip, unsigned int offset) +{ + struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); + u32 reg_off, reg; + + reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, 1); + sppctl_gpio_oinv_writel(spp_gchip, reg, reg_off); +} + +static int sppctl_gpio_output_od_get(struct gpio_chip *chip, unsigned int offset) +{ + struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); + u32 reg_off, bit_off, reg; + + bit_off = sppctl_get_moon_reg_and_bit_offset(offset, ®_off); + reg = sppctl_gpio_od_readl(spp_gchip, reg_off); + + return (reg & BIT(bit_off)) ? 1 : 0; +} + +static void sppctl_gpio_output_od_set(struct gpio_chip *chip, unsigned int offset, + unsigned int val) +{ + struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); + u32 reg_off, reg; + + reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, val); + sppctl_gpio_od_writel(spp_gchip, reg, reg_off); +} + +static int sppctl_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) +{ + struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); + u32 reg_off, bit_off, reg; + + bit_off = sppctl_get_moon_reg_and_bit_offset(offset, ®_off); + reg = sppctl_gpio_oe_readl(spp_gchip, reg_off); + + return (reg & BIT(bit_off)) ? 0 : 1; +} + +static int sppctl_gpio_inv_get(struct gpio_chip *chip, unsigned int offset) +{ + struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); + u32 reg_off, bit_off, reg; + unsigned long flags; + + bit_off = sppctl_get_moon_reg_and_bit_offset(offset, ®_off); + + spin_lock_irqsave(&spp_gchip->lock, flags); + + if (sppctl_gpio_get_direction(chip, offset)) + reg = sppctl_gpio_iinv_readl(spp_gchip, reg_off); + else + reg = sppctl_gpio_oinv_readl(spp_gchip, reg_off); + + spin_unlock_irqrestore(&spp_gchip->lock, flags); + + return (reg & BIT(bit_off)) ? 1 : 0; +} + +static int sppctl_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) +{ + struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); + unsigned long flags; + u32 reg_off, reg; + + reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, 0); + + spin_lock_irqsave(&spp_gchip->lock, flags); + + sppctl_gpio_oe_writel(spp_gchip, reg, reg_off); + + spin_unlock_irqrestore(&spp_gchip->lock, flags); + return 0; +} + +static int sppctl_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, int val) +{ + struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); + unsigned long flags; + u32 reg_off, reg; + + reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, 1); + + spin_lock_irqsave(&spp_gchip->lock, flags); + + sppctl_gpio_oe_writel(spp_gchip, reg, reg_off); + + if (val < 0) { + spin_unlock_irqrestore(&spp_gchip->lock, flags); + return 0; + } + + reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, val); + sppctl_gpio_out_writel(spp_gchip, reg, reg_off); + + spin_unlock_irqrestore(&spp_gchip->lock, flags); + return 0; +} + +static int sppctl_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); + u32 reg_off, bit_off, reg; + + bit_off = sppctl_get_reg_and_bit_offset(offset, ®_off); + reg = sppctl_gpio_in_readl(spp_gchip, reg_off); + + return (reg & BIT(bit_off)) ? 1 : 0; +} + +static void sppctl_gpio_set(struct gpio_chip *chip, unsigned int offset, int val) +{ + struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); + u32 reg_off, reg; + + reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, val); + sppctl_gpio_out_writel(spp_gchip, reg, reg_off); +} + +static int sppctl_gpio_set_config(struct gpio_chip *chip, unsigned int offset, + unsigned long config) +{ + enum pin_config_param param = pinconf_to_config_param(config); + struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); + u32 reg_off, reg; + + switch (param) { + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, 1); + sppctl_gpio_od_writel(spp_gchip, reg, reg_off); + break; + + case PIN_CONFIG_INPUT_ENABLE: + break; + + case PIN_CONFIG_OUTPUT: + return sppctl_gpio_direction_output(chip, offset, 0); + + case PIN_CONFIG_PERSIST_STATE: + return -ENOTSUPP; + + default: + return -EINVAL; + } + + return 0; +} + +#ifdef CONFIG_DEBUG_FS +static void sppctl_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) +{ + const char *label; + int i; + + for (i = 0; i < chip->ngpio; i++) { + label = gpiochip_is_requested(chip, i); + if (!label) + label = ""; + + seq_printf(s, " gpio-%03d (%-16.16s | %-16.16s)", i + chip->base, + chip->names[i], label); + seq_printf(s, " %c", sppctl_gpio_get_direction(chip, i) ? 'I' : 'O'); + seq_printf(s, ":%d", sppctl_gpio_get(chip, i)); + seq_printf(s, " %s", sppctl_first_get(chip, i) ? "gpi" : "mux"); + seq_printf(s, " %s", sppctl_master_get(chip, i) ? "gpi" : "iop"); + seq_printf(s, " %s", sppctl_gpio_inv_get(chip, i) ? "inv" : " "); + seq_printf(s, " %s", sppctl_gpio_output_od_get(chip, i) ? "oDr" : ""); + seq_puts(s, "\n"); + } +} +#endif + +static int sppctl_gpio_new(struct platform_device *pdev, struct sppctl_pdata *pctl) +{ + struct sppctl_gpio_chip *spp_gchip; + struct gpio_chip *gchip; + int err; + + spp_gchip = devm_kzalloc(&pdev->dev, sizeof(*spp_gchip), GFP_KERNEL); + if (!spp_gchip) + return -ENOMEM; + pctl->spp_gchip = spp_gchip; + + spp_gchip->gpioxt_base = pctl->gpioxt_base; + spp_gchip->first_base = pctl->first_base; + spin_lock_init(&spp_gchip->lock); + + gchip = &spp_gchip->chip; + gchip->label = SPPCTL_MODULE_NAME; + gchip->parent = &pdev->dev; + gchip->owner = THIS_MODULE; + gchip->request = gpiochip_generic_request; + gchip->free = gpiochip_generic_free; + gchip->get_direction = sppctl_gpio_get_direction; + gchip->direction_input = sppctl_gpio_direction_input; + gchip->direction_output = sppctl_gpio_direction_output; + gchip->get = sppctl_gpio_get; + gchip->set = sppctl_gpio_set; + gchip->set_config = sppctl_gpio_set_config; +#ifdef CONFIG_DEBUG_FS + gchip->dbg_show = sppctl_gpio_dbg_show; +#endif + gchip->base = -1; + gchip->ngpio = sppctl_gpio_list_sz; + gchip->names = sppctl_gpio_list_s; + gchip->of_gpio_n_cells = 2; + + pctl->pctl_grange.npins = gchip->ngpio; + pctl->pctl_grange.name = gchip->label; + pctl->pctl_grange.gc = gchip; + + err = devm_gpiochip_add_data(&pdev->dev, gchip, spp_gchip); + if (err) + return dev_err_probe(&pdev->dev, err, "Failed to add gpiochip!\n"); + + return 0; +} + +static int sppctl_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *config) +{ + struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev); + unsigned int param = pinconf_to_config_param(*config); + unsigned int arg; + + switch (param) { + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + if (!sppctl_gpio_output_od_get(&pctl->spp_gchip->chip, pin)) + return -EINVAL; + arg = 0; + break; + + case PIN_CONFIG_OUTPUT: + if (!sppctl_first_get(&pctl->spp_gchip->chip, pin)) + return -EINVAL; + if (!sppctl_master_get(&pctl->spp_gchip->chip, pin)) + return -EINVAL; + if (sppctl_gpio_get_direction(&pctl->spp_gchip->chip, pin)) + return -EINVAL; + arg = sppctl_gpio_get(&pctl->spp_gchip->chip, pin); + break; + + default: + return -EOPNOTSUPP; + } + *config = pinconf_to_config_packed(param, arg); + + return 0; +} + +static int sppctl_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned int num_configs) +{ + struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev); + int i; + + /* Special handling for IOP pins */ + if (configs[0] == SPPCTL_IOP_CONFIGS) { + sppctl_first_master_set(&pctl->spp_gchip->chip, pin, mux_f_gpio, mux_m_iop); + return 0; + } + + for (i = 0; i < num_configs; i++) { + if (configs[i] & SPPCTL_PCTL_L_OUT) + sppctl_gpio_direction_output(&pctl->spp_gchip->chip, pin, 0); + if (configs[i] & SPPCTL_PCTL_L_OU1) + sppctl_gpio_direction_output(&pctl->spp_gchip->chip, pin, 1); + if (configs[i] & SPPCTL_PCTL_L_INV) + sppctl_gpio_input_inv_set(&pctl->spp_gchip->chip, pin); + if (configs[i] & SPPCTL_PCTL_L_ONV) + sppctl_gpio_output_inv_set(&pctl->spp_gchip->chip, pin); + if (configs[i] & SPPCTL_PCTL_L_ODR) + sppctl_gpio_output_od_set(&pctl->spp_gchip->chip, pin, 1); + } + + return 0; +} + +static const struct pinconf_ops sppctl_pconf_ops = { + .is_generic = true, + .pin_config_get = sppctl_pin_config_get, + .pin_config_set = sppctl_pin_config_set, +}; + +static int sppctl_get_functions_count(struct pinctrl_dev *pctldev) +{ + return sppctl_list_funcs_sz; +} + +static const char *sppctl_get_function_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + return sppctl_list_funcs[selector].name; +} + +static int sppctl_get_function_groups(struct pinctrl_dev *pctldev, unsigned int selector, + const char * const **groups, unsigned int *num_groups) +{ + struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev); + const struct sppctl_func *f = &sppctl_list_funcs[selector]; + int i; + + *num_groups = 0; + switch (f->type) { + case pinmux_type_fpmx: + *num_groups = sppctl_pmux_list_sz; + *groups = sppctl_pmux_list_s; + break; + + case pinmux_type_grp: + if (!f->grps) + break; + + *num_groups = f->gnum; + for (i = 0; i < pctl->unq_grps_sz; i++) + if (pctl->g2fp_maps[i].f_idx == selector) + break; + *groups = &pctl->unq_grps[i]; + break; + + default: + dev_err(pctldev->dev, "Unknown pinmux (selector: %d, type: %d)\n", + selector, f->type); + break; + } + + return 0; +} + +/** + * sppctl_fully_pinmux_conv - Convert GPIO# to fully-pinmux control-field setting + * + * Each fully-pinmux function can be mapped to any of GPIO 8 ~ 71 by + * settings its control-field. Refer to following table: + * + * control-field | GPIO + * --------------+-------- + * 0 | No map + * 1 | 8 + * 2 | 9 + * 3 | 10 + * : | : + * 65 | 71 + */ +static inline int sppctl_fully_pinmux_conv(unsigned int offset) +{ + return (offset < 8) ? 0 : offset - 7; +} + +static int sppctl_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector, + unsigned int group_selector) +{ + const struct sppctl_func *f = &sppctl_list_funcs[func_selector]; + struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev); + struct grp2fp_map g2fpm = pctl->g2fp_maps[group_selector]; + int i; + + switch (f->type) { + case pinmux_type_fpmx: + sppctl_first_master_set(&pctl->spp_gchip->chip, group_selector, + mux_f_mux, mux_m_keep); + sppctl_func_set(pctl, func_selector, sppctl_fully_pinmux_conv(group_selector)); + break; + + case pinmux_type_grp: + for (i = 0; i < f->grps[g2fpm.g_idx].pnum; i++) + sppctl_first_master_set(&pctl->spp_gchip->chip, + f->grps[g2fpm.g_idx].pins[i], + mux_f_mux, mux_m_keep); + sppctl_gmx_set(pctl, f->roff, f->boff, f->blen, f->grps[g2fpm.g_idx].gval); + break; + + default: + dev_err(pctldev->dev, "Unknown pinmux type (func_selector: %d, type: %d)\n", + func_selector, f->type); + break; + } + + return 0; +} + +static int sppctl_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, unsigned int offset) +{ + struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev); + int g_f, g_m; + + g_f = sppctl_first_get(&pctl->spp_gchip->chip, offset); + g_m = sppctl_master_get(&pctl->spp_gchip->chip, offset); + if (g_f == mux_f_gpio && g_m == mux_m_gpio) + return 0; + + sppctl_first_master_set(&pctl->spp_gchip->chip, offset, mux_f_gpio, mux_m_gpio); + return 0; +} + +static const struct pinmux_ops sppctl_pinmux_ops = { + .get_functions_count = sppctl_get_functions_count, + .get_function_name = sppctl_get_function_name, + .get_function_groups = sppctl_get_function_groups, + .set_mux = sppctl_set_mux, + .gpio_request_enable = sppctl_gpio_request_enable, + .strict = true, +}; + +static int sppctl_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev); + + return pctl->unq_grps_sz; +} + +static const char *sppctl_get_group_name(struct pinctrl_dev *pctldev, unsigned int selector) +{ + struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev); + + return pctl->unq_grps[selector]; +} + +static int sppctl_get_group_pins(struct pinctrl_dev *pctldev, unsigned int selector, + const unsigned int **pins, unsigned int *num_pins) +{ + struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev); + struct grp2fp_map g2fpm = pctl->g2fp_maps[selector]; + const struct sppctl_func *f; + + f = &sppctl_list_funcs[g2fpm.f_idx]; + *num_pins = 0; + + /* Except group-pinmux, each group has 1 pin. */ + if (f->type != pinmux_type_grp) { + *num_pins = 1; + *pins = &sppctl_pins_gpio[selector]; + return 0; + } + + /* Group-pinmux may have more than one pin. */ + if (!f->grps) + return 0; + + if (f->gnum < 1) + return 0; + + *num_pins = f->grps[g2fpm.g_idx].pnum; + *pins = f->grps[g2fpm.g_idx].pins; + + return 0; +} + +#ifdef CONFIG_DEBUG_FS +static void sppctl_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, + unsigned int offset) +{ + struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev); + const char *pin_type; + u8 first, master; + + first = sppctl_first_get(&pctl->spp_gchip->chip, offset); + master = sppctl_master_get(&pctl->spp_gchip->chip, offset); + if (first) + if (master) + pin_type = "GPIO"; + else + pin_type = " IOP"; + else + pin_type = " MUX"; + seq_printf(s, " %s", pin_type); +} +#endif + +static int sppctl_dt_node_to_map(struct pinctrl_dev *pctldev, struct device_node *np_config, + struct pinctrl_map **map, unsigned int *num_maps) +{ + struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev); + int nmG = of_property_count_strings(np_config, "groups"); + const struct sppctl_func *f = NULL; + u8 pin_num, pin_type, pin_func; + struct device_node *parent; + unsigned long *configs; + struct property *prop; + const char *s_f, *s_g; + + const __be32 *list; + u32 dt_pin, dt_fun; + int i, size = 0; + + list = of_get_property(np_config, "sunplus,pins", &size); + + if (nmG <= 0) + nmG = 0; + + parent = of_get_parent(np_config); + *num_maps = size / sizeof(*list); + + /* + * Process property: + * sunplus,pins = < u32 u32 u32 ... >; + * + * Each 32-bit integer defines a individual pin in which: + * + * Bit 32~24: defines GPIO pin number. Its range is 0 ~ 98. + * Bit 23~16: defines types: (1) fully-pinmux pins + * (2) IO processor pins + * (3) digital GPIO pins + * Bit 15~8: defines pins of peripherals (which are defined in + * 'include/dt-binging/pinctrl/sppctl.h'). + * Bit 7~0: defines types or initial-state of digital GPIO pins. + */ + for (i = 0; i < (*num_maps); i++) { + dt_pin = be32_to_cpu(list[i]); + pin_num = FIELD_GET(GENMASK(31, 24), dt_pin); + + if (pin_num >= sppctl_pins_all_sz) { + dev_err(pctldev->dev, "Invalid pin property at index %d (0x%08x)\n", + i, dt_pin); + return -EINVAL; + } + } + + *map = kcalloc(*num_maps + nmG, sizeof(**map), GFP_KERNEL); + for (i = 0; i < (*num_maps); i++) { + dt_pin = be32_to_cpu(list[i]); + pin_num = FIELD_GET(GENMASK(31, 24), dt_pin); + pin_type = FIELD_GET(GENMASK(23, 16), dt_pin); + pin_func = FIELD_GET(GENMASK(15, 8), dt_pin); + (*map)[i].name = parent->name; + + if (pin_type == SPPCTL_PCTL_G_GPIO) { + /* A digital GPIO pin */ + (*map)[i].type = PIN_MAP_TYPE_CONFIGS_PIN; + (*map)[i].data.configs.num_configs = 1; + (*map)[i].data.configs.group_or_pin = pin_get_name(pctldev, pin_num); + configs = kmalloc(sizeof(*configs), GFP_KERNEL); + *configs = FIELD_GET(GENMASK(7, 0), dt_pin); + (*map)[i].data.configs.configs = configs; + + dev_dbg(pctldev->dev, "%s: GPIO (%s)\n", + (*map)[i].data.configs.group_or_pin, + (*configs & (SPPCTL_PCTL_L_OUT | SPPCTL_PCTL_L_OU1)) ? + "OUT" : "IN"); + } else if (pin_type == SPPCTL_PCTL_G_IOPP) { + /* A IO Processor (IOP) pin */ + (*map)[i].type = PIN_MAP_TYPE_CONFIGS_PIN; + (*map)[i].data.configs.num_configs = 1; + (*map)[i].data.configs.group_or_pin = pin_get_name(pctldev, pin_num); + configs = kmalloc(sizeof(*configs), GFP_KERNEL); + *configs = SPPCTL_IOP_CONFIGS; + (*map)[i].data.configs.configs = configs; + + dev_dbg(pctldev->dev, "%s: IOP\n", + (*map)[i].data.configs.group_or_pin); + } else { + /* A fully-pinmux pin */ + (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP; + (*map)[i].data.mux.function = sppctl_list_funcs[pin_func].name; + (*map)[i].data.mux.group = pin_get_name(pctldev, pin_num); + + dev_dbg(pctldev->dev, "%s: %s\n", (*map)[i].data.mux.group, + (*map)[i].data.mux.function); + } + } + + /* + * Process properties: + * function = "xxx"; + * groups = "yyy"; + */ + if (nmG > 0 && of_property_read_string(np_config, "function", &s_f) == 0) { + of_property_for_each_string(np_config, "groups", prop, s_g) { + (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; + (*map)[*num_maps].data.mux.function = s_f; + (*map)[*num_maps].data.mux.group = s_g; + (*num_maps)++; + + dev_dbg(pctldev->dev, "%s: %s\n", s_f, s_g); + } + } + + /* + * Process property: + * sunplus,zerofunc = < u32 u32 u32 ...> + */ + list = of_get_property(np_config, "sunplus,zerofunc", &size); + if (list) { + for (i = 0; i < (size / sizeof(*list)); i++) { + dt_fun = be32_to_cpu(list[i]); + if (dt_fun >= sppctl_list_funcs_sz) { + dev_err(pctldev->dev, "Zero-func %d out of range!\n", + dt_fun); + continue; + } + + f = &sppctl_list_funcs[dt_fun]; + switch (f->type) { + case pinmux_type_fpmx: + sppctl_func_set(pctl, dt_fun, 0); + dev_dbg(pctldev->dev, "%s: No map\n", f->name); + break; + + case pinmux_type_grp: + sppctl_gmx_set(pctl, f->roff, f->boff, f->blen, 0); + dev_dbg(pctldev->dev, "%s: No map\n", f->name); + break; + + default: + dev_err(pctldev->dev, "Wrong zero-group: %d (%s)\n", + dt_fun, f->name); + break; + } + } + } + + of_node_put(parent); + dev_dbg(pctldev->dev, "%d pins mapped\n", *num_maps); + return 0; +} + +static const struct pinctrl_ops sppctl_pctl_ops = { + .get_groups_count = sppctl_get_groups_count, + .get_group_name = sppctl_get_group_name, + .get_group_pins = sppctl_get_group_pins, +#ifdef CONFIG_DEBUG_FS + .pin_dbg_show = sppctl_pin_dbg_show, +#endif + .dt_node_to_map = sppctl_dt_node_to_map, + .dt_free_map = pinctrl_utils_free_map, +}; + +static int sppctl_group_groups(struct platform_device *pdev) +{ + struct sppctl_pdata *sppctl = platform_get_drvdata(pdev); + int i, k, j; + + /* Calculate number of total group (GPIO + group-pinmux group). */ + sppctl->unq_grps_sz = sppctl_gpio_list_sz; + for (i = 0; i < sppctl_list_funcs_sz; i++) + if (sppctl_list_funcs[i].type == pinmux_type_grp) + sppctl->unq_grps_sz += sppctl_list_funcs[i].gnum; + + sppctl->unq_grps = devm_kcalloc(&pdev->dev, sppctl->unq_grps_sz + 1, + sizeof(*sppctl->unq_grps), GFP_KERNEL); + if (!sppctl->unq_grps) + return -ENOMEM; + + sppctl->g2fp_maps = devm_kcalloc(&pdev->dev, sppctl->unq_grps_sz + 1, + sizeof(*sppctl->g2fp_maps), GFP_KERNEL); + if (!sppctl->g2fp_maps) + return -ENOMEM; + + /* Add GPIO pins. */ + for (i = 0; i < sppctl_gpio_list_sz; i++) { + sppctl->unq_grps[i] = sppctl_gpio_list_s[i]; + sppctl->g2fp_maps[i].f_idx = 0; + sppctl->g2fp_maps[i].g_idx = i; + } + + /* Add group-pinmux to end of GPIO pins. */ + j = sppctl_gpio_list_sz; + for (i = 0; i < sppctl_list_funcs_sz; i++) { + if (sppctl_list_funcs[i].type != pinmux_type_grp) + continue; + + for (k = 0; k < sppctl_list_funcs[i].gnum; k++) { + sppctl->unq_grps[j] = sppctl_list_funcs[i].grps[k].name; + sppctl->g2fp_maps[j].f_idx = i; + sppctl->g2fp_maps[j].g_idx = k; + j++; + } + } + + return 0; +} + +static int sppctl_pinctrl_init(struct platform_device *pdev) +{ + struct sppctl_pdata *sppctl = platform_get_drvdata(pdev); + int err; + + sppctl->pctl_desc.owner = THIS_MODULE; + sppctl->pctl_desc.name = dev_name(&pdev->dev); + sppctl->pctl_desc.pins = sppctl_pins_all; + sppctl->pctl_desc.npins = sppctl_pins_all_sz; + sppctl->pctl_desc.pctlops = &sppctl_pctl_ops; + sppctl->pctl_desc.confops = &sppctl_pconf_ops; + sppctl->pctl_desc.pmxops = &sppctl_pinmux_ops; + + err = sppctl_group_groups(pdev); + if (err) + return err; + + err = devm_pinctrl_register_and_init(&pdev->dev, &sppctl->pctl_desc, + sppctl, &sppctl->pctl_dev); + if (err) + return dev_err_probe(&pdev->dev, err, "Failed to register pinctrl!\n"); + + pinctrl_enable(sppctl->pctl_dev); + return 0; +} + +static int sppctl_resource_map(struct platform_device *pdev, struct sppctl_pdata *sppctl) +{ + sppctl->moon2_base = devm_platform_ioremap_resource_byname(pdev, "moon2"); + if (IS_ERR(sppctl->moon2_base)) + return PTR_ERR(sppctl->moon2_base); + + sppctl->gpioxt_base = devm_platform_ioremap_resource_byname(pdev, "gpioxt"); + if (IS_ERR(sppctl->gpioxt_base)) + return PTR_ERR(sppctl->gpioxt_base); + + sppctl->first_base = devm_platform_ioremap_resource_byname(pdev, "first"); + if (IS_ERR(sppctl->first_base)) + return PTR_ERR(sppctl->first_base); + + sppctl->moon1_base = devm_platform_ioremap_resource_byname(pdev, "moon1"); + if (IS_ERR(sppctl->moon1_base)) + return PTR_ERR(sppctl->moon1_base); + + return 0; +} + +static int sppctl_probe(struct platform_device *pdev) +{ + struct sppctl_pdata *sppctl; + int ret; + + sppctl = devm_kzalloc(&pdev->dev, sizeof(*sppctl), GFP_KERNEL); + if (!sppctl) + return -ENOMEM; + platform_set_drvdata(pdev, sppctl); + + ret = sppctl_resource_map(pdev, sppctl); + if (ret) + return ret; + + ret = sppctl_gpio_new(pdev, sppctl); + if (ret) + return ret; + + ret = sppctl_pinctrl_init(pdev); + if (ret) + return ret; + + pinctrl_add_gpio_range(sppctl->pctl_dev, &sppctl->pctl_grange); + + return 0; +} + +static const struct of_device_id sppctl_match_table[] = { + { .compatible = "sunplus,sp7021-pctl" }, + { /* sentinel */ } +}; + +static struct platform_driver sppctl_pinctrl_driver = { + .driver = { + .name = SPPCTL_MODULE_NAME, + .of_match_table = sppctl_match_table, + }, + .probe = sppctl_probe, +}; +builtin_platform_driver(sppctl_pinctrl_driver) + +MODULE_AUTHOR("Dvorkin Dmitry <[email protected]>"); +MODULE_AUTHOR("Wells Lu <[email protected]>"); +MODULE_DESCRIPTION("Sunplus SP7021 Pin Control and GPIO driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/sunplus/sppctl.h b/drivers/pinctrl/sunplus/sppctl.h new file mode 100644 index 000000000000..6210f2200586 --- /dev/null +++ b/drivers/pinctrl/sunplus/sppctl.h @@ -0,0 +1,170 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * SP7021 Pin Controller Driver. + * Copyright (C) Sunplus Tech / Tibbo Tech. + */ + +#ifndef __SPPCTL_H__ +#define __SPPCTL_H__ + +#include <linux/bits.h> +#include <linux/gpio/driver.h> +#include <linux/kernel.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/spinlock.h> +#include <linux/types.h> + +#define SPPCTL_MODULE_NAME "sppctl_sp7021" + +#define SPPCTL_GPIO_OFF_FIRST 0x00 +#define SPPCTL_GPIO_OFF_MASTER 0x00 +#define SPPCTL_GPIO_OFF_OE 0x20 +#define SPPCTL_GPIO_OFF_OUT 0x40 +#define SPPCTL_GPIO_OFF_IN 0x60 +#define SPPCTL_GPIO_OFF_IINV 0x80 +#define SPPCTL_GPIO_OFF_OINV 0xa0 +#define SPPCTL_GPIO_OFF_OD 0xc0 + +#define SPPCTL_FULLY_PINMUX_MASK_MASK GENMASK(22, 16) +#define SPPCTL_FULLY_PINMUX_SEL_MASK GENMASK(6, 0) +#define SPPCTL_FULLY_PINMUX_UPPER_SHIFT 8 + +/* + * Mask-fields and control-fields of MOON registers of SP7021 are + * arranged as shown below: + * + * register | mask-fields | control-fields + * ----------+--------------+---------------- + * base[0] | (31 : 16) | (15 : 0) + * base[1] | (31 : 24) | (15 : 0) + * base[2] | (31 : 24) | (15 : 0) + * : | : | : + * + * where mask-fields are used to protect control-fields from write-in + * accidentally. Set the corresponding bits in the mask-field before + * you write a value into a control-field. + */ +#define SPPCTL_MOON_REG_MASK_SHIFT 16 +#define SPPCTL_SET_MOON_REG_BIT(bit) (BIT((bit) + SPPCTL_MOON_REG_MASK_SHIFT) | BIT(bit)) +#define SPPCTL_CLR_MOON_REG_BIT(bit) BIT((bit) + SPPCTL_MOON_REG_MASK_SHIFT) + +#define SPPCTL_IOP_CONFIGS 0xff + +#define FNCE(n, r, o, bo, bl, g) { \ + .name = n, \ + .type = r, \ + .roff = o, \ + .boff = bo, \ + .blen = bl, \ + .grps = (g), \ + .gnum = ARRAY_SIZE(g), \ +} + +#define FNCN(n, r, o, bo, bl) { \ + .name = n, \ + .type = r, \ + .roff = o, \ + .boff = bo, \ + .blen = bl, \ + .grps = NULL, \ + .gnum = 0, \ +} + +#define EGRP(n, v, p) { \ + .name = n, \ + .gval = (v), \ + .pins = (p), \ + .pnum = ARRAY_SIZE(p), \ +} + +/** + * enum mux_first_reg - Define modes of access of FIRST register + * @mux_f_mux: Set the corresponding pin to a fully-pinmux pin + * @mux_f_gpio: Set the corresponding pin to a GPIO or IOP pin + * @mux_f_keep: Don't change (keep intact) + */ +enum mux_first_reg { + mux_f_mux = 0, + mux_f_gpio = 1, + mux_f_keep = 2, +}; + +/** + * enum mux_master_reg - Define modes of access of MASTER register + * @mux_m_iop: Set the corresponding pin to an IO processor (IOP) pin + * @mux_m_gpio: Set the corresponding pin to a digital GPIO pin + * @mux_m_keep: Don't change (keep intact) + */ +enum mux_master_reg { + mux_m_iop = 0, + mux_m_gpio = 1, + mux_m_keep = 2, +}; + +/** + * enum pinmux_type - Define types of pinmux pins + * @pinmux_type_fpmx: A fully-pinmux pin + * @pinmux_type_grp: A group-pinmux pin + */ +enum pinmux_type { + pinmux_type_fpmx, + pinmux_type_grp, +}; + +/** + * struct grp2fp_map - A map storing indexes + * @f_idx: an index to function table + * @g_idx: an index to group table + */ +struct grp2fp_map { + u16 f_idx; + u16 g_idx; +}; + +struct sppctl_gpio_chip; + +struct sppctl_pdata { + void __iomem *moon2_base; /* MOON2 */ + void __iomem *gpioxt_base; /* MASTER, OE, OUT, IN, I_INV, O_INV, OD */ + void __iomem *first_base; /* FIRST */ + void __iomem *moon1_base; /* MOON1 */ + + struct pinctrl_desc pctl_desc; + struct pinctrl_dev *pctl_dev; + struct pinctrl_gpio_range pctl_grange; + struct sppctl_gpio_chip *spp_gchip; + + char const **unq_grps; + size_t unq_grps_sz; + struct grp2fp_map *g2fp_maps; +}; + +struct sppctl_grp { + const char * const name; + const u8 gval; /* group number */ + const unsigned * const pins; /* list of pins */ + const unsigned int pnum; /* number of pins */ +}; + +struct sppctl_func { + const char * const name; + const enum pinmux_type type; /* function type */ + const u8 roff; /* register offset */ + const u8 boff; /* bit offset */ + const u8 blen; /* bit length */ + const struct sppctl_grp * const grps; /* list of groups */ + const unsigned int gnum; /* number of groups */ +}; + +extern const struct sppctl_func sppctl_list_funcs[]; +extern const char * const sppctl_pmux_list_s[]; +extern const char * const sppctl_gpio_list_s[]; +extern const struct pinctrl_pin_desc sppctl_pins_all[]; +extern const unsigned int sppctl_pins_gpio[]; + +extern const size_t sppctl_list_funcs_sz; +extern const size_t sppctl_pmux_list_sz; +extern const size_t sppctl_gpio_list_sz; +extern const size_t sppctl_pins_all_sz; + +#endif diff --git a/drivers/pinctrl/sunplus/sppctl_sp7021.c b/drivers/pinctrl/sunplus/sppctl_sp7021.c new file mode 100644 index 000000000000..9748345b9298 --- /dev/null +++ b/drivers/pinctrl/sunplus/sppctl_sp7021.c @@ -0,0 +1,583 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SP7021 Pin Controller Driver. + * Copyright (C) Sunplus Tech / Tibbo Tech. + */ + +#include <linux/gpio/driver.h> +#include <linux/kernel.h> +#include <linux/pinctrl/pinctrl.h> + +#include "sppctl.h" + +#define D_PIS(x, y) "P" __stringify(x) "_0" __stringify(y) +#define D(x, y) ((x) * 8 + (y)) +#define P(x, y) PINCTRL_PIN(D(x, y), D_PIS(x, y)) + +const char * const sppctl_gpio_list_s[] = { + D_PIS(0, 0), D_PIS(0, 1), D_PIS(0, 2), D_PIS(0, 3), + D_PIS(0, 4), D_PIS(0, 5), D_PIS(0, 6), D_PIS(0, 7), + D_PIS(1, 0), D_PIS(1, 1), D_PIS(1, 2), D_PIS(1, 3), + D_PIS(1, 4), D_PIS(1, 5), D_PIS(1, 6), D_PIS(1, 7), + D_PIS(2, 0), D_PIS(2, 1), D_PIS(2, 2), D_PIS(2, 3), + D_PIS(2, 4), D_PIS(2, 5), D_PIS(2, 6), D_PIS(2, 7), + D_PIS(3, 0), D_PIS(3, 1), D_PIS(3, 2), D_PIS(3, 3), + D_PIS(3, 4), D_PIS(3, 5), D_PIS(3, 6), D_PIS(3, 7), + D_PIS(4, 0), D_PIS(4, 1), D_PIS(4, 2), D_PIS(4, 3), + D_PIS(4, 4), D_PIS(4, 5), D_PIS(4, 6), D_PIS(4, 7), + D_PIS(5, 0), D_PIS(5, 1), D_PIS(5, 2), D_PIS(5, 3), + D_PIS(5, 4), D_PIS(5, 5), D_PIS(5, 6), D_PIS(5, 7), + D_PIS(6, 0), D_PIS(6, 1), D_PIS(6, 2), D_PIS(6, 3), + D_PIS(6, 4), D_PIS(6, 5), D_PIS(6, 6), D_PIS(6, 7), + D_PIS(7, 0), D_PIS(7, 1), D_PIS(7, 2), D_PIS(7, 3), + D_PIS(7, 4), D_PIS(7, 5), D_PIS(7, 6), D_PIS(7, 7), + D_PIS(8, 0), D_PIS(8, 1), D_PIS(8, 2), D_PIS(8, 3), + D_PIS(8, 4), D_PIS(8, 5), D_PIS(8, 6), D_PIS(8, 7), + D_PIS(9, 0), D_PIS(9, 1), D_PIS(9, 2), D_PIS(9, 3), + D_PIS(9, 4), D_PIS(9, 5), D_PIS(9, 6), D_PIS(9, 7), + D_PIS(10, 0), D_PIS(10, 1), D_PIS(10, 2), D_PIS(10, 3), + D_PIS(10, 4), D_PIS(10, 5), D_PIS(10, 6), D_PIS(10, 7), + D_PIS(11, 0), D_PIS(11, 1), D_PIS(11, 2), D_PIS(11, 3), + D_PIS(11, 4), D_PIS(11, 5), D_PIS(11, 6), D_PIS(11, 7), + D_PIS(12, 0), D_PIS(12, 1), D_PIS(12, 2), +}; + +const size_t sppctl_gpio_list_sz = ARRAY_SIZE(sppctl_gpio_list_s); + +const unsigned int sppctl_pins_gpio[] = { + D(0, 0), D(0, 1), D(0, 2), D(0, 3), D(0, 4), D(0, 5), D(0, 6), D(0, 7), + D(1, 0), D(1, 1), D(1, 2), D(1, 3), D(1, 4), D(1, 5), D(1, 6), D(1, 7), + D(2, 0), D(2, 1), D(2, 2), D(2, 3), D(2, 4), D(2, 5), D(2, 6), D(2, 7), + D(3, 0), D(3, 1), D(3, 2), D(3, 3), D(3, 4), D(3, 5), D(3, 6), D(3, 7), + D(4, 0), D(4, 1), D(4, 2), D(4, 3), D(4, 4), D(4, 5), D(4, 6), D(4, 7), + D(5, 0), D(5, 1), D(5, 2), D(5, 3), D(5, 4), D(5, 5), D(5, 6), D(5, 7), + D(6, 0), D(6, 1), D(6, 2), D(6, 3), D(6, 4), D(6, 5), D(6, 6), D(6, 7), + D(7, 0), D(7, 1), D(7, 2), D(7, 3), D(7, 4), D(7, 5), D(7, 6), D(7, 7), + D(8, 0), D(8, 1), D(8, 2), D(8, 3), D(8, 4), D(8, 5), D(8, 6), D(8, 7), + D(9, 0), D(9, 1), D(9, 2), D(9, 3), D(9, 4), D(9, 5), D(9, 6), D(9, 7), + D(10, 0), D(10, 1), D(10, 2), D(10, 3), D(10, 4), D(10, 5), D(10, 6), D(10, 7), + D(11, 0), D(11, 1), D(11, 2), D(11, 3), D(11, 4), D(11, 5), D(11, 6), D(11, 7), + D(12, 0), D(12, 1), D(12, 2), +}; + +const struct pinctrl_pin_desc sppctl_pins_all[] = { + /* gpio and iop only */ + P(0, 0), P(0, 1), P(0, 2), P(0, 3), P(0, 4), P(0, 5), P(0, 6), P(0, 7), + /* gpio, iop, muxable */ + P(1, 0), P(1, 1), P(1, 2), P(1, 3), P(1, 4), P(1, 5), P(1, 6), P(1, 7), + P(2, 0), P(2, 1), P(2, 2), P(2, 3), P(2, 4), P(2, 5), P(2, 6), P(2, 7), + P(3, 0), P(3, 1), P(3, 2), P(3, 3), P(3, 4), P(3, 5), P(3, 6), P(3, 7), + P(4, 0), P(4, 1), P(4, 2), P(4, 3), P(4, 4), P(4, 5), P(4, 6), P(4, 7), + P(5, 0), P(5, 1), P(5, 2), P(5, 3), P(5, 4), P(5, 5), P(5, 6), P(5, 7), + P(6, 0), P(6, 1), P(6, 2), P(6, 3), P(6, 4), P(6, 5), P(6, 6), P(6, 7), + P(7, 0), P(7, 1), P(7, 2), P(7, 3), P(7, 4), P(7, 5), P(7, 6), P(7, 7), + P(8, 0), P(8, 1), P(8, 2), P(8, 3), P(8, 4), P(8, 5), P(8, 6), P(8, 7), + /* gpio and iop only */ + P(9, 0), P(9, 1), P(9, 2), P(9, 3), P(9, 4), P(9, 5), P(9, 6), P(9, 7), + P(10, 0), P(10, 1), P(10, 2), P(10, 3), P(10, 4), P(10, 5), P(10, 6), P(10, 7), + P(11, 0), P(11, 1), P(11, 2), P(11, 3), P(11, 4), P(11, 5), P(11, 6), P(11, 7), + P(12, 0), P(12, 1), P(12, 2), +}; + +const size_t sppctl_pins_all_sz = ARRAY_SIZE(sppctl_pins_all); + +const char * const sppctl_pmux_list_s[] = { + D_PIS(0, 0), + D_PIS(1, 0), D_PIS(1, 1), D_PIS(1, 2), D_PIS(1, 3), + D_PIS(1, 4), D_PIS(1, 5), D_PIS(1, 6), D_PIS(1, 7), + D_PIS(2, 0), D_PIS(2, 1), D_PIS(2, 2), D_PIS(2, 3), + D_PIS(2, 4), D_PIS(2, 5), D_PIS(2, 6), D_PIS(2, 7), + D_PIS(3, 0), D_PIS(3, 1), D_PIS(3, 2), D_PIS(3, 3), + D_PIS(3, 4), D_PIS(3, 5), D_PIS(3, 6), D_PIS(3, 7), + D_PIS(4, 0), D_PIS(4, 1), D_PIS(4, 2), D_PIS(4, 3), + D_PIS(4, 4), D_PIS(4, 5), D_PIS(4, 6), D_PIS(4, 7), + D_PIS(5, 0), D_PIS(5, 1), D_PIS(5, 2), D_PIS(5, 3), + D_PIS(5, 4), D_PIS(5, 5), D_PIS(5, 6), D_PIS(5, 7), + D_PIS(6, 0), D_PIS(6, 1), D_PIS(6, 2), D_PIS(6, 3), + D_PIS(6, 4), D_PIS(6, 5), D_PIS(6, 6), D_PIS(6, 7), + D_PIS(7, 0), D_PIS(7, 1), D_PIS(7, 2), D_PIS(7, 3), + D_PIS(7, 4), D_PIS(7, 5), D_PIS(7, 6), D_PIS(7, 7), + D_PIS(8, 0), D_PIS(8, 1), D_PIS(8, 2), D_PIS(8, 3), + D_PIS(8, 4), D_PIS(8, 5), D_PIS(8, 6), D_PIS(8, 7), +}; + +const size_t sppctl_pmux_list_sz = ARRAY_SIZE(sppctl_pmux_list_s); + +static const unsigned int pins_spif1[] = { + D(10, 3), D(10, 4), D(10, 6), D(10, 7), +}; + +static const unsigned int pins_spif2[] = { + D(9, 4), D(9, 6), D(9, 7), D(10, 1), +}; + +static const struct sppctl_grp sp7021grps_spif[] = { + EGRP("SPI_FLASH1", 1, pins_spif1), + EGRP("SPI_FLASH2", 2, pins_spif2), +}; + +static const unsigned int pins_spi41[] = { + D(10, 2), D(10, 5), +}; + +static const unsigned int pins_spi42[] = { + D(9, 5), D(9, 8), +}; + +static const struct sppctl_grp sp7021grps_spi4[] = { + EGRP("SPI_FLASH_4BIT1", 1, pins_spi41), + EGRP("SPI_FLASH_4BIT2", 2, pins_spi42), +}; + +static const unsigned int pins_snan[] = { + D(9, 4), D(9, 5), D(9, 6), D(9, 7), D(10, 0), D(10, 1), +}; + +static const struct sppctl_grp sp7021grps_snan[] = { + EGRP("SPI_NAND", 1, pins_snan), +}; + +static const unsigned int pins_emmc[] = { + D(9, 0), D(9, 1), D(9, 2), D(9, 3), D(9, 4), D(9, 5), + D(9, 6), D(9, 7), D(10, 0), D(10, 1), +}; + +static const struct sppctl_grp sp7021grps_emmc[] = { + EGRP("CARD0_EMMC", 1, pins_emmc), +}; + +static const unsigned int pins_sdsd[] = { + D(8, 1), D(8, 2), D(8, 3), D(8, 4), D(8, 5), D(8, 6), +}; + +static const struct sppctl_grp sp7021grps_sdsd[] = { + EGRP("SD_CARD", 1, pins_sdsd), +}; + +static const unsigned int pins_uar0[] = { + D(11, 0), D(11, 1), +}; + +static const struct sppctl_grp sp7021grps_uar0[] = { + EGRP("UA0", 1, pins_uar0), +}; + +static const unsigned int pins_adbg1[] = { + D(10, 2), D(10, 3), +}; + +static const unsigned int pins_adbg2[] = { + D(7, 1), D(7, 2), +}; + +static const struct sppctl_grp sp7021grps_adbg[] = { + EGRP("ACHIP_DEBUG1", 1, pins_adbg1), + EGRP("ACHIP_DEBUG2", 2, pins_adbg2), +}; + +static const unsigned int pins_aua2axi1[] = { + D(2, 0), D(2, 1), D(2, 2), +}; + +static const unsigned int pins_aua2axi2[] = { + D(1, 0), D(1, 1), D(1, 2), +}; + +static const struct sppctl_grp sp7021grps_au2x[] = { + EGRP("ACHIP_UA2AXI1", 1, pins_aua2axi1), + EGRP("ACHIP_UA2AXI2", 2, pins_aua2axi2), +}; + +static const unsigned int pins_fpga[] = { + D(0, 2), D(0, 3), D(0, 4), D(0, 5), D(0, 6), D(0, 7), + D(1, 0), D(1, 1), D(1, 2), D(1, 3), D(1, 4), D(1, 5), + D(1, 6), D(1, 7), D(2, 0), D(2, 1), D(2, 2), D(2, 3), + D(2, 4), D(2, 5), D(2, 6), D(2, 7), D(3, 0), D(3, 1), + D(3, 2), D(3, 3), D(3, 4), D(3, 5), D(3, 6), D(3, 7), + D(4, 0), D(4, 1), D(4, 2), D(4, 3), D(4, 4), D(4, 5), + D(4, 6), D(4, 7), D(5, 0), D(5, 1), D(5, 2), +}; + +static const struct sppctl_grp sp7021grps_fpga[] = { + EGRP("FPGA_IFX", 1, pins_fpga), +}; + +static const unsigned int pins_hdmi1[] = { + D(10, 6), D(12, 2), D(12, 1), +}; + +static const unsigned int pins_hdmi2[] = { + D(8, 3), D(8, 5), D(8, 6), +}; + +static const unsigned int pins_hdmi3[] = { + D(7, 4), D(7, 6), D(7, 7), +}; + +static const struct sppctl_grp sp7021grps_hdmi[] = { + EGRP("HDMI_TX1", 1, pins_hdmi1), + EGRP("HDMI_TX2", 2, pins_hdmi2), + EGRP("HDMI_TX3", 3, pins_hdmi3), +}; + +static const unsigned int pins_eadc[] = { + D(1, 0), D(1, 1), D(1, 2), D(1, 3), D(1, 4), D(1, 5), D(1, 6), +}; + +static const struct sppctl_grp sp7021grps_eadc[] = { + EGRP("AUD_EXT_ADC_IFX0", 1, pins_eadc), +}; + +static const unsigned int pins_edac[] = { + D(2, 5), D(2, 6), D(2, 7), D(3, 0), D(3, 1), D(3, 2), D(3, 4), +}; + +static const struct sppctl_grp sp7021grps_edac[] = { + EGRP("AUD_EXT_DAC_IFX0", 1, pins_edac), +}; + +static const unsigned int pins_spdi[] = { + D(2, 4), +}; + +static const struct sppctl_grp sp7021grps_spdi[] = { + EGRP("AUD_IEC_RX0", 1, pins_spdi), +}; + +static const unsigned int pins_spdo[] = { + D(3, 6), +}; + +static const struct sppctl_grp sp7021grps_spdo[] = { + EGRP("AUD_IEC_TX0", 1, pins_spdo), +}; + +static const unsigned int pins_tdmt[] = { + D(2, 5), D(2, 6), D(2, 7), D(3, 0), D(3, 1), D(3, 2), +}; + +static const struct sppctl_grp sp7021grps_tdmt[] = { + EGRP("TDMTX_IFX0", 1, pins_tdmt), +}; + +static const unsigned int pins_tdmr[] = { + D(1, 7), D(2, 0), D(2, 1), D(2, 2), +}; + +static const struct sppctl_grp sp7021grps_tdmr[] = { + EGRP("TDMRX_IFX0", 1, pins_tdmr), +}; + +static const unsigned int pins_pdmr[] = { + D(1, 7), D(2, 0), D(2, 1), D(2, 2), D(2, 3), +}; + +static const struct sppctl_grp sp7021grps_pdmr[] = { + EGRP("PDMRX_IFX0", 1, pins_pdmr), +}; + +static const unsigned int pins_pcmt[] = { + D(3, 7), D(4, 0), D(4, 1), D(4, 2), D(4, 3), D(4, 4), +}; + +static const struct sppctl_grp sp7021grps_pcmt[] = { + EGRP("PCM_IEC_TX", 1, pins_pcmt), +}; + +static const unsigned int pins_lcdi[] = { + D(1, 4), D(1, 5), D(1, 6), D(1, 7), D(2, 0), D(2, 1), D(2, 2), D(2, 3), + D(2, 4), D(2, 5), D(2, 6), D(2, 7), D(3, 0), D(3, 1), D(3, 2), D(3, 3), + D(3, 4), D(3, 5), D(3, 6), D(3, 7), D(4, 0), D(4, 1), D(4, 2), D(4, 3), + D(4, 4), D(4, 5), D(4, 6), D(4, 7), +}; + +static const struct sppctl_grp sp7021grps_lcdi[] = { + EGRP("LCDIF", 1, pins_lcdi), +}; + +static const unsigned int pins_dvdd[] = { + D(7, 0), D(7, 1), D(7, 2), D(7, 3), D(7, 4), D(7, 5), D(7, 6), D(7, 7), + D(8, 0), D(8, 1), D(8, 2), D(8, 3), D(8, 4), D(8, 5), +}; + +static const struct sppctl_grp sp7021grps_dvdd[] = { + EGRP("DVD_DSP_DEBUG", 1, pins_dvdd), +}; + +static const unsigned int pins_i2cd[] = { + D(1, 0), D(1, 1), +}; + +static const struct sppctl_grp sp7021grps_i2cd[] = { + EGRP("I2C_DEBUG", 1, pins_i2cd), +}; + +static const unsigned int pins_i2cs[] = { + D(0, 0), D(0, 1), +}; + +static const struct sppctl_grp sp7021grps_i2cs[] = { + EGRP("I2C_SLAVE", 1, pins_i2cs), +}; + +static const unsigned int pins_wakp[] = { + D(10, 5), +}; + +static const struct sppctl_grp sp7021grps_wakp[] = { + EGRP("WAKEUP", 1, pins_wakp), +}; + +static const unsigned int pins_u2ax[] = { + D(2, 0), D(2, 1), D(3, 0), D(3, 1), +}; + +static const struct sppctl_grp sp7021grps_u2ax[] = { + EGRP("UART2AXI", 1, pins_u2ax), +}; + +static const unsigned int pins_u0ic[] = { + D(0, 0), D(0, 1), D(0, 4), D(0, 5), D(1, 0), D(1, 1), +}; + +static const struct sppctl_grp sp7021grps_u0ic[] = { + EGRP("USB0_I2C", 1, pins_u0ic), +}; + +static const unsigned int pins_u1ic[] = { + D(0, 2), D(0, 3), D(0, 6), D(0, 7), D(1, 2), D(1, 3), +}; + +static const struct sppctl_grp sp7021grps_u1ic[] = { + EGRP("USB1_I2C", 1, pins_u1ic), +}; + +static const unsigned int pins_u0ot[] = { + D(11, 2), +}; + +static const struct sppctl_grp sp7021grps_u0ot[] = { + EGRP("USB0_OTG", 1, pins_u0ot), +}; + +static const unsigned int pins_u1ot[] = { + D(11, 3), +}; + +static const struct sppctl_grp sp7021grps_u1ot[] = { + EGRP("USB1_OTG", 1, pins_u1ot), +}; + +static const unsigned int pins_uphd[] = { + D(0, 1), D(0, 2), D(0, 3), D(7, 4), D(7, 5), D(7, 6), + D(7, 7), D(8, 0), D(8, 1), D(8, 2), D(8, 3), + D(9, 7), D(10, 2), D(10, 3), D(10, 4), +}; + +static const struct sppctl_grp sp7021grps_up0d[] = { + EGRP("UPHY0_DEBUG", 1, pins_uphd), +}; + +static const struct sppctl_grp sp7021grps_up1d[] = { + EGRP("UPHY1_DEBUG", 1, pins_uphd), +}; + +static const unsigned int pins_upex[] = { + D(0, 0), D(0, 1), D(0, 2), D(0, 3), D(0, 4), D(0, 5), D(0, 6), D(0, 7), + D(1, 0), D(1, 1), D(1, 2), D(1, 3), D(1, 4), D(1, 5), D(1, 6), D(1, 7), + D(2, 0), D(2, 1), D(2, 2), D(2, 3), D(2, 4), D(2, 5), D(2, 6), D(2, 7), + D(3, 0), D(3, 1), D(3, 2), D(3, 3), D(3, 4), D(3, 5), D(3, 6), D(3, 7), + D(4, 0), D(4, 1), D(4, 2), D(4, 3), D(4, 4), D(4, 5), D(4, 6), D(4, 7), + D(5, 0), D(5, 1), D(5, 2), D(5, 3), D(5, 4), D(5, 5), D(5, 6), D(5, 7), + D(6, 0), D(6, 1), D(6, 2), D(6, 3), D(6, 4), D(6, 5), D(6, 6), D(6, 7), + D(7, 0), D(7, 1), D(7, 2), D(7, 3), D(7, 4), D(7, 5), D(7, 6), D(7, 7), + D(8, 0), D(8, 1), D(8, 2), D(8, 3), D(8, 4), D(8, 5), D(8, 6), D(8, 7), + D(9, 0), D(9, 1), D(9, 2), D(9, 3), D(9, 4), D(9, 5), D(9, 6), D(9, 7), + D(10, 0), D(10, 1), D(10, 2), D(10, 3), D(10, 4), D(10, 5), D(10, 6), D(10, 7), +}; + +static const struct sppctl_grp sp7021grps_upex[] = { + EGRP("UPHY0_EXT", 1, pins_upex), +}; + +static const unsigned int pins_prp1[] = { + D(0, 6), D(0, 7), + D(1, 0), D(1, 1), D(1, 2), D(1, 3), D(1, 4), D(1, 5), D(1, 6), D(1, 7), + D(2, 1), D(2, 2), D(2, 3), D(2, 4), D(2, 5), D(2, 6), D(2, 7), + D(3, 0), D(3, 1), D(3, 2), +}; + +static const unsigned int pins_prp2[] = { + D(3, 4), D(3, 6), D(3, 7), + D(4, 0), D(4, 1), D(4, 2), D(4, 3), D(4, 4), D(4, 5), D(4, 6), D(4, 7), + D(5, 0), D(5, 1), D(5, 2), D(5, 3), D(5, 4), D(5, 5), D(5, 6), D(5, 7), + D(6, 4), +}; + +static const struct sppctl_grp sp7021grps_prbp[] = { + EGRP("PROBE_PORT1", 1, pins_prp1), + EGRP("PROBE_PORT2", 2, pins_prp2), +}; + +const struct sppctl_func sppctl_list_funcs[] = { + FNCN("L2SW_CLK_OUT", pinmux_type_fpmx, 0x00, 0, 7), + FNCN("L2SW_MAC_SMI_MDC", pinmux_type_fpmx, 0x00, 8, 7), + FNCN("L2SW_LED_FLASH0", pinmux_type_fpmx, 0x01, 0, 7), + FNCN("L2SW_LED_FLASH1", pinmux_type_fpmx, 0x01, 8, 7), + FNCN("L2SW_LED_ON0", pinmux_type_fpmx, 0x02, 0, 7), + FNCN("L2SW_LED_ON1", pinmux_type_fpmx, 0x02, 8, 7), + FNCN("L2SW_MAC_SMI_MDIO", pinmux_type_fpmx, 0x03, 0, 7), + FNCN("L2SW_P0_MAC_RMII_TXEN", pinmux_type_fpmx, 0x03, 8, 7), + FNCN("L2SW_P0_MAC_RMII_TXD0", pinmux_type_fpmx, 0x04, 0, 7), + FNCN("L2SW_P0_MAC_RMII_TXD1", pinmux_type_fpmx, 0x04, 8, 7), + FNCN("L2SW_P0_MAC_RMII_CRSDV", pinmux_type_fpmx, 0x05, 0, 7), + FNCN("L2SW_P0_MAC_RMII_RXD0", pinmux_type_fpmx, 0x05, 8, 7), + FNCN("L2SW_P0_MAC_RMII_RXD1", pinmux_type_fpmx, 0x06, 0, 7), + FNCN("L2SW_P0_MAC_RMII_RXER", pinmux_type_fpmx, 0x06, 8, 7), + FNCN("L2SW_P1_MAC_RMII_TXEN", pinmux_type_fpmx, 0x07, 0, 7), + FNCN("L2SW_P1_MAC_RMII_TXD0", pinmux_type_fpmx, 0x07, 8, 7), + FNCN("L2SW_P1_MAC_RMII_TXD1", pinmux_type_fpmx, 0x08, 0, 7), + FNCN("L2SW_P1_MAC_RMII_CRSDV", pinmux_type_fpmx, 0x08, 8, 7), + FNCN("L2SW_P1_MAC_RMII_RXD0", pinmux_type_fpmx, 0x09, 0, 7), + FNCN("L2SW_P1_MAC_RMII_RXD1", pinmux_type_fpmx, 0x09, 8, 7), + FNCN("L2SW_P1_MAC_RMII_RXER", pinmux_type_fpmx, 0x0A, 0, 7), + FNCN("DAISY_MODE", pinmux_type_fpmx, 0x0A, 8, 7), + FNCN("SDIO_CLK", pinmux_type_fpmx, 0x0B, 0, 7), /* 1x SDIO */ + FNCN("SDIO_CMD", pinmux_type_fpmx, 0x0B, 8, 7), + FNCN("SDIO_D0", pinmux_type_fpmx, 0x0C, 0, 7), + FNCN("SDIO_D1", pinmux_type_fpmx, 0x0C, 8, 7), + FNCN("SDIO_D2", pinmux_type_fpmx, 0x0D, 0, 7), + FNCN("SDIO_D3", pinmux_type_fpmx, 0x0D, 8, 7), + FNCN("PWM0", pinmux_type_fpmx, 0x0E, 0, 7), /* 8x PWM */ + FNCN("PWM1", pinmux_type_fpmx, 0x0E, 8, 7), + FNCN("PWM2", pinmux_type_fpmx, 0x0F, 0, 7), + FNCN("PWM3", pinmux_type_fpmx, 0x0F, 8, 7), + + FNCN("PWM4", pinmux_type_fpmx, 0x10, 0, 7), + FNCN("PWM5", pinmux_type_fpmx, 0x10, 8, 7), + FNCN("PWM6", pinmux_type_fpmx, 0x11, 0, 7), + FNCN("PWM7", pinmux_type_fpmx, 0x11, 8, 7), + FNCN("ICM0_D", pinmux_type_fpmx, 0x12, 0, 7), /* 4x Input captures */ + FNCN("ICM1_D", pinmux_type_fpmx, 0x12, 8, 7), + FNCN("ICM2_D", pinmux_type_fpmx, 0x13, 0, 7), + FNCN("ICM3_D", pinmux_type_fpmx, 0x13, 8, 7), + FNCN("ICM0_CLK", pinmux_type_fpmx, 0x14, 0, 7), + FNCN("ICM1_CLK", pinmux_type_fpmx, 0x14, 8, 7), + FNCN("ICM2_CLK", pinmux_type_fpmx, 0x15, 0, 7), + FNCN("ICM3_CLK", pinmux_type_fpmx, 0x15, 8, 7), + FNCN("SPIM0_INT", pinmux_type_fpmx, 0x16, 0, 7), /* 4x SPI masters */ + FNCN("SPIM0_CLK", pinmux_type_fpmx, 0x16, 8, 7), + FNCN("SPIM0_EN", pinmux_type_fpmx, 0x17, 0, 7), + FNCN("SPIM0_DO", pinmux_type_fpmx, 0x17, 8, 7), + FNCN("SPIM0_DI", pinmux_type_fpmx, 0x18, 0, 7), + FNCN("SPIM1_INT", pinmux_type_fpmx, 0x18, 8, 7), + FNCN("SPIM1_CLK", pinmux_type_fpmx, 0x19, 0, 7), + FNCN("SPIM1_EN", pinmux_type_fpmx, 0x19, 8, 7), + FNCN("SPIM1_DO", pinmux_type_fpmx, 0x1A, 0, 7), + FNCN("SPIM1_DI", pinmux_type_fpmx, 0x1A, 8, 7), + FNCN("SPIM2_INT", pinmux_type_fpmx, 0x1B, 0, 7), + FNCN("SPIM2_CLK", pinmux_type_fpmx, 0x1B, 8, 7), + FNCN("SPIM2_EN", pinmux_type_fpmx, 0x1C, 0, 7), + FNCN("SPIM2_DO", pinmux_type_fpmx, 0x1C, 8, 7), + FNCN("SPIM2_DI", pinmux_type_fpmx, 0x1D, 0, 7), + FNCN("SPIM3_INT", pinmux_type_fpmx, 0x1D, 8, 7), + FNCN("SPIM3_CLK", pinmux_type_fpmx, 0x1E, 0, 7), + FNCN("SPIM3_EN", pinmux_type_fpmx, 0x1E, 8, 7), + FNCN("SPIM3_DO", pinmux_type_fpmx, 0x1F, 0, 7), + FNCN("SPIM3_DI", pinmux_type_fpmx, 0x1F, 8, 7), + + FNCN("SPI0S_INT", pinmux_type_fpmx, 0x20, 0, 7), /* 4x SPI slaves */ + FNCN("SPI0S_CLK", pinmux_type_fpmx, 0x20, 8, 7), + FNCN("SPI0S_EN", pinmux_type_fpmx, 0x21, 0, 7), + FNCN("SPI0S_DO", pinmux_type_fpmx, 0x21, 8, 7), + FNCN("SPI0S_DI", pinmux_type_fpmx, 0x22, 0, 7), + FNCN("SPI1S_INT", pinmux_type_fpmx, 0x22, 8, 7), + FNCN("SPI1S_CLK", pinmux_type_fpmx, 0x23, 0, 7), + FNCN("SPI1S_EN", pinmux_type_fpmx, 0x23, 8, 7), + FNCN("SPI1S_DO", pinmux_type_fpmx, 0x24, 0, 7), + FNCN("SPI1S_DI", pinmux_type_fpmx, 0x24, 8, 7), + FNCN("SPI2S_INT", pinmux_type_fpmx, 0x25, 0, 7), + FNCN("SPI2S_CLK", pinmux_type_fpmx, 0x25, 8, 7), + FNCN("SPI2S_EN", pinmux_type_fpmx, 0x26, 0, 7), + FNCN("SPI2S_DO", pinmux_type_fpmx, 0x26, 8, 7), + FNCN("SPI2S_DI", pinmux_type_fpmx, 0x27, 0, 7), + FNCN("SPI3S_INT", pinmux_type_fpmx, 0x27, 8, 7), + FNCN("SPI3S_CLK", pinmux_type_fpmx, 0x28, 0, 7), + FNCN("SPI3S_EN", pinmux_type_fpmx, 0x28, 8, 7), + FNCN("SPI3S_DO", pinmux_type_fpmx, 0x29, 0, 7), + FNCN("SPI3S_DI", pinmux_type_fpmx, 0x29, 8, 7), + FNCN("I2CM0_CLK", pinmux_type_fpmx, 0x2A, 0, 7), /* 4x I2C masters */ + FNCN("I2CM0_DAT", pinmux_type_fpmx, 0x2A, 8, 7), + FNCN("I2CM1_CLK", pinmux_type_fpmx, 0x2B, 0, 7), + FNCN("I2CM1_DAT", pinmux_type_fpmx, 0x2B, 8, 7), + FNCN("I2CM2_CLK", pinmux_type_fpmx, 0x2C, 0, 7), + FNCN("I2CM2_DAT", pinmux_type_fpmx, 0x2C, 8, 7), + FNCN("I2CM3_CLK", pinmux_type_fpmx, 0x2D, 0, 7), + FNCN("I2CM3_DAT", pinmux_type_fpmx, 0x2D, 8, 7), + FNCN("UA1_TX", pinmux_type_fpmx, 0x2E, 0, 7), /* 4x UARTS */ + FNCN("UA1_RX", pinmux_type_fpmx, 0x2E, 8, 7), + FNCN("UA1_CTS", pinmux_type_fpmx, 0x2F, 0, 7), + FNCN("UA1_RTS", pinmux_type_fpmx, 0x2F, 8, 7), + + FNCN("UA2_TX", pinmux_type_fpmx, 0x30, 0, 7), + FNCN("UA2_RX", pinmux_type_fpmx, 0x30, 8, 7), + FNCN("UA2_CTS", pinmux_type_fpmx, 0x31, 0, 7), + FNCN("UA2_RTS", pinmux_type_fpmx, 0x31, 8, 7), + FNCN("UA3_TX", pinmux_type_fpmx, 0x32, 0, 7), + FNCN("UA3_RX", pinmux_type_fpmx, 0x32, 8, 7), + FNCN("UA3_CTS", pinmux_type_fpmx, 0x33, 0, 7), + FNCN("UA3_RTS", pinmux_type_fpmx, 0x33, 8, 7), + FNCN("UA4_TX", pinmux_type_fpmx, 0x34, 0, 7), + FNCN("UA4_RX", pinmux_type_fpmx, 0x34, 8, 7), + FNCN("UA4_CTS", pinmux_type_fpmx, 0x35, 0, 7), + FNCN("UA4_RTS", pinmux_type_fpmx, 0x35, 8, 7), + FNCN("TIMER0_INT", pinmux_type_fpmx, 0x36, 0, 7), /* 4x timer int. */ + FNCN("TIMER1_INT", pinmux_type_fpmx, 0x36, 8, 7), + FNCN("TIMER2_INT", pinmux_type_fpmx, 0x37, 0, 7), + FNCN("TIMER3_INT", pinmux_type_fpmx, 0x37, 8, 7), + FNCN("GPIO_INT0", pinmux_type_fpmx, 0x38, 0, 7), /* 8x GPIO int. */ + FNCN("GPIO_INT1", pinmux_type_fpmx, 0x38, 8, 7), + FNCN("GPIO_INT2", pinmux_type_fpmx, 0x39, 0, 7), + FNCN("GPIO_INT3", pinmux_type_fpmx, 0x39, 8, 7), + FNCN("GPIO_INT4", pinmux_type_fpmx, 0x3A, 0, 7), + FNCN("GPIO_INT5", pinmux_type_fpmx, 0x3A, 8, 7), + FNCN("GPIO_INT6", pinmux_type_fpmx, 0x3B, 0, 7), + FNCN("GPIO_INT7", pinmux_type_fpmx, 0x3B, 8, 7), + + /* MOON1 register */ + FNCE("SPI_FLASH", pinmux_type_grp, 0x01, 0, 2, sp7021grps_spif), + FNCE("SPI_FLASH_4BIT", pinmux_type_grp, 0x01, 2, 2, sp7021grps_spi4), + FNCE("SPI_NAND", pinmux_type_grp, 0x01, 4, 1, sp7021grps_snan), + FNCE("CARD0_EMMC", pinmux_type_grp, 0x01, 5, 1, sp7021grps_emmc), + FNCE("SD_CARD", pinmux_type_grp, 0x01, 6, 1, sp7021grps_sdsd), + FNCE("UA0", pinmux_type_grp, 0x01, 7, 1, sp7021grps_uar0), + FNCE("ACHIP_DEBUG", pinmux_type_grp, 0x01, 8, 2, sp7021grps_adbg), + FNCE("ACHIP_UA2AXI", pinmux_type_grp, 0x01, 10, 2, sp7021grps_au2x), + FNCE("FPGA_IFX", pinmux_type_grp, 0x01, 12, 1, sp7021grps_fpga), + FNCE("HDMI_TX", pinmux_type_grp, 0x01, 13, 2, sp7021grps_hdmi), + + FNCE("AUD_EXT_ADC_IFX0", pinmux_type_grp, 0x01, 15, 1, sp7021grps_eadc), + FNCE("AUD_EXT_DAC_IFX0", pinmux_type_grp, 0x02, 0, 1, sp7021grps_edac), + FNCE("SPDIF_RX", pinmux_type_grp, 0x02, 2, 1, sp7021grps_spdi), + FNCE("SPDIF_TX", pinmux_type_grp, 0x02, 3, 1, sp7021grps_spdo), + FNCE("TDMTX_IFX0", pinmux_type_grp, 0x02, 4, 1, sp7021grps_tdmt), + FNCE("TDMRX_IFX0", pinmux_type_grp, 0x02, 5, 1, sp7021grps_tdmr), + FNCE("PDMRX_IFX0", pinmux_type_grp, 0x02, 6, 1, sp7021grps_pdmr), + FNCE("PCM_IEC_TX", pinmux_type_grp, 0x02, 7, 1, sp7021grps_pcmt), + FNCE("LCDIF", pinmux_type_grp, 0x04, 6, 1, sp7021grps_lcdi), + FNCE("DVD_DSP_DEBUG", pinmux_type_grp, 0x02, 8, 1, sp7021grps_dvdd), + FNCE("I2C_DEBUG", pinmux_type_grp, 0x02, 9, 1, sp7021grps_i2cd), + FNCE("I2C_SLAVE", pinmux_type_grp, 0x02, 10, 1, sp7021grps_i2cs), + FNCE("WAKEUP", pinmux_type_grp, 0x02, 11, 1, sp7021grps_wakp), + FNCE("UART2AXI", pinmux_type_grp, 0x02, 12, 2, sp7021grps_u2ax), + FNCE("USB0_I2C", pinmux_type_grp, 0x02, 14, 2, sp7021grps_u0ic), + FNCE("USB1_I2C", pinmux_type_grp, 0x03, 0, 2, sp7021grps_u1ic), + FNCE("USB0_OTG", pinmux_type_grp, 0x03, 2, 1, sp7021grps_u0ot), + FNCE("USB1_OTG", pinmux_type_grp, 0x03, 3, 1, sp7021grps_u1ot), + FNCE("UPHY0_DEBUG", pinmux_type_grp, 0x03, 4, 1, sp7021grps_up0d), + FNCE("UPHY1_DEBUG", pinmux_type_grp, 0x03, 5, 1, sp7021grps_up1d), + FNCE("UPHY0_EXT", pinmux_type_grp, 0x03, 6, 1, sp7021grps_upex), + FNCE("PROBE_PORT", pinmux_type_grp, 0x03, 7, 2, sp7021grps_prbp), +}; + +const size_t sppctl_list_funcs_sz = ARRAY_SIZE(sppctl_list_funcs); diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c index a4fa8e3af607..65ed20bc1fa2 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c @@ -461,10 +461,18 @@ static const struct pinctrl_pin_desc uniphier_ld11_pins[] = { 166, UNIPHIER_PIN_PULL_DOWN), }; -static const unsigned ain1_pins[] = {151, 152, 153, 154, 155, 156, 157}; -static const int ain1_muxvals[] = {4, 4, 4, 4, 4, 4, 4}; -static const unsigned aout1_pins[] = {137, 138, 139, 140, 141, 142}; -static const int aout1_muxvals[] = {0, 0, 0, 0, 0, 0}; +static const unsigned ain1_pins[] = {151, 152, 153, 154}; +static const int ain1_muxvals[] = {4, 4, 4, 4}; +static const unsigned ain1_dat2_pins[] = {155}; +static const int ain1_dat2_muxvals[] = {4}; +static const unsigned ain1_dat4_pins[] = {156, 157}; +static const int ain1_dat4_muxvals[] = {4, 4}; +static const unsigned aout1_pins[] = {137, 138, 139, 140}; +static const int aout1_muxvals[] = {0, 0, 0, 0}; +static const unsigned aout1_dat2_pins[] = {141}; +static const int aout1_dat2_muxvals[] = {0}; +static const unsigned aout1_dat4_pins[] = {142, 143}; +static const int aout1_dat4_muxvals[] = {0, 3}; static const unsigned ainiec1_pins[] = {150}; static const int ainiec1_muxvals[] = {4}; static const unsigned ainiec1b_pins[] = {141}; @@ -582,7 +590,11 @@ static const unsigned int gpio_range5_pins[] = { static const struct uniphier_pinctrl_group uniphier_ld11_groups[] = { UNIPHIER_PINCTRL_GROUP(ain1), + UNIPHIER_PINCTRL_GROUP(ain1_dat2), + UNIPHIER_PINCTRL_GROUP(ain1_dat4), UNIPHIER_PINCTRL_GROUP(aout1), + UNIPHIER_PINCTRL_GROUP(aout1_dat2), + UNIPHIER_PINCTRL_GROUP(aout1_dat4), UNIPHIER_PINCTRL_GROUP(ainiec1), UNIPHIER_PINCTRL_GROUP(ainiec1b), UNIPHIER_PINCTRL_GROUP(aoutiec1), @@ -626,8 +638,10 @@ static const struct uniphier_pinctrl_group uniphier_ld11_groups[] = { UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range5), }; -static const char * const ain1_groups[] = {"ain1"}; -static const char * const aout1_groups[] = {"aout1"}; +static const char * const ain1_groups[] = {"ain1", "ain1_dat2", + "ain1_dat4"}; +static const char * const aout1_groups[] = {"aout1", "aout1_dat2", + "aout1_dat4"}; static const char * const ainiec1_groups[] = {"ainiec1", "ainiec1b"}; static const char * const aoutiec1_groups[] = {"aoutiec1"}; static const char * const aoutiec2_groups[] = {"aoutiec2"}; diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c index 850736998206..a68b21fbd0c7 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c @@ -542,18 +542,38 @@ static const struct pinctrl_pin_desc uniphier_ld20_pins[] = { 175, UNIPHIER_PIN_PULL_DOWN), }; -static const unsigned ain1_pins[] = {150, 151, 152, 153, 154, 155, 156}; -static const int ain1_muxvals[] = {4, 4, 4, 4, 4, 4, 4}; -static const unsigned ain2_pins[] = {116, 117, 118, 119, 120, 121, 122}; -static const int ain2_muxvals[] = {26, 26, 26, 26, 26, 26, 26}; +static const unsigned ain1_pins[] = {150, 151, 152, 153}; +static const int ain1_muxvals[] = {4, 4, 4, 4}; +static const unsigned ain1_dat2_pins[] = {154}; +static const int ain1_dat2_muxvals[] = {4}; +static const unsigned ain1_dat4_pins[] = {155, 156}; +static const int ain1_dat4_muxvals[] = {4, 4}; +static const unsigned ain2_pins[] = {116, 117, 118, 119}; +static const int ain2_muxvals[] = {26, 26, 26, 26}; +static const unsigned ain2_dat2_pins[] = {120}; +static const int ain2_dat2_muxvals[] = {26}; +static const unsigned ain2_dat4_pins[] = {121, 122}; +static const int ain2_dat4_muxvals[] = {26, 26}; static const unsigned ain3_pins[] = {116, 117, 118, 119}; static const int ain3_muxvals[] = {27, 27, 27, 27}; -static const unsigned aout1_pins[] = {137, 138, 139, 140, 141, 142}; -static const int aout1_muxvals[] = {0, 0, 0, 0, 0, 0}; -static const unsigned aout1b_pins[] = {150, 151, 152, 153, 154, 155, 156}; -static const int aout1b_muxvals[] = {1, 1, 1, 1, 1, 1, 1}; -static const unsigned aout2_pins[] = {165, 157, 162, 158, 159, 160, 161}; -static const int aout2_muxvals[] = {2, 2, 2, 1, 1, 1, 1}; +static const unsigned aout1_pins[] = {137, 138, 139, 140}; +static const int aout1_muxvals[] = {0, 0, 0, 0}; +static const unsigned aout1_dat2_pins[] = {141}; +static const int aout1_dat2_muxvals[] = {0}; +static const unsigned aout1_dat4_pins[] = {142, 156}; +static const int aout1_dat4_muxvals[] = {0, 1}; +static const unsigned aout1b_pins[] = {150, 151, 152, 153}; +static const int aout1b_muxvals[] = {1, 1, 1, 1}; +static const unsigned aout1b_dat2_pins[] = {154}; +static const int aout1b_dat2_muxvals[] = {1}; +static const unsigned aout1b_dat4_pins[] = {155, 156}; +static const int aout1b_dat4_muxvals[] = {1, 1}; +static const unsigned aout2_pins[] = {165, 157, 162, 158}; +static const int aout2_muxvals[] = {2, 2, 2, 1}; +static const unsigned aout2_dat2_pins[] = {159}; +static const int aout2_dat2_muxvals[] = {1}; +static const unsigned aout2_dat4_pins[] = {160, 161}; +static const int aout2_dat4_muxvals[] = {1, 1}; static const unsigned aout3_pins[] = {166, 167, 168, 163}; static const int aout3_muxvals[] = {2, 2, 2, 1}; static const unsigned aout4_pins[] = {169, 170, 171, 164}; @@ -682,11 +702,21 @@ static const unsigned int gpio_range2_pins[] = { static const struct uniphier_pinctrl_group uniphier_ld20_groups[] = { UNIPHIER_PINCTRL_GROUP(ain1), + UNIPHIER_PINCTRL_GROUP(ain1_dat2), + UNIPHIER_PINCTRL_GROUP(ain1_dat4), UNIPHIER_PINCTRL_GROUP(ain2), + UNIPHIER_PINCTRL_GROUP(ain2_dat2), + UNIPHIER_PINCTRL_GROUP(ain2_dat4), UNIPHIER_PINCTRL_GROUP(ain3), UNIPHIER_PINCTRL_GROUP(aout1), + UNIPHIER_PINCTRL_GROUP(aout1_dat2), + UNIPHIER_PINCTRL_GROUP(aout1_dat4), UNIPHIER_PINCTRL_GROUP(aout1b), + UNIPHIER_PINCTRL_GROUP(aout1b_dat2), + UNIPHIER_PINCTRL_GROUP(aout1b_dat4), UNIPHIER_PINCTRL_GROUP(aout2), + UNIPHIER_PINCTRL_GROUP(aout2_dat2), + UNIPHIER_PINCTRL_GROUP(aout2_dat4), UNIPHIER_PINCTRL_GROUP(aout3), UNIPHIER_PINCTRL_GROUP(aout4), UNIPHIER_PINCTRL_GROUP(aoutiec1), @@ -734,11 +764,17 @@ static const struct uniphier_pinctrl_group uniphier_ld20_groups[] = { UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range2), }; -static const char * const ain1_groups[] = {"ain1"}; -static const char * const ain2_groups[] = {"ain2"}; +static const char * const ain1_groups[] = {"ain1", "ain1_dat2", + "ain1_dat4"}; +static const char * const ain2_groups[] = {"ain2", "ain2_dat2", + "ain2_dat4"}; static const char * const ain3_groups[] = {"ain3"}; -static const char * const aout1_groups[] = {"aout1", "aout1b"}; -static const char * const aout2_groups[] = {"aout2"}; +static const char * const aout1_groups[] = {"aout1", "aout1_dat2", + "aout1_dat4", + "aout1b", "aout1b_dat2", + "aout1b_dat4"}; +static const char * const aout2_groups[] = {"aout2", "aout2_dat2", + "aout2_dat4"}; static const char * const aout3_groups[] = {"aout3"}; static const char * const aout4_groups[] = {"aout4"}; static const char * const aoutiec1_groups[] = {"aoutiec1"}; diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c index e52e65a24048..2a9dbf969f0b 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c @@ -721,12 +721,32 @@ static const struct pinctrl_pin_desc uniphier_pxs2_pins[] = { static const unsigned ain1_pins[] = {161, 162, 173, 174}; static const int ain1_muxvals[] = {8, 8, 8, 8}; -static const unsigned ain2_pins[] = {98, 99, 100, 101, 102, 103, 104}; -static const int ain2_muxvals[] = {8, 8, 8, 8, 8, 8, 8}; +static const unsigned ain1_dat2_pins[] = {127}; +static const int ain1_dat2_muxvals[] = {3}; +static const unsigned ain1_dat4_pins[] = {128, 129}; +static const int ain1_dat4_muxvals[] = {3, 3}; +static const unsigned ain2_pins[] = {98, 99, 100, 101}; +static const int ain2_muxvals[] = {8, 8, 8, 8}; +static const unsigned ain2_dat2_pins[] = {102}; +static const int ain2_dat2_muxvals[] = {8}; +static const unsigned ain2_dat4_pins[] = {103, 104}; +static const int ain2_dat4_muxvals[] = {8, 8}; +static const unsigned ain3_pins[] = {132, 133, 134, 131}; +static const int ain3_muxvals[] = {5, 5, 5, 5}; static const unsigned ainiec1_pins[] = {91}; static const int ainiec1_muxvals[] = {11}; -static const unsigned aout2_pins[] = {175, 176, 177, 178, 183, 184, 185}; -static const int aout2_muxvals[] = {8, 8, 8, 8, 9, 9, 9}; +static const unsigned aout1_pins[] = {87, 88, 89, 90}; +static const int aout1_muxvals[] = {11, 11, 11, 11}; +static const unsigned aout1_dat2_pins[] = {92}; +static const int aout1_dat2_muxvals[] = {11}; +static const unsigned aout1_dat4_pins[] = {93, 94}; +static const int aout1_dat4_muxvals[] = {11, 11}; +static const unsigned aout2_pins[] = {177, 178, 175, 176}; +static const int aout2_muxvals[] = {8, 8, 8, 8}; +static const unsigned aout2_dat2_pins[] = {183}; +static const int aout2_dat2_muxvals[] = {9}; +static const unsigned aout2_dat4_pins[] = {184, 185}; +static const int aout2_dat4_muxvals[] = {9, 9}; static const unsigned aout3_pins[] = {105, 106, 107, 108}; static const int aout3_muxvals[] = {8, 8, 8, 8}; static const unsigned aoutiec1_pins[] = {95}; @@ -797,8 +817,12 @@ static const unsigned uart3b_pins[] = {181, 182}; static const int uart3b_muxvals[] = {10, 10}; static const unsigned usb0_pins[] = {56, 57}; static const int usb0_muxvals[] = {8, 8}; +static const unsigned usb0_device_pins[] = {213}; +static const int usb0_device_muxvals[] = {9}; static const unsigned usb1_pins[] = {58, 59}; static const int usb1_muxvals[] = {8, 8}; +static const unsigned usb1_device_pins[] = {214}; +static const int usb1_device_muxvals[] = {9}; static const unsigned usb2_pins[] = {60, 61}; static const int usb2_muxvals[] = {8, 8}; static const unsigned usb3_pins[] = {62, 63}; @@ -838,9 +862,19 @@ static const unsigned int gpio_range1_pins[] = { static const struct uniphier_pinctrl_group uniphier_pxs2_groups[] = { UNIPHIER_PINCTRL_GROUP(ain1), + UNIPHIER_PINCTRL_GROUP(ain1_dat2), + UNIPHIER_PINCTRL_GROUP(ain1_dat4), UNIPHIER_PINCTRL_GROUP(ain2), + UNIPHIER_PINCTRL_GROUP(ain2_dat2), + UNIPHIER_PINCTRL_GROUP(ain2_dat4), + UNIPHIER_PINCTRL_GROUP(ain3), UNIPHIER_PINCTRL_GROUP(ainiec1), + UNIPHIER_PINCTRL_GROUP(aout1), + UNIPHIER_PINCTRL_GROUP(aout1_dat2), + UNIPHIER_PINCTRL_GROUP(aout1_dat4), UNIPHIER_PINCTRL_GROUP(aout2), + UNIPHIER_PINCTRL_GROUP(aout2_dat2), + UNIPHIER_PINCTRL_GROUP(aout2_dat4), UNIPHIER_PINCTRL_GROUP(aout3), UNIPHIER_PINCTRL_GROUP(aoutiec1), UNIPHIER_PINCTRL_GROUP(aoutiec2), @@ -871,17 +905,25 @@ static const struct uniphier_pinctrl_group uniphier_pxs2_groups[] = { UNIPHIER_PINCTRL_GROUP(uart3), UNIPHIER_PINCTRL_GROUP(uart3b), UNIPHIER_PINCTRL_GROUP(usb0), + UNIPHIER_PINCTRL_GROUP(usb0_device), UNIPHIER_PINCTRL_GROUP(usb1), + UNIPHIER_PINCTRL_GROUP(usb1_device), UNIPHIER_PINCTRL_GROUP(usb2), UNIPHIER_PINCTRL_GROUP(usb3), UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range0), UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range1), }; -static const char * const ain1_groups[] = {"ain1"}; -static const char * const ain2_groups[] = {"ain2"}; +static const char * const ain1_groups[] = {"ain1", "ain1_dat2", + "ain1_dat4"}; +static const char * const ain2_groups[] = {"ain2", "ain2_dat2", + "ain2_dat4"}; +static const char * const ain3_groups[] = {"ain3"}; static const char * const ainiec1_groups[] = {"ainiec1"}; -static const char * const aout2_groups[] = {"aout2"}; +static const char * const aout1_groups[] = {"aout1", "aout1_dat2", + "aout1_dat4"}; +static const char * const aout2_groups[] = {"aout2", "aout2_dat2", + "aout2_dat4"}; static const char * const aout3_groups[] = {"aout3"}; static const char * const aoutiec1_groups[] = {"aoutiec1"}; static const char * const aoutiec2_groups[] = {"aoutiec2"}; @@ -906,15 +948,17 @@ static const char * const uart0_groups[] = {"uart0", "uart0b", static const char * const uart1_groups[] = {"uart1"}; static const char * const uart2_groups[] = {"uart2"}; static const char * const uart3_groups[] = {"uart3", "uart3b"}; -static const char * const usb0_groups[] = {"usb0"}; -static const char * const usb1_groups[] = {"usb1"}; +static const char * const usb0_groups[] = {"usb0", "usb0_device"}; +static const char * const usb1_groups[] = {"usb1", "usb1_device"}; static const char * const usb2_groups[] = {"usb2"}; static const char * const usb3_groups[] = {"usb3"}; static const struct uniphier_pinmux_function uniphier_pxs2_functions[] = { UNIPHIER_PINMUX_FUNCTION(ain1), UNIPHIER_PINMUX_FUNCTION(ain2), + UNIPHIER_PINMUX_FUNCTION(ain3), UNIPHIER_PINMUX_FUNCTION(ainiec1), + UNIPHIER_PINMUX_FUNCTION(aout1), UNIPHIER_PINMUX_FUNCTION(aout2), UNIPHIER_PINMUX_FUNCTION(aout3), UNIPHIER_PINMUX_FUNCTION(aoutiec1), diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c index 4810db6c0ee8..ab3bd2d9c6c7 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c @@ -767,14 +767,30 @@ static const struct pinctrl_pin_desc uniphier_pxs3_pins[] = { 250, UNIPHIER_PIN_PULL_DOWN), }; -static const unsigned ain1_pins[] = {186, 187, 188, 189, 237, 238, 239}; -static const int ain1_muxvals[] = {0, 0, 0, 0, 1, 1, 1}; -static const unsigned ain2_pins[] = {243, 244, 245, 246, 247, 248, 249}; -static const int ain2_muxvals[] = {1, 1, 1, 1, 1, 1, 1}; -static const unsigned aout1_pins[] = {226, 227, 228, 229, 230, 231, 232}; -static const int aout1_muxvals[] = {1, 1, 1, 1, 1, 1, 1}; -static const unsigned aout2_pins[] = {192, 193, 194, 195, 196, 197, 198}; -static const int aout2_muxvals[] = {0, 0, 0, 0, 0, 0, 0}; +static const unsigned ain1_pins[] = {186, 187, 188, 189}; +static const int ain1_muxvals[] = {0, 0, 0, 0}; +static const unsigned ain1_dat2_pins[] = {237}; +static const int ain1_dat2_muxvals[] = {1}; +static const unsigned ain1_dat4_pins[] = {238, 239}; +static const int ain1_dat4_muxvals[] = {1, 1}; +static const unsigned ain2_pins[] = {243, 244, 245, 246}; +static const int ain2_muxvals[] = {1, 1, 1, 1}; +static const unsigned ain2_dat2_pins[] = {247}; +static const int ain2_dat2_muxvals[] = {1}; +static const unsigned ain2_dat4_pins[] = {248, 249}; +static const int ain2_dat4_muxvals[] = {1, 1}; +static const unsigned aout1_pins[] = {226, 227, 228, 229}; +static const int aout1_muxvals[] = {1, 1, 1, 1}; +static const unsigned aout1_dat2_pins[] = {230}; +static const int aout1_dat2_muxvals[] = {1}; +static const unsigned aout1_dat4_pins[] = {231, 232}; +static const int aout1_dat4_muxvals[] = {1, 1}; +static const unsigned aout2_pins[] = {192, 193, 194, 195}; +static const int aout2_muxvals[] = {0, 0, 0, 0}; +static const unsigned aout2_dat2_pins[] = {196}; +static const int aout2_dat2_muxvals[] = {0}; +static const unsigned aout2_dat4_pins[] = {197, 198}; +static const int aout2_dat4_muxvals[] = {0, 0}; static const unsigned aout3_pins[] = {199, 200, 201, 202}; static const int aout3_muxvals[] = {0, 0, 0, 0}; static const unsigned ainiec1_pins[] = {240}; @@ -839,8 +855,12 @@ static const unsigned int uart3_pins[] = {98, 99}; static const int uart3_muxvals[] = {0, 0}; static const unsigned int usb0_pins[] = {84, 85}; static const int usb0_muxvals[] = {0, 0}; +static const unsigned int usb0_device_pins[] = {110}; +static const int usb0_device_muxvals[] = {2}; static const unsigned int usb1_pins[] = {86, 87}; static const int usb1_muxvals[] = {0, 0}; +static const unsigned int usb1_device_pins[] = {111}; +static const int usb1_device_muxvals[] = {2}; static const unsigned int usb2_pins[] = {88, 89}; static const int usb2_muxvals[] = {0, 0}; static const unsigned int usb3_pins[] = {90, 91}; @@ -888,9 +908,17 @@ static const unsigned int gpio_range2_pins[] = { static const struct uniphier_pinctrl_group uniphier_pxs3_groups[] = { UNIPHIER_PINCTRL_GROUP(ain1), + UNIPHIER_PINCTRL_GROUP(ain1_dat2), + UNIPHIER_PINCTRL_GROUP(ain1_dat4), UNIPHIER_PINCTRL_GROUP(ain2), + UNIPHIER_PINCTRL_GROUP(ain2_dat2), + UNIPHIER_PINCTRL_GROUP(ain2_dat4), UNIPHIER_PINCTRL_GROUP(aout1), + UNIPHIER_PINCTRL_GROUP(aout1_dat2), + UNIPHIER_PINCTRL_GROUP(aout1_dat4), UNIPHIER_PINCTRL_GROUP(aout2), + UNIPHIER_PINCTRL_GROUP(aout2_dat2), + UNIPHIER_PINCTRL_GROUP(aout2_dat4), UNIPHIER_PINCTRL_GROUP(aout3), UNIPHIER_PINCTRL_GROUP(ainiec1), UNIPHIER_PINCTRL_GROUP(aoutiec1), @@ -918,7 +946,9 @@ static const struct uniphier_pinctrl_group uniphier_pxs3_groups[] = { UNIPHIER_PINCTRL_GROUP(uart2), UNIPHIER_PINCTRL_GROUP(uart3), UNIPHIER_PINCTRL_GROUP(usb0), + UNIPHIER_PINCTRL_GROUP(usb0_device), UNIPHIER_PINCTRL_GROUP(usb1), + UNIPHIER_PINCTRL_GROUP(usb1_device), UNIPHIER_PINCTRL_GROUP(usb2), UNIPHIER_PINCTRL_GROUP(usb3), UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range0), @@ -926,10 +956,14 @@ static const struct uniphier_pinctrl_group uniphier_pxs3_groups[] = { UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range2), }; -static const char * const ain1_groups[] = {"ain1"}; -static const char * const ain2_groups[] = {"ain2"}; -static const char * const aout1_groups[] = {"aout1"}; -static const char * const aout2_groups[] = {"aout2"}; +static const char * const ain1_groups[] = {"ain1", "ain1_dat2", + "ain1_dat4"}; +static const char * const ain2_groups[] = {"ain2", "ain2_dat2", + "ain1_dat4"}; +static const char * const aout1_groups[] = {"aout1", "aout1_dat2", + "aout1_dat4"}; +static const char * const aout2_groups[] = {"aout2", "aout2_dat2", + "aout2_dat4"}; static const char * const aout3_groups[] = {"aout3"}; static const char * const ainiec1_groups[] = {"ainiec1"}; static const char * const aoutiec1_groups[] = {"aoutiec1"}; @@ -954,8 +988,8 @@ static const char * const uart0_groups[] = {"uart0", "uart0_ctsrts", static const char * const uart1_groups[] = {"uart1"}; static const char * const uart2_groups[] = {"uart2"}; static const char * const uart3_groups[] = {"uart3"}; -static const char * const usb0_groups[] = {"usb0"}; -static const char * const usb1_groups[] = {"usb1"}; +static const char * const usb0_groups[] = {"usb0", "usb0_device"}; +static const char * const usb1_groups[] = {"usb1", "usb1_device"}; static const char * const usb2_groups[] = {"usb2"}; static const char * const usb3_groups[] = {"usb3"}; diff --git a/include/dt-bindings/gpio/meson-s4-gpio.h b/include/dt-bindings/gpio/meson-s4-gpio.h new file mode 100644 index 000000000000..35aee21b94f1 --- /dev/null +++ b/include/dt-bindings/gpio/meson-s4-gpio.h @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2021 Amlogic, Inc. All rights reserved. + * Author: Qianggui Song <[email protected]> + */ + +#ifndef _DT_BINDINGS_MESON_S4_GPIO_H +#define _DT_BINDINGS_MESON_S4_GPIO_H + +#define GPIOB_0 0 +#define GPIOB_1 1 +#define GPIOB_2 2 +#define GPIOB_3 3 +#define GPIOB_4 4 +#define GPIOB_5 5 +#define GPIOB_6 6 +#define GPIOB_7 7 +#define GPIOB_8 8 +#define GPIOB_9 9 +#define GPIOB_10 10 +#define GPIOB_11 11 +#define GPIOB_12 12 +#define GPIOB_13 13 + +#define GPIOC_0 14 +#define GPIOC_1 15 +#define GPIOC_2 16 +#define GPIOC_3 17 +#define GPIOC_4 18 +#define GPIOC_5 19 +#define GPIOC_6 20 +#define GPIOC_7 21 + +#define GPIOE_0 22 +#define GPIOE_1 23 + +#define GPIOD_0 24 +#define GPIOD_1 25 +#define GPIOD_2 26 +#define GPIOD_3 27 +#define GPIOD_4 28 +#define GPIOD_5 29 +#define GPIOD_6 30 +#define GPIOD_7 31 +#define GPIOD_8 32 +#define GPIOD_9 33 +#define GPIOD_10 34 +#define GPIOD_11 35 + +#define GPIOH_0 36 +#define GPIOH_1 37 +#define GPIOH_2 38 +#define GPIOH_3 39 +#define GPIOH_4 40 +#define GPIOH_5 41 +#define GPIOH_6 42 +#define GPIOH_7 43 +#define GPIOH_8 44 +#define GPIOH_9 45 +#define GPIOH_10 46 +#define GPIOH_11 47 + +#define GPIOX_0 48 +#define GPIOX_1 49 +#define GPIOX_2 50 +#define GPIOX_3 51 +#define GPIOX_4 52 +#define GPIOX_5 53 +#define GPIOX_6 54 +#define GPIOX_7 55 +#define GPIOX_8 56 +#define GPIOX_9 57 +#define GPIOX_10 58 +#define GPIOX_11 59 +#define GPIOX_12 60 +#define GPIOX_13 61 +#define GPIOX_14 62 +#define GPIOX_15 63 +#define GPIOX_16 64 +#define GPIOX_17 65 +#define GPIOX_18 66 +#define GPIOX_19 67 + +#define GPIOZ_0 68 +#define GPIOZ_1 69 +#define GPIOZ_2 70 +#define GPIOZ_3 71 +#define GPIOZ_4 72 +#define GPIOZ_5 73 +#define GPIOZ_6 74 +#define GPIOZ_7 75 +#define GPIOZ_8 76 +#define GPIOZ_9 77 +#define GPIOZ_10 78 +#define GPIOZ_11 79 +#define GPIOZ_12 80 + +#define GPIO_TEST_N 81 +#endif /* _DT_BINDINGS_MESON_S4_GPIO_H */ diff --git a/include/dt-bindings/pinctrl/sppctl-sp7021.h b/include/dt-bindings/pinctrl/sppctl-sp7021.h new file mode 100644 index 000000000000..629aa9b5ffbc --- /dev/null +++ b/include/dt-bindings/pinctrl/sppctl-sp7021.h @@ -0,0 +1,179 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Sunplus SP7021 dt-bindings Pinctrl header file + * Copyright (C) Sunplus Tech/Tibbo Tech. + * Author: Dvorkin Dmitry <[email protected]> + */ + +#ifndef __DT_BINDINGS_PINCTRL_SPPCTL_SP7021_H__ +#define __DT_BINDINGS_PINCTRL_SPPCTL_SP7021_H__ + +#include <dt-bindings/pinctrl/sppctl.h> + +/* + * Please don't change the order of the following defines. + * They are based on order of 'hardware' control register + * defined in MOON2 ~ MOON3 registers. + */ +#define MUXF_GPIO 0 +#define MUXF_IOP 1 +#define MUXF_L2SW_CLK_OUT 2 +#define MUXF_L2SW_MAC_SMI_MDC 3 +#define MUXF_L2SW_LED_FLASH0 4 +#define MUXF_L2SW_LED_FLASH1 5 +#define MUXF_L2SW_LED_ON0 6 +#define MUXF_L2SW_LED_ON1 7 +#define MUXF_L2SW_MAC_SMI_MDIO 8 +#define MUXF_L2SW_P0_MAC_RMII_TXEN 9 +#define MUXF_L2SW_P0_MAC_RMII_TXD0 10 +#define MUXF_L2SW_P0_MAC_RMII_TXD1 11 +#define MUXF_L2SW_P0_MAC_RMII_CRSDV 12 +#define MUXF_L2SW_P0_MAC_RMII_RXD0 13 +#define MUXF_L2SW_P0_MAC_RMII_RXD1 14 +#define MUXF_L2SW_P0_MAC_RMII_RXER 15 +#define MUXF_L2SW_P1_MAC_RMII_TXEN 16 +#define MUXF_L2SW_P1_MAC_RMII_TXD0 17 +#define MUXF_L2SW_P1_MAC_RMII_TXD1 18 +#define MUXF_L2SW_P1_MAC_RMII_CRSDV 19 +#define MUXF_L2SW_P1_MAC_RMII_RXD0 20 +#define MUXF_L2SW_P1_MAC_RMII_RXD1 21 +#define MUXF_L2SW_P1_MAC_RMII_RXER 22 +#define MUXF_DAISY_MODE 23 +#define MUXF_SDIO_CLK 24 +#define MUXF_SDIO_CMD 25 +#define MUXF_SDIO_D0 26 +#define MUXF_SDIO_D1 27 +#define MUXF_SDIO_D2 28 +#define MUXF_SDIO_D3 29 +#define MUXF_PWM0 30 +#define MUXF_PWM1 31 +#define MUXF_PWM2 32 +#define MUXF_PWM3 33 +#define MUXF_PWM4 34 +#define MUXF_PWM5 35 +#define MUXF_PWM6 36 +#define MUXF_PWM7 37 +#define MUXF_ICM0_D 38 +#define MUXF_ICM1_D 39 +#define MUXF_ICM2_D 40 +#define MUXF_ICM3_D 41 +#define MUXF_ICM0_CLK 42 +#define MUXF_ICM1_CLK 43 +#define MUXF_ICM2_CLK 44 +#define MUXF_ICM3_CLK 45 +#define MUXF_SPIM0_INT 46 +#define MUXF_SPIM0_CLK 47 +#define MUXF_SPIM0_EN 48 +#define MUXF_SPIM0_DO 49 +#define MUXF_SPIM0_DI 50 +#define MUXF_SPIM1_INT 51 +#define MUXF_SPIM1_CLK 52 +#define MUXF_SPIM1_EN 53 +#define MUXF_SPIM1_DO 54 +#define MUXF_SPIM1_DI 55 +#define MUXF_SPIM2_INT 56 +#define MUXF_SPIM2_CLK 57 +#define MUXF_SPIM2_EN 58 +#define MUXF_SPIM2_DO 59 +#define MUXF_SPIM2_DI 60 +#define MUXF_SPIM3_INT 61 +#define MUXF_SPIM3_CLK 62 +#define MUXF_SPIM3_EN 63 +#define MUXF_SPIM3_DO 64 +#define MUXF_SPIM3_DI 65 +#define MUXF_SPI0S_INT 66 +#define MUXF_SPI0S_CLK 67 +#define MUXF_SPI0S_EN 68 +#define MUXF_SPI0S_DO 69 +#define MUXF_SPI0S_DI 70 +#define MUXF_SPI1S_INT 71 +#define MUXF_SPI1S_CLK 72 +#define MUXF_SPI1S_EN 73 +#define MUXF_SPI1S_DO 74 +#define MUXF_SPI1S_DI 75 +#define MUXF_SPI2S_INT 76 +#define MUXF_SPI2S_CLK 77 +#define MUXF_SPI2S_EN 78 +#define MUXF_SPI2S_DO 79 +#define MUXF_SPI2S_DI 80 +#define MUXF_SPI3S_INT 81 +#define MUXF_SPI3S_CLK 82 +#define MUXF_SPI3S_EN 83 +#define MUXF_SPI3S_DO 84 +#define MUXF_SPI3S_DI 85 +#define MUXF_I2CM0_CLK 86 +#define MUXF_I2CM0_DAT 87 +#define MUXF_I2CM1_CLK 88 +#define MUXF_I2CM1_DAT 89 +#define MUXF_I2CM2_CLK 90 +#define MUXF_I2CM2_DAT 91 +#define MUXF_I2CM3_CLK 92 +#define MUXF_I2CM3_DAT 93 +#define MUXF_UA1_TX 94 +#define MUXF_UA1_RX 95 +#define MUXF_UA1_CTS 96 +#define MUXF_UA1_RTS 97 +#define MUXF_UA2_TX 98 +#define MUXF_UA2_RX 99 +#define MUXF_UA2_CTS 100 +#define MUXF_UA2_RTS 101 +#define MUXF_UA3_TX 102 +#define MUXF_UA3_RX 103 +#define MUXF_UA3_CTS 104 +#define MUXF_UA3_RTS 105 +#define MUXF_UA4_TX 106 +#define MUXF_UA4_RX 107 +#define MUXF_UA4_CTS 108 +#define MUXF_UA4_RTS 109 +#define MUXF_TIMER0_INT 110 +#define MUXF_TIMER1_INT 111 +#define MUXF_TIMER2_INT 112 +#define MUXF_TIMER3_INT 113 +#define MUXF_GPIO_INT0 114 +#define MUXF_GPIO_INT1 115 +#define MUXF_GPIO_INT2 116 +#define MUXF_GPIO_INT3 117 +#define MUXF_GPIO_INT4 118 +#define MUXF_GPIO_INT5 119 +#define MUXF_GPIO_INT6 120 +#define MUXF_GPIO_INT7 121 + +/* + * Please don't change the order of the following defines. + * They are based on order of items in array 'sppctl_list_funcs' + * in Sunplus pinctrl driver. + */ +#define GROP_SPI_FLASH 122 +#define GROP_SPI_FLASH_4BIT 123 +#define GROP_SPI_NAND 124 +#define GROP_CARD0_EMMC 125 +#define GROP_SD_CARD 126 +#define GROP_UA0 127 +#define GROP_ACHIP_DEBUG 128 +#define GROP_ACHIP_UA2AXI 129 +#define GROP_FPGA_IFX 130 +#define GROP_HDMI_TX 131 +#define GROP_AUD_EXT_ADC_IFX0 132 +#define GROP_AUD_EXT_DAC_IFX0 133 +#define GROP_SPDIF_RX 134 +#define GROP_SPDIF_TX 135 +#define GROP_TDMTX_IFX0 136 +#define GROP_TDMRX_IFX0 137 +#define GROP_PDMRX_IFX0 138 +#define GROP_PCM_IEC_TX 139 +#define GROP_LCDIF 140 +#define GROP_DVD_DSP_DEBUG 141 +#define GROP_I2C_DEBUG 142 +#define GROP_I2C_SLAVE 143 +#define GROP_WAKEUP 144 +#define GROP_UART2AXI 145 +#define GROP_USB0_I2C 146 +#define GROP_USB1_I2C 147 +#define GROP_USB0_OTG 148 +#define GROP_USB1_OTG 149 +#define GROP_UPHY0_DEBUG 150 +#define GROP_UPHY1_DEBUG 151 +#define GROP_UPHY0_EXT 152 +#define GROP_PROBE_PORT 153 + +#endif diff --git a/include/dt-bindings/pinctrl/sppctl.h b/include/dt-bindings/pinctrl/sppctl.h new file mode 100644 index 000000000000..50557265dbfc --- /dev/null +++ b/include/dt-bindings/pinctrl/sppctl.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Sunplus dt-bindings Pinctrl header file + * Copyright (C) Sunplus Tech / Tibbo Tech. + * Author: Dvorkin Dmitry <[email protected]> + */ + +#ifndef __DT_BINDINGS_PINCTRL_SPPCTL_H__ +#define __DT_BINDINGS_PINCTRL_SPPCTL_H__ + +#define IOP_G_MASTE (0x01 << 0) +#define IOP_G_FIRST (0x01 << 1) + +#define SPPCTL_PCTL_G_PMUX (0x00 | IOP_G_MASTE) +#define SPPCTL_PCTL_G_GPIO (IOP_G_FIRST | IOP_G_MASTE) +#define SPPCTL_PCTL_G_IOPP (IOP_G_FIRST | 0x00) + +#define SPPCTL_PCTL_L_OUT (0x01 << 0) /* Output LOW */ +#define SPPCTL_PCTL_L_OU1 (0x01 << 1) /* Output HIGH */ +#define SPPCTL_PCTL_L_INV (0x01 << 2) /* Input Invert */ +#define SPPCTL_PCTL_L_ONV (0x01 << 3) /* Output Invert */ +#define SPPCTL_PCTL_L_ODR (0x01 << 4) /* Output Open Drain */ + +/* + * pack into 32-bit value: + * pin# (8bit), typ (8bit), function (8bit), flag (8bit) + */ +#define SPPCTL_IOPAD(pin, typ, fun, flg) (((pin) << 24) | ((typ) << 16) | \ + ((fun) << 8) | (flg)) + +#endif |