diff options
| -rw-r--r-- | arch/arm64/boot/dts/mediatek/mt6795.dtsi | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi index ae2eaad99cda..bb575837e4ce 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -382,5 +382,46 @@ dma-names = "tx", "rx"; status = "disabled"; }; + + mmc0: mmc@11230000 { + compatible = "mediatek,mt6795-mmc"; + reg = <0 0x11230000 0 0x1000>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; + clocks = <&pericfg CLK_PERI_MSDC30_0>, + <&topckgen CLK_TOP_MSDC50_0_H_SEL>, + <&topckgen CLK_TOP_MSDC50_0_SEL>; + clock-names = "source", "hclk", "source_cg"; + status = "disabled"; + }; + + mmc1: mmc@11240000 { + compatible = "mediatek,mt6795-mmc"; + reg = <0 0x11240000 0 0x1000>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; + clocks = <&pericfg CLK_PERI_MSDC30_1>, + <&topckgen CLK_TOP_AXI_SEL>; + clock-names = "source", "hclk"; + status = "disabled"; + }; + + mmc2: mmc@11250000 { + compatible = "mediatek,mt6795-mmc"; + reg = <0 0x11250000 0 0x1000>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; + clocks = <&pericfg CLK_PERI_MSDC30_2>, + <&topckgen CLK_TOP_AXI_SEL>; + clock-names = "source", "hclk"; + status = "disabled"; + }; + + mmc3: mmc@11260000 { + compatible = "mediatek,mt6795-mmc"; + reg = <0 0x11260000 0 0x1000>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; + clocks = <&pericfg CLK_PERI_MSDC30_3>, + <&topckgen CLK_TOP_AXI_SEL>; + clock-names = "source", "hclk"; + status = "disabled"; + }; }; }; |