diff options
| -rw-r--r-- | drivers/gpu/drm/xe/regs/xe_engine_regs.h | 9 | ||||
| -rw-r--r-- | drivers/gpu/drm/xe/xe_wa.c | 2 |
2 files changed, 5 insertions, 6 deletions
diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h index 1a857c4edcf5..67da19f9836f 100644 --- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h @@ -46,11 +46,6 @@ #define RING_ESR(base) XE_REG((base) + 0xb8) #define RING_CMD_CCTL(base) XE_REG((base) + 0xc4, XE_REG_OPTION_MASKED) - -#define CSFE_CHICKEN1_REG(base) XE_REG((base) + 0xd4, XE_REG_OPTION_MASKED) -#define GHWSP_CSB_REPORT_DIS REG_BIT(15) -#define PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS REG_BIT(14) - /* * CMD_CCTL read/write fields take a MOCS value and _not_ a table index. * The lsb of each can be considered a separate enabling bit for encryption. @@ -61,6 +56,10 @@ #define CMD_CCTL_WRITE_OVERRIDE_MASK REG_GENMASK(13, 8) #define CMD_CCTL_READ_OVERRIDE_MASK REG_GENMASK(6, 1) +#define CSFE_CHICKEN1(base) XE_REG((base) + 0xd4, XE_REG_OPTION_MASKED) +#define GHWSP_CSB_REPORT_DIS REG_BIT(15) +#define PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS REG_BIT(14) + #define RING_BBADDR(base) XE_REG((base) + 0x140) #define RING_BBADDR_UDW(base) XE_REG((base) + 0x168) diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c index 23f1285135b8..12829748bb6c 100644 --- a/drivers/gpu/drm/xe/xe_wa.c +++ b/drivers/gpu/drm/xe/xe_wa.c @@ -605,7 +605,7 @@ static const struct xe_rtp_entry_sr engine_was[] = { */ { XE_RTP_NAME("18032095049, 16021639441"), XE_RTP_RULES(GRAPHICS_VERSION(2004)), - XE_RTP_ACTIONS(SET(CSFE_CHICKEN1_REG(0), + XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), GHWSP_CSB_REPORT_DIS | PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS, XE_RTP_ACTION_FLAG(ENGINE_BASE))) |