diff options
107 files changed, 3517 insertions, 1893 deletions
diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-chipid.txt b/Documentation/devicetree/bindings/arm/samsung/exynos-chipid.txt deleted file mode 100644 index 85c5dfd4a720..000000000000 --- a/Documentation/devicetree/bindings/arm/samsung/exynos-chipid.txt +++ /dev/null @@ -1,12 +0,0 @@ -SAMSUNG Exynos SoCs Chipid driver. - -Required properties: -- compatible : Should at least contain "samsung,exynos4210-chipid". - -- reg: offset and length of the register set - -Example: - chipid@10000000 { - compatible = "samsung,exynos4210-chipid"; - reg = <0x10000000 0x100>; - }; diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-chipid.yaml b/Documentation/devicetree/bindings/arm/samsung/exynos-chipid.yaml new file mode 100644 index 000000000000..53c29d567789 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/samsung/exynos-chipid.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/samsung/exynos-chipid.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos SoC series Chipid driver + +maintainers: + - Krzysztof Kozlowski <[email protected]> + +properties: + compatible: + items: + - const: samsung,exynos4210-chipid + - const: syscon + + reg: + maxItems: 1 + + samsung,asv-bin: + description: + Adaptive Supply Voltage bin selection. This can be used + to determine the ASV bin of an SoC if respective information + is missing in the CHIPID registers or in the OTP memory. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [ 0, 1, 2, 3 ] + +required: + - compatible + - reg + +examples: + - | + chipid@10000000 { + compatible = "samsung,exynos4210-chipid", "syscon"; + reg = <0x10000000 0x100>; + samsung,asv-bin = <2>; + }; diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt b/Documentation/devicetree/bindings/arm/samsung/pmu.txt deleted file mode 100644 index 433bfd7593ac..000000000000 --- a/Documentation/devicetree/bindings/arm/samsung/pmu.txt +++ /dev/null @@ -1,72 +0,0 @@ -SAMSUNG Exynos SoC series PMU Registers - -Properties: - - compatible : should contain two values. First value must be one from following list: - - "samsung,exynos3250-pmu" - for Exynos3250 SoC, - - "samsung,exynos4210-pmu" - for Exynos4210 SoC, - - "samsung,exynos4412-pmu" - for Exynos4412 SoC, - - "samsung,exynos5250-pmu" - for Exynos5250 SoC, - - "samsung,exynos5260-pmu" - for Exynos5260 SoC. - - "samsung,exynos5410-pmu" - for Exynos5410 SoC, - - "samsung,exynos5420-pmu" - for Exynos5420 SoC. - - "samsung,exynos5433-pmu" - for Exynos5433 SoC. - - "samsung,exynos7-pmu" - for Exynos7 SoC. - second value must be always "syscon". - - - reg : offset and length of the register set. - - - #clock-cells : must be <1>, since PMU requires once cell as clock specifier. - The single specifier cell is used as index to list of clocks - provided by PMU, which is currently: - 0 : SoC clock output (CLKOUT pin) - - - clock-names : list of clock names for particular CLKOUT mux inputs in - following format: - "clkoutN", where N is a decimal number corresponding to - CLKOUT mux control bits value for given input, e.g. - "clkout0", "clkout7", "clkout15". - - - clocks : list of phandles and specifiers to all input clocks listed in - clock-names property. - -Optional properties: - -Some PMUs are capable of behaving as an interrupt controller (mostly -to wake up a suspended PMU). In which case, they can have the -following properties: - -- interrupt-controller: indicate that said PMU is an interrupt controller - -- #interrupt-cells: must be identical to the that of the parent interrupt - controller. - - -Optional nodes: - -- nodes defining the restart and poweroff syscon children - - -Example : -pmu_system_controller: system-controller@10040000 { - compatible = "samsung,exynos5250-pmu", "syscon"; - reg = <0x10040000 0x5000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - #clock-cells = <1>; - clock-names = "clkout0", "clkout1", "clkout2", "clkout3", - "clkout4", "clkout8", "clkout9"; - clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>, - <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>, - <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, - <&clock CLK_XUSBXTI>; -}; - -Example of clock consumer : - -usb3503: usb3503@8 { - /* ... */ - clock-names = "refclk"; - clocks = <&pmu_system_controller 0>; - /* ... */ -}; diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.yaml b/Documentation/devicetree/bindings/arm/samsung/pmu.yaml new file mode 100644 index 000000000000..73b56fc5bf58 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/samsung/pmu.yaml @@ -0,0 +1,105 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/samsung/pmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos SoC series Power Management Unit (PMU) + +maintainers: + - Krzysztof Kozlowski <[email protected]> + +# Custom select to avoid matching all nodes with 'syscon' +select: + properties: + compatible: + contains: + enum: + - samsung,exynos3250-pmu + - samsung,exynos4210-pmu + - samsung,exynos4412-pmu + - samsung,exynos5250-pmu + - samsung,exynos5260-pmu + - samsung,exynos5410-pmu + - samsung,exynos5420-pmu + - samsung,exynos5433-pmu + - samsung,exynos7-pmu + required: + - compatible + +properties: + compatible: + items: + - enum: + - samsung,exynos3250-pmu + - samsung,exynos4210-pmu + - samsung,exynos4412-pmu + - samsung,exynos5250-pmu + - samsung,exynos5260-pmu + - samsung,exynos5410-pmu + - samsung,exynos5420-pmu + - samsung,exynos5433-pmu + - samsung,exynos7-pmu + - const: syscon + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + clock-names: + description: + List of clock names for particular CLKOUT mux inputs + minItems: 1 + maxItems: 32 + items: + pattern: '^clkout([0-9]|[12][0-9]|3[0-1])$' + + clocks: + minItems: 1 + maxItems: 32 + + interrupt-controller: + description: + Some PMUs are capable of behaving as an interrupt controller (mostly + to wake up a suspended PMU). + + '#interrupt-cells': + description: + Must be identical to the that of the parent interrupt controller. + const: 3 + + syscon-poweroff: + $ref: "../../power/reset/syscon-poweroff.yaml#" + type: object + description: + Node for power off method + + syscon-reboot: + $ref: "../../power/reset/syscon-reboot.yaml#" + type: object + description: + Node for reboot method + +required: + - compatible + - reg + - '#clock-cells' + - clock-names + - clocks + +examples: + - | + #include <dt-bindings/clock/exynos5250.h> + + pmu_system_controller: system-controller@10040000 { + compatible = "samsung,exynos5250-pmu", "syscon"; + reg = <0x10040000 0x5000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + #clock-cells = <1>; + clock-names = "clkout16"; + clocks = <&clock CLK_FIN_PLL>; + }; diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt deleted file mode 100644 index 56021bf2a916..000000000000 --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt +++ /dev/null @@ -1,83 +0,0 @@ -* Samsung's Exynos and S5P SoC based boards - -Required root node properties: - - compatible = should be one or more of the following. - - "samsung,aries" - for S5PV210-based Samsung Aries board. - - "samsung,fascinate4g" - for S5PV210-based Samsung Galaxy S Fascinate 4G (SGH-T959P) board. - - "samsung,galaxys" - for S5PV210-based Samsung Galaxy S (i9000) board. - - "samsung,artik5" - for Exynos3250-based Samsung ARTIK5 module. - - "samsung,artik5-eval" - for Exynos3250-based Samsung ARTIK5 eval board. - - "samsung,monk" - for Exynos3250-based Samsung Simband board. - - "samsung,rinato" - for Exynos3250-based Samsung Gear2 board. - - "samsung,smdkv310" - for Exynos4210-based Samsung SMDKV310 eval board. - - "samsung,trats" - for Exynos4210-based Tizen Reference board. - - "samsung,universal_c210" - for Exynos4210-based Samsung board. - - "samsung,i9300" - for Exynos4412-based Samsung GT-I9300 board. - - "samsung,i9305" - for Exynos4412-based Samsung GT-I9305 board. - - "samsung,midas" - for Exynos4412-based Samsung Midas board. - - "samsung,smdk4412", - for Exynos4412-based Samsung SMDK4412 eval board. - - "samsung,n710x" - for Exynos4412-based Samsung GT-N7100/GT-N7105 board. - - "samsung,trats2" - for Exynos4412-based Tizen Reference board. - - "samsung,smdk5250" - for Exynos5250-based Samsung SMDK5250 eval board. - - "samsung,xyref5260" - for Exynos5260-based Samsung board. - - "samsung,smdk5410" - for Exynos5410-based Samsung SMDK5410 eval board. - - "samsung,smdk5420" - for Exynos5420-based Samsung SMDK5420 eval board. - - "samsung,tm2" - for Exynos5433-based Samsung TM2 board. - - "samsung,tm2e" - for Exynos5433-based Samsung TM2E board. - -* Other companies Exynos SoC based - * FriendlyARM - - "friendlyarm,tiny4412" - for Exynos4412-based FriendlyARM - TINY4412 board. - * TOPEET - - "topeet,itop4412-elite" - for Exynos4412-based TOPEET - Elite base board. - - * Google - - "google,pi" - for Exynos5800-based Google Peach Pi - Rev 10+ board, - also: "google,pi-rev16", "google,pi-rev15", "google,pi-rev14", - "google,pi-rev13", "google,pi-rev12", "google,pi-rev11", - "google,pi-rev10", "google,peach". - - - "google,pit" - for Exynos5420-based Google Peach Pit - Rev 6+ (Exynos5420), - also: "google,pit-rev16", "google,pit-rev15", "google,pit-rev14", - "google,pit-rev13", "google,pit-rev12", "google,pit-rev11", - "google,pit-rev10", "google,pit-rev9", "google,pit-rev8", - "google,pit-rev7", "google,pit-rev6", "google,peach". - - - "google,snow-rev4" - for Exynos5250-based Google Snow board, - also: "google,snow" - - "google,snow-rev5" - for Exynos5250-based Google Snow - Rev 5+ board. - - "google,spring" - for Exynos5250-based Google Spring board. - - * Hardkernel - - "hardkernel,odroid-u3" - for Exynos4412-based Hardkernel Odroid U3. - - "hardkernel,odroid-x" - for Exynos4412-based Hardkernel Odroid X. - - "hardkernel,odroid-x2" - for Exynos4412-based Hardkernel Odroid X2. - - "hardkernel,odroid-xu" - for Exynos5410-based Hardkernel Odroid XU. - - "hardkernel,odroid-xu3" - for Exynos5422-based Hardkernel Odroid XU3. - - "hardkernel,odroid-xu3-lite" - for Exynos5422-based Hardkernel - Odroid XU3 Lite board. - - "hardkernel,odroid-xu4" - for Exynos5422-based Hardkernel Odroid XU4. - - "hardkernel,odroid-hc1" - for Exynos5422-based Hardkernel Odroid HC1. - - * Insignal - - "insignal,arndale" - for Exynos5250-based Insignal Arndale board. - - "insignal,arndale-octa" - for Exynos5420-based Insignal Arndale - Octa board. - - "insignal,origen" - for Exynos4210-based Insignal Origen board. - - "insignal,origen4412" - for Exynos4412-based Insignal Origen board. - - -Optional nodes: - - firmware node, specifying presence and type of secure firmware: - - compatible: only "samsung,secure-firmware" is currently supported - - reg: address of non-secure SYSRAM used for communication with firmware - - firmware@203f000 { - compatible = "samsung,secure-firmware"; - reg = <0x0203F000 0x1000>; - }; diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml new file mode 100644 index 000000000000..63acd57c4799 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml @@ -0,0 +1,181 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/samsung/samsung-boards.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos and S5P SoC based boards + +maintainers: + - Krzysztof Kozlowski <[email protected]> + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: S5PV210 based boards + items: + - enum: + - aesop,torbreck # aESOP Torbreck based on S5PV210 + - samsung,aquila # Samsung Aquila based on S5PC110 + - samsung,goni # Samsung Goni based on S5PC110 + - yic,smdkc110 # YIC System SMDKC110 based on S5PC110 + - yic,smdkv210 # YIC System SMDKV210 based on S5PV210 + - const: samsung,s5pv210 + + - description: S5PV210 based Aries boards + items: + - enum: + - samsung,fascinate4g # Samsung Galaxy S Fascinate 4G (SGH-T959P) + - samsung,galaxys # Samsung Galaxy S (i9000) + - const: samsung,aries + - const: samsung,s5pv210 + + - description: Exynos3250 based boards + items: + - enum: + - samsung,monk # Samsung Simband + - samsung,rinato # Samsung Gear2 + - const: samsung,exynos3250 + - const: samsung,exynos3 + + - description: Samsung ARTIK5 boards + items: + - enum: + - samsung,artik5-eval # Samsung ARTIK5 eval board + - const: samsung,artik5 # Samsung ARTIK5 module + - const: samsung,exynos3250 + - const: samsung,exynos3 + + - description: Exynos4210 based boards + items: + - enum: + - insignal,origen # Insignal Origen + - samsung,smdkv310 # Samsung SMDKV310 eval + - samsung,trats # Samsung Tizen Reference + - samsung,universal_c210 # Samsung C210 + - const: samsung,exynos4210 + - const: samsung,exynos4 + + - description: Exynos4412 based boards + items: + - enum: + - friendlyarm,tiny4412 # FriendlyARM TINY4412 + - hardkernel,odroid-u3 # Hardkernel Odroid U3 + - hardkernel,odroid-x # Hardkernel Odroid X + - hardkernel,odroid-x2 # Hardkernel Odroid X2 + - insignal,origen4412 # Insignal Origen + - samsung,smdk4412 # Samsung SMDK4412 eval + - topeet,itop4412-elite # TOPEET Elite base + - const: samsung,exynos4412 + - const: samsung,exynos4 + + - description: Samsung Midas family boards + items: + - enum: + - samsung,i9300 # Samsung GT-I9300 + - samsung,i9305 # Samsung GT-I9305 + - samsung,n710x # Samsung GT-N7100/GT-N7105 + - samsung,trats2 # Samsung Tizen Reference + - const: samsung,midas + - const: samsung,exynos4412 + - const: samsung,exynos4 + + - description: Exynos5250 based boards + items: + - enum: + - google,snow-rev5 # Google Snow Rev 5+ + - google,spring # Google Spring + - insignal,arndale # Insignal Arndale + - samsung,smdk5250 # Samsung SMDK5250 eval + - const: samsung,exynos5250 + - const: samsung,exynos5 + + - description: Google Snow Boards (Rev 4+) + items: + - const: google,snow-rev4 + - const: google,snow + - const: samsung,exynos5250 + - const: samsung,exynos5 + + - description: Exynos5260 based boards + items: + - enum: + - samsung,xyref5260 # Samsung Xyref5260 eval + - const: samsung,exynos5260 + - const: samsung,exynos5 + + - description: Exynos5410 based boards + items: + - enum: + - hardkernel,odroid-xu # Hardkernel Odroid XU + - samsung,smdk5410 # Samsung SMDK5410 eval + - const: samsung,exynos5410 + - const: samsung,exynos5 + + - description: Exynos5420 based boards + items: + - enum: + - insignal,arndale-octa # Insignal Arndale Octa + - samsung,smdk5420 # Samsung SMDK5420 eval + - const: samsung,exynos5420 + - const: samsung,exynos5 + + - description: Google Peach Pit Boards (Rev 6+) + items: + - const: google,pit-rev16 + - const: google,pit-rev15 + - const: google,pit-rev14 + - const: google,pit-rev13 + - const: google,pit-rev12 + - const: google,pit-rev11 + - const: google,pit-rev10 + - const: google,pit-rev9 + - const: google,pit-rev8 + - const: google,pit-rev7 + - const: google,pit-rev6 + - const: google,pit + - const: google,peach + - const: samsung,exynos5420 + - const: samsung,exynos5 + + - description: Exynos5800 based boards + items: + - enum: + - hardkernel,odroid-xu3 # Hardkernel Odroid XU3 + - hardkernel,odroid-xu3-lite # Hardkernel Odroid XU3 Lite + - hardkernel,odroid-xu4 # Hardkernel Odroid XU4 + - hardkernel,odroid-hc1 # Hardkernel Odroid HC1 + - const: samsung,exynos5800 + - const: samsung,exynos5 + + - description: Google Peach Pi Boards (Rev 10+) + items: + - const: google,pi-rev16 + - const: google,pi-rev15 + - const: google,pi-rev14 + - const: google,pi-rev13 + - const: google,pi-rev12 + - const: google,pi-rev11 + - const: google,pi-rev10 + - const: google,pi + - const: google,peach + - const: samsung,exynos5800 + - const: samsung,exynos5 + + - description: Exynos5433 based boards + items: + - enum: + - samsung,tm2 # Samsung TM2 + - samsung,tm2e # Samsung TM2E + - const: samsung,exynos5433 + + - description: Exynos7 based boards + items: + - enum: + - samsung,exynos7-espresso # Samsung Exynos7 Espresso + - const: samsung,exynos7 + +required: + - compatible diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-secure-firmware.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-secure-firmware.yaml new file mode 100644 index 000000000000..51d23b6f8a94 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-secure-firmware.yaml @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/samsung/samsung-secure-firmware.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos Secure Firmware + +maintainers: + - Krzysztof Kozlowski <[email protected]> + +properties: + compatible: + items: + - const: samsung,secure-firmware + + reg: + description: + Address of non-secure SYSRAM used for communication with firmware. + maxItems: 1 + +required: + - compatible + - reg + +examples: + - | + firmware@203f000 { + compatible = "samsung,secure-firmware"; + reg = <0x0203f000 0x1000>; + }; diff --git a/Documentation/devicetree/bindings/arm/samsung/sysreg.txt b/Documentation/devicetree/bindings/arm/samsung/sysreg.txt deleted file mode 100644 index 4fced6e9d5e4..000000000000 --- a/Documentation/devicetree/bindings/arm/samsung/sysreg.txt +++ /dev/null @@ -1,19 +0,0 @@ -SAMSUNG S5P/Exynos SoC series System Registers (SYSREG) - -Properties: - - compatible : should contain two values. First value must be one from following list: - - "samsung,exynos4-sysreg" - for Exynos4 based SoCs, - - "samsung,exynos5-sysreg" - for Exynos5 based SoCs. - second value must be always "syscon". - - reg : offset and length of the register set. - -Example: - syscon@10010000 { - compatible = "samsung,exynos4-sysreg", "syscon"; - reg = <0x10010000 0x400>; - }; - - syscon@10050000 { - compatible = "samsung,exynos5-sysreg", "syscon"; - reg = <0x10050000 0x5000>; - }; diff --git a/Documentation/devicetree/bindings/arm/samsung/sysreg.yaml b/Documentation/devicetree/bindings/arm/samsung/sysreg.yaml new file mode 100644 index 000000000000..3b7811804cb4 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/samsung/sysreg.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/samsung/sysreg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S5P/Exynos SoC series System Registers (SYSREG) + +maintainers: + - Krzysztof Kozlowski <[email protected]> + +# Custom select to avoid matching all nodes with 'syscon' +select: + properties: + compatible: + contains: + enum: + - samsung,exynos4-sysreg + - samsung,exynos5-sysreg + required: + - compatible + +properties: + compatible: + allOf: + - items: + - enum: + - samsung,exynos4-sysreg + - samsung,exynos5-sysreg + - const: syscon + + reg: + maxItems: 1 + +examples: + - | + syscon@10010000 { + compatible = "samsung,exynos4-sysreg", "syscon"; + reg = <0x10010000 0x400>; + }; + + syscon@10050000 { + compatible = "samsung,exynos5-sysreg", "syscon"; + reg = <0x10050000 0x5000>; + }; diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index 4d194f1eb03a..1fcf306bd2d1 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -13,19 +13,38 @@ properties: compatible: oneOf: - items: + - enum: + - st,stm32f429i-disco + - st,stm32429i-eval - const: st,stm32f429 - - items: + - enum: + - st,stm32f469i-disco - const: st,stm32f469 - - items: + - enum: + - st,stm32f746-disco + - st,stm32746g-eval - const: st,stm32f746 - - items: + - enum: + - st,stm32f769-disco + - const: st,stm32f769 + - items: + - enum: + - st,stm32h743i-disco + - st,stm32h743i-eval - const: st,stm32h743 - - items: - enum: - arrow,stm32mp157a-avenger96 # Avenger96 + - st,stm32mp157c-ed1 + - st,stm32mp157a-dk1 + - st,stm32mp157c-dk2 + + - const: st,stm32mp157 + - items: + - const: st,stm32mp157c-ev1 + - const: st,stm32mp157c-ed1 - const: st,stm32mp157 ... diff --git a/Documentation/devicetree/bindings/bus/renesas,bsc.txt b/Documentation/devicetree/bindings/bus/renesas,bsc.txt deleted file mode 100644 index 90e947269437..000000000000 --- a/Documentation/devicetree/bindings/bus/renesas,bsc.txt +++ /dev/null @@ -1,46 +0,0 @@ -Renesas Bus State Controller (BSC) -================================== - -The Renesas Bus State Controller (BSC, sometimes called "LBSC within Bus -Bridge", or "External Bus Interface") can be found in several Renesas ARM SoCs. -It provides an external bus for connecting multiple external devices to the -SoC, driving several chip select lines, for e.g. NOR FLASH, Ethernet and USB. - -While the BSC is a fairly simple memory-mapped bus, it may be part of a PM -domain, and may have a gateable functional clock. -Before a device connected to the BSC can be accessed, the PM domain -containing the BSC must be powered on, and the functional clock -driving the BSC must be enabled. - -The bindings for the BSC extend the bindings for "simple-pm-bus". - - -Required properties - - compatible: Must contain an SoC-specific value, and "renesas,bsc" and - "simple-pm-bus" as fallbacks. - SoC-specific values can be: - "renesas,bsc-r8a73a4" for R-Mobile APE6 (r8a73a4) - "renesas,bsc-sh73a0" for SH-Mobile AG5 (sh73a0) - - #address-cells, #size-cells, ranges: Must describe the mapping between - parent address and child address spaces. - - reg: Must contain the base address and length to access the bus controller. - -Optional properties: - - interrupts: Must contain a reference to the BSC interrupt, if available. - - clocks: Must contain a reference to the functional clock, if available. - - power-domains: Must contain a reference to the PM domain, if available. - - -Example: - - bsc: bus@fec10000 { - compatible = "renesas,bsc-sh73a0", "renesas,bsc", - "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x20000000>; - reg = <0xfec10000 0x400>; - interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&zb_clk>; - power-domains = <&pd_a4s>; - }; diff --git a/Documentation/devicetree/bindings/bus/renesas,bsc.yaml b/Documentation/devicetree/bindings/bus/renesas,bsc.yaml new file mode 100644 index 000000000000..7d10b62a52d5 --- /dev/null +++ b/Documentation/devicetree/bindings/bus/renesas,bsc.yaml @@ -0,0 +1,60 @@ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/renesas,bsc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas Bus State Controller (BSC) + +maintainers: + - Geert Uytterhoeven <[email protected]> + +description: | + The Renesas Bus State Controller (BSC, sometimes called "LBSC within Bus + Bridge", or "External Bus Interface") can be found in several Renesas ARM + SoCs. It provides an external bus for connecting multiple external + devices to the SoC, driving several chip select lines, for e.g. NOR + FLASH, Ethernet and USB. + + While the BSC is a fairly simple memory-mapped bus, it may be part of a + PM domain, and may have a gateable functional clock. Before a device + connected to the BSC can be accessed, the PM domain containing the BSC + must be powered on, and the functional clock driving the BSC must be + enabled. + + The bindings for the BSC extend the bindings for "simple-pm-bus". + +allOf: + - $ref: simple-pm-bus.yaml# + +properties: + compatible: + items: + - enum: + - renesas,bsc-r8a73a4 # R-Mobile APE6 (r8a73a4) + - renesas,bsc-sh73a0 # SH-Mobile AG5 (sh73a0) + - const: renesas,bsc + - {} # simple-pm-bus, but not listed here to avoid false select + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - reg + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + bsc: bus@fec10000 { + compatible = "renesas,bsc-sh73a0", "renesas,bsc", "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x20000000>; + reg = <0xfec10000 0x400>; + interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&zb_clk>; + power-domains = <&pd_a4s>; + }; diff --git a/Documentation/devicetree/bindings/bus/simple-pm-bus.txt b/Documentation/devicetree/bindings/bus/simple-pm-bus.txt deleted file mode 100644 index 6f15037131ed..000000000000 --- a/Documentation/devicetree/bindings/bus/simple-pm-bus.txt +++ /dev/null @@ -1,44 +0,0 @@ -Simple Power-Managed Bus -======================== - -A Simple Power-Managed Bus is a transparent bus that doesn't need a real -driver, as it's typically initialized by the boot loader. - -However, its bus controller is part of a PM domain, or under the control of a -functional clock. Hence, the bus controller's PM domain and/or clock must be -enabled for child devices connected to the bus (either on-SoC or externally) -to function. - -While "simple-pm-bus" follows the "simple-bus" set of properties, as specified -in the Devicetree Specification, it is not an extension of "simple-bus". - - -Required properties: - - compatible: Must contain at least "simple-pm-bus". - Must not contain "simple-bus". - It's recommended to let this be preceded by one or more - vendor-specific compatible values. - - #address-cells, #size-cells, ranges: Must describe the mapping between - parent address and child address spaces. - -Optional platform-specific properties for clock or PM domain control (at least -one of them is required): - - clocks: Must contain a reference to the functional clock(s), - - power-domains: Must contain a reference to the PM domain. -Please refer to the binding documentation for the clock and/or PM domain -providers for more details. - - -Example: - - bsc: bus@fec10000 { - compatible = "renesas,bsc-sh73a0", "renesas,bsc", - "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x20000000>; - reg = <0xfec10000 0x400>; - interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&zb_clk>; - power-domains = <&pd_a4s>; - }; diff --git a/Documentation/devicetree/bindings/bus/simple-pm-bus.yaml b/Documentation/devicetree/bindings/bus/simple-pm-bus.yaml new file mode 100644 index 000000000000..33326ffdb266 --- /dev/null +++ b/Documentation/devicetree/bindings/bus/simple-pm-bus.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/simple-pm-bus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Simple Power-Managed Bus + +maintainers: + - Geert Uytterhoeven <[email protected]> + +description: | + A Simple Power-Managed Bus is a transparent bus that doesn't need a real + driver, as it's typically initialized by the boot loader. + + However, its bus controller is part of a PM domain, or under the control + of a functional clock. Hence, the bus controller's PM domain and/or + clock must be enabled for child devices connected to the bus (either + on-SoC or externally) to function. + + While "simple-pm-bus" follows the "simple-bus" set of properties, as + specified in the Devicetree Specification, it is not an extension of + "simple-bus". + +properties: + $nodename: + pattern: "^bus(@[0-9a-f]+)?$" + + compatible: + contains: + const: simple-pm-bus + description: + Shall contain "simple-pm-bus" in addition to a optional bus-specific + compatible strings defined in individual pm-bus bindings. + + '#address-cells': + enum: [ 1, 2 ] + + '#size-cells': + enum: [ 1, 2 ] + + ranges: true + + clocks: true + # Functional clocks + # Required if power-domains is absent, optional otherwise + + power-domains: + # Required if clocks is absent, optional otherwise + minItems: 1 + +required: + - compatible + - '#address-cells' + - '#size-cells' + - ranges + +anyOf: + - required: + - clocks + - required: + - power-domains + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-msm8996.h> + #include <dt-bindings/interrupt-controller/irq.h> + + bus { + power-domains = <&gcc AGGRE0_NOC_GDSC>; + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + }; diff --git a/Documentation/devicetree/bindings/crypto/samsung-slimsss.txt b/Documentation/devicetree/bindings/crypto/samsung-slimsss.txt deleted file mode 100644 index 7ec9a5a7727a..000000000000 --- a/Documentation/devicetree/bindings/crypto/samsung-slimsss.txt +++ /dev/null @@ -1,19 +0,0 @@ -Samsung SoC SlimSSS (Slim Security SubSystem) module - -The SlimSSS module in Exynos5433 SoC supports the following: --- Feeder (FeedCtrl) --- Advanced Encryption Standard (AES) with ECB,CBC,CTR,XTS and (CBC/XTS)/CTS --- SHA-1/SHA-256 and (SHA-1/SHA-256)/HMAC - -Required properties: - -- compatible : Should contain entry for slimSSS version: - - "samsung,exynos5433-slim-sss" for Exynos5433 SoC. -- reg : Offset and length of the register set for the module -- interrupts : interrupt specifiers of SlimSSS module interrupts (one feed - control interrupt). - -- clocks : list of clock phandle and specifier pairs for all clocks listed in - clock-names property. -- clock-names : list of device clock input names; should contain "pclk" and - "aclk" for slim-sss in Exynos5433. diff --git a/Documentation/devicetree/bindings/crypto/samsung-slimsss.yaml b/Documentation/devicetree/bindings/crypto/samsung-slimsss.yaml new file mode 100644 index 000000000000..04fe5dfa794a --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/samsung-slimsss.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/crypto/samsung-slimsss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos SoC SlimSSS (Slim Security SubSystem) module + +maintainers: + - Krzysztof Kozlowski <[email protected]> + - Kamil Konieczny <[email protected]> + +description: |+ + The SlimSSS module in Exynos5433 SoC supports the following: + -- Feeder (FeedCtrl) + -- Advanced Encryption Standard (AES) with ECB,CBC,CTR,XTS and (CBC/XTS)/CTS + -- SHA-1/SHA-256 and (SHA-1/SHA-256)/HMAC + +properties: + compatible: + items: + - const: samsung,exynos5433-slim-ss + + reg: + maxItems: 1 + + clocks: + minItems: 2 + maxItems: 2 + + clock-names: + items: + - const: pclk + - const: aclk + + interrupts: + description: One feed control interrupt. + maxItems: 1 + +required: + - compatible + - reg + - clock-names + - clocks + - interrupts + +additionalProperties: false diff --git a/Documentation/devicetree/bindings/crypto/samsung-sss.txt b/Documentation/devicetree/bindings/crypto/samsung-sss.txt deleted file mode 100644 index 7a5ca56683cc..000000000000 --- a/Documentation/devicetree/bindings/crypto/samsung-sss.txt +++ /dev/null @@ -1,32 +0,0 @@ -Samsung SoC SSS (Security SubSystem) module - -The SSS module in S5PV210 SoC supports the following: --- Feeder (FeedCtrl) --- Advanced Encryption Standard (AES) --- Data Encryption Standard (DES)/3DES --- Public Key Accelerator (PKA) --- SHA-1/SHA-256/MD5/HMAC (SHA-1/SHA-256/MD5)/PRNG --- PRNG: Pseudo Random Number Generator - -The SSS module in Exynos4 (Exynos4210) and -Exynos5 (Exynos5420 and Exynos5250) SoCs -supports the following also: --- ARCFOUR (ARC4) --- True Random Number Generator (TRNG) --- Secure Key Manager - -Required properties: - -- compatible : Should contain entries for this and backward compatible - SSS versions: - - "samsung,s5pv210-secss" for S5PV210 SoC. - - "samsung,exynos4210-secss" for Exynos4210, Exynos4212, Exynos4412, Exynos5250, - Exynos5260 and Exynos5420 SoCs. -- reg : Offset and length of the register set for the module -- interrupts : interrupt specifiers of SSS module interrupts (one feed - control interrupt). - -- clocks : list of clock phandle and specifier pairs for all clocks listed in - clock-names property. -- clock-names : list of device clock input names; should contain one entry - "secss". diff --git a/Documentation/devicetree/bindings/crypto/samsung-sss.yaml b/Documentation/devicetree/bindings/crypto/samsung-sss.yaml new file mode 100644 index 000000000000..cf1c47a81d7f --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/samsung-sss.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/crypto/samsung-sss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos SoC SSS (Security SubSystem) module + +maintainers: + - Krzysztof Kozlowski <[email protected]> + - Kamil Konieczny <[email protected]> + +description: |+ + The SSS module in S5PV210 SoC supports the following: + -- Feeder (FeedCtrl) + -- Advanced Encryption Standard (AES) + -- Data Encryption Standard (DES)/3DES + -- Public Key Accelerator (PKA) + -- SHA-1/SHA-256/MD5/HMAC (SHA-1/SHA-256/MD5)/PRNG + -- PRNG: Pseudo Random Number Generator + + The SSS module in Exynos4 (Exynos4210) and Exynos5 (Exynos5420 and Exynos5250) + SoCs supports the following also: + -- ARCFOUR (ARC4) + -- True Random Number Generator (TRNG) + -- Secure Key Manager + +properties: + compatible: + items: + - enum: + - samsung,s5pv210-secss # for S5PV210 + - samsung,exynos4210-secss # for Exynos4210, Exynos4212, + # Exynos4412, Exynos5250, + # Exynos5260 and Exynos5420 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: secss + + interrupts: + description: One feed control interrupt. + maxItems: 1 + +required: + - compatible + - reg + - clock-names + - clocks + - interrupts + +additionalProperties: false diff --git a/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml b/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml index fb747682006d..0da42ab8fd3a 100644 --- a/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml +++ b/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml @@ -79,8 +79,6 @@ properties: hdmi-supply: description: phandle to an external 5V regulator to power the HDMI logic - allOf: - - $ref: /schemas/types.yaml#/definitions/phandle port@0: type: object diff --git a/Documentation/devicetree/bindings/display/cirrus,clps711x-fb.txt b/Documentation/devicetree/bindings/display/cirrus,clps711x-fb.txt index b0e506610400..0ab5f0663611 100644 --- a/Documentation/devicetree/bindings/display/cirrus,clps711x-fb.txt +++ b/Documentation/devicetree/bindings/display/cirrus,clps711x-fb.txt @@ -27,11 +27,11 @@ Example: display: display { model = "320x240x4"; - native-mode = <&timing0>; bits-per-pixel = <4>; ac-prescale = <17>; display-timings { + native-mode = <&timing0>; timing0: 320x240 { hactive = <320>; hback-porch = <0>; diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx-fb.txt b/Documentation/devicetree/bindings/display/imx/fsl,imx-fb.txt index e5a8b363d829..f4df9e83bcd2 100644 --- a/Documentation/devicetree/bindings/display/imx/fsl,imx-fb.txt +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx-fb.txt @@ -38,10 +38,10 @@ Example: display0: display0 { model = "Primeview-PD050VL1"; - native-mode = <&timing_disp0>; bits-per-pixel = <16>; fsl,pcr = <0xf0c88080>; /* non-standard but required */ display-timings { + native-mode = <&timing_disp0>; timing_disp0: 640x480 { hactive = <640>; vactive = <480>; diff --git a/Documentation/devicetree/bindings/display/panel/sharp,ld-d5116z01b.txt b/Documentation/devicetree/bindings/display/panel/sharp,ld-d5116z01b.txt deleted file mode 100644 index fd9cf39bde77..000000000000 --- a/Documentation/devicetree/bindings/display/panel/sharp,ld-d5116z01b.txt +++ /dev/null @@ -1,26 +0,0 @@ -Sharp LD-D5116Z01B 12.3" WUXGA+ eDP panel - -Required properties: -- compatible: should be "sharp,ld-d5116z01b" -- power-supply: regulator to provide the VCC supply voltage (3.3 volts) - -This binding is compatible with the simple-panel binding. - -The device node can contain one 'port' child node with one child -'endpoint' node, according to the bindings defined in [1]. This -node should describe panel's video bus. - -[1]: Documentation/devicetree/bindings/media/video-interfaces.txt - -Example: - - panel: panel { - compatible = "sharp,ld-d5116z01b"; - power-supply = <&vlcd_3v3>; - - port { - panel_ep: endpoint { - remote-endpoint = <&bridge_out_ep>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/panel/sharp,ld-d5116z01b.yaml b/Documentation/devicetree/bindings/display/panel/sharp,ld-d5116z01b.yaml new file mode 100644 index 000000000000..fbb647eb33c9 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/sharp,ld-d5116z01b.yaml @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/sharp,ld-d5116z01b.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sharp LD-D5116Z01B 12.3" WUXGA+ eDP panel + +maintainers: + - Jeffrey Hugo <[email protected]> + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: sharp,ld-d5116z01b + + power-supply: true + backlight: true + port: true + no-hpd: true + +additionalProperties: false + +required: + - compatible + - power-supply + +... diff --git a/Documentation/devicetree/bindings/display/st,stm32-dsi.yaml b/Documentation/devicetree/bindings/display/st,stm32-dsi.yaml new file mode 100644 index 000000000000..de6c99198cbe --- /dev/null +++ b/Documentation/devicetree/bindings/display/st,stm32-dsi.yaml @@ -0,0 +1,150 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/st,stm32-dsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32 DSI host controller + +maintainers: + - Philippe Cornu <[email protected]> + - Yannick Fertre <[email protected]> + +description: + The STMicroelectronics STM32 DSI controller uses the Synopsys DesignWare MIPI-DSI host controller. + +properties: + compatible: + const: st,stm32-dsi + + reg: + maxItems: 1 + + clocks: + items: + - description: Module Clock + - description: DSI bus clock + - description: Pixel clock + minItems: 2 + maxItems: 3 + + clock-names: + items: + - const: pclk + - const: ref + - const: px_clk + minItems: 2 + maxItems: 3 + + resets: + maxItems: 1 + + reset-names: + items: + - const: apb + + phy-dsi-supply: + description: + Phandle of the regulator that provides the supply voltage. + + ports: + type: object + description: + A node containing DSI input & output port nodes with endpoint + definitions as documented in + Documentation/devicetree/bindings/media/video-interfaces.txt + Documentation/devicetree/bindings/graph.txt + properties: + port@0: + type: object + description: + DSI input port node, connected to the ltdc rgb output port. + + port@1: + type: object + description: + DSI output port node, connected to a panel or a bridge input port" + +patternProperties: + "^(panel|panel-dsi)@[0-9]$": + type: object + description: + A node containing the panel or bridge description as documented in + Documentation/devicetree/bindings/display/mipi-dsi-bus.txt + properties: + port: + type: object + description: + Panel or bridge port node, connected to the DSI output port (port@1) + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +required: + - "#address-cells" + - "#size-cells" + - compatible + - reg + - clocks + - clock-names + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/stm32mp1-clks.h> + #include <dt-bindings/reset/stm32mp1-resets.h> + #include <dt-bindings/gpio/gpio.h> + dsi: dsi@5a000000 { + compatible = "st,stm32-dsi"; + reg = <0x5a000000 0x800>; + clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>; + clock-names = "pclk", "ref", "px_clk"; + resets = <&rcc DSI_R>; + reset-names = "apb"; + phy-dsi-supply = <®18>; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <<dc_ep1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + + panel-dsi@0 { + compatible = "orisetech,otm8009a"; + reg = <0>; + reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>; + power-supply = <&v3v3>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; + }; + +... + + diff --git a/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt b/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt deleted file mode 100644 index 60c54da4e526..000000000000 --- a/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt +++ /dev/null @@ -1,144 +0,0 @@ -* STMicroelectronics STM32 lcd-tft display controller - -- ltdc: lcd-tft display controller host - Required properties: - - compatible: "st,stm32-ltdc" - - reg: Physical base address of the IP registers and length of memory mapped region. - - clocks: A list of phandle + clock-specifier pairs, one for each - entry in 'clock-names'. - - clock-names: A list of clock names. For ltdc it should contain: - - "lcd" for the clock feeding the output pixel clock & IP clock. - - resets: reset to be used by the device (defined by use of RCC macro). - Required nodes: - - Video port for DPI RGB output: ltdc has one video port with up to 2 - endpoints: - - for external dpi rgb panel or bridge, using gpios. - - for internal dpi input of the MIPI DSI host controller. - Note: These 2 endpoints cannot be activated simultaneously. - -* STMicroelectronics STM32 DSI controller specific extensions to Synopsys - DesignWare MIPI DSI host controller - -The STMicroelectronics STM32 DSI controller uses the Synopsys DesignWare MIPI -DSI host controller. For all mandatory properties & nodes, please refer -to the related documentation in [5]. - -Mandatory properties specific to STM32 DSI: -- #address-cells: Should be <1>. -- #size-cells: Should be <0>. -- compatible: "st,stm32-dsi". -- clock-names: - - phy pll reference clock string name, must be "ref". -- resets: see [5]. -- reset-names: see [5]. - -Mandatory nodes specific to STM32 DSI: -- ports: A node containing DSI input & output port nodes with endpoint - definitions as documented in [3] & [4]. - - port@0: DSI input port node, connected to the ltdc rgb output port. - - port@1: DSI output port node, connected to a panel or a bridge input port. -- panel or bridge node: A node containing the panel or bridge description as - documented in [6]. - - port: panel or bridge port node, connected to the DSI output port (port@1). -Optional properties: -- phy-dsi-supply: phandle of the regulator that provides the supply voltage. - -Note: You can find more documentation in the following references -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] Documentation/devicetree/bindings/reset/reset.txt -[3] Documentation/devicetree/bindings/media/video-interfaces.txt -[4] Documentation/devicetree/bindings/graph.txt -[5] Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt -[6] Documentation/devicetree/bindings/display/mipi-dsi-bus.txt - -Example 1: RGB panel -/ { - ... - soc { - ... - ltdc: display-controller@40016800 { - compatible = "st,stm32-ltdc"; - reg = <0x40016800 0x200>; - interrupts = <88>, <89>; - resets = <&rcc STM32F4_APB2_RESET(LTDC)>; - clocks = <&rcc 1 CLK_LCD>; - clock-names = "lcd"; - - port { - ltdc_out_rgb: endpoint { - }; - }; - }; - }; -}; - -Example 2: DSI panel - -/ { - ... - soc { - ... - ltdc: display-controller@40016800 { - compatible = "st,stm32-ltdc"; - reg = <0x40016800 0x200>; - interrupts = <88>, <89>; - resets = <&rcc STM32F4_APB2_RESET(LTDC)>; - clocks = <&rcc 1 CLK_LCD>; - clock-names = "lcd"; - - port { - ltdc_out_dsi: endpoint { - remote-endpoint = <&dsi_in>; - }; - }; - }; - - - dsi: dsi@40016c00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-dsi"; - reg = <0x40016c00 0x800>; - clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>; - clock-names = "pclk", "ref"; - resets = <&rcc STM32F4_APB2_RESET(DSI)>; - reset-names = "apb"; - phy-dsi-supply = <®18>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dsi_in: endpoint { - remote-endpoint = <<dc_out_dsi>; - }; - }; - - port@1 { - reg = <1>; - dsi_out: endpoint { - remote-endpoint = <&dsi_in_panel>; - }; - }; - - }; - - panel-dsi@0 { - reg = <0>; /* dsi virtual channel (0..3) */ - compatible = ...; - enable-gpios = ...; - - port { - dsi_in_panel: endpoint { - remote-endpoint = <&dsi_out>; - }; - }; - - }; - - }; - - }; -}; diff --git a/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml b/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml new file mode 100644 index 000000000000..a40197ab281e --- /dev/null +++ b/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/st,stm32-ltdc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32 lcd-tft display controller + +maintainers: + - Philippe Cornu <[email protected]> + - Yannick Fertre <[email protected]> + +properties: + compatible: + const: st,stm32-ltdc + + reg: + maxItems: 1 + + interrupts: + items: + - description: events interrupt line. + - description: errors interrupt line. + minItems: 1 + maxItems: 2 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: lcd + + resets: + maxItems: 1 + + port: + type: object + description: + "Video port for DPI RGB output. + ltdc has one video port with up to 2 endpoints: + - for external dpi rgb panel or bridge, using gpios. + - for internal dpi input of the MIPI DSI host controller. + Note: These 2 endpoints cannot be activated simultaneously. + Please refer to the bindings defined in + Documentation/devicetree/bindings/media/video-interfaces.txt." + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - port + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/stm32mp1-clks.h> + #include <dt-bindings/reset/stm32mp1-resets.h> + ltdc: display-controller@40016800 { + compatible = "st,stm32-ltdc"; + reg = <0x5a001000 0x400>; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LTDC_PX>; + clock-names = "lcd"; + resets = <&rcc LTDC_R>; + + port { + ltdc_out_dsi: endpoint { + remote-endpoint = <&dsi_in>; + }; + }; + }; + +... + diff --git a/Documentation/devicetree/bindings/eeprom/at24.txt b/Documentation/devicetree/bindings/eeprom/at24.txt index 22aead844d0f..c94acbb8cb0c 100644 --- a/Documentation/devicetree/bindings/eeprom/at24.txt +++ b/Documentation/devicetree/bindings/eeprom/at24.txt @@ -1,89 +1 @@ -EEPROMs (I2C) - -Required properties: - - - compatible: Must be a "<manufacturer>,<model>" pair. The following <model> - values are supported (assuming "atmel" as manufacturer): - - "atmel,24c00", - "atmel,24c01", - "atmel,24cs01", - "atmel,24c02", - "atmel,24cs02", - "atmel,24mac402", - "atmel,24mac602", - "atmel,spd", - "atmel,24c04", - "atmel,24cs04", - "atmel,24c08", - "atmel,24cs08", - "atmel,24c16", - "atmel,24cs16", - "atmel,24c32", - "atmel,24cs32", - "atmel,24c64", - "atmel,24cs64", - "atmel,24c128", - "atmel,24c256", - "atmel,24c512", - "atmel,24c1024", - "atmel,24c2048", - - If <manufacturer> is not "atmel", then a fallback must be used - with the same <model> and "atmel" as manufacturer. - - Example: - compatible = "microchip,24c128", "atmel,24c128"; - - Supported manufacturers are: - - "catalyst", - "microchip", - "nxp", - "ramtron", - "renesas", - "rohm", - "st", - - Some vendors use different model names for chips which are just - variants of the above. Known such exceptions are listed below: - - "nxp,se97b" - the fallback is "atmel,24c02", - "renesas,r1ex24002" - the fallback is "atmel,24c02" - "renesas,r1ex24016" - the fallback is "atmel,24c16" - "renesas,r1ex24128" - the fallback is "atmel,24c128" - "rohm,br24t01" - the fallback is "atmel,24c01" - - - reg: The I2C address of the EEPROM. - -Optional properties: - - - pagesize: The length of the pagesize for writing. Please consult the - manual of your device, that value varies a lot. A wrong value - may result in data loss! If not specified, a safety value of - '1' is used which will be very slow. - - - read-only: This parameterless property disables writes to the eeprom. - - - size: Total eeprom size in bytes. - - - no-read-rollover: This parameterless property indicates that the - multi-address eeprom does not automatically roll over - reads to the next slave address. Please consult the - manual of your device. - - - wp-gpios: GPIO to which the write-protect pin of the chip is connected. - - - address-width: number of address bits (one of 8, 16). - - - num-addresses: total number of i2c slave addresses this device takes - -Example: - -eeprom@52 { - compatible = "atmel,24c32"; - reg = <0x52>; - pagesize = <32>; - wp-gpios = <&gpio1 3 0>; - num-addresses = <8>; -}; +This file has been moved to at24.yaml. diff --git a/Documentation/devicetree/bindings/eeprom/at24.yaml b/Documentation/devicetree/bindings/eeprom/at24.yaml new file mode 100644 index 000000000000..e8778560d966 --- /dev/null +++ b/Documentation/devicetree/bindings/eeprom/at24.yaml @@ -0,0 +1,188 @@ +# SPDX-License-Identifier: GPL-2.0-only +# Copyright 2019 BayLibre SAS +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/eeprom/at24.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: I2C EEPROMs compatible with Atmel's AT24 + +maintainers: + - Bartosz Golaszewski <[email protected]> + +select: + properties: + compatible: + contains: + pattern: "^atmel,(24(c|cs|mac)[0-9]+|spd)$" + required: + - compatible + +properties: + $nodename: + pattern: "^eeprom@[0-9a-f]{1,2}$" + + # There are multiple known vendors who manufacture EEPROM chips compatible + # with Atmel's AT24. The compatible string requires either a single item + # if the memory comes from Atmel (in which case the vendor part must be + # 'atmel') or two items with the same 'model' part where the vendor part of + # the first one is the actual manufacturer and the second item is the + # corresponding 'atmel,<model>' from Atmel. + compatible: + oneOf: + - allOf: + - minItems: 1 + maxItems: 2 + items: + - pattern: "^(atmel|catalyst|microchip|nxp|ramtron|renesas|rohm|st),(24(c|cs|mac)[0-9]+|spd)$" + - pattern: "^atmel,(24(c|cs|mac)[0-9]+|spd)$" + - oneOf: + - items: + pattern: c00$ + - items: + pattern: c01$ + - items: + pattern: cs01$ + - items: + pattern: c02$ + - items: + pattern: cs02$ + - items: + pattern: mac402$ + - items: + pattern: mac602$ + - items: + pattern: c04$ + - items: + pattern: cs04$ + - items: + pattern: c08$ + - items: + pattern: cs08$ + - items: + pattern: c16$ + - items: + pattern: cs16$ + - items: + pattern: c32$ + - items: + pattern: cs32$ + - items: + pattern: c64$ + - items: + pattern: cs64$ + - items: + pattern: c128$ + - items: + pattern: cs128$ + - items: + pattern: c256$ + - items: + pattern: cs256$ + - items: + pattern: c512$ + - items: + pattern: cs512$ + - items: + pattern: c1024$ + - items: + pattern: cs1024$ + - items: + pattern: c2048$ + - items: + pattern: cs2048$ + - items: + pattern: spd$ + # These are special cases that don't conform to the above pattern. + # Each requires a standard at24 model as fallback. + - items: + - const: rohm,br24t01 + - const: atmel,24c01 + - items: + - const: nxp,se97b + - const: atmel,24c02 + - items: + - const: renesas,r1ex24002 + - const: atmel,24c02 + - items: + - const: renesas,r1ex24016 + - const: atmel,24c16 + - items: + - const: giantec,gt24c32a + - const: atmel,24c32 + - items: + - const: renesas,r1ex24128 + - const: atmel,24c128 + + reg: + maxItems: 1 + + pagesize: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + description: + The length of the pagesize for writing. Please consult the + manual of your device, that value varies a lot. A wrong value + may result in data loss! If not specified, a safety value of + '1' is used which will be very slow. + enum: [ 1, 8, 16, 32, 64, 128, 258 ] + default: 1 + + read-only: + $ref: /schemas/types.yaml#definitions/flag + description: + Disables writes to the eeprom. + + size: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Total eeprom size in bytes. + + no-read-rollover: + $ref: /schemas/types.yaml#definitions/flag + description: + Indicates that the multi-address eeprom does not automatically roll + over reads to the next slave address. Please consult the manual of + your device. + + wp-gpios: + description: + GPIO to which the write-protect pin of the chip is connected. + maxItems: 1 + + address-width: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + description: + Number of address bits. + default: 8 + enum: [ 8, 16 ] + + num-addresses: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + description: + Total number of i2c slave addresses this device takes. + default: 1 + minimum: 1 + maximum: 8 + +required: + - compatible + - reg + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + eeprom@52 { + compatible = "microchip,24c32", "atmel,24c32"; + reg = <0x52>; + pagesize = <32>; + wp-gpios = <&gpio1 3 0>; + num-addresses = <8>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/example-schema.yaml b/Documentation/devicetree/bindings/example-schema.yaml index c43819c2783a..f27ad5c90353 100644 --- a/Documentation/devicetree/bindings/example-schema.yaml +++ b/Documentation/devicetree/bindings/example-schema.yaml @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) # Copyright 2018 Linaro Ltd. %YAML 1.2 --- @@ -71,7 +71,7 @@ properties: # minItems/maxItems equal to 2 is implied reg-names: - # The core schema enforces this is a string array + # The core schema enforces this (*-names) is a string array items: - const: core - const: aux @@ -79,7 +79,8 @@ properties: clocks: # Cases that have only a single entry just need to express that with maxItems maxItems: 1 - description: bus clock + description: bus clock. A description is only needed for a single item if + there's something unique to add. clock-names: items: @@ -127,6 +128,14 @@ properties: maxItems: 1 description: A connection of the 'foo' gpio line. + # *-supply is always a single phandle, so nothing more to define. + foo-supply: true + + # Vendor specific properties + # + # Vendor specific properties have slightly different schema requirements than + # common properties. They must have at least a type definition and + # 'description'. vendor,int-property: description: Vendor specific properties must have a description # 'allOf' is the json-schema way of subclassing a schema. Here the base @@ -137,9 +146,9 @@ properties: - enum: [2, 4, 6, 8, 10] vendor,bool-property: - description: Vendor specific properties must have a description - # boolean properties is one case where the json-schema 'type' keyword - # can be used directly + description: Vendor specific properties must have a description. Boolean + properties are one case where the json-schema 'type' keyword can be used + directly. type: boolean vendor,string-array-property: @@ -151,14 +160,72 @@ properties: - enum: [ foo, bar ] - enum: [ baz, boo ] + vendor,property-in-standard-units-microvolts: + description: Vendor specific properties having a standard unit suffix + don't need a type. + enum: [ 100, 200, 300 ] + + child-node: + description: Child nodes are just another property from a json-schema + perspective. + type: object # DT nodes are json objects + properties: + vendor,a-child-node-property: + description: Child node properties have all the same schema + requirements. + type: boolean + + required: + - vendor,a-child-node-property + +# Describe the relationship between different properties +dependencies: + # 'vendor,bool-property' is only allowed when 'vendor,string-array-property' + # is present + vendor,bool-property: [ vendor,string-array-property ] + # Expressing 2 properties in both orders means all of the set of properties + # must be present or none of them. + vendor,string-array-property: [ vendor,bool-property ] + required: - compatible - reg - interrupts - interrupt-controller +# if/then schema can be used to handle conditions on a property affecting +# another property. A typical case is a specific 'compatible' value changes the +# constraints on other properties. +# +# For multiple 'if' schema, group them under an 'allOf'. +# +# If the conditionals become too unweldy, then it may be better to just split +# the binding into separate schema documents. +if: + properties: + compatible: + contains: + const: vendor,soc2-ip +then: + required: + - foo-supply + +# Ideally, the schema should have this line otherwise any other properties +# present are allowed. There's a few common properties such as 'status' and +# 'pinctrl-*' which are added automatically by the tooling. +# +# This can't be used in cases where another schema is referenced +# (i.e. allOf: [{$ref: ...}]). +additionalProperties: false + examples: - # Examples are now compiled with dtc + # Examples are now compiled with dtc and validated against the schemas + # + # Examples have a default #address-cells and #size-cells value of 1. This can + # be overridden or an appropriate parent bus node should be shown (such as on + # i2c buses). + # + # Any includes used have to be explicitly included. - | node@1000 { compatible = "vendor,soc4-ip", "vendor,soc1-ip"; diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml index 5f1fd6d7ee0f..e50a0cc78fff 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml @@ -37,8 +37,7 @@ properties: clocks: maxItems: 1 - mali-supply: - maxItems: 1 + mali-supply: true operating-points-v2: true diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml index 47bc1ac36426..5c576e5019c6 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml @@ -69,8 +69,7 @@ properties: - const: core - const: bus - mali-supply: - maxItems: 1 + mali-supply: true resets: minItems: 1 diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml index c5d93c5839d3..afde81be3c29 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml @@ -97,8 +97,7 @@ properties: memory-region: true - mali-supply: - maxItems: 1 + mali-supply: true power-domains: maxItems: 1 diff --git a/Documentation/devicetree/bindings/gpu/samsung-g2d.txt b/Documentation/devicetree/bindings/gpu/samsung-g2d.txt deleted file mode 100644 index 1e7959332dbc..000000000000 --- a/Documentation/devicetree/bindings/gpu/samsung-g2d.txt +++ /dev/null @@ -1,27 +0,0 @@ -* Samsung 2D Graphics Accelerator - -Required properties: - - compatible : value should be one among the following: - (a) "samsung,s5pv210-g2d" for G2D IP present in S5PV210 & Exynos4210 SoC - (b) "samsung,exynos4212-g2d" for G2D IP present in Exynos4x12 SoCs - (c) "samsung,exynos5250-g2d" for G2D IP present in Exynos5250 SoC - - - reg : Physical base address of the IP registers and length of memory - mapped region. - - - interrupts : G2D interrupt number to the CPU. - - clocks : from common clock binding: handle to G2D clocks. - - clock-names : names of clocks listed in clocks property, in the same - order, depending on SoC type: - - for S5PV210 and Exynos4 based SoCs: "fimg2d" and - "sclk_fimg2d" - - for Exynos5250 SoC: "fimg2d". - -Example: - g2d@12800000 { - compatible = "samsung,s5pv210-g2d"; - reg = <0x12800000 0x1000>; - interrupts = <0 89 0>; - clocks = <&clock 177>, <&clock 277>; - clock-names = "sclk_fimg2d", "fimg2d"; - }; diff --git a/Documentation/devicetree/bindings/gpu/samsung-g2d.yaml b/Documentation/devicetree/bindings/gpu/samsung-g2d.yaml new file mode 100644 index 000000000000..e7daae862578 --- /dev/null +++ b/Documentation/devicetree/bindings/gpu/samsung-g2d.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpu/samsung-g2d.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung SoC 2D Graphics Accelerator + +maintainers: + - Inki Dae <[email protected]> + +properties: + compatible: + enum: + - samsung,s5pv210-g2d # in S5PV210 & Exynos4210 SoC + - samsung,exynos4212-g2d # in Exynos4x12 SoCs + - samsung,exynos5250-g2d + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: {} + clock-names: {} + iommus: {} + power-domains: {} + +if: + properties: + compatible: + contains: + const: samsung,exynos5250-g2d + +then: + properties: + clocks: + items: + - description: fimg2d clock + clock-names: + items: + - const: fimg2d + +else: + properties: + clocks: + items: + - description: sclk_fimg2d clock + - description: fimg2d clock + clock-names: + items: + - const: sclk_fimg2d + - const: fimg2d + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + g2d@12800000 { + compatible = "samsung,s5pv210-g2d"; + reg = <0x12800000 0x1000>; + interrupts = <0 89 0>; + clocks = <&clock 177>, <&clock 277>; + clock-names = "sclk_fimg2d", "fimg2d"; + }; + +... diff --git a/Documentation/devicetree/bindings/gpu/samsung-rotator.txt b/Documentation/devicetree/bindings/gpu/samsung-rotator.txt deleted file mode 100644 index 3aca2578da0b..000000000000 --- a/Documentation/devicetree/bindings/gpu/samsung-rotator.txt +++ /dev/null @@ -1,28 +0,0 @@ -* Samsung Image Rotator - -Required properties: - - compatible : value should be one of the following: - * "samsung,s5pv210-rotator" for Rotator IP in S5PV210 - * "samsung,exynos4210-rotator" for Rotator IP in Exynos4210 - * "samsung,exynos4212-rotator" for Rotator IP in Exynos4212/4412 - * "samsung,exynos5250-rotator" for Rotator IP in Exynos5250 - - - reg : Physical base address of the IP registers and length of memory - mapped region. - - - interrupts : Interrupt specifier for rotator interrupt, according to format - specific to interrupt parent. - - - clocks : Clock specifier for rotator clock, according to generic clock - bindings. (See Documentation/devicetree/bindings/clock/exynos*.txt) - - - clock-names : Names of clocks. For exynos rotator, it should be "rotator". - -Example: - rotator@12810000 { - compatible = "samsung,exynos4210-rotator"; - reg = <0x12810000 0x1000>; - interrupts = <0 83 0>; - clocks = <&clock 278>; - clock-names = "rotator"; - }; diff --git a/Documentation/devicetree/bindings/gpu/samsung-rotator.yaml b/Documentation/devicetree/bindings/gpu/samsung-rotator.yaml new file mode 100644 index 000000000000..f4dfa6fc724c --- /dev/null +++ b/Documentation/devicetree/bindings/gpu/samsung-rotator.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpu/samsung-rotator.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung SoC Image Rotator + +maintainers: + - Inki Dae <[email protected]> + +properties: + compatible: + enum: + - "samsung,s5pv210-rotator" + - "samsung,exynos4210-rotator" + - "samsung,exynos4212-rotator" + - "samsung,exynos5250-rotator" + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: rotator + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +examples: + - | + rotator@12810000 { + compatible = "samsung,exynos4210-rotator"; + reg = <0x12810000 0x1000>; + interrupts = <0 83 0>; + clocks = <&clock 278>; + clock-names = "rotator"; + }; + diff --git a/Documentation/devicetree/bindings/gpu/samsung-scaler.txt b/Documentation/devicetree/bindings/gpu/samsung-scaler.txt deleted file mode 100644 index 9c3d98105dfd..000000000000 --- a/Documentation/devicetree/bindings/gpu/samsung-scaler.txt +++ /dev/null @@ -1,27 +0,0 @@ -* Samsung Exynos Image Scaler - -Required properties: - - compatible : value should be one of the following: - (a) "samsung,exynos5420-scaler" for Scaler IP in Exynos5420 - (b) "samsung,exynos5433-scaler" for Scaler IP in Exynos5433 - - - reg : Physical base address of the IP registers and length of memory - mapped region. - - - interrupts : Interrupt specifier for scaler interrupt, according to format - specific to interrupt parent. - - - clocks : Clock specifier for scaler clock, according to generic clock - bindings. (See Documentation/devicetree/bindings/clock/exynos*.txt) - - - clock-names : Names of clocks. For exynos scaler, it should be "mscl" - on 5420 and "pclk", "aclk" and "aclk_xiu" on 5433. - -Example: - scaler@12800000 { - compatible = "samsung,exynos5420-scaler"; - reg = <0x12800000 0x1294>; - interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clock CLK_MSCL0>; - clock-names = "mscl"; - }; diff --git a/Documentation/devicetree/bindings/gpu/samsung-scaler.yaml b/Documentation/devicetree/bindings/gpu/samsung-scaler.yaml new file mode 100644 index 000000000000..5317ac64426a --- /dev/null +++ b/Documentation/devicetree/bindings/gpu/samsung-scaler.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpu/samsung-scaler.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos SoC Image Scaler + +maintainers: + - Inki Dae <[email protected]> + +properties: + compatible: + enum: + - samsung,exynos5420-scaler + - samsung,exynos5433-scaler + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: {} + clock-names: {} + iommus: {} + power-domains: {} + +if: + properties: + compatible: + contains: + const: samsung,exynos5420-scaler + +then: + properties: + clocks: + items: + - description: mscl clock + + clock-names: + items: + - const: mscl + +else: + properties: + clocks: + items: + - description: pclk clock + - description: aclk clock + - description: aclk_xiu clock + + clock-names: + items: + - const: pclk + - const: aclk + - const: aclk_xiu + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/exynos5420.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + scaler@12800000 { + compatible = "samsung,exynos5420-scaler"; + reg = <0x12800000 0x1294>; + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clock CLK_MSCL0>; + clock-names = "mscl"; + }; + +... diff --git a/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.txt b/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.txt deleted file mode 100644 index adf4f000ea3d..000000000000 --- a/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.txt +++ /dev/null @@ -1,23 +0,0 @@ -STM32 Hardware Spinlock Device Binding -------------------------------------- - -Required properties : -- compatible : should be "st,stm32-hwspinlock". -- reg : the register address of hwspinlock. -- #hwlock-cells : hwlock users only use the hwlock id to represent a specific - hwlock, so the number of cells should be <1> here. -- clock-names : Must contain "hsem". -- clocks : Must contain a phandle entry for the clock in clock-names, see the - common clock bindings. - -Please look at the generic hwlock binding for usage information for consumers, -"Documentation/devicetree/bindings/hwlock/hwlock.txt" - -Example of hwlock provider: - hwspinlock@4c000000 { - compatible = "st,stm32-hwspinlock"; - #hwlock-cells = <1>; - reg = <0x4c000000 0x400>; - clocks = <&rcc HSEM>; - clock-names = "hsem"; - }; diff --git a/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.yaml b/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.yaml new file mode 100644 index 000000000000..47cf9c8d97e9 --- /dev/null +++ b/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwlock/st,stm32-hwspinlock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32 Hardware Spinlock bindings + +maintainers: + - Benjamin Gaignard <[email protected]> + - Fabien Dessenne <[email protected]> + +properties: + "#hwlock-cells": + const: 1 + + compatible: + const: st,stm32-hwspinlock + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: hsem + +required: + - "#hwlock-cells" + - compatible + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/stm32mp1-clks.h> + hwspinlock@4c000000 { + compatible = "st,stm32-hwspinlock"; + #hwlock-cells = <1>; + reg = <0x4c000000 0x400>; + clocks = <&rcc HSEM>; + clock-names = "hsem"; + }; + +... diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7124.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7124.yaml index 9692b7f719f5..e932d5aed02f 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7124.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7124.yaml @@ -45,15 +45,12 @@ properties: refin1-supply: description: refin1 supply can be used as reference for conversion. - maxItems: 1 refin2-supply: description: refin2 supply can be used as reference for conversion. - maxItems: 1 avdd-supply: description: avdd supply can be used as reference for conversion. - maxItems: 1 required: - compatible diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml index cc544fdc38be..6eb33207a167 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml @@ -31,10 +31,7 @@ properties: spi-cpha: true - avcc-supply: - description: - Phandle to the Avcc power supply - maxItems: 1 + avcc-supply: true interrupts: maxItems: 1 diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7780.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7780.yaml index d1109416963c..9acde6d2e2d9 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7780.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7780.yaml @@ -39,7 +39,6 @@ properties: avdd-supply: description: The regulator supply for the ADC reference voltage. - maxItems: 1 powerdown-gpios: description: diff --git a/Documentation/devicetree/bindings/iio/adc/avia-hx711.yaml b/Documentation/devicetree/bindings/iio/adc/avia-hx711.yaml index d76ece97c76c..91ab9c842273 100644 --- a/Documentation/devicetree/bindings/iio/adc/avia-hx711.yaml +++ b/Documentation/devicetree/bindings/iio/adc/avia-hx711.yaml @@ -41,7 +41,6 @@ properties: avdd-supply: description: Definition of the regulator used as analog supply - maxItems: 1 clock-frequency: minimum: 20000 diff --git a/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.txt b/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.txt deleted file mode 100644 index e1fe02f3e3e9..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.txt +++ /dev/null @@ -1,107 +0,0 @@ -Samsung Exynos Analog to Digital Converter bindings - -The devicetree bindings are for the new ADC driver written for -Exynos4 and upward SoCs from Samsung. - -New driver handles the following -1. Supports ADC IF found on EXYNOS4412/EXYNOS5250 - and future SoCs from Samsung -2. Add ADC driver under iio/adc framework -3. Also adds the Documentation for device tree bindings - -Required properties: -- compatible: Must be "samsung,exynos-adc-v1" - for Exynos5250 controllers. - Must be "samsung,exynos-adc-v2" for - future controllers. - Must be "samsung,exynos3250-adc" for - controllers compatible with ADC of Exynos3250. - Must be "samsung,exynos4212-adc" for - controllers compatible with ADC of Exynos4212 and Exynos4412. - Must be "samsung,exynos7-adc" for - the ADC in Exynos7 and compatibles - Must be "samsung,s3c2410-adc" for - the ADC in s3c2410 and compatibles - Must be "samsung,s3c2416-adc" for - the ADC in s3c2416 and compatibles - Must be "samsung,s3c2440-adc" for - the ADC in s3c2440 and compatibles - Must be "samsung,s3c2443-adc" for - the ADC in s3c2443 and compatibles - Must be "samsung,s3c6410-adc" for - the ADC in s3c6410 and compatibles - Must be "samsung,s5pv210-adc" for - the ADC in s5pv210 and compatibles -- reg: List of ADC register address range - - The base address and range of ADC register - - The base address and range of ADC_PHY register (every - SoC except for s3c24xx/s3c64xx ADC) -- interrupts: Contains the interrupt information for the timer. The - format is being dependent on which interrupt controller - the Samsung device uses. -- #io-channel-cells = <1>; As ADC has multiple outputs -- clocks From common clock bindings: handles to clocks specified - in "clock-names" property, in the same order. -- clock-names From common clock bindings: list of clock input names - used by ADC block: - - "adc" : ADC bus clock - - "sclk" : ADC special clock (only for Exynos3250 and - compatible ADC block) -- vdd-supply VDD input supply. - -- samsung,syscon-phandle Contains the PMU system controller node - (To access the ADC_PHY register on Exynos5250/5420/5800/3250) -Optional properties: -- has-touchscreen: If present, indicates that a touchscreen is - connected an usable. - -Note: child nodes can be added for auto probing from device tree. - -Example: adding device info in dtsi file - -adc: adc@12d10000 { - compatible = "samsung,exynos-adc-v1"; - reg = <0x12D10000 0x100>; - interrupts = <0 106 0>; - #io-channel-cells = <1>; - io-channel-ranges; - - clocks = <&clock 303>; - clock-names = "adc"; - - vdd-supply = <&buck5_reg>; - samsung,syscon-phandle = <&pmu_system_controller>; -}; - -Example: adding device info in dtsi file for Exynos3250 with additional sclk - -adc: adc@126c0000 { - compatible = "samsung,exynos3250-adc", "samsung,exynos-adc-v2; - reg = <0x126C0000 0x100>; - interrupts = <0 137 0>; - #io-channel-cells = <1>; - io-channel-ranges; - - clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>; - clock-names = "adc", "sclk"; - - vdd-supply = <&buck5_reg>; - samsung,syscon-phandle = <&pmu_system_controller>; -}; - -Example: Adding child nodes in dts file - -adc@12d10000 { - - /* NTC thermistor is a hwmon device */ - ncp15wb473@0 { - compatible = "murata,ncp15wb473"; - pullup-uv = <1800000>; - pullup-ohm = <47000>; - pulldown-ohm = <0>; - io-channels = <&adc 4>; - }; -}; - -Note: Does not apply to ADC driver under arch/arm/plat-samsung/ -Note: The child node can be added under the adc node or separately. diff --git a/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml b/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml new file mode 100644 index 000000000000..f46de17c0878 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml @@ -0,0 +1,151 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/samsung,exynos-adc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos Analog to Digital Converter (ADC) + +maintainers: + - Krzysztof Kozlowski <[email protected]> + +properties: + compatible: + enum: + - samsung,exynos-adc-v1 # Exynos5250 + - samsung,exynos-adc-v2 + - samsung,exynos3250-adc + - samsung,exynos4212-adc # Exynos4212 and Exynos4412 + - samsung,exynos7-adc + - samsung,s3c2410-adc + - samsung,s3c2416-adc + - samsung,s3c2440-adc + - samsung,s3c2443-adc + - samsung,s3c6410-adc + - samsung,s5pv210-adc + + reg: + maxItems: 1 + + clocks: + description: + Phandle to ADC bus clock. For Exynos3250 additional clock is needed. + minItems: 1 + maxItems: 2 + + clock-names: + description: + Must contain clock names (adc, sclk) matching phandles in clocks + property. + minItems: 1 + maxItems: 2 + + interrupts: + maxItems: 1 + + "#io-channel-cells": + const: 1 + + vdd-supply: true + + samsung,syscon-phandle: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: + Phandle to the PMU system controller node (to access the ADC_PHY + register on Exynos3250/4x12/5250/5420/5800). + + has-touchscreen: + description: + If present, indicates that a touchscreen is connected and usable. + type: boolean + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - "#io-channel-cells" + - vdd-supply + +allOf: + - if: + properties: + compatible: + contains: + enum: + - samsung,exynos-adc-v1 + - samsung,exynos-adc-v2 + - samsung,exynos3250-adc + - samsung,exynos4212-adc + - samsung,s5pv210-adc + then: + required: + - samsung,syscon-phandle + + - if: + properties: + compatible: + contains: + enum: + - samsung,exynos3250-adc + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: adc + - const: sclk + else: + properties: + clocks: + minItems: 1 + maxItems: 1 + clock-names: + items: + - const: adc + +examples: + - | + adc: adc@12d10000 { + compatible = "samsung,exynos-adc-v1"; + reg = <0x12d10000 0x100>; + interrupts = <0 106 0>; + #io-channel-cells = <1>; + io-channel-ranges; + + clocks = <&clock 303>; + clock-names = "adc"; + + vdd-supply = <&buck5_reg>; + samsung,syscon-phandle = <&pmu_system_controller>; + + /* NTC thermistor is a hwmon device */ + ncp15wb473@0 { + compatible = "murata,ncp15wb473"; + pullup-uv = <1800000>; + pullup-ohm = <47000>; + pulldown-ohm = <0>; + io-channels = <&adc 4>; + }; + }; + + - | + #include <dt-bindings/clock/exynos3250.h> + + adc@126c0000 { + compatible = "samsung,exynos3250-adc"; + reg = <0x126C0000 0x100>; + interrupts = <0 137 0>; + #io-channel-cells = <1>; + io-channel-ranges; + + clocks = <&cmu CLK_TSADC>, + <&cmu CLK_SCLK_TSADC>; + clock-names = "adc", "sclk"; + + vdd-supply = <&buck5_reg>; + samsung,syscon-phandle = <&pmu_system_controller>; + }; diff --git a/Documentation/devicetree/bindings/iio/chemical/plantower,pms7003.yaml b/Documentation/devicetree/bindings/iio/chemical/plantower,pms7003.yaml index a551d3101f93..19e53930ebf6 100644 --- a/Documentation/devicetree/bindings/iio/chemical/plantower,pms7003.yaml +++ b/Documentation/devicetree/bindings/iio/chemical/plantower,pms7003.yaml @@ -25,7 +25,6 @@ properties: vcc-supply: description: regulator that provides power to the sensor - maxItems: 1 plantower,set-gpios: description: GPIO connected to the SET line diff --git a/Documentation/devicetree/bindings/iio/pressure/bmp085.yaml b/Documentation/devicetree/bindings/iio/pressure/bmp085.yaml index c6721a7e8938..519137e5c170 100644 --- a/Documentation/devicetree/bindings/iio/pressure/bmp085.yaml +++ b/Documentation/devicetree/bindings/iio/pressure/bmp085.yaml @@ -28,12 +28,10 @@ properties: vddd-supply: description: digital voltage regulator (see regulator/regulator.txt) - maxItems: 1 vdda-supply: description: analog voltage regulator (see regulator/regulator.txt) - maxItems: 1 reset-gpios: description: diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt b/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt deleted file mode 100644 index f977ea7617f6..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt +++ /dev/null @@ -1,48 +0,0 @@ -DT bindings for the R-Mobile/R-Car/RZ/G interrupt controller - -Required properties: - -- compatible: must be "renesas,irqc-<soctype>" or "renesas,intc-ex-<soctype>", - and "renesas,irqc" as fallback. - Examples with soctypes are: - - "renesas,irqc-r8a73a4" (R-Mobile APE6) - - "renesas,irqc-r8a7743" (RZ/G1M) - - "renesas,irqc-r8a7744" (RZ/G1N) - - "renesas,irqc-r8a7745" (RZ/G1E) - - "renesas,irqc-r8a77470" (RZ/G1C) - - "renesas,irqc-r8a7790" (R-Car H2) - - "renesas,irqc-r8a7791" (R-Car M2-W) - - "renesas,irqc-r8a7792" (R-Car V2H) - - "renesas,irqc-r8a7793" (R-Car M2-N) - - "renesas,irqc-r8a7794" (R-Car E2) - - "renesas,intc-ex-r8a774a1" (RZ/G2M) - - "renesas,intc-ex-r8a774c0" (RZ/G2E) - - "renesas,intc-ex-r8a7795" (R-Car H3) - - "renesas,intc-ex-r8a7796" (R-Car M3-W) - - "renesas,intc-ex-r8a77965" (R-Car M3-N) - - "renesas,intc-ex-r8a77970" (R-Car V3M) - - "renesas,intc-ex-r8a77980" (R-Car V3H) - - "renesas,intc-ex-r8a77990" (R-Car E3) - - "renesas,intc-ex-r8a77995" (R-Car D3) -- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in - interrupts.txt in this directory -- clocks: Must contain a reference to the functional clock. - -Optional properties: - -- any properties, listed in interrupts.txt, and any standard resource allocation - properties - -Example: - - irqc0: interrupt-controller@e61c0000 { - compatible = "renesas,irqc-r8a7790", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, - <0 1 IRQ_TYPE_LEVEL_HIGH>, - <0 2 IRQ_TYPE_LEVEL_HIGH>, - <0 3 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp4_clks R8A7790_CLK_IRQC>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.yaml new file mode 100644 index 000000000000..ee5273b6c5a3 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/renesas,irqc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: DT bindings for the R-Mobile/R-Car/RZ/G interrupt controller + +maintainers: + - Geert Uytterhoeven <[email protected]> + +properties: + compatible: + items: + - enum: + - renesas,irqc-r8a73a4 # R-Mobile APE6 + - renesas,irqc-r8a7743 # RZ/G1M + - renesas,irqc-r8a7744 # RZ/G1N + - renesas,irqc-r8a7745 # RZ/G1E + - renesas,irqc-r8a77470 # RZ/G1C + - renesas,irqc-r8a7790 # R-Car H2 + - renesas,irqc-r8a7791 # R-Car M2-W + - renesas,irqc-r8a7792 # R-Car V2H + - renesas,irqc-r8a7793 # R-Car M2-N + - renesas,irqc-r8a7794 # R-Car E2 + - renesas,intc-ex-r8a774a1 # RZ/G2M + - renesas,intc-ex-r8a774b1 # RZ/G2N + - renesas,intc-ex-r8a774c0 # RZ/G2E + - renesas,intc-ex-r8a7795 # R-Car H3 + - renesas,intc-ex-r8a7796 # R-Car M3-W + - renesas,intc-ex-r8a77965 # R-Car M3-N + - renesas,intc-ex-r8a77970 # R-Car V3M + - renesas,intc-ex-r8a77980 # R-Car V3H + - renesas,intc-ex-r8a77990 # R-Car E3 + - renesas,intc-ex-r8a77995 # R-Car D3 + - const: renesas,irqc + + '#interrupt-cells': + # an interrupt index and flags, as defined in interrupts.txt in + # this directory + const: 2 + + interrupt-controller: true + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + maxItems: 32 + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - '#interrupt-cells' + - interrupt-controller + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/r8a7790-cpg-mssr.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + + irqc0: interrupt-controller@e61c0000 { + compatible = "renesas,irqc-r8a7790", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 407>; + }; diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt deleted file mode 100644 index c9abbf3e4f68..000000000000 --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt +++ /dev/null @@ -1,77 +0,0 @@ -* ARM SMMUv3 Architecture Implementation - -The SMMUv3 architecture is a significant departure from previous -revisions, replacing the MMIO register interface with in-memory command -and event queues and adding support for the ATS and PRI components of -the PCIe specification. - -** SMMUv3 required properties: - -- compatible : Should include: - - * "arm,smmu-v3" for any SMMUv3 compliant - implementation. This entry should be last in the - compatible list. - -- reg : Base address and size of the SMMU. - -- interrupts : Non-secure interrupt list describing the wired - interrupt sources corresponding to entries in - interrupt-names. If no wired interrupts are - present then this property may be omitted. - -- interrupt-names : When the interrupts property is present, should - include the following: - * "eventq" - Event Queue not empty - * "priq" - PRI Queue not empty - * "cmdq-sync" - CMD_SYNC complete - * "gerror" - Global Error activated - * "combined" - The combined interrupt is optional, - and should only be provided if the - hardware supports just a single, - combined interrupt line. - If provided, then the combined interrupt - will be used in preference to any others. - -- #iommu-cells : See the generic IOMMU binding described in - devicetree/bindings/pci/pci-iommu.txt - for details. For SMMUv3, must be 1, with each cell - describing a single stream ID. All possible stream - IDs which a device may emit must be described. - -** SMMUv3 optional properties: - -- dma-coherent : Present if DMA operations made by the SMMU (page - table walks, stream table accesses etc) are cache - coherent with the CPU. - - NOTE: this only applies to the SMMU itself, not - masters connected upstream of the SMMU. - -- msi-parent : See the generic MSI binding described in - devicetree/bindings/interrupt-controller/msi.txt - for a description of the msi-parent property. - -- hisilicon,broken-prefetch-cmd - : Avoid sending CMD_PREFETCH_* commands to the SMMU. - -- cavium,cn9900-broken-page1-regspace - : Replaces all page 1 offsets used for EVTQ_PROD/CONS, - PRIQ_PROD/CONS register access with page 0 offsets. - Set for Cavium ThunderX2 silicon that doesn't support - SMMU page1 register space. - -** Example - - smmu@2b400000 { - compatible = "arm,smmu-v3"; - reg = <0x0 0x2b400000 0x0 0x20000>; - interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "eventq", "priq", "cmdq-sync", "gerror"; - dma-coherent; - #iommu-cells = <1>; - msi-parent = <&its 0xff0000>; - }; diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml new file mode 100644 index 000000000000..5951c6f98c74 --- /dev/null +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml @@ -0,0 +1,95 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iommu/arm,smmu-v3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM SMMUv3 Architecture Implementation + +maintainers: + - Will Deacon <[email protected]> + - Robin Murphy <[email protected]> + +description: |+ + The SMMUv3 architecture is a significant departure from previous + revisions, replacing the MMIO register interface with in-memory command + and event queues and adding support for the ATS and PRI components of + the PCIe specification. + +properties: + $nodename: + pattern: "^iommu@[0-9a-f]*" + compatible: + const: arm,smmu-v3 + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + maxItems: 4 + + interrupt-names: + oneOf: + - const: combined + description: + The combined interrupt is optional, and should only be provided if the + hardware supports just a single, combined interrupt line. + If provided, then the combined interrupt will be used in preference to + any others. + - minItems: 2 + maxItems: 4 + items: + - const: eventq # Event Queue not empty + - const: gerror # Global Error activated + - const: priq # PRI Queue not empty + - const: cmdq-sync # CMD_SYNC complete + + '#iommu-cells': + const: 1 + + dma-coherent: + description: | + Present if page table walks made by the SMMU are cache coherent with the + CPU. + + NOTE: this only applies to the SMMU itself, not masters connected + upstream of the SMMU. + + msi-parent: true + + hisilicon,broken-prefetch-cmd: + type: boolean + description: Avoid sending CMD_PREFETCH_* commands to the SMMU. + + cavium,cn9900-broken-page1-regspace: + type: boolean + description: + Replaces all page 1 offsets used for EVTQ_PROD/CONS, PRIQ_PROD/CONS + register access with page 0 offsets. Set for Cavium ThunderX2 silicon that + doesn't support SMMU page1 register space. + +required: + - compatible + - reg + - '#iommu-cells' + +additionalProperties: false + +examples: + - |+ + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + + iommu@2b400000 { + compatible = "arm,smmu-v3"; + reg = <0x2b400000 0x20000>; + interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; + dma-coherent; + #iommu-cells = <1>; + msi-parent = <&its 0xff0000>; + }; diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt deleted file mode 100644 index 3133f3ba7567..000000000000 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt +++ /dev/null @@ -1,182 +0,0 @@ -* ARM System MMU Architecture Implementation - -ARM SoCs may contain an implementation of the ARM System Memory -Management Unit Architecture, which can be used to provide 1 or 2 stages -of address translation to bus masters external to the CPU. - -The SMMU may also raise interrupts in response to various fault -conditions. - -** System MMU required properties: - -- compatible : Should be one of: - - "arm,smmu-v1" - "arm,smmu-v2" - "arm,mmu-400" - "arm,mmu-401" - "arm,mmu-500" - "cavium,smmu-v2" - "qcom,smmu-v2" - - depending on the particular implementation and/or the - version of the architecture implemented. - - Qcom SoCs must contain, as below, SoC-specific compatibles - along with "qcom,smmu-v2": - "qcom,msm8996-smmu-v2", "qcom,smmu-v2", - "qcom,sdm845-smmu-v2", "qcom,smmu-v2". - - Qcom SoCs implementing "arm,mmu-500" must also include, - as below, SoC-specific compatibles: - "qcom,sdm845-smmu-500", "arm,mmu-500" - -- reg : Base address and size of the SMMU. - -- #global-interrupts : The number of global interrupts exposed by the - device. - -- interrupts : Interrupt list, with the first #global-irqs entries - corresponding to the global interrupts and any - following entries corresponding to context interrupts, - specified in order of their indexing by the SMMU. - - For SMMUv2 implementations, there must be exactly one - interrupt per context bank. In the case of a single, - combined interrupt, it must be listed multiple times. - -- #iommu-cells : See Documentation/devicetree/bindings/iommu/iommu.txt - for details. With a value of 1, each IOMMU specifier - represents a distinct stream ID emitted by that device - into the relevant SMMU. - - SMMUs with stream matching support and complex masters - may use a value of 2, where the second cell of the - IOMMU specifier represents an SMR mask to combine with - the ID in the first cell. Care must be taken to ensure - the set of matched IDs does not result in conflicts. - -** System MMU optional properties: - -- dma-coherent : Present if page table walks made by the SMMU are - cache coherent with the CPU. - - NOTE: this only applies to the SMMU itself, not - masters connected upstream of the SMMU. - -- calxeda,smmu-secure-config-access : Enable proper handling of buggy - implementations that always use secure access to - SMMU configuration registers. In this case non-secure - aliases of secure registers have to be used during - SMMU configuration. - -- stream-match-mask : For SMMUs supporting stream matching and using - #iommu-cells = <1>, specifies a mask of bits to ignore - when matching stream IDs (e.g. this may be programmed - into the SMRn.MASK field of every stream match register - used). For cases where it is desirable to ignore some - portion of every Stream ID (e.g. for certain MMU-500 - configurations given globally unique input IDs). This - property is not valid for SMMUs using stream indexing, - or using stream matching with #iommu-cells = <2>, and - may be ignored if present in such cases. - -- clock-names: List of the names of clocks input to the device. The - required list depends on particular implementation and - is as follows: - - for "qcom,smmu-v2": - - "bus": clock required for downstream bus access and - for the smmu ptw, - - "iface": clock required to access smmu's registers - through the TCU's programming interface. - - unspecified for other implementations. - -- clocks: Specifiers for all clocks listed in the clock-names property, - as per generic clock bindings. - -- power-domains: Specifiers for power domains required to be powered on for - the SMMU to operate, as per generic power domain bindings. - -** Deprecated properties: - -- mmu-masters (deprecated in favour of the generic "iommus" binding) : - A list of phandles to device nodes representing bus - masters for which the SMMU can provide a translation - and their corresponding Stream IDs. Each device node - linked from this list must have a "#stream-id-cells" - property, indicating the number of Stream ID - arguments associated with its phandle. - -** Examples: - - /* SMMU with stream matching or stream indexing */ - smmu1: iommu { - compatible = "arm,smmu-v1"; - reg = <0xba5e0000 0x10000>; - #global-interrupts = <2>; - interrupts = <0 32 4>, - <0 33 4>, - <0 34 4>, /* This is the first context interrupt */ - <0 35 4>, - <0 36 4>, - <0 37 4>; - #iommu-cells = <1>; - }; - - /* device with two stream IDs, 0 and 7 */ - master1 { - iommus = <&smmu1 0>, - <&smmu1 7>; - }; - - - /* SMMU with stream matching */ - smmu2: iommu { - ... - #iommu-cells = <2>; - }; - - /* device with stream IDs 0 and 7 */ - master2 { - iommus = <&smmu2 0 0>, - <&smmu2 7 0>; - }; - - /* device with stream IDs 1, 17, 33 and 49 */ - master3 { - iommus = <&smmu2 1 0x30>; - }; - - - /* ARM MMU-500 with 10-bit stream ID input configuration */ - smmu3: iommu { - compatible = "arm,mmu-500", "arm,smmu-v2"; - ... - #iommu-cells = <1>; - /* always ignore appended 5-bit TBU number */ - stream-match-mask = 0x7c00; - }; - - bus { - /* bus whose child devices emit one unique 10-bit stream - ID each, but may master through multiple SMMU TBUs */ - iommu-map = <0 &smmu3 0 0x400>; - ... - }; - - /* Qcom's arm,smmu-v2 implementation */ - smmu4: iommu@d00000 { - compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; - reg = <0xd00000 0x10000>; - - #global-interrupts = <1>; - interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; - #iommu-cells = <1>; - power-domains = <&mmcc MDSS_GDSC>; - - clocks = <&mmcc SMMU_MDP_AXI_CLK>, - <&mmcc SMMU_MDP_AHB_CLK>; - clock-names = "bus", "iface"; - }; diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml new file mode 100644 index 000000000000..3b31b4802a54 --- /dev/null +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -0,0 +1,229 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iommu/arm,smmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM System MMU Architecture Implementation + +maintainers: + - Will Deacon <[email protected]> + - Robin Murphy <[email protected]> + +description: |+ + ARM SoCs may contain an implementation of the ARM System Memory + Management Unit Architecture, which can be used to provide 1 or 2 stages + of address translation to bus masters external to the CPU. + + The SMMU may also raise interrupts in response to various fault + conditions. + +properties: + $nodename: + pattern: "^iommu@[0-9a-f]*" + compatible: + oneOf: + - description: Qcom SoCs implementing "arm,smmu-v2" + items: + - enum: + - qcom,msm8996-smmu-v2 + - qcom,msm8998-smmu-v2 + - qcom,sdm845-smmu-v2 + - const: qcom,smmu-v2 + + - description: Qcom SoCs implementing "arm,mmu-500" + items: + - enum: + - qcom,sdm845-smmu-500 + - const: arm,mmu-500 + - items: + - const: arm,mmu-500 + - const: arm,smmu-v2 + - items: + - const: arm,mmu-401 + - const: arm,smmu-v1 + - enum: + - arm,smmu-v1 + - arm,smmu-v2 + - arm,mmu-400 + - arm,mmu-401 + - arm,mmu-500 + - cavium,smmu-v2 + + reg: + maxItems: 1 + + '#global-interrupts': + description: The number of global interrupts exposed by the device. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 260 # 2 secure, 2 non-secure, and up to 256 perf counters + + '#iommu-cells': + enum: [ 1, 2 ] + description: | + See Documentation/devicetree/bindings/iommu/iommu.txt for details. With a + value of 1, each IOMMU specifier represents a distinct stream ID emitted + by that device into the relevant SMMU. + + SMMUs with stream matching support and complex masters may use a value of + 2, where the second cell of the IOMMU specifier represents an SMR mask to + combine with the ID in the first cell. Care must be taken to ensure the + set of matched IDs does not result in conflicts. + + interrupts: + minItems: 1 + maxItems: 388 # 260 plus 128 contexts + description: | + Interrupt list, with the first #global-interrupts entries corresponding to + the global interrupts and any following entries corresponding to context + interrupts, specified in order of their indexing by the SMMU. + + For SMMUv2 implementations, there must be exactly one interrupt per + context bank. In the case of a single, combined interrupt, it must be + listed multiple times. + + dma-coherent: + description: | + Present if page table walks made by the SMMU are cache coherent with the + CPU. + + NOTE: this only applies to the SMMU itself, not masters connected + upstream of the SMMU. + + calxeda,smmu-secure-config-access: + type: boolean + description: + Enable proper handling of buggy implementations that always use secure + access to SMMU configuration registers. In this case non-secure aliases of + secure registers have to be used during SMMU configuration. + + stream-match-mask: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + For SMMUs supporting stream matching and using #iommu-cells = <1>, + specifies a mask of bits to ignore when matching stream IDs (e.g. this may + be programmed into the SMRn.MASK field of every stream match register + used). For cases where it is desirable to ignore some portion of every + Stream ID (e.g. for certain MMU-500 configurations given globally unique + input IDs). This property is not valid for SMMUs using stream indexing, or + using stream matching with #iommu-cells = <2>, and may be ignored if + present in such cases. + + clock-names: + items: + - const: bus + - const: iface + + clocks: + items: + - description: bus clock required for downstream bus access and for the + smmu ptw + - description: interface clock required to access smmu's registers + through the TCU's programming interface. + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - '#global-interrupts' + - '#iommu-cells' + - interrupts + +additionalProperties: false + +examples: + - |+ + /* SMMU with stream matching or stream indexing */ + smmu1: iommu@ba5e0000 { + compatible = "arm,smmu-v1"; + reg = <0xba5e0000 0x10000>; + #global-interrupts = <2>; + interrupts = <0 32 4>, + <0 33 4>, + <0 34 4>, /* This is the first context interrupt */ + <0 35 4>, + <0 36 4>, + <0 37 4>; + #iommu-cells = <1>; + }; + + /* device with two stream IDs, 0 and 7 */ + master1 { + iommus = <&smmu1 0>, + <&smmu1 7>; + }; + + + /* SMMU with stream matching */ + smmu2: iommu@ba5f0000 { + compatible = "arm,smmu-v1"; + reg = <0xba5f0000 0x10000>; + #global-interrupts = <2>; + interrupts = <0 38 4>, + <0 39 4>, + <0 40 4>, /* This is the first context interrupt */ + <0 41 4>, + <0 42 4>, + <0 43 4>; + #iommu-cells = <2>; + }; + + /* device with stream IDs 0 and 7 */ + master2 { + iommus = <&smmu2 0 0>, + <&smmu2 7 0>; + }; + + /* device with stream IDs 1, 17, 33 and 49 */ + master3 { + iommus = <&smmu2 1 0x30>; + }; + + + /* ARM MMU-500 with 10-bit stream ID input configuration */ + smmu3: iommu@ba600000 { + compatible = "arm,mmu-500", "arm,smmu-v2"; + reg = <0xba600000 0x10000>; + #global-interrupts = <2>; + interrupts = <0 44 4>, + <0 45 4>, + <0 46 4>, /* This is the first context interrupt */ + <0 47 4>, + <0 48 4>, + <0 49 4>; + #iommu-cells = <1>; + /* always ignore appended 5-bit TBU number */ + stream-match-mask = <0x7c00>; + }; + + bus { + /* bus whose child devices emit one unique 10-bit stream + ID each, but may master through multiple SMMU TBUs */ + iommu-map = <0 &smmu3 0 0x400>; + + + }; + + - |+ + /* Qcom's arm,smmu-v2 implementation */ + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + smmu4: iommu@d00000 { + compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; + reg = <0xd00000 0x10000>; + + #global-interrupts = <1>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + power-domains = <&mmcc 0>; + + clocks = <&mmcc 123>, + <&mmcc 124>; + clock-names = "bus", "iface"; + }; diff --git a/Documentation/devicetree/bindings/iommu/samsung,sysmmu.txt b/Documentation/devicetree/bindings/iommu/samsung,sysmmu.txt deleted file mode 100644 index 525ec82615a6..000000000000 --- a/Documentation/devicetree/bindings/iommu/samsung,sysmmu.txt +++ /dev/null @@ -1,67 +0,0 @@ -Samsung Exynos IOMMU H/W, System MMU (System Memory Management Unit) - -Samsung's Exynos architecture contains System MMUs that enables scattered -physical memory chunks visible as a contiguous region to DMA-capable peripheral -devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth. - -System MMU is an IOMMU and supports identical translation table format to -ARMv7 translation tables with minimum set of page properties including access -permissions, shareability and security protection. In addition, System MMU has -another capabilities like L2 TLB or block-fetch buffers to minimize translation -latency. - -System MMUs are in many to one relation with peripheral devices, i.e. single -peripheral device might have multiple System MMUs (usually one for each bus -master), but one System MMU can handle transactions from only one peripheral -device. The relation between a System MMU and the peripheral device needs to be -defined in device node of the peripheral device. - -MFC in all Exynos SoCs and FIMD, M2M Scalers and G2D in Exynos5420 has 2 System -MMUs. -* MFC has one System MMU on its left and right bus. -* FIMD in Exynos5420 has one System MMU for window 0 and 4, the other system MMU - for window 1, 2 and 3. -* M2M Scalers and G2D in Exynos5420 has one System MMU on the read channel and - the other System MMU on the write channel. - -For information on assigning System MMU controller to its peripheral devices, -see generic IOMMU bindings. - -Required properties: -- compatible: Should be "samsung,exynos-sysmmu" -- reg: A tuple of base address and size of System MMU registers. -- #iommu-cells: Should be <0>. -- interrupts: An interrupt specifier for interrupt signal of System MMU, - according to the format defined by a particular interrupt - controller. -- clock-names: Should be "sysmmu" or a pair of "aclk" and "pclk" to gate - SYSMMU core clocks. - Optional "master" if the clock to the System MMU is gated by - another gate clock other core (usually main gate clock - of peripheral device this SYSMMU belongs to). -- clocks: Phandles for respective clocks described by clock-names. -- power-domains: Required if the System MMU is needed to gate its power. - Please refer to the following document: - Documentation/devicetree/bindings/power/pd-samsung.txt - -Examples: - gsc_0: gsc@13e00000 { - compatible = "samsung,exynos5-gsc"; - reg = <0x13e00000 0x1000>; - interrupts = <0 85 0>; - power-domains = <&pd_gsc>; - clocks = <&clock CLK_GSCL0>; - clock-names = "gscl"; - iommus = <&sysmmu_gsc0>; - }; - - sysmmu_gsc0: sysmmu@13e80000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13E80000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <2 0>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>; - power-domains = <&pd_gsc>; - #iommu-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/iommu/samsung,sysmmu.yaml b/Documentation/devicetree/bindings/iommu/samsung,sysmmu.yaml new file mode 100644 index 000000000000..ecde98da5b72 --- /dev/null +++ b/Documentation/devicetree/bindings/iommu/samsung,sysmmu.yaml @@ -0,0 +1,108 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iommu/samsung,sysmmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos IOMMU H/W, System MMU (System Memory Management Unit) + +maintainers: + - Marek Szyprowski <[email protected]> + +description: |+ + Samsung's Exynos architecture contains System MMUs that enables scattered + physical memory chunks visible as a contiguous region to DMA-capable peripheral + devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth. + + System MMU is an IOMMU and supports identical translation table format to + ARMv7 translation tables with minimum set of page properties including access + permissions, shareability and security protection. In addition, System MMU has + another capabilities like L2 TLB or block-fetch buffers to minimize translation + latency. + + System MMUs are in many to one relation with peripheral devices, i.e. single + peripheral device might have multiple System MMUs (usually one for each bus + master), but one System MMU can handle transactions from only one peripheral + device. The relation between a System MMU and the peripheral device needs to be + defined in device node of the peripheral device. + + MFC in all Exynos SoCs and FIMD, M2M Scalers and G2D in Exynos5420 has 2 System + MMUs. + * MFC has one System MMU on its left and right bus. + * FIMD in Exynos5420 has one System MMU for window 0 and 4, the other system MMU + for window 1, 2 and 3. + * M2M Scalers and G2D in Exynos5420 has one System MMU on the read channel and + the other System MMU on the write channel. + + For information on assigning System MMU controller to its peripheral devices, + see generic IOMMU bindings. + +properties: + compatible: + const: samsung,exynos-sysmmu + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + oneOf: + - items: + - const: sysmmu + - items: + - const: sysmmu + - const: master + - items: + - const: aclk + - const: pclk + + "#iommu-cells": + const: 0 + + power-domains: + description: | + Required if the System MMU is needed to gate its power. + Please refer to the following document: + Documentation/devicetree/bindings/power/pd-samsung.txt + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - "#iommu-cells" + +examples: + - | + #include <dt-bindings/clock/exynos5250.h> + + gsc_0: scaler@13e00000 { + compatible = "samsung,exynos5-gsc"; + reg = <0x13e00000 0x1000>; + interrupts = <0 85 0>; + power-domains = <&pd_gsc>; + clocks = <&clock CLK_GSCL0>; + clock-names = "gscl"; + iommus = <&sysmmu_gsc0>; + }; + + sysmmu_gsc0: iommu@13e80000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13E80000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <2 0>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_GSCL0>, + <&clock CLK_GSCL0>; + power-domains = <&pd_gsc>; + #iommu-cells = <0>; + }; + diff --git a/Documentation/devicetree/bindings/media/st,stm32-cec.txt b/Documentation/devicetree/bindings/media/st,stm32-cec.txt deleted file mode 100644 index 6be2381c180d..000000000000 --- a/Documentation/devicetree/bindings/media/st,stm32-cec.txt +++ /dev/null @@ -1,19 +0,0 @@ -STMicroelectronics STM32 CEC driver - -Required properties: - - compatible : value should be "st,stm32-cec" - - reg : Physical base address of the IP registers and length of memory - mapped region. - - clocks : from common clock binding: handle to CEC clocks - - clock-names : from common clock binding: must be "cec" and "hdmi-cec". - - interrupts : CEC interrupt number to the CPU. - -Example for stm32f746: - -cec: cec@40006c00 { - compatible = "st,stm32-cec"; - reg = <0x40006C00 0x400>; - interrupts = <94>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>; - clock-names = "cec", "hdmi-cec"; -}; diff --git a/Documentation/devicetree/bindings/media/st,stm32-cec.yaml b/Documentation/devicetree/bindings/media/st,stm32-cec.yaml new file mode 100644 index 000000000000..d75019c093a4 --- /dev/null +++ b/Documentation/devicetree/bindings/media/st,stm32-cec.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/st,stm32-cec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32 CEC bindings + +maintainers: + - Benjamin Gaignard <[email protected]> + - Yannick Fertre <[email protected]> + +properties: + compatible: + const: st,stm32-cec + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Module Clock + - description: Bus Clock + + clock-names: + items: + - const: cec + - const: hdmi-cec + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/stm32mp1-clks.h> + cec: cec@40006c00 { + compatible = "st,stm32-cec"; + reg = <0x40006c00 0x400>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CEC_K>, <&clk_lse>; + clock-names = "cec", "hdmi-cec"; + }; + +... diff --git a/Documentation/devicetree/bindings/media/st,stm32-dcmi.txt b/Documentation/devicetree/bindings/media/st,stm32-dcmi.txt deleted file mode 100644 index 3122ded82eb4..000000000000 --- a/Documentation/devicetree/bindings/media/st,stm32-dcmi.txt +++ /dev/null @@ -1,45 +0,0 @@ -STMicroelectronics STM32 Digital Camera Memory Interface (DCMI) - -Required properties: -- compatible: "st,stm32-dcmi" -- reg: physical base address and length of the registers set for the device -- interrupts: should contain IRQ line for the DCMI -- resets: reference to a reset controller, - see Documentation/devicetree/bindings/reset/st,stm32-rcc.txt -- clocks: list of clock specifiers, corresponding to entries in - the clock-names property -- clock-names: must contain "mclk", which is the DCMI peripherial clock -- pinctrl: the pincontrol settings to configure muxing properly - for pins that connect to DCMI device. - See Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml. -- dmas: phandle to DMA controller node, - see Documentation/devicetree/bindings/dma/stm32-dma.txt -- dma-names: must contain "tx", which is the transmit channel from DCMI to DMA - -DCMI supports a single port node with parallel bus. It should contain one -'port' child node with child 'endpoint' node. Please refer to the bindings -defined in Documentation/devicetree/bindings/media/video-interfaces.txt. - -Example: - - dcmi: dcmi@50050000 { - compatible = "st,stm32-dcmi"; - reg = <0x50050000 0x400>; - interrupts = <78>; - resets = <&rcc STM32F4_AHB2_RESET(DCMI)>; - clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>; - clock-names = "mclk"; - pinctrl-names = "default"; - pinctrl-0 = <&dcmi_pins>; - dmas = <&dma2 1 1 0x414 0x3>; - dma-names = "tx"; - port { - dcmi_0: endpoint { - remote-endpoint = <...>; - bus-width = <8>; - hsync-active = <0>; - vsync-active = <0>; - pclk-sample = <1>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml b/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml new file mode 100644 index 000000000000..3fe778cb5cc3 --- /dev/null +++ b/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/st,stm32-dcmi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32 Digital Camera Memory Interface (DCMI) binding + +maintainers: + - Hugues Fruchet <[email protected]> + +properties: + compatible: + const: st,stm32-dcmi + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: mclk + + dmas: + maxItems: 1 + + dma-names: + items: + - const: tx + + resets: + maxItems: 1 + + port: + type: object + description: + DCMI supports a single port node with parallel bus. It should contain + one 'port' child node with child 'endpoint' node. Please refer to the + bindings defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - dmas + - dma-names + - port + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/stm32mp1-clks.h> + #include <dt-bindings/reset/stm32mp1-resets.h> + dcmi: dcmi@4c006000 { + compatible = "st,stm32-dcmi"; + reg = <0x4c006000 0x400>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rcc CAMITF_R>; + clocks = <&rcc DCMI>; + clock-names = "mclk"; + dmas = <&dmamux1 75 0x400 0x0d>; + dma-names = "tx"; + + port { + dcmi_0: endpoint { + remote-endpoint = <&ov5640_0>; + bus-width = <8>; + hsync-active = <0>; + vsync-active = <0>; + pclk-sample = <1>; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/memory-controllers/exynos-srom.txt b/Documentation/devicetree/bindings/memory-controllers/exynos-srom.txt deleted file mode 100644 index f633b5d0f8ca..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/exynos-srom.txt +++ /dev/null @@ -1,79 +0,0 @@ -SAMSUNG Exynos SoCs SROM Controller driver. - -Required properties: -- compatible : Should contain "samsung,exynos4210-srom". - -- reg: offset and length of the register set - -Optional properties: -The SROM controller can be used to attach external peripherals. In this case -extra properties, describing the bus behind it, should be specified as below: - -- #address-cells: Must be set to 2 to allow device address translation. - Address is specified as (bank#, offset). - -- #size-cells: Must be set to 1 to allow device size passing - -- ranges: Must be set up to reflect the memory layout with four integer values - per bank: - <bank-number> 0 <parent address of bank> <size> - -Sub-nodes: -The actual device nodes should be added as subnodes to the SROMc node. These -subnodes, in addition to regular device specification, should contain the following -properties, describing configuration of the relevant SROM bank: - -Required properties: -- reg: bank number, base address (relative to start of the bank) and size of - the memory mapped for the device. Note that base address will be - typically 0 as this is the start of the bank. - -- samsung,srom-timing : array of 6 integers, specifying bank timings in the - following order: Tacp, Tcah, Tcoh, Tacc, Tcos, Tacs. - Each value is specified in cycles and has the following - meaning and valid range: - Tacp : Page mode access cycle at Page mode (0 - 15) - Tcah : Address holding time after CSn (0 - 15) - Tcoh : Chip selection hold on OEn (0 - 15) - Tacc : Access cycle (0 - 31, the actual time is N + 1) - Tcos : Chip selection set-up before OEn (0 - 15) - Tacs : Address set-up before CSn (0 - 15) - -Optional properties: -- reg-io-width : data width in bytes (1 or 2). If omitted, default of 1 is used. - -- samsung,srom-page-mode : if page mode is set, 4 data page mode will be configured, - else normal (1 data) page mode will be set. - -Example: basic definition, no banks are configured - memory-controller@12570000 { - compatible = "samsung,exynos4210-srom"; - reg = <0x12570000 0x14>; - }; - -Example: SROMc with SMSC911x ethernet chip on bank 3 - memory-controller@12570000 { - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x04000000 0x20000 // Bank0 - 1 0 0x05000000 0x20000 // Bank1 - 2 0 0x06000000 0x20000 // Bank2 - 3 0 0x07000000 0x20000>; // Bank3 - - compatible = "samsung,exynos4210-srom"; - reg = <0x12570000 0x14>; - - ethernet@3,0 { - compatible = "smsc,lan9115"; - reg = <3 0 0x10000>; // Bank 3, offset = 0 - phy-mode = "mii"; - interrupt-parent = <&gpx0>; - interrupts = <5 8>; - reg-io-width = <2>; - smsc,irq-push-pull; - smsc,force-internal-phy; - - samsung,srom-page-mode; - samsung,srom-timing = <9 12 1 9 1 1>; - }; - }; diff --git a/Documentation/devicetree/bindings/memory-controllers/exynos-srom.yaml b/Documentation/devicetree/bindings/memory-controllers/exynos-srom.yaml new file mode 100644 index 000000000000..cdfe3f7f0ea9 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/exynos-srom.yaml @@ -0,0 +1,128 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/exynos-srom.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos SoC SROM Controller driver + +maintainers: + - Krzysztof Kozlowski <[email protected]> + +description: |+ + The SROM controller can be used to attach external peripherals. In this case + extra properties, describing the bus behind it, should be specified. + +properties: + compatible: + items: + - const: samsung,exynos4210-srom + + reg: + maxItems: 1 + + "#address-cells": + const: 2 + + "#size-cells": + const: 1 + + ranges: + description: | + Reflects the memory layout with four integer values per bank. Format: + <bank-number> 0 <parent address of bank> <size> + Up to four banks are supported. + +patternProperties: + "^.*@[0-3],[a-f0-9]+$": + type: object + description: + The actual device nodes should be added as subnodes to the SROMc node. + These subnodes, in addition to regular device specification, should + contain the following properties, describing configuration + of the relevant SROM bank. + + properties: + reg: + description: + Bank number, base address (relative to start of the bank) and size + of the memory mapped for the device. Note that base address will be + typically 0 as this is the start of the bank. + maxItems: 1 + + reg-io-width: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [1, 2] + description: + Data width in bytes (1 or 2). If omitted, default of 1 is used. + + samsung,srom-page-mode: + description: + If page mode is set, 4 data page mode will be configured, + else normal (1 data) page mode will be set. + type: boolean + + samsung,srom-timing: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32-array + - items: + minItems: 6 + maxItems: 6 + description: | + Array of 6 integers, specifying bank timings in the following order: + Tacp, Tcah, Tcoh, Tacc, Tcos, Tacs. + Each value is specified in cycles and has the following meaning + and valid range: + Tacp: Page mode access cycle at Page mode (0 - 15) + Tcah: Address holding time after CSn (0 - 15) + Tcoh: Chip selection hold on OEn (0 - 15) + Tacc: Access cycle (0 - 31, the actual time is N + 1) + Tcos: Chip selection set-up before OEn (0 - 15) + Tacs: Address set-up before CSn (0 - 15) + + required: + - reg + - samsung,srom-timing + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + // Example: basic definition, no banks are configured + memory-controller@12560000 { + compatible = "samsung,exynos4210-srom"; + reg = <0x12560000 0x14>; + }; + + - | + // Example: SROMc with SMSC911x ethernet chip on bank 3 + memory-controller@12570000 { + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x04000000 0x20000 // Bank0 + 1 0 0x05000000 0x20000 // Bank1 + 2 0 0x06000000 0x20000 // Bank2 + 3 0 0x07000000 0x20000>; // Bank3 + + compatible = "samsung,exynos4210-srom"; + reg = <0x12570000 0x14>; + + ethernet@3,0 { + compatible = "smsc,lan9115"; + reg = <3 0 0x10000>; // Bank 3, offset = 0 + phy-mode = "mii"; + interrupt-parent = <&gpx0>; + interrupts = <5 8>; + reg-io-width = <2>; + smsc,irq-push-pull; + smsc,force-internal-phy; + + samsung,srom-page-mode; + samsung,srom-timing = <9 12 1 9 1 1>; + }; + }; diff --git a/Documentation/devicetree/bindings/pci/rcar-pci.txt b/Documentation/devicetree/bindings/pci/rcar-pci.txt index 45bba9f88a51..12702c8c46ce 100644 --- a/Documentation/devicetree/bindings/pci/rcar-pci.txt +++ b/Documentation/devicetree/bindings/pci/rcar-pci.txt @@ -4,6 +4,7 @@ Required properties: compatible: "renesas,pcie-r8a7743" for the R8A7743 SoC; "renesas,pcie-r8a7744" for the R8A7744 SoC; "renesas,pcie-r8a774a1" for the R8A774A1 SoC; + "renesas,pcie-r8a774b1" for the R8A774B1 SoC; "renesas,pcie-r8a774c0" for the R8A774C0 SoC; "renesas,pcie-r8a7779" for the R8A7779 SoC; "renesas,pcie-r8a7790" for the R8A7790 SoC; diff --git a/Documentation/devicetree/bindings/phy/amlogic,meson-g12a-usb2-phy.yaml b/Documentation/devicetree/bindings/phy/amlogic,meson-g12a-usb2-phy.yaml index 51254b4e65dd..57d8603076bd 100644 --- a/Documentation/devicetree/bindings/phy/amlogic,meson-g12a-usb2-phy.yaml +++ b/Documentation/devicetree/bindings/phy/amlogic,meson-g12a-usb2-phy.yaml @@ -36,7 +36,6 @@ properties: const: 0 phy-supply: - maxItems: 1 description: Phandle to a regulator that provides power to the PHY. This regulator will be managed during the PHY power on/off sequence. diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml index 400df2da018a..754ea7ab040a 100644 --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml @@ -40,10 +40,9 @@ properties: allOf: - $ref: "/schemas/types.yaml#/definitions/phandle-array" description: Should be phandle/offset/mask - items: - - description: Phandle to the syscon node which includes IRQ mux selection. - - description: The offset of the IRQ mux selection register. - - description: The field mask of IRQ mux, needed if different of 0xf. + - Phandle to the syscon node which includes IRQ mux selection. + - The offset of the IRQ mux selection register. + - The field mask of IRQ mux, needed if different of 0xf. st,package: allOf: diff --git a/Documentation/devicetree/bindings/power/reset/syscon-poweroff.txt b/Documentation/devicetree/bindings/power/reset/syscon-poweroff.txt deleted file mode 100644 index 022ed1f3bc80..000000000000 --- a/Documentation/devicetree/bindings/power/reset/syscon-poweroff.txt +++ /dev/null @@ -1,30 +0,0 @@ -Generic SYSCON mapped register poweroff driver - -This is a generic poweroff driver using syscon to map the poweroff register. -The poweroff is generally performed with a write to the poweroff register -defined by the register map pointed by syscon reference plus the offset -with the value and mask defined in the poweroff node. - -Required properties: -- compatible: should contain "syscon-poweroff" -- regmap: this is phandle to the register map node -- offset: offset in the register map for the poweroff register (in bytes) -- value: the poweroff value written to the poweroff register (32 bit access) - -Optional properties: -- mask: update only the register bits defined by the mask (32 bit) - -Legacy usage: -If a node doesn't contain a value property but contains a mask property, the -mask property is used as the value. - -Default will be little endian mode, 32 bit access only. - -Examples: - - poweroff { - compatible = "syscon-poweroff"; - regmap = <®mapnode>; - offset = <0x0>; - mask = <0x7a>; - }; diff --git a/Documentation/devicetree/bindings/power/reset/syscon-poweroff.yaml b/Documentation/devicetree/bindings/power/reset/syscon-poweroff.yaml new file mode 100644 index 000000000000..520e07e6f21b --- /dev/null +++ b/Documentation/devicetree/bindings/power/reset/syscon-poweroff.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/reset/syscon-poweroff.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Generic SYSCON mapped register poweroff driver + +maintainers: + - Sebastian Reichel <[email protected]> + +description: |+ + This is a generic poweroff driver using syscon to map the poweroff register. + The poweroff is generally performed with a write to the poweroff register + defined by the register map pointed by syscon reference plus the offset + with the value and mask defined in the poweroff node. + Default will be little endian mode, 32 bit access only. + +properties: + compatible: + const: syscon-poweroff + + mask: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Update only the register bits defined by the mask (32 bit). + + offset: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Offset in the register map for the poweroff register (in bytes). + + regmap: + $ref: /schemas/types.yaml#/definitions/phandle + description: Phandle to the register map node. + + value: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The poweroff value written to the poweroff register (32 bit access). + +required: + - compatible + - regmap + - offset + +allOf: + - if: + not: + required: + - mask + then: + required: + - value + +examples: + - | + poweroff { + compatible = "syscon-poweroff"; + regmap = <®mapnode>; + offset = <0x0>; + mask = <0x7a>; + }; diff --git a/Documentation/devicetree/bindings/power/reset/syscon-reboot.txt b/Documentation/devicetree/bindings/power/reset/syscon-reboot.txt deleted file mode 100644 index e23dea8344f8..000000000000 --- a/Documentation/devicetree/bindings/power/reset/syscon-reboot.txt +++ /dev/null @@ -1,30 +0,0 @@ -Generic SYSCON mapped register reset driver - -This is a generic reset driver using syscon to map the reset register. -The reset is generally performed with a write to the reset register -defined by the register map pointed by syscon reference plus the offset -with the value and mask defined in the reboot node. - -Required properties: -- compatible: should contain "syscon-reboot" -- regmap: this is phandle to the register map node -- offset: offset in the register map for the reboot register (in bytes) -- value: the reset value written to the reboot register (32 bit access) - -Optional properties: -- mask: update only the register bits defined by the mask (32 bit) - -Legacy usage: -If a node doesn't contain a value property but contains a mask property, the -mask property is used as the value. - -Default will be little endian mode, 32 bit access only. - -Examples: - - reboot { - compatible = "syscon-reboot"; - regmap = <®mapnode>; - offset = <0x0>; - mask = <0x1>; - }; diff --git a/Documentation/devicetree/bindings/power/reset/syscon-reboot.yaml b/Documentation/devicetree/bindings/power/reset/syscon-reboot.yaml new file mode 100644 index 000000000000..d38006b1f1f4 --- /dev/null +++ b/Documentation/devicetree/bindings/power/reset/syscon-reboot.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/reset/syscon-reboot.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Generic SYSCON mapped register reset driver + +maintainers: + - Sebastian Reichel <[email protected]> + +description: |+ + This is a generic reset driver using syscon to map the reset register. + The reset is generally performed with a write to the reset register + defined by the register map pointed by syscon reference plus the offset + with the value and mask defined in the reboot node. + Default will be little endian mode, 32 bit access only. + +properties: + compatible: + const: syscon-reboot + + mask: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Update only the register bits defined by the mask (32 bit). + + offset: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Offset in the register map for the reboot register (in bytes). + + regmap: + $ref: /schemas/types.yaml#/definitions/phandle + description: Phandle to the register map node. + + value: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The reset value written to the reboot register (32 bit access). + +required: + - compatible + - regmap + - offset + +allOf: + - if: + not: + required: + - mask + then: + required: + - value + +examples: + - | + reboot { + compatible = "syscon-reboot"; + regmap = <®mapnode>; + offset = <0x0>; + mask = <0x1>; + }; diff --git a/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt b/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt deleted file mode 100644 index fbd6a4f943ce..000000000000 --- a/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt +++ /dev/null @@ -1,40 +0,0 @@ -* Renesas R-Car PWM Timer Controller - -Required Properties: -- compatible: should be "renesas,pwm-rcar" and one of the following. - - "renesas,pwm-r8a7743": for RZ/G1M - - "renesas,pwm-r8a7744": for RZ/G1N - - "renesas,pwm-r8a7745": for RZ/G1E - - "renesas,pwm-r8a774a1": for RZ/G2M - - "renesas,pwm-r8a774c0": for RZ/G2E - - "renesas,pwm-r8a7778": for R-Car M1A - - "renesas,pwm-r8a7779": for R-Car H1 - - "renesas,pwm-r8a7790": for R-Car H2 - - "renesas,pwm-r8a7791": for R-Car M2-W - - "renesas,pwm-r8a7794": for R-Car E2 - - "renesas,pwm-r8a7795": for R-Car H3 - - "renesas,pwm-r8a7796": for R-Car M3-W - - "renesas,pwm-r8a77965": for R-Car M3-N - - "renesas,pwm-r8a77970": for R-Car V3M - - "renesas,pwm-r8a77980": for R-Car V3H - - "renesas,pwm-r8a77990": for R-Car E3 - - "renesas,pwm-r8a77995": for R-Car D3 -- reg: base address and length of the registers block for the PWM. -- #pwm-cells: should be 2. See pwm.txt in this directory for a description of - the cells format. -- clocks: clock phandle and specifier pair. -- pinctrl-0: phandle, referring to a default pin configuration node. -- pinctrl-names: Set to "default". - -Example: R8A7743 (RZ/G1M) PWM Timer node - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - pinctrl-0 = <&pwm0_pins>; - pinctrl-names = "default"; - }; diff --git a/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.yaml b/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.yaml new file mode 100644 index 000000000000..272a4df4a9d1 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/renesas,pwm-rcar.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas R-Car PWM Timer Controller + +maintainers: + - Yoshihiro Shimoda <[email protected]> + +properties: + compatible: + items: + - enum: + - renesas,pwm-r8a7743 # RZ/G1M + - renesas,pwm-r8a7744 # RZ/G1N + - renesas,pwm-r8a7745 # RZ/G1E + - renesas,pwm-r8a77470 # RZ/G1C + - renesas,pwm-r8a774a1 # RZ/G2M + - renesas,pwm-r8a774b1 # RZ/G2N + - renesas,pwm-r8a774c0 # RZ/G2E + - renesas,pwm-r8a7778 # R-Car M1A + - renesas,pwm-r8a7779 # R-Car H1 + - renesas,pwm-r8a7790 # R-Car H2 + - renesas,pwm-r8a7791 # R-Car M2-W + - renesas,pwm-r8a7794 # R-Car E2 + - renesas,pwm-r8a7795 # R-Car H3 + - renesas,pwm-r8a7796 # R-Car M3-W + - renesas,pwm-r8a77965 # R-Car M3-N + - renesas,pwm-r8a77970 # R-Car V3M + - renesas,pwm-r8a77980 # R-Car V3H + - renesas,pwm-r8a77990 # R-Car E3 + - renesas,pwm-r8a77995 # R-Car D3 + - const: renesas,pwm-rcar + + reg: + # base address and length of the registers block for the PWM. + maxItems: 1 + + '#pwm-cells': + # should be 2. See pwm.txt in this directory for a description of + # the cells format. + const: 2 + + clocks: + # clock phandle and specifier pair. + maxItems: 1 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - '#pwm-cells' + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/r8a7743-cpg-mssr.h> + #include <dt-bindings/power/r8a7743-sysc.h> + + pwm0: pwm@e6e30000 { + compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar"; + reg = <0 0xe6e30000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + pinctrl-0 = <&pwm0_pins>; + pinctrl-names = "default"; + }; diff --git a/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt b/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt deleted file mode 100644 index 848a92b53d81..000000000000 --- a/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt +++ /dev/null @@ -1,35 +0,0 @@ -* Renesas R-Car Timer Pulse Unit PWM Controller - -Required Properties: - - - compatible: must contain one or more of the following: - - "renesas,tpu-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible PWM controller. - - "renesas,tpu-r8a7740": for R8A7740 (R-Mobile A1) compatible PWM controller. - - "renesas,tpu-r8a7743": for R8A7743 (RZ/G1M) compatible PWM controller. - - "renesas,tpu-r8a7744": for R8A7744 (RZ/G1N) compatible PWM controller. - - "renesas,tpu-r8a7745": for R8A7745 (RZ/G1E) compatible PWM controller. - - "renesas,tpu-r8a7790": for R8A7790 (R-Car H2) compatible PWM controller. - - "renesas,tpu-r8a77970": for R8A77970 (R-Car V3M) compatible PWM - controller. - - "renesas,tpu-r8a77980": for R8A77980 (R-Car V3H) compatible PWM - controller. - - "renesas,tpu": for the generic TPU PWM controller; this is a fallback for - the entries listed above. - - - reg: Base address and length of each memory resource used by the PWM - controller hardware module. - - - #pwm-cells: should be 3. See pwm.txt in this directory for a description of - the cells format. The only third cell flag supported by this binding is - PWM_POLARITY_INVERTED. - -Please refer to pwm.txt in this directory for details of the common PWM bindings -used by client devices. - -Example: R8A7740 (R-Mobile A1) TPU controller node - - tpu: pwm@e6600000 { - compatible = "renesas,tpu-r8a7740", "renesas,tpu"; - reg = <0xe6600000 0x148>; - #pwm-cells = <3>; - }; diff --git a/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.yaml b/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.yaml new file mode 100644 index 000000000000..4908f004651b --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/renesas,tpu-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas R-Car Timer Pulse Unit PWM Controller + +maintainers: + - Laurent Pinchart <[email protected]> + +properties: + compatible: + items: + - enum: + - renesas,tpu-r8a73a4 # R-Mobile APE6 + - renesas,tpu-r8a7740 # R-Mobile A1 + - renesas,tpu-r8a7743 # RZ/G1M + - renesas,tpu-r8a7744 # RZ/G1N + - renesas,tpu-r8a7745 # RZ/G1E + - renesas,tpu-r8a7790 # R-Car H2 + - renesas,tpu-r8a7795 # R-Car H3 + - renesas,tpu-r8a7796 # R-Car M3-W + - renesas,tpu-r8a77965 # R-Car M3-N + - renesas,tpu-r8a77970 # R-Car V3M + - renesas,tpu-r8a77980 # R-Car V3H + - const: renesas,tpu + + reg: + # Base address and length of each memory resource used by the PWM + # controller hardware module. + maxItems: 1 + + interrupts: + maxItems: 1 + + '#pwm-cells': + # should be 3. See pwm.txt in this directory for a description of + # the cells format. The only third cell flag supported by this binding is + # PWM_POLARITY_INVERTED. + const: 3 + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - '#pwm-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/r8a7740-clock.h> + + tpu: pwm@e6600000 { + compatible = "renesas,tpu-r8a7740", "renesas,tpu"; + reg = <0xe6600000 0x148>; + clocks = <&mstp3_clks R8A7740_CLK_TPU0>; + power-domains = <&pd_a3sp>; + #pwm-cells = <3>; + }; diff --git a/Documentation/devicetree/bindings/regulator/fixed-regulator.yaml b/Documentation/devicetree/bindings/regulator/fixed-regulator.yaml index a78150c47aa2..e56d97b233f4 100644 --- a/Documentation/devicetree/bindings/regulator/fixed-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/fixed-regulator.yaml @@ -64,7 +64,6 @@ properties: vin-supply: description: Input supply phandle. - $ref: /schemas/types.yaml#/definitions/phandle required: - compatible diff --git a/Documentation/devicetree/bindings/rng/samsung,exynos4-rng.txt b/Documentation/devicetree/bindings/rng/samsung,exynos4-rng.txt deleted file mode 100644 index a13fbdb4bd88..000000000000 --- a/Documentation/devicetree/bindings/rng/samsung,exynos4-rng.txt +++ /dev/null @@ -1,19 +0,0 @@ -Exynos Pseudo Random Number Generator - -Required properties: - -- compatible : One of: - - "samsung,exynos4-rng" for Exynos4210 and Exynos4412 - - "samsung,exynos5250-prng" for Exynos5250+ -- reg : Specifies base physical address and size of the registers map. -- clocks : Phandle to clock-controller plus clock-specifier pair. -- clock-names : "secss" as a clock name. - -Example: - - rng@10830400 { - compatible = "samsung,exynos4-rng"; - reg = <0x10830400 0x200>; - clocks = <&clock CLK_SSS>; - clock-names = "secss"; - }; diff --git a/Documentation/devicetree/bindings/rng/samsung,exynos4-rng.yaml b/Documentation/devicetree/bindings/rng/samsung,exynos4-rng.yaml new file mode 100644 index 000000000000..3362cb1213c0 --- /dev/null +++ b/Documentation/devicetree/bindings/rng/samsung,exynos4-rng.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rng/samsung,exynos4-rng.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos SoC Pseudo Random Number Generator + +maintainers: + - Krzysztof Kozlowski <[email protected]> + +properties: + compatible: + enum: + - samsung,exynos4-rng # for Exynos4210 and Exynos4412 + - samsung,exynos5250-prng # for Exynos5250+ + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: secss + +required: + - compatible + - reg + - clock-names + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/exynos4.h> + + rng@10830400 { + compatible = "samsung,exynos4-rng"; + reg = <0x10830400 0x200>; + clocks = <&clock CLK_SSS>; + clock-names = "secss"; + }; diff --git a/Documentation/devicetree/bindings/rtc/renesas,sh-rtc.yaml b/Documentation/devicetree/bindings/rtc/renesas,sh-rtc.yaml new file mode 100644 index 000000000000..dcff573cbdb1 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/renesas,sh-rtc.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/renesas,sh-rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Real Time Clock for Renesas SH and ARM SoCs + +maintainers: + - Chris Brandt <[email protected]> + - Geert Uytterhoeven <[email protected]> + +properties: + compatible: + items: + - const: renesas,r7s72100-rtc # RZ/A1H + - const: renesas,sh-rtc + + reg: + maxItems: 1 + + interrupts: + maxItems: 3 + + interrupt-names: + items: + - const: alarm + - const: period + - const: carry + + clocks: + # The functional clock source for the RTC controller must be listed + # first (if it exists). Additionally, potential clock counting sources + # are to be listed. + minItems: 1 + maxItems: 4 + + clock-names: + # The functional clock must be labeled as "fck". Other clocks + # may be named in accordance to the SoC hardware manuals. + minItems: 1 + maxItems: 4 + items: + enum: [ fck, rtc_x1, rtc_x3, extal ] + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + +examples: + - | + #include <dt-bindings/clock/r7s72100-clock.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + + rtc: rtc@fcff1000 { + compatible = "renesas,r7s72100-rtc", "renesas,sh-rtc"; + reg = <0xfcff1000 0x2e>; + interrupts = <GIC_SPI 276 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 278 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "alarm", "period", "carry"; + clocks = <&mstp6_clks R7S72100_CLK_RTC>, <&rtc_x1_clk>, + <&rtc_x3_clk>, <&extal_clk>; + clock-names = "fck", "rtc_x1", "rtc_x3", "extal"; + }; diff --git a/Documentation/devicetree/bindings/rtc/rtc-sh.txt b/Documentation/devicetree/bindings/rtc/rtc-sh.txt deleted file mode 100644 index 7676c7d28874..000000000000 --- a/Documentation/devicetree/bindings/rtc/rtc-sh.txt +++ /dev/null @@ -1,28 +0,0 @@ -* Real Time Clock for Renesas SH and ARM SoCs - -Required properties: -- compatible: Should be "renesas,r7s72100-rtc" and "renesas,sh-rtc" as a - fallback. -- reg: physical base address and length of memory mapped region. -- interrupts: 3 interrupts for alarm, period, and carry. -- interrupt-names: The interrupts should be labeled as "alarm", "period", and - "carry". -- clocks: The functional clock source for the RTC controller must be listed - first (if exists). Additionally, potential clock counting sources are to be - listed. -- clock-names: The functional clock must be labeled as "fck". Other clocks - may be named in accordance to the SoC hardware manuals. - - -Example: -rtc: rtc@fcff1000 { - compatible = "renesas,r7s72100-rtc", "renesas,sh-rtc"; - reg = <0xfcff1000 0x2e>; - interrupts = <GIC_SPI 276 IRQ_TYPE_EDGE_RISING - GIC_SPI 277 IRQ_TYPE_EDGE_RISING - GIC_SPI 278 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "alarm", "period", "carry"; - clocks = <&mstp6_clks R7S72100_CLK_RTC>, <&rtc_x1_clk>, - <&rtc_x3_clk>, <&extal_clk>; - clock-names = "fck", "rtc_x1", "rtc_x3", "extal"; -}; diff --git a/Documentation/devicetree/bindings/rtc/s3c-rtc.txt b/Documentation/devicetree/bindings/rtc/s3c-rtc.txt deleted file mode 100644 index fdde63a5419c..000000000000 --- a/Documentation/devicetree/bindings/rtc/s3c-rtc.txt +++ /dev/null @@ -1,31 +0,0 @@ -* Samsung's S3C Real Time Clock controller - -Required properties: -- compatible: should be one of the following. - * "samsung,s3c2410-rtc" - for controllers compatible with s3c2410 rtc. - * "samsung,s3c2416-rtc" - for controllers compatible with s3c2416 rtc. - * "samsung,s3c2443-rtc" - for controllers compatible with s3c2443 rtc. - * "samsung,s3c6410-rtc" - for controllers compatible with s3c6410 rtc. - * "samsung,exynos3250-rtc" - (deprecated) for controllers compatible with - exynos3250 rtc (use "samsung,s3c6410-rtc"). -- reg: physical base address of the controller and length of memory mapped - region. -- interrupts: Two interrupt numbers to the cpu should be specified. First - interrupt number is the rtc alarm interrupt and second interrupt number - is the rtc tick interrupt. The number of cells representing a interrupt - depends on the parent interrupt controller. -- clocks: Must contain a list of phandle and clock specifier for the rtc - clock and in the case of a s3c6410 compatible controller, also - a source clock. -- clock-names: Must contain "rtc" and for a s3c6410 compatible controller, - a "rtc_src" sorted in the same order as the clocks property. - -Example: - - rtc@10070000 { - compatible = "samsung,s3c6410-rtc"; - reg = <0x10070000 0x100>; - interrupts = <44 0 45 0>; - clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>; - clock-names = "rtc", "rtc_src"; - }; diff --git a/Documentation/devicetree/bindings/rtc/s3c-rtc.yaml b/Documentation/devicetree/bindings/rtc/s3c-rtc.yaml new file mode 100644 index 000000000000..76bbf8b7555b --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/s3c-rtc.yaml @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/s3c-rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S3C, S5P and Exynos Real Time Clock controller + +maintainers: + - Krzysztof Kozlowski <[email protected]> + +properties: + compatible: + oneOf: + - enum: + - samsung,s3c2410-rtc + - samsung,s3c2416-rtc + - samsung,s3c2443-rtc + - samsung,s3c6410-rtc + - const: samsung,exynos3250-rtc + deprecated: true + + reg: + maxItems: 1 + + clocks: + description: + Must contain a list of phandle and clock specifier for the rtc + clock and in the case of a s3c6410 compatible controller, also + a source clock. + minItems: 1 + maxItems: 2 + + clock-names: + description: + Must contain "rtc" and for a s3c6410 compatible controller + also "rtc_src". + minItems: 1 + maxItems: 2 + + interrupts: + description: + Two interrupt numbers to the cpu should be specified. First + interrupt number is the rtc alarm interrupt and second interrupt number + is the rtc tick interrupt. The number of cells representing a interrupt + depends on the parent interrupt controller. + minItems: 2 + maxItems: 2 + +allOf: + - $ref: rtc.yaml# + - if: + properties: + compatible: + contains: + enum: + - samsung,s3c6410-rtc + - samsung,exynos3250-rtc + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: rtc + - const: rtc_src + else: + properties: + clocks: + minItems: 1 + maxItems: 1 + clock-names: + items: + - const: rtc + +examples: + - | + #include <dt-bindings/clock/exynos5420.h> + #include <dt-bindings/clock/samsung,s2mps11.h> + + rtc@10070000 { + compatible = "samsung,s3c6410-rtc"; + reg = <0x10070000 0x100>; + interrupts = <0 44 4>, <0 45 4>; + clocks = <&clock CLK_RTC>, + <&s2mps11_osc S2MPS11_CLK_AP>; + clock-names = "rtc", "rtc_src"; + }; diff --git a/Documentation/devicetree/bindings/serio/allwinner,sun4i-a10-ps2.yaml b/Documentation/devicetree/bindings/serio/allwinner,sun4i-a10-ps2.yaml new file mode 100644 index 000000000000..ee9712f1c97d --- /dev/null +++ b/Documentation/devicetree/bindings/serio/allwinner,sun4i-a10-ps2.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serio/allwinner,sun4i-a10-ps2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 PS2 Host Controller Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <[email protected]> + - Maxime Ripard <[email protected]> + +description: + A20 PS2 is dual role controller (PS2 host and PS2 device). These + bindings for PS2 A10/A20 host controller. IBM compliant IBM PS2 and + AT-compatible keyboard and mouse can be connected. + +properties: + compatible: + const: allwinner,sun4i-a10-ps2 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/sun7i-a20-ccu.h> + + ps20: ps2@1c2a000 { + compatible = "allwinner,sun4i-a10-ps2"; + reg = <0x01c2a000 0x400>; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_APB1_PS20>; + }; + +... diff --git a/Documentation/devicetree/bindings/serio/allwinner,sun4i-ps2.txt b/Documentation/devicetree/bindings/serio/allwinner,sun4i-ps2.txt deleted file mode 100644 index 75996b6111bb..000000000000 --- a/Documentation/devicetree/bindings/serio/allwinner,sun4i-ps2.txt +++ /dev/null @@ -1,22 +0,0 @@ -* Device tree bindings for Allwinner A10, A20 PS2 host controller - -A20 PS2 is dual role controller (PS2 host and PS2 device). These bindings are -for PS2 A10/A20 host controller. IBM compliant IBM PS2 and AT-compatible keyboard -and mouse can be connected. - -Required properties: - - - reg : Offset and length of the register set for the device. - - compatible : Should be as of the following: - - "allwinner,sun4i-a10-ps2" - - interrupts : The interrupt line connected to the PS2. - - clocks : The gate clk connected to the PS2. - - -Example: - ps20: ps2@01c2a000 { - compatible = "allwinner,sun4i-a10-ps2"; - reg = <0x01c2a000 0x400>; - interrupts = <0 62 4>; - clocks = <&apb1_gates 6>; - }; diff --git a/Documentation/devicetree/bindings/submitting-patches.txt b/Documentation/devicetree/bindings/submitting-patches.txt index de0d6090c0fd..98bee6240b65 100644 --- a/Documentation/devicetree/bindings/submitting-patches.txt +++ b/Documentation/devicetree/bindings/submitting-patches.txt @@ -15,17 +15,28 @@ I. For patch submitters use "Documentation" or "doc" because that is implied. All bindings are docs. Repeating "binding" again should also be avoided. - 2) Submit the entire series to the devicetree mailinglist at + 2) DT binding files are written in DT schema format using json-schema + vocabulary and YAML file format. The DT binding files must pass validation + by running: + + make dt_binding_check + + See ../writing-schema.rst for more details about schema and tools setup. + + 3) DT binding files should be dual licensed. The preferred license tag is + (GPL-2.0-only OR BSD-2-Clause). + + 4) Submit the entire series to the devicetree mailinglist at and Cc: the DT maintainers. Use scripts/get_maintainer.pl to identify all of the DT maintainers. - 3) The Documentation/ portion of the patch should come in the series before + 5) The Documentation/ portion of the patch should come in the series before the code implementing the binding. - 4) Any compatible strings used in a chip or board DTS file must be + 6) Any compatible strings used in a chip or board DTS file must be previously documented in the corresponding DT binding text file in Documentation/devicetree/bindings. This rule applies even if the Linux device driver does not yet match on the compatible @@ -33,7 +44,7 @@ I. For patch submitters followed as of commit bff5da4335256513497cc8c79f9a9d1665e09864 ("checkpatch: add DT compatible string documentation checks"). ] - 5) The wildcard "<chip>" may be used in compatible strings, as in + 7) The wildcard "<chip>" may be used in compatible strings, as in the following example: - compatible: Must contain '"nvidia,<chip>-pcie", @@ -42,7 +53,7 @@ I. For patch submitters As in the above example, the known values of "<chip>" should be documented if it is used. - 6) If a documented compatible string is not yet matched by the + 8) If a documented compatible string is not yet matched by the driver, the documentation should also include a compatible string that is matched by the driver (as in the "nvidia,tegra20-pcie" example above). diff --git a/Documentation/devicetree/bindings/thermal/st,stm32-thermal.yaml b/Documentation/devicetree/bindings/thermal/st,stm32-thermal.yaml new file mode 100644 index 000000000000..c0f59c56003d --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/st,stm32-thermal.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/st,stm32-thermal.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32 digital thermal sensor (DTS) binding + +maintainers: + - David Hernandez Sanchez <[email protected]> + +properties: + compatible: + const: st,stm32-thermal + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: pclk + + "#thermal-sensor-cells": + const: 0 + +required: + - "#thermal-sensor-cells" + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/stm32mp1-clks.h> + dts: thermal@50028000 { + compatible = "st,stm32-thermal"; + reg = <0x50028000 0x100>; + clocks = <&rcc TMPSENS>; + clock-names = "pclk"; + #thermal-sensor-cells = <0>; + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&dts>; + trips { + cpu_alert1: cpu-alert1 { + temperature = <85000>; + hysteresis = <0>; + type = "passive"; + }; + + cpu_crit: cpu-crit { + temperature = <120000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/thermal/stm32-thermal.txt b/Documentation/devicetree/bindings/thermal/stm32-thermal.txt deleted file mode 100644 index 8c0d5a4d8031..000000000000 --- a/Documentation/devicetree/bindings/thermal/stm32-thermal.txt +++ /dev/null @@ -1,61 +0,0 @@ -Binding for Thermal Sensor for STMicroelectronics STM32 series of SoCs. - -On STM32 SoCs, the Digital Temperature Sensor (DTS) is in charge of managing an -analog block which delivers a frequency depending on the internal SoC's -temperature. By using a reference frequency, DTS is able to provide a sample -number which can be translated into a temperature by the user. - -DTS provides interrupt notification mechanism by threshold. This mechanism -offers two temperature trip points: passive and critical. The first is intended -for passive cooling notification while the second is used for over-temperature -reset. - -Required parameters: -------------------- - -compatible: Should be "st,stm32-thermal" -reg: This should be the physical base address and length of the - sensor's registers. -clocks: Phandle of the clock used by the thermal sensor. - See: Documentation/devicetree/bindings/clock/clock-bindings.txt -clock-names: Should be "pclk" for register access clock and reference clock. - See: Documentation/devicetree/bindings/resource-names.txt -#thermal-sensor-cells: Should be 0. See ./thermal.txt for a description. -interrupts: Standard way to define interrupt number. - -Example: - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = <&thermal>; - - trips { - cpu_alert1: cpu-alert1 { - temperature = <85000>; - hysteresis = <0>; - type = "passive"; - }; - - cpu-crit: cpu-crit { - temperature = <120000>; - hysteresis = <0>; - type = "critical"; - }; - }; - - cooling-maps { - }; - }; - }; - - thermal: thermal@50028000 { - compatible = "st,stm32-thermal"; - reg = <0x50028000 0x100>; - clocks = <&rcc TMPSENS>; - clock-names = "pclk"; - #thermal-sensor-cells = <0>; - interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; - }; diff --git a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt deleted file mode 100644 index 8f78640ad64c..000000000000 --- a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt +++ /dev/null @@ -1,88 +0,0 @@ -Samsung's Multi Core Timer (MCT) - -The Samsung's Multi Core Timer (MCT) module includes two main blocks, the -global timer and CPU local timers. The global timer is a 64-bit free running -up-counter and can generate 4 interrupts when the counter reaches one of the -four preset counter values. The CPU local timers are 32-bit free running -down-counters and generate an interrupt when the counter expires. There is -one CPU local timer instantiated in MCT for every CPU in the system. - -Required properties: - -- compatible: should be "samsung,exynos4210-mct". - (a) "samsung,exynos4210-mct", for mct compatible with Exynos4210 mct. - (b) "samsung,exynos4412-mct", for mct compatible with Exynos4412 mct. - -- reg: base address of the mct controller and length of the address space - it occupies. - -- interrupts: the list of interrupts generated by the controller. The following - should be the order of the interrupts specified. The local timer interrupts - should be specified after the four global timer interrupts have been - specified. - - 0: Global Timer Interrupt 0 - 1: Global Timer Interrupt 1 - 2: Global Timer Interrupt 2 - 3: Global Timer Interrupt 3 - 4: Local Timer Interrupt 0 - 5: Local Timer Interrupt 1 - 6: .. - 7: .. - i: Local Timer Interrupt n - - For MCT block that uses a per-processor interrupt for local timers, such - as ones compatible with "samsung,exynos4412-mct", only one local timer - interrupt might be specified, meaning that all local timers use the same - per processor interrupt. - -Example 1: In this example, the IP contains two local timers, using separate - interrupts, so two local timer interrupts have been specified, - in addition to four global timer interrupts. - - mct@10050000 { - compatible = "samsung,exynos4210-mct"; - reg = <0x10050000 0x800>; - interrupts = <0 57 0>, <0 69 0>, <0 70 0>, <0 71 0>, - <0 42 0>, <0 48 0>; - }; - -Example 2: In this example, the timer interrupts are connected to two separate - interrupt controllers. Hence, an interrupt-map is created to map - the interrupts to the respective interrupt controllers. - - mct@101c0000 { - compatible = "samsung,exynos4210-mct"; - reg = <0x101C0000 0x800>; - interrupt-parent = <&mct_map>; - interrupts = <0>, <1>, <2>, <3>, <4>, <5>; - - mct_map: mct-map { - #interrupt-cells = <1>; - #address-cells = <0>; - #size-cells = <0>; - interrupt-map = <0 &gic 0 57 0>, - <1 &gic 0 69 0>, - <2 &combiner 12 6>, - <3 &combiner 12 7>, - <4 &gic 0 42 0>, - <5 &gic 0 48 0>; - }; - }; - -Example 3: In this example, the IP contains four local timers, but using - a per-processor interrupt to handle them. Either all the local - timer interrupts can be specified, with the same interrupt specifier - value or just the first one. - - mct@10050000 { - compatible = "samsung,exynos4412-mct"; - reg = <0x10050000 0x800>; - - /* Both ways are possible in this case. Either: */ - interrupts = <0 57 0>, <0 69 0>, <0 70 0>, <0 71 0>, - <0 42 0>; - /* or: */ - interrupts = <0 57 0>, <0 69 0>, <0 70 0>, <0 71 0>, - <0 42 0>, <0 42 0>, <0 42 0>, <0 42 0>; - }; diff --git a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml new file mode 100644 index 000000000000..273e359854dd --- /dev/null +++ b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml @@ -0,0 +1,124 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/samsung,exynos4210-mct.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos SoC Multi Core Timer (MCT) + +maintainers: + - Krzysztof Kozlowski <[email protected]> + +description: |+ + The Samsung's Multi Core Timer (MCT) module includes two main blocks, the + global timer and CPU local timers. The global timer is a 64-bit free running + up-counter and can generate 4 interrupts when the counter reaches one of the + four preset counter values. The CPU local timers are 32-bit free running + down-counters and generate an interrupt when the counter expires. There is + one CPU local timer instantiated in MCT for every CPU in the system. + +properties: + compatible: + enum: + - samsung,exynos4210-mct + - samsung,exynos4412-mct + + reg: + maxItems: 1 + + interrupts: + description: | + Interrupts should be put in specific order. This is, the local timer + interrupts should be specified after the four global timer interrupts + have been specified: + 0: Global Timer Interrupt 0 + 1: Global Timer Interrupt 1 + 2: Global Timer Interrupt 2 + 3: Global Timer Interrupt 3 + 4: Local Timer Interrupt 0 + 5: Local Timer Interrupt 1 + 6: .. + 7: .. + i: Local Timer Interrupt n + For MCT block that uses a per-processor interrupt for local timers, such + as ones compatible with "samsung,exynos4412-mct", only one local timer + interrupt might be specified, meaning that all local timers use the same + per processor interrupt. + minItems: 5 # 4 Global + 1 local + maxItems: 20 # 4 Global + 16 local + +required: + - compatible + - interrupts + - reg + +examples: + - | + // In this example, the IP contains two local timers, using separate + // interrupts, so two local timer interrupts have been specified, + // in addition to four global timer interrupts. + #include <dt-bindings/interrupt-controller/arm-gic.h> + + timer@10050000 { + compatible = "samsung,exynos4210-mct"; + reg = <0x10050000 0x800>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + }; + + - | + // In this example, the timer interrupts are connected to two separate + // interrupt controllers. Hence, an interrupts-extended is needed. + #include <dt-bindings/interrupt-controller/arm-gic.h> + + timer@101c0000 { + compatible = "samsung,exynos4210-mct"; + reg = <0x101C0000 0x800>; + interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, + <&combiner 12 6>, + <&combiner 12 7>, + <&gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + }; + + - | + // In this example, the IP contains four local timers, but using + // a per-processor interrupt to handle them. Only one first local + // interrupt is specified. + #include <dt-bindings/interrupt-controller/arm-gic.h> + + timer@10050000 { + compatible = "samsung,exynos4412-mct"; + reg = <0x10050000 0x800>; + + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>; + }; + + - | + // In this example, the IP contains four local timers, but using + // a per-processor interrupt to handle them. All the local timer + // interrupts are specified. + #include <dt-bindings/interrupt-controller/arm-gic.h> + + timer@10050000 { + compatible = "samsung,exynos4412-mct"; + reg = <0x10050000 0x800>; + + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>; + }; diff --git a/Documentation/devicetree/bindings/timer/st,stm32-timer.txt b/Documentation/devicetree/bindings/timer/st,stm32-timer.txt deleted file mode 100644 index 8ef28e70d6e8..000000000000 --- a/Documentation/devicetree/bindings/timer/st,stm32-timer.txt +++ /dev/null @@ -1,22 +0,0 @@ -. STMicroelectronics STM32 timer - -The STM32 MCUs family has several general-purpose 16 and 32 bits timers. - -Required properties: -- compatible : Should be "st,stm32-timer" -- reg : Address and length of the register set -- clocks : Reference on the timer input clock -- interrupts : Reference to the timer interrupt - -Optional properties: -- resets: Reference to a reset controller asserting the timer - -Example: - -timer5: timer@40000c00 { - compatible = "st,stm32-timer"; - reg = <0x40000c00 0x400>; - interrupts = <50>; - resets = <&rrc 259>; - clocks = <&clk_pmtr1>; -}; diff --git a/Documentation/devicetree/bindings/timer/st,stm32-timer.yaml b/Documentation/devicetree/bindings/timer/st,stm32-timer.yaml new file mode 100644 index 000000000000..176aa3c9baf8 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/st,stm32-timer.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/st,stm32-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32 general-purpose 16 and 32 bits timers bindings + +maintainers: + - Benjamin Gaignard <[email protected]> + +properties: + compatible: + const: st,stm32-timer + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/stm32mp1-clks.h> + timer: timer@40000c00 { + compatible = "st,stm32-timer"; + reg = <0x40000c00 0x400>; + interrupts = <50>; + clocks = <&clk_pmtr1>; + }; + +... diff --git a/Documentation/devicetree/bindings/usb/generic-ehci.yaml b/Documentation/devicetree/bindings/usb/generic-ehci.yaml index 059f6ef1ad4a..ce8854bc8c84 100644 --- a/Documentation/devicetree/bindings/usb/generic-ehci.yaml +++ b/Documentation/devicetree/bindings/usb/generic-ehci.yaml @@ -63,6 +63,11 @@ properties: description: Set this flag to force EHCI reset after resume. + companion: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle of a companion. + phys: true required: diff --git a/Documentation/devicetree/bindings/watchdog/amlogic,meson-gxbb-wdt.yaml b/Documentation/devicetree/bindings/watchdog/amlogic,meson-gxbb-wdt.yaml index d7352f709b37..4ddae6feef3b 100644 --- a/Documentation/devicetree/bindings/watchdog/amlogic,meson-gxbb-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/amlogic,meson-gxbb-wdt.yaml @@ -10,6 +10,9 @@ title: Meson GXBB SoCs Watchdog timer maintainers: - Neil Armstrong <[email protected]> +allOf: + - $ref: watchdog.yaml# + properties: compatible: enum: diff --git a/Documentation/devicetree/bindings/watchdog/renesas,wdt.txt b/Documentation/devicetree/bindings/watchdog/renesas,wdt.txt index 9f365c1a3399..a5bf04dba410 100644 --- a/Documentation/devicetree/bindings/watchdog/renesas,wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/renesas,wdt.txt @@ -10,6 +10,7 @@ Required properties: - "renesas,r8a7745-wdt" (RZ/G1E) - "renesas,r8a77470-wdt" (RZ/G1C) - "renesas,r8a774a1-wdt" (RZ/G2M) + - "renesas,r8a774b1-wdt" (RZ/G2N) - "renesas,r8a774c0-wdt" (RZ/G2E) - "renesas,r8a7790-wdt" (R-Car H2) - "renesas,r8a7791-wdt" (R-Car M2-W) diff --git a/Documentation/devicetree/bindings/watchdog/samsung-wdt.txt b/Documentation/devicetree/bindings/watchdog/samsung-wdt.txt deleted file mode 100644 index 46dcb48e75b4..000000000000 --- a/Documentation/devicetree/bindings/watchdog/samsung-wdt.txt +++ /dev/null @@ -1,35 +0,0 @@ -* Samsung's Watchdog Timer Controller - -The Samsung's Watchdog controller is used for resuming system operation -after a preset amount of time during which the WDT reset event has not -occurred. - -Required properties: -- compatible : should be one among the following - - "samsung,s3c2410-wdt" for S3C2410 - - "samsung,s3c6410-wdt" for S3C6410, S5PV210 and Exynos4 - - "samsung,exynos5250-wdt" for Exynos5250 - - "samsung,exynos5420-wdt" for Exynos5420 - - "samsung,exynos7-wdt" for Exynos7 - -- reg : base physical address of the controller and length of memory mapped - region. -- interrupts : interrupt number to the cpu. -- samsung,syscon-phandle : reference to syscon node (This property required only - in case of compatible being "samsung,exynos5250-wdt" or "samsung,exynos5420-wdt". - In case of Exynos5250 and 5420 this property points to syscon node holding the PMU - base address) - -Optional properties: -- timeout-sec : contains the watchdog timeout in seconds. - -Example: - -watchdog@101d0000 { - compatible = "samsung,exynos5250-wdt"; - reg = <0x101D0000 0x100>; - interrupts = <0 42 0>; - clocks = <&clock 336>; - clock-names = "watchdog"; - samsung,syscon-phandle = <&pmu_syscon>; -}; diff --git a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml new file mode 100644 index 000000000000..2fa40d8864b2 --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/samsung-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung SoC Watchdog Timer Controller + +maintainers: + - Krzysztof Kozlowski <[email protected]> + +description: |+ + The Samsung's Watchdog controller is used for resuming system operation + after a preset amount of time during which the WDT reset event has not + occurred. + +properties: + compatible: + enum: + - samsung,s3c2410-wdt # for S3C2410 + - samsung,s3c6410-wdt # for S3C6410, S5PV210 and Exynos4 + - samsung,exynos5250-wdt # for Exynos5250 + - samsung,exynos5420-wdt # for Exynos5420 + - samsung,exynos7-wdt # for Exynos7 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: watchdog + + interrupts: + maxItems: 1 + + samsung,syscon-phandle: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the PMU system controller node (in case of Exynos5250 + and Exynos5420). + +required: + - compatible + - clocks + - clock-names + - interrupts + - reg + +allOf: + - $ref: watchdog.yaml# + - if: + properties: + compatible: + contains: + enum: + - samsung,exynos5250-wdt + - samsung,exynos5420-wdt + then: + required: + - samsung,syscon-phandle + +examples: + - | + watchdog@101d0000 { + compatible = "samsung,exynos5250-wdt"; + reg = <0x101D0000 0x100>; + interrupts = <0 42 0>; + clocks = <&clock 336>; + clock-names = "watchdog"; + samsung,syscon-phandle = <&pmu_syscon>; + }; diff --git a/Documentation/devicetree/writing-schema.rst b/Documentation/devicetree/writing-schema.rst index f4a638072262..3fce61cfd649 100644 --- a/Documentation/devicetree/writing-schema.rst +++ b/Documentation/devicetree/writing-schema.rst @@ -117,6 +117,9 @@ project can be installed with pip:: pip3 install git+https://github.com/devicetree-org/dt-schema.git@master +Several executables (dt-doc-validate, dt-mk-schema, dt-validate) will be +installed. Ensure they are in your PATH (~/.local/bin by default). + dtc must also be built with YAML output support enabled. This requires that libyaml and its headers be installed on the host system. diff --git a/MAINTAINERS b/MAINTAINERS index 296de2b51c83..03302605a0a6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2699,7 +2699,7 @@ M: Bartosz Golaszewski <[email protected]> T: git git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux.git S: Maintained -F: Documentation/devicetree/bindings/eeprom/at24.txt +F: Documentation/devicetree/bindings/eeprom/at24.yaml F: drivers/misc/eeprom/at24.c ATA OVER ETHERNET (AOE) DRIVER @@ -14212,7 +14212,7 @@ L: [email protected] S: Maintained F: drivers/crypto/exynos-rng.c -F: Documentation/devicetree/bindings/rng/samsung,exynos4-rng.txt +F: Documentation/devicetree/bindings/rng/samsung,exynos4-rng.yaml SAMSUNG EXYNOS TRUE RANDOM NUMBER GENERATOR (TRNG) DRIVER M: Łukasz Stelmach <[email protected]> @@ -14287,8 +14287,8 @@ M: Kamil Konieczny <[email protected]> S: Maintained -F: Documentation/devicetree/bindings/crypto/samsung-slimsss.txt -F: Documentation/devicetree/bindings/crypto/samsung-sss.txt +F: Documentation/devicetree/bindings/crypto/samsung-slimsss.yaml +F: Documentation/devicetree/bindings/crypto/samsung-sss.yaml F: drivers/crypto/s5p-sss.c SAMSUNG S5P/EXYNOS4 SOC SERIES CAMERA SUBSYSTEM DRIVERS diff --git a/drivers/of/address.c b/drivers/of/address.c index 978427a9d5e6..99c1b8058559 100644 --- a/drivers/of/address.c +++ b/drivers/of/address.c @@ -14,6 +14,8 @@ #include <linux/slab.h> #include <linux/string.h> +#include "of_private.h" + /* Max address size we deal with */ #define OF_MAX_ADDR_CELLS 4 #define OF_CHECK_ADDR_COUNT(na) ((na) > 0 && (na) <= OF_MAX_ADDR_CELLS) @@ -241,6 +243,7 @@ static int parser_init(struct of_pci_range_parser *parser, parser->node = node; parser->pna = of_n_addr_cells(node); parser->np = parser->pna + na + ns; + parser->dma = !strcmp(name, "dma-ranges"); parser->range = of_get_property(node, name, &rlen); if (parser->range == NULL) @@ -279,7 +282,11 @@ struct of_pci_range *of_pci_range_parser_one(struct of_pci_range_parser *parser, range->pci_space = be32_to_cpup(parser->range); range->flags = of_bus_pci_get_flags(parser->range); range->pci_addr = of_read_number(parser->range + 1, ns); - range->cpu_addr = of_translate_address(parser->node, + if (parser->dma) + range->cpu_addr = of_translate_dma_address(parser->node, + parser->range + na); + else + range->cpu_addr = of_translate_address(parser->node, parser->range + na); range->size = of_read_number(parser->range + parser->pna + na, ns); @@ -292,8 +299,12 @@ struct of_pci_range *of_pci_range_parser_one(struct of_pci_range_parser *parser, flags = of_bus_pci_get_flags(parser->range); pci_addr = of_read_number(parser->range + 1, ns); - cpu_addr = of_translate_address(parser->node, - parser->range + na); + if (parser->dma) + cpu_addr = of_translate_dma_address(parser->node, + parser->range + na); + else + cpu_addr = of_translate_address(parser->node, + parser->range + na); size = of_read_number(parser->range + parser->pna + na, ns); if (flags != range->flags) @@ -517,9 +528,13 @@ static int of_translate_one(struct device_node *parent, struct of_bus *bus, * * As far as we know, this damage only exists on Apple machines, so * This code is only enabled on powerpc. --gcl + * + * This quirk also applies for 'dma-ranges' which frequently exist in + * child nodes without 'dma-ranges' in the parent nodes. --RobH */ ranges = of_get_property(parent, rprop, &rlen); - if (ranges == NULL && !of_empty_ranges_quirk(parent)) { + if (ranges == NULL && !of_empty_ranges_quirk(parent) && + strcmp(rprop, "dma-ranges")) { pr_debug("no ranges; cannot translate\n"); return 1; } @@ -695,6 +710,16 @@ static struct device_node *__of_get_dma_parent(const struct device_node *np) return of_node_get(args.np); } +static struct device_node *of_get_next_dma_parent(struct device_node *np) +{ + struct device_node *parent; + + parent = __of_get_dma_parent(np); + of_node_put(np); + + return parent; +} + u64 of_translate_dma_address(struct device_node *dev, const __be32 *in_addr) { struct device_node *host; @@ -826,25 +851,6 @@ int of_address_to_resource(struct device_node *dev, int index, } EXPORT_SYMBOL_GPL(of_address_to_resource); -struct device_node *of_find_matching_node_by_address(struct device_node *from, - const struct of_device_id *matches, - u64 base_address) -{ - struct device_node *dn = of_find_matching_node(from, matches); - struct resource res; - - while (dn) { - if (!of_address_to_resource(dn, 0, &res) && - res.start == base_address) - return dn; - - dn = of_find_matching_node(dn, matches); - } - - return NULL; -} - - /** * of_iomap - Maps the memory mapped IO for a given device_node * @device: the device whose io range will be mapped @@ -924,47 +930,39 @@ int of_dma_get_range(struct device_node *np, u64 *dma_addr, u64 *paddr, u64 *siz const __be32 *ranges = NULL; int len, naddr, nsize, pna; int ret = 0; + bool found_dma_ranges = false; u64 dmaaddr; - if (!node) - return -EINVAL; - - while (1) { - struct device_node *parent; - - naddr = of_n_addr_cells(node); - nsize = of_n_size_cells(node); - - parent = __of_get_dma_parent(node); - of_node_put(node); - - node = parent; - if (!node) - break; - + while (node) { ranges = of_get_property(node, "dma-ranges", &len); /* Ignore empty ranges, they imply no translation required */ if (ranges && len > 0) break; - /* - * At least empty ranges has to be defined for parent node if - * DMA is supported - */ - if (!ranges) - break; + /* Once we find 'dma-ranges', then a missing one is an error */ + if (found_dma_ranges && !ranges) { + ret = -ENODEV; + goto out; + } + found_dma_ranges = true; + + node = of_get_next_dma_parent(node); } - if (!ranges) { + if (!node || !ranges) { pr_debug("no dma-ranges found for node(%pOF)\n", np); ret = -ENODEV; goto out; } - len /= sizeof(u32); - + naddr = of_bus_n_addr_cells(node); + nsize = of_bus_n_size_cells(node); pna = of_n_addr_cells(node); + if ((len / sizeof(__be32)) % (pna + naddr + nsize)) { + ret = -EINVAL; + goto out; + } /* dma-ranges format: * DMA addr : naddr cells @@ -972,10 +970,10 @@ int of_dma_get_range(struct device_node *np, u64 *dma_addr, u64 *paddr, u64 *siz * size : nsize cells */ dmaaddr = of_read_number(ranges, naddr); - *paddr = of_translate_dma_address(np, ranges); + *paddr = of_translate_dma_address(node, ranges + naddr); if (*paddr == OF_BAD_ADDR) { - pr_err("translation of DMA address(%pad) to CPU address failed node(%pOF)\n", - dma_addr, np); + pr_err("translation of DMA address(%llx) to CPU address failed node(%pOF)\n", + dmaaddr, np); ret = -EINVAL; goto out; } @@ -991,7 +989,6 @@ out: return ret; } -EXPORT_SYMBOL_GPL(of_dma_get_range); /** * of_dma_is_coherent - Check if device is coherent @@ -1009,7 +1006,7 @@ bool of_dma_is_coherent(struct device_node *np) of_node_put(node); return true; } - node = of_get_next_parent(node); + node = of_get_next_dma_parent(node); } of_node_put(node); return false; diff --git a/drivers/of/base.c b/drivers/of/base.c index 1d667eb730e1..db7fbc0c0893 100644 --- a/drivers/of/base.c +++ b/drivers/of/base.c @@ -86,34 +86,46 @@ static bool __of_node_is_type(const struct device_node *np, const char *type) return np && match && type && !strcmp(match, type); } -int of_n_addr_cells(struct device_node *np) +int of_bus_n_addr_cells(struct device_node *np) { u32 cells; - do { - if (np->parent) - np = np->parent; + for (; np; np = np->parent) if (!of_property_read_u32(np, "#address-cells", &cells)) return cells; - } while (np->parent); + /* No #address-cells property for the root node */ return OF_ROOT_NODE_ADDR_CELLS_DEFAULT; } + +int of_n_addr_cells(struct device_node *np) +{ + if (np->parent) + np = np->parent; + + return of_bus_n_addr_cells(np); +} EXPORT_SYMBOL(of_n_addr_cells); -int of_n_size_cells(struct device_node *np) +int of_bus_n_size_cells(struct device_node *np) { u32 cells; - do { - if (np->parent) - np = np->parent; + for (; np; np = np->parent) if (!of_property_read_u32(np, "#size-cells", &cells)) return cells; - } while (np->parent); + /* No #size-cells property for the root node */ return OF_ROOT_NODE_SIZE_CELLS_DEFAULT; } + +int of_n_size_cells(struct device_node *np) +{ + if (np->parent) + np = np->parent; + + return of_bus_n_size_cells(np); +} EXPORT_SYMBOL(of_n_size_cells); #ifdef CONFIG_NUMA diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c index 223d617ecfe1..d01d834b26b0 100644 --- a/drivers/of/fdt.c +++ b/drivers/of/fdt.c @@ -947,8 +947,8 @@ int __init early_init_dt_scan_chosen_stdout(void) if (fdt_node_check_compatible(fdt, offset, match->compatible)) continue; - of_setup_earlycon(match, offset, options); - return 0; + if (of_setup_earlycon(match, offset, options) == 0) + return 0; } return -ENODEV; } diff --git a/drivers/of/of_private.h b/drivers/of/of_private.h index 24786818e32e..66294d29942a 100644 --- a/drivers/of/of_private.h +++ b/drivers/of/of_private.h @@ -158,4 +158,18 @@ extern void __of_sysfs_remove_bin_file(struct device_node *np, #define for_each_transaction_entry_reverse(_oft, _te) \ list_for_each_entry_reverse(_te, &(_oft)->te_list, node) +extern int of_bus_n_addr_cells(struct device_node *np); +extern int of_bus_n_size_cells(struct device_node *np); + +#ifdef CONFIG_OF_ADDRESS +extern int of_dma_get_range(struct device_node *np, u64 *dma_addr, + u64 *paddr, u64 *size); +#else +static inline int of_dma_get_range(struct device_node *np, u64 *dma_addr, + u64 *paddr, u64 *size) +{ + return -ENODEV; +} +#endif + #endif /* _LINUX_OF_PRIVATE_H */ diff --git a/drivers/of/unittest-data/testcases.dts b/drivers/of/unittest-data/testcases.dts index 55fe0ee20109..a85b5e1c381a 100644 --- a/drivers/of/unittest-data/testcases.dts +++ b/drivers/of/unittest-data/testcases.dts @@ -15,5 +15,6 @@ #include "tests-phandle.dtsi" #include "tests-interrupts.dtsi" #include "tests-match.dtsi" +#include "tests-address.dtsi" #include "tests-platform.dtsi" #include "tests-overlay.dtsi" diff --git a/drivers/of/unittest-data/tests-address.dtsi b/drivers/of/unittest-data/tests-address.dtsi new file mode 100644 index 000000000000..3fe5d3987beb --- /dev/null +++ b/drivers/of/unittest-data/tests-address.dtsi @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + #address-cells = <1>; + #size-cells = <1>; + + testcase-data { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + address-tests { + #address-cells = <1>; + #size-cells = <1>; + /* ranges here is to make sure we don't use it for + * dma-ranges translation */ + ranges = <0x70000000 0x70000000 0x40000000>, + <0x00000000 0xd0000000 0x20000000>; + dma-ranges = <0x0 0x20000000 0x40000000>; + + device@70000000 { + reg = <0x70000000 0x1000>; + }; + + bus@80000000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x80000000 0x100000>; + dma-ranges = <0x10000000 0x0 0x40000000>; + + device@1000 { + reg = <0x1000 0x1000>; + }; + }; + + pci@90000000 { + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0x90000000 0x1000>; + ranges = <0x42000000 0x0 0x40000000 0x40000000 0x0 0x10000000>; + dma-ranges = <0x42000000 0x0 0x80000000 0x00000000 0x0 0x10000000>, + <0x42000000 0x0 0xc0000000 0x20000000 0x0 0x10000000>; + }; + + }; + }; +}; diff --git a/drivers/of/unittest.c b/drivers/of/unittest.c index 92e895d86458..445f134b62c0 100644 --- a/drivers/of/unittest.c +++ b/drivers/of/unittest.c @@ -12,6 +12,7 @@ #include <linux/hashtable.h> #include <linux/libfdt.h> #include <linux/of.h> +#include <linux/of_address.h> #include <linux/of_fdt.h> #include <linux/of_irq.h> #include <linux/of_platform.h> @@ -779,6 +780,95 @@ static void __init of_unittest_changeset(void) #endif } +static void __init of_unittest_dma_ranges_one(const char *path, + u64 expect_dma_addr, u64 expect_paddr, u64 expect_size) +{ + struct device_node *np; + u64 dma_addr, paddr, size; + int rc; + + np = of_find_node_by_path(path); + if (!np) { + pr_err("missing testcase data\n"); + return; + } + + rc = of_dma_get_range(np, &dma_addr, &paddr, &size); + + unittest(!rc, "of_dma_get_range failed on node %pOF rc=%i\n", np, rc); + if (!rc) { + unittest(size == expect_size, + "of_dma_get_range wrong size on node %pOF size=%llx\n", np, size); + unittest(paddr == expect_paddr, + "of_dma_get_range wrong phys addr (%llx) on node %pOF", paddr, np); + unittest(dma_addr == expect_dma_addr, + "of_dma_get_range wrong DMA addr (%llx) on node %pOF", dma_addr, np); + } + of_node_put(np); +} + +static void __init of_unittest_parse_dma_ranges(void) +{ + of_unittest_dma_ranges_one("/testcase-data/address-tests/device@70000000", + 0x0, 0x20000000, 0x40000000); + of_unittest_dma_ranges_one("/testcase-data/address-tests/bus@80000000/device@1000", + 0x10000000, 0x20000000, 0x40000000); + of_unittest_dma_ranges_one("/testcase-data/address-tests/pci@90000000", + 0x80000000, 0x20000000, 0x10000000); +} + +static void __init of_unittest_pci_dma_ranges(void) +{ + struct device_node *np; + struct of_pci_range range; + struct of_pci_range_parser parser; + int i = 0; + + if (!IS_ENABLED(CONFIG_PCI)) + return; + + np = of_find_node_by_path("/testcase-data/address-tests/pci@90000000"); + if (!np) { + pr_err("missing testcase data\n"); + return; + } + + if (of_pci_dma_range_parser_init(&parser, np)) { + pr_err("missing dma-ranges property\n"); + return; + } + + /* + * Get the dma-ranges from the device tree + */ + for_each_of_pci_range(&parser, &range) { + if (!i) { + unittest(range.size == 0x10000000, + "for_each_of_pci_range wrong size on node %pOF size=%llx\n", + np, range.size); + unittest(range.cpu_addr == 0x20000000, + "for_each_of_pci_range wrong CPU addr (%llx) on node %pOF", + range.cpu_addr, np); + unittest(range.pci_addr == 0x80000000, + "for_each_of_pci_range wrong DMA addr (%llx) on node %pOF", + range.pci_addr, np); + } else { + unittest(range.size == 0x10000000, + "for_each_of_pci_range wrong size on node %pOF size=%llx\n", + np, range.size); + unittest(range.cpu_addr == 0x40000000, + "for_each_of_pci_range wrong CPU addr (%llx) on node %pOF", + range.cpu_addr, np); + unittest(range.pci_addr == 0xc0000000, + "for_each_of_pci_range wrong DMA addr (%llx) on node %pOF", + range.pci_addr, np); + } + i++; + } + + of_node_put(np); +} + static void __init of_unittest_parse_interrupts(void) { struct device_node *np; @@ -2555,6 +2645,8 @@ static int __init of_unittest(void) of_unittest_changeset(); of_unittest_parse_interrupts(); of_unittest_parse_interrupts_extended(); + of_unittest_parse_dma_ranges(); + of_unittest_pci_dma_ranges(); of_unittest_match_node(); of_unittest_platform_populate(); of_unittest_overlay(); diff --git a/include/dt-bindings/sound/samsung-i2s.h b/include/dt-bindings/sound/samsung-i2s.h index 77545f14c379..250de0d6c734 100644 --- a/include/dt-bindings/sound/samsung-i2s.h +++ b/include/dt-bindings/sound/samsung-i2s.h @@ -2,8 +2,14 @@ #ifndef _DT_BINDINGS_SAMSUNG_I2S_H #define _DT_BINDINGS_SAMSUNG_I2S_H -#define CLK_I2S_CDCLK 0 -#define CLK_I2S_RCLK_SRC 1 -#define CLK_I2S_RCLK_PSR 2 +#define CLK_I2S_CDCLK 0 /* the CDCLK (CODECLKO) gate clock */ + +#define CLK_I2S_RCLK_SRC 1 /* the RCLKSRC mux clock (corresponding to + * RCLKSRC bit in IISMOD register) + */ + +#define CLK_I2S_RCLK_PSR 2 /* the RCLK prescaler divider clock + * (corresponding to the IISPSR register) + */ #endif /* _DT_BINDINGS_SAMSUNG_I2S_H */ diff --git a/include/linux/libfdt_env.h b/include/linux/libfdt_env.h index edb0f0c30904..2231eb855e8f 100644 --- a/include/linux/libfdt_env.h +++ b/include/linux/libfdt_env.h @@ -2,7 +2,7 @@ #ifndef LIBFDT_ENV_H #define LIBFDT_ENV_H -#include <linux/kernel.h> /* For INT_MAX */ +#include <linux/limits.h> /* For INT_MAX */ #include <linux/string.h> #include <asm/byteorder.h> diff --git a/include/linux/of_address.h b/include/linux/of_address.h index 30e40fb6936b..eac7ab109df4 100644 --- a/include/linux/of_address.h +++ b/include/linux/of_address.h @@ -12,6 +12,7 @@ struct of_pci_range_parser { const __be32 *end; int np; int pna; + bool dma; }; struct of_pci_range { @@ -33,10 +34,6 @@ extern u64 of_translate_dma_address(struct device_node *dev, extern u64 of_translate_address(struct device_node *np, const __be32 *addr); extern int of_address_to_resource(struct device_node *dev, int index, struct resource *r); -extern struct device_node *of_find_matching_node_by_address( - struct device_node *from, - const struct of_device_id *matches, - u64 base_address); extern void __iomem *of_iomap(struct device_node *device, int index); void __iomem *of_io_request_and_map(struct device_node *device, int index, const char *name); @@ -55,8 +52,6 @@ extern int of_pci_dma_range_parser_init(struct of_pci_range_parser *parser, extern struct of_pci_range *of_pci_range_parser_one( struct of_pci_range_parser *parser, struct of_pci_range *range); -extern int of_dma_get_range(struct device_node *np, u64 *dma_addr, - u64 *paddr, u64 *size); extern bool of_dma_is_coherent(struct device_node *np); #else /* CONFIG_OF_ADDRESS */ static inline void __iomem *of_io_request_and_map(struct device_node *device, @@ -71,14 +66,6 @@ static inline u64 of_translate_address(struct device_node *np, return OF_BAD_ADDR; } -static inline struct device_node *of_find_matching_node_by_address( - struct device_node *from, - const struct of_device_id *matches, - u64 base_address) -{ - return NULL; -} - static inline const __be32 *of_get_address(struct device_node *dev, int index, u64 *size, unsigned int *flags) { @@ -104,12 +91,6 @@ static inline struct of_pci_range *of_pci_range_parser_one( return NULL; } -static inline int of_dma_get_range(struct device_node *np, u64 *dma_addr, - u64 *paddr, u64 *size) -{ - return -ENODEV; -} - static inline bool of_dma_is_coherent(struct device_node *np) { return false; diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl index 6fcc66afb088..375c1e17562c 100755 --- a/scripts/checkpatch.pl +++ b/scripts/checkpatch.pl @@ -2826,6 +2826,14 @@ sub process { "added, moved or deleted file(s), does MAINTAINERS need updating?\n" . $herecurr); } +# Check for adding new DT bindings not in schema format + if (!$in_commit_log && + ($line =~ /^new file mode\s*\d+\s*$/) && + ($realfile =~ m@^Documentation/devicetree/bindings/.*\.txt$@)) { + WARN("DT_SCHEMA_BINDING_PATCH", + "DT bindings should be in DT schema format. See: Documentation/devicetree/writing-schema.rst\n"); + } + # Check for wrappage within a valid hunk of the file if ($realcnt != 0 && $line !~ m{^(?:\+|-| |\\ No newline|$)}) { ERROR("CORRUPTED_PATCH", |